Attachment 133296 Details for Bug 101907 – Dmesg.log (comment 10)

Dmesg.log (comment 10)

KmsPlaneMultipleDM00.log (text/plain), 1.27 MB, created by Hector Velazquez on 2017-08-07 15:10:19 UTC

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Creator: Hector Velazquez

Created: 2017-08-07 15:10:19 UTC

Size: 1.27 MB

patch

obsolete

>=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2017.08.07 09:25:34 =~=~=~=~=~=~=~=~=~=~=~=
>login as: gfx
>
>
>Distro        : Ubuntu 16.10
>Memory        : 4 GB
>Processor     : Intel(R) Core(TM) i5-3330 CPU @ 3.00GHz
>Graphic card  : Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller (rev 09) (prog-if 00 [VGA controller])
>OS-Type       : 64-bit
>Disk          : 74GiB (80GB)
>Hostname      : IVB-1
>                              ,-.             __
>                             ,'   `---.___.---'  `.
>                           ,'   ,-                 `-._
>                         ,'    /                       \
>                      ,\/     /                        \\
>                  )`._)>)     |                         \\
>                  `>,'    _   \                  /       |\
>                    )      \   |   |            |        |\\
>           .   ,   /        \  |    `.          |        | ))
>           \`. \`-'          )-|      `.        |        /((
>            \ `-`   a`     _/ ;\ _     )`-.___.--\      /  `'
>             `._         ,'    \`j`.__/        \  `.    \
>               / ,    ,'       _)\   /`        _) ( \   /
>               \__   /        /  _) (         / __\_) (
>                 `--'          /_ __\             / ___\
>
>
>
>
>gfx@10.219.106.127's password: 
>=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2017.08.07 09:36:42 =~=~=~=~=~=~=~=~=~=~=~=
>login as: gfx
>
>
>Distro        : Ubuntu 16.10
>Memory        : 4 GB
>Processor     : Intel(R) Core(TM) i5-3330 CPU @ 3.00GHz
>Graphic card  : Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller (rev 09) (prog-if 00 [VGA controller])
>OS-Type       : 64-bit
>Disk          : 74GiB (80GB)
>Hostname      : IVB-1
>                              ,-.             __
>                             ,'   `---.___.---'  `.
>                           ,'   ,-                 `-._
>                         ,'    /                       \
>                      ,\/     /                        \\
>                  )`._)>)     |                         \\
>                  `>,'    _   \                  /       |\
>                    )      \   |   |            |        |\\
>           .   ,   /        \  |    `.          |        | ))
>           \`. \`-'          )-|      `.        |        /((
>            \ `-`   a`     _/ ;\ _     )`-.___.--\      /  `'
>             `._         ,'    \`j`.__/        \  `.    \
>               / ,    ,'       _)\   /`        _) ( \   /
>               \__   /        /  _) (         / __\_) (
>                 `--'          /_ __\             / ___\
>
>
>
>
>gfx@10.219.106.127's password: 
>Welcome to Ubuntu 16.10 (GNU/Linux 4.13.0-rc4-drm-tip-ww32-commit-96c5eac+ x86_64)
>
> * Documentation:  https://help.ubuntu.com
> * Management:     https://landscape.canonical.com
> * Support:        https://ubuntu.com/advantage
>
>377 packages can be updated.
>204 updates are security updates.
>
>Your Ubuntu release is not supported anymore.
>For upgrade information, please visit:
>http://www.ubuntu.com/releaseendoflife
>
>New release '17.04' available.
>Run 'do-release-upgrade' to upgrade to it.
>
>
>#######################################################
>#                                                     #
># +-+-+-+-+-+ +-+-+-+-+-+-+-+-+ +-+-+-+ +-+-+-+-+-+   #
># |I|n|t|e|l| |G|r|a|p|h|i|c|s| |f|o|r| |L|i|n|u|x|   #
># +-+-+-+-+-+ +-+-+-+-+-+-+-+-+ +-+-+-+ +-+-+-+-+-+   #
>#                                                     #
># https://01.org/linuxgraphics                        #
># https://github.com/IntelGraphics/dev                #
># https://linuxgraphics.intel.com                     #
># Project: 01.org Intel Open Source                   #
>#                                                     #
>#                                                     #
>#######################################################
>
>
>                 .88888888:.
>                88888888.88888.
>              .8888888888888888.
>              888888888888888888
>              88' _`88'_  `88888
>              88 88 88 88  88888
>              88_88_::_88_:88888
>              88:::,::,:::::8888
>              88`:::::::::'`8888
>             .88  `::::'    8:88.
>            8888            `8:888.
>          .8888'             `888888.
>         .8888:..  .::.  ...:'8888888:.
>        .8888.'     :'     `'::`88:88888
>       .8888        '         `.888:8888.
>      888:8         .           888:88888
>    .888:88        .:           888:88888:
>    8888888.       ::           88:888888
>    `.::.888.      ::          .88888888
>   .::::::.888.    ::         :::`8888'.:.
>  ::::::::::.888   '         .::::::::::::
>  ::::::::::::.8    '      .:8::::::::::::.
> .::::::::::::::.        .:888:::::::::::::
> :::::::::::::::88:.__..:88888:::::::::::'
>  `'.:::::::::::88888888888.88:::::::::'
>        `':::_:' -- '' -'-' `':_::::'`
> 
>
>
>Last login: Mon Aug  7 09:56:45 2017 from 10.219.18.13

>(09:57 AM) [gfx@IVB-1-0XR1GT] [~]$ : login as: gfx
>
>
>Distro        : Ubuntu 16.10
>Memory        : 4 GB
>Processor     : Intel(R) Core(TM) i5-3330 CPU @ 3.00GHz
>Graphic card  : Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller (rev 09) (prog-if 00 [VGA controller])
>OS-Type       : 64-bit
>Disk          : 74GiB (80GB)
>Hostname      : IVB-1
>                              ,-.             __
>                             ,'   `---.___.---'  `.
>                           ,'   ,-                 `-._
>                         ,'    /                       \
>                      ,\/     /                        \\
>                  )`._)>)     |                         \\
>                  `>,'    _   \                  /       |\
>                    )      \   |   |            |        |\\
>           .   ,   /        \  |    `.          |        | ))
>           \`. \`-'          )-|      `.        |        /((
>            \ `-`   a`     _/ ;\ _     )`-.___.--\      /  `'
>             `._         ,'    \`j`.__/        \  `.    \
>               / ,    ,'       _)\   /`        _) ( \   /
>               \__   /        /  _) (         / __\_) (
>                 `--'          /_ __\             / ___\
>
>
>
>
>gfx@10.219.106.127's password: 
>Welcome to Ubuntu 16.10 (GNU/Linux 4.13.0-rc4-drm-tip-ww32-commit-96c5eac+ x86_64)
>
> * Documentation:  https://help.ubuntu.com
> * Management:     https://landscape.canonical.com
> * Support:        https://ubuntu.com/advantage
>
>377 packages can be updated.
>204 updates are security updates.
>
>Your Ubuntu release is not supported anymore.
>For upgrade information, please visit:
>http://www.ubuntu.com/releaseendoflife
>
>New release '17.04' available.
>Run 'do-release-upgrade' to upgrade to it.
>
>
>#######################################################
>#                                                     #
># +-+-+-+-+-+ +-+-+-+-+-+-+-+-+ +-+-+-+ +-+-+-+-+-+   #
># |I|n|t|e|l| |G|r|a|p|h|i|c|s| |f|o|r| |L|i|n|u|x|   #
># +-+-+-+-+-+ +-+-+-+-+-+-+-+-+ +-+-+-+ +-+-+-+-+-+   #
>#                                                     #
># https://01.org/linuxgraphics                        #
># https://github.com/IntelGraphics/dev                #
># https://linuxgraphics.intel.com                     #
># Project: 01.org Intel Open Source                   #
>#                                                     #
>#                                                     #
>#######################################################
>
>
>                 .88888888:.
>                88888888.88888.
>              .8888888888888888.
>              888888888888888888
>              88' _`88'_  `88888
>              88 88 88 88  88888
>              88_88_::_88_:88888
>              88:::,::,:::::8888
>              88`:::::::::'`8888
>             .88  `::::'    8:88.
>            8888            `8:888.
>          .8888'             `888888.
>         .8888:..  .::.  ...:'8888888:.
>        .8888.'     :'     `'::`88:88888
>       .8888        '         `.888:8888.
>      888:8         .           888:88888
>    .888:88        .:           888:88888:
>    8888888.       ::           88:888888
>    `.::.888.      ::          .88888888
>   .::::::.888.    ::         :::`8888'.:.
>  ::::::::::.888   '         .::::::::::::
>  ::::::::::::.8    '      .:8::::::::::::.
> .::::::::::::::.        .:888:::::::::::::
> :::::::::::::::88:.__..:88888:::::::::::'
>  `'.:::::::::::88888888888.88:::::::::'
>        `':::_:' -- '' -'-' `':_::::'`
> 
>
>
>Last login: Mon Aug  7 10:18:59 2017 from 10.219.18.13

>(10:19 AM) [gfx@IVB-1-0XR1GT] [~]$ : sudo dmesg -C[K[K[K[K[K[K[K[K[K[K[K[K[Ksudo[K[K[K[Ksudo cp[K[K[K[K[K[K[Ksudo dmesg -C
>(10:19 AM) [gfx@IVB-1-0XR1GT] [~]$ : dmesh[Kg -w
>[32m[  236.560674] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  236.560793] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  236.574775] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  236.574818] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  236.574857] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  236.574878] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  236.612461] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  236.612536] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  236.612545] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  236.612547] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  236.612550] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  236.612552] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  236.612554] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  236.612556] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  236.612558] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  236.612560] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  236.612562] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  236.612564] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  236.612566] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  236.612568] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  236.612695] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  236.612723] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  236.687406] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  236.687436] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  236.689494] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  236.689501] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  236.689504] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  236.689520] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  236.689636] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  236.689638] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  236.689640] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  236.689909] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  236.689912] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  236.689914] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  236.689917] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  236.689919] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  236.689921] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  236.689923] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  236.689925] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  236.689927] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  236.689929] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  236.689931] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  236.689933] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  236.689935] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  236.689937] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  236.689939] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  236.689941] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  236.689944] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  236.689946] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  236.689948] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  236.690583] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801fb673528
>[32m[  236.690592] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211e0d5c8 state to ffff8801fb673528
>[32m[  236.690598] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f95e2548 state to ffff8801fb673528
>[32m[  236.690601] [0m[drm:drm_atomic_check_only] checking ffff8801fb673528
>[32m[  236.690635] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  236.690638] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  236.690640] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  236.690643] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801fb673528
>[32m[  236.690650] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128e9728 state to ffff8801fb673528
>[32m[  236.690653] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801fb673528
>[32m[  236.690679] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  236.690701] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  236.690724] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  236.690745] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  236.690766] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  236.690794] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  236.690815] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  236.690836] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  236.690855] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  236.690874] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  236.690893] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  236.690895] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  236.690914] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  236.690916] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  236.690935] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  236.690953] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  236.690972] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  236.690990] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  236.691457] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  236.691477] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  236.691510] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:96, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  236.691529] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  236.691548] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  236.691573] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  236.691593] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  236.691653] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  236.691673] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  236.691683] [0m[drm:drm_atomic_commit] committing ffff8801fb673528
>[32m[  236.692212] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  236.716666] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  236.716707] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  236.716940] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  236.716960] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  236.716979] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  236.716999] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  236.717201] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  236.717235] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  236.717914] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  236.718107] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  236.718139] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  236.718161] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  236.718200] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  236.718231] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  236.718249] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  236.718272] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  236.718292] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  236.736451] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  236.736478] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  236.736518] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  236.753076] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  236.753092] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801fb673528
>[32m[  236.753123] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  236.753149] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  236.755757] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.758323] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.760907] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.763464] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.766034] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.768600] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.771162] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.773714] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.776268] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.778818] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.781371] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.783921] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.786474] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.789080] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.791632] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.794186] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.796747] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.799300] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.801850] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.804408] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.806964] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.809523] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.812106] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.814660] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.817218] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.819770] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.822332] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.824883] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.827436] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.829989] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.832577] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.835131] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  236.835144] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  236.835155] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  236.835290] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801fb673528
>[32m[  236.835298] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802128b95c8 state to ffff8801fb673528
>[32m[  236.835301] [0m[drm:drm_atomic_check_only] checking ffff8801fb673528
>[32m[  236.835304] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  236.835306] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  236.835310] [0m[drm:drm_atomic_commit] committing ffff8801fb673528
>[32m[  236.835323] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  236.835336] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801fb673528
>[32m[  236.835407] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest atomic-pipe-A-tiling-none
>[32m[  236.835669] [0m[drm:drm_mode_addfb2] [FB:97]
>[32m[  236.846198] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801fb673528
>[32m[  236.846258] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128eabf8 state to ffff8801fb673528
>[32m[  236.846271] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020f82dd28 state to ffff8801fb673528
>[32m[  236.846276] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [CRTC:36:pipe A]
>[32m[  236.846287] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8802128eabf8
>[32m[  236.846297] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128eb538 state to ffff8801fb673528
>[32m[  236.846299] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [NOCRTC]
>[32m[  236.846302] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb538
>[32m[  236.846308] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128eb098 state to ffff8801fb673528
>[32m[  236.846310] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb098 to [NOCRTC]
>[32m[  236.846312] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb098
>[32m[  236.846318] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff88020f82dd28
>[32m[  236.846324] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128ea2b8 state to ffff8801fb673528
>[32m[  236.846330] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff880211ecb7e8 state to ffff8801fb673528
>[32m[  236.846332] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [NOCRTC]
>[32m[  236.846334] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128ea2b8
>[32m[  236.846339] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  236.846363] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cd4d8 state to ffff8801fb673528
>[32m[  236.846367] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880211ecb7e8 state to ffff8801fb673528
>[32m[  236.846370] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd4d8 to [CRTC:36:pipe A]
>[32m[  236.846373] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8802111cd4d8
>[32m[  236.846381] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cf098 state to ffff8801fb673528
>[32m[  236.846383] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [NOCRTC]
>[32m[  236.846386] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf098
>[32m[  236.846389] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  236.846400] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cf098 state to ffff8801fb673528
>[32m[  236.846405] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880211ecb7e8 state to ffff8801fb673528
>[32m[  236.846407] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [CRTC:36:pipe A]
>[32m[  236.846410] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8802111cf098
>[32m[  236.846418] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cfc28 state to ffff8801fb673528
>[32m[  236.846420] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cfc28 to [NOCRTC]
>[32m[  236.846423] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cfc28
>[32m[  236.846428] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cd4d8 state to ffff8801fb673528
>[32m[  236.846430] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd4d8 to [NOCRTC]
>[32m[  236.846432] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd4d8
>[32m[  236.846436] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880211ecb7e8
>[32m[  236.846442] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cc948 state to ffff8801fb673528
>[32m[  236.846446] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff880211ec8958 state to ffff8801fb673528
>[32m[  236.846448] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [NOCRTC]
>[32m[  236.846451] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc948
>[32m[  236.846456] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cc6f8 state to ffff8801fb673528
>[32m[  236.846458] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  236.846461] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  236.846466] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cebf8 state to ffff8801fb673528
>[32m[  236.846468] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [NOCRTC]
>[32m[  236.846471] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cebf8
>[32m[  236.846474] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff880211ec8958
>[32m[  236.846480] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cdbc8 state to ffff8801fb673528
>[32m[  236.846482] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cdbc8 to [NOCRTC]
>[32m[  236.846485] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cdbc8
>[32m[  236.846490] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cf9d8 state to ffff8801fb673528
>[32m[  236.846492] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  236.846495] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  236.846500] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cc4a8 state to ffff8801fb673528
>[32m[  236.846502] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [NOCRTC]
>[32m[  236.846504] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc4a8
>[32m[  236.846508] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  236.846535] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cc4a8 state to ffff8801fb673528
>[32m[  236.846540] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ffbc138 state to ffff8801fb673528
>[32m[  236.846542] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [CRTC:36:pipe A]
>[32m[  236.846545] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8802111cc4a8
>[32m[  236.846553] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cf2e8 state to ffff8801fb673528
>[32m[  236.846555] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [NOCRTC]
>[32m[  236.846558] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf2e8
>[32m[  236.846563] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cf9d8 state to ffff8801fb673528
>[32m[  236.846565] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  236.846567] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  236.846571] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff88020ffbc138
>[32m[  236.846577] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cee48 state to ffff8801fb673528
>[32m[  236.846581] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8802144bc138 state to ffff8801fb673528
>[32m[  236.846583] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cee48 to [NOCRTC]
>[32m[  236.846586] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cee48
>[32m[  236.846591] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cdbc8 state to ffff8801fb673528
>[32m[  236.846593] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cdbc8 to [NOCRTC]
>[32m[  236.846596] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cdbc8
>[32m[  236.846601] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111ccb98 state to ffff8801fb673528
>[32m[  236.846603] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [NOCRTC]
>[32m[  236.846605] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccb98
>[32m[  236.846608] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8802144bc138
>[32m[  236.846614] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cebf8 state to ffff8801fb673528
>[32m[  236.846616] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [NOCRTC]
>[32m[  236.846618] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cebf8
>[32m[  236.846623] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cd288 state to ffff8801fb673528
>[32m[  236.846625] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [NOCRTC]
>[32m[  236.846628] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd288
>[32m[  236.846633] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cc6f8 state to ffff8801fb673528
>[32m[  236.846635] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  236.846637] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  236.846643] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff880210688958 state to ffff8801fb673528
>[32m[  236.846653] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f94661b8 state to ffff8801fb673528
>[32m[  236.846660] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801fb673528
>[32m[  236.846663] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b81d8 to [NOCRTC]
>[32m[  236.846668] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802128b8ae8 state to ffff8801fb673528
>[32m[  236.846671] [0m[drm:drm_atomic_check_only] checking ffff8801fb673528
>[32m[  236.846675] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  236.846677] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  236.846679] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  236.846686] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  236.846689] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  236.846691] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  236.846693] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  236.846695] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  236.846697] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  236.846699] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: n, active: n
>[32m[  236.846702] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801fb673528
>[32m[  236.846740] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 97
>[32m[  236.846763] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  236.846784] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb -1
>[32m[  236.846804] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  236.846814] [0m[drm:drm_atomic_commit] committing ffff8801fb673528
>[32m[  236.851516] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  236.871390] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  236.871430] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  236.871664] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  236.871684] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  236.871706] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  236.871726] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  236.871748] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:65:DP-1]
>[32m[  236.871769] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  236.871792] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  236.875570] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  236.875582] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  236.875624] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801fb673528
>[32m[  236.909417] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  236.909575] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  236.914271] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  236.925474] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801fb673528
>[32m[  236.925485] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ee51978 state to ffff8801fb673528
>[32m[  236.925491] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff8801fb673528
>[32m[  236.925494] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee51978 to [CRTC:36:pipe A]
>[32m[  236.925498] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff88020ee51978
>[32m[  236.925508] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ee529a8 state to ffff8801fb673528
>[32m[  236.925510] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee529a8 to [CRTC:36:pipe A]
>[32m[  236.925513] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff88020ee529a8
>[32m[  236.925522] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212945978 state to ffff8801fb673528
>[32m[  236.925524] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212945978 to [CRTC:36:pipe A]
>[32m[  236.925527] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff880212945978
>[32m[  236.925535] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f95e12a8
>[32m[  236.925545] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f94677a8 state to ffff8801fb673528
>[32m[  236.925551] [0m[drm:drm_atomic_check_only] checking ffff8801fb673528
>[32m[  236.925558] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  236.925561] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  236.925595] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 100
>[32m[  236.925617] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  236.925639] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 82
>[32m[  236.925659] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  236.925678] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 99
>[32m[  236.925697] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  236.925704] [0m[drm:drm_atomic_commit] committing ffff8801fb673528
>[32m[  236.942087] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  236.942108] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801fb673528
>[32m[  236.942546] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b83528
>[32m[  236.942554] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff880211b83528
>[32m[  236.942556] [0m[drm:drm_atomic_check_only] checking ffff880211b83528
>[32m[  236.942559] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  236.942561] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  236.942564] [0m[drm:drm_atomic_commit] committing ffff880211b83528
>[32m[  236.942577] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b83528
>[32m[  236.942590] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b83528
>[32m[  236.942641] [0m[drm:drm_mode_addfb2] [FB:98]
>[32m[  236.949049] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f53db528
>[32m[  236.949061] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95304a8 state to ffff8801f53db528
>[32m[  236.949068] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880210694a88 state to ffff8801f53db528
>[32m[  236.949071] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [CRTC:36:pipe A]
>[32m[  236.949075] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:98] for plane state ffff8801f95304a8
>[32m[  236.949085] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9531728 state to ffff8801f53db528
>[32m[  236.949087] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [NOCRTC]
>[32m[  236.949090] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531728
>[32m[  236.949098] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f95339d8 state to ffff8801f53db528
>[32m[  236.949100] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  236.949103] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  236.949111] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880210694a88
>[32m[  236.949121] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f94661b8 state to ffff8801f53db528
>[32m[  236.949124] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f94661b8 to [NOCRTC]
>[32m[  236.949130] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b95c8 state to ffff8801f53db528
>[32m[  236.949133] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b95c8 to [CRTC:36:pipe A]
>[32m[  236.949135] [0m[drm:drm_atomic_check_only] checking ffff8801f53db528
>[32m[  236.949139] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  236.949144] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  236.949146] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  236.949148] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  236.949151] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:36:pipe A]
>[32m[  236.949153] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  236.949156] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f53db528
>[32m[  236.949161] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f53db528
>[32m[  236.949193] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  236.949216] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  236.949239] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  236.949259] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  236.949281] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  236.949301] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  236.949322] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  236.949342] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  236.949362] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  236.949381] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  236.949400] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  236.949403] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  236.949421] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  236.949424] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  236.949443] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  236.949461] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  236.949479] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  236.949497] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  236.949517] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  236.949535] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  236.949554] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  236.949573] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:82, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  236.949591] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:99, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  236.949616] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 98
>[32m[  236.949636] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  236.949655] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  236.949674] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  236.949693] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  236.949712] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  236.949750] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  236.949769] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  236.949774] [0m[drm:drm_atomic_commit] committing ffff8801f53db528
>[32m[  236.953077] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  236.975634] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  236.975662] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  236.975896] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  236.975919] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  236.975938] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  236.975958] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  236.975979] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  236.976003] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  236.976310] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  236.976979] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  236.977297] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  236.977344] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  236.977365] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  236.977391] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  236.977411] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  236.977429] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  236.977452] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  236.977479] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  237.012301] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  237.012333] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  237.012373] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.012386] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f53db528
>[32m[  237.012404] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f53db528
>[32m[  237.045808] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b83528
>[32m[  237.045817] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff880211b83528
>[32m[  237.045822] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ec9c138 state to ffff880211b83528
>[32m[  237.045825] [0m[drm:drm_atomic_check_only] checking ffff880211b83528
>[32m[  237.045830] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.045833] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  237.045838] [0m[drm:drm_atomic_commit] committing ffff880211b83528
>[32m[  237.062267] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b83528
>[32m[  237.062280] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b83528
>[32m[  237.062553] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  237.062695] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  237.067124] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  237.079063] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  237.079073] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9533788 state to ffff880212a68008
>[32m[  237.079079] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff880212a68008
>[32m[  237.079082] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [CRTC:36:pipe A]
>[32m[  237.079086] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801f9533788
>[32m[  237.079096] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95332e8 state to ffff880212a68008
>[32m[  237.079098] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [CRTC:36:pipe A]
>[32m[  237.079101] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8801f95332e8
>[32m[  237.079109] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9533c28 state to ffff880212a68008
>[32m[  237.079112] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533c28 to [CRTC:36:pipe A]
>[32m[  237.079114] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801f9533c28
>[32m[  237.079122] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f95e12a8
>[32m[  237.079132] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff880212a68008
>[32m[  237.079137] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  237.079143] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.079145] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  237.079179] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 109
>[32m[  237.079202] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  237.079224] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 102
>[32m[  237.079244] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  237.079264] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 108
>[32m[  237.079284] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  237.079290] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  237.095613] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  237.095636] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  237.095832] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  237.095839] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b83a8 state to ffff880212118008
>[32m[  237.095845] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9692548 state to ffff880212118008
>[32m[  237.095847] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  237.095852] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.095854] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  237.095859] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  237.112261] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  237.112272] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  237.112528] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  237.119088] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b83528
>[32m[  237.119098] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020e07b788 state to ffff880211b83528
>[32m[  237.119104] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9694a88 state to ffff880211b83528
>[32m[  237.119107] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b788 to [CRTC:36:pipe A]
>[32m[  237.119110] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:104] for plane state ffff88020e07b788
>[32m[  237.119120] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e078de8 state to ffff880211b83528
>[32m[  237.119122] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078de8 to [NOCRTC]
>[32m[  237.119125] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078de8
>[32m[  237.119133] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e07a9a8 state to ffff880211b83528
>[32m[  237.119135] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [NOCRTC]
>[32m[  237.119138] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a9a8
>[32m[  237.119146] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9694a88
>[32m[  237.119155] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9467448 state to ffff880211b83528
>[32m[  237.119158] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467448 to [CRTC:36:pipe A]
>[32m[  237.119164] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff880211b83528
>[32m[  237.119166] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b81d8 to [NOCRTC]
>[32m[  237.119168] [0m[drm:drm_atomic_check_only] checking ffff880211b83528
>[32m[  237.119172] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  237.119177] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  237.119180] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  237.119182] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.119184] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  237.119186] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  237.119189] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880211b83528
>[32m[  237.119193] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880211b83528
>[32m[  237.119225] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  237.119248] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  237.119269] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  237.119289] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  237.119310] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  237.119330] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  237.119350] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  237.119369] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  237.119388] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  237.119390] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  237.119409] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  237.119411] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  237.119430] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  237.119449] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  237.119467] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  237.119485] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  237.119506] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  237.119524] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  237.119543] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  237.119561] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:102, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  237.119579] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:108, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  237.119603] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 104
>[32m[  237.119622] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  237.119642] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  237.119661] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.119680] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  237.119699] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.119737] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  237.119756] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  237.119761] [0m[drm:drm_atomic_commit] committing ffff880211b83528
>[32m[  237.123063] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  237.147765] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  237.147793] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  237.148116] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  237.148147] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  237.148170] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  237.148191] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  237.148213] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.148245] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  237.148276] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  237.148891] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  237.149154] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  237.149185] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  237.149207] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  237.149234] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  237.149255] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  237.149294] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  237.149319] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  237.149340] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  237.184081] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  237.184113] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  237.184152] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.184165] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b83528
>[32m[  237.184182] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b83528
>[32m[  237.217697] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  237.217881] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  237.222497] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  237.233987] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b83528
>[32m[  237.234016] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212c008 state to ffff880211b83528
>[32m[  237.234022] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802106c6678 state to ffff880211b83528
>[32m[  237.234025] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [CRTC:36:pipe A]
>[32m[  237.234029] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff88021212c008
>[32m[  237.234038] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212d978 state to ffff880211b83528
>[32m[  237.234041] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [CRTC:36:pipe A]
>[32m[  237.234044] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88021212d978
>[32m[  237.234061] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212ebf8 state to ffff880211b83528
>[32m[  237.234063] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [CRTC:36:pipe A]
>[32m[  237.234066] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88021212ebf8
>[32m[  237.234073] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8802106c6678
>[32m[  237.234083] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f94666c8 state to ffff880211b83528
>[32m[  237.234088] [0m[drm:drm_atomic_check_only] checking ffff880211b83528
>[32m[  237.234094] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  237.234097] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  237.234129] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 113
>[32m[  237.234152] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  237.234174] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 110
>[32m[  237.234194] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  237.234215] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 112
>[32m[  237.234234] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  237.234240] [0m[drm:drm_atomic_commit] committing ffff880211b83528
>[32m[  237.250555] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b83528
>[32m[  237.250578] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b83528
>[32m[  237.250955] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  237.250963] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b95c8 state to ffff880212118008
>[32m[  237.250965] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  237.250968] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.250970] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  237.250973] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  237.250985] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  237.251200] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  237.251253] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  237.257186] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f53db528
>[32m[  237.257196] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2e9a8 state to ffff8801f53db528
>[32m[  237.257202] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff8801f53db528
>[32m[  237.257205] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [CRTC:36:pipe A]
>[32m[  237.257209] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff88020ec2e9a8
>[32m[  237.257218] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2f098 state to ffff8801f53db528
>[32m[  237.257221] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f098 to [NOCRTC]
>[32m[  237.257223] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f098
>[32m[  237.257231] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2c008 state to ffff8801f53db528
>[32m[  237.257234] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  237.257236] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  237.257243] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f95e12a8
>[32m[  237.257248] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f53db528
>[32m[  237.257262] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2c008 state to ffff8801f53db528
>[32m[  237.257266] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff8801f53db528
>[32m[  237.257269] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [CRTC:36:pipe A]
>[32m[  237.257272] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff88020ec2c008
>[32m[  237.257279] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2dbc8 state to ffff8801f53db528
>[32m[  237.257282] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  237.257284] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  237.257290] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f53db528
>[32m[  237.257301] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2dbc8 state to ffff8801f53db528
>[32m[  237.257306] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff8801f53db528
>[32m[  237.257308] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [CRTC:36:pipe A]
>[32m[  237.257311] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff88020ec2dbc8
>[32m[  237.257319] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2c4a8 state to ffff8801f53db528
>[32m[  237.257321] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [NOCRTC]
>[32m[  237.257323] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c4a8
>[32m[  237.257331] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2c008 state to ffff8801f53db528
>[32m[  237.257333] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  237.257335] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  237.257342] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f95e12a8
>[32m[  237.257350] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9467448 state to ffff8801f53db528
>[32m[  237.257352] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467448 to [NOCRTC]
>[32m[  237.257358] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b83a8 state to ffff8801f53db528
>[32m[  237.257360] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b83a8 to [CRTC:36:pipe A]
>[32m[  237.257363] [0m[drm:drm_atomic_check_only] checking ffff8801f53db528
>[32m[  237.257366] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  237.257370] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  237.257372] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  237.257374] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.257377] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:36:pipe A]
>[32m[  237.257379] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  237.257382] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f53db528
>[32m[  237.257386] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f53db528
>[32m[  237.257417] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  237.257439] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  237.257463] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  237.257483] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  237.257504] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  237.257524] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  237.257544] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  237.257565] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  237.257584] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  237.257603] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  237.257622] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  237.257625] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  237.257643] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  237.257646] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  237.257664] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  237.257683] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  237.257701] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  237.257719] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  237.257739] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  237.257757] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  237.257776] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:113, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  237.257795] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:110, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  237.257813] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:112, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  237.257837] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 111
>[32m[  237.257857] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  237.257876] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  237.257896] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.257915] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  237.257933] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.257971] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  237.257990] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  237.259089] [0m[drm:drm_atomic_commit] committing ffff8801f53db528
>[32m[  237.261345] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  237.285694] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  237.285722] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  237.285955] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  237.285978] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  237.285997] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  237.286186] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  237.286219] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.286243] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  237.286283] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  237.286936] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  237.287188] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  237.287220] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  237.287241] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  237.287268] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  237.287288] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  237.287307] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  237.287331] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  237.287351] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  237.322170] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  237.322201] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  237.322241] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.322253] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f53db528
>[32m[  237.322271] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f53db528
>[32m[  237.355677] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b83528
>[32m[  237.355686] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff880211b83528
>[32m[  237.355691] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880211ec8958 state to ffff880211b83528
>[32m[  237.355693] [0m[drm:drm_atomic_check_only] checking ffff880211b83528
>[32m[  237.355698] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.355701] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  237.355706] [0m[drm:drm_atomic_commit] committing ffff880211b83528
>[32m[  237.372149] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b83528
>[32m[  237.372160] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b83528
>[32m[  237.372418] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  237.372558] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  237.376711] [0m[drm:drm_mode_addfb2] [FB:117]
>[32m[  237.388865] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801fb673528
>[32m[  237.388875] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cc6f8 state to ffff8801fb673528
>[32m[  237.388880] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e5d28 state to ffff8801fb673528
>[32m[  237.388883] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc6f8 to [CRTC:36:pipe A]
>[32m[  237.388887] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5cc6f8
>[32m[  237.388897] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ce2b8 state to ffff8801fb673528
>[32m[  237.388899] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce2b8 to [CRTC:36:pipe A]
>[32m[  237.388902] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801fb5ce2b8
>[32m[  237.388911] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cf2e8 state to ffff8801fb673528
>[32m[  237.388913] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf2e8 to [CRTC:36:pipe A]
>[32m[  237.388916] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801fb5cf2e8
>[32m[  237.388923] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f95e5d28
>[32m[  237.388932] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b95c8 state to ffff8801fb673528
>[32m[  237.388936] [0m[drm:drm_atomic_check_only] checking ffff8801fb673528
>[32m[  237.388942] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.388944] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  237.388976] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 117
>[32m[  237.388998] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  237.389351] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 114
>[32m[  237.389373] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  237.389402] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 116
>[32m[  237.389421] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  237.389427] [0m[drm:drm_atomic_commit] committing ffff8801fb673528
>[32m[  237.405481] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  237.405505] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801fb673528
>[32m[  237.405734] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f53db528
>[32m[  237.405742] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b9b38 state to ffff8801f53db528
>[32m[  237.405747] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ec9c138 state to ffff8801f53db528
>[32m[  237.405750] [0m[drm:drm_atomic_check_only] checking ffff8801f53db528
>[32m[  237.405754] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.405757] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  237.405761] [0m[drm:drm_atomic_commit] committing ffff8801f53db528
>[32m[  237.422134] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f53db528
>[32m[  237.422146] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f53db528
>[32m[  237.422298] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  237.432482] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  237.432505] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cdbc8 state to ffff880212a68008
>[32m[  237.432513] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9692e98 state to ffff880212a68008
>[32m[  237.432517] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ce508 state to ffff880212a68008
>[32m[  237.432519] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [NOCRTC]
>[32m[  237.432520] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce508
>[32m[  237.432525] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cd728 state to ffff880212a68008
>[32m[  237.432526] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [NOCRTC]
>[32m[  237.432528] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd728
>[32m[  237.432532] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cfc28 state to ffff880212a68008
>[32m[  237.432536] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cd288 state to ffff880212a68008
>[32m[  237.432538] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd288 to [NOCRTC]
>[32m[  237.432539] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd288
>[32m[  237.432544] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802121314d8 state to ffff880212a68008
>[32m[  237.432545] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [NOCRTC]
>[32m[  237.432547] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121314d8
>[32m[  237.432551] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff880212131038 state to ffff880212a68008
>[32m[  237.432554] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff880212131288 state to ffff880212a68008
>[32m[  237.432556] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [NOCRTC]
>[32m[  237.432557] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131288
>[32m[  237.432561] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802121329a8 state to ffff880212a68008
>[32m[  237.432563] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [NOCRTC]
>[32m[  237.432564] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121329a8
>[32m[  237.432575] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9692e98
>[32m[  237.432577] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [CRTC:36:pipe A]
>[32m[  237.432579] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801fb5cdbc8
>[32m[  237.432582] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212a68008
>[32m[  237.432595] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff880212a68008
>[32m[  237.432600] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048918 to [NOCRTC]
>[32m[  237.432604] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9467cb8 state to ffff880212a68008
>[32m[  237.432606] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467cb8 to [CRTC:36:pipe A]
>[32m[  237.432611] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9692548 state to ffff880212a68008
>[32m[  237.432616] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f9692548
>[32m[  237.432618] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [CRTC:46:pipe B]
>[32m[  237.432620] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801fb5cfc28
>[32m[  237.432622] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212a68008
>[32m[  237.432625] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048918 to [CRTC:46:pipe B]
>[32m[  237.432629] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9696678 state to ffff880212a68008
>[32m[  237.432631] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9696678
>[32m[  237.432633] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [NOCRTC]
>[32m[  237.432634] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131038
>[32m[  237.432637] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880212a68008
>[32m[  237.432639] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  237.432642] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  237.432644] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  237.432645] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  237.432647] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  237.432651] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  237.432653] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  237.432654] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.432657] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  237.432658] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  237.432660] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212a68008
>[32m[  237.432664] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  237.432665] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212a68008
>[32m[  237.432669] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212a68008
>[32m[  237.432699] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  237.432720] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  237.432741] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  237.432761] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  237.432782] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  237.432801] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  237.432821] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  237.432840] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  237.432858] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  237.432861] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  237.432879] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  237.432881] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  237.432900] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  237.432918] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  237.432936] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  237.432954] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  237.432974] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  237.432992] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  237.433034] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:117, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  237.433061] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:114, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  237.433079] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:116, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  237.433081] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212a68008
>[32m[  237.433102] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  237.433121] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  237.433142] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  237.433161] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  237.433180] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  237.433198] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  237.433216] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  237.433234] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  237.433251] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  237.433268] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  237.433285] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  237.433287] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  237.433303] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  237.433305] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  237.433323] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  237.433339] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  237.433356] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  237.433373] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  237.433392] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  237.433409] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  237.433426] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0
>[32m[  237.433443] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  237.433459] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  237.433483] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  237.433502] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  237.433521] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  237.433539] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.433558] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  237.433576] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.433594] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  237.433612] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  237.433650] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  237.433669] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  237.433705] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  237.433724] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  237.433731] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  237.434087] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  237.456669] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  237.456705] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  237.456941] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  237.456961] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  237.456979] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  237.456999] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.457046] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  237.457087] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  237.457723] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  237.457905] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  237.457934] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  237.457953] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  237.457978] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  237.457997] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  237.458023] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  237.458046] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  237.458065] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  237.476184] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  237.476849] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  237.477035] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  237.477075] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  237.477095] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  237.477121] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  237.477141] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  237.477158] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  237.477181] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  237.477200] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  237.512040] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  237.512074] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  237.512114] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.512144] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  237.512166] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  237.512203] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  237.512219] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  237.512262] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  237.516337] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  237.524275] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  237.524304] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ffdc948 state to ffff880211b85fa8
>[32m[  237.524312] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  237.524323] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ffdc948 state to ffff880211b85fa8
>[32m[  237.524328] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802144bc138 state to ffff880211b85fa8
>[32m[  237.524333] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ffdf2e8 state to ffff880211b85fa8
>[32m[  237.524335] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdf2e8 to [NOCRTC]
>[32m[  237.524337] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdf2e8
>[32m[  237.524342] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ffdee48 state to ffff880211b85fa8
>[32m[  237.524344] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdee48 to [NOCRTC]
>[32m[  237.524346] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdee48
>[32m[  237.524348] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  237.524363] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128e8258 state to ffff880211b85fa8
>[32m[  237.524368] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880210688958 state to ffff880211b85fa8
>[32m[  237.524372] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128eabf8 state to ffff880211b85fa8
>[32m[  237.524374] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [NOCRTC]
>[32m[  237.524376] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eabf8
>[32m[  237.524381] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128e86f8 state to ffff880211b85fa8
>[32m[  237.524383] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [NOCRTC]
>[32m[  237.524385] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e86f8
>[32m[  237.524389] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128eb538 state to ffff880211b85fa8
>[32m[  237.524394] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8802144bc138 state to ffff880211b85fa8
>[32m[  237.524398] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128e9978 state to ffff880211b85fa8
>[32m[  237.524400] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [NOCRTC]
>[32m[  237.524402] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9978
>[32m[  237.524406] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128eb098 state to ffff880211b85fa8
>[32m[  237.524408] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb098 to [NOCRTC]
>[32m[  237.524410] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb098
>[32m[  237.524415] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128e9728 state to ffff880211b85fa8
>[32m[  237.524419] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128ea2b8 state to ffff880211b85fa8
>[32m[  237.524421] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [NOCRTC]
>[32m[  237.524423] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128ea2b8
>[32m[  237.524428] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cf098 state to ffff880211b85fa8
>[32m[  237.524430] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [NOCRTC]
>[32m[  237.524432] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf098
>[32m[  237.524443] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880210688958
>[32m[  237.524446] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e8258 to [CRTC:36:pipe A]
>[32m[  237.524448] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802128e8258
>[32m[  237.524451] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  237.524481] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cf098 state to ffff880211b85fa8
>[32m[  237.524485] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880210688958 state to ffff880211b85fa8
>[32m[  237.524490] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cd4d8 state to ffff880211b85fa8
>[32m[  237.524492] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd4d8 to [NOCRTC]
>[32m[  237.524494] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd4d8
>[32m[  237.524498] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cc4a8 state to ffff880211b85fa8
>[32m[  237.524500] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [NOCRTC]
>[32m[  237.524502] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc4a8
>[32m[  237.524507] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cc6f8 state to ffff880211b85fa8
>[32m[  237.524511] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8802144bc138 state to ffff880211b85fa8
>[32m[  237.524516] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cf2e8 state to ffff880211b85fa8
>[32m[  237.524518] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [NOCRTC]
>[32m[  237.524520] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf2e8
>[32m[  237.524524] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cd288 state to ffff880211b85fa8
>[32m[  237.524526] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [NOCRTC]
>[32m[  237.524528] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd288
>[32m[  237.524532] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cf9d8 state to ffff880211b85fa8
>[32m[  237.524536] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cebf8 state to ffff880211b85fa8
>[32m[  237.524538] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [NOCRTC]
>[32m[  237.524540] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cebf8
>[32m[  237.524545] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cc948 state to ffff880211b85fa8
>[32m[  237.524547] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [NOCRTC]
>[32m[  237.524549] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc948
>[32m[  237.524554] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880210688958
>[32m[  237.524556] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [CRTC:36:pipe A]
>[32m[  237.524558] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802111cf098
>[32m[  237.524561] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880211b85fa8
>[32m[  237.524575] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9467958 state to ffff880211b85fa8
>[32m[  237.524584] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467958 to [NOCRTC]
>[32m[  237.524586] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467958 to [CRTC:36:pipe A]
>[32m[  237.524592] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8802144bc138
>[32m[  237.524594] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [CRTC:46:pipe B]
>[32m[  237.524596] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802111cc6f8
>[32m[  237.524599] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880211b85fa8
>[32m[  237.524605] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0495c8 state to ffff880211b85fa8
>[32m[  237.524607] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0495c8 to [NOCRTC]
>[32m[  237.524610] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0495c8 to [CRTC:46:pipe B]
>[32m[  237.524621] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1218008 state to ffff880211b85fa8
>[32m[  237.524624] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f1218008
>[32m[  237.524626] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  237.524628] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  237.524630] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  237.524633] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  237.524640] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  237.524642] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  237.524644] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.524647] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  237.524678] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  237.524700] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  237.524722] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  237.524743] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  237.524752] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  237.542662] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  237.542713] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  237.579890] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  237.580092] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  237.601106] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  237.601141] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  237.601168] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  237.601189] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  237.639547] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  237.639622] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  237.639626] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  237.639628] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  237.639630] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  237.639632] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  237.639634] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  237.639636] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  237.639638] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  237.639640] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  237.639643] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  237.639645] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  237.639647] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  237.639649] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  237.639765] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  237.639795] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  237.714876] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  237.714899] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  237.716957] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  237.716963] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  237.716967] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  237.716982] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  237.717338] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  237.717341] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  237.717343] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  237.717482] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  237.717486] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  237.717488] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  237.717491] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  237.717493] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  237.717495] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  237.717497] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  237.717499] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  237.717501] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  237.717503] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  237.717505] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  237.717507] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  237.717509] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  237.717511] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  237.717513] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  237.717515] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  237.717517] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  237.717519] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  237.717521] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  237.717658] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  237.717666] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135aa918 state to ffff880212118008
>[32m[  237.717671] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121d3d8 state to ffff880212118008
>[32m[  237.717674] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  237.717680] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.717683] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  237.717689] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  237.728649] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  237.728663] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  237.728689] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  237.728714] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  237.731293] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.733850] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.736407] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.738961] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.741523] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.744063] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.746597] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.749126] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.751654] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.754181] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.756715] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.759242] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.761769] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.764295] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.766818] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.769345] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.771871] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.774397] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.776923] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.779450] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.781979] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.784570] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.787101] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.789629] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.792155] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.794680] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.797208] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.799736] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.802262] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.804787] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.807312] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.809838] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  237.809845] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  237.809849] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  237.810138] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801fb673528
>[32m[  237.810146] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802135ab3f8 state to ffff8801fb673528
>[32m[  237.810149] [0m[drm:drm_atomic_check_only] checking ffff8801fb673528
>[32m[  237.810152] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  237.810155] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  237.810158] [0m[drm:drm_atomic_commit] committing ffff8801fb673528
>[32m[  237.810172] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801fb673528
>[32m[  237.810185] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801fb673528
>[32m[  237.810283] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest atomic-pipe-A-tiling-x
>[32m[  237.810559] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  237.817408] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  237.817418] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212fc28 state to ffff880212118008
>[32m[  237.817424] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1219bf8 state to ffff880212118008
>[32m[  237.817428] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [CRTC:36:pipe A]
>[32m[  237.817431] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff88021212fc28
>[32m[  237.817441] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212c008 state to ffff880212118008
>[32m[  237.817444] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [NOCRTC]
>[32m[  237.817446] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c008
>[32m[  237.817452] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212e9a8 state to ffff880212118008
>[32m[  237.817454] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [NOCRTC]
>[32m[  237.817456] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212e9a8
>[32m[  237.817461] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1219bf8
>[32m[  237.817467] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212c6f8 state to ffff880212118008
>[32m[  237.817472] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121c138 state to ffff880212118008
>[32m[  237.817474] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  237.817477] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  237.817482] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212c4a8 state to ffff880212118008
>[32m[  237.817484] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [NOCRTC]
>[32m[  237.817486] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c4a8
>[32m[  237.817492] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212de18 state to ffff880212118008
>[32m[  237.817494] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  237.817496] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  237.817500] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f121c138
>[32m[  237.817507] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2cb98 state to ffff880212118008
>[32m[  237.817509] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [NOCRTC]
>[32m[  237.817511] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cb98
>[32m[  237.817517] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2dbc8 state to ffff880212118008
>[32m[  237.817519] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  237.817521] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  237.817527] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2e758 state to ffff880212118008
>[32m[  237.817529] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  237.817531] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  237.817535] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  237.817564] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2e758 state to ffff880212118008
>[32m[  237.817568] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121c138 state to ffff880212118008
>[32m[  237.817571] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [CRTC:36:pipe A]
>[32m[  237.817574] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff88020ec2e758
>[32m[  237.817582] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2e2b8 state to ffff880212118008
>[32m[  237.817584] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [NOCRTC]
>[32m[  237.817586] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e2b8
>[32m[  237.817590] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  237.817601] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2e2b8 state to ffff880212118008
>[32m[  237.817606] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121c138 state to ffff880212118008
>[32m[  237.817608] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [CRTC:36:pipe A]
>[32m[  237.817611] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff88020ec2e2b8
>[32m[  237.817619] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2e508 state to ffff880212118008
>[32m[  237.817621] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e508 to [NOCRTC]
>[32m[  237.817623] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e508
>[32m[  237.817628] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2e758 state to ffff880212118008
>[32m[  237.817630] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  237.817633] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  237.817636] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121c138
>[32m[  237.817642] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2f538 state to ffff880212118008
>[32m[  237.817646] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1219bf8 state to ffff880212118008
>[32m[  237.817649] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [NOCRTC]
>[32m[  237.817651] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f538
>[32m[  237.817656] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2dbc8 state to ffff880212118008
>[32m[  237.817658] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  237.817661] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  237.817666] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2cde8 state to ffff880212118008
>[32m[  237.817668] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  237.817670] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  237.817673] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f1219bf8
>[32m[  237.817679] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2cb98 state to ffff880212118008
>[32m[  237.817681] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [NOCRTC]
>[32m[  237.817683] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cb98
>[32m[  237.817688] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2d288 state to ffff880212118008
>[32m[  237.817690] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d288 to [NOCRTC]
>[32m[  237.817693] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d288
>[32m[  237.817698] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2c4a8 state to ffff880212118008
>[32m[  237.817700] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [NOCRTC]
>[32m[  237.817702] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c4a8
>[32m[  237.817706] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  237.817730] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2c4a8 state to ffff880212118008
>[32m[  237.817735] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1219bf8 state to ffff880212118008
>[32m[  237.817737] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [CRTC:36:pipe A]
>[32m[  237.817740] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff88020ec2c4a8
>[32m[  237.817748] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2c008 state to ffff880212118008
>[32m[  237.817750] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  237.817753] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  237.817758] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2d288 state to ffff880212118008
>[32m[  237.817760] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d288 to [NOCRTC]
>[32m[  237.817762] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d288
>[32m[  237.817766] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1219bf8
>[32m[  237.817771] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2f098 state to ffff880212118008
>[32m[  237.817776] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121ca88 state to ffff880212118008
>[32m[  237.817778] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f098 to [NOCRTC]
>[32m[  237.817780] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f098
>[32m[  237.817785] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2cb98 state to ffff880212118008
>[32m[  237.817788] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [NOCRTC]
>[32m[  237.817790] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cb98
>[32m[  237.817795] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2d038 state to ffff880212118008
>[32m[  237.817797] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  237.817800] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  237.817803] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f121ca88
>[32m[  237.817808] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2cde8 state to ffff880212118008
>[32m[  237.817810] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  237.817813] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  237.817817] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2ee48 state to ffff880212118008
>[32m[  237.817820] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2ee48 to [NOCRTC]
>[32m[  237.817822] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2ee48
>[32m[  237.817827] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2dbc8 state to ffff880212118008
>[32m[  237.817829] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  237.817831] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  237.817837] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f121c138 state to ffff880212118008
>[32m[  237.817845] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd660f38 state to ffff880212118008
>[32m[  237.817851] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135aaae8 state to ffff880212118008
>[32m[  237.817853] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135aaae8 to [NOCRTC]
>[32m[  237.817858] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802135aa748 state to ffff880212118008
>[32m[  237.817861] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  237.817864] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  237.817866] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  237.817868] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  237.817872] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  237.817875] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  237.817877] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.817879] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  237.817881] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  237.817883] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  237.817885] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: n, active: n
>[32m[  237.817888] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212118008
>[32m[  237.817924] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 66
>[32m[  237.817946] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  237.817967] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb -1
>[32m[  237.817987] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.819748] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  237.822303] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  237.847043] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  237.847083] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  237.847315] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  237.847335] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  237.847357] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  237.847377] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  237.847399] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:65:DP-1]
>[32m[  237.847421] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.847444] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  237.858608] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  237.858621] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  237.858662] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  237.892296] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  237.892446] [0m[drm:drm_mode_addfb2] [FB:97]
>[32m[  237.896977] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  237.908519] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  237.908528] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2e508 state to ffff8801f12574e8
>[32m[  237.908535] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880211ec8958 state to ffff8801f12574e8
>[32m[  237.908538] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e508 to [CRTC:36:pipe A]
>[32m[  237.908541] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff88020ec2e508
>[32m[  237.908552] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ce9a8 state to ffff8801f12574e8
>[32m[  237.908555] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce9a8 to [CRTC:36:pipe A]
>[32m[  237.908558] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff8801fb5ce9a8
>[32m[  237.908566] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cc6f8 state to ffff8801f12574e8
>[32m[  237.908569] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc6f8 to [CRTC:36:pipe A]
>[32m[  237.908572] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8801fb5cc6f8
>[32m[  237.908579] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880211ec8958
>[32m[  237.908588] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd661298 state to ffff8801f12574e8
>[32m[  237.908593] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  237.908599] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  237.908602] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  237.908634] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 100
>[32m[  237.908656] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  237.908678] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 82
>[32m[  237.908698] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  237.908718] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 97
>[32m[  237.908738] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  237.908743] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  237.925085] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  237.925107] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  237.925506] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  237.925514] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211c5fd08 state to ffff8801f12574e8
>[32m[  237.925516] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  237.925519] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.925521] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  237.925524] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  237.925536] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  237.925550] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  237.925598] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  237.931656] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  237.931666] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5ce758 state to ffff8801f12574e8
>[32m[  237.931672] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e5d28 state to ffff8801f12574e8
>[32m[  237.931675] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [CRTC:36:pipe A]
>[32m[  237.931678] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8801fb5ce758
>[32m[  237.931688] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cd978 state to ffff8801f12574e8
>[32m[  237.931690] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd978 to [NOCRTC]
>[32m[  237.931692] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd978
>[32m[  237.931701] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cf9d8 state to ffff8801f12574e8
>[32m[  237.931703] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf9d8 to [NOCRTC]
>[32m[  237.931705] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf9d8
>[32m[  237.931712] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f95e5d28
>[32m[  237.931721] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd660f38 state to ffff8801f12574e8
>[32m[  237.931723] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd660f38 to [NOCRTC]
>[32m[  237.931730] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135becb8 state to ffff8801f12574e8
>[32m[  237.931732] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135becb8 to [CRTC:36:pipe A]
>[32m[  237.931734] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  237.931738] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  237.931742] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  237.931744] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  237.931746] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  237.931749] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:36:pipe A]
>[32m[  237.931751] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  237.931754] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  237.931758] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  237.931789] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  237.931811] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  237.931835] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  237.931855] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  237.931876] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  237.931896] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  237.931917] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  237.931937] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  237.931956] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  237.931975] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  237.931994] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  237.932559] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  237.932580] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  237.932583] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  237.932603] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  237.932631] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  237.932649] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  237.932676] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  237.932698] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  237.932716] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  237.932744] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  237.932763] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:82, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  237.932781] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:97, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  237.932806] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 99
>[32m[  237.932825] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  237.932845] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  237.932873] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.932893] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  237.932920] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  237.932958] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  237.932978] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  237.932983] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  237.935585] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  237.959692] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  237.959721] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  237.959953] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  237.959977] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  237.959996] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  237.960168] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  237.960192] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.960217] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  237.960266] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  237.960919] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  237.961135] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  237.961166] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  237.961188] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  237.961215] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  237.961244] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  237.961263] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  237.961287] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  237.961307] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  237.996123] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  237.996155] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  237.996193] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  237.996206] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  237.996226] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.029612] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.029621] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f978ccb8 state to ffff8801f12574e8
>[32m[  238.029626] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1218958 state to ffff8801f12574e8
>[32m[  238.029629] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.029633] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.029636] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  238.029641] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.046102] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.046116] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.046373] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  238.046513] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  238.050825] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  238.062866] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.062875] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cd728 state to ffff8801f12574e8
>[32m[  238.062881] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121d3d8 state to ffff8801f12574e8
>[32m[  238.062884] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [CRTC:36:pipe A]
>[32m[  238.062887] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801fb5cd728
>[32m[  238.062896] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ccb98 state to ffff8801f12574e8
>[32m[  238.062899] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ccb98 to [CRTC:36:pipe A]
>[32m[  238.062902] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8801fb5ccb98
>[32m[  238.062910] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5ce508 state to ffff8801f12574e8
>[32m[  238.062912] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [CRTC:36:pipe A]
>[32m[  238.062915] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801fb5ce508
>[32m[  238.062922] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121d3d8
>[32m[  238.062931] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211e0d3f8 state to ffff8801f12574e8
>[32m[  238.062936] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.062941] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.062944] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  238.062975] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 109
>[32m[  238.062997] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  238.063459] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 102
>[32m[  238.063480] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  238.063502] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 108
>[32m[  238.063543] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  238.063549] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.079434] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.079457] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.079663] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.079671] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211e0d5c8 state to ffff8801f12574e8
>[32m[  238.079676] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1218958 state to ffff8801f12574e8
>[32m[  238.079679] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.079684] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.079686] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  238.079691] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.096086] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.096098] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.096356] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  238.102852] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.102861] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ffdee48 state to ffff8801f12574e8
>[32m[  238.102867] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121d3d8 state to ffff8801f12574e8
>[32m[  238.102870] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdee48 to [CRTC:36:pipe A]
>[32m[  238.102873] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:104] for plane state ffff88020ffdee48
>[32m[  238.102882] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ffdc948 state to ffff8801f12574e8
>[32m[  238.102884] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdc948 to [NOCRTC]
>[32m[  238.102887] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdc948
>[32m[  238.102895] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ffdf2e8 state to ffff8801f12574e8
>[32m[  238.102897] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdf2e8 to [NOCRTC]
>[32m[  238.102900] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdf2e8
>[32m[  238.102907] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121d3d8
>[32m[  238.102915] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd661298 state to ffff8801f12574e8
>[32m[  238.102917] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd661298 to [CRTC:36:pipe A]
>[32m[  238.102923] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8ae8 state to ffff8801f12574e8
>[32m[  238.102926] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8ae8 to [NOCRTC]
>[32m[  238.102928] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.102931] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  238.102935] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  238.102938] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  238.102940] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.102942] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  238.102944] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  238.102946] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  238.102951] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  238.102979] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  238.103001] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  238.103580] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  238.103623] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  238.103644] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  238.103665] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  238.103685] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  238.103704] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  238.103722] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  238.103725] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  238.103744] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  238.103753] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  238.103772] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  238.103791] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  238.103809] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  238.103827] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  238.103847] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  238.103865] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  238.103884] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  238.103902] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:102, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  238.103921] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:108, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  238.103945] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 104
>[32m[  238.103965] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  238.103984] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  238.104471] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.104492] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  238.104520] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.104577] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  238.104598] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  238.104603] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.107247] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  238.129934] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  238.129963] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  238.130206] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  238.130228] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  238.130251] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  238.130271] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  238.130292] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.130316] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  238.130357] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  238.130971] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  238.131266] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  238.131295] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  238.131316] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  238.131341] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  238.131361] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  238.131387] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  238.131410] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  238.131430] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  238.166170] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  238.166201] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  238.166240] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.166252] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.166271] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.199762] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  238.199940] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  238.204603] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  238.216074] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.216083] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128e9978 state to ffff8801f12574e8
>[32m[  238.216089] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121e678 state to ffff8801f12574e8
>[32m[  238.216092] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [CRTC:36:pipe A]
>[32m[  238.216095] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802128e9978
>[32m[  238.216104] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128eb538 state to ffff8801f12574e8
>[32m[  238.216107] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [CRTC:36:pipe A]
>[32m[  238.216110] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8802128eb538
>[32m[  238.216118] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802135a3098 state to ffff8801f12574e8
>[32m[  238.216120] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [CRTC:36:pipe A]
>[32m[  238.216123] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff8802135a3098
>[32m[  238.216130] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121e678
>[32m[  238.216139] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd660a28 state to ffff8801f12574e8
>[32m[  238.216144] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.216150] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  238.216153] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  238.216183] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 113
>[32m[  238.216205] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  238.216227] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 110
>[32m[  238.216247] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  238.216266] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 112
>[32m[  238.216285] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  238.216290] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.232644] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.232667] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.233238] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.233246] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b83a8 state to ffff8801f12574e8
>[32m[  238.233249] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.233252] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.233254] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  238.233257] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.233268] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.233281] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.233336] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  238.239334] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.239342] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111ccde8 state to ffff8801f12574e8
>[32m[  238.239348] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121d3d8 state to ffff8801f12574e8
>[32m[  238.239351] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [CRTC:36:pipe A]
>[32m[  238.239354] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff8802111ccde8
>[32m[  238.239363] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cf098 state to ffff8801f12574e8
>[32m[  238.239365] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [NOCRTC]
>[32m[  238.239368] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf098
>[32m[  238.239376] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cd288 state to ffff8801f12574e8
>[32m[  238.239378] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [NOCRTC]
>[32m[  238.239381] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd288
>[32m[  238.239387] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121d3d8
>[32m[  238.239395] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd661298 state to ffff8801f12574e8
>[32m[  238.239398] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd661298 to [NOCRTC]
>[32m[  238.239403] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b9b38 state to ffff8801f12574e8
>[32m[  238.239406] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b9b38 to [CRTC:36:pipe A]
>[32m[  238.239408] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.239411] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  238.239415] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  238.239417] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  238.239419] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.239422] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:36:pipe A]
>[32m[  238.239424] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  238.239426] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  238.239431] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  238.239460] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  238.239482] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  238.239505] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  238.239525] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  238.239547] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  238.239567] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  238.239587] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  238.239607] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  238.239627] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  238.239646] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  238.239664] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  238.239667] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  238.239685] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  238.239687] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  238.239706] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  238.239723] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  238.239741] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  238.239759] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  238.239779] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  238.239797] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  238.239816] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:113, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  238.239834] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:110, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  238.239853] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:112, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  238.239876] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 111
>[32m[  238.239896] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  238.239915] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  238.239934] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.239953] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  238.239972] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.241025] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  238.241047] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  238.241052] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.243385] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  238.268087] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  238.268114] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  238.268346] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  238.268369] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  238.268388] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  238.268408] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  238.268430] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.268452] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  238.268482] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  238.269354] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  238.269536] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  238.269567] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  238.269586] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  238.269612] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  238.269632] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  238.269650] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  238.269673] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  238.269692] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  238.304723] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  238.304755] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  238.304795] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.304808] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.304826] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.338222] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.338231] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff8801f12574e8
>[32m[  238.338236] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9694a88 state to ffff8801f12574e8
>[32m[  238.338239] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.338244] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.338247] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  238.338252] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.354696] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.354708] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.354971] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  238.355327] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  238.359617] [0m[drm:drm_mode_addfb2] [FB:117]
>[32m[  238.371414] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.371423] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ee51978 state to ffff8801f12574e8
>[32m[  238.371429] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880211ec8958 state to ffff8801f12574e8
>[32m[  238.371432] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee51978 to [CRTC:36:pipe A]
>[32m[  238.371436] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff88020ee51978
>[32m[  238.371445] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ee52e48 state to ffff8801f12574e8
>[32m[  238.371448] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [CRTC:36:pipe A]
>[32m[  238.371451] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88020ee52e48
>[32m[  238.371459] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212945978 state to ffff8801f12574e8
>[32m[  238.371462] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212945978 to [CRTC:36:pipe A]
>[32m[  238.371464] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff880212945978
>[32m[  238.371472] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880211ec8958
>[32m[  238.371481] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b83a8 state to ffff8801f12574e8
>[32m[  238.371485] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.371491] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.371494] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  238.371525] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 117
>[32m[  238.371548] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  238.371570] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 114
>[32m[  238.371590] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  238.371610] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 116
>[32m[  238.371629] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  238.371634] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.388030] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.388053] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.388299] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  238.388307] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801f12574e8
>[32m[  238.388312] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e2548 state to ffff8801f12574e8
>[32m[  238.388314] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  238.388319] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.388322] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  238.388326] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  238.404681] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  238.404694] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  238.404836] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  238.414413] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250ff8
>[32m[  238.414419] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95304a8 state to ffff8801f1250ff8
>[32m[  238.414425] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ec9c138 state to ffff8801f1250ff8
>[32m[  238.414429] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95306f8 state to ffff8801f1250ff8
>[32m[  238.414431] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [NOCRTC]
>[32m[  238.414433] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95306f8
>[32m[  238.414437] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9530258 state to ffff8801f1250ff8
>[32m[  238.414438] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [NOCRTC]
>[32m[  238.414440] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530258
>[32m[  238.414444] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9531288 state to ffff8801f1250ff8
>[32m[  238.414446] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250ff8
>[32m[  238.414463] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9531288 state to ffff8801f1250ff8
>[32m[  238.414467] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ec9c138 state to ffff8801f1250ff8
>[32m[  238.414471] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95314d8 state to ffff8801f1250ff8
>[32m[  238.414472] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95314d8 to [NOCRTC]
>[32m[  238.414474] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95314d8
>[32m[  238.414476] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250ff8
>[32m[  238.414486] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95314d8 state to ffff8801f1250ff8
>[32m[  238.414490] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ec9c138 state to ffff8801f1250ff8
>[32m[  238.414494] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9533c28 state to ffff8801f1250ff8
>[32m[  238.414496] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533c28 to [NOCRTC]
>[32m[  238.414497] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533c28
>[32m[  238.414501] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9531288 state to ffff8801f1250ff8
>[32m[  238.414502] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [NOCRTC]
>[32m[  238.414504] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531288
>[32m[  238.414508] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9531038 state to ffff8801f1250ff8
>[32m[  238.414511] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9530258 state to ffff8801f1250ff8
>[32m[  238.414513] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [NOCRTC]
>[32m[  238.414514] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530258
>[32m[  238.414518] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f95332e8 state to ffff8801f1250ff8
>[32m[  238.414520] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [NOCRTC]
>[32m[  238.414521] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95332e8
>[32m[  238.414525] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f95306f8 state to ffff8801f1250ff8
>[32m[  238.414529] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9532758 state to ffff8801f1250ff8
>[32m[  238.414530] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [NOCRTC]
>[32m[  238.414532] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532758
>[32m[  238.414536] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f95304a8 state to ffff8801f1250ff8
>[32m[  238.414537] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [NOCRTC]
>[32m[  238.414539] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95304a8
>[32m[  238.414545] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff88020ec9c138
>[32m[  238.414547] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95314d8 to [CRTC:36:pipe A]
>[32m[  238.414549] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f95314d8
>[32m[  238.414552] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1250ff8
>[32m[  238.414559] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff8801f1250ff8
>[32m[  238.414561] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [NOCRTC]
>[32m[  238.414566] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd660f38 state to ffff8801f1250ff8
>[32m[  238.414568] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd660f38 to [CRTC:36:pipe A]
>[32m[  238.414570] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250ff8
>[32m[  238.414601] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95304a8 state to ffff8801f1250ff8
>[32m[  238.414605] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ec9c138 state to ffff8801f1250ff8
>[32m[  238.414609] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9532e48 state to ffff8801f1250ff8
>[32m[  238.414610] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532e48 to [NOCRTC]
>[32m[  238.414612] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532e48
>[32m[  238.414616] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9532758 state to ffff8801f1250ff8
>[32m[  238.414617] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [NOCRTC]
>[32m[  238.414619] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532758
>[32m[  238.414622] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9533788 state to ffff8801f1250ff8
>[32m[  238.414626] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f95306f8 state to ffff8801f1250ff8
>[32m[  238.414628] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [NOCRTC]
>[32m[  238.414629] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95306f8
>[32m[  238.414633] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f95314d8 state to ffff8801f1250ff8
>[32m[  238.414634] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95314d8 to [NOCRTC]
>[32m[  238.414636] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95314d8
>[32m[  238.414640] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f95332e8 state to ffff8801f1250ff8
>[32m[  238.414643] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9533c28 state to ffff8801f1250ff8
>[32m[  238.414645] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533c28 to [NOCRTC]
>[32m[  238.414646] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533c28
>[32m[  238.414650] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9530258 state to ffff8801f1250ff8
>[32m[  238.414651] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [NOCRTC]
>[32m[  238.414653] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530258
>[32m[  238.414657] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff88020ec9c138
>[32m[  238.414659] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [CRTC:36:pipe A]
>[32m[  238.414660] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f95304a8
>[32m[  238.414663] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1250ff8
>[32m[  238.414667] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff8801f1250ff8
>[32m[  238.414669] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [NOCRTC]
>[32m[  238.414673] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd660f38 state to ffff8801f1250ff8
>[32m[  238.414675] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd660f38 to [CRTC:36:pipe A]
>[32m[  238.414679] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff88020ec9d3d8 state to ffff8801f1250ff8
>[32m[  238.414684] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88020ec9d3d8
>[32m[  238.414686] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [CRTC:46:pipe B]
>[32m[  238.414687] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9533788
>[32m[  238.414689] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250ff8
>[32m[  238.414692] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [CRTC:46:pipe B]
>[32m[  238.414697] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8802144bc138 state to ffff8801f1250ff8
>[32m[  238.414699] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8802144bc138
>[32m[  238.414700] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [NOCRTC]
>[32m[  238.414702] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95332e8
>[32m[  238.414704] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1250ff8
>[32m[  238.414707] [0m[drm:drm_atomic_check_only] checking ffff8801f1250ff8
>[32m[  238.414710] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  238.414711] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  238.414713] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  238.414714] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  238.414718] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  238.414720] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  238.414722] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.414724] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  238.414726] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  238.414728] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1250ff8
>[32m[  238.414731] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  238.414733] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250ff8
>[32m[  238.414737] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1250ff8
>[32m[  238.414765] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  238.414787] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  238.414808] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  238.414828] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  238.414849] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  238.414869] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  238.414889] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  238.414908] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  238.414926] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  238.414928] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  238.414946] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  238.414948] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  238.414967] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  238.414985] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  238.415028] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  238.415055] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  238.415075] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  238.415093] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  238.415111] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:117, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  238.415129] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:114, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  238.415147] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:116, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  238.415150] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250ff8
>[32m[  238.415170] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  238.415189] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  238.415210] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  238.415229] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  238.415249] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  238.415267] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  238.415285] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  238.415303] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  238.415320] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  238.415337] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  238.415354] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  238.415356] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  238.415373] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  238.415375] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  238.415392] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  238.415409] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  238.415426] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  238.415443] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  238.415463] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  238.415480] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  238.415497] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0
>[32m[  238.415514] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  238.415531] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  238.415554] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  238.415573] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  238.415592] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  238.415610] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.415628] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  238.415646] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.415664] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  238.415682] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  238.415719] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  238.415738] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  238.415775] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  238.415793] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  238.415797] [0m[drm:drm_atomic_commit] committing ffff8801f1250ff8
>[32m[  238.415877] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  238.439657] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  238.439685] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  238.439920] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  238.439940] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  238.439958] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  238.439978] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.440001] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  238.440065] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  238.440696] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  238.440878] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  238.440907] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  238.440926] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  238.440951] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  238.440970] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  238.440987] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  238.441018] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  238.441037] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  238.459152] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  238.459818] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  238.460002] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  238.460057] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  238.460086] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  238.460112] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  238.460131] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  238.460149] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  238.460172] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  238.460191] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  238.495006] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  238.495054] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  238.495102] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.495132] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  238.495155] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  238.495192] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  238.495207] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250ff8
>[32m[  238.495250] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250ff8
>[32m[  238.499241] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  238.508446] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250ff8
>[32m[  238.508454] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9532508 state to ffff8801f1250ff8
>[32m[  238.508460] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e5d28 state to ffff8801f1250ff8
>[32m[  238.508465] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9531288 state to ffff8801f1250ff8
>[32m[  238.508468] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [NOCRTC]
>[32m[  238.508470] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531288
>[32m[  238.508475] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9531038 state to ffff8801f1250ff8
>[32m[  238.508477] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [NOCRTC]
>[32m[  238.508479] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531038
>[32m[  238.508483] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec51728 state to ffff8801f1250ff8
>[32m[  238.508488] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff88020ffbc138 state to ffff8801f1250ff8
>[32m[  238.508491] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250ff8
>[32m[  238.508513] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020e07b2e8 state to ffff8801f1250ff8
>[32m[  238.508518] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e5d28 state to ffff8801f1250ff8
>[32m[  238.508522] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e07a508 state to ffff8801f1250ff8
>[32m[  238.508525] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [NOCRTC]
>[32m[  238.508527] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a508
>[32m[  238.508529] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250ff8
>[32m[  238.508541] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020e07a508 state to ffff8801f1250ff8
>[32m[  238.508545] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ffbc138 state to ffff8801f1250ff8
>[32m[  238.508550] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e07b788 state to ffff8801f1250ff8
>[32m[  238.508552] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b788 to [NOCRTC]
>[32m[  238.508554] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b788
>[32m[  238.508559] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e07b2e8 state to ffff8801f1250ff8
>[32m[  238.508561] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b2e8 to [NOCRTC]
>[32m[  238.508563] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b2e8
>[32m[  238.508567] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020e0794d8 state to ffff8801f1250ff8
>[32m[  238.508572] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f95e5d28 state to ffff8801f1250ff8
>[32m[  238.508576] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e07a9a8 state to ffff8801f1250ff8
>[32m[  238.508578] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [NOCRTC]
>[32m[  238.508580] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a9a8
>[32m[  238.508585] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020e078de8 state to ffff8801f1250ff8
>[32m[  238.508587] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078de8 to [NOCRTC]
>[32m[  238.508589] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078de8
>[32m[  238.508593] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020e078258 state to ffff8801f1250ff8
>[32m[  238.508598] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212c258 state to ffff8801f1250ff8
>[32m[  238.508600] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c258 to [NOCRTC]
>[32m[  238.508602] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c258
>[32m[  238.508606] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212fc28 state to ffff8801f1250ff8
>[32m[  238.508608] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [NOCRTC]
>[32m[  238.508610] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212fc28
>[32m[  238.508617] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff88020ffbc138
>[32m[  238.508620] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [CRTC:36:pipe A]
>[32m[  238.508622] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020e07a508
>[32m[  238.508625] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250ff8
>[32m[  238.508654] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212fc28 state to ffff8801f1250ff8
>[32m[  238.508659] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ffbc138 state to ffff8801f1250ff8
>[32m[  238.508664] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212c008 state to ffff8801f1250ff8
>[32m[  238.508666] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [NOCRTC]
>[32m[  238.508668] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c008
>[32m[  238.508672] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212c258 state to ffff8801f1250ff8
>[32m[  238.508674] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c258 to [NOCRTC]
>[32m[  238.508676] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c258
>[32m[  238.508681] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212e9a8 state to ffff8801f1250ff8
>[32m[  238.508685] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f95e5d28 state to ffff8801f1250ff8
>[32m[  238.508690] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212d978 state to ffff8801f1250ff8
>[32m[  238.508692] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [NOCRTC]
>[32m[  238.508694] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212d978
>[32m[  238.508698] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212c6f8 state to ffff8801f1250ff8
>[32m[  238.508700] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  238.508702] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  238.508707] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212ebf8 state to ffff8801f1250ff8
>[32m[  238.508711] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212c4a8 state to ffff8801f1250ff8
>[32m[  238.508713] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [NOCRTC]
>[32m[  238.508715] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c4a8
>[32m[  238.508719] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212de18 state to ffff8801f1250ff8
>[32m[  238.508721] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  238.508723] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  238.508729] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff88020ffbc138
>[32m[  238.508731] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [CRTC:36:pipe A]
>[32m[  238.508733] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88021212fc28
>[32m[  238.508736] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1250ff8
>[32m[  238.508744] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd661cb8 state to ffff8801f1250ff8
>[32m[  238.508748] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd661cb8 to [NOCRTC]
>[32m[  238.508751] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd661cb8 to [CRTC:36:pipe A]
>[32m[  238.508756] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f95e5d28
>[32m[  238.508758] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [CRTC:46:pipe B]
>[32m[  238.508760] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88021212e9a8
>[32m[  238.508763] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250ff8
>[32m[  238.508769] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048ae8 state to ffff8801f1250ff8
>[32m[  238.508771] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048ae8 to [NOCRTC]
>[32m[  238.508774] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048ae8 to [CRTC:46:pipe B]
>[32m[  238.508784] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff8801f1250ff8
>[32m[  238.508786] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f1268008
>[32m[  238.508788] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [NOCRTC]
>[32m[  238.508790] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212ebf8
>[32m[  238.508793] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1250ff8
>[32m[  238.508796] [0m[drm:drm_atomic_check_only] checking ffff8801f1250ff8
>[32m[  238.508802] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  238.508805] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  238.508807] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.508810] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  238.508841] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  238.508864] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  238.508887] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  238.508908] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  238.508915] [0m[drm:drm_atomic_commit] committing ffff8801f1250ff8
>[32m[  238.525626] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250ff8
>[32m[  238.525676] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250ff8
>[32m[  238.561728] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  238.561824] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  238.580200] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  238.580234] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  238.580262] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  238.580282] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  238.618596] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  238.618667] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  238.618670] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  238.618672] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  238.618675] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  238.618677] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  238.618679] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  238.618681] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  238.618683] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  238.618685] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  238.618687] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  238.618689] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  238.618691] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  238.618693] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  238.618788] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  238.618818] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  238.693371] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  238.693394] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  238.695453] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  238.695459] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  238.695463] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  238.695479] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  238.695591] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  238.695593] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  238.695595] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  238.695724] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  238.695727] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  238.695729] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  238.695731] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  238.695733] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  238.695735] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  238.695737] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  238.695739] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  238.695742] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  238.695744] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  238.695746] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  238.695748] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  238.695750] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  238.695752] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  238.695754] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  238.695756] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  238.695758] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  238.695760] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  238.695762] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  238.695911] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  238.695920] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f978d058 state to ffff8801f1251fe8
>[32m[  238.695926] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126dd28 state to ffff8801f1251fe8
>[32m[  238.695929] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  238.695934] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.695937] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  238.695943] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  238.711657] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  238.711686] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  238.711714] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  238.711739] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  238.714299] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.716828] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.719359] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.721887] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.724414] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.726943] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.729470] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.731998] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.734617] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.737175] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.739729] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.742284] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.744837] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.747389] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.749939] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.752493] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.755056] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.757594] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.760122] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.762649] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.765179] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.767707] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.770238] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.772766] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.775293] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.777821] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.780347] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.782873] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.785402] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.787927] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.790454] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.792981] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  238.793043] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  238.793060] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  238.793223] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  238.793231] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff880211e0d3f8 state to ffff8801f1251fe8
>[32m[  238.793233] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  238.793249] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  238.793251] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  238.793254] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  238.793268] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  238.793281] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  238.793367] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest atomic-pipe-B-tiling-none
>[32m[  238.793610] [0m[drm:drm_mode_addfb2] [FB:95]
>[32m[  238.800525] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252538
>[32m[  238.800537] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128ea2b8 state to ffff8801f1252538
>[32m[  238.800543] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12692a8 state to ffff8801f1252538
>[32m[  238.800546] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [NOCRTC]
>[32m[  238.800549] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128ea2b8
>[32m[  238.800555] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128e8258 state to ffff8801f1252538
>[32m[  238.800558] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e8258 to [NOCRTC]
>[32m[  238.800560] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e8258
>[32m[  238.800566] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128eb098 state to ffff8801f1252538
>[32m[  238.800568] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb098 to [NOCRTC]
>[32m[  238.800570] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb098
>[32m[  238.800575] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f12692a8
>[32m[  238.800581] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128e9978 state to ffff8801f1252538
>[32m[  238.800587] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126ca88 state to ffff8801f1252538
>[32m[  238.800589] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [CRTC:46:pipe B]
>[32m[  238.800592] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:95] for plane state ffff8802128e9978
>[32m[  238.800602] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128e9728 state to ffff8801f1252538
>[32m[  238.800604] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [NOCRTC]
>[32m[  238.800606] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9728
>[32m[  238.800612] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128eb538 state to ffff8801f1252538
>[32m[  238.800614] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [NOCRTC]
>[32m[  238.800616] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb538
>[32m[  238.800621] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126ca88
>[32m[  238.800627] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128eabf8 state to ffff8801f1252538
>[32m[  238.800629] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [NOCRTC]
>[32m[  238.800631] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eabf8
>[32m[  238.800637] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128e86f8 state to ffff8801f1252538
>[32m[  238.800639] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [NOCRTC]
>[32m[  238.800641] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e86f8
>[32m[  238.800647] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802121329a8 state to ffff8801f1252538
>[32m[  238.800649] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [NOCRTC]
>[32m[  238.800651] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121329a8
>[32m[  238.800657] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff8801f1252538
>[32m[  238.800668] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d57a8 state to ffff8801f1252538
>[32m[  238.800670] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d57a8 to [CRTC:46:pipe B]
>[32m[  238.800676] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211e0d5c8 state to ffff8801f1252538
>[32m[  238.800679] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880211e0d5c8 to [NOCRTC]
>[32m[  238.800684] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff880211e0d798 state to ffff8801f1252538
>[32m[  238.800686] [0m[drm:drm_atomic_check_only] checking ffff8801f1252538
>[32m[  238.800690] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  238.800692] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  238.800694] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  238.800696] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  238.800700] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  238.800703] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  238.800705] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.800707] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  238.800709] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  238.800711] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  238.800713] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: n, active: n
>[32m[  238.800716] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252538
>[32m[  238.800719] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  238.800721] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252538
>[32m[  238.800725] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252538
>[32m[  238.800758] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  238.800780] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  238.800801] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  238.800821] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  238.800842] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  238.800862] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  238.800882] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  238.800901] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  238.800920] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  238.800923] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  238.800941] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  238.800944] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  238.800963] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  238.800982] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  238.801000] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  238.802127] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  238.802161] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  238.802181] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  238.802201] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:96, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  238.802219] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  238.802238] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  238.802261] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb -1
>[32m[  238.802281] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.802302] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 95
>[32m[  238.802321] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  238.802361] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  238.802381] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  238.802386] [0m[drm:drm_atomic_commit] committing ffff8801f1252538
>[32m[  238.805038] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  238.825711] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  238.825739] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  238.825983] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  238.846774] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  238.846801] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  238.847114] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  238.847136] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  238.847159] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  238.847192] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  238.847214] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:65:DP-1]
>[32m[  238.847235] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.847258] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  238.847295] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  238.847921] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  238.848185] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  238.848228] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  238.848260] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  238.848286] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  238.848305] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  238.848322] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  238.848346] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  238.848378] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  238.883143] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  238.883174] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  238.883201] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  238.883240] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.883255] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252538
>[32m[  238.883295] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252538
>[32m[  238.916778] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  238.916930] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  238.921622] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  238.933049] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  238.933070] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802135a3098 state to ffff8801f1250aa8
>[32m[  238.933077] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121c138 state to ffff8801f1250aa8
>[32m[  238.933080] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [CRTC:46:pipe B]
>[32m[  238.933083] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8802135a3098
>[32m[  238.933093] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cfc28 state to ffff8801f1250aa8
>[32m[  238.933096] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cfc28 to [CRTC:46:pipe B]
>[32m[  238.933099] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff8802111cfc28
>[32m[  238.933107] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111ccde8 state to ffff8801f1250aa8
>[32m[  238.933110] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [CRTC:46:pipe B]
>[32m[  238.933112] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff8802111ccde8
>[32m[  238.933120] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121c138
>[32m[  238.933129] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d4518 state to ffff8801f1250aa8
>[32m[  238.933134] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  238.933140] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  238.933143] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  238.933173] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 100
>[32m[  238.933196] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  238.933218] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 66
>[32m[  238.933239] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  238.933259] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 82
>[32m[  238.933278] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  238.933283] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  238.949591] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  238.949614] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  238.950150] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  238.950159] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b9b38 state to ffff8801f1250aa8
>[32m[  238.950175] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  238.950178] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.950180] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  238.950184] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  238.950207] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  238.950219] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  238.950317] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  238.956214] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  238.956223] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cdbc8 state to ffff8801f1256f98
>[32m[  238.956229] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121dd28 state to ffff8801f1256f98
>[32m[  238.956232] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cdbc8 to [CRTC:46:pipe B]
>[32m[  238.956235] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8802111cdbc8
>[32m[  238.956244] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cf9d8 state to ffff8801f1256f98
>[32m[  238.956246] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  238.956249] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  238.956257] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cee48 state to ffff8801f1256f98
>[32m[  238.956259] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cee48 to [NOCRTC]
>[32m[  238.956262] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cee48
>[32m[  238.956269] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121dd28
>[32m[  238.956277] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d57a8 state to ffff8801f1256f98
>[32m[  238.956279] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d57a8 to [NOCRTC]
>[32m[  238.956285] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801f1256f98
>[32m[  238.956287] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b81d8 to [CRTC:46:pipe B]
>[32m[  238.956290] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  238.956293] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  238.956297] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  238.956299] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  238.956301] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  238.956304] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:46:pipe B]
>[32m[  238.956306] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  238.956309] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  238.956313] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  238.956342] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  238.956365] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  238.956388] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  238.956408] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  238.956430] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  238.956449] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  238.956470] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  238.956490] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  238.956509] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  238.956528] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  238.956546] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  238.956549] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  238.956568] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  238.956570] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  238.956589] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  238.956608] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  238.956626] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  238.956644] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  238.956665] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  238.956683] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  238.956702] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  238.956720] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  238.956739] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:82, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  238.956762] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 99
>[32m[  238.956782] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  238.956802] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  238.956821] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.956840] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  238.956859] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  238.956896] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  238.956916] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  238.956920] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  238.959953] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  238.983696] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  238.983724] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  238.983956] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  238.983979] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  238.983999] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  238.984152] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  238.984176] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  238.984209] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  238.984249] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  238.984890] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  238.985125] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  238.985165] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  238.985186] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  238.985219] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  238.985238] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  238.985256] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  238.985279] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  238.985298] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  239.020117] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  239.020149] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  239.020188] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.020200] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.020219] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.053609] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.053618] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff8801f1256f98
>[32m[  239.053624] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121e678 state to ffff8801f1256f98
>[32m[  239.053626] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.053631] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.053634] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.053638] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.070095] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.070106] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.070359] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  239.070496] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  239.074619] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  239.086862] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.086871] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ee51978 state to ffff8801f1256f98
>[32m[  239.086877] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121d3d8 state to ffff8801f1256f98
>[32m[  239.086880] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee51978 to [CRTC:46:pipe B]
>[32m[  239.086883] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff88020ee51978
>[32m[  239.086893] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ee52e48 state to ffff8801f1256f98
>[32m[  239.086896] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [CRTC:46:pipe B]
>[32m[  239.086899] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff88020ee52e48
>[32m[  239.086907] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802129462b8 state to ffff8801f1256f98
>[32m[  239.086909] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802129462b8 to [CRTC:46:pipe B]
>[32m[  239.086912] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8802129462b8
>[32m[  239.086919] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121d3d8
>[32m[  239.086928] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b9b38 state to ffff8801f1256f98
>[32m[  239.086933] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.086938] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.086941] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.086973] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 109
>[32m[  239.086996] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  239.087354] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 102
>[32m[  239.087376] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  239.087405] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 108
>[32m[  239.087425] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  239.087430] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.103427] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.103448] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.103657] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.103665] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff8801f1256f98
>[32m[  239.103670] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121e678 state to ffff8801f1256f98
>[32m[  239.103672] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.103677] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.103680] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.103684] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.120080] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.120091] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.120335] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  239.126823] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.126832] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9533538 state to ffff8801f1256f98
>[32m[  239.126838] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121d3d8 state to ffff8801f1256f98
>[32m[  239.126840] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533538 to [CRTC:46:pipe B]
>[32m[  239.126844] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:104] for plane state ffff8801f9533538
>[32m[  239.126853] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f95304a8 state to ffff8801f1256f98
>[32m[  239.126855] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [NOCRTC]
>[32m[  239.126858] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95304a8
>[32m[  239.126866] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9532bf8 state to ffff8801f1256f98
>[32m[  239.126868] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [NOCRTC]
>[32m[  239.126871] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532bf8
>[32m[  239.126878] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121d3d8
>[32m[  239.126886] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d4518 state to ffff8801f1256f98
>[32m[  239.126889] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d4518 to [CRTC:46:pipe B]
>[32m[  239.126894] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8ae8 state to ffff8801f1256f98
>[32m[  239.126896] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8ae8 to [NOCRTC]
>[32m[  239.126899] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.126902] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  239.126906] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  239.126908] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:46:pipe B]
>[32m[  239.126910] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.126912] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  239.126915] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  239.126917] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  239.126921] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  239.126950] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  239.126972] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  239.126994] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  239.127446] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  239.127468] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  239.127497] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  239.127537] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  239.127557] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  239.127575] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  239.127578] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  239.127597] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  239.127599] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  239.127619] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  239.127637] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  239.127656] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  239.127674] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  239.127702] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  239.127720] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  239.127739] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  239.127758] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:102, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  239.127776] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:108, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  239.127800] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 104
>[32m[  239.127820] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  239.127840] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  239.127859] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  239.127878] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  239.127897] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  239.127934] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  239.127954] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  239.127958] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.130879] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  239.154700] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  239.154728] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  239.154961] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  239.154981] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  239.155002] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  239.155164] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  239.155196] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.155220] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  239.155252] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  239.155875] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  239.156125] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  239.156157] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  239.156186] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  239.156219] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  239.156239] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  239.156256] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  239.156279] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  239.156299] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  239.191044] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  239.191076] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  239.191114] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.191126] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.191143] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.224673] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  239.224810] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  239.229468] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  239.240949] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.240958] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f95306f8 state to ffff8801f1256f98
>[32m[  239.240964] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121e678 state to ffff8801f1256f98
>[32m[  239.240967] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [CRTC:46:pipe B]
>[32m[  239.240970] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8801f95306f8
>[32m[  239.240980] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f95332e8 state to ffff8801f1256f98
>[32m[  239.240982] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [CRTC:46:pipe B]
>[32m[  239.240985] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801f95332e8
>[32m[  239.241238] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f95314d8 state to ffff8801f1256f98
>[32m[  239.241241] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95314d8 to [CRTC:46:pipe B]
>[32m[  239.241243] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff8801f95314d8
>[32m[  239.241251] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121e678
>[32m[  239.241255] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.241272] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec51728 state to ffff8801f1256f98
>[32m[  239.241277] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121e678 state to ffff8801f1256f98
>[32m[  239.241279] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec51728 to [CRTC:46:pipe B]
>[32m[  239.241282] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff88020ec51728
>[32m[  239.241291] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e078258 state to ffff8801f1256f98
>[32m[  239.241293] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [CRTC:46:pipe B]
>[32m[  239.241296] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88020e078258
>[32m[  239.241302] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.241314] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020e078258 state to ffff8801f1256f98
>[32m[  239.241318] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121e678 state to ffff8801f1256f98
>[32m[  239.241321] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [CRTC:46:pipe B]
>[32m[  239.241323] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff88020e078258
>[32m[  239.241331] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e078de8 state to ffff8801f1256f98
>[32m[  239.241334] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078de8 to [CRTC:46:pipe B]
>[32m[  239.241336] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88020e078de8
>[32m[  239.241344] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020e07a508 state to ffff8801f1256f98
>[32m[  239.241347] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [CRTC:46:pipe B]
>[32m[  239.241349] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88020e07a508
>[32m[  239.241356] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121e678
>[32m[  239.241364] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d57a8 state to ffff8801f1256f98
>[32m[  239.241369] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.241375] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  239.241377] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  239.241408] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 113
>[32m[  239.241440] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  239.241462] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 110
>[32m[  239.241482] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  239.241502] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 112
>[32m[  239.241521] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  239.241526] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.257521] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.257542] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.257940] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.257948] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801f1256f98
>[32m[  239.257951] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.257954] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.257956] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  239.257959] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.257971] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.257984] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.258276] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  239.264106] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.264114] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2ee48 state to ffff8801f1256f98
>[32m[  239.264120] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12192a8 state to ffff8801f1256f98
>[32m[  239.264123] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2ee48 to [CRTC:46:pipe B]
>[32m[  239.264126] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff88020ec2ee48
>[32m[  239.264135] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2e2b8 state to ffff8801f1256f98
>[32m[  239.264138] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [NOCRTC]
>[32m[  239.264140] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e2b8
>[32m[  239.264148] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2cde8 state to ffff8801f1256f98
>[32m[  239.264150] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  239.264153] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  239.264160] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f12192a8
>[32m[  239.264168] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d4518 state to ffff8801f1256f98
>[32m[  239.264170] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d4518 to [NOCRTC]
>[32m[  239.264176] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff8801f1256f98
>[32m[  239.264178] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b93f8 to [CRTC:46:pipe B]
>[32m[  239.264180] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.264184] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  239.264188] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  239.264190] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  239.264192] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.264194] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:46:pipe B]
>[32m[  239.264197] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  239.264199] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  239.264204] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  239.264232] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  239.264254] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  239.264277] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  239.264298] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  239.264319] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  239.264339] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  239.264360] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  239.264380] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  239.264400] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  239.264419] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  239.264437] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  239.264440] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  239.264459] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  239.264461] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  239.264480] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  239.264499] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  239.264517] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  239.264535] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  239.264555] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  239.264573] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  239.264592] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:113, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  239.264611] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:110, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  239.264629] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:112, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  239.264652] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 111
>[32m[  239.264672] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  239.264692] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  239.264711] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  239.264730] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  239.264748] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  239.264786] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  239.264805] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  239.264810] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.267767] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  239.291694] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  239.291722] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  239.291954] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  239.291977] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  239.291996] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  239.292158] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  239.292190] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.292214] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  239.292245] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  239.292896] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  239.293124] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  239.293156] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  239.293185] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  239.293221] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  239.293242] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  239.293261] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  239.293306] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  239.293327] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  239.328152] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  239.328183] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  239.328222] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.328234] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.328251] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.361643] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.361651] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff8801f1256f98
>[32m[  239.361656] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121d3d8 state to ffff8801f1256f98
>[32m[  239.361659] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.361664] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.361667] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.361671] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.378131] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.378143] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.378391] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  239.378526] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  239.382725] [0m[drm:drm_mode_addfb2] [FB:117]
>[32m[  239.394895] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.394905] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5ce2b8 state to ffff8801f1256f98
>[32m[  239.394911] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121ca88 state to ffff8801f1256f98
>[32m[  239.394914] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce2b8 to [CRTC:46:pipe B]
>[32m[  239.394917] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5ce2b8
>[32m[  239.394927] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5ce508 state to ffff8801f1256f98
>[32m[  239.394929] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [CRTC:46:pipe B]
>[32m[  239.394932] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801fb5ce508
>[32m[  239.394941] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5ce758 state to ffff8801f1256f98
>[32m[  239.394943] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [CRTC:46:pipe B]
>[32m[  239.394946] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801fb5ce758
>[32m[  239.394953] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121ca88
>[32m[  239.394958] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.394973] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5ce758 state to ffff8801f1256f98
>[32m[  239.394978] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121ca88 state to ffff8801f1256f98
>[32m[  239.394980] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [CRTC:46:pipe B]
>[32m[  239.394983] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5ce758
>[32m[  239.395300] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cf098 state to ffff8801f1256f98
>[32m[  239.395303] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [CRTC:46:pipe B]
>[32m[  239.395306] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801fb5cf098
>[32m[  239.395313] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.395327] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cf098 state to ffff8801f1256f98
>[32m[  239.395333] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121ca88 state to ffff8801f1256f98
>[32m[  239.395335] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [CRTC:46:pipe B]
>[32m[  239.395338] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5cf098
>[32m[  239.395347] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cd978 state to ffff8801f1256f98
>[32m[  239.395350] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd978 to [CRTC:46:pipe B]
>[32m[  239.395353] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801fb5cd978
>[32m[  239.395362] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5ce758 state to ffff8801f1256f98
>[32m[  239.395364] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [CRTC:46:pipe B]
>[32m[  239.395367] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801fb5ce758
>[32m[  239.395374] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121ca88
>[32m[  239.395383] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801f1256f98
>[32m[  239.395388] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.395394] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.395405] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.395447] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 117
>[32m[  239.395487] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  239.395512] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 114
>[32m[  239.395534] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  239.395556] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 116
>[32m[  239.395577] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  239.395583] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.411466] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.411487] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.411698] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  239.411706] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b83a8 state to ffff8801f1256f98
>[32m[  239.411711] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9692548 state to ffff8801f1256f98
>[32m[  239.411713] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  239.411718] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.411721] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.411725] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  239.428117] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  239.428129] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  239.428267] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  239.438370] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12564f8
>[32m[  239.438377] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cdbc8 state to ffff8801f12564f8
>[32m[  239.438381] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ccb98 state to ffff8801f12564f8
>[32m[  239.438383] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ccb98 to [NOCRTC]
>[32m[  239.438385] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ccb98
>[32m[  239.438389] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cde18 state to ffff8801f12564f8
>[32m[  239.438391] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cde18 to [NOCRTC]
>[32m[  239.438392] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cde18
>[32m[  239.438396] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cd288 state to ffff8801f12564f8
>[32m[  239.438401] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9696678 state to ffff8801f12564f8
>[32m[  239.438405] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cf538 state to ffff8801f12564f8
>[32m[  239.438406] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf538 to [NOCRTC]
>[32m[  239.438408] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf538
>[32m[  239.438412] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cd728 state to ffff8801f12564f8
>[32m[  239.438413] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [NOCRTC]
>[32m[  239.438415] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd728
>[32m[  239.438418] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cf2e8 state to ffff8801f12564f8
>[32m[  239.438422] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cc258 state to ffff8801f12564f8
>[32m[  239.438424] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc258 to [NOCRTC]
>[32m[  239.438425] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc258
>[32m[  239.438430] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212de18 state to ffff8801f12564f8
>[32m[  239.438432] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  239.438433] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  239.438436] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12564f8
>[32m[  239.438462] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212de18 state to ffff8801f12564f8
>[32m[  239.438466] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212c4a8 state to ffff8801f12564f8
>[32m[  239.438467] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [NOCRTC]
>[32m[  239.438469] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c4a8
>[32m[  239.438473] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212fc28 state to ffff8801f12564f8
>[32m[  239.438474] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [NOCRTC]
>[32m[  239.438476] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212fc28
>[32m[  239.438478] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12564f8
>[32m[  239.438489] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212fc28 state to ffff8801f12564f8
>[32m[  239.438493] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212c008 state to ffff8801f12564f8
>[32m[  239.438494] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [NOCRTC]
>[32m[  239.438496] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c008
>[32m[  239.438500] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212c4a8 state to ffff8801f12564f8
>[32m[  239.438501] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [NOCRTC]
>[32m[  239.438503] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c4a8
>[32m[  239.438507] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212c258 state to ffff8801f12564f8
>[32m[  239.438511] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9696678 state to ffff8801f12564f8
>[32m[  239.438514] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212de18 state to ffff8801f12564f8
>[32m[  239.438516] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  239.438517] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  239.438521] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212e9a8 state to ffff8801f12564f8
>[32m[  239.438523] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [NOCRTC]
>[32m[  239.438524] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212e9a8
>[32m[  239.438528] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212ebf8 state to ffff8801f12564f8
>[32m[  239.438532] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212d978 state to ffff8801f12564f8
>[32m[  239.438533] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [NOCRTC]
>[32m[  239.438535] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212d978
>[32m[  239.438538] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212c6f8 state to ffff8801f12564f8
>[32m[  239.438540] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  239.438541] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  239.438546] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9694a88 state to ffff8801f12564f8
>[32m[  239.438552] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9694a88
>[32m[  239.438553] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [CRTC:36:pipe A]
>[32m[  239.438555] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88021212fc28
>[32m[  239.438558] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12564f8
>[32m[  239.438588] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128eb538 state to ffff8801f12564f8
>[32m[  239.438592] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128e9978 state to ffff8801f12564f8
>[32m[  239.438593] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [NOCRTC]
>[32m[  239.438595] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9978
>[32m[  239.438599] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128e9728 state to ffff8801f12564f8
>[32m[  239.438600] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [NOCRTC]
>[32m[  239.438602] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9728
>[32m[  239.438606] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff880212131038 state to ffff8801f12564f8
>[32m[  239.438610] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9696678 state to ffff8801f12564f8
>[32m[  239.438614] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ffdf2e8 state to ffff8801f12564f8
>[32m[  239.438615] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdf2e8 to [NOCRTC]
>[32m[  239.438617] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdf2e8
>[32m[  239.438620] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ffdee48 state to ffff8801f12564f8
>[32m[  239.438622] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdee48 to [NOCRTC]
>[32m[  239.438624] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdee48
>[32m[  239.438627] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802135a3098 state to ffff8801f12564f8
>[32m[  239.438632] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cd288 state to ffff8801f12564f8
>[32m[  239.438633] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [NOCRTC]
>[32m[  239.438635] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd288
>[32m[  239.438638] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cebf8 state to ffff8801f12564f8
>[32m[  239.438640] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [NOCRTC]
>[32m[  239.438642] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cebf8
>[32m[  239.438646] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9692e98 state to ffff8801f12564f8
>[32m[  239.438650] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9692e98
>[32m[  239.438652] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [CRTC:36:pipe A]
>[32m[  239.438654] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802128eb538
>[32m[  239.438656] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12564f8
>[32m[  239.438664] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d41b8 state to ffff8801f12564f8
>[32m[  239.438666] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d41b8 to [CRTC:36:pipe A]
>[32m[  239.438670] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f9696678
>[32m[  239.438672] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [CRTC:46:pipe B]
>[32m[  239.438674] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff880212131038
>[32m[  239.438676] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12564f8
>[32m[  239.438681] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0b8ae8 state to ffff8801f12564f8
>[32m[  239.438684] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0b8ae8 to [NOCRTC]
>[32m[  239.438686] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0b8ae8 to [CRTC:46:pipe B]
>[32m[  239.438690] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9694a88 state to ffff8801f12564f8
>[32m[  239.438692] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9694a88
>[32m[  239.438694] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [NOCRTC]
>[32m[  239.438695] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a3098
>[32m[  239.438697] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f12564f8
>[32m[  239.438700] [0m[drm:drm_atomic_check_only] checking ffff8801f12564f8
>[32m[  239.438703] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  239.438704] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  239.438706] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  239.438710] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  239.438712] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  239.438714] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.438716] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.438718] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  239.438720] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12564f8
>[32m[  239.438724] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12564f8
>[32m[  239.438752] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  239.438774] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  239.438795] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  239.438815] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  239.438835] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  239.438855] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  239.438875] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  239.438894] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  239.438912] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  239.438915] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  239.438933] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  239.438935] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  239.438954] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  239.438972] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  239.438990] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  239.439032] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  239.439062] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  239.439080] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  239.439097] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0
>[32m[  239.439115] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0
>[32m[  239.439132] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0
>[32m[  239.439156] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  239.439176] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  239.439195] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  239.439214] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  239.439233] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  239.439251] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  239.439270] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  239.439288] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  239.439326] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL B
>[32m[  239.439345] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe A
>[32m[  239.439350] [0m[drm:drm_atomic_commit] committing ffff8801f12564f8
>[32m[  239.439415] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  239.439433] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  239.439452] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  239.439470] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.439493] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  239.439523] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  239.440175] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  239.440356] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  239.440385] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  239.440405] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  239.440430] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  239.440458] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  239.440474] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  239.440497] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 1, on? 0) for crtc 36
>[32m[  239.440516] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  239.475255] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  239.475281] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  239.475320] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  239.475336] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12564f8
>[32m[  239.475377] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12564f8
>[32m[  239.479379] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  239.487276] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  239.487284] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cf2e8 state to ffff8801f12574e8
>[32m[  239.487291] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020ec9d3d8 state to ffff8801f12574e8
>[32m[  239.487296] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111ccde8 state to ffff8801f12574e8
>[32m[  239.487298] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [NOCRTC]
>[32m[  239.487300] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccde8
>[32m[  239.487305] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cc6f8 state to ffff8801f12574e8
>[32m[  239.487307] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  239.487309] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  239.487314] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cee48 state to ffff8801f12574e8
>[32m[  239.487319] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff88020ec9c138 state to ffff8801f12574e8
>[32m[  239.487324] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cfc28 state to ffff8801f12574e8
>[32m[  239.487326] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cfc28 to [NOCRTC]
>[32m[  239.487328] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cfc28
>[32m[  239.487332] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cf9d8 state to ffff8801f12574e8
>[32m[  239.487334] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  239.487336] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  239.487341] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cd4d8 state to ffff8801f12574e8
>[32m[  239.487345] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cdbc8 state to ffff8801f12574e8
>[32m[  239.487347] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cdbc8 to [NOCRTC]
>[32m[  239.487349] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cdbc8
>[32m[  239.487354] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ee529a8 state to ffff8801f12574e8
>[32m[  239.487356] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee529a8 to [NOCRTC]
>[32m[  239.487358] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee529a8
>[32m[  239.487365] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff88020ec9d3d8
>[32m[  239.487367] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [CRTC:36:pipe A]
>[32m[  239.487369] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802111cf2e8
>[32m[  239.487372] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  239.487404] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ee529a8 state to ffff8801f12574e8
>[32m[  239.487409] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802144bc138 state to ffff8801f12574e8
>[32m[  239.487414] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ee52e48 state to ffff8801f12574e8
>[32m[  239.487416] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [NOCRTC]
>[32m[  239.487418] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee52e48
>[32m[  239.487420] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  239.487432] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ee52e48 state to ffff8801f12574e8
>[32m[  239.487437] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1269bf8 state to ffff8801f12574e8
>[32m[  239.487442] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ee51978 state to ffff8801f12574e8
>[32m[  239.487444] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee51978 to [NOCRTC]
>[32m[  239.487446] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee51978
>[32m[  239.487450] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ee529a8 state to ffff8801f12574e8
>[32m[  239.487452] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee529a8 to [NOCRTC]
>[32m[  239.487454] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee529a8
>[32m[  239.487459] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802129462b8 state to ffff8801f12574e8
>[32m[  239.487464] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126a548 state to ffff8801f12574e8
>[32m[  239.487468] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9530008 state to ffff8801f12574e8
>[32m[  239.487471] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [NOCRTC]
>[32m[  239.487473] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530008
>[32m[  239.487477] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f95306f8 state to ffff8801f12574e8
>[32m[  239.487479] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [NOCRTC]
>[32m[  239.487481] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95306f8
>[32m[  239.487486] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f9532758 state to ffff8801f12574e8
>[32m[  239.487490] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f95332e8 state to ffff8801f12574e8
>[32m[  239.487492] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [NOCRTC]
>[32m[  239.487494] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95332e8
>[32m[  239.487499] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9530258 state to ffff8801f12574e8
>[32m[  239.487501] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [NOCRTC]
>[32m[  239.487503] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530258
>[32m[  239.487508] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1269bf8
>[32m[  239.487511] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [CRTC:36:pipe A]
>[32m[  239.487513] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ee52e48
>[32m[  239.487515] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  239.487546] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9530258 state to ffff8801f12574e8
>[32m[  239.487551] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126a548 state to ffff8801f12574e8
>[32m[  239.487556] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9533c28 state to ffff8801f12574e8
>[32m[  239.487558] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533c28 to [NOCRTC]
>[32m[  239.487560] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533c28
>[32m[  239.487564] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f95332e8 state to ffff8801f12574e8
>[32m[  239.487566] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [NOCRTC]
>[32m[  239.487568] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95332e8
>[32m[  239.487573] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9530948 state to ffff8801f12574e8
>[32m[  239.487578] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126b7e8 state to ffff8801f12574e8
>[32m[  239.487582] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9532758 state to ffff8801f12574e8
>[32m[  239.487584] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [NOCRTC]
>[32m[  239.487587] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532758
>[32m[  239.487591] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9531288 state to ffff8801f12574e8
>[32m[  239.487593] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [NOCRTC]
>[32m[  239.487595] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531288
>[32m[  239.487599] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f95306f8 state to ffff8801f12574e8
>[32m[  239.487604] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f95339d8 state to ffff8801f12574e8
>[32m[  239.487606] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  239.487608] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  239.487612] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9530008 state to ffff8801f12574e8
>[32m[  239.487614] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [NOCRTC]
>[32m[  239.487616] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530008
>[32m[  239.487621] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126a548
>[32m[  239.487623] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [CRTC:36:pipe A]
>[32m[  239.487626] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9530258
>[32m[  239.487628] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  239.487637] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d5cb8 state to ffff8801f12574e8
>[32m[  239.487640] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d5cb8 to [NOCRTC]
>[32m[  239.487643] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d5cb8 to [CRTC:36:pipe A]
>[32m[  239.487648] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126b7e8
>[32m[  239.487650] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [CRTC:46:pipe B]
>[32m[  239.487652] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9530948
>[32m[  239.487655] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  239.487661] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788748 state to ffff8801f12574e8
>[32m[  239.487663] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788748 to [NOCRTC]
>[32m[  239.487666] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788748 to [CRTC:46:pipe B]
>[32m[  239.487671] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff8801f12574e8
>[32m[  239.487673] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f1269bf8
>[32m[  239.487675] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [NOCRTC]
>[32m[  239.487678] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95306f8
>[32m[  239.487680] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f12574e8
>[32m[  239.487683] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  239.487689] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  239.487692] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  239.487694] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.487697] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.487727] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  239.487750] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  239.487773] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  239.487794] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  239.487801] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  239.494782] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  239.494829] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  239.531074] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  239.531170] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  239.547096] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  239.547132] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  239.547159] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  239.547180] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  239.585493] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  239.585566] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  239.585569] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  239.585572] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  239.585574] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  239.585576] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  239.585578] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  239.585580] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  239.585582] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  239.585584] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  239.585586] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  239.585588] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  239.585590] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  239.585592] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  239.585701] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  239.585733] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  239.660836] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  239.660859] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  239.662917] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  239.662924] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  239.662927] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  239.662943] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  239.663227] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  239.663230] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  239.663232] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  239.663371] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  239.663375] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  239.663377] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  239.663379] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  239.663381] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  239.663383] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  239.663385] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  239.663387] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  239.663389] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  239.663391] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  239.663393] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  239.663395] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  239.663398] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  239.663400] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  239.663402] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  239.663404] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  239.663406] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  239.663408] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  239.663410] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  239.663565] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255a58
>[32m[  239.663574] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f978ccb8 state to ffff8801f1255a58
>[32m[  239.663580] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121c138 state to ffff8801f1255a58
>[32m[  239.663583] [0m[drm:drm_atomic_check_only] checking ffff8801f1255a58
>[32m[  239.663588] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.663591] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  239.663597] [0m[drm:drm_atomic_commit] committing ffff8801f1255a58
>[32m[  239.678120] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255a58
>[32m[  239.678134] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255a58
>[32m[  239.678162] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  239.678188] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  239.680769] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.683325] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.685880] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.688435] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.690990] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.693572] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.696133] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.698686] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.701248] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.703802] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.706356] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.708907] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.711460] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.714023] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.716567] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.719105] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.721636] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.724169] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.726696] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.729228] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.731760] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.734287] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.736814] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.739338] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.741865] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.744395] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.746922] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.749450] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.751976] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.754525] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.757101] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.759658] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  239.759667] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  239.759670] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  239.759800] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255a58
>[32m[  239.759809] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff880211e0d3f8 state to ffff8801f1255a58
>[32m[  239.759811] [0m[drm:drm_atomic_check_only] checking ffff8801f1255a58
>[32m[  239.759814] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  239.759817] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  239.759820] [0m[drm:drm_atomic_commit] committing ffff8801f1255a58
>[32m[  239.759832] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255a58
>[32m[  239.759844] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255a58
>[32m[  239.759918] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest atomic-pipe-B-tiling-x
>[32m[  239.760448] [0m[drm:drm_mode_addfb2] [FB:98]
>[32m[  239.767103] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255a58
>[32m[  239.767113] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cf2e8 state to ffff8801f1255a58
>[32m[  239.767119] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121d3d8 state to ffff8801f1255a58
>[32m[  239.767122] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf2e8 to [NOCRTC]
>[32m[  239.767125] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf2e8
>[32m[  239.767131] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cd288 state to ffff8801f1255a58
>[32m[  239.767133] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd288 to [NOCRTC]
>[32m[  239.767136] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd288
>[32m[  239.767141] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cc258 state to ffff8801f1255a58
>[32m[  239.767143] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc258 to [NOCRTC]
>[32m[  239.767146] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc258
>[32m[  239.767150] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f121d3d8
>[32m[  239.767157] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5ce508 state to ffff8801f1255a58
>[32m[  239.767160] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255a58
>[32m[  239.767177] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5ce508 state to ffff8801f1255a58
>[32m[  239.767181] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121d3d8 state to ffff8801f1255a58
>[32m[  239.767183] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [NOCRTC]
>[32m[  239.767186] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce508
>[32m[  239.767191] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cde18 state to ffff8801f1255a58
>[32m[  239.767193] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cde18 to [NOCRTC]
>[32m[  239.767196] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cde18
>[32m[  239.767199] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255a58
>[32m[  239.767210] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cde18 state to ffff8801f1255a58
>[32m[  239.767215] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121d3d8 state to ffff8801f1255a58
>[32m[  239.767217] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cde18 to [NOCRTC]
>[32m[  239.767220] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cde18
>[32m[  239.767225] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cd4d8 state to ffff8801f1255a58
>[32m[  239.767227] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [NOCRTC]
>[32m[  239.767229] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd4d8
>[32m[  239.767235] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5ce508 state to ffff8801f1255a58
>[32m[  239.767237] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [NOCRTC]
>[32m[  239.767239] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce508
>[32m[  239.767242] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f121d3d8
>[32m[  239.767248] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5ccb98 state to ffff8801f1255a58
>[32m[  239.767253] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12192a8 state to ffff8801f1255a58
>[32m[  239.767255] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ccb98 to [CRTC:46:pipe B]
>[32m[  239.767258] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:98] for plane state ffff8801fb5ccb98
>[32m[  239.767267] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cc258 state to ffff8801f1255a58
>[32m[  239.767270] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc258 to [NOCRTC]
>[32m[  239.767272] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc258
>[32m[  239.767277] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cc6f8 state to ffff8801f1255a58
>[32m[  239.767279] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc6f8 to [NOCRTC]
>[32m[  239.767282] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc6f8
>[32m[  239.767286] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12192a8
>[32m[  239.767291] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cd288 state to ffff8801f1255a58
>[32m[  239.767293] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd288 to [NOCRTC]
>[32m[  239.767296] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd288
>[32m[  239.767301] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cdbc8 state to ffff8801f1255a58
>[32m[  239.767303] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [NOCRTC]
>[32m[  239.767306] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cdbc8
>[32m[  239.767311] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cf2e8 state to ffff8801f1255a58
>[32m[  239.767313] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf2e8 to [NOCRTC]
>[32m[  239.767315] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf2e8
>[32m[  239.767319] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255a58
>[32m[  239.767343] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cf2e8 state to ffff8801f1255a58
>[32m[  239.767348] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12192a8 state to ffff8801f1255a58
>[32m[  239.767350] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf2e8 to [NOCRTC]
>[32m[  239.767353] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf2e8
>[32m[  239.767358] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cf098 state to ffff8801f1255a58
>[32m[  239.767360] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [NOCRTC]
>[32m[  239.767362] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf098
>[32m[  239.767368] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cdbc8 state to ffff8801f1255a58
>[32m[  239.767370] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [NOCRTC]
>[32m[  239.767372] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cdbc8
>[32m[  239.767375] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f12192a8
>[32m[  239.767381] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cd978 state to ffff8801f1255a58
>[32m[  239.767386] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1218008 state to ffff8801f1255a58
>[32m[  239.767388] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd978 to [CRTC:46:pipe B]
>[32m[  239.767391] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:98] for plane state ffff8801fb5cd978
>[32m[  239.767399] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cd288 state to ffff8801f1255a58
>[32m[  239.767401] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd288 to [NOCRTC]
>[32m[  239.767403] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd288
>[32m[  239.767408] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5ce758 state to ffff8801f1255a58
>[32m[  239.767411] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [NOCRTC]
>[32m[  239.767413] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce758
>[32m[  239.767417] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1218008
>[32m[  239.767422] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cc6f8 state to ffff8801f1255a58
>[32m[  239.767424] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc6f8 to [NOCRTC]
>[32m[  239.767427] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc6f8
>[32m[  239.767432] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5ce2b8 state to ffff8801f1255a58
>[32m[  239.767434] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce2b8 to [NOCRTC]
>[32m[  239.767436] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce2b8
>[32m[  239.767441] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cc258 state to ffff8801f1255a58
>[32m[  239.767443] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc258 to [NOCRTC]
>[32m[  239.767446] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc258
>[32m[  239.767451] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f121d3d8 state to ffff8801f1255a58
>[32m[  239.767459] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d57a8 state to ffff8801f1255a58
>[32m[  239.767462] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d57a8 to [CRTC:46:pipe B]
>[32m[  239.767468] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff8801f1255a58
>[32m[  239.767470] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b93f8 to [NOCRTC]
>[32m[  239.767475] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802128b81d8 state to ffff8801f1255a58
>[32m[  239.767478] [0m[drm:drm_atomic_check_only] checking ffff8801f1255a58
>[32m[  239.767481] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  239.767483] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  239.767485] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  239.767487] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  239.767491] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  239.767494] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  239.767496] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.767498] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  239.767500] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  239.767502] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  239.767504] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: n, active: n
>[32m[  239.767506] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1255a58
>[32m[  239.767510] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  239.767512] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1255a58
>[32m[  239.767516] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1255a58
>[32m[  239.767544] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  239.767566] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  239.767587] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  239.767607] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  239.767628] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  239.767648] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  239.767668] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  239.767687] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  239.767706] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  239.767709] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  239.767727] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  239.767730] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  239.767749] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  239.767767] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  239.767786] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  239.767804] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  239.767824] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  239.767842] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  239.767861] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:96, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  239.767879] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  239.767897] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  239.767920] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb -1
>[32m[  239.767940] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  239.767960] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 98
>[32m[  239.767979] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  239.769973] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  239.770002] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  239.770147] [0m[drm:drm_atomic_commit] committing ffff8801f1255a58
>[32m[  239.772702] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  239.791366] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 1, on? 1) for crtc 36
>[32m[  239.791395] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  239.791639] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  239.812337] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  239.812365] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  239.812598] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  239.812618] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  239.812640] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  239.812660] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  239.812681] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:65:DP-1]
>[32m[  239.812703] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.812725] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  239.812762] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  239.813552] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  239.813735] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  239.813765] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  239.813785] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  239.813810] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  239.813830] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  239.813848] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  239.813872] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  239.813891] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  239.848887] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  239.848919] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  239.848946] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  239.848984] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.849251] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255a58
>[32m[  239.849292] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255a58
>[32m[  239.882518] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  239.882668] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  239.887340] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  239.898788] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  239.898798] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cd4d8 state to ffff8801f1250aa8
>[32m[  239.898804] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f95e2548 state to ffff8801f1250aa8
>[32m[  239.898806] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [CRTC:46:pipe B]
>[32m[  239.898810] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801fb5cd4d8
>[32m[  239.898819] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cde18 state to ffff8801f1250aa8
>[32m[  239.898822] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cde18 to [CRTC:46:pipe B]
>[32m[  239.898825] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff8801fb5cde18
>[32m[  239.898834] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212c6f8 state to ffff8801f1250aa8
>[32m[  239.898836] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [CRTC:46:pipe B]
>[32m[  239.898839] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff88021212c6f8
>[32m[  239.898846] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f95e2548
>[32m[  239.898855] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d5958 state to ffff8801f1250aa8
>[32m[  239.898860] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  239.898866] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  239.898868] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  239.898898] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 100
>[32m[  239.898921] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  239.898943] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 66
>[32m[  239.898963] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  239.898983] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 82
>[32m[  239.899002] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  239.899584] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  239.915361] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  239.915383] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  239.915756] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  239.915763] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b95c8 state to ffff8801f1250aa8
>[32m[  239.915766] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  239.915769] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.915771] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  239.915774] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  239.915786] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  239.915799] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  239.915886] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  239.921793] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  239.921801] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212c258 state to ffff8801f1250aa8
>[32m[  239.921807] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126a548 state to ffff8801f1250aa8
>[32m[  239.921810] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c258 to [CRTC:46:pipe B]
>[32m[  239.921813] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff88021212c258
>[32m[  239.921822] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212de18 state to ffff8801f1250aa8
>[32m[  239.921824] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  239.921827] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  239.921835] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128e9728 state to ffff8801f1250aa8
>[32m[  239.921837] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [NOCRTC]
>[32m[  239.921840] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9728
>[32m[  239.921847] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126a548
>[32m[  239.921851] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  239.921866] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128e9728 state to ffff8801f1250aa8
>[32m[  239.921871] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126a548 state to ffff8801f1250aa8
>[32m[  239.921873] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [CRTC:46:pipe B]
>[32m[  239.921876] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8802128e9728
>[32m[  239.921884] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128e9978 state to ffff8801f1250aa8
>[32m[  239.921886] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [NOCRTC]
>[32m[  239.921888] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9978
>[32m[  239.921894] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  239.921905] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128e9978 state to ffff8801f1250aa8
>[32m[  239.921910] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126a548 state to ffff8801f1250aa8
>[32m[  239.921912] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [CRTC:46:pipe B]
>[32m[  239.921915] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8802128e9978
>[32m[  239.921923] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128eb538 state to ffff8801f1250aa8
>[32m[  239.921925] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [NOCRTC]
>[32m[  239.921928] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb538
>[32m[  239.921935] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128e9728 state to ffff8801f1250aa8
>[32m[  239.921937] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [NOCRTC]
>[32m[  239.921940] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9728
>[32m[  239.921946] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126a548
>[32m[  239.921954] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d57a8 state to ffff8801f1250aa8
>[32m[  239.921956] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d57a8 to [NOCRTC]
>[32m[  239.921962] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b9b38 state to ffff8801f1250aa8
>[32m[  239.921964] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b9b38 to [CRTC:46:pipe B]
>[32m[  239.921966] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  239.921969] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  239.921973] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  239.921975] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  239.921977] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  239.921980] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:46:pipe B]
>[32m[  239.921982] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  239.921985] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250aa8
>[32m[  239.922661] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250aa8
>[32m[  239.922702] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  239.922724] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  239.922747] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  239.922788] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  239.922810] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  239.922829] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  239.922850] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  239.922870] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  239.922889] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  239.922908] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  239.922927] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  239.922938] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  239.922957] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  239.922959] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  239.922978] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  239.922997] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  239.923332] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  239.923350] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  239.923372] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  239.923402] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  239.923422] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  239.923440] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  239.923458] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:82, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  239.923482] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 99
>[32m[  239.923518] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  239.923538] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  239.923557] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  239.923577] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  239.923595] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  239.923633] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  239.923652] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  239.923664] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  239.926159] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  239.948844] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  239.948872] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  239.949108] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  239.949133] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  239.949154] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  239.949191] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  239.949213] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.949236] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  239.949267] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  239.949918] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  239.950174] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  239.950204] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  239.950233] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  239.950259] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  239.950278] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  239.950295] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  239.950318] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  239.950346] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  239.985165] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  239.985196] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  239.985234] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  239.985247] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  239.985265] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.018667] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.018675] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b83a8 state to ffff8801f1250aa8
>[32m[  240.018681] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121dd28 state to ffff8801f1250aa8
>[32m[  240.018683] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.018688] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.018691] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.018696] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.035143] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.035154] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.035407] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  240.035541] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  240.039701] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  240.051910] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.051920] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802121329a8 state to ffff8801f1250aa8
>[32m[  240.051926] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1219bf8 state to ffff8801f1250aa8
>[32m[  240.051929] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [CRTC:46:pipe B]
>[32m[  240.051933] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802121329a8
>[32m[  240.051942] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff880212131038 state to ffff8801f1250aa8
>[32m[  240.051944] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [CRTC:46:pipe B]
>[32m[  240.051947] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff880212131038
>[32m[  240.051955] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802121314d8 state to ffff8801f1250aa8
>[32m[  240.051958] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [CRTC:46:pipe B]
>[32m[  240.051960] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8802121314d8
>[32m[  240.051968] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1219bf8
>[32m[  240.051977] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b95c8 state to ffff8801f1250aa8
>[32m[  240.051981] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.051987] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.052264] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.052298] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 109
>[32m[  240.052329] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  240.052352] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 102
>[32m[  240.052372] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  240.052392] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 108
>[32m[  240.052433] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  240.052439] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.068477] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.068499] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.068697] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.068704] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8ae8 state to ffff8801f1250aa8
>[32m[  240.068710] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9692548 state to ffff8801f1250aa8
>[32m[  240.068712] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.068717] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.068720] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.068724] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.085129] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.085141] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.085402] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  240.091794] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.091803] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cf098 state to ffff8801f1250aa8
>[32m[  240.091809] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9688008 state to ffff8801f1250aa8
>[32m[  240.091812] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [CRTC:46:pipe B]
>[32m[  240.091815] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:104] for plane state ffff8802111cf098
>[32m[  240.091825] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cf2e8 state to ffff8801f1250aa8
>[32m[  240.091827] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [NOCRTC]
>[32m[  240.091830] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf2e8
>[32m[  240.091838] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111ccb98 state to ffff8801f1250aa8
>[32m[  240.091840] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [NOCRTC]
>[32m[  240.091843] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccb98
>[32m[  240.091850] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9688008
>[32m[  240.091854] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.091868] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111ccb98 state to ffff8801f1250aa8
>[32m[  240.091873] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9688008 state to ffff8801f1250aa8
>[32m[  240.091876] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [CRTC:46:pipe B]
>[32m[  240.091878] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:104] for plane state ffff8802111ccb98
>[32m[  240.091886] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cc948 state to ffff8801f1250aa8
>[32m[  240.091889] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [NOCRTC]
>[32m[  240.091891] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc948
>[32m[  240.091897] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.091908] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cc948 state to ffff8801f1250aa8
>[32m[  240.091913] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9688008 state to ffff8801f1250aa8
>[32m[  240.091915] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [CRTC:46:pipe B]
>[32m[  240.091918] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:104] for plane state ffff8802111cc948
>[32m[  240.091926] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cc4a8 state to ffff8801f1250aa8
>[32m[  240.091928] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [NOCRTC]
>[32m[  240.091931] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc4a8
>[32m[  240.091938] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111ccb98 state to ffff8801f1250aa8
>[32m[  240.091941] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [NOCRTC]
>[32m[  240.091943] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccb98
>[32m[  240.091949] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9688008
>[32m[  240.091957] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d5958 state to ffff8801f1250aa8
>[32m[  240.091960] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d5958 to [CRTC:46:pipe B]
>[32m[  240.091965] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff8801f1250aa8
>[32m[  240.091968] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b93f8 to [NOCRTC]
>[32m[  240.091970] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.091973] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  240.091977] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  240.091980] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:46:pipe B]
>[32m[  240.091982] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.091983] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  240.091986] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  240.092641] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250aa8
>[32m[  240.092646] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250aa8
>[32m[  240.092675] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  240.092698] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  240.092727] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  240.092747] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  240.092767] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  240.092787] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  240.092807] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  240.092826] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  240.092845] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  240.092848] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  240.092866] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  240.092869] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  240.092888] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  240.092906] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  240.092925] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  240.092943] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  240.092963] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  240.092981] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  240.093000] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  240.093370] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:102, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  240.093389] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:108, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  240.093414] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 104
>[32m[  240.093443] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  240.093463] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  240.093499] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  240.093519] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  240.093537] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  240.093575] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  240.093595] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  240.093599] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.096244] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  240.118936] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  240.118964] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  240.119207] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  240.119229] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  240.119252] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  240.119280] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  240.119302] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.119325] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  240.119356] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  240.119980] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  240.120338] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  240.120369] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  240.120389] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  240.120415] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  240.120442] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  240.120460] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  240.120484] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  240.120504] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  240.155242] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  240.155273] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  240.155312] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.155324] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.155341] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.188892] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  240.189109] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  240.193704] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  240.205147] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.205157] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111ccde8 state to ffff8801f1250aa8
>[32m[  240.205163] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1268008 state to ffff8801f1250aa8
>[32m[  240.205165] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [CRTC:46:pipe B]
>[32m[  240.205169] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802111ccde8
>[32m[  240.205178] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cd4d8 state to ffff8801f1250aa8
>[32m[  240.205180] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd4d8 to [CRTC:46:pipe B]
>[32m[  240.205183] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8802111cd4d8
>[32m[  240.205191] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cc6f8 state to ffff8801f1250aa8
>[32m[  240.205194] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [CRTC:46:pipe B]
>[32m[  240.205197] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff8802111cc6f8
>[32m[  240.205204] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1268008
>[32m[  240.205213] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d41b8 state to ffff8801f1250aa8
>[32m[  240.205217] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.205223] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  240.205226] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  240.205256] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 113
>[32m[  240.205278] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  240.205301] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 110
>[32m[  240.205321] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  240.205341] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 112
>[32m[  240.205360] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  240.205365] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.221719] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.221741] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.222253] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.222261] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b9b38 state to ffff8801f1250aa8
>[32m[  240.222263] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.222266] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.222268] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  240.222271] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.222283] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.222315] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.222362] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  240.228392] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.228402] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9530008 state to ffff8801f1250aa8
>[32m[  240.228408] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9688008 state to ffff8801f1250aa8
>[32m[  240.228411] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [CRTC:46:pipe B]
>[32m[  240.228414] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff8801f9530008
>[32m[  240.228423] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9531038 state to ffff8801f1250aa8
>[32m[  240.228426] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [NOCRTC]
>[32m[  240.228428] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531038
>[32m[  240.228434] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.228449] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9531038 state to ffff8801f1250aa8
>[32m[  240.228453] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9688008 state to ffff8801f1250aa8
>[32m[  240.228455] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [CRTC:46:pipe B]
>[32m[  240.228458] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff8801f9531038
>[32m[  240.228466] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9531728 state to ffff8801f1250aa8
>[32m[  240.228469] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [NOCRTC]
>[32m[  240.228471] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531728
>[32m[  240.228479] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9530008 state to ffff8801f1250aa8
>[32m[  240.228481] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [NOCRTC]
>[32m[  240.228484] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530008
>[32m[  240.228491] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f9688008
>[32m[  240.228494] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.228508] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9530008 state to ffff8801f1250aa8
>[32m[  240.228513] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9688008 state to ffff8801f1250aa8
>[32m[  240.228515] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [CRTC:46:pipe B]
>[32m[  240.228518] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff8801f9530008
>[32m[  240.228526] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f95339d8 state to ffff8801f1250aa8
>[32m[  240.228528] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  240.228530] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  240.228538] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9531728 state to ffff8801f1250aa8
>[32m[  240.228540] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [NOCRTC]
>[32m[  240.228543] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531728
>[32m[  240.228549] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f9688008
>[32m[  240.228557] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d5958 state to ffff8801f1250aa8
>[32m[  240.228559] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d5958 to [NOCRTC]
>[32m[  240.228565] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8ae8 state to ffff8801f1250aa8
>[32m[  240.228567] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8ae8 to [CRTC:46:pipe B]
>[32m[  240.228569] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.228572] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  240.228576] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  240.228578] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  240.228580] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.228583] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:46:pipe B]
>[32m[  240.228585] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  240.228588] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250aa8
>[32m[  240.228592] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250aa8
>[32m[  240.228620] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  240.228642] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  240.228666] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  240.228686] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  240.228707] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  240.228728] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  240.228748] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  240.228768] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  240.228788] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  240.228807] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  240.228825] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  240.228828] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  240.228847] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  240.228849] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  240.228868] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  240.228886] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  240.228904] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  240.228922] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  240.228942] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  240.228961] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  240.228980] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:113, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  240.228998] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:110, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  240.230023] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:112, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  240.230051] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 111
>[32m[  240.230073] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  240.230095] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  240.230115] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  240.230136] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  240.230156] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  240.230197] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  240.230218] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  240.230224] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.232658] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  240.256642] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  240.256669] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  240.256902] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  240.256925] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  240.256944] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  240.256964] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  240.256986] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.257169] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  240.257202] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  240.257859] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  240.258100] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  240.258132] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  240.258153] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  240.258181] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  240.258202] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  240.258221] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  240.258246] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  240.258267] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  240.293107] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  240.293138] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  240.293178] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.293190] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.293206] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.326611] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.326620] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b83a8 state to ffff8801f1250aa8
>[32m[  240.326625] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1218008 state to ffff8801f1250aa8
>[32m[  240.326627] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.326632] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.326635] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.326639] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.343085] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.343097] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.343349] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  240.343485] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  240.347628] [0m[drm:drm_mode_addfb2] [FB:117]
>[32m[  240.359844] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.359853] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f95304a8 state to ffff8801f1250aa8
>[32m[  240.359859] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121dd28 state to ffff8801f1250aa8
>[32m[  240.359862] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [CRTC:46:pipe B]
>[32m[  240.359865] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801f95304a8
>[32m[  240.359875] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9530948 state to ffff8801f1250aa8
>[32m[  240.359877] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [CRTC:46:pipe B]
>[32m[  240.359880] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801f9530948
>[32m[  240.359888] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f95314d8 state to ffff8801f1250aa8
>[32m[  240.359890] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95314d8 to [CRTC:46:pipe B]
>[32m[  240.359893] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801f95314d8
>[32m[  240.359900] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121dd28
>[32m[  240.359909] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff8801f1250aa8
>[32m[  240.359913] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.359919] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.359921] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.359951] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 117
>[32m[  240.359974] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  240.359995] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 114
>[32m[  240.360363] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  240.360386] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 116
>[32m[  240.360408] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  240.360413] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.376418] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.376440] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.376640] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  240.376647] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b95c8 state to ffff8801f1250aa8
>[32m[  240.376653] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff88020ec9d3d8 state to ffff8801f1250aa8
>[32m[  240.376655] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  240.376660] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.376662] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.376667] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  240.393070] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  240.393082] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  240.393221] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  240.403374] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  240.403380] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95339d8 state to ffff8801f1256a48
>[32m[  240.403385] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec51728 state to ffff8801f1256a48
>[32m[  240.403387] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec51728 to [NOCRTC]
>[32m[  240.403389] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec51728
>[32m[  240.403394] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e0794d8 state to ffff8801f1256a48
>[32m[  240.403395] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e0794d8 to [NOCRTC]
>[32m[  240.403397] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e0794d8
>[32m[  240.403401] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020e07a508 state to ffff8801f1256a48
>[32m[  240.403406] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f968ae98 state to ffff8801f1256a48
>[32m[  240.403410] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e07b788 state to ffff8801f1256a48
>[32m[  240.403412] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b788 to [NOCRTC]
>[32m[  240.403413] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b788
>[32m[  240.403417] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020e07a9a8 state to ffff8801f1256a48
>[32m[  240.403419] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [NOCRTC]
>[32m[  240.403420] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a9a8
>[32m[  240.403424] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020e078258 state to ffff8801f1256a48
>[32m[  240.403429] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020e07b2e8 state to ffff8801f1256a48
>[32m[  240.403430] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b2e8 to [NOCRTC]
>[32m[  240.403432] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b2e8
>[32m[  240.403437] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2e758 state to ffff8801f1256a48
>[32m[  240.403439] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  240.403440] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  240.403445] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802106c0958 state to ffff8801f1256a48
>[32m[  240.403451] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8802106c0958
>[32m[  240.403453] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [CRTC:36:pipe A]
>[32m[  240.403455] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f95339d8
>[32m[  240.403457] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  240.403465] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d57a8 state to ffff8801f1256a48
>[32m[  240.403467] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d57a8 to [CRTC:36:pipe A]
>[32m[  240.403471] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f968ae98
>[32m[  240.403473] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [CRTC:46:pipe B]
>[32m[  240.403475] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020e07a508
>[32m[  240.403477] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256a48
>[32m[  240.403483] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801fd72e578 state to ffff8801f1256a48
>[32m[  240.403485] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd72e578 to [NOCRTC]
>[32m[  240.403487] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd72e578 to [CRTC:46:pipe B]
>[32m[  240.403492] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8802106c6678 state to ffff8801f1256a48
>[32m[  240.403493] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8802106c6678
>[32m[  240.403495] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [NOCRTC]
>[32m[  240.403496] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078258
>[32m[  240.403498] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1256a48
>[32m[  240.403501] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  240.403504] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  240.403506] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  240.403507] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  240.403511] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  240.403513] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  240.403515] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.403517] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.403519] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  240.403521] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  240.403525] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  240.403553] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  240.403574] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  240.403595] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  240.403615] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  240.403635] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  240.403655] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  240.403674] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  240.403693] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  240.403712] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  240.403714] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  240.403732] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  240.403734] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  240.403753] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  240.403771] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  240.403790] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  240.403807] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  240.403827] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  240.403845] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  240.403863] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0
>[32m[  240.403881] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0
>[32m[  240.403898] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0
>[32m[  240.403921] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  240.403941] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  240.403960] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  240.403979] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  240.403998] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  240.404039] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  240.404066] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  240.404084] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  240.404122] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL B
>[32m[  240.404141] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe A
>[32m[  240.404146] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  240.404201] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  240.404219] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  240.404237] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  240.404256] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.404279] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  240.404310] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  240.404941] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  240.405123] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  240.405151] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  240.405170] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  240.405195] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  240.405214] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  240.405231] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  240.405254] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 1, on? 0) for crtc 36
>[32m[  240.405273] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  240.440035] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  240.440069] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  240.440109] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  240.440125] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  240.440167] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  240.444153] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  240.451234] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251a98
>[32m[  240.451242] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2e508 state to ffff8801f1251a98
>[32m[  240.451248] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126ca88 state to ffff8801f1251a98
>[32m[  240.451253] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2d038 state to ffff8801f1251a98
>[32m[  240.451256] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  240.451258] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  240.451263] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2d288 state to ffff8801f1251a98
>[32m[  240.451265] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d288 to [NOCRTC]
>[32m[  240.451267] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d288
>[32m[  240.451271] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2c4a8 state to ffff8801f1251a98
>[32m[  240.451285] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126e678 state to ffff8801f1251a98
>[32m[  240.451290] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2f098 state to ffff8801f1251a98
>[32m[  240.451292] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f098 to [NOCRTC]
>[32m[  240.451294] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f098
>[32m[  240.451298] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2ee48 state to ffff8801f1251a98
>[32m[  240.451300] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2ee48 to [NOCRTC]
>[32m[  240.451302] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2ee48
>[32m[  240.451306] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2c008 state to ffff8801f1251a98
>[32m[  240.451311] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2f538 state to ffff8801f1251a98
>[32m[  240.451313] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [NOCRTC]
>[32m[  240.451315] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f538
>[32m[  240.451319] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2de18 state to ffff8801f1251a98
>[32m[  240.451321] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2de18 to [NOCRTC]
>[32m[  240.451323] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2de18
>[32m[  240.451330] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126ca88
>[32m[  240.451332] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e508 to [CRTC:36:pipe A]
>[32m[  240.451334] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ec2e508
>[32m[  240.451337] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251a98
>[32m[  240.451345] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97d5cb8 state to ffff8801f1251a98
>[32m[  240.451349] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d5cb8 to [NOCRTC]
>[32m[  240.451351] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97d5cb8 to [CRTC:36:pipe A]
>[32m[  240.451356] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126e678
>[32m[  240.451358] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [CRTC:46:pipe B]
>[32m[  240.451361] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ec2c4a8
>[32m[  240.451363] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1251a98
>[32m[  240.451369] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880212b24ae8 state to ffff8801f1251a98
>[32m[  240.451371] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880212b24ae8 to [NOCRTC]
>[32m[  240.451374] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880212b24ae8 to [CRTC:46:pipe B]
>[32m[  240.451379] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126b7e8 state to ffff8801f1251a98
>[32m[  240.451381] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f126b7e8
>[32m[  240.451383] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  240.451385] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  240.451388] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1251a98
>[32m[  240.451391] [0m[drm:drm_atomic_check_only] checking ffff8801f1251a98
>[32m[  240.451396] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  240.451399] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  240.451401] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.451404] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.451432] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  240.451455] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  240.451477] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  240.451498] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  240.451504] [0m[drm:drm_atomic_commit] committing ffff8801f1251a98
>[32m[  240.459725] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251a98
>[32m[  240.459777] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251a98
>[32m[  240.495592] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  240.495691] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  240.514138] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  240.514173] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  240.514201] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  240.514222] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  240.552458] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  240.552531] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  240.552535] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  240.552537] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  240.552539] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  240.552541] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  240.552543] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  240.552545] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  240.552547] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  240.552549] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  240.552551] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  240.552554] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  240.552556] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  240.552558] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  240.552671] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  240.552702] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  240.627453] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  240.627475] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  240.629534] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  240.629540] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  240.629544] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  240.629560] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  240.629671] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  240.629674] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  240.629676] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  240.629804] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  240.629808] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  240.629810] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  240.629813] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  240.629815] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  240.629817] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  240.629819] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  240.629821] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  240.629823] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  240.629825] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  240.629827] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  240.629829] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  240.629831] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  240.629833] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  240.629835] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  240.629837] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  240.629839] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  240.629841] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  240.629843] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  240.629985] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  240.630500] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048748 state to ffff8801f1253528
>[32m[  240.630506] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12192a8 state to ffff8801f1253528
>[32m[  240.630509] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  240.630516] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.630519] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  240.630526] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  240.643073] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  240.643086] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  240.643112] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  240.643138] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  240.645714] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.648271] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.650825] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.653378] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.655932] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.658485] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.661092] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.663643] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.666194] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.668750] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.671300] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.673849] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.676400] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.678947] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.681498] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.684080] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.686631] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.689180] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.691731] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.694280] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.696828] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.699376] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.701926] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.704476] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.707131] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.709684] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.712237] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.714798] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.717349] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.719899] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.722451] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.724995] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  240.725014] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  240.725018] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  240.725163] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  240.725171] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff88020e048ae8 state to ffff8801f1253528
>[32m[  240.725174] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  240.725177] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  240.725179] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  240.725182] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  240.725194] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  240.725206] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  240.725280] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest atomic-pipe-C-tiling-none
>[32m[  240.725535] [0m[drm:drm_mode_addfb2] [FB:97]
>[32m[  240.732278] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  240.732288] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128e9728 state to ffff8801f1253528
>[32m[  240.732294] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126dd28 state to ffff8801f1253528
>[32m[  240.732297] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [NOCRTC]
>[32m[  240.732300] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9728
>[32m[  240.732305] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128eb098 state to ffff8801f1253528
>[32m[  240.732308] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb098 to [NOCRTC]
>[32m[  240.732310] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb098
>[32m[  240.732316] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128ea2b8 state to ffff8801f1253528
>[32m[  240.732318] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [NOCRTC]
>[32m[  240.732320] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128ea2b8
>[32m[  240.732324] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f126dd28
>[32m[  240.732330] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128e86f8 state to ffff8801f1253528
>[32m[  240.732335] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126c138 state to ffff8801f1253528
>[32m[  240.732337] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [NOCRTC]
>[32m[  240.732340] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e86f8
>[32m[  240.732345] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128e8258 state to ffff8801f1253528
>[32m[  240.732347] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e8258 to [NOCRTC]
>[32m[  240.732350] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e8258
>[32m[  240.732356] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff880212131978 state to ffff8801f1253528
>[32m[  240.732358] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [NOCRTC]
>[32m[  240.732361] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131978
>[32m[  240.732364] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f126c138
>[32m[  240.732370] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802121329a8 state to ffff8801f1253528
>[32m[  240.732375] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126d3d8 state to ffff8801f1253528
>[32m[  240.732377] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [CRTC:56:pipe C]
>[32m[  240.732380] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8802121329a8
>[32m[  240.732388] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  240.732413] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802121329a8 state to ffff8801f1253528
>[32m[  240.732418] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126d3d8 state to ffff8801f1253528
>[32m[  240.732420] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [NOCRTC]
>[32m[  240.732422] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121329a8
>[32m[  240.732427] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff880212131038 state to ffff8801f1253528
>[32m[  240.732430] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [NOCRTC]
>[32m[  240.732432] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131038
>[32m[  240.732435] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  240.732446] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff880212131038 state to ffff8801f1253528
>[32m[  240.732450] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126d3d8 state to ffff8801f1253528
>[32m[  240.732452] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [NOCRTC]
>[32m[  240.732455] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131038
>[32m[  240.732460] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802121314d8 state to ffff8801f1253528
>[32m[  240.732462] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [NOCRTC]
>[32m[  240.732464] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121314d8
>[32m[  240.732469] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802121329a8 state to ffff8801f1253528
>[32m[  240.732471] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [NOCRTC]
>[32m[  240.732474] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121329a8
>[32m[  240.732477] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f126d3d8
>[32m[  240.732482] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff880212131288 state to ffff8801f1253528
>[32m[  240.732486] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126c138 state to ffff8801f1253528
>[32m[  240.732489] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [NOCRTC]
>[32m[  240.732491] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131288
>[32m[  240.732496] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff880212131978 state to ffff8801f1253528
>[32m[  240.732498] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [NOCRTC]
>[32m[  240.732501] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131978
>[32m[  240.732507] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cebf8 state to ffff8801f1253528
>[32m[  240.732509] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [NOCRTC]
>[32m[  240.732511] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cebf8
>[32m[  240.732514] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f126c138
>[32m[  240.732520] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cc948 state to ffff8801f1253528
>[32m[  240.732525] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126efc8 state to ffff8801f1253528
>[32m[  240.732527] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [CRTC:56:pipe C]
>[32m[  240.732530] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8802111cc948
>[32m[  240.732538] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cee48 state to ffff8801f1253528
>[32m[  240.732540] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cee48 to [NOCRTC]
>[32m[  240.732542] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cee48
>[32m[  240.732545] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  240.732571] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cee48 state to ffff8801f1253528
>[32m[  240.732575] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126efc8 state to ffff8801f1253528
>[32m[  240.732577] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cee48 to [NOCRTC]
>[32m[  240.732580] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cee48
>[32m[  240.732585] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cfc28 state to ffff8801f1253528
>[32m[  240.732587] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cfc28 to [NOCRTC]
>[32m[  240.732590] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cfc28
>[32m[  240.732595] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cc948 state to ffff8801f1253528
>[32m[  240.732597] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [NOCRTC]
>[32m[  240.732599] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc948
>[32m[  240.732602] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f126efc8
>[32m[  240.732608] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cf9d8 state to ffff8801f1253528
>[32m[  240.732612] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126dd28 state to ffff8801f1253528
>[32m[  240.732614] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  240.732617] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  240.732622] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cebf8 state to ffff8801f1253528
>[32m[  240.732624] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [NOCRTC]
>[32m[  240.732626] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cebf8
>[32m[  240.732631] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cd288 state to ffff8801f1253528
>[32m[  240.732633] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [NOCRTC]
>[32m[  240.732636] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd288
>[32m[  240.732639] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f126dd28
>[32m[  240.732644] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cc4a8 state to ffff8801f1253528
>[32m[  240.732649] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126c138 state to ffff8801f1253528
>[32m[  240.732651] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [CRTC:56:pipe C]
>[32m[  240.732654] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8802111cc4a8
>[32m[  240.732661] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cf098 state to ffff8801f1253528
>[32m[  240.732664] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [NOCRTC]
>[32m[  240.732666] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf098
>[32m[  240.732671] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111ccb98 state to ffff8801f1253528
>[32m[  240.732673] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [NOCRTC]
>[32m[  240.732676] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccb98
>[32m[  240.732680] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126c138
>[32m[  240.732688] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997958 state to ffff8801f1253528
>[32m[  240.732690] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997958 to [CRTC:56:pipe C]
>[32m[  240.732696] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff8801f1253528
>[32m[  240.732698] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [NOCRTC]
>[32m[  240.732704] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff88020e0495c8 state to ffff8801f1253528
>[32m[  240.732706] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  240.732709] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  240.732711] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  240.732713] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  240.732715] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  240.732717] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  240.732719] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  240.732721] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  240.732723] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] enable changed
>[32m[  240.732725] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] active changed
>[32m[  240.732728] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  240.732731] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  240.732733] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.732735] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  240.732737] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  240.732739] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  240.732741] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: n, active: n
>[32m[  240.732744] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1253528
>[32m[  240.732747] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: n, active: n
>[32m[  240.732749] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253528
>[32m[  240.732752] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  240.732754] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  240.732759] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  240.732787] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  240.732809] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  240.732831] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  240.732852] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  240.732873] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  240.732893] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  240.732913] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  240.732932] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  240.732951] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  240.732954] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  240.732972] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  240.732974] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  240.732993] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  240.734947] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  240.734980] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  240.735000] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  240.735185] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0x0, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[32m[  240.735205] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  240.735254] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] disabled, scaler_id = 0
>[32m[  240.735275] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] disabled, scaler_id = 0
>[32m[  240.735295] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] disabled, scaler_id = 0
>[32m[  240.735321] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb -1
>[32m[  240.735342] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  240.735364] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb -1
>[32m[  240.735385] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  240.735407] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 97
>[32m[  240.735448] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  240.735492] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  240.735513] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  240.735518] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  240.738288] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  240.756362] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 1, on? 1) for crtc 36
>[32m[  240.756390] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  240.756634] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  240.777330] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  240.777358] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  240.777593] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  240.777614] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  240.777636] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  240.777656] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  240.777678] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:65:DP-1]
>[32m[  240.777699] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.777722] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  240.777762] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  240.778395] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  240.778588] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  240.778618] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  240.778638] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  240.778664] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  240.778683] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  240.778701] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  240.778724] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  240.778744] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  240.813569] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  240.813599] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  240.813628] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  240.813651] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  240.813688] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.813703] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  240.813743] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  240.847222] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  240.847371] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  240.851899] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  240.863472] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  240.863481] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ffdf2e8 state to ffff8801f1252a88
>[32m[  240.863501] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12c0008 state to ffff8801f1252a88
>[32m[  240.863504] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdf2e8 to [CRTC:56:pipe C]
>[32m[  240.863507] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff88020ffdf2e8
>[32m[  240.863517] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ffdc948 state to ffff8801f1252a88
>[32m[  240.863519] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdc948 to [CRTC:56:pipe C]
>[32m[  240.863522] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff88020ffdc948
>[32m[  240.863531] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ffdee48 state to ffff8801f1252a88
>[32m[  240.863533] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdee48 to [CRTC:56:pipe C]
>[32m[  240.863536] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff88020ffdee48
>[32m[  240.863543] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12c0008
>[32m[  240.863551] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f996518 state to ffff8801f1252a88
>[32m[  240.863557] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  240.863562] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  240.863565] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  240.863596] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 100
>[32m[  240.863618] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  240.863641] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 66
>[32m[  240.863661] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  240.863681] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 82
>[32m[  240.863700] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  240.863705] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  240.880043] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  240.880065] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  240.880459] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  240.880466] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048748 state to ffff8801f1252a88
>[32m[  240.880469] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  240.880472] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.880474] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  240.880477] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  240.880489] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  240.880502] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  240.880594] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  240.886517] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  240.886526] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f95304a8 state to ffff8801f1252a88
>[32m[  240.886532] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12c12a8 state to ffff8801f1252a88
>[32m[  240.886535] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [CRTC:56:pipe C]
>[32m[  240.886538] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8801f95304a8
>[32m[  240.886547] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9530948 state to ffff8801f1252a88
>[32m[  240.886550] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [NOCRTC]
>[32m[  240.886552] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530948
>[32m[  240.886560] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9531728 state to ffff8801f1252a88
>[32m[  240.886563] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [NOCRTC]
>[32m[  240.886565] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531728
>[32m[  240.886572] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f12c12a8
>[32m[  240.886580] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997958 state to ffff8801f1252a88
>[32m[  240.886582] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997958 to [NOCRTC]
>[32m[  240.886588] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048ae8 state to ffff8801f1252a88
>[32m[  240.886591] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048ae8 to [CRTC:56:pipe C]
>[32m[  240.886593] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  240.886596] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  240.886600] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  240.886602] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  240.886604] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.886607] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:56:pipe C]
>[32m[  240.886609] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  240.886611] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252a88
>[32m[  240.886616] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252a88
>[32m[  240.886645] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  240.886667] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  240.886691] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  240.886711] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  240.886732] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  240.886738] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12c5d28 state to ffff8801f1252a88
>[32m[  240.886759] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  240.886780] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  240.886800] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  240.886819] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  240.886838] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  240.886857] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  240.886860] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  240.886878] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  240.886881] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  240.886900] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  240.886918] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  240.886937] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  240.886955] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  240.886975] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  240.886993] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  240.887726] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  240.887748] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  240.887768] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:82, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  240.887794] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 99
>[32m[  240.887816] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  240.887837] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  240.887882] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  240.887903] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  240.887924] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  240.887966] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  240.887987] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  240.888276] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  240.890512] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  240.914719] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  240.914746] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  240.914979] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  240.915002] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  240.915143] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  240.915164] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  240.915188] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.915214] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  240.915247] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  240.915891] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  240.916130] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  240.916161] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  240.916183] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  240.916210] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  240.916231] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  240.916251] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  240.916275] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  240.916313] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  240.951133] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  240.951164] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  240.951202] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  240.951216] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  240.951239] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  240.984624] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  240.984633] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049968 state to ffff8801f1252a88
>[32m[  240.984638] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1218958 state to ffff8801f1252a88
>[32m[  240.984641] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  240.984646] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  240.984648] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  240.984653] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.001109] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.001121] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.001369] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  241.001505] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  241.005639] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  241.017874] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.017883] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f9532bf8 state to ffff8801f1252a88
>[32m[  241.017889] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f121ae98 state to ffff8801f1252a88
>[32m[  241.017892] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [CRTC:56:pipe C]
>[32m[  241.017895] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801f9532bf8
>[32m[  241.017905] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f95306f8 state to ffff8801f1252a88
>[32m[  241.017907] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [CRTC:56:pipe C]
>[32m[  241.017910] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8801f95306f8
>[32m[  241.017919] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9531288 state to ffff8801f1252a88
>[32m[  241.017921] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [CRTC:56:pipe C]
>[32m[  241.017924] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801f9531288
>[32m[  241.017931] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121ae98
>[32m[  241.017940] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048748 state to ffff8801f1252a88
>[32m[  241.017945] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.017950] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.017953] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  241.017983] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 109
>[32m[  241.018005] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  241.018367] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 102
>[32m[  241.018390] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  241.018412] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 108
>[32m[  241.018433] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  241.018439] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.034444] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.034466] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.034666] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.034674] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff8801f1252a88
>[32m[  241.034679] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9692548 state to ffff8801f1252a88
>[32m[  241.034681] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.034686] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.034689] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  241.034694] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.051096] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.051108] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.051369] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  241.057757] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.057766] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f95339d8 state to ffff8801f1252a88
>[32m[  241.057772] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff880210688958 state to ffff8801f1252a88
>[32m[  241.057774] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [CRTC:56:pipe C]
>[32m[  241.057778] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:104] for plane state ffff8801f95339d8
>[32m[  241.057787] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9530948 state to ffff8801f1252a88
>[32m[  241.057789] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [NOCRTC]
>[32m[  241.057792] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530948
>[32m[  241.057800] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9532508 state to ffff8801f1252a88
>[32m[  241.057802] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532508 to [NOCRTC]
>[32m[  241.057804] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532508
>[32m[  241.057811] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880210688958
>[32m[  241.057819] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997cb8 state to ffff8801f1252a88
>[32m[  241.057822] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997cb8 to [CRTC:56:pipe C]
>[32m[  241.057828] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff8801f1252a88
>[32m[  241.057830] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [NOCRTC]
>[32m[  241.057832] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.057835] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  241.057839] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  241.057842] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:56:pipe C]
>[32m[  241.057844] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.057846] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  241.057848] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  241.057851] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252a88
>[32m[  241.057855] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252a88
>[32m[  241.057883] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  241.057906] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  241.057927] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  241.057934] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff88020f82dd28 state to ffff8801f1252a88
>[32m[  241.057955] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  241.057976] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  241.057996] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  241.058534] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  241.058555] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  241.058575] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  241.058578] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  241.058598] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  241.058601] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  241.058621] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  241.058658] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  241.058678] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  241.058697] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  241.058719] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  241.058738] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  241.058758] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  241.058778] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:102, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  241.058797] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:108, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  241.058837] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 104
>[32m[  241.058859] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  241.058880] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  241.058900] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.058920] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  241.058940] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.058981] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  241.059533] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  241.059538] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.062023] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  241.084705] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  241.084733] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  241.084966] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  241.084986] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  241.085128] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  241.085150] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  241.085174] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.085199] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  241.085231] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  241.085847] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  241.086138] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  241.086178] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  241.086199] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  241.086225] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  241.086245] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  241.086263] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  241.086287] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  241.086315] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  241.121054] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  241.121085] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  241.121123] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.121136] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.121170] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.154693] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  241.154830] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  241.159375] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  241.170958] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.170967] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020e078258 state to ffff8801f1252a88
>[32m[  241.170973] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9688008 state to ffff8801f1252a88
>[32m[  241.170976] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [CRTC:56:pipe C]
>[32m[  241.170980] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff88020e078258
>[32m[  241.171146] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020e07b788 state to ffff8801f1252a88
>[32m[  241.171149] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b788 to [CRTC:56:pipe C]
>[32m[  241.171152] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88020e07b788
>[32m[  241.171170] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020e07a9a8 state to ffff8801f1252a88
>[32m[  241.171173] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [CRTC:56:pipe C]
>[32m[  241.171176] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88020e07a9a8
>[32m[  241.171184] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9688008
>[32m[  241.171193] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f996368 state to ffff8801f1252a88
>[32m[  241.171207] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.171213] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  241.171216] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  241.171248] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 113
>[32m[  241.171272] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  241.171318] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 110
>[32m[  241.171341] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  241.171363] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 112
>[32m[  241.171384] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  241.171390] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.187530] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.187553] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.187935] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.187942] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048ae8 state to ffff8801f1252a88
>[32m[  241.187945] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.187948] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.187950] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  241.187953] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.187965] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.187978] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.188233] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  241.194107] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.194116] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2c008 state to ffff8801f1252a88
>[32m[  241.194121] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12c5d28 state to ffff8801f1252a88
>[32m[  241.194124] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [CRTC:56:pipe C]
>[32m[  241.194127] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff88020ec2c008
>[32m[  241.194136] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2e9a8 state to ffff8801f1252a88
>[32m[  241.194139] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [NOCRTC]
>[32m[  241.194141] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e9a8
>[32m[  241.194149] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2ee48 state to ffff8801f1252a88
>[32m[  241.194152] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2ee48 to [NOCRTC]
>[32m[  241.194154] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2ee48
>[32m[  241.194161] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f12c5d28
>[32m[  241.194169] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997cb8 state to ffff8801f1252a88
>[32m[  241.194171] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997cb8 to [NOCRTC]
>[32m[  241.194177] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff8801f1252a88
>[32m[  241.194180] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048918 to [CRTC:56:pipe C]
>[32m[  241.194182] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.194185] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  241.194189] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  241.194191] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  241.194193] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.194196] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:56:pipe C]
>[32m[  241.194198] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  241.194200] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252a88
>[32m[  241.194205] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252a88
>[32m[  241.194232] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  241.194254] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  241.194278] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  241.194298] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  241.194319] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  241.194326] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12c1bf8 state to ffff8801f1252a88
>[32m[  241.194346] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  241.194366] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  241.194386] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  241.194406] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  241.194425] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  241.194443] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  241.194446] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  241.194464] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  241.194467] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  241.194485] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  241.194503] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  241.194521] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  241.194539] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  241.194559] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  241.194577] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  241.194596] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:113, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  241.194615] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:110, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  241.194633] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:112, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  241.194656] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 111
>[32m[  241.194676] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  241.194696] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  241.194715] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.194734] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  241.194753] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.194792] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  241.194811] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  241.194815] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.197803] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  241.221686] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  241.221714] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  241.221946] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  241.221969] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  241.221989] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  241.222142] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  241.222166] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.222191] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  241.222224] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  241.222869] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  241.223126] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  241.223166] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  241.223187] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  241.223223] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  241.223244] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  241.223262] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  241.223287] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  241.223317] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  241.258148] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  241.258179] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  241.258218] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.258231] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.258253] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.291649] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.291657] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049968 state to ffff8801f1252a88
>[32m[  241.291662] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f121a548 state to ffff8801f1252a88
>[32m[  241.291665] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.291669] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.291672] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  241.291677] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.308126] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.308138] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.308387] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  241.308522] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  241.312633] [0m[drm:drm_mode_addfb2] [FB:117]
>[32m[  241.324886] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.324896] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cd728 state to ffff8801f1252a88
>[32m[  241.324902] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1219bf8 state to ffff8801f1252a88
>[32m[  241.324905] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [CRTC:56:pipe C]
>[32m[  241.324908] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5cd728
>[32m[  241.324918] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5ce2b8 state to ffff8801f1252a88
>[32m[  241.324920] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce2b8 to [CRTC:56:pipe C]
>[32m[  241.324923] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801fb5ce2b8
>[32m[  241.324932] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5ce508 state to ffff8801f1252a88
>[32m[  241.324934] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [CRTC:56:pipe C]
>[32m[  241.324937] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801fb5ce508
>[32m[  241.324944] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1219bf8
>[32m[  241.324953] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048ae8 state to ffff8801f1252a88
>[32m[  241.324958] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.324963] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.324966] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  241.324996] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 117
>[32m[  241.325352] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  241.325378] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 114
>[32m[  241.325400] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  241.325422] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 116
>[32m[  241.325443] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  241.325466] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.341451] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.341473] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.341669] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252a88
>[32m[  241.341676] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049798 state to ffff8801f1252a88
>[32m[  241.341682] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9692548 state to ffff8801f1252a88
>[32m[  241.341684] [0m[drm:drm_atomic_check_only] checking ffff8801f1252a88
>[32m[  241.341689] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.341691] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  241.341696] [0m[drm:drm_atomic_commit] committing ffff8801f1252a88
>[32m[  241.358112] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252a88
>[32m[  241.358124] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252a88
>[32m[  241.358254] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  241.368370] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  241.368377] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cd978 state to ffff8801f1253fc8
>[32m[  241.368381] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cc948 state to ffff8801f1253fc8
>[32m[  241.368383] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc948 to [NOCRTC]
>[32m[  241.368385] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc948
>[32m[  241.368389] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cf098 state to ffff8801f1253fc8
>[32m[  241.368391] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [NOCRTC]
>[32m[  241.368392] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf098
>[32m[  241.368396] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cde18 state to ffff8801f1253fc8
>[32m[  241.368399] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  241.368412] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cde18 state to ffff8801f1253fc8
>[32m[  241.368416] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cd288 state to ffff8801f1253fc8
>[32m[  241.368418] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd288 to [NOCRTC]
>[32m[  241.368419] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd288
>[32m[  241.368423] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cf098 state to ffff8801f1253fc8
>[32m[  241.368424] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [NOCRTC]
>[32m[  241.368426] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf098
>[32m[  241.368428] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  241.368438] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cf098 state to ffff8801f1253fc8
>[32m[  241.368442] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cc948 state to ffff8801f1253fc8
>[32m[  241.368443] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc948 to [NOCRTC]
>[32m[  241.368445] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc948
>[32m[  241.368448] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cd288 state to ffff8801f1253fc8
>[32m[  241.368450] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd288 to [NOCRTC]
>[32m[  241.368451] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd288
>[32m[  241.368455] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cd978 state to ffff8801f1253fc8
>[32m[  241.368459] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cde18 state to ffff8801f1253fc8
>[32m[  241.368460] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cde18 to [NOCRTC]
>[32m[  241.368462] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cde18
>[32m[  241.368466] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cf9d8 state to ffff8801f1253fc8
>[32m[  241.368467] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf9d8 to [NOCRTC]
>[32m[  241.368469] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf9d8
>[32m[  241.368472] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cf2e8 state to ffff8801f1253fc8
>[32m[  241.368477] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9694a88 state to ffff8801f1253fc8
>[32m[  241.368482] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212ebf8 state to ffff8801f1253fc8
>[32m[  241.368484] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [NOCRTC]
>[32m[  241.368485] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212ebf8
>[32m[  241.368489] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212d978 state to ffff8801f1253fc8
>[32m[  241.368491] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [NOCRTC]
>[32m[  241.368492] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212d978
>[32m[  241.368497] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802144bc138 state to ffff8801f1253fc8
>[32m[  241.368503] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8802144bc138
>[32m[  241.368505] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [CRTC:36:pipe A]
>[32m[  241.368507] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801fb5cf098
>[32m[  241.368509] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  241.368541] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212d978 state to ffff8801f1253fc8
>[32m[  241.368545] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212c258 state to ffff8801f1253fc8
>[32m[  241.368546] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c258 to [NOCRTC]
>[32m[  241.368548] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c258
>[32m[  241.368552] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212ebf8 state to ffff8801f1253fc8
>[32m[  241.368553] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [NOCRTC]
>[32m[  241.368555] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212ebf8
>[32m[  241.368558] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212c008 state to ffff8801f1253fc8
>[32m[  241.368562] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212c4a8 state to ffff8801f1253fc8
>[32m[  241.368564] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [NOCRTC]
>[32m[  241.368565] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c4a8
>[32m[  241.368569] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212de18 state to ffff8801f1253fc8
>[32m[  241.368571] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  241.368572] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  241.368576] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212e9a8 state to ffff8801f1253fc8
>[32m[  241.368580] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9688008 state to ffff8801f1253fc8
>[32m[  241.368584] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212fc28 state to ffff8801f1253fc8
>[32m[  241.368585] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [NOCRTC]
>[32m[  241.368587] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212fc28
>[32m[  241.368591] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212c6f8 state to ffff8801f1253fc8
>[32m[  241.368592] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  241.368594] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  241.368598] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f968ae98 state to ffff8801f1253fc8
>[32m[  241.368602] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f968ae98
>[32m[  241.368604] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [CRTC:36:pipe A]
>[32m[  241.368606] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88021212d978
>[32m[  241.368608] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1253fc8
>[32m[  241.368615] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997b08 state to ffff8801f1253fc8
>[32m[  241.368617] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997b08 to [CRTC:36:pipe A]
>[32m[  241.368622] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff880210694a88 state to ffff8801f1253fc8
>[32m[  241.368627] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880210694a88
>[32m[  241.368628] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [CRTC:46:pipe B]
>[32m[  241.368630] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88021212c008
>[32m[  241.368632] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253fc8
>[32m[  241.368638] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801f1253fc8
>[32m[  241.368640] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b81d8 to [CRTC:46:pipe B]
>[32m[  241.368642] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f9688008
>[32m[  241.368644] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9688008
>[32m[  241.368645] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [NOCRTC]
>[32m[  241.368647] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212e9a8
>[32m[  241.368649] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253fc8
>[32m[  241.368652] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  241.368654] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  241.368656] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  241.368657] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  241.368659] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  241.368660] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  241.368661] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  241.368663] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  241.368664] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] enable changed
>[32m[  241.368666] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] active changed
>[32m[  241.368670] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  241.368672] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  241.368674] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.368676] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  241.368678] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  241.368680] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1253fc8
>[32m[  241.368683] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  241.368685] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253fc8
>[32m[  241.368688] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: n, active: n
>[32m[  241.368689] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253fc8
>[32m[  241.368694] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1253fc8
>[32m[  241.368722] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  241.368744] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  241.368765] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  241.368785] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  241.368806] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  241.368826] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  241.368845] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  241.368864] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  241.368882] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  241.368885] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  241.368903] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  241.368905] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  241.368923] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  241.368941] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  241.368959] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  241.368976] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  241.368996] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  241.369039] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  241.369066] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0
>[32m[  241.369084] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0
>[32m[  241.369101] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0
>[32m[  241.369104] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253fc8
>[32m[  241.369124] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  241.369143] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  241.369164] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  241.369183] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  241.369202] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  241.369220] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  241.369239] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  241.369256] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  241.369274] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  241.369292] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  241.369309] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  241.369311] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  241.369328] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  241.369330] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  241.369348] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  241.369365] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  241.369382] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  241.369399] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  241.369418] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  241.369435] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  241.369452] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0
>[32m[  241.369469] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  241.369486] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  241.369509] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  241.369529] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  241.369548] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  241.369566] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  241.369585] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb -1
>[32m[  241.369603] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.369621] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  241.369639] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.369657] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  241.369675] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.369712] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  241.369731] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  241.369767] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  241.369785] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  241.369790] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  241.369874] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  241.393404] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  241.393431] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  241.393663] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  241.393683] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  241.393702] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  241.393721] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.393744] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  241.393794] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  241.394427] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  241.394609] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  241.394638] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  241.394657] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  241.394683] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  241.394702] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  241.394719] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  241.394741] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  241.394760] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  241.412876] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  241.413539] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  241.413724] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  241.413754] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  241.413775] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  241.413801] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  241.413820] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  241.413838] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  241.413861] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  241.413880] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  241.448698] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  241.448723] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  241.448763] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.448792] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  241.448814] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  241.448851] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  241.448877] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  241.448888] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  241.448950] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  241.452964] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  241.461403] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255fa8
>[32m[  241.461411] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128eabf8 state to ffff8801f1255fa8
>[32m[  241.461417] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1219bf8 state to ffff8801f1255fa8
>[32m[  241.461423] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128eb538 state to ffff8801f1255fa8
>[32m[  241.461425] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [NOCRTC]
>[32m[  241.461427] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb538
>[32m[  241.461432] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128e9978 state to ffff8801f1255fa8
>[32m[  241.461434] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [NOCRTC]
>[32m[  241.461436] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9978
>[32m[  241.461441] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128e8258 state to ffff8801f1255fa8
>[32m[  241.461443] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255fa8
>[32m[  241.461468] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128e8258 state to ffff8801f1255fa8
>[32m[  241.461473] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1219bf8 state to ffff8801f1255fa8
>[32m[  241.461477] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128e86f8 state to ffff8801f1255fa8
>[32m[  241.461479] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [NOCRTC]
>[32m[  241.461481] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e86f8
>[32m[  241.461483] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255fa8
>[32m[  241.461494] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128e86f8 state to ffff8801f1255fa8
>[32m[  241.461499] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1219bf8 state to ffff8801f1255fa8
>[32m[  241.461503] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128ea2b8 state to ffff8801f1255fa8
>[32m[  241.461505] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [NOCRTC]
>[32m[  241.461507] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128ea2b8
>[32m[  241.461511] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128e8258 state to ffff8801f1255fa8
>[32m[  241.461513] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e8258 to [NOCRTC]
>[32m[  241.461515] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e8258
>[32m[  241.461520] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128eb098 state to ffff8801f1255fa8
>[32m[  241.461524] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121a548 state to ffff8801f1255fa8
>[32m[  241.461529] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128e9978 state to ffff8801f1255fa8
>[32m[  241.461531] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [NOCRTC]
>[32m[  241.461533] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9978
>[32m[  241.461537] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128e9728 state to ffff8801f1255fa8
>[32m[  241.461539] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [NOCRTC]
>[32m[  241.461541] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9728
>[32m[  241.461545] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128eb538 state to ffff8801f1255fa8
>[32m[  241.461549] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128eabf8 state to ffff8801f1255fa8
>[32m[  241.461551] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [NOCRTC]
>[32m[  241.461553] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eabf8
>[32m[  241.461558] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff880212131978 state to ffff8801f1255fa8
>[32m[  241.461560] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [NOCRTC]
>[32m[  241.461562] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131978
>[32m[  241.461568] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1219bf8
>[32m[  241.461571] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [CRTC:36:pipe A]
>[32m[  241.461573] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802128e86f8
>[32m[  241.461576] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255fa8
>[32m[  241.461604] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff880212131978 state to ffff8801f1255fa8
>[32m[  241.461609] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802144bc138 state to ffff8801f1255fa8
>[32m[  241.461613] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff880212131288 state to ffff8801f1255fa8
>[32m[  241.461615] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [NOCRTC]
>[32m[  241.461617] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131288
>[32m[  241.461621] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212131038 state to ffff8801f1255fa8
>[32m[  241.461623] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [NOCRTC]
>[32m[  241.461625] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131038
>[32m[  241.461630] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802121329a8 state to ffff8801f1255fa8
>[32m[  241.461634] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9692548 state to ffff8801f1255fa8
>[32m[  241.461638] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802121314d8 state to ffff8801f1255fa8
>[32m[  241.461640] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [NOCRTC]
>[32m[  241.461642] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121314d8
>[32m[  241.461647] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cc6f8 state to ffff8801f1255fa8
>[32m[  241.461649] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  241.461651] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  241.461655] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cc4a8 state to ffff8801f1255fa8
>[32m[  241.461660] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111ccde8 state to ffff8801f1255fa8
>[32m[  241.461662] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [NOCRTC]
>[32m[  241.461664] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccde8
>[32m[  241.461668] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cf098 state to ffff8801f1255fa8
>[32m[  241.461670] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [NOCRTC]
>[32m[  241.461672] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf098
>[32m[  241.461677] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8802144bc138
>[32m[  241.461679] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [CRTC:36:pipe A]
>[32m[  241.461681] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff880212131978
>[32m[  241.461684] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1255fa8
>[32m[  241.461692] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997958 state to ffff8801f1255fa8
>[32m[  241.461695] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997958 to [NOCRTC]
>[32m[  241.461698] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997958 to [CRTC:36:pipe A]
>[32m[  241.461703] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f9692548
>[32m[  241.461705] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [CRTC:46:pipe B]
>[32m[  241.461707] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802121329a8
>[32m[  241.461710] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1255fa8
>[32m[  241.461715] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff8801f1255fa8
>[32m[  241.461718] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8cb8 to [NOCRTC]
>[32m[  241.461720] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8cb8 to [CRTC:46:pipe B]
>[32m[  241.461725] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9694a88 state to ffff8801f1255fa8
>[32m[  241.461728] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9694a88
>[32m[  241.461730] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [NOCRTC]
>[32m[  241.461732] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc4a8
>[32m[  241.461734] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1255fa8
>[32m[  241.461737] [0m[drm:drm_atomic_check_only] checking ffff8801f1255fa8
>[32m[  241.461743] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  241.461746] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  241.461748] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.461751] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  241.461781] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  241.461803] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  241.461825] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  241.461845] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  241.461852] [0m[drm:drm_atomic_commit] committing ffff8801f1255fa8
>[32m[  241.465328] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255fa8
>[32m[  241.465378] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255fa8
>[32m[  241.501742] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  241.501839] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  241.513191] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  241.513226] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  241.513253] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  241.513274] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  241.551477] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  241.551548] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  241.551552] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  241.551554] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  241.551556] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  241.551558] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  241.551561] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  241.551563] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  241.551565] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  241.551567] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  241.551569] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  241.551571] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  241.551573] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  241.551575] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  241.551677] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  241.551708] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  241.626361] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  241.626384] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  241.628442] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  241.628448] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  241.628452] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  241.628468] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  241.628584] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  241.628587] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  241.628588] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  241.628720] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  241.628723] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  241.628725] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  241.628728] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  241.628730] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  241.628732] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  241.628734] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  241.628736] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  241.628738] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  241.628740] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  241.628742] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  241.628744] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  241.628746] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  241.628748] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  241.628750] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  241.628752] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  241.628754] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  241.628756] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  241.628758] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  241.628905] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254518
>[32m[  241.628913] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135aa748 state to ffff8801f1254518
>[32m[  241.628919] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129a548 state to ffff8801f1254518
>[32m[  241.628922] [0m[drm:drm_atomic_check_only] checking ffff8801f1254518
>[32m[  241.628927] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.628930] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  241.628936] [0m[drm:drm_atomic_commit] committing ffff8801f1254518
>[32m[  241.632015] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254518
>[32m[  241.632028] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254518
>[32m[  241.632067] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  241.632093] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  241.634666] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.637219] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.639778] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.642331] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.644883] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.647433] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.649982] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.652605] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.655158] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.657710] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.660264] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.662817] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.665369] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.667920] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.670472] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.673072] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.675609] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.678140] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.680667] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.683197] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.685724] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.688254] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.690780] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.693306] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.695831] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.698357] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.700882] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.703408] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.705934] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.708458] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.710982] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.713528] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  241.713536] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  241.713539] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  241.713694] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254518
>[32m[  241.713701] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802135aa918 state to ffff8801f1254518
>[32m[  241.713704] [0m[drm:drm_atomic_check_only] checking ffff8801f1254518
>[32m[  241.713707] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  241.713709] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  241.713712] [0m[drm:drm_atomic_commit] committing ffff8801f1254518
>[32m[  241.713725] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254518
>[32m[  241.713732] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254518
>[32m[  241.713817] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest atomic-pipe-C-tiling-x
>[32m[  241.714118] [0m[drm:drm_mode_addfb2] [FB:95]
>[32m[  241.721032] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254518
>[32m[  241.721042] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2cb98 state to ffff8801f1254518
>[32m[  241.721048] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126dd28 state to ffff8801f1254518
>[32m[  241.721051] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [NOCRTC]
>[32m[  241.721054] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cb98
>[32m[  241.721072] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2cde8 state to ffff8801f1254518
>[32m[  241.721074] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  241.721077] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  241.721082] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2dbc8 state to ffff8801f1254518
>[32m[  241.721084] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  241.721087] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  241.721090] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f126dd28
>[32m[  241.721097] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2c008 state to ffff8801f1254518
>[32m[  241.721101] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1268008 state to ffff8801f1254518
>[32m[  241.721104] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  241.721106] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  241.721111] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2e758 state to ffff8801f1254518
>[32m[  241.721114] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  241.721116] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  241.721121] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2e9a8 state to ffff8801f1254518
>[32m[  241.721124] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [NOCRTC]
>[32m[  241.721126] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e9a8
>[32m[  241.721129] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f1268008
>[32m[  241.721135] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2c4a8 state to ffff8801f1254518
>[32m[  241.721140] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12692a8 state to ffff8801f1254518
>[32m[  241.721142] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [CRTC:56:pipe C]
>[32m[  241.721145] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:95] for plane state ffff88020ec2c4a8
>[32m[  241.721155] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2ee48 state to ffff8801f1254518
>[32m[  241.721157] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2ee48 to [NOCRTC]
>[32m[  241.721160] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2ee48
>[32m[  241.721165] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2d038 state to ffff8801f1254518
>[32m[  241.721167] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  241.721169] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  241.721174] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12692a8
>[32m[  241.721182] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f996008 state to ffff8801f1254518
>[32m[  241.721185] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f996008 to [CRTC:56:pipe C]
>[32m[  241.721190] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135ab228 state to ffff8801f1254518
>[32m[  241.721192] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135ab228 to [NOCRTC]
>[32m[  241.721197] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802135ab058 state to ffff8801f1254518
>[32m[  241.721200] [0m[drm:drm_atomic_check_only] checking ffff8801f1254518
>[32m[  241.721203] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  241.721205] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  241.721207] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  241.721209] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  241.721211] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  241.721213] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  241.721215] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  241.721217] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] enable changed
>[32m[  241.721218] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] active changed
>[32m[  241.721222] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  241.721225] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  241.721227] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.721229] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  241.721231] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  241.721233] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  241.721235] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: n, active: n
>[32m[  241.721237] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1254518
>[32m[  241.721240] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: n, active: n
>[32m[  241.721243] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1254518
>[32m[  241.721246] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  241.721248] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254518
>[32m[  241.721252] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254518
>[32m[  241.721279] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  241.721301] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  241.721323] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  241.721343] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  241.721364] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  241.721384] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  241.721404] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  241.721423] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  241.721442] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  241.721445] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  241.721463] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  241.721466] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  241.721485] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  241.721503] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  241.721521] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  241.721539] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  241.721560] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  241.721579] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  241.721597] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] disabled, scaler_id = 0
>[32m[  241.721615] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] disabled, scaler_id = 0
>[32m[  241.721633] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] disabled, scaler_id = 0
>[32m[  241.721656] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb -1
>[32m[  241.721676] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.721696] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb -1
>[32m[  241.721715] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.721735] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 95
>[32m[  241.721753] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  241.721793] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  241.721813] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  241.721817] [0m[drm:drm_atomic_commit] committing ffff8801f1254518
>[32m[  241.725944] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  241.745647] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  241.745676] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  241.745919] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  241.766583] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  241.766611] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  241.766846] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  241.766866] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  241.766888] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  241.766908] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  241.766930] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:65:DP-1]
>[32m[  241.766952] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.766975] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  241.767284] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  241.767900] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  241.768165] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  241.768207] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  241.768227] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  241.768253] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  241.768273] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  241.768291] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  241.768326] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  241.768347] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  241.803123] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  241.803153] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  241.803182] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  241.803205] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  241.803242] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.803258] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254518
>[32m[  241.803301] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254518
>[32m[  241.836766] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  241.836919] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  241.841570] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  241.853068] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254518
>[32m[  241.853079] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cd4d8 state to ffff8801f1254518
>[32m[  241.853084] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12b2548 state to ffff8801f1254518
>[32m[  241.853088] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [CRTC:56:pipe C]
>[32m[  241.853091] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801fb5cd4d8
>[32m[  241.853101] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cc948 state to ffff8801f1254518
>[32m[  241.853103] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc948 to [CRTC:56:pipe C]
>[32m[  241.853106] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff8801fb5cc948
>[32m[  241.853115] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cdbc8 state to ffff8801f1254518
>[32m[  241.853117] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [CRTC:56:pipe C]
>[32m[  241.853120] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff8801fb5cdbc8
>[32m[  241.853127] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12b2548
>[32m[  241.853132] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254518
>[32m[  241.853148] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cdbc8 state to ffff8801f1254518
>[32m[  241.853153] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12b2548 state to ffff8801f1254518
>[32m[  241.853156] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [CRTC:56:pipe C]
>[32m[  241.853158] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801fb5cdbc8
>[32m[  241.853167] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cfc28 state to ffff8801f1254518
>[32m[  241.853169] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [CRTC:56:pipe C]
>[32m[  241.853172] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff8801fb5cfc28
>[32m[  241.853178] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254518
>[32m[  241.853190] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cfc28 state to ffff8801f1254518
>[32m[  241.853195] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12b2548 state to ffff8801f1254518
>[32m[  241.853197] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [CRTC:56:pipe C]
>[32m[  241.853200] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801fb5cfc28
>[32m[  241.853208] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cf538 state to ffff8801f1254518
>[32m[  241.853210] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf538 to [CRTC:56:pipe C]
>[32m[  241.853213] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff8801fb5cf538
>[32m[  241.853221] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cdbc8 state to ffff8801f1254518
>[32m[  241.853223] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [CRTC:56:pipe C]
>[32m[  241.853226] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff8801fb5cdbc8
>[32m[  241.853232] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12b2548
>[32m[  241.853241] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997cb8 state to ffff8801f1254518
>[32m[  241.853247] [0m[drm:drm_atomic_check_only] checking ffff8801f1254518
>[32m[  241.853253] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  241.853255] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  241.853287] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 100
>[32m[  241.853310] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  241.853332] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 66
>[32m[  241.853353] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  241.853373] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 82
>[32m[  241.853393] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  241.853399] [0m[drm:drm_atomic_commit] committing ffff8801f1254518
>[32m[  241.869594] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254518
>[32m[  241.869618] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254518
>[32m[  241.870138] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254518
>[32m[  241.870147] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049798 state to ffff8801f1254518
>[32m[  241.870150] [0m[drm:drm_atomic_check_only] checking ffff8801f1254518
>[32m[  241.870153] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.870163] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  241.870167] [0m[drm:drm_atomic_commit] committing ffff8801f1254518
>[32m[  241.870178] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254518
>[32m[  241.870190] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254518
>[32m[  241.870280] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  241.876179] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  241.876187] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5ce758 state to ffff8801f1254a68
>[32m[  241.876193] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8802144bc138 state to ffff8801f1254a68
>[32m[  241.876196] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [CRTC:56:pipe C]
>[32m[  241.876199] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8801fb5ce758
>[32m[  241.876208] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5ce508 state to ffff8801f1254a68
>[32m[  241.876211] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [NOCRTC]
>[32m[  241.876213] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce508
>[32m[  241.876221] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cd978 state to ffff8801f1254a68
>[32m[  241.876223] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd978 to [NOCRTC]
>[32m[  241.876226] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd978
>[32m[  241.876233] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8802144bc138
>[32m[  241.876241] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f996008 state to ffff8801f1254a68
>[32m[  241.876243] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f996008 to [NOCRTC]
>[32m[  241.876250] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0495c8 state to ffff8801f1254a68
>[32m[  241.876252] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0495c8 to [CRTC:56:pipe C]
>[32m[  241.876254] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  241.876257] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  241.876261] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  241.876263] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  241.876265] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.876268] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:56:pipe C]
>[32m[  241.876270] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  241.876273] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254a68
>[32m[  241.876277] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254a68
>[32m[  241.876306] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  241.876329] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  241.876352] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  241.876373] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  241.876394] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  241.876400] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129a548 state to ffff8801f1254a68
>[32m[  241.876420] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  241.876441] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  241.876461] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  241.876480] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  241.876499] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  241.876518] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  241.876521] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  241.876539] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  241.876541] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  241.876560] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  241.876579] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  241.876597] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  241.876614] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  241.876635] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  241.876652] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  241.876671] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  241.876689] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  241.876707] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:82, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  241.876731] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 99
>[32m[  241.876750] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  241.876770] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  241.876789] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.876808] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  241.876826] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  241.876866] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  241.876885] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  241.876889] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  241.879960] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  241.904687] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  241.904715] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  241.904947] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  241.904970] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  241.904989] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  241.905151] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  241.905183] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.905216] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  241.905247] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  241.905887] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  241.906121] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  241.906152] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  241.906181] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  241.906215] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  241.906234] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  241.906251] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  241.906274] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  241.906294] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  241.941127] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  241.941159] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  241.941199] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  241.941212] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  241.941234] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  241.974621] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  241.974630] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049228 state to ffff8801f1254a68
>[32m[  241.974635] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129ae98 state to ffff8801f1254a68
>[32m[  241.974638] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  241.974643] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  241.974645] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  241.974650] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  241.991087] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  241.991110] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  241.991362] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  241.991499] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  241.995707] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  242.007865] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.007874] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cf9d8 state to ffff8801f1254a68
>[32m[  242.007880] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129ca88 state to ffff8801f1254a68
>[32m[  242.007883] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf9d8 to [CRTC:56:pipe C]
>[32m[  242.007886] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801fb5cf9d8
>[32m[  242.007896] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cfc28 state to ffff8801f1254a68
>[32m[  242.007898] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [CRTC:56:pipe C]
>[32m[  242.007901] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8801fb5cfc28
>[32m[  242.007909] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cde18 state to ffff8801f1254a68
>[32m[  242.007911] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cde18 to [CRTC:56:pipe C]
>[32m[  242.007914] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801fb5cde18
>[32m[  242.007921] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129ca88
>[32m[  242.007926] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.007942] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128eabf8 state to ffff8801f1254a68
>[32m[  242.007947] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129ca88 state to ffff8801f1254a68
>[32m[  242.007949] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [CRTC:56:pipe C]
>[32m[  242.007952] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802128eabf8
>[32m[  242.007960] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128e86f8 state to ffff8801f1254a68
>[32m[  242.007962] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [CRTC:56:pipe C]
>[32m[  242.007965] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8802128e86f8
>[32m[  242.007971] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.007983] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128e86f8 state to ffff8801f1254a68
>[32m[  242.008371] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129ca88 state to ffff8801f1254a68
>[32m[  242.008374] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [CRTC:56:pipe C]
>[32m[  242.008377] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802128e86f8
>[32m[  242.008387] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128ea2b8 state to ffff8801f1254a68
>[32m[  242.008389] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [CRTC:56:pipe C]
>[32m[  242.008392] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8802128ea2b8
>[32m[  242.008400] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802128eabf8 state to ffff8801f1254a68
>[32m[  242.008403] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [CRTC:56:pipe C]
>[32m[  242.008406] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8802128eabf8
>[32m[  242.008412] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129ca88
>[32m[  242.008430] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049798 state to ffff8801f1254a68
>[32m[  242.008435] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.008440] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.008443] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  242.008474] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 109
>[32m[  242.008497] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  242.008527] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 102
>[32m[  242.008549] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  242.008570] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 108
>[32m[  242.008599] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  242.008604] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.024420] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.024451] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.024662] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.024670] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048ae8 state to ffff8801f1254a68
>[32m[  242.024675] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff880210694a88 state to ffff8801f1254a68
>[32m[  242.024678] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.024682] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.024685] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  242.024690] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.041081] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.041103] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.041358] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  242.047721] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.047730] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212d978 state to ffff8801f1254a68
>[32m[  242.047736] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1219bf8 state to ffff8801f1254a68
>[32m[  242.047738] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [CRTC:56:pipe C]
>[32m[  242.047742] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:104] for plane state ffff88021212d978
>[32m[  242.047751] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212fc28 state to ffff8801f1254a68
>[32m[  242.047753] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [NOCRTC]
>[32m[  242.047756] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212fc28
>[32m[  242.047763] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212c258 state to ffff8801f1254a68
>[32m[  242.047766] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c258 to [NOCRTC]
>[32m[  242.047768] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c258
>[32m[  242.047775] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1219bf8
>[32m[  242.047783] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997958 state to ffff8801f1254a68
>[32m[  242.047785] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997958 to [CRTC:56:pipe C]
>[32m[  242.047791] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff8801f1254a68
>[32m[  242.047794] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [NOCRTC]
>[32m[  242.047796] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.047799] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  242.047803] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  242.047805] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:56:pipe C]
>[32m[  242.047807] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.047809] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  242.047812] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  242.047814] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254a68
>[32m[  242.047818] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254a68
>[32m[  242.047847] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  242.047870] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  242.047891] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  242.047898] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121c138 state to ffff8801f1254a68
>[32m[  242.047918] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  242.047939] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  242.047959] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  242.047979] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  242.047998] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  242.048529] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  242.048533] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  242.048553] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  242.048556] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  242.048576] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  242.048596] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  242.048615] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  242.048634] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  242.048657] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  242.048676] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  242.048696] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  242.048716] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:102, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  242.048734] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:108, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  242.048768] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 104
>[32m[  242.048797] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  242.048819] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  242.048839] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  242.048859] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  242.048879] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  242.048921] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  242.048942] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  242.048948] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.051842] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  242.075709] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  242.075738] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  242.075971] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  242.075992] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  242.076130] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  242.076152] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  242.076176] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.076201] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  242.076233] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  242.076856] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  242.077122] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  242.077154] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  242.077176] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  242.077203] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  242.077224] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  242.077244] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  242.077268] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  242.077289] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  242.112056] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  242.112087] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  242.112124] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.112138] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.112160] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.145667] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  242.145804] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  242.150344] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  242.161926] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254fb8
>[32m[  242.161936] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802135a3098 state to ffff8801f1254fb8
>[32m[  242.161942] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff8801f1254fb8
>[32m[  242.161945] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [CRTC:56:pipe C]
>[32m[  242.161948] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802135a3098
>[32m[  242.161957] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802135a0de8 state to ffff8801f1254fb8
>[32m[  242.161960] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a0de8 to [CRTC:56:pipe C]
>[32m[  242.161963] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8802135a0de8
>[32m[  242.161969] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.161983] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff880212945978 state to ffff8801f1254fb8
>[32m[  242.162187] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff8801f1254fb8
>[32m[  242.162191] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212945978 to [CRTC:56:pipe C]
>[32m[  242.162203] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff880212945978
>[32m[  242.162212] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802129462b8 state to ffff8801f1254fb8
>[32m[  242.162215] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802129462b8 to [CRTC:56:pipe C]
>[32m[  242.162218] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8802129462b8
>[32m[  242.162227] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cf098 state to ffff8801f1254fb8
>[32m[  242.162229] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [CRTC:56:pipe C]
>[32m[  242.162232] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff8802111cf098
>[32m[  242.162240] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1268008
>[32m[  242.162244] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.162268] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cf098 state to ffff8801f1254fb8
>[32m[  242.162273] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff8801f1254fb8
>[32m[  242.162275] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [CRTC:56:pipe C]
>[32m[  242.162278] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802111cf098
>[32m[  242.162286] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111ccde8 state to ffff8801f1254fb8
>[32m[  242.162288] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [CRTC:56:pipe C]
>[32m[  242.162291] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8802111ccde8
>[32m[  242.162299] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cebf8 state to ffff8801f1254fb8
>[32m[  242.162302] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [CRTC:56:pipe C]
>[32m[  242.162304] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff8802111cebf8
>[32m[  242.162311] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1268008
>[32m[  242.162319] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f9961b8 state to ffff8801f1254fb8
>[32m[  242.162324] [0m[drm:drm_atomic_check_only] checking ffff8801f1254fb8
>[32m[  242.162329] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  242.162332] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  242.162363] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 113
>[32m[  242.162385] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  242.162407] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 110
>[32m[  242.162437] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  242.162458] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 112
>[32m[  242.162477] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  242.162482] [0m[drm:drm_atomic_commit] committing ffff8801f1254fb8
>[32m[  242.178500] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.178523] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254fb8
>[32m[  242.178929] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254fb8
>[32m[  242.178936] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0495c8 state to ffff8801f1254fb8
>[32m[  242.178939] [0m[drm:drm_atomic_check_only] checking ffff8801f1254fb8
>[32m[  242.178942] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.178944] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  242.178947] [0m[drm:drm_atomic_commit] committing ffff8801f1254fb8
>[32m[  242.178959] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.178972] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254fb8
>[32m[  242.179237] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  242.185026] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254fb8
>[32m[  242.185034] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cfc28 state to ffff8801f1254fb8
>[32m[  242.185040] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126e678 state to ffff8801f1254fb8
>[32m[  242.185043] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cfc28 to [CRTC:56:pipe C]
>[32m[  242.185046] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:111] for plane state ffff8802111cfc28
>[32m[  242.185055] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cf2e8 state to ffff8801f1254fb8
>[32m[  242.185058] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [NOCRTC]
>[32m[  242.185060] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf2e8
>[32m[  242.185069] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ffdc948 state to ffff8801f1254fb8
>[32m[  242.185071] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdc948 to [NOCRTC]
>[32m[  242.185073] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdc948
>[32m[  242.185080] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126e678
>[32m[  242.185088] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f997958 state to ffff8801f1254fb8
>[32m[  242.185091] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f997958 to [NOCRTC]
>[32m[  242.185096] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048ae8 state to ffff8801f1254fb8
>[32m[  242.185099] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048ae8 to [CRTC:56:pipe C]
>[32m[  242.185101] [0m[drm:drm_atomic_check_only] checking ffff8801f1254fb8
>[32m[  242.185104] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  242.185108] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  242.185110] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  242.185112] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.185115] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:56:pipe C]
>[32m[  242.185117] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  242.185120] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254fb8
>[32m[  242.185124] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254fb8
>[32m[  242.185153] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  242.185175] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  242.185198] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  242.185218] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  242.185239] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  242.185246] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126a548 state to ffff8801f1254fb8
>[32m[  242.185266] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  242.185286] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  242.185306] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  242.185326] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  242.185345] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  242.185363] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  242.185366] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  242.185384] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  242.185386] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  242.185405] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  242.185423] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  242.185441] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  242.185459] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  242.185479] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  242.185497] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  242.185516] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:113, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  242.185534] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:110, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  242.185552] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:112, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  242.185575] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 111
>[32m[  242.185594] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  242.185614] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  242.185633] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  242.185652] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  242.185670] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  242.185709] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  242.185728] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  242.185732] [0m[drm:drm_atomic_commit] committing ffff8801f1254fb8
>[32m[  242.188741] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  242.212690] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  242.212717] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  242.212949] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  242.212972] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  242.212991] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  242.213152] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  242.213185] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.213209] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  242.213248] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  242.213890] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  242.214118] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  242.214149] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  242.214171] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  242.214206] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  242.214225] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  242.214243] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  242.214266] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  242.214285] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  242.249104] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  242.249135] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  242.249174] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.249187] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.249209] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254fb8
>[32m[  242.282590] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254fb8
>[32m[  242.282599] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049228 state to ffff8801f1254fb8
>[32m[  242.282604] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12692a8 state to ffff8801f1254fb8
>[32m[  242.282606] [0m[drm:drm_atomic_check_only] checking ffff8801f1254fb8
>[32m[  242.282611] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.282614] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  242.282619] [0m[drm:drm_atomic_commit] committing ffff8801f1254fb8
>[32m[  242.299082] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.299094] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254fb8
>[32m[  242.299346] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  242.299480] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  242.303644] [0m[drm:drm_mode_addfb2] [FB:117]
>[32m[  242.315841] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254fb8
>[32m[  242.315850] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f9532bf8 state to ffff8801f1254fb8
>[32m[  242.315856] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff8801f1254fb8
>[32m[  242.315859] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [CRTC:56:pipe C]
>[32m[  242.315862] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801f9532bf8
>[32m[  242.315872] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9532758 state to ffff8801f1254fb8
>[32m[  242.315874] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [CRTC:56:pipe C]
>[32m[  242.315877] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801f9532758
>[32m[  242.315884] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.315898] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f9532758 state to ffff8801f1254fb8
>[32m[  242.315902] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff8801f1254fb8
>[32m[  242.315905] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [CRTC:56:pipe C]
>[32m[  242.315907] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801f9532758
>[32m[  242.315916] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9530008 state to ffff8801f1254fb8
>[32m[  242.315918] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [CRTC:56:pipe C]
>[32m[  242.315921] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801f9530008
>[32m[  242.315929] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9532bf8 state to ffff8801f1254fb8
>[32m[  242.315931] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [CRTC:56:pipe C]
>[32m[  242.315934] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801f9532bf8
>[32m[  242.315941] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1269bf8
>[32m[  242.315945] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.315959] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f9532bf8 state to ffff8801f1254fb8
>[32m[  242.315963] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff8801f1254fb8
>[32m[  242.315966] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [CRTC:56:pipe C]
>[32m[  242.315968] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801f9532bf8
>[32m[  242.315977] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9532e48 state to ffff8801f1254fb8
>[32m[  242.315979] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532e48 to [CRTC:56:pipe C]
>[32m[  242.315982] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801f9532e48
>[32m[  242.316447] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9530008 state to ffff8801f1254fb8
>[32m[  242.316449] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [CRTC:56:pipe C]
>[32m[  242.316452] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801f9530008
>[32m[  242.316459] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1269bf8
>[32m[  242.316468] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0495c8 state to ffff8801f1254fb8
>[32m[  242.316474] [0m[drm:drm_atomic_check_only] checking ffff8801f1254fb8
>[32m[  242.316488] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.316490] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  242.316521] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 117
>[32m[  242.316544] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  242.316566] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 114
>[32m[  242.316610] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  242.316631] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 116
>[32m[  242.316650] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  242.316655] [0m[drm:drm_atomic_commit] committing ffff8801f1254fb8
>[32m[  242.332415] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.332437] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254fb8
>[32m[  242.332649] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254fb8
>[32m[  242.332657] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0493f8 state to ffff8801f1254fb8
>[32m[  242.332662] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8802106c0958 state to ffff8801f1254fb8
>[32m[  242.332665] [0m[drm:drm_atomic_check_only] checking ffff8801f1254fb8
>[32m[  242.332669] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.332672] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  242.332676] [0m[drm:drm_atomic_commit] committing ffff8801f1254fb8
>[32m[  242.349067] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254fb8
>[32m[  242.349078] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254fb8
>[32m[  242.349209] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  242.359370] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  242.359376] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95339d8 state to ffff8801f12574e8
>[32m[  242.359381] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9531038 state to ffff8801f12574e8
>[32m[  242.359383] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [NOCRTC]
>[32m[  242.359385] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531038
>[32m[  242.359389] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f95304a8 state to ffff8801f12574e8
>[32m[  242.359390] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [NOCRTC]
>[32m[  242.359392] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95304a8
>[32m[  242.359396] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9532508 state to ffff8801f12574e8
>[32m[  242.359400] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9530948 state to ffff8801f12574e8
>[32m[  242.359401] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [NOCRTC]
>[32m[  242.359403] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530948
>[32m[  242.359407] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9533788 state to ffff8801f12574e8
>[32m[  242.359408] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [NOCRTC]
>[32m[  242.359410] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533788
>[32m[  242.359414] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec51728 state to ffff8801f12574e8
>[32m[  242.359419] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff88020f82dd28 state to ffff8801f12574e8
>[32m[  242.359424] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020e07a508 state to ffff8801f12574e8
>[32m[  242.359425] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [NOCRTC]
>[32m[  242.359427] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a508
>[32m[  242.359429] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  242.359454] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020e07a508 state to ffff8801f12574e8
>[32m[  242.359457] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e07a9a8 state to ffff8801f12574e8
>[32m[  242.359459] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [NOCRTC]
>[32m[  242.359460] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a9a8
>[32m[  242.359464] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e07b2e8 state to ffff8801f12574e8
>[32m[  242.359466] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b2e8 to [NOCRTC]
>[32m[  242.359467] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b2e8
>[32m[  242.359469] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  242.359479] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020e07b2e8 state to ffff8801f12574e8
>[32m[  242.359483] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e078258 state to ffff8801f12574e8
>[32m[  242.359485] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [NOCRTC]
>[32m[  242.359486] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078258
>[32m[  242.359490] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e07a9a8 state to ffff8801f12574e8
>[32m[  242.359492] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [NOCRTC]
>[32m[  242.359493] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a9a8
>[32m[  242.359497] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020e078de8 state to ffff8801f12574e8
>[32m[  242.359500] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e07a508 state to ffff8801f12574e8
>[32m[  242.359502] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [NOCRTC]
>[32m[  242.359504] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a508
>[32m[  242.359507] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020e07b788 state to ffff8801f12574e8
>[32m[  242.359509] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b788 to [NOCRTC]
>[32m[  242.359510] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b788
>[32m[  242.359514] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020e0794d8 state to ffff8801f12574e8
>[32m[  242.359519] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12b2548 state to ffff8801f12574e8
>[32m[  242.359523] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802121314d8 state to ffff8801f12574e8
>[32m[  242.359525] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [NOCRTC]
>[32m[  242.359526] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121314d8
>[32m[  242.359530] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff880212131978 state to ffff8801f12574e8
>[32m[  242.359532] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [NOCRTC]
>[32m[  242.359533] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131978
>[32m[  242.359538] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12b0008 state to ffff8801f12574e8
>[32m[  242.359544] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12b0008
>[32m[  242.359546] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b2e8 to [CRTC:36:pipe A]
>[32m[  242.359548] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020e07b2e8
>[32m[  242.359550] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  242.359579] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff880212131978 state to ffff8801f12574e8
>[32m[  242.359583] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff880212131288 state to ffff8801f12574e8
>[32m[  242.359584] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [NOCRTC]
>[32m[  242.359586] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131288
>[32m[  242.359589] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802121314d8 state to ffff8801f12574e8
>[32m[  242.359591] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [NOCRTC]
>[32m[  242.359592] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121314d8
>[32m[  242.359596] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff880212131038 state to ffff8801f12574e8
>[32m[  242.359600] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802121329a8 state to ffff8801f12574e8
>[32m[  242.359601] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [NOCRTC]
>[32m[  242.359603] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121329a8
>[32m[  242.359607] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2e508 state to ffff8801f12574e8
>[32m[  242.359609] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e508 to [NOCRTC]
>[32m[  242.359610] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e508
>[32m[  242.359614] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2c4a8 state to ffff8801f12574e8
>[32m[  242.359618] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12b2548 state to ffff8801f12574e8
>[32m[  242.359622] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2de18 state to ffff8801f12574e8
>[32m[  242.359624] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2de18 to [NOCRTC]
>[32m[  242.359625] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2de18
>[32m[  242.359629] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2ee48 state to ffff8801f12574e8
>[32m[  242.359631] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2ee48 to [NOCRTC]
>[32m[  242.359632] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2ee48
>[32m[  242.359637] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12b6fc8 state to ffff8801f12574e8
>[32m[  242.359641] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12b6fc8
>[32m[  242.359643] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [CRTC:36:pipe A]
>[32m[  242.359644] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff880212131978
>[32m[  242.359647] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  242.359654] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f996368 state to ffff8801f12574e8
>[32m[  242.359656] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f996368 to [CRTC:36:pipe A]
>[32m[  242.359661] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12b0008 state to ffff8801f12574e8
>[32m[  242.359665] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f12b0008
>[32m[  242.359667] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [CRTC:46:pipe B]
>[32m[  242.359668] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff880212131038
>[32m[  242.359670] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  242.359676] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801fd72e578 state to ffff8801f12574e8
>[32m[  242.359677] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd72e578 to [CRTC:46:pipe B]
>[32m[  242.359679] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f12b2548
>[32m[  242.359681] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f12b2548
>[32m[  242.359683] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [NOCRTC]
>[32m[  242.359684] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c4a8
>[32m[  242.359686] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f12574e8
>[32m[  242.359689] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  242.359692] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  242.359693] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  242.359695] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  242.359696] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  242.359698] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  242.359699] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  242.359701] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  242.359702] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] enable changed
>[32m[  242.359704] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] active changed
>[32m[  242.359707] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  242.359710] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  242.359711] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.359713] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  242.359715] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  242.359717] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  242.359720] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  242.359722] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  242.359725] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: n, active: n
>[32m[  242.359727] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f12574e8
>[32m[  242.359731] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  242.359757] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  242.359779] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  242.359800] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  242.359820] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  242.359840] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  242.359860] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  242.359879] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  242.359898] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  242.359916] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  242.359918] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  242.359936] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  242.359938] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  242.359957] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  242.359975] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  242.359992] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  242.360037] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  242.360066] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  242.360084] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  242.360101] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0
>[32m[  242.360119] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0
>[32m[  242.360136] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0
>[32m[  242.360139] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  242.360159] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  242.360178] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  242.360199] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  242.360218] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  242.360237] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  242.360256] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  242.360274] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  242.360291] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  242.360309] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  242.360326] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  242.360343] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  242.360345] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  242.360362] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  242.360364] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  242.360382] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  242.360399] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  242.360416] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  242.360432] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  242.360452] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  242.360469] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  242.360486] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0
>[32m[  242.360502] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  242.360519] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  242.360542] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  242.360561] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  242.360580] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  242.360598] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  242.360617] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb -1
>[32m[  242.360635] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  242.360654] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  242.360672] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  242.360690] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  242.360708] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  242.360745] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  242.360764] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  242.360800] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  242.360818] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  242.360822] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  242.360897] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  242.382662] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  242.382689] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  242.382921] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  242.382941] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  242.382960] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  242.382979] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.383002] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  242.383072] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  242.383702] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  242.383884] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  242.383913] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  242.383932] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  242.383957] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  242.383976] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  242.383993] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  242.384023] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  242.384042] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  242.402155] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  242.402819] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  242.403004] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  242.403058] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  242.403087] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  242.403114] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  242.403133] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  242.403151] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  242.403174] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  242.403193] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  242.438033] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  242.438068] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  242.438108] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.438138] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  242.438160] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  242.438197] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  242.438222] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  242.438233] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  242.438275] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  242.442280] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  242.450879] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252fd8
>[32m[  242.450887] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2d288 state to ffff8801f1252fd8
>[32m[  242.450893] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1298958 state to ffff8801f1252fd8
>[32m[  242.450898] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2e758 state to ffff8801f1252fd8
>[32m[  242.450900] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  242.450903] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  242.450908] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2f538 state to ffff8801f1252fd8
>[32m[  242.450910] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [NOCRTC]
>[32m[  242.450912] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f538
>[32m[  242.450917] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2c008 state to ffff8801f1252fd8
>[32m[  242.450922] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129e678 state to ffff8801f1252fd8
>[32m[  242.450926] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2e9a8 state to ffff8801f1252fd8
>[32m[  242.450929] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [NOCRTC]
>[32m[  242.450931] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e9a8
>[32m[  242.450936] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2dbc8 state to ffff8801f1252fd8
>[32m[  242.450938] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  242.450940] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  242.450944] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2d038 state to ffff8801f1252fd8
>[32m[  242.450949] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2cde8 state to ffff8801f1252fd8
>[32m[  242.450951] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  242.450953] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  242.450956] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  242.450983] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2cde8 state to ffff8801f1252fd8
>[32m[  242.451333] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129e678 state to ffff8801f1252fd8
>[32m[  242.451339] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2cb98 state to ffff8801f1252fd8
>[32m[  242.451342] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [NOCRTC]
>[32m[  242.451344] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cb98
>[32m[  242.451347] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  242.451359] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2cb98 state to ffff8801f1252fd8
>[32m[  242.451364] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129e678 state to ffff8801f1252fd8
>[32m[  242.451369] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2e2b8 state to ffff8801f1252fd8
>[32m[  242.451371] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [NOCRTC]
>[32m[  242.451373] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e2b8
>[32m[  242.451378] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2cde8 state to ffff8801f1252fd8
>[32m[  242.451380] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  242.451382] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  242.451387] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2d288 state to ffff8801f1252fd8
>[32m[  242.451392] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f1252fd8
>[32m[  242.451396] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2d038 state to ffff8801f1252fd8
>[32m[  242.451398] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  242.451401] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  242.451405] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2e758 state to ffff8801f1252fd8
>[32m[  242.451407] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  242.451409] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  242.451414] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2dbc8 state to ffff8801f1252fd8
>[32m[  242.451418] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2f538 state to ffff8801f1252fd8
>[32m[  242.451420] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [NOCRTC]
>[32m[  242.451423] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f538
>[32m[  242.451427] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2e9a8 state to ffff8801f1252fd8
>[32m[  242.451429] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [NOCRTC]
>[32m[  242.451431] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e9a8
>[32m[  242.451439] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129e678
>[32m[  242.451442] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [CRTC:36:pipe A]
>[32m[  242.451444] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ec2cb98
>[32m[  242.451447] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  242.451496] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2e9a8 state to ffff8801f1252fd8
>[32m[  242.451501] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880210694a88 state to ffff8801f1252fd8
>[32m[  242.451506] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2c008 state to ffff8801f1252fd8
>[32m[  242.451508] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  242.451510] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  242.451515] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2f538 state to ffff8801f1252fd8
>[32m[  242.451517] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [NOCRTC]
>[32m[  242.451519] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f538
>[32m[  242.451524] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2cb98 state to ffff8801f1252fd8
>[32m[  242.451529] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9688008 state to ffff8801f1252fd8
>[32m[  242.451534] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2dbc8 state to ffff8801f1252fd8
>[32m[  242.451536] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  242.451538] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  242.451542] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2e2b8 state to ffff8801f1252fd8
>[32m[  242.451545] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [NOCRTC]
>[32m[  242.451547] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e2b8
>[32m[  242.451551] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2e758 state to ffff8801f1252fd8
>[32m[  242.451556] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2cde8 state to ffff8801f1252fd8
>[32m[  242.451558] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  242.451560] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  242.451564] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2d038 state to ffff8801f1252fd8
>[32m[  242.451567] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  242.451569] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  242.451574] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880210694a88
>[32m[  242.451577] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [CRTC:36:pipe A]
>[32m[  242.451579] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ec2e9a8
>[32m[  242.451582] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  242.451591] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020f9970e8 state to ffff8801f1252fd8
>[32m[  242.451594] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f9970e8 to [NOCRTC]
>[32m[  242.451597] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020f9970e8 to [CRTC:36:pipe A]
>[32m[  242.451602] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f9688008
>[32m[  242.451605] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [CRTC:46:pipe B]
>[32m[  242.451607] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ec2cb98
>[32m[  242.451610] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252fd8
>[32m[  242.451616] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880212b25058 state to ffff8801f1252fd8
>[32m[  242.451619] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880212b25058 to [NOCRTC]
>[32m[  242.451621] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880212b25058 to [CRTC:46:pipe B]
>[32m[  242.451627] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f968ae98 state to ffff8801f1252fd8
>[32m[  242.451629] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f968ae98
>[32m[  242.451631] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  242.451641] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  242.451644] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252fd8
>[32m[  242.451647] [0m[drm:drm_atomic_check_only] checking ffff8801f1252fd8
>[32m[  242.451654] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  242.451657] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  242.451659] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.451662] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  242.451694] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  242.451718] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  242.451742] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  242.451764] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  242.451770] [0m[drm:drm_atomic_commit] committing ffff8801f1252fd8
>[32m[  242.454641] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  242.454688] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252fd8
>[32m[  242.490928] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  242.491123] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  242.510081] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  242.510118] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  242.510145] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  242.510166] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  242.548420] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  242.548493] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  242.548497] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  242.548500] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  242.548502] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  242.548504] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  242.548506] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  242.548508] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  242.548510] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  242.548512] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  242.548514] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  242.548516] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  242.548518] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  242.548520] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  242.548623] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  242.548654] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  242.623740] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  242.623763] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  242.625821] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  242.625827] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  242.625831] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  242.625847] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  242.625959] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  242.625961] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  242.625963] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  242.626144] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  242.626148] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  242.626150] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  242.626153] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  242.626155] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  242.626157] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  242.626160] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  242.626162] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  242.626164] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  242.626166] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  242.626168] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  242.626171] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  242.626173] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  242.626175] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  242.626177] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  242.626179] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  242.626182] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  242.626184] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  242.626186] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  242.626382] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  242.626390] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801fd72e3a8 state to ffff8801f1256f98
>[32m[  242.626396] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121ae98 state to ffff8801f1256f98
>[32m[  242.626399] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  242.626405] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.626408] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  242.626414] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  242.637977] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  242.638036] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  242.638064] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  242.638092] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  242.640658] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.643214] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.645775] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.648327] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.650878] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.653432] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.655983] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.658557] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.661091] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.663622] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.666153] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.668681] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.671209] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.673737] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.676263] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.678791] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.681319] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.683846] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.686372] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.688899] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.691426] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.693951] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.696478] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.699055] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.701580] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.704106] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.706634] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.709163] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.711692] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.714221] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.716751] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.719277] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  242.719284] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  242.719288] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  242.719427] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.719435] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff88020e0493f8 state to ffff8801f1254a68
>[32m[  242.719438] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.719441] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  242.719443] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  242.719447] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.719459] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.719472] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.719539] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest legacy-pipe-A-tiling-none
>[32m[  242.719791] [0m[drm:drm_mode_addfb2] [FB:98]
>[32m[  242.726653] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  242.726674] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  242.726683] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.726689] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129ae98 state to ffff8801f1254a68
>[32m[  242.726694] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212fc28 state to ffff8801f1254a68
>[32m[  242.726700] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129ae98
>[32m[  242.726702] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [CRTC:36:pipe A]
>[32m[  242.726704] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:98] for plane state ffff88021212fc28
>[32m[  242.726707] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1254a68
>[32m[  242.726725] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f5058d88 state to ffff8801f1254a68
>[32m[  242.726736] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5058d88 to [NOCRTC]
>[32m[  242.726739] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5058d88 to [CRTC:36:pipe A]
>[32m[  242.726743] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.726747] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  242.726750] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  242.726779] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 98
>[32m[  242.726801] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  242.726807] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.734669] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.734703] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.734748] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.734753] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212de18 state to ffff8801f1254a68
>[32m[  242.734756] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  242.734758] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  242.734760] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.734763] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.734775] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.734788] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.734809] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.734814] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212c4a8 state to ffff8801f1254a68
>[32m[  242.734816] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [NOCRTC]
>[32m[  242.734818] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c4a8
>[32m[  242.734820] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.734823] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.734831] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.734841] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.751302] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  242.751326] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.751333] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8802129ab7e8 state to ffff8801f1254a68
>[32m[  242.751338] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212c258 state to ffff8801f1254a68
>[32m[  242.751341] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8802129ab7e8
>[32m[  242.751343] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c258 to [NOCRTC]
>[32m[  242.751345] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c258
>[32m[  242.751348] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1254a68
>[32m[  242.751356] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff8801f1254a68
>[32m[  242.751359] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048918 to [NOCRTC]
>[32m[  242.751362] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.751364] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  242.751366] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  242.751368] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  242.751371] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.751373] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  242.751375] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: n, active: n
>[32m[  242.751377] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1254a68
>[32m[  242.751407] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb -1
>[32m[  242.751430] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  242.751434] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.751493] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  242.772177] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  242.772205] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  242.772438] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  242.772459] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  242.772480] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  242.772500] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  242.772522] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.772545] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  242.772595] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  242.772603] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.772617] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.772654] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.772659] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212ebf8 state to ffff8801f1254a68
>[32m[  242.772662] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [NOCRTC]
>[32m[  242.772664] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212ebf8
>[32m[  242.772666] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.772669] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.772680] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.772693] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.772713] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.772719] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111ccb98 state to ffff8801f1254a68
>[32m[  242.772721] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [NOCRTC]
>[32m[  242.772723] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccb98
>[32m[  242.772725] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.772728] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.772736] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.772746] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.772759] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  242.772778] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.772783] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9688008 state to ffff8801f1254a68
>[32m[  242.772788] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cf098 state to ffff8801f1254a68
>[32m[  242.772790] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9688008
>[32m[  242.772792] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [NOCRTC]
>[32m[  242.772794] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf098
>[32m[  242.772797] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1254a68
>[32m[  242.772800] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.772804] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.772824] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.772833] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.772861] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.772866] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cd288 state to ffff8801f1254a68
>[32m[  242.772868] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [NOCRTC]
>[32m[  242.772870] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd288
>[32m[  242.772872] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.772874] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.772882] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.772892] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.772910] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.772915] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111ccde8 state to ffff8801f1254a68
>[32m[  242.772917] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [NOCRTC]
>[32m[  242.772919] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccde8
>[32m[  242.772920] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.772923] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.772930] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.772940] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.801341] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  242.801654] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  242.801833] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  242.808350] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  242.808371] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  242.808380] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.808386] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121ae98 state to ffff8801f1254a68
>[32m[  242.808391] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cf2e8 state to ffff8801f1254a68
>[32m[  242.808397] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121ae98
>[32m[  242.808399] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [CRTC:36:pipe A]
>[32m[  242.808401] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8802111cf2e8
>[32m[  242.808404] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1254a68
>[32m[  242.808412] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f5059298 state to ffff8801f1254a68
>[32m[  242.808415] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5059298 to [NOCRTC]
>[32m[  242.808418] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5059298 to [CRTC:36:pipe A]
>[32m[  242.808422] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.808426] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  242.808429] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  242.808460] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 99
>[32m[  242.808483] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  242.808488] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.817804] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.817836] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.817878] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.817883] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cc948 state to ffff8801f1254a68
>[32m[  242.817888] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1219bf8 state to ffff8801f1254a68
>[32m[  242.817891] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [CRTC:36:pipe A]
>[32m[  242.817893] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff8802111cc948
>[32m[  242.817895] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.817922] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 66
>[32m[  242.817945] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  242.817949] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.834424] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.834445] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.834495] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.834500] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cf9d8 state to ffff8801f1254a68
>[32m[  242.834505] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121ae98 state to ffff8801f1254a68
>[32m[  242.834507] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [CRTC:36:pipe A]
>[32m[  242.834510] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8802111cf9d8
>[32m[  242.834512] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.834538] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 100
>[32m[  242.834561] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  242.834565] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.851060] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.851073] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.851100] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff88020ffdc948
>[32m[  242.851126] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 100
>[32m[  242.851149] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  242.868117] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1254a68
>[32m[  242.868126] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0495c8 state to ffff8801f1254a68
>[32m[  242.868129] [0m[drm:drm_atomic_check_only] checking ffff8801f1254a68
>[32m[  242.868132] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.868134] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  242.868137] [0m[drm:drm_atomic_commit] committing ffff8801f1254a68
>[32m[  242.868148] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1254a68
>[32m[  242.868161] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1254a68
>[32m[  242.868209] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  242.874045] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  242.874060] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  242.874069] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  242.874075] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121dd28 state to ffff8801f1255508
>[32m[  242.874079] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9531038 state to ffff8801f1255508
>[32m[  242.874085] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121dd28
>[32m[  242.874087] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [CRTC:36:pipe A]
>[32m[  242.874089] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8801f9531038
>[32m[  242.874092] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1255508
>[32m[  242.874100] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f5058d88 state to ffff8801f1255508
>[32m[  242.874103] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5058d88 to [NOCRTC]
>[32m[  242.874108] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048ae8 state to ffff8801f1255508
>[32m[  242.874110] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048ae8 to [CRTC:36:pipe A]
>[32m[  242.874114] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  242.874117] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  242.874121] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  242.874123] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  242.874125] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  242.874127] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:36:pipe A]
>[32m[  242.874130] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  242.874132] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1255508
>[32m[  242.874138] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9533538 state to ffff8801f1255508
>[32m[  242.874143] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f95304a8 state to ffff8801f1255508
>[32m[  242.874146] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1255508
>[32m[  242.874174] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  242.874197] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  242.874220] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  242.874241] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  242.874262] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  242.874282] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  242.874303] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  242.874323] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  242.874342] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  242.874361] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  242.874380] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  242.874383] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  242.874401] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  242.874403] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  242.874422] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  242.874440] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  242.874459] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  242.874476] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  242.874497] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  242.874515] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  242.874534] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  242.874553] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  242.874571] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:100, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  242.874595] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 102
>[32m[  242.874614] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  242.874634] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 66
>[32m[  242.874654] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  242.874673] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 100
>[32m[  242.874692] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  242.874730] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  242.874749] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  242.874754] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  242.877733] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  242.902439] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  242.902467] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  242.902701] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  242.902724] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  242.902743] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  242.902763] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  242.902784] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.902808] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  242.902838] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  242.903581] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  242.903763] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  242.903792] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  242.903812] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  242.903838] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  242.903857] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  242.903875] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  242.903898] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  242.903918] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  242.938840] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  242.938872] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  242.938912] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  242.938924] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  242.938942] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  242.938979] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  242.938984] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95339d8 state to ffff8801f1255508
>[32m[  242.939151] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9694a88 state to ffff8801f1255508
>[32m[  242.939154] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  242.939156] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  242.939158] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  242.939191] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  242.939212] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  242.939217] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  242.955481] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  242.955495] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  242.955523] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  242.955528] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9533538 state to ffff8801f1255508
>[32m[  242.955534] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802145f0958 state to ffff8801f1255508
>[32m[  242.955536] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533538 to [NOCRTC]
>[32m[  242.955538] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533538
>[32m[  242.955540] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  242.955566] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  242.955589] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  242.955593] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  242.972146] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  242.972161] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  243.022344] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  243.022353] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049228 state to ffff8801f1255508
>[32m[  243.022358] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e2548 state to ffff8801f1255508
>[32m[  243.022361] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  243.022365] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.022368] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  243.022373] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  243.038799] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  243.038814] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  243.038884] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  243.039332] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  243.039478] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  243.045347] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  243.045369] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  243.045377] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  243.045383] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126ca88 state to ffff8801f1255508
>[32m[  243.045388] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9533788 state to ffff8801f1255508
>[32m[  243.045394] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126ca88
>[32m[  243.045396] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [CRTC:36:pipe A]
>[32m[  243.045398] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801f9533788
>[32m[  243.045401] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1255508
>[32m[  243.045410] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0495c8 state to ffff8801f1255508
>[32m[  243.045413] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0495c8 to [NOCRTC]
>[32m[  243.045415] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0495c8 to [CRTC:36:pipe A]
>[32m[  243.045419] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  243.045423] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.045426] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  243.045457] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 108
>[32m[  243.045480] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.045485] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  243.055473] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  243.055491] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  243.055533] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  243.055538] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9530948 state to ffff8801f1255508
>[32m[  243.055544] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88020f82dd28 state to ffff8801f1255508
>[32m[  243.055546] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [CRTC:36:pipe A]
>[32m[  243.055548] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801f9530948
>[32m[  243.055550] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  243.055578] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 100
>[32m[  243.055600] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  243.055605] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  243.072137] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  243.072149] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  243.072182] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  243.072187] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9531728 state to ffff8801f1255508
>[32m[  243.072193] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129ae98 state to ffff8801f1255508
>[32m[  243.072195] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [CRTC:36:pipe A]
>[32m[  243.072197] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801f9531728
>[32m[  243.072199] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  243.072226] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 109
>[32m[  243.072248] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  243.072253] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  243.088797] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  243.088811] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  243.088880] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801f9533538
>[32m[  243.088907] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 109
>[32m[  243.088930] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.105647] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  243.105655] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048748 state to ffff8801f1255508
>[32m[  243.105661] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1255508
>[32m[  243.105663] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  243.105667] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.105670] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  243.105675] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  243.122118] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  243.122129] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  243.122382] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  243.128697] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  243.128717] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  243.128726] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.128732] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129ae98 state to ffff8801f1256a48
>[32m[  243.128737] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9532bf8 state to ffff8801f1256a48
>[32m[  243.128742] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129ae98
>[32m[  243.128745] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [CRTC:36:pipe A]
>[32m[  243.128747] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801f9532bf8
>[32m[  243.128749] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  243.128758] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049228 state to ffff8801f1256a48
>[32m[  243.128761] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e049228 to [NOCRTC]
>[32m[  243.128766] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f5059298 state to ffff8801f1256a48
>[32m[  243.128768] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5059298 to [CRTC:36:pipe A]
>[32m[  243.128772] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.128775] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  243.128778] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  243.128781] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  243.128783] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.128785] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  243.128787] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  243.128789] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  243.128795] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9532e48 state to ffff8801f1256a48
>[32m[  243.128800] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec51728 state to ffff8801f1256a48
>[32m[  243.128803] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  243.128832] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  243.128854] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  243.128875] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  243.128896] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  243.128916] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  243.128937] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  243.128957] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  243.128976] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  243.128994] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  243.129029] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  243.129049] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  243.129055] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  243.129076] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  243.129097] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  243.129118] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  243.129139] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  243.129162] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  243.129183] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  243.129204] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  243.129224] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:100, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  243.129245] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:109, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  243.129271] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 110
>[32m[  243.129293] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  243.129316] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 100
>[32m[  243.129356] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  243.129377] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 109
>[32m[  243.129398] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  243.129439] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  243.129460] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  243.129466] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.132254] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  243.156957] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  243.156985] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  243.157322] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  243.157351] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  243.157374] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  243.157394] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  243.157416] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  243.157439] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  243.157471] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  243.158251] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  243.158434] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  243.158465] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  243.158486] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  243.158512] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  243.158532] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  243.158550] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  243.158575] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  243.158595] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  243.193338] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  243.193369] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  243.193408] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  243.193420] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.193439] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.193481] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.193487] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e07b2e8 state to ffff8801f1256a48
>[32m[  243.193492] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121c138 state to ffff8801f1256a48
>[32m[  243.193494] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b2e8 to [NOCRTC]
>[32m[  243.193496] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b2e8
>[32m[  243.193498] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.193522] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  243.193542] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  243.193547] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.209941] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.209953] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.209980] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.209986] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e07b788 state to ffff8801f1256a48
>[32m[  243.210031] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121e678 state to ffff8801f1256a48
>[32m[  243.210034] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b788 to [NOCRTC]
>[32m[  243.210037] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b788
>[32m[  243.210041] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.210071] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  243.210097] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  243.210102] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.226562] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.226576] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.276642] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  243.276953] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  243.277134] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  243.283558] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  243.283581] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  243.283589] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.283595] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9696678 state to ffff8801f1256a48
>[32m[  243.283600] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ee52e48 state to ffff8801f1256a48
>[32m[  243.283605] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9696678
>[32m[  243.283608] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [CRTC:36:pipe A]
>[32m[  243.283610] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88020ee52e48
>[32m[  243.283613] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  243.283621] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f5058d88 state to ffff8801f1256a48
>[32m[  243.283624] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5058d88 to [NOCRTC]
>[32m[  243.283627] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5058d88 to [CRTC:36:pipe A]
>[32m[  243.283630] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.283635] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  243.283638] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  243.283669] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 112
>[32m[  243.283691] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.283697] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.293075] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.293093] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.293136] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.293142] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802121329a8 state to ffff8801f1256a48
>[32m[  243.293148] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e5d28 state to ffff8801f1256a48
>[32m[  243.293150] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [CRTC:36:pipe A]
>[32m[  243.293152] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802121329a8
>[32m[  243.293154] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.293182] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 109
>[32m[  243.293205] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  243.293209] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.309700] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.309712] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.309746] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.309752] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212131288 state to ffff8801f1256a48
>[32m[  243.309757] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff8801f1256a48
>[32m[  243.309759] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [CRTC:36:pipe A]
>[32m[  243.309761] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff880212131288
>[32m[  243.309763] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.309790] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 113
>[32m[  243.309812] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  243.309817] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.326320] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.326334] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.326360] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff88020ec2d038
>[32m[  243.326386] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 113
>[32m[  243.326408] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.343415] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.343424] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048578 state to ffff8801f1256a48
>[32m[  243.343426] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.343430] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.343432] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  243.343435] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.343447] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.343460] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.343508] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  243.349363] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  243.349384] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  243.349392] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.349399] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126efc8 state to ffff8801f1256a48
>[32m[  243.349403] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2c4a8 state to ffff8801f1256a48
>[32m[  243.349409] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126efc8
>[32m[  243.349411] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [CRTC:36:pipe A]
>[32m[  243.349413] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88020ec2c4a8
>[32m[  243.349416] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  243.349424] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f5059298 state to ffff8801f1256a48
>[32m[  243.349427] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5059298 to [NOCRTC]
>[32m[  243.349432] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048748 state to ffff8801f1256a48
>[32m[  243.349434] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048748 to [CRTC:36:pipe A]
>[32m[  243.349438] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.349441] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  243.349445] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  243.349447] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  243.349449] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.349451] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:36:pipe A]
>[32m[  243.349454] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  243.349456] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  243.349462] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2e2b8 state to ffff8801f1256a48
>[32m[  243.349466] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2ee48 state to ffff8801f1256a48
>[32m[  243.349469] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  243.349498] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  243.349520] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  243.349543] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  243.349563] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  243.349585] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  243.349605] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  243.349626] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  243.349646] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  243.349666] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  243.349685] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  243.349703] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  243.349706] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  243.349724] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  243.349727] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  243.349745] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  243.349764] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  243.349782] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  243.349800] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  243.349821] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  243.349839] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  243.349858] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:112, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  243.349877] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:109, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  243.349895] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:113, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  243.349919] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 114
>[32m[  243.349939] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  243.349959] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 109
>[32m[  243.349978] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  243.349997] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 113
>[32m[  243.350752] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  243.350791] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  243.350819] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  243.350849] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.353149] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  243.377704] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  243.377732] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  243.377965] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  243.377988] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  243.378127] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  243.378149] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  243.378181] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  243.378213] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  243.378244] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  243.378890] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  243.379128] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  243.379168] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  243.379188] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  243.379222] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  243.379241] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  243.379259] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  243.379282] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  243.379302] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  243.414125] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  243.414156] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  243.414195] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  243.414208] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.414227] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.414271] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.414276] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2e758 state to ffff8801f1256a48
>[32m[  243.414281] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802106c5d28 state to ffff8801f1256a48
>[32m[  243.414283] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  243.414286] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  243.414288] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.414311] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  243.414331] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  243.414335] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.430764] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.430777] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.430806] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.430811] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2e2b8 state to ffff8801f1256a48
>[32m[  243.430817] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129ae98 state to ffff8801f1256a48
>[32m[  243.430820] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [NOCRTC]
>[32m[  243.430822] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e2b8
>[32m[  243.430824] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.430850] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  243.430872] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  243.430877] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.447424] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.447436] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.497623] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.497631] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0495c8 state to ffff8801f1256a48
>[32m[  243.497637] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1256a48
>[32m[  243.497639] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.497645] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.497648] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  243.497652] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.514102] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.514114] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.514176] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  243.514486] [0m[drm:drm_mode_addfb2] [FB:115]
>[32m[  243.514617] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  243.520410] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  243.520426] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  243.520435] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.520441] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1299bf8 state to ffff8801f1256a48
>[32m[  243.520446] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cd288 state to ffff8801f1256a48
>[32m[  243.520452] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1299bf8
>[32m[  243.520454] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd288 to [CRTC:36:pipe A]
>[32m[  243.520456] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801fb5cd288
>[32m[  243.520459] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1256a48
>[32m[  243.520468] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048578 state to ffff8801f1256a48
>[32m[  243.520471] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048578 to [NOCRTC]
>[32m[  243.520473] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048578 to [CRTC:36:pipe A]
>[32m[  243.520477] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.520482] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.520485] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  243.520517] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 116
>[32m[  243.520539] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.520544] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.530772] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.530788] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.530824] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.530829] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ce508 state to ffff8801f1256a48
>[32m[  243.530834] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1256a48
>[32m[  243.530837] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [CRTC:36:pipe A]
>[32m[  243.530839] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8801fb5ce508
>[32m[  243.530841] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.530869] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 113
>[32m[  243.530891] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  243.530896] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.547437] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.547448] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.547482] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.547487] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cde18 state to ffff8801f1256a48
>[32m[  243.547492] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1299bf8 state to ffff8801f1256a48
>[32m[  243.547495] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cde18 to [CRTC:36:pipe A]
>[32m[  243.547497] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5cde18
>[32m[  243.547499] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.547526] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 117
>[32m[  243.547548] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  243.547553] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.564100] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.564113] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.564139] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5cdbc8
>[32m[  243.564168] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 117
>[32m[  243.564190] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.580966] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256a48
>[32m[  243.580975] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048e88 state to ffff8801f1256a48
>[32m[  243.580980] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129dd28 state to ffff8801f1256a48
>[32m[  243.580983] [0m[drm:drm_atomic_check_only] checking ffff8801f1256a48
>[32m[  243.581125] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.581129] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  243.581134] [0m[drm:drm_atomic_commit] committing ffff8801f1256a48
>[32m[  243.597420] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256a48
>[32m[  243.597431] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256a48
>[32m[  243.597604] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  243.607366] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252fd8
>[32m[  243.607373] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cfc28 state to ffff8801f1252fd8
>[32m[  243.607378] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1299bf8 state to ffff8801f1252fd8
>[32m[  243.607382] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cf538 state to ffff8801f1252fd8
>[32m[  243.607384] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf538 to [NOCRTC]
>[32m[  243.607386] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf538
>[32m[  243.607390] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cd4d8 state to ffff8801f1252fd8
>[32m[  243.607391] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [NOCRTC]
>[32m[  243.607393] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd4d8
>[32m[  243.607397] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cf9d8 state to ffff8801f1252fd8
>[32m[  243.607400] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5ce9a8 state to ffff8801f1252fd8
>[32m[  243.607402] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce9a8 to [NOCRTC]
>[32m[  243.607404] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce9a8
>[32m[  243.607408] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cf2e8 state to ffff8801f1252fd8
>[32m[  243.607409] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf2e8 to [NOCRTC]
>[32m[  243.607411] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf2e8
>[32m[  243.607415] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128e9978 state to ffff8801f1252fd8
>[32m[  243.607418] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  243.607439] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128e9978 state to ffff8801f1252fd8
>[32m[  243.607444] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1299bf8 state to ffff8801f1252fd8
>[32m[  243.607448] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128e9728 state to ffff8801f1252fd8
>[32m[  243.607449] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [NOCRTC]
>[32m[  243.607451] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9728
>[32m[  243.607453] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  243.607464] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128e9728 state to ffff8801f1252fd8
>[32m[  243.607468] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1299bf8 state to ffff8801f1252fd8
>[32m[  243.607472] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128eabf8 state to ffff8801f1252fd8
>[32m[  243.607473] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [NOCRTC]
>[32m[  243.607475] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eabf8
>[32m[  243.607479] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128e9978 state to ffff8801f1252fd8
>[32m[  243.607480] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [NOCRTC]
>[32m[  243.607482] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9978
>[32m[  243.607486] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128e8258 state to ffff8801f1252fd8
>[32m[  243.607489] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128eb538 state to ffff8801f1252fd8
>[32m[  243.607491] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [NOCRTC]
>[32m[  243.607492] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb538
>[32m[  243.607496] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128ea2b8 state to ffff8801f1252fd8
>[32m[  243.607497] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [NOCRTC]
>[32m[  243.607499] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128ea2b8
>[32m[  243.607503] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128e86f8 state to ffff8801f1252fd8
>[32m[  243.607506] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128eb098 state to ffff8801f1252fd8
>[32m[  243.607508] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb098 to [NOCRTC]
>[32m[  243.607510] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb098
>[32m[  243.607513] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802135a3098 state to ffff8801f1252fd8
>[32m[  243.607515] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [NOCRTC]
>[32m[  243.607517] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a3098
>[32m[  243.607523] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1299bf8
>[32m[  243.607525] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [CRTC:36:pipe A]
>[32m[  243.607527] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802128e9728
>[32m[  243.607529] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  243.607537] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f97893f8 state to ffff8801f1252fd8
>[32m[  243.607539] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97893f8 to [NOCRTC]
>[32m[  243.607544] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f5059448 state to ffff8801f1252fd8
>[32m[  243.607545] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5059448 to [CRTC:36:pipe A]
>[32m[  243.607548] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  243.607578] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802135a3098 state to ffff8801f1252fd8
>[32m[  243.607583] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1299bf8 state to ffff8801f1252fd8
>[32m[  243.607587] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802135a0de8 state to ffff8801f1252fd8
>[32m[  243.607588] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a0de8 to [NOCRTC]
>[32m[  243.607590] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a0de8
>[32m[  243.607594] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212945978 state to ffff8801f1252fd8
>[32m[  243.607595] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212945978 to [NOCRTC]
>[32m[  243.607597] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212945978
>[32m[  243.607600] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802129462b8 state to ffff8801f1252fd8
>[32m[  243.607605] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212e9a8 state to ffff8801f1252fd8
>[32m[  243.607606] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [NOCRTC]
>[32m[  243.607608] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212e9a8
>[32m[  243.607612] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212fc28 state to ffff8801f1252fd8
>[32m[  243.607613] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [NOCRTC]
>[32m[  243.607615] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212fc28
>[32m[  243.607618] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212c6f8 state to ffff8801f1252fd8
>[32m[  243.607622] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212de18 state to ffff8801f1252fd8
>[32m[  243.607624] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  243.607625] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  243.607629] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212c4a8 state to ffff8801f1252fd8
>[32m[  243.607630] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [NOCRTC]
>[32m[  243.607632] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c4a8
>[32m[  243.607636] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1299bf8
>[32m[  243.607638] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [CRTC:36:pipe A]
>[32m[  243.607639] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802135a3098
>[32m[  243.607642] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  243.607646] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135becb8 state to ffff8801f1252fd8
>[32m[  243.607649] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135becb8 to [NOCRTC]
>[32m[  243.607652] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f5059448 state to ffff8801f1252fd8
>[32m[  243.607654] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f5059448 to [CRTC:36:pipe A]
>[32m[  243.607659] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129a548 state to ffff8801f1252fd8
>[32m[  243.607663] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129a548
>[32m[  243.607665] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802129462b8 to [CRTC:46:pipe B]
>[32m[  243.607666] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802129462b8
>[32m[  243.607668] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252fd8
>[32m[  243.607671] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135becb8 to [CRTC:46:pipe B]
>[32m[  243.607676] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129efc8 state to ffff8801f1252fd8
>[32m[  243.607678] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f129efc8
>[32m[  243.607679] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  243.607681] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  243.607683] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252fd8
>[32m[  243.607686] [0m[drm:drm_atomic_check_only] checking ffff8801f1252fd8
>[32m[  243.607689] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  243.607691] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  243.607692] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  243.607694] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  243.607698] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  243.607700] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  243.607702] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.607704] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  243.607706] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  243.607708] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  243.607711] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  243.607713] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252fd8
>[32m[  243.607717] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  243.607746] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  243.607767] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  243.607789] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  243.607809] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  243.607829] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  243.607850] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  243.607869] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  243.607888] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  243.607906] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  243.607909] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  243.607927] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  243.607929] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  243.607947] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  243.607965] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  243.607983] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  243.608001] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  243.608043] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  243.608070] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  243.608089] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:116, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  243.608107] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:113, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  243.608125] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:117, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  243.608128] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252fd8
>[32m[  243.608148] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  243.608167] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  243.608188] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  243.608207] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  243.608227] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  243.608245] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  243.608263] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  243.608281] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  243.608298] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  243.608315] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  243.608332] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  243.608334] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  243.608351] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  243.608353] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  243.608370] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  243.608387] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  243.608404] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  243.608421] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  243.608440] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  243.608457] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  243.608474] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0
>[32m[  243.608491] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  243.608508] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  243.608531] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  243.608550] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  243.608569] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  243.608588] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  243.608606] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  243.608624] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  243.608643] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  243.608661] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  243.608699] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  243.608718] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  243.608754] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  243.608772] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  243.608777] [0m[drm:drm_atomic_commit] committing ffff8801f1252fd8
>[32m[  243.608858] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  243.632397] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  243.632424] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  243.632659] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  243.632679] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  243.632698] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  243.632717] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  243.632741] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  243.632771] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  243.633424] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  243.633606] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  243.633634] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  243.633654] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  243.633679] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  243.633698] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  243.633715] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  243.633737] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  243.633756] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  243.651872] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  243.652537] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  243.652722] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  243.652752] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  243.652772] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  243.652798] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  243.652817] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  243.652835] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  243.652858] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  243.652877] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  243.687696] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  243.687726] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  243.687766] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  243.687796] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  243.687818] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  243.687855] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  243.687871] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  243.687935] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252fd8
>[32m[  243.691946] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  243.700210] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  243.700218] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cebf8 state to ffff8801f1253fc8
>[32m[  243.700225] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121dd28 state to ffff8801f1253fc8
>[32m[  243.700230] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cd288 state to ffff8801f1253fc8
>[32m[  243.700232] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [NOCRTC]
>[32m[  243.700234] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd288
>[32m[  243.700239] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cc4a8 state to ffff8801f1253fc8
>[32m[  243.700241] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [NOCRTC]
>[32m[  243.700243] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc4a8
>[32m[  243.700248] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cf098 state to ffff8801f1253fc8
>[32m[  243.700253] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1219bf8 state to ffff8801f1253fc8
>[32m[  243.700258] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cfc28 state to ffff8801f1253fc8
>[32m[  243.700260] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cfc28 to [NOCRTC]
>[32m[  243.700262] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cfc28
>[32m[  243.700266] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111ccb98 state to ffff8801f1253fc8
>[32m[  243.700269] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [NOCRTC]
>[32m[  243.700271] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccb98
>[32m[  243.700275] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111ccde8 state to ffff8801f1253fc8
>[32m[  243.700278] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.700303] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111ccde8 state to ffff8801f1253fc8
>[32m[  243.700309] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9692e98 state to ffff8801f1253fc8
>[32m[  243.700313] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cc6f8 state to ffff8801f1253fc8
>[32m[  243.700315] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  243.700317] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  243.700320] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.700332] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cc6f8 state to ffff8801f1253fc8
>[32m[  243.700336] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9692e98 state to ffff8801f1253fc8
>[32m[  243.700341] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cf2e8 state to ffff8801f1253fc8
>[32m[  243.700343] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [NOCRTC]
>[32m[  243.700345] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf2e8
>[32m[  243.700349] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111ccde8 state to ffff8801f1253fc8
>[32m[  243.700352] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [NOCRTC]
>[32m[  243.700354] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccde8
>[32m[  243.700358] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cc948 state to ffff8801f1253fc8
>[32m[  243.700363] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9694a88 state to ffff8801f1253fc8
>[32m[  243.700367] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111ccb98 state to ffff8801f1253fc8
>[32m[  243.700369] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [NOCRTC]
>[32m[  243.700371] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccb98
>[32m[  243.700376] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cf9d8 state to ffff8801f1253fc8
>[32m[  243.700378] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  243.700380] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  243.700384] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cfc28 state to ffff8801f1253fc8
>[32m[  243.700389] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cee48 state to ffff8801f1253fc8
>[32m[  243.700391] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cee48 to [NOCRTC]
>[32m[  243.700393] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cee48
>[32m[  243.700397] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cf098 state to ffff8801f1253fc8
>[32m[  243.700399] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [NOCRTC]
>[32m[  243.700401] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf098
>[32m[  243.700408] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9692e98
>[32m[  243.700410] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [CRTC:36:pipe A]
>[32m[  243.700413] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802111cc6f8
>[32m[  243.700415] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.700445] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cf098 state to ffff8801f1253fc8
>[32m[  243.700450] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9694a88 state to ffff8801f1253fc8
>[32m[  243.700455] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cc4a8 state to ffff8801f1253fc8
>[32m[  243.700457] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [NOCRTC]
>[32m[  243.700459] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc4a8
>[32m[  243.700463] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cee48 state to ffff8801f1253fc8
>[32m[  243.700465] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cee48 to [NOCRTC]
>[32m[  243.700467] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cee48
>[32m[  243.700472] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cd288 state to ffff8801f1253fc8
>[32m[  243.700477] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9696678 state to ffff8801f1253fc8
>[32m[  243.700481] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cfc28 state to ffff8801f1253fc8
>[32m[  243.700483] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cfc28 to [NOCRTC]
>[32m[  243.700485] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cfc28
>[32m[  243.700490] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cebf8 state to ffff8801f1253fc8
>[32m[  243.700492] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [NOCRTC]
>[32m[  243.700494] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cebf8
>[32m[  243.700498] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cf9d8 state to ffff8801f1253fc8
>[32m[  243.700503] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cc6f8 state to ffff8801f1253fc8
>[32m[  243.700505] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  243.700507] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  243.700511] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111ccb98 state to ffff8801f1253fc8
>[32m[  243.700513] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [NOCRTC]
>[32m[  243.700515] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccb98
>[32m[  243.700520] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f9694a88
>[32m[  243.700522] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [CRTC:36:pipe A]
>[32m[  243.700525] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802111cf098
>[32m[  243.700527] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1253fc8
>[32m[  243.700535] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f50586c8 state to ffff8801f1253fc8
>[32m[  243.700539] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f50586c8 to [NOCRTC]
>[32m[  243.700542] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f50586c8 to [CRTC:36:pipe A]
>[32m[  243.700547] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f9696678
>[32m[  243.700549] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [CRTC:46:pipe B]
>[32m[  243.700551] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802111cd288
>[32m[  243.700554] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253fc8
>[32m[  243.700560] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211e0d5c8 state to ffff8801f1253fc8
>[32m[  243.700562] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880211e0d5c8 to [NOCRTC]
>[32m[  243.700565] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880211e0d5c8 to [CRTC:46:pipe B]
>[32m[  243.700570] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9692e98 state to ffff8801f1253fc8
>[32m[  243.700572] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f9692e98
>[32m[  243.700574] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  243.700577] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  243.700579] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253fc8
>[32m[  243.700582] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  243.700589] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  243.700592] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  243.700594] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.700597] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  243.700628] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  243.700652] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.700675] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  243.700696] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.700703] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  243.704325] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.704374] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  243.741403] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  243.741499] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  243.762162] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  243.762197] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  243.762223] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  243.762244] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  243.800541] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  243.800616] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  243.800619] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  243.800621] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  243.800624] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  243.800626] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  243.800628] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  243.800630] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  243.800632] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  243.800634] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  243.800636] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  243.800638] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  243.800640] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  243.800642] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  243.800739] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  243.800771] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  243.875875] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  243.875898] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  243.877944] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  243.877949] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  243.877953] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  243.877967] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  243.878154] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  243.878157] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  243.878159] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  243.878317] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  243.878320] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  243.878322] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  243.878324] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  243.878326] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  243.878328] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  243.878330] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  243.878333] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  243.878335] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  243.878337] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  243.878339] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  243.878341] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  243.878343] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  243.878345] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  243.878347] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  243.878349] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  243.878351] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  243.878353] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  243.878355] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  243.878526] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  243.878534] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801fd72e008 state to ffff8801f1253fc8
>[32m[  243.878539] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126dd28 state to ffff8801f1253fc8
>[32m[  243.878542] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  243.878548] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  243.878551] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  243.878556] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  243.887663] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.887676] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  243.887702] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  243.887728] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  243.890290] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.892836] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.895389] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.897941] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.900491] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.903060] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.905613] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.908163] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.910717] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.913266] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.915819] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.918370] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.920918] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.923469] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.926031] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.928580] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.931132] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.933682] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.936230] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.938780] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.941328] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.943879] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.946428] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.948978] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.951577] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.954128] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.956685] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.959248] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.961801] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.964352] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.966904] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.969455] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  243.969462] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  243.969466] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  243.969609] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  243.969616] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8801f9788578 state to ffff8801f1253fc8
>[32m[  243.969619] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  243.969622] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  243.969624] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  243.969628] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  243.969639] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.969645] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  243.969708] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest legacy-pipe-A-tiling-x
>[32m[  243.969940] [0m[drm:drm_mode_addfb2] [FB:97]
>[32m[  243.976415] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  243.976436] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  243.976445] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  243.976452] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff8801f1253fc8
>[32m[  243.976457] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff880212131978 state to ffff8801f1253fc8
>[32m[  243.976462] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f95e12a8
>[32m[  243.976465] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [CRTC:36:pipe A]
>[32m[  243.976467] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff880212131978
>[32m[  243.976470] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1253fc8
>[32m[  243.976478] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e908bd8 state to ffff8801f1253fc8
>[32m[  243.976481] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e908bd8 to [NOCRTC]
>[32m[  243.976484] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e908bd8 to [CRTC:36:pipe A]
>[32m[  243.976488] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  243.976492] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  243.976495] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  243.976524] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 97
>[32m[  243.976547] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  243.976552] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  243.984383] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.984417] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  243.984460] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  243.984466] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2c008 state to ffff8801f1253fc8
>[32m[  243.984469] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  243.984471] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  243.984473] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  243.984476] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  243.984489] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.984493] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  243.984514] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  243.984518] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2dbc8 state to ffff8801f1253fc8
>[32m[  243.984521] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  243.984522] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  243.984524] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  243.984527] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  243.984532] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  243.984537] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  244.001024] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  244.001048] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  244.001055] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff88020ec9c138 state to ffff8801f1253fc8
>[32m[  244.001061] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2c4a8 state to ffff8801f1253fc8
>[32m[  244.001063] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020ec9c138
>[32m[  244.001065] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [NOCRTC]
>[32m[  244.001067] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c4a8
>[32m[  244.001070] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253fc8
>[32m[  244.001078] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789968 state to ffff8801f1253fc8
>[32m[  244.001081] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9789968 to [NOCRTC]
>[32m[  244.001083] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  244.001086] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  244.001088] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  244.001090] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  244.001092] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.001094] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  244.001097] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: n, active: n
>[32m[  244.001099] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253fc8
>[32m[  244.001128] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb -1
>[32m[  244.001151] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  244.001155] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  244.001207] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  244.021891] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  244.021919] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  244.022154] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  244.022176] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  244.022212] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  244.022233] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.022256] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.022279] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  244.022322] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  244.022331] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  244.022344] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  244.022383] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  244.022388] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2f098 state to ffff8801f1253fc8
>[32m[  244.022391] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f098 to [NOCRTC]
>[32m[  244.022393] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f098
>[32m[  244.022395] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  244.022399] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  244.022411] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  244.022425] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  244.022447] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  244.022452] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2e758 state to ffff8801f1253fc8
>[32m[  244.022454] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  244.022456] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  244.022458] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  244.022461] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  244.022470] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  244.022481] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  244.022495] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  244.022514] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  244.022520] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff880210694a88 state to ffff8801f1253fc8
>[32m[  244.022525] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2d288 state to ffff8801f1253fc8
>[32m[  244.022528] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880210694a88
>[32m[  244.022530] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d288 to [NOCRTC]
>[32m[  244.022532] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d288
>[32m[  244.022536] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253fc8
>[32m[  244.022539] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  244.022543] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  244.022564] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  244.022574] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  244.022603] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  244.022608] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2e2b8 state to ffff8801f1253fc8
>[32m[  244.022611] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [NOCRTC]
>[32m[  244.022613] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e2b8
>[32m[  244.022615] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  244.022617] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  244.022626] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  244.022636] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  244.022655] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253fc8
>[32m[  244.022660] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2de18 state to ffff8801f1253fc8
>[32m[  244.022662] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2de18 to [NOCRTC]
>[32m[  244.022664] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2de18
>[32m[  244.022666] [0m[drm:drm_atomic_check_only] checking ffff8801f1253fc8
>[32m[  244.022668] [0m[drm:drm_atomic_commit] committing ffff8801f1253fc8
>[32m[  244.022676] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253fc8
>[32m[  244.022686] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253fc8
>[32m[  244.051333] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  244.051475] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  244.056139] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  244.058147] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  244.058161] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  244.058171] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  244.058177] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126e678 state to ffff8801f1250aa8
>[32m[  244.058182] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2f538 state to ffff8801f1250aa8
>[32m[  244.058187] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126e678
>[32m[  244.058190] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [CRTC:36:pipe A]
>[32m[  244.058192] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff88020ec2f538
>[32m[  244.058195] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1250aa8
>[32m[  244.058202] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e908f38 state to ffff8801f1250aa8
>[32m[  244.058206] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e908f38 to [NOCRTC]
>[32m[  244.058208] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e908f38 to [CRTC:36:pipe A]
>[32m[  244.058212] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  244.058217] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  244.058220] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  244.058250] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 99
>[32m[  244.058273] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.058278] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  244.067518] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  244.067549] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  244.067591] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  244.067597] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cfc28 state to ffff8801f1250aa8
>[32m[  244.067602] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12692a8 state to ffff8801f1250aa8
>[32m[  244.067605] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [CRTC:36:pipe A]
>[32m[  244.067607] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff8801fb5cfc28
>[32m[  244.067609] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  244.067637] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 66
>[32m[  244.067659] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  244.067663] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  244.084144] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  244.084168] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  244.084204] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  244.084209] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cc258 state to ffff8801f1250aa8
>[32m[  244.084214] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126e678 state to ffff8801f1250aa8
>[32m[  244.084217] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc258 to [CRTC:36:pipe A]
>[32m[  244.084219] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801fb5cc258
>[32m[  244.084221] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  244.084247] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 100
>[32m[  244.084270] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  244.084274] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  244.100781] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  244.100793] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  244.100820] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801fb5cc6f8
>[32m[  244.100846] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 100
>[32m[  244.100869] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.117782] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  244.117790] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788748 state to ffff8801f1250aa8
>[32m[  244.117793] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  244.117796] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.117798] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  244.117801] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  244.117812] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  244.117825] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  244.117872] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  244.123717] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  244.123731] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.123740] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.123746] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1268008 state to ffff8801f1251fe8
>[32m[  244.123751] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5ce2b8 state to ffff8801f1251fe8
>[32m[  244.123756] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1268008
>[32m[  244.123758] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce2b8 to [CRTC:36:pipe A]
>[32m[  244.123761] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8801fb5ce2b8
>[32m[  244.123763] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.123771] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e908bd8 state to ffff8801f1251fe8
>[32m[  244.123774] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e908bd8 to [NOCRTC]
>[32m[  244.123779] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789058 state to ffff8801f1251fe8
>[32m[  244.123781] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9789058 to [CRTC:36:pipe A]
>[32m[  244.123785] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.123788] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  244.123791] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  244.123793] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  244.123796] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.123798] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:36:pipe A]
>[32m[  244.123801] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  244.123803] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.123809] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ce9a8 state to ffff8801f1251fe8
>[32m[  244.123813] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cf098 state to ffff8801f1251fe8
>[32m[  244.123816] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.123844] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  244.123867] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  244.123890] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  244.123910] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  244.123931] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  244.123951] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  244.123971] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  244.123991] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  244.124046] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  244.124069] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  244.124092] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  244.124097] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  244.124118] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  244.124122] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  244.124144] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  244.124165] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  244.124186] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  244.124207] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  244.124230] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  244.124251] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  244.124273] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  244.124294] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  244.124315] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:100, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  244.124341] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 102
>[32m[  244.124364] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.124386] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 66
>[32m[  244.124406] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.124429] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 100
>[32m[  244.124450] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.124490] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  244.124511] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  244.124517] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.126801] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  244.151527] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  244.151556] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  244.151788] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  244.151810] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  244.151829] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  244.151849] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  244.151870] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.151893] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  244.151924] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  244.152595] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  244.152776] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  244.152805] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  244.152824] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  244.152849] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  244.152869] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  244.152886] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  244.152909] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  244.152928] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  244.187764] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.187798] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  244.187838] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.187850] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.187869] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.187906] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.187911] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cd728 state to ffff8801f1251fe8
>[32m[  244.187916] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126e678 state to ffff8801f1251fe8
>[32m[  244.187918] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [NOCRTC]
>[32m[  244.187921] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd728
>[32m[  244.187923] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.187946] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  244.187966] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  244.187971] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.204405] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.204419] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.204448] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.204453] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5ce9a8 state to ffff8801f1251fe8
>[32m[  244.204458] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1268008 state to ffff8801f1251fe8
>[32m[  244.204461] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce9a8 to [NOCRTC]
>[32m[  244.204463] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce9a8
>[32m[  244.204465] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.204491] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  244.204513] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  244.204517] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.221069] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.221083] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.271260] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.271268] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f97893f8 state to ffff8801f1251fe8
>[32m[  244.271273] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126e678 state to ffff8801f1251fe8
>[32m[  244.271276] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.271280] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.271283] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  244.271288] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.287721] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.287735] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.288045] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  244.288204] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  244.292304] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  244.294130] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  244.294151] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.294160] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.294165] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126efc8 state to ffff8801f1251fe8
>[32m[  244.294170] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cc258 state to ffff8801f1251fe8
>[32m[  244.294176] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126efc8
>[32m[  244.294178] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc258 to [CRTC:36:pipe A]
>[32m[  244.294181] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801fb5cc258
>[32m[  244.294183] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.294191] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788748 state to ffff8801f1251fe8
>[32m[  244.294194] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788748 to [NOCRTC]
>[32m[  244.294197] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788748 to [CRTC:36:pipe A]
>[32m[  244.294201] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.294205] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.294208] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  244.294238] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 108
>[32m[  244.294261] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.294266] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.304396] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.304423] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.304469] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.304474] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ccb98 state to ffff8801f1251fe8
>[32m[  244.304479] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126e678 state to ffff8801f1251fe8
>[32m[  244.304481] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ccb98 to [CRTC:36:pipe A]
>[32m[  244.304483] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801fb5ccb98
>[32m[  244.304486] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.304514] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 100
>[32m[  244.304536] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  244.304541] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.321057] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.321070] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.321114] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.321119] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cfc28 state to ffff8801f1251fe8
>[32m[  244.321124] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126efc8 state to ffff8801f1251fe8
>[32m[  244.321126] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [CRTC:36:pipe A]
>[32m[  244.321128] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801fb5cfc28
>[32m[  244.321131] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.321158] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 109
>[32m[  244.321180] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  244.321185] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.337736] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.337749] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.337775] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802128eb098
>[32m[  244.337801] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 109
>[32m[  244.337823] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.354593] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.354601] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789968 state to ffff8801f1251fe8
>[32m[  244.354607] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1268008 state to ffff8801f1251fe8
>[32m[  244.354609] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.354614] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.354616] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  244.354621] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.371054] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.371075] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.371311] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  244.377694] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  244.377715] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  244.377724] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.377729] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126efc8 state to ffff8801f1251fe8
>[32m[  244.377734] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128eabf8 state to ffff8801f1251fe8
>[32m[  244.377739] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126efc8
>[32m[  244.377742] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [CRTC:36:pipe A]
>[32m[  244.377744] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8802128eabf8
>[32m[  244.377747] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.377755] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f97893f8 state to ffff8801f1251fe8
>[32m[  244.377758] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97893f8 to [NOCRTC]
>[32m[  244.377762] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e9090e8 state to ffff8801f1251fe8
>[32m[  244.377764] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e9090e8 to [CRTC:36:pipe A]
>[32m[  244.377768] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.377771] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  244.377774] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  244.377777] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  244.377779] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.377781] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  244.377783] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  244.377786] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.377792] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128eb538 state to ffff8801f1251fe8
>[32m[  244.377796] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128e9978 state to ffff8801f1251fe8
>[32m[  244.377799] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.377828] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  244.377850] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  244.377871] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  244.377892] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  244.377913] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  244.377933] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  244.377953] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  244.377973] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  244.377992] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  244.378028] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  244.378048] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  244.378055] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  244.378076] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  244.378098] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  244.378119] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  244.378140] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  244.378163] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  244.378185] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  244.378207] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  244.378228] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:100, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  244.378249] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:109, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  244.378276] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 110
>[32m[  244.378298] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.378321] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 100
>[32m[  244.378344] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.378366] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 109
>[32m[  244.378388] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.378430] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  244.378451] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  244.378458] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.381042] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  244.405759] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  244.405787] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  244.406056] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  244.406079] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  244.406104] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  244.406126] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.406149] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.406174] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  244.406207] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  244.406828] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  244.407029] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  244.407061] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  244.407082] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  244.407109] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  244.407129] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  244.407148] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  244.407172] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  244.407211] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  244.441946] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  244.441977] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  244.442059] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.442075] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.442095] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.442142] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.442148] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212c008 state to ffff8801f1251fe8
>[32m[  244.442154] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1219bf8 state to ffff8801f1251fe8
>[32m[  244.442156] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [NOCRTC]
>[32m[  244.442158] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c008
>[32m[  244.442161] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.442185] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  244.442207] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  244.442212] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.458550] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.458562] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.458590] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.458596] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212c258 state to ffff8801f1251fe8
>[32m[  244.458601] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121dd28 state to ffff8801f1251fe8
>[32m[  244.458603] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c258 to [NOCRTC]
>[32m[  244.458605] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c258
>[32m[  244.458607] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.458633] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  244.458655] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  244.458659] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.475170] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.475183] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.525438] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  244.525572] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  244.530088] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  244.532062] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  244.532085] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  244.532094] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.532100] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121a548 state to ffff8801f1251fe8
>[32m[  244.532104] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212e9a8 state to ffff8801f1251fe8
>[32m[  244.532110] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121a548
>[32m[  244.532112] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [CRTC:36:pipe A]
>[32m[  244.532115] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88021212e9a8
>[32m[  244.532117] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.532125] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e908878 state to ffff8801f1251fe8
>[32m[  244.532129] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e908878 to [NOCRTC]
>[32m[  244.532131] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e908878 to [CRTC:36:pipe A]
>[32m[  244.532135] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.532139] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  244.532142] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  244.532173] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 112
>[32m[  244.532196] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.532201] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.541681] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.541699] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.541744] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.541750] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802135a0de8 state to ffff8801f1251fe8
>[32m[  244.541755] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9696678 state to ffff8801f1251fe8
>[32m[  244.541758] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a0de8 to [CRTC:36:pipe A]
>[32m[  244.541760] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802135a0de8
>[32m[  244.541762] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.541790] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 109
>[32m[  244.541812] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  244.541817] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.558307] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.558318] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.558397] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.558402] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212945978 state to ffff8801f1251fe8
>[32m[  244.558407] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f9694a88 state to ffff8801f1251fe8
>[32m[  244.558410] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212945978 to [CRTC:36:pipe A]
>[32m[  244.558412] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff880212945978
>[32m[  244.558414] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.558441] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 113
>[32m[  244.558463] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  244.558468] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.574928] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.574940] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.574965] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802111ccde8
>[32m[  244.574991] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 113
>[32m[  244.575055] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.591906] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.591914] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789058 state to ffff8801f1251fe8
>[32m[  244.591917] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.591920] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.591922] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  244.591925] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.591936] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.591950] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.592047] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  244.597874] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  244.597894] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.597903] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.597909] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129b7e8 state to ffff8801f1251fe8
>[32m[  244.597914] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111cf098 state to ffff8801f1251fe8
>[32m[  244.597919] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129b7e8
>[32m[  244.597921] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [CRTC:36:pipe A]
>[32m[  244.597924] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8802111cf098
>[32m[  244.597926] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.597934] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e9090e8 state to ffff8801f1251fe8
>[32m[  244.597937] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e9090e8 to [NOCRTC]
>[32m[  244.597942] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789968 state to ffff8801f1251fe8
>[32m[  244.597944] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9789968 to [CRTC:36:pipe A]
>[32m[  244.597948] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.597951] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  244.597954] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  244.597956] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  244.597958] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.597961] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:36:pipe A]
>[32m[  244.597963] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  244.597966] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.597971] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cf9d8 state to ffff8801f1251fe8
>[32m[  244.597976] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cc4a8 state to ffff8801f1251fe8
>[32m[  244.597979] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.598006] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  244.598063] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  244.598089] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  244.598114] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  244.598137] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  244.598161] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  244.598184] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  244.598207] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  244.598230] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  244.598252] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  244.598273] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  244.598278] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  244.598298] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  244.598303] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  244.598324] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  244.598344] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  244.598363] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  244.598382] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  244.598406] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  244.598426] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  244.598446] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:112, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  244.598466] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:109, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  244.598485] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:113, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  244.598510] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 114
>[32m[  244.598531] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.598553] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 109
>[32m[  244.598573] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.598594] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 113
>[32m[  244.598623] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.598662] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  244.598682] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  244.598687] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.600944] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  244.626726] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  244.626754] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  244.626987] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  244.627053] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  244.627077] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  244.627100] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  244.627124] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.627149] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  244.627181] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  244.627846] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  244.628036] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  244.628070] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  244.628091] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  244.628118] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  244.628139] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  244.628157] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  244.628191] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  244.628211] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  244.663058] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.663090] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  244.663131] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.663143] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.663164] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.663207] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.663212] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cf2e8 state to ffff8801f1251fe8
>[32m[  244.663217] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129e678 state to ffff8801f1251fe8
>[32m[  244.663219] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [NOCRTC]
>[32m[  244.663221] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf2e8
>[32m[  244.663224] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.663247] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  244.663267] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  244.663271] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.679669] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.679680] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.679708] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.679713] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cf9d8 state to ffff8801f1251fe8
>[32m[  244.679718] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129b7e8 state to ffff8801f1251fe8
>[32m[  244.679720] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [NOCRTC]
>[32m[  244.679723] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf9d8
>[32m[  244.679725] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.679751] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  244.679773] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  244.679777] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.696330] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.696342] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.746525] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.746534] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788748 state to ffff8801f1251fe8
>[32m[  244.746539] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129e678 state to ffff8801f1251fe8
>[32m[  244.746541] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.746546] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.746549] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  244.746553] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.763007] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.763018] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.763267] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  244.763399] [0m[drm:drm_mode_addfb2] [FB:115]
>[32m[  244.767479] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  244.769255] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  244.769269] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.769279] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.769284] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1251fe8
>[32m[  244.769290] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9532508 state to ffff8801f1251fe8
>[32m[  244.769296] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f12992a8
>[32m[  244.769299] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532508 to [CRTC:36:pipe A]
>[32m[  244.769301] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8801f9532508
>[32m[  244.769303] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1251fe8
>[32m[  244.769311] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789058 state to ffff8801f1251fe8
>[32m[  244.769315] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9789058 to [NOCRTC]
>[32m[  244.769317] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9789058 to [CRTC:36:pipe A]
>[32m[  244.769321] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.769325] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.769328] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  244.769358] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 116
>[32m[  244.769381] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.769385] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.779677] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.779693] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.779730] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.779736] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9532758 state to ffff8801f1251fe8
>[32m[  244.779741] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129e678 state to ffff8801f1251fe8
>[32m[  244.779743] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [CRTC:36:pipe A]
>[32m[  244.779745] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8801f9532758
>[32m[  244.779747] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.779775] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb 113
>[32m[  244.779798] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  244.779802] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.796343] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.796353] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.796387] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.796393] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9532e48 state to ffff8801f1251fe8
>[32m[  244.796398] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1251fe8
>[32m[  244.796400] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532e48 to [CRTC:36:pipe A]
>[32m[  244.796402] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801f9532e48
>[32m[  244.796404] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.796431] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 117
>[32m[  244.796453] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  244.796458] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.813005] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.813017] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.813042] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801f9530948
>[32m[  244.813068] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb 117
>[32m[  244.813090] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.829861] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1251fe8
>[32m[  244.829868] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f97893f8 state to ffff8801f1251fe8
>[32m[  244.829874] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129e678 state to ffff8801f1251fe8
>[32m[  244.829876] [0m[drm:drm_atomic_check_only] checking ffff8801f1251fe8
>[32m[  244.829881] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.829884] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:36:pipe A]
>[32m[  244.829888] [0m[drm:drm_atomic_commit] committing ffff8801f1251fe8
>[32m[  244.846325] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1251fe8
>[32m[  244.846336] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1251fe8
>[32m[  244.846510] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  244.856371] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252fd8
>[32m[  244.856377] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9532bf8 state to ffff8801f1252fd8
>[32m[  244.856383] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1252fd8
>[32m[  244.856387] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95306f8 state to ffff8801f1252fd8
>[32m[  244.856389] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [NOCRTC]
>[32m[  244.856390] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95306f8
>[32m[  244.856394] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9533788 state to ffff8801f1252fd8
>[32m[  244.856396] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [NOCRTC]
>[32m[  244.856397] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533788
>[32m[  244.856401] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f95304a8 state to ffff8801f1252fd8
>[32m[  244.856405] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9530258 state to ffff8801f1252fd8
>[32m[  244.856407] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [NOCRTC]
>[32m[  244.856408] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530258
>[32m[  244.856412] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9531288 state to ffff8801f1252fd8
>[32m[  244.856414] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [NOCRTC]
>[32m[  244.856415] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531288
>[32m[  244.856417] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  244.856438] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec51728 state to ffff8801f1252fd8
>[32m[  244.856442] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1252fd8
>[32m[  244.856446] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ee52e48 state to ffff8801f1252fd8
>[32m[  244.856448] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [NOCRTC]
>[32m[  244.856449] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee52e48
>[32m[  244.856451] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  244.856462] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ee52e48 state to ffff8801f1252fd8
>[32m[  244.856466] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1252fd8
>[32m[  244.856470] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ee51978 state to ffff8801f1252fd8
>[32m[  244.856471] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee51978 to [NOCRTC]
>[32m[  244.856473] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee51978
>[32m[  244.856477] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ee529a8 state to ffff8801f1252fd8
>[32m[  244.856478] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee529a8 to [NOCRTC]
>[32m[  244.856480] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee529a8
>[32m[  244.856484] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020e078de8 state to ffff8801f1252fd8
>[32m[  244.856488] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e0794d8 state to ffff8801f1252fd8
>[32m[  244.856489] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e0794d8 to [NOCRTC]
>[32m[  244.856491] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e0794d8
>[32m[  244.856495] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020e078258 state to ffff8801f1252fd8
>[32m[  244.856496] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [NOCRTC]
>[32m[  244.856498] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078258
>[32m[  244.856502] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020e07b2e8 state to ffff8801f1252fd8
>[32m[  244.856505] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020e07a9a8 state to ffff8801f1252fd8
>[32m[  244.856507] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [NOCRTC]
>[32m[  244.856508] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a9a8
>[32m[  244.856512] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020e07a508 state to ffff8801f1252fd8
>[32m[  244.856514] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [NOCRTC]
>[32m[  244.856515] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a508
>[32m[  244.856521] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12992a8
>[32m[  244.856523] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [CRTC:36:pipe A]
>[32m[  244.856525] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ee52e48
>[32m[  244.856528] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  244.856535] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135becb8 state to ffff8801f1252fd8
>[32m[  244.856538] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135becb8 to [NOCRTC]
>[32m[  244.856542] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e909298 state to ffff8801f1252fd8
>[32m[  244.856544] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e909298 to [CRTC:36:pipe A]
>[32m[  244.856546] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  244.856577] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020e07a508 state to ffff8801f1252fd8
>[32m[  244.856581] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1252fd8
>[32m[  244.856585] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e07b788 state to ffff8801f1252fd8
>[32m[  244.856587] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b788 to [NOCRTC]
>[32m[  244.856588] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b788
>[32m[  244.856592] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e07a9a8 state to ffff8801f1252fd8
>[32m[  244.856593] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [NOCRTC]
>[32m[  244.856595] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a9a8
>[32m[  244.856599] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020e078de8 state to ffff8801f1252fd8
>[32m[  244.856602] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e07b2e8 state to ffff8801f1252fd8
>[32m[  244.856604] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b2e8 to [NOCRTC]
>[32m[  244.856605] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b2e8
>[32m[  244.856609] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020e0794d8 state to ffff8801f1252fd8
>[32m[  244.856610] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e0794d8 to [NOCRTC]
>[32m[  244.856612] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e0794d8
>[32m[  244.856616] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020e078258 state to ffff8801f1252fd8
>[32m[  244.856620] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802121314d8 state to ffff8801f1252fd8
>[32m[  244.856621] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [NOCRTC]
>[32m[  244.856623] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121314d8
>[32m[  244.856626] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff880212131288 state to ffff8801f1252fd8
>[32m[  244.856628] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [NOCRTC]
>[32m[  244.856629] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131288
>[32m[  244.856634] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12992a8
>[32m[  244.856636] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [CRTC:36:pipe A]
>[32m[  244.856637] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020e07a508
>[32m[  244.856639] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  244.856644] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801fb7f5058 state to ffff8801f1252fd8
>[32m[  244.856646] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fb7f5058 to [NOCRTC]
>[32m[  244.856650] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e909298 state to ffff8801f1252fd8
>[32m[  244.856652] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e909298 to [CRTC:36:pipe A]
>[32m[  244.856656] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff8801f1252fd8
>[32m[  244.856661] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1299bf8
>[32m[  244.856663] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078de8 to [CRTC:46:pipe B]
>[32m[  244.856665] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020e078de8
>[32m[  244.856667] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252fd8
>[32m[  244.856670] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fb7f5058 to [CRTC:46:pipe B]
>[32m[  244.856674] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129c138 state to ffff8801f1252fd8
>[32m[  244.856676] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f129c138
>[32m[  244.856678] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [NOCRTC]
>[32m[  244.856679] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078258
>[32m[  244.856681] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252fd8
>[32m[  244.856684] [0m[drm:drm_atomic_check_only] checking ffff8801f1252fd8
>[32m[  244.856687] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  244.856689] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  244.856690] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  244.856692] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  244.856695] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  244.856698] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  244.856699] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.856701] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  244.856703] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  244.856705] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  244.856708] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  244.856710] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252fd8
>[32m[  244.856714] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  244.856742] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  244.856764] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  244.856785] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  244.856805] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  244.856826] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  244.856846] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  244.856865] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  244.856884] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  244.856902] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  244.856904] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  244.856922] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  244.856924] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  244.856942] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  244.856960] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  244.856978] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  244.856995] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  244.857040] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  244.857067] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  244.857086] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:116, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  244.857103] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] FB:113, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  244.857121] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] FB:117, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  244.857124] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252fd8
>[32m[  244.857144] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  244.857163] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  244.857185] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  244.857204] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  244.857223] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  244.857241] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  244.857259] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  244.857277] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  244.857294] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  244.857312] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  244.857329] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  244.857331] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  244.857347] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  244.857349] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  244.857367] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  244.857384] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  244.857401] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  244.857418] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  244.857437] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  244.857454] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  244.857471] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0
>[32m[  244.857488] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  244.857505] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  244.857528] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  244.857547] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  244.857566] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:30:sprite A] with fb -1
>[32m[  244.857584] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:30:sprite A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  244.857603] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:33:cursor A] with fb -1
>[32m[  244.857621] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:33:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  244.857639] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  244.857657] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  244.857694] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  244.857713] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  244.857749] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  244.857768] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  244.857772] [0m[drm:drm_atomic_commit] committing ffff8801f1252fd8
>[32m[  244.857851] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  244.881395] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  244.881422] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  244.881657] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  244.881676] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  244.881695] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  244.881714] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.881737] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  244.881768] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  244.882423] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  244.882605] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  244.882634] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  244.882653] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  244.882678] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  244.882697] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  244.882714] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  244.882736] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  244.882755] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  244.900870] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  244.901536] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  244.901721] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  244.901751] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  244.901771] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  244.901797] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  244.901817] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  244.901834] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  244.901857] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  244.901876] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  244.936694] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  244.936725] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  244.936765] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  244.936795] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  244.936817] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  244.936855] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  244.936871] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  244.936920] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252fd8
>[32m[  244.940933] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  244.946780] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  244.946787] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802121329a8 state to ffff8801f12574e8
>[32m[  244.946794] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8802144bc138 state to ffff8801f12574e8
>[32m[  244.946799] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff880212131978 state to ffff8801f12574e8
>[32m[  244.946803] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [NOCRTC]
>[32m[  244.946805] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131978
>[32m[  244.946810] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212131038 state to ffff8801f12574e8
>[32m[  244.946812] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [NOCRTC]
>[32m[  244.946814] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131038
>[32m[  244.946820] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2cb98 state to ffff8801f12574e8
>[32m[  244.946825] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f95e12a8 state to ffff8801f12574e8
>[32m[  244.946831] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2d038 state to ffff8801f12574e8
>[32m[  244.946833] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  244.946835] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  244.946840] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2cde8 state to ffff8801f12574e8
>[32m[  244.946842] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  244.946845] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  244.946848] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  244.946873] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2cde8 state to ffff8801f12574e8
>[32m[  244.946878] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff8801f12574e8
>[32m[  244.946892] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2e9a8 state to ffff8801f12574e8
>[32m[  244.946894] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [NOCRTC]
>[32m[  244.946897] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e9a8
>[32m[  244.946900] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  244.946912] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2e9a8 state to ffff8801f12574e8
>[32m[  244.946917] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e12a8 state to ffff8801f12574e8
>[32m[  244.946922] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2de18 state to ffff8801f12574e8
>[32m[  244.946924] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2de18 to [NOCRTC]
>[32m[  244.946927] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2de18
>[32m[  244.946932] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2cde8 state to ffff8801f12574e8
>[32m[  244.946935] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  244.946937] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  244.946942] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2e2b8 state to ffff8801f12574e8
>[32m[  244.946947] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f95e2548 state to ffff8801f12574e8
>[32m[  244.946952] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2d038 state to ffff8801f12574e8
>[32m[  244.946954] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  244.946956] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  244.946961] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2d288 state to ffff8801f12574e8
>[32m[  244.946963] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d288 to [NOCRTC]
>[32m[  244.946966] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d288
>[32m[  244.946971] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2cb98 state to ffff8801f12574e8
>[32m[  244.946975] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2e758 state to ffff8801f12574e8
>[32m[  244.946978] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  244.946980] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  244.946985] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2c008 state to ffff8801f12574e8
>[32m[  244.947253] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  244.947255] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  244.947265] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f95e12a8
>[32m[  244.947267] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [CRTC:36:pipe A]
>[32m[  244.947270] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ec2e9a8
>[32m[  244.947273] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  244.947305] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2c008 state to ffff8801f12574e8
>[32m[  244.947311] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f95e2548 state to ffff8801f12574e8
>[32m[  244.947316] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2dbc8 state to ffff8801f12574e8
>[32m[  244.947318] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  244.947320] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  244.947325] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2e758 state to ffff8801f12574e8
>[32m[  244.947328] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  244.947330] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  244.947335] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2ee48 state to ffff8801f12574e8
>[32m[  244.947340] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f95e5d28 state to ffff8801f12574e8
>[32m[  244.947346] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2cb98 state to ffff8801f12574e8
>[32m[  244.947348] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [NOCRTC]
>[32m[  244.947350] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cb98
>[32m[  244.947354] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2f538 state to ffff8801f12574e8
>[32m[  244.947357] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [NOCRTC]
>[32m[  244.947359] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f538
>[32m[  244.947364] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2d288 state to ffff8801f12574e8
>[32m[  244.947368] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2c4a8 state to ffff8801f12574e8
>[32m[  244.947371] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [NOCRTC]
>[32m[  244.947374] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c4a8
>[32m[  244.947378] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2d038 state to ffff8801f12574e8
>[32m[  244.947380] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  244.947382] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  244.947388] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f95e2548
>[32m[  244.947390] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [CRTC:36:pipe A]
>[32m[  244.947393] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ec2c008
>[32m[  244.947395] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  244.947405] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff88020e909448 state to ffff8801f12574e8
>[32m[  244.947409] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e909448 to [NOCRTC]
>[32m[  244.947412] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e909448 to [CRTC:36:pipe A]
>[32m[  244.947418] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f95e5d28
>[32m[  244.947420] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2ee48 to [CRTC:46:pipe B]
>[32m[  244.947422] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88020ec2ee48
>[32m[  244.947426] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  244.947432] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801fb579b38 state to ffff8801f12574e8
>[32m[  244.947435] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fb579b38 to [NOCRTC]
>[32m[  244.947438] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fb579b38 to [CRTC:46:pipe B]
>[32m[  244.947444] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f95e12a8 state to ffff8801f12574e8
>[32m[  244.947446] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f95e12a8
>[32m[  244.947448] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d288 to [NOCRTC]
>[32m[  244.947451] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d288
>[32m[  244.947454] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f12574e8
>[32m[  244.947457] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  244.947464] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  244.947467] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  244.947470] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  244.947472] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  244.947504] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  244.947529] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.947554] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  244.947577] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  244.947584] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  244.953326] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  244.953373] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  244.989232] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  244.989339] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  245.010123] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  245.010159] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  245.010186] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  245.010207] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  245.048430] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  245.048503] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  245.048507] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  245.048509] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  245.048511] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  245.048513] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  245.048516] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  245.048518] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  245.048520] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  245.048522] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  245.048524] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  245.048526] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  245.048528] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  245.048530] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  245.048621] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.048652] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.123768] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  245.123791] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  245.125849] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  245.125855] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  245.125859] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  245.125875] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  245.126032] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  245.126034] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  245.126036] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  245.126176] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  245.126180] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  245.126183] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  245.126185] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  245.126188] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  245.126190] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  245.126192] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  245.126195] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  245.126197] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  245.126199] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  245.126202] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  245.126205] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  245.126207] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  245.126209] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  245.126212] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  245.126214] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  245.126216] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  245.126231] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  245.126233] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  245.126405] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.126413] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880212b24918 state to ffff8801f12574e8
>[32m[  245.126419] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121a548 state to ffff8801f12574e8
>[32m[  245.126422] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.126428] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.126431] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  245.126438] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.136660] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.136675] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.136702] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  245.136728] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  245.139313] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.141865] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.144418] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.146970] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.149537] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.152072] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.154610] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.157142] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.159669] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.162197] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.164721] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.167251] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.169776] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.172301] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.174826] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.177351] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.179876] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.182402] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.184926] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.187452] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.189980] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.192529] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.195061] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.197590] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.200117] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.202641] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.205164] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.207690] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.210215] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.212743] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.215269] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.217798] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  245.217806] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  245.217809] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  245.217960] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.217968] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff88020e0b9058 state to ffff8801f12574e8
>[32m[  245.217970] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.217974] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  245.217976] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  245.217979] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.218036] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.218051] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.218133] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest legacy-pipe-B-tiling-none
>[32m[  245.218401] [0m[drm:drm_mode_addfb2] [FB:95]
>[32m[  245.225106] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  245.225128] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.225134] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1219bf8 state to ffff8801f12574e8
>[32m[  245.225139] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212e9a8 state to ffff8801f12574e8
>[32m[  245.225142] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f1219bf8
>[32m[  245.225144] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [NOCRTC]
>[32m[  245.225146] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212e9a8
>[32m[  245.225149] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  245.225157] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508dcb8 state to ffff8801f12574e8
>[32m[  245.225161] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508dcb8 to [NOCRTC]
>[32m[  245.225163] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.225166] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  245.225168] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  245.225170] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  245.225172] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  245.225174] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  245.225176] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: n, active: n
>[32m[  245.225179] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f12574e8
>[32m[  245.225210] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb -1
>[32m[  245.225232] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  245.225237] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.225303] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  245.251695] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  245.251723] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  245.251956] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  245.251991] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  245.252050] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  245.252073] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  245.252097] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.252122] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  245.252166] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  245.252176] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.252191] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.252233] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.252239] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212ebf8 state to ffff8801f12574e8
>[32m[  245.252242] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [NOCRTC]
>[32m[  245.252244] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212ebf8
>[32m[  245.252246] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.252250] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.252262] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.252278] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.252313] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.252318] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212c6f8 state to ffff8801f12574e8
>[32m[  245.252321] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  245.252323] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  245.252325] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.252328] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.252337] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.252347] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.252362] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  245.252382] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  245.252390] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.252395] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121c138 state to ffff8801f12574e8
>[32m[  245.252400] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212fc28 state to ffff8801f12574e8
>[32m[  245.252406] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121c138
>[32m[  245.252409] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [CRTC:46:pipe B]
>[32m[  245.252411] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:95] for plane state ffff88021212fc28
>[32m[  245.252414] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  245.252422] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801fd72f968 state to ffff8801f12574e8
>[32m[  245.252425] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd72f968 to [NOCRTC]
>[32m[  245.252430] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508c6c8 state to ffff8801f12574e8
>[32m[  245.252433] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508c6c8 to [CRTC:46:pipe B]
>[32m[  245.252437] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.252440] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  245.252444] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  245.252447] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:46:pipe B]
>[32m[  245.252449] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.252451] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  245.252454] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  245.252456] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  245.252461] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  245.252484] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  245.252504] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  245.252525] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  245.252545] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  245.252565] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  245.252586] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  245.252606] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  245.252625] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  245.252644] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  245.252647] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  245.252666] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  245.252669] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  245.252689] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  245.252708] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  245.252727] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  245.252745] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  245.252766] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  245.252785] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  245.252804] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:96, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  245.252823] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  245.252841] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  245.252865] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 95
>[32m[  245.252886] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.252925] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  245.252945] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  245.252950] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.255519] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  245.288309] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  245.288337] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  245.288569] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  245.288589] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  245.288611] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  245.288631] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.288653] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.288676] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  245.288707] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  245.289339] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  245.289526] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  245.289555] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  245.289575] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  245.289600] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  245.289620] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  245.289637] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  245.289660] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  245.289680] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  245.324454] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  245.324489] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  245.324529] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.324543] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.324561] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.324617] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.324623] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802135a3098 state to ffff8801f12574e8
>[32m[  245.324625] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [NOCRTC]
>[32m[  245.324628] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a3098
>[32m[  245.324630] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.324634] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.324648] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.324663] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.324684] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.324689] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802135a0de8 state to ffff8801f12574e8
>[32m[  245.324691] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a0de8 to [NOCRTC]
>[32m[  245.324693] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a0de8
>[32m[  245.324695] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.324698] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.324706] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.324716] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.341043] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  245.341068] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.341075] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129c138 state to ffff8801f12574e8
>[32m[  245.341080] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802129462b8 state to ffff8801f12574e8
>[32m[  245.341083] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f129c138
>[32m[  245.341085] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802129462b8 to [NOCRTC]
>[32m[  245.341087] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802129462b8
>[32m[  245.341090] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f12574e8
>[32m[  245.341094] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.341100] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.341126] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.341137] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.341167] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.341172] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff880212945978 state to ffff8801f12574e8
>[32m[  245.341174] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212945978 to [NOCRTC]
>[32m[  245.341176] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212945978
>[32m[  245.341178] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.341181] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.341190] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.341201] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.341220] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.341226] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cdbc8 state to ffff8801f12574e8
>[32m[  245.341228] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cdbc8 to [NOCRTC]
>[32m[  245.341230] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cdbc8
>[32m[  245.341232] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.341234] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.341242] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.341252] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.374500] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  245.374874] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  245.375066] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  245.381680] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  245.381699] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  245.381710] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.381716] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f12574e8
>[32m[  245.381721] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cc948 state to ffff8801f12574e8
>[32m[  245.381727] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12992a8
>[32m[  245.381730] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [CRTC:46:pipe B]
>[32m[  245.381732] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8802111cc948
>[32m[  245.381735] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f12574e8
>[32m[  245.381744] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508dcb8 state to ffff8801f12574e8
>[32m[  245.381747] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508dcb8 to [NOCRTC]
>[32m[  245.381750] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508dcb8 to [CRTC:46:pipe B]
>[32m[  245.381754] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.381759] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  245.381762] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  245.381796] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 100
>[32m[  245.381819] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  245.381825] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.390907] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.390935] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.390972] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.390978] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cf2e8 state to ffff8801f12574e8
>[32m[  245.390983] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129e678 state to ffff8801f12574e8
>[32m[  245.390985] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [CRTC:46:pipe B]
>[32m[  245.391135] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff8802111cf2e8
>[32m[  245.391137] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.391167] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 66
>[32m[  245.391199] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  245.391204] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.407529] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.407551] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.407587] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.407592] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cd4d8 state to ffff8801f12574e8
>[32m[  245.407597] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f12574e8
>[32m[  245.407600] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd4d8 to [CRTC:46:pipe B]
>[32m[  245.407602] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8802111cd4d8
>[32m[  245.407604] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.407631] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 99
>[32m[  245.407654] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  245.407658] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.424163] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.424176] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.424204] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8802111ccde8
>[32m[  245.424231] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 99
>[32m[  245.424253] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  245.441220] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f12574e8
>[32m[  245.441229] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801fd72e3a8 state to ffff8801f12574e8
>[32m[  245.441231] [0m[drm:drm_atomic_check_only] checking ffff8801f12574e8
>[32m[  245.441234] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.441236] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  245.441240] [0m[drm:drm_atomic_commit] committing ffff8801f12574e8
>[32m[  245.441252] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f12574e8
>[32m[  245.441266] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f12574e8
>[32m[  245.441316] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  245.447085] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  245.447108] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.447117] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  245.447123] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff8801f1256f98
>[32m[  245.447127] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ffdee48 state to ffff8801f1256f98
>[32m[  245.447133] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1299bf8
>[32m[  245.447135] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdee48 to [CRTC:46:pipe B]
>[32m[  245.447138] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff88020ffdee48
>[32m[  245.447141] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  245.447148] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508c6c8 state to ffff8801f1256f98
>[32m[  245.447151] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508c6c8 to [NOCRTC]
>[32m[  245.447156] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135becb8 state to ffff8801f1256f98
>[32m[  245.447159] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135becb8 to [CRTC:46:pipe B]
>[32m[  245.447162] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  245.447166] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  245.447169] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  245.447171] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  245.447173] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.447176] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:46:pipe B]
>[32m[  245.447178] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  245.447181] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  245.447186] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ffdf2e8 state to ffff8801f1256f98
>[32m[  245.447192] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9531728 state to ffff8801f1256f98
>[32m[  245.447195] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  245.447224] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  245.447246] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  245.447269] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  245.447290] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  245.447311] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  245.447331] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  245.447352] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  245.447372] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  245.447392] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  245.447412] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  245.447431] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  245.447433] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  245.447452] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  245.447454] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  245.447474] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  245.447492] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  245.447511] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  245.447529] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  245.447550] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  245.447568] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  245.447587] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  245.447605] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  245.447623] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:99, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  245.447647] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 102
>[32m[  245.447667] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.447687] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 66
>[32m[  245.447706] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.447725] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 99
>[32m[  245.447744] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.447782] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  245.447801] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  245.447806] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  245.450858] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  245.475574] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  245.475602] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  245.475835] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  245.475858] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  245.475877] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  245.475897] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  245.475919] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.475942] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  245.475972] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  245.476656] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  245.476839] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  245.476868] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  245.476888] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  245.476913] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  245.476932] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  245.476949] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  245.476972] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  245.476991] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  245.511834] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.511866] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  245.511906] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.511918] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  245.511936] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  245.511973] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  245.511979] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9533538 state to ffff8801f1256f98
>[32m[  245.511984] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f1256f98
>[32m[  245.512026] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533538 to [NOCRTC]
>[32m[  245.512028] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533538
>[32m[  245.512031] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  245.512056] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  245.512080] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  245.512086] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  245.528474] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  245.528485] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  245.528513] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  245.528519] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f95306f8 state to ffff8801f1256f98
>[32m[  245.528524] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff8801f1256f98
>[32m[  245.528526] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [NOCRTC]
>[32m[  245.528529] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95306f8
>[32m[  245.528531] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  245.528557] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  245.528579] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  245.528583] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  245.545135] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  245.545147] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  245.595319] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  245.595328] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f978ccb8 state to ffff8801f1256f98
>[32m[  245.595333] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f1256f98
>[32m[  245.595336] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  245.595341] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.595344] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  245.595348] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  245.611812] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  245.611824] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  245.611885] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  245.612260] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  245.612404] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  245.618178] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  245.618199] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.618209] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253a78
>[32m[  245.618215] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff8801f1253a78
>[32m[  245.618219] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9531038 state to ffff8801f1253a78
>[32m[  245.618225] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1299bf8
>[32m[  245.618228] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [CRTC:46:pipe B]
>[32m[  245.618230] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801f9531038
>[32m[  245.618233] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  245.618241] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788578 state to ffff8801f1253a78
>[32m[  245.618244] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788578 to [NOCRTC]
>[32m[  245.618247] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788578 to [CRTC:46:pipe B]
>[32m[  245.618251] [0m[drm:drm_atomic_check_only] checking ffff8801f1253a78
>[32m[  245.618255] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.618258] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  245.618290] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 108
>[32m[  245.618313] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  245.618318] [0m[drm:drm_atomic_commit] committing ffff8801f1253a78
>[32m[  245.628484] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  245.628501] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253a78
>[32m[  245.628587] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  245.628593] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f95339d8 state to ffff880212118008
>[32m[  245.628598] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff880212118008
>[32m[  245.628601] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [CRTC:46:pipe B]
>[32m[  245.628603] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8801f95339d8
>[32m[  245.628605] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  245.628634] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 99
>[32m[  245.628656] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  245.628661] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  245.645149] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  245.645160] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  245.645195] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  245.645200] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9532508 state to ffff8801f5241548
>[32m[  245.645205] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff8801f5241548
>[32m[  245.645207] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532508 to [CRTC:46:pipe B]
>[32m[  245.645209] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801f9532508
>[32m[  245.645211] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  245.645239] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 109
>[32m[  245.645261] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  245.645266] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  245.661810] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  245.661823] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  245.661848] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801f95306f8
>[32m[  245.661874] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 109
>[32m[  245.661896] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  245.678669] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  245.678677] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788748 state to ffff880211b85fa8
>[32m[  245.678683] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff880211b85fa8
>[32m[  245.678685] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  245.678690] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.678693] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  245.678697] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  245.695132] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  245.695143] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  245.695385] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  245.701714] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  245.701735] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  245.701744] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253a78
>[32m[  245.701750] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff8801f1253a78
>[32m[  245.701755] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9530008 state to ffff8801f1253a78
>[32m[  245.701760] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1299bf8
>[32m[  245.701763] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [CRTC:46:pipe B]
>[32m[  245.701765] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801f9530008
>[32m[  245.701768] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  245.701776] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789968 state to ffff8801f1253a78
>[32m[  245.701779] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9789968 to [NOCRTC]
>[32m[  245.701783] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508d298 state to ffff8801f1253a78
>[32m[  245.701785] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508d298 to [CRTC:46:pipe B]
>[32m[  245.701789] [0m[drm:drm_atomic_check_only] checking ffff8801f1253a78
>[32m[  245.701792] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  245.701796] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  245.701799] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:46:pipe B]
>[32m[  245.701801] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.701803] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  245.701805] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  245.701808] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  245.701813] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9532e48 state to ffff8801f1253a78
>[32m[  245.701818] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9530948 state to ffff8801f1253a78
>[32m[  245.701821] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  245.701850] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  245.701872] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  245.701894] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  245.701914] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  245.701935] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  245.701955] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  245.701975] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  245.701994] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  245.702047] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  245.702054] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  245.702075] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  245.702079] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  245.702100] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  245.702121] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  245.702143] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  245.702163] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  245.702187] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  245.702208] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  245.702229] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  245.702250] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:99, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  245.702271] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:109, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  245.702298] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 110
>[32m[  245.702320] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.702343] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 99
>[32m[  245.702364] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.702386] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 109
>[32m[  245.702407] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.702448] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  245.702469] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  245.702475] [0m[drm:drm_atomic_commit] committing ffff8801f1253a78
>[32m[  245.704959] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  245.729293] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  245.729321] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  245.729554] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  245.729574] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  245.729596] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  245.729616] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.729637] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.729660] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  245.729691] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  245.730312] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  245.730495] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  245.730525] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  245.730544] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  245.730570] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  245.730589] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  245.730606] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  245.730629] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  245.730649] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  245.765394] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  245.765425] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  245.765464] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.765476] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  245.765495] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253a78
>[32m[  245.765536] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  245.765542] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ee529a8 state to ffff8801f5241548
>[32m[  245.765547] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f5241548
>[32m[  245.765549] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee529a8 to [NOCRTC]
>[32m[  245.765551] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee529a8
>[32m[  245.765553] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  245.765577] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  245.765597] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  245.765601] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  245.782020] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  245.782032] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  245.782068] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  245.782074] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ee52e48 state to ffff880212a68008
>[32m[  245.782079] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff880212a68008
>[32m[  245.782081] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [NOCRTC]
>[32m[  245.782083] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee52e48
>[32m[  245.782085] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  245.782112] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  245.782134] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  245.782138] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  245.798618] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  245.798630] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  245.848691] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  245.849126] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  245.849281] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  245.855795] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  245.855817] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  245.855827] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253a78
>[32m[  245.855832] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1298958 state to ffff8801f1253a78
>[32m[  245.855837] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff880212131038 state to ffff8801f1253a78
>[32m[  245.855843] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1298958
>[32m[  245.855846] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [CRTC:46:pipe B]
>[32m[  245.855848] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff880212131038
>[32m[  245.855851] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  245.855859] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508c6c8 state to ffff8801f1253a78
>[32m[  245.855862] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508c6c8 to [NOCRTC]
>[32m[  245.855865] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508c6c8 to [CRTC:46:pipe B]
>[32m[  245.855869] [0m[drm:drm_atomic_check_only] checking ffff8801f1253a78
>[32m[  245.855873] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  245.855876] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  245.855907] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 112
>[32m[  245.855930] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  245.855935] [0m[drm:drm_atomic_commit] committing ffff8801f1253a78
>[32m[  245.865130] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  245.865148] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253a78
>[32m[  245.865191] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  245.865197] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e07a508 state to ffff880212118008
>[32m[  245.865202] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff880212118008
>[32m[  245.865204] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [CRTC:46:pipe B]
>[32m[  245.865206] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff88020e07a508
>[32m[  245.865208] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  245.865237] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 109
>[32m[  245.865259] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  245.865263] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  245.881755] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  245.881766] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  245.881800] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  245.881805] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020e07b2e8 state to ffff8801f5241548
>[32m[  245.881810] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1298958 state to ffff8801f5241548
>[32m[  245.881812] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b2e8 to [CRTC:46:pipe B]
>[32m[  245.881815] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff88020e07b2e8
>[32m[  245.881817] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  245.881844] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 113
>[32m[  245.881866] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  245.881870] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  245.898378] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  245.898390] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  245.898414] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff88020e078de8
>[32m[  245.898440] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 113
>[32m[  245.898462] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  245.915412] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  245.915420] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789058 state to ffff880212a68008
>[32m[  245.915423] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  245.915426] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.915428] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  245.915431] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  245.915443] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  245.915457] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  245.915503] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  245.921261] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  245.921282] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.921291] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253a78
>[32m[  245.921296] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f1253a78
>[32m[  245.921301] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2de18 state to ffff8801f1253a78
>[32m[  245.921307] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f12992a8
>[32m[  245.921309] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2de18 to [CRTC:46:pipe B]
>[32m[  245.921311] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88020ec2de18
>[32m[  245.921314] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  245.921322] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508d298 state to ffff8801f1253a78
>[32m[  245.921325] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508d298 to [NOCRTC]
>[32m[  245.921330] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788748 state to ffff8801f1253a78
>[32m[  245.921332] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788748 to [CRTC:46:pipe B]
>[32m[  245.921336] [0m[drm:drm_atomic_check_only] checking ffff8801f1253a78
>[32m[  245.921339] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  245.921343] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  245.921345] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  245.921347] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  245.921350] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:46:pipe B]
>[32m[  245.921352] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  245.921355] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  245.921361] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2d288 state to ffff8801f1253a78
>[32m[  245.921365] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2e508 state to ffff8801f1253a78
>[32m[  245.921368] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  245.921396] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  245.921418] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  245.921442] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  245.921462] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  245.921483] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  245.921503] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  245.921523] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  245.921543] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  245.921563] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  245.921582] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  245.921600] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  245.921603] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  245.921621] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  245.921624] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  245.921643] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  245.921661] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  245.921679] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  245.921697] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  245.921718] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  245.921736] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  245.921754] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:112, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  245.921773] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:109, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  245.921791] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:113, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  245.921815] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 114
>[32m[  245.921834] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.921855] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 109
>[32m[  245.921874] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.921893] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 113
>[32m[  245.921912] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  245.921949] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  245.921969] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  245.921973] [0m[drm:drm_atomic_commit] committing ffff8801f1253a78
>[32m[  245.924232] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  245.948943] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  245.948970] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  245.949204] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  245.949229] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  245.949249] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  245.949270] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  245.949303] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.949327] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  245.949359] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  245.950036] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  245.950224] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  245.950254] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  245.950275] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  245.950301] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  245.950321] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  245.950347] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  245.950371] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  245.950392] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  245.985209] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  245.985240] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  245.985279] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  245.985291] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  245.985309] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253a78
>[32m[  245.985350] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  245.985355] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2f098 state to ffff8801f5241548
>[32m[  245.985361] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1298958 state to ffff8801f5241548
>[32m[  245.985363] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f098 to [NOCRTC]
>[32m[  245.985365] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f098
>[32m[  245.985367] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  245.985390] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  245.985411] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  245.985415] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  246.001851] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  246.001862] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  246.001890] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  246.001895] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2d288 state to ffff880211b85fa8
>[32m[  246.001900] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff880211b85fa8
>[32m[  246.001902] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d288 to [NOCRTC]
>[32m[  246.001904] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d288
>[32m[  246.001907] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  246.001933] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  246.001955] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  246.001959] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  246.018510] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  246.018523] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  246.068719] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253a78
>[32m[  246.068727] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788578 state to ffff8801f1253a78
>[32m[  246.068732] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1298958 state to ffff8801f1253a78
>[32m[  246.068735] [0m[drm:drm_atomic_check_only] checking ffff8801f1253a78
>[32m[  246.068740] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.068743] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.068747] [0m[drm:drm_atomic_commit] committing ffff8801f1253a78
>[32m[  246.085188] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  246.085199] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253a78
>[32m[  246.085259] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  246.085567] [0m[drm:drm_mode_addfb2] [FB:115]
>[32m[  246.085700] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  246.091497] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  246.091512] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  246.091521] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  246.091527] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f5241548
>[32m[  246.091532] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2e758 state to ffff8801f5241548
>[32m[  246.091538] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f12992a8
>[32m[  246.091540] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [CRTC:46:pipe B]
>[32m[  246.091542] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff88020ec2e758
>[32m[  246.091545] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f5241548
>[32m[  246.091554] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9789058 state to ffff8801f5241548
>[32m[  246.091557] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9789058 to [NOCRTC]
>[32m[  246.091559] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9789058 to [CRTC:46:pipe B]
>[32m[  246.091563] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  246.091568] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.091570] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.091603] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 116
>[32m[  246.091625] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.091630] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  246.101860] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  246.101878] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  246.101915] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  246.101921] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cc258 state to ffff880212a68008
>[32m[  246.101926] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1298958 state to ffff880212a68008
>[32m[  246.101929] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc258 to [CRTC:46:pipe B]
>[32m[  246.101931] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8801fb5cc258
>[32m[  246.101933] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  246.101960] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 113
>[32m[  246.101983] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  246.102022] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  246.118525] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  246.118536] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  246.118570] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253a78
>[32m[  246.118576] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cdbc8 state to ffff8801f1253a78
>[32m[  246.118581] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f1253a78
>[32m[  246.118583] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [CRTC:46:pipe B]
>[32m[  246.118586] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5cdbc8
>[32m[  246.118588] [0m[drm:drm_atomic_check_only] checking ffff8801f1253a78
>[32m[  246.118615] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 117
>[32m[  246.118637] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  246.118641] [0m[drm:drm_atomic_commit] committing ffff8801f1253a78
>[32m[  246.135186] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  246.135198] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253a78
>[32m[  246.135223] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801fb5cf9d8
>[32m[  246.135249] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 117
>[32m[  246.135271] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.152098] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  246.152106] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f97893f8 state to ffff8801f5241548
>[32m[  246.152111] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129dd28 state to ffff8801f5241548
>[32m[  246.152114] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  246.152119] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.152122] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.152126] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  246.168508] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  246.168519] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  246.168681] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  246.178375] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1252fd8
>[32m[  246.178382] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5ce9a8 state to ffff8801f1252fd8
>[32m[  246.178386] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cfc28 state to ffff8801f1252fd8
>[32m[  246.178388] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [NOCRTC]
>[32m[  246.178390] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cfc28
>[32m[  246.178394] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cf098 state to ffff8801f1252fd8
>[32m[  246.178396] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [NOCRTC]
>[32m[  246.178397] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf098
>[32m[  246.178401] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5ce758 state to ffff8801f1252fd8
>[32m[  246.178406] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129b7e8 state to ffff8801f1252fd8
>[32m[  246.178410] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cd4d8 state to ffff8801f1252fd8
>[32m[  246.178412] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [NOCRTC]
>[32m[  246.178413] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd4d8
>[32m[  246.178416] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  246.178433] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cd4d8 state to ffff8801f1252fd8
>[32m[  246.178437] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ce508 state to ffff8801f1252fd8
>[32m[  246.178439] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [NOCRTC]
>[32m[  246.178440] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce508
>[32m[  246.178444] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5ce758 state to ffff8801f1252fd8
>[32m[  246.178446] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [NOCRTC]
>[32m[  246.178447] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce758
>[32m[  246.178449] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  246.178459] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5ce758 state to ffff8801f1252fd8
>[32m[  246.178463] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5cf098 state to ffff8801f1252fd8
>[32m[  246.178465] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [NOCRTC]
>[32m[  246.178466] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf098
>[32m[  246.178470] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5ce508 state to ffff8801f1252fd8
>[32m[  246.178471] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [NOCRTC]
>[32m[  246.178473] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce508
>[32m[  246.178477] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cfc28 state to ffff8801f1252fd8
>[32m[  246.178481] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129b7e8 state to ffff8801f1252fd8
>[32m[  246.178485] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cd4d8 state to ffff8801f1252fd8
>[32m[  246.178486] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [NOCRTC]
>[32m[  246.178488] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd4d8
>[32m[  246.178491] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5ce9a8 state to ffff8801f1252fd8
>[32m[  246.178493] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce9a8 to [NOCRTC]
>[32m[  246.178494] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce9a8
>[32m[  246.178498] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cf538 state to ffff8801f1252fd8
>[32m[  246.178502] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cd728 state to ffff8801f1252fd8
>[32m[  246.178504] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [NOCRTC]
>[32m[  246.178505] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd728
>[32m[  246.178509] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802128eabf8 state to ffff8801f1252fd8
>[32m[  246.178511] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [NOCRTC]
>[32m[  246.178513] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eabf8
>[32m[  246.178517] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129a548 state to ffff8801f1252fd8
>[32m[  246.178523] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129a548
>[32m[  246.178525] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [CRTC:36:pipe A]
>[32m[  246.178527] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801fb5ce758
>[32m[  246.178529] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  246.178558] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128eabf8 state to ffff8801f1252fd8
>[32m[  246.178562] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128e86f8 state to ffff8801f1252fd8
>[32m[  246.178564] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [NOCRTC]
>[32m[  246.178565] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e86f8
>[32m[  246.178569] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128e8258 state to ffff8801f1252fd8
>[32m[  246.178571] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e8258 to [NOCRTC]
>[32m[  246.178572] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e8258
>[32m[  246.178576] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128e9978 state to ffff8801f1252fd8
>[32m[  246.178580] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129b7e8 state to ffff8801f1252fd8
>[32m[  246.178584] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128ea2b8 state to ffff8801f1252fd8
>[32m[  246.178586] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [NOCRTC]
>[32m[  246.178587] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128ea2b8
>[32m[  246.178591] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128eb098 state to ffff8801f1252fd8
>[32m[  246.178592] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb098 to [NOCRTC]
>[32m[  246.178594] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb098
>[32m[  246.178598] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128e9728 state to ffff8801f1252fd8
>[32m[  246.178601] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128eb538 state to ffff8801f1252fd8
>[32m[  246.178603] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [NOCRTC]
>[32m[  246.178604] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb538
>[32m[  246.178608] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212de18 state to ffff8801f1252fd8
>[32m[  246.178610] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  246.178611] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  246.178616] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129efc8 state to ffff8801f1252fd8
>[32m[  246.178620] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129efc8
>[32m[  246.178622] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [CRTC:36:pipe A]
>[32m[  246.178623] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802128eabf8
>[32m[  246.178626] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  246.178633] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508d448 state to ffff8801f1252fd8
>[32m[  246.178635] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508d448 to [CRTC:36:pipe A]
>[32m[  246.178639] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129b7e8
>[32m[  246.178641] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [CRTC:46:pipe B]
>[32m[  246.178643] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802128e9978
>[32m[  246.178645] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1252fd8
>[32m[  246.178650] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b95c8 state to ffff8801f1252fd8
>[32m[  246.178653] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b95c8 to [NOCRTC]
>[32m[  246.178655] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b95c8 to [CRTC:46:pipe B]
>[32m[  246.178659] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129a548 state to ffff8801f1252fd8
>[32m[  246.178661] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f129a548
>[32m[  246.178663] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9728 to [NOCRTC]
>[32m[  246.178664] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9728
>[32m[  246.178666] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1252fd8
>[32m[  246.178669] [0m[drm:drm_atomic_check_only] checking ffff8801f1252fd8
>[32m[  246.178672] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  246.178674] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  246.178675] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  246.178679] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  246.178682] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  246.178683] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.178685] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.178687] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  246.178689] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  246.178694] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1252fd8
>[32m[  246.178722] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  246.178744] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  246.178765] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  246.178785] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  246.178806] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  246.178825] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  246.178845] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  246.178864] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  246.178882] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  246.178885] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  246.178903] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  246.178905] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  246.178923] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  246.178941] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  246.178959] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  246.178976] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  246.178997] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  246.179041] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  246.179068] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0
>[32m[  246.179085] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0
>[32m[  246.179103] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0
>[32m[  246.179126] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  246.179146] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  246.179166] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  246.179184] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.179204] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  246.179222] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  246.179240] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  246.179258] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  246.179296] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL B
>[32m[  246.179316] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe A
>[32m[  246.179321] [0m[drm:drm_atomic_commit] committing ffff8801f1252fd8
>[32m[  246.179385] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  246.179404] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  246.179422] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  246.179440] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  246.179464] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  246.179494] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  246.180146] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  246.180328] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  246.180356] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  246.180375] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  246.180400] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  246.180419] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  246.180445] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  246.180467] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 1, on? 0) for crtc 36
>[32m[  246.180486] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  246.215227] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  246.215253] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  246.215292] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  246.215308] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1252fd8
>[32m[  246.215363] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1252fd8
>[32m[  246.219405] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  246.224856] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1255508
>[32m[  246.224865] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212c008 state to ffff8801f1255508
>[32m[  246.224871] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1255508
>[32m[  246.224877] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212ebf8 state to ffff8801f1255508
>[32m[  246.224880] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [NOCRTC]
>[32m[  246.224882] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212ebf8
>[32m[  246.224887] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212c6f8 state to ffff8801f1255508
>[32m[  246.224890] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  246.224892] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  246.224897] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212e9a8 state to ffff8801f1255508
>[32m[  246.224903] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129e678 state to ffff8801f1255508
>[32m[  246.224907] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212d978 state to ffff8801f1255508
>[32m[  246.224910] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [NOCRTC]
>[32m[  246.224913] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212d978
>[32m[  246.224915] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  246.224936] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212d978 state to ffff8801f1255508
>[32m[  246.224942] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129e678 state to ffff8801f1255508
>[32m[  246.224947] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212fc28 state to ffff8801f1255508
>[32m[  246.224950] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [NOCRTC]
>[32m[  246.224952] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212fc28
>[32m[  246.224955] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  246.224966] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212fc28 state to ffff8801f1255508
>[32m[  246.224972] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129e678 state to ffff8801f1255508
>[32m[  246.224977] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212c4a8 state to ffff8801f1255508
>[32m[  246.224979] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [NOCRTC]
>[32m[  246.224982] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c4a8
>[32m[  246.225177] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212d978 state to ffff8801f1255508
>[32m[  246.225180] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [NOCRTC]
>[32m[  246.225182] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212d978
>[32m[  246.225188] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212c008 state to ffff8801f1255508
>[32m[  246.225194] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f1255508
>[32m[  246.225199] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212e9a8 state to ffff8801f1255508
>[32m[  246.225201] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [NOCRTC]
>[32m[  246.225203] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212e9a8
>[32m[  246.225207] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212ebf8 state to ffff8801f1255508
>[32m[  246.225210] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [NOCRTC]
>[32m[  246.225212] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212ebf8
>[32m[  246.225217] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212c6f8 state to ffff8801f1255508
>[32m[  246.225222] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802135a0de8 state to ffff8801f1255508
>[32m[  246.225224] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a0de8 to [NOCRTC]
>[32m[  246.225227] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a0de8
>[32m[  246.225231] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802135a3098 state to ffff8801f1255508
>[32m[  246.225233] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [NOCRTC]
>[32m[  246.225236] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a3098
>[32m[  246.225243] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129e678
>[32m[  246.225245] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [CRTC:36:pipe A]
>[32m[  246.225248] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88021212fc28
>[32m[  246.225251] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  246.225283] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802111ccb98 state to ffff8801f1255508
>[32m[  246.225289] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1255508
>[32m[  246.225294] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802111cc948 state to ffff8801f1255508
>[32m[  246.225296] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [NOCRTC]
>[32m[  246.225298] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc948
>[32m[  246.225303] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802111cf098 state to ffff8801f1255508
>[32m[  246.225306] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf098 to [NOCRTC]
>[32m[  246.225308] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cf098
>[32m[  246.225313] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cf2e8 state to ffff8801f1255508
>[32m[  246.225318] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129dd28 state to ffff8801f1255508
>[32m[  246.225323] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cebf8 state to ffff8801f1255508
>[32m[  246.225325] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [NOCRTC]
>[32m[  246.225327] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cebf8
>[32m[  246.225332] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cd4d8 state to ffff8801f1255508
>[32m[  246.225335] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd4d8 to [NOCRTC]
>[32m[  246.225337] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd4d8
>[32m[  246.225342] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111ccde8 state to ffff8801f1255508
>[32m[  246.225346] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cc6f8 state to ffff8801f1255508
>[32m[  246.225348] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  246.225351] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  246.225355] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cdbc8 state to ffff8801f1255508
>[32m[  246.225357] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cdbc8 to [NOCRTC]
>[32m[  246.225360] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cdbc8
>[32m[  246.225365] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12992a8
>[32m[  246.225368] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccb98 to [CRTC:36:pipe A]
>[32m[  246.225370] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802111ccb98
>[32m[  246.225374] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1255508
>[32m[  246.225382] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f508cd88 state to ffff8801f1255508
>[32m[  246.225386] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508cd88 to [NOCRTC]
>[32m[  246.225389] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f508cd88 to [CRTC:36:pipe A]
>[32m[  246.225395] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129dd28
>[32m[  246.225397] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf2e8 to [CRTC:46:pipe B]
>[32m[  246.225400] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802111cf2e8
>[32m[  246.225403] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1255508
>[32m[  246.225408] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801f1255508
>[32m[  246.225411] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b81d8 to [NOCRTC]
>[32m[  246.225414] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b81d8 to [CRTC:46:pipe B]
>[32m[  246.225420] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff88020ffbc138 state to ffff8801f1255508
>[32m[  246.225422] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff88020ffbc138
>[32m[  246.225425] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [NOCRTC]
>[32m[  246.225427] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111ccde8
>[32m[  246.225430] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1255508
>[32m[  246.225434] [0m[drm:drm_atomic_check_only] checking ffff8801f1255508
>[32m[  246.225440] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  246.225443] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  246.225445] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.225448] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.225480] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  246.225536] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.225561] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  246.225584] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.225592] [0m[drm:drm_atomic_commit] committing ffff8801f1255508
>[32m[  246.235174] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1255508
>[32m[  246.235222] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1255508
>[32m[  246.271577] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  246.271678] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  246.288244] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  246.288280] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  246.288308] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  246.288329] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  246.326385] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  246.326459] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  246.326463] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  246.326466] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  246.326468] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  246.326470] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  246.326472] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  246.326474] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  246.326476] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  246.326478] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  246.326481] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  246.326483] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  246.326485] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  246.326487] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  246.326576] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  246.326607] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  246.401681] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  246.401704] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  246.403763] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  246.403769] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  246.403773] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  246.403789] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  246.403902] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  246.403905] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  246.403906] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  246.404245] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  246.404249] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  246.404251] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  246.404254] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  246.404256] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  246.404258] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  246.404260] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  246.404262] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  246.404264] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  246.404267] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  246.404269] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  246.404271] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  246.404273] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  246.404275] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  246.404277] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  246.404279] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  246.404281] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  246.404283] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  246.404285] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  246.404447] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.404455] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049b38 state to ffff8801f1256f98
>[32m[  246.404461] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126efc8 state to ffff8801f1256f98
>[32m[  246.404464] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.404469] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.404472] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.404478] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.418508] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.418522] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.418548] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  246.418575] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  246.421130] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.423662] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.426191] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.428717] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.431249] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.433774] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.436300] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.438826] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.441351] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.443878] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.446404] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.448928] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.451453] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.453977] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.456555] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.459089] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.461617] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.464142] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.466665] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.469191] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.471714] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.474240] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.476762] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.479288] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.481810] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.484333] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.486857] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.489383] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.491906] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.494429] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.496953] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.499477] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  246.499485] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  246.499489] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  246.499645] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  246.499653] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff88020e048008 state to ffff8801f5241548
>[32m[  246.499656] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  246.499659] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  246.499661] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  246.499664] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  246.499676] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  246.499690] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  246.499764] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest legacy-pipe-B-tiling-x
>[32m[  246.500402] [0m[drm:drm_mode_addfb2] [FB:98]
>[32m[  246.507137] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  246.507158] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  246.507164] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1268008 state to ffff8801f5245508
>[32m[  246.507170] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020e0794d8 state to ffff8801f5245508
>[32m[  246.507172] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f1268008
>[32m[  246.507174] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e0794d8 to [NOCRTC]
>[32m[  246.507177] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e0794d8
>[32m[  246.507180] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f5245508
>[32m[  246.507188] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97eea28 state to ffff8801f5245508
>[32m[  246.507191] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97eea28 to [NOCRTC]
>[32m[  246.507194] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  246.507196] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  246.507198] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  246.507200] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  246.507203] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  246.507205] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  246.507207] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: n, active: n
>[32m[  246.507210] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f5245508
>[32m[  246.507241] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb -1
>[32m[  246.507264] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  246.507269] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  246.507333] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  246.531692] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 1, on? 1) for crtc 36
>[32m[  246.531720] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  246.531953] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  246.531976] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  246.531995] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  246.532175] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  246.532199] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  246.532235] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  246.532276] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  246.532285] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  246.532299] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  246.532351] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.532356] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e07a508 state to ffff8801f1256f98
>[32m[  246.532359] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [NOCRTC]
>[32m[  246.532361] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a508
>[32m[  246.532375] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.532378] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.532390] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.532403] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.532425] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.532430] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e078de8 state to ffff8801f1256f98
>[32m[  246.532432] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078de8 to [NOCRTC]
>[32m[  246.532434] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078de8
>[32m[  246.532436] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.532438] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.532447] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.532457] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.532471] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  246.532491] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  246.532499] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.532504] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126dd28 state to ffff8801f1256f98
>[32m[  246.532510] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2cde8 state to ffff8801f1256f98
>[32m[  246.532515] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126dd28
>[32m[  246.532517] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [CRTC:46:pipe B]
>[32m[  246.532520] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:98] for plane state ffff88020ec2cde8
>[32m[  246.532522] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  246.532531] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff8801f1256f98
>[32m[  246.532533] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048918 to [NOCRTC]
>[32m[  246.532538] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97ef448 state to ffff8801f1256f98
>[32m[  246.532540] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97ef448 to [CRTC:46:pipe B]
>[32m[  246.532544] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.532547] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  246.532550] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  246.532553] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:46:pipe B]
>[32m[  246.532555] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.532557] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  246.532559] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  246.532562] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  246.532566] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1256f98
>[32m[  246.532588] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  246.532608] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  246.532628] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  246.532647] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  246.532667] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  246.532686] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  246.532706] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  246.532725] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  246.532743] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  246.532746] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  246.532764] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  246.532766] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  246.532785] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  246.532803] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  246.532821] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  246.532839] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  246.532859] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  246.532877] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  246.532896] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:96, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  246.532914] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  246.532931] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  246.532954] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 98
>[32m[  246.532974] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  246.534037] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  246.534070] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  246.534075] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.536652] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  246.569434] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  246.569462] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  246.569693] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  246.569714] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  246.569736] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  246.569756] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  246.569778] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  246.569802] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  246.569833] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  246.570479] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  246.570660] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  246.570690] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  246.570710] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  246.570735] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  246.570754] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  246.570771] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  246.570794] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  246.570814] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  246.605546] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  246.605578] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  246.605617] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  246.605628] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.605643] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.605686] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.605692] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2f538 state to ffff8801f1256f98
>[32m[  246.605694] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [NOCRTC]
>[32m[  246.605696] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f538
>[32m[  246.605699] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.605702] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.605714] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.605729] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.605750] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.605755] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2dbc8 state to ffff8801f1256f98
>[32m[  246.605757] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2dbc8 to [NOCRTC]
>[32m[  246.605759] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2dbc8
>[32m[  246.605761] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.605764] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.605772] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.605782] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.622145] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  246.622169] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.622175] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f95e12a8 state to ffff8801f1256f98
>[32m[  246.622180] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2e2b8 state to ffff8801f1256f98
>[32m[  246.622182] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f95e12a8
>[32m[  246.622185] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [NOCRTC]
>[32m[  246.622187] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e2b8
>[32m[  246.622190] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1256f98
>[32m[  246.622193] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.622198] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.622224] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.622235] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.622265] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.622270] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2f098 state to ffff8801f1256f98
>[32m[  246.622272] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f098 to [NOCRTC]
>[32m[  246.622274] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f098
>[32m[  246.622276] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.622279] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.622288] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.622298] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.622317] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1256f98
>[32m[  246.622322] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2c4a8 state to ffff8801f1256f98
>[32m[  246.622324] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [NOCRTC]
>[32m[  246.622326] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c4a8
>[32m[  246.622328] [0m[drm:drm_atomic_check_only] checking ffff8801f1256f98
>[32m[  246.622331] [0m[drm:drm_atomic_commit] committing ffff8801f1256f98
>[32m[  246.622338] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1256f98
>[32m[  246.622348] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1256f98
>[32m[  246.655805] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  246.656043] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  246.660577] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  246.662554] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  246.662569] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  246.662579] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  246.662585] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121a548 state to ffff880212a68008
>[32m[  246.662589] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2ee48 state to ffff880212a68008
>[32m[  246.662595] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121a548
>[32m[  246.662597] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2ee48 to [CRTC:46:pipe B]
>[32m[  246.662599] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff88020ec2ee48
>[32m[  246.662602] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212a68008
>[32m[  246.662610] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97eea28 state to ffff880212a68008
>[32m[  246.662614] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97eea28 to [NOCRTC]
>[32m[  246.662616] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97eea28 to [CRTC:46:pipe B]
>[32m[  246.662620] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  246.662625] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  246.662628] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  246.662659] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 100
>[32m[  246.662681] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.662686] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  246.672030] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  246.672047] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  246.672084] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  246.672089] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2e9a8 state to ffff8801f1253528
>[32m[  246.672094] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121ae98 state to ffff8801f1253528
>[32m[  246.672096] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [CRTC:46:pipe B]
>[32m[  246.672098] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff88020ec2e9a8
>[32m[  246.672100] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  246.672128] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 66
>[32m[  246.672150] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  246.672155] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  246.688655] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  246.688666] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  246.688699] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  246.688704] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2cde8 state to ffff880211b85fa8
>[32m[  246.688709] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121a548 state to ffff880211b85fa8
>[32m[  246.688712] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [CRTC:46:pipe B]
>[32m[  246.688714] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff88020ec2cde8
>[32m[  246.688716] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  246.688743] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 99
>[32m[  246.688765] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  246.688769] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  246.705275] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  246.705289] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  246.705318] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8801fb5ce758
>[32m[  246.705344] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 99
>[32m[  246.705367] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.722340] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  246.722349] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048e88 state to ffff880212118008
>[32m[  246.722351] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  246.722354] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.722356] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  246.722359] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  246.722371] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  246.722385] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  246.722432] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  246.728146] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  246.728169] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  246.728177] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  246.728183] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1219bf8 state to ffff880211b85fa8
>[32m[  246.728188] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cfc28 state to ffff880211b85fa8
>[32m[  246.728194] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1219bf8
>[32m[  246.728196] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [CRTC:46:pipe B]
>[32m[  246.728199] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8801fb5cfc28
>[32m[  246.728201] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880211b85fa8
>[32m[  246.728209] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97ef448 state to ffff880211b85fa8
>[32m[  246.728212] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97ef448 to [NOCRTC]
>[32m[  246.728217] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049b38 state to ffff880211b85fa8
>[32m[  246.728220] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e049b38 to [CRTC:46:pipe B]
>[32m[  246.728224] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  246.728226] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  246.728230] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  246.728232] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  246.728234] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.728237] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:46:pipe B]
>[32m[  246.728239] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  246.728242] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880211b85fa8
>[32m[  246.728248] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cd288 state to ffff880211b85fa8
>[32m[  246.728252] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cd4d8 state to ffff880211b85fa8
>[32m[  246.728255] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880211b85fa8
>[32m[  246.728284] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  246.728306] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  246.728329] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  246.728350] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  246.728371] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  246.728391] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  246.728411] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  246.728431] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  246.728451] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  246.728470] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  246.728488] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  246.728491] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  246.728509] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  246.728512] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  246.728531] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  246.728549] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  246.728567] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  246.728585] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  246.728605] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  246.728623] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  246.728642] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  246.728661] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  246.728679] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:99, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  246.728703] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 102
>[32m[  246.728722] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  246.728743] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 66
>[32m[  246.728762] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  246.728781] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 99
>[32m[  246.728800] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  246.728838] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  246.728858] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  246.728862] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  246.731908] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  246.757353] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  246.757381] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  246.757614] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  246.757638] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  246.757657] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  246.757677] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  246.757698] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  246.757722] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  246.757752] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  246.758437] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  246.758621] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  246.758649] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  246.758669] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  246.758695] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  246.758714] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  246.758732] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  246.758754] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  246.758774] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  246.793593] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  246.793624] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  246.793664] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  246.793676] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  246.793694] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  246.793739] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  246.793744] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5ce508 state to ffff880212118008
>[32m[  246.793749] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9692e98 state to ffff880212118008
>[32m[  246.793751] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [NOCRTC]
>[32m[  246.793754] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce508
>[32m[  246.793756] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  246.793779] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  246.793799] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  246.793803] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  246.810234] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  246.810246] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  246.810274] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  246.810279] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cd288 state to ffff880212a68008
>[32m[  246.810284] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f9694a88 state to ffff880212a68008
>[32m[  246.810287] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd288 to [NOCRTC]
>[32m[  246.810289] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd288
>[32m[  246.810291] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  246.810317] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  246.810339] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  246.810343] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  246.826893] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  246.826907] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  246.877109] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  246.877118] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049798 state to ffff880212118008
>[32m[  246.877124] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff880212118008
>[32m[  246.877126] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  246.877131] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.877134] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.877139] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  246.893570] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  246.893583] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  246.893840] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  246.894029] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  246.898291] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  246.900102] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  246.900123] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  246.900132] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  246.900137] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129e678 state to ffff880212a68008
>[32m[  246.900142] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cf538 state to ffff880212a68008
>[32m[  246.900148] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129e678
>[32m[  246.900151] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf538 to [CRTC:46:pipe B]
>[32m[  246.900153] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801fb5cf538
>[32m[  246.900156] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212a68008
>[32m[  246.900164] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff880212a68008
>[32m[  246.900167] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [NOCRTC]
>[32m[  246.900169] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [CRTC:46:pipe B]
>[32m[  246.900173] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  246.900178] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.900181] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.900212] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 108
>[32m[  246.900235] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.900240] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  246.910241] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  246.910258] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  246.910301] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  246.910306] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5ce2b8 state to ffff880212118008
>[32m[  246.910311] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff880212118008
>[32m[  246.910313] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce2b8 to [CRTC:46:pipe B]
>[32m[  246.910315] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:99] for plane state ffff8801fb5ce2b8
>[32m[  246.910317] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  246.910346] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 99
>[32m[  246.910368] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  246.910373] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  246.926907] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  246.926919] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  246.926952] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  246.926957] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cf2e8 state to ffff880212a68008
>[32m[  246.926962] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129e678 state to ffff880212a68008
>[32m[  246.926965] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf2e8 to [CRTC:46:pipe B]
>[32m[  246.926967] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801fb5cf2e8
>[32m[  246.926969] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  246.926996] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 109
>[32m[  246.927060] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  246.927069] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  246.943568] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  246.943581] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  246.943606] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801fb5cd288
>[32m[  246.943632] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 109
>[32m[  246.943654] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  246.960426] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  246.960434] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049b38 state to ffff8801f1253528
>[32m[  246.960440] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ae98 state to ffff8801f1253528
>[32m[  246.960442] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  246.960447] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.960450] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  246.960454] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  246.976891] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  246.976902] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  246.977231] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  246.983543] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  246.983558] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  246.983567] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  246.983573] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ca88 state to ffff8801f1253528
>[32m[  246.983578] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cd4d8 state to ffff8801f1253528
>[32m[  246.983583] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129ca88
>[32m[  246.983585] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [CRTC:46:pipe B]
>[32m[  246.983588] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801fb5cd4d8
>[32m[  246.983591] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253528
>[32m[  246.983599] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049798 state to ffff8801f1253528
>[32m[  246.983602] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e049798 to [NOCRTC]
>[32m[  246.983607] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97eea28 state to ffff8801f1253528
>[32m[  246.983609] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97eea28 to [CRTC:46:pipe B]
>[32m[  246.983613] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  246.983616] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  246.983619] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  246.983622] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:46:pipe B]
>[32m[  246.983624] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  246.983626] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  246.983629] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  246.983631] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253528
>[32m[  246.983637] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cd288 state to ffff8801f1253528
>[32m[  246.983642] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff880212945978 state to ffff8801f1253528
>[32m[  246.983645] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253528
>[32m[  246.983675] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  246.983697] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  246.983718] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  246.983738] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  246.983759] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  246.983779] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  246.983799] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  246.983818] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  246.983837] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  246.983839] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  246.983858] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  246.983860] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  246.983880] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  246.983898] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  246.983917] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  246.983935] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  246.983955] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  246.983974] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  246.983993] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  246.984046] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:99, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  246.984069] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:109, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  246.984096] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 110
>[32m[  246.984119] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  246.984142] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 99
>[32m[  246.984164] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  246.984186] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 109
>[32m[  246.984208] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  246.984250] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  246.984271] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  246.984276] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  246.986763] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  247.010702] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  247.010730] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  247.010963] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  247.010983] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  247.011047] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  247.011073] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  247.011097] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.011121] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  247.011153] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  247.011773] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  247.011956] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  247.011986] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  247.012039] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  247.012068] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  247.012089] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  247.012107] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  247.012131] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  247.012152] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  247.046886] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  247.046916] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  247.046955] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.046966] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  247.046985] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  247.047069] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  247.047075] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212c258 state to ffff880212118008
>[32m[  247.047080] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ae98 state to ffff880212118008
>[32m[  247.047083] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c258 to [NOCRTC]
>[32m[  247.047085] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c258
>[32m[  247.047088] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  247.047112] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  247.047134] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  247.047139] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  247.063488] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  247.063500] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  247.063529] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  247.063535] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212fc28 state to ffff880212a68008
>[32m[  247.063540] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ca88 state to ffff880212a68008
>[32m[  247.063542] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [NOCRTC]
>[32m[  247.063544] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212fc28
>[32m[  247.063546] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  247.063572] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  247.063594] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  247.063598] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  247.080111] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  247.080125] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  247.130393] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  247.130540] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  247.135077] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  247.137111] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  247.137133] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  247.137143] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  247.137148] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ae98 state to ffff8801f1253528
>[32m[  247.137153] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212c008 state to ffff8801f1253528
>[32m[  247.137159] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129ae98
>[32m[  247.137161] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [CRTC:46:pipe B]
>[32m[  247.137163] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88021212c008
>[32m[  247.137166] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253528
>[32m[  247.137175] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97efcb8 state to ffff8801f1253528
>[32m[  247.137178] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97efcb8 to [NOCRTC]
>[32m[  247.137181] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97efcb8 to [CRTC:46:pipe B]
>[32m[  247.137185] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  247.137190] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  247.137193] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:46:pipe B]
>[32m[  247.137226] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 112
>[32m[  247.137250] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.137255] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  247.146623] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  247.146640] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  247.146684] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  247.146690] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802135a3098 state to ffff880212118008
>[32m[  247.146695] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ca88 state to ffff880212118008
>[32m[  247.146697] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [CRTC:46:pipe B]
>[32m[  247.146700] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802135a3098
>[32m[  247.146702] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  247.146731] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 109
>[32m[  247.146754] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  247.146758] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  247.163254] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  247.163266] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  247.163300] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  247.163306] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128eabf8 state to ffff8801f1253528
>[32m[  247.163311] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ae98 state to ffff8801f1253528
>[32m[  247.163313] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [CRTC:46:pipe B]
>[32m[  247.163316] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802128eabf8
>[32m[  247.163318] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  247.163346] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 113
>[32m[  247.163369] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  247.163374] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  247.179866] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  247.179880] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  247.179905] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802128e86f8
>[32m[  247.179932] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 113
>[32m[  247.179955] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.196879] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  247.196887] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff880212a68008
>[32m[  247.196890] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  247.196893] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.196896] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  247.196899] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  247.196911] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  247.196925] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  247.196974] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  247.202837] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  247.202858] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  247.202867] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  247.202873] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1299bf8 state to ffff880212118008
>[32m[  247.202878] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128ea2b8 state to ffff880212118008
>[32m[  247.202883] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1299bf8
>[32m[  247.202886] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [CRTC:46:pipe B]
>[32m[  247.202888] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8802128ea2b8
>[32m[  247.202891] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212118008
>[32m[  247.202899] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97eea28 state to ffff880212118008
>[32m[  247.202902] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97eea28 to [NOCRTC]
>[32m[  247.202907] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049b38 state to ffff880212118008
>[32m[  247.202910] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e049b38 to [CRTC:46:pipe B]
>[32m[  247.202914] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  247.202917] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  247.202921] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  247.202923] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  247.202925] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.202928] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:46:pipe B]
>[32m[  247.202930] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  247.202933] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212118008
>[32m[  247.202939] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec51728 state to ffff880212118008
>[32m[  247.202945] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cdbc8 state to ffff880212118008
>[32m[  247.202948] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212118008
>[32m[  247.202977] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  247.203000] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  247.203052] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  247.203077] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  247.203100] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  247.203123] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  247.203146] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  247.203169] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  247.203192] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  247.203214] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  247.203235] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  247.203239] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  247.203259] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  247.203263] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  247.203284] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  247.203304] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  247.203345] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  247.203364] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  247.203386] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  247.203406] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  247.203426] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:112, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  247.203445] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] FB:109, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  247.203465] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:113, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  247.203490] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 114
>[32m[  247.203526] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  247.203549] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 109
>[32m[  247.203570] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  247.203592] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 113
>[32m[  247.203612] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  247.203653] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL A
>[32m[  247.203689] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe B
>[32m[  247.203695] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  247.206261] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  247.230700] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  247.230728] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  247.230962] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  247.230985] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  247.231045] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  247.231070] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  247.231095] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.231120] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  247.231152] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  247.231813] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  247.232005] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  247.232061] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  247.232083] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  247.232110] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  247.232131] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  247.232150] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  247.232174] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 2, on? 0) for crtc 46
>[32m[  247.232196] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  247.267038] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  247.267077] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  247.267117] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.267129] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  247.267149] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  247.267191] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  247.267197] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cc6f8 state to ffff8801f1253528
>[32m[  247.267202] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1268958 state to ffff8801f1253528
>[32m[  247.267204] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  247.267206] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  247.267209] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  247.267231] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  247.267252] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  247.267256] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  247.283654] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  247.283666] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  247.283694] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  247.283700] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802111cfc28 state to ffff880212118008
>[32m[  247.283704] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126c138 state to ffff880212118008
>[32m[  247.283707] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cfc28 to [NOCRTC]
>[32m[  247.283709] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cfc28
>[32m[  247.283711] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  247.283737] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  247.283760] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  247.283764] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  247.300313] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  247.300327] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  247.350525] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  247.350534] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff880212a68008
>[32m[  247.350539] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1268958 state to ffff880212a68008
>[32m[  247.350541] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  247.350547] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.350550] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  247.350554] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  247.367014] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  247.367026] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  247.367290] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  247.367429] [0m[drm:drm_mode_addfb2] [FB:115]
>[32m[  247.371568] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  247.373363] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  247.373386] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  247.373395] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  247.373400] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126b7e8 state to ffff8801f1253528
>[32m[  247.373405] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802111cc948 state to ffff8801f1253528
>[32m[  247.373411] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126b7e8
>[32m[  247.373413] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc948 to [CRTC:46:pipe B]
>[32m[  247.373416] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8802111cc948
>[32m[  247.373418] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253528
>[32m[  247.373427] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff8801f1253528
>[32m[  247.373430] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048918 to [NOCRTC]
>[32m[  247.373432] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048918 to [CRTC:46:pipe B]
>[32m[  247.373437] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  247.373442] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.373444] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  247.373476] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 116
>[32m[  247.373499] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.373504] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  247.383665] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  247.383682] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  247.383719] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  247.383724] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802111cebf8 state to ffff880212a68008
>[32m[  247.383729] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff88020f82dd28 state to ffff880212a68008
>[32m[  247.383732] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cebf8 to [CRTC:46:pipe B]
>[32m[  247.383734] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802111cebf8
>[32m[  247.383736] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  247.383765] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb 113
>[32m[  247.383787] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  247.383791] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  247.400328] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  247.400339] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  247.400373] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  247.400378] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ffdee48 state to ffff8801f1253528
>[32m[  247.400383] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8802106c6678 state to ffff8801f1253528
>[32m[  247.400386] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdee48 to [CRTC:46:pipe B]
>[32m[  247.400388] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff88020ffdee48
>[32m[  247.400390] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  247.400417] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 117
>[32m[  247.400440] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  247.400444] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  247.417010] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  247.417023] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  247.417058] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8801f95304a8
>[32m[  247.417084] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb 117
>[32m[  247.417106] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.433874] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  247.433882] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0493f8 state to ffff880212118008
>[32m[  247.433888] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1219bf8 state to ffff880212118008
>[32m[  247.433891] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  247.433896] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.433899] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  247.433903] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  247.450311] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  247.450323] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  247.450481] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  247.460372] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212a68008
>[32m[  247.460379] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9533788 state to ffff880212a68008
>[32m[  247.460384] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95332e8 state to ffff880212a68008
>[32m[  247.460386] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [NOCRTC]
>[32m[  247.460388] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95332e8
>[32m[  247.460392] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9531728 state to ffff880212a68008
>[32m[  247.460394] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [NOCRTC]
>[32m[  247.460395] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531728
>[32m[  247.460400] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9532e48 state to ffff880212a68008
>[32m[  247.460404] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121dd28 state to ffff880212a68008
>[32m[  247.460407] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  247.460424] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9532e48 state to ffff880212a68008
>[32m[  247.460428] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95339d8 state to ffff880212a68008
>[32m[  247.460429] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  247.460431] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  247.460435] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9531728 state to ffff880212a68008
>[32m[  247.460436] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [NOCRTC]
>[32m[  247.460438] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531728
>[32m[  247.460440] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  247.460450] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9531728 state to ffff880212a68008
>[32m[  247.460454] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95332e8 state to ffff880212a68008
>[32m[  247.460456] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [NOCRTC]
>[32m[  247.460457] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95332e8
>[32m[  247.460461] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f95339d8 state to ffff880212a68008
>[32m[  247.460463] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  247.460464] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  247.460468] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9533788 state to ffff880212a68008
>[32m[  247.460473] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121dd28 state to ffff880212a68008
>[32m[  247.460476] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9532e48 state to ffff880212a68008
>[32m[  247.460478] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532e48 to [NOCRTC]
>[32m[  247.460480] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532e48
>[32m[  247.460484] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9530258 state to ffff880212a68008
>[32m[  247.460485] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [NOCRTC]
>[32m[  247.460487] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530258
>[32m[  247.460491] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f9530948 state to ffff880212a68008
>[32m[  247.460495] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9532758 state to ffff880212a68008
>[32m[  247.460496] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [NOCRTC]
>[32m[  247.460498] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532758
>[32m[  247.460502] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9531288 state to ffff880212a68008
>[32m[  247.460503] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [NOCRTC]
>[32m[  247.460505] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531288
>[32m[  247.460509] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121a548 state to ffff880212a68008
>[32m[  247.460515] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121a548
>[32m[  247.460517] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [CRTC:36:pipe A]
>[32m[  247.460519] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9531728
>[32m[  247.460521] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  247.460550] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9531288 state to ffff880212a68008
>[32m[  247.460554] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9533538 state to ffff880212a68008
>[32m[  247.460556] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533538 to [NOCRTC]
>[32m[  247.460557] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533538
>[32m[  247.460561] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9532758 state to ffff880212a68008
>[32m[  247.460563] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [NOCRTC]
>[32m[  247.460564] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532758
>[32m[  247.460568] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9531038 state to ffff880212a68008
>[32m[  247.460572] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121dd28 state to ffff880212a68008
>[32m[  247.460576] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9530948 state to ffff880212a68008
>[32m[  247.460578] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [NOCRTC]
>[32m[  247.460579] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530948
>[32m[  247.460583] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9530008 state to ffff880212a68008
>[32m[  247.460585] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [NOCRTC]
>[32m[  247.460586] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530008
>[32m[  247.460590] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f9530258 state to ffff880212a68008
>[32m[  247.460594] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9532bf8 state to ffff880212a68008
>[32m[  247.460596] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [NOCRTC]
>[32m[  247.460597] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532bf8
>[32m[  247.460601] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9532e48 state to ffff880212a68008
>[32m[  247.460603] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532e48 to [NOCRTC]
>[32m[  247.460604] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532e48
>[32m[  247.460609] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f121ae98 state to ffff880212a68008
>[32m[  247.460613] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f121ae98
>[32m[  247.460614] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [CRTC:36:pipe A]
>[32m[  247.460616] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9531288
>[32m[  247.460618] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212a68008
>[32m[  247.460626] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97ef5f8 state to ffff880212a68008
>[32m[  247.460628] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97ef5f8 to [CRTC:36:pipe A]
>[32m[  247.460632] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121dd28
>[32m[  247.460634] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [CRTC:46:pipe B]
>[32m[  247.460636] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9531038
>[32m[  247.460638] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212a68008
>[32m[  247.460643] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135becb8 state to ffff880212a68008
>[32m[  247.460646] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135becb8 to [NOCRTC]
>[32m[  247.460648] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135becb8 to [CRTC:46:pipe B]
>[32m[  247.460652] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f121a548 state to ffff880212a68008
>[32m[  247.460654] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f121a548
>[32m[  247.460656] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [NOCRTC]
>[32m[  247.460657] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530258
>[32m[  247.460659] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880212a68008
>[32m[  247.460662] [0m[drm:drm_atomic_check_only] checking ffff880212a68008
>[32m[  247.460665] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  247.460667] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  247.460668] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  247.460672] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  247.460675] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  247.460676] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.460678] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  247.460681] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  247.460683] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212a68008
>[32m[  247.460687] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212a68008
>[32m[  247.460714] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  247.460736] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  247.460757] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  247.460777] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  247.460798] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  247.460818] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  247.460837] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  247.460856] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  247.460875] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  247.460877] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  247.460895] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  247.460897] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  247.460915] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  247.460933] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  247.460951] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  247.460968] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  247.460988] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  247.461032] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  247.461058] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0
>[32m[  247.461076] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0
>[32m[  247.461093] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0
>[32m[  247.461116] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  247.461136] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  247.461155] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  247.461174] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.461192] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:40:sprite B] with fb -1
>[32m[  247.461210] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:40:sprite B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  247.461229] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:43:cursor B] with fb -1
>[32m[  247.461247] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:43:cursor B] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  247.461284] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL B
>[32m[  247.461303] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe A
>[32m[  247.461309] [0m[drm:drm_atomic_commit] committing ffff880212a68008
>[32m[  247.461373] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  247.461392] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  247.461410] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  247.461429] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.461452] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  247.461483] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  247.462134] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  247.462315] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  247.462343] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  247.462362] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  247.462387] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  247.462405] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  247.462423] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  247.462454] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 1, on? 0) for crtc 36
>[32m[  247.462473] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  247.497213] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  247.497238] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  247.497278] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  247.497295] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212a68008
>[32m[  247.497346] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212a68008
>[32m[  247.501379] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  247.506898] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1250aa8
>[32m[  247.506906] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95304a8 state to ffff8801f1250aa8
>[32m[  247.506913] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880210694a88 state to ffff8801f1250aa8
>[32m[  247.506918] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9531728 state to ffff8801f1250aa8
>[32m[  247.506921] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [NOCRTC]
>[32m[  247.506923] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531728
>[32m[  247.506928] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9533788 state to ffff8801f1250aa8
>[32m[  247.506931] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [NOCRTC]
>[32m[  247.506933] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533788
>[32m[  247.506939] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f95332e8 state to ffff8801f1250aa8
>[32m[  247.506944] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8802144bc138 state to ffff8801f1250aa8
>[32m[  247.506964] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  247.506986] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95332e8 state to ffff8801f1250aa8
>[32m[  247.507137] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129a548 state to ffff8801f1250aa8
>[32m[  247.507143] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95339d8 state to ffff8801f1250aa8
>[32m[  247.507145] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  247.507147] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  247.507150] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  247.507162] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95339d8 state to ffff8801f1250aa8
>[32m[  247.507168] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129a548 state to ffff8801f1250aa8
>[32m[  247.507173] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95304a8 state to ffff8801f1250aa8
>[32m[  247.507175] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [NOCRTC]
>[32m[  247.507178] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95304a8
>[32m[  247.507183] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f95332e8 state to ffff8801f1250aa8
>[32m[  247.507185] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [NOCRTC]
>[32m[  247.507187] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95332e8
>[32m[  247.507192] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9531728 state to ffff8801f1250aa8
>[32m[  247.507197] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129efc8 state to ffff8801f1250aa8
>[32m[  247.507202] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9533788 state to ffff8801f1250aa8
>[32m[  247.507204] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [NOCRTC]
>[32m[  247.507206] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533788
>[32m[  247.507212] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802121314d8 state to ffff8801f1250aa8
>[32m[  247.507214] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [NOCRTC]
>[32m[  247.507216] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121314d8
>[32m[  247.507221] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff880212131288 state to ffff8801f1250aa8
>[32m[  247.507226] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff880212131038 state to ffff8801f1250aa8
>[32m[  247.507228] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [NOCRTC]
>[32m[  247.507230] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131038
>[32m[  247.507234] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff880212131978 state to ffff8801f1250aa8
>[32m[  247.507237] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [NOCRTC]
>[32m[  247.507239] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131978
>[32m[  247.507247] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129a548
>[32m[  247.507250] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [CRTC:36:pipe A]
>[32m[  247.507253] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f95339d8
>[32m[  247.507255] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  247.507302] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff880212131978 state to ffff8801f1250aa8
>[32m[  247.507308] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff8801f1250aa8
>[32m[  247.507313] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802121329a8 state to ffff8801f1250aa8
>[32m[  247.507316] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [NOCRTC]
>[32m[  247.507318] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121329a8
>[32m[  247.507323] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212131038 state to ffff8801f1250aa8
>[32m[  247.507325] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131038 to [NOCRTC]
>[32m[  247.507327] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131038
>[32m[  247.507333] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802121314d8 state to ffff8801f1250aa8
>[32m[  247.507338] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129a548 state to ffff8801f1250aa8
>[32m[  247.507343] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff880212131288 state to ffff8801f1250aa8
>[32m[  247.507345] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [NOCRTC]
>[32m[  247.507348] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131288
>[32m[  247.507353] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ee52e48 state to ffff8801f1250aa8
>[32m[  247.507355] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee52e48 to [NOCRTC]
>[32m[  247.507357] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee52e48
>[32m[  247.507362] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ee51978 state to ffff8801f1250aa8
>[32m[  247.507366] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ee529a8 state to ffff8801f1250aa8
>[32m[  247.507368] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee529a8 to [NOCRTC]
>[32m[  247.507370] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee529a8
>[32m[  247.507375] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020e078258 state to ffff8801f1250aa8
>[32m[  247.507378] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [NOCRTC]
>[32m[  247.507380] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078258
>[32m[  247.507385] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f12992a8
>[32m[  247.507388] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [CRTC:36:pipe A]
>[32m[  247.507390] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff880212131978
>[32m[  247.507393] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1250aa8
>[32m[  247.507401] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f97ee518 state to ffff8801f1250aa8
>[32m[  247.507405] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97ee518 to [NOCRTC]
>[32m[  247.507408] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f97ee518 to [CRTC:36:pipe A]
>[32m[  247.507414] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129a548
>[32m[  247.507416] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [CRTC:46:pipe B]
>[32m[  247.507419] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802121314d8
>[32m[  247.507422] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1250aa8
>[32m[  247.507428] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f9788ae8 state to ffff8801f1250aa8
>[32m[  247.507431] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788ae8 to [NOCRTC]
>[32m[  247.507434] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9788ae8 to [CRTC:46:pipe B]
>[32m[  247.507453] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129e678 state to ffff8801f1250aa8
>[32m[  247.507456] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f129e678
>[32m[  247.507459] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee51978 to [NOCRTC]
>[32m[  247.507461] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee51978
>[32m[  247.507464] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1250aa8
>[32m[  247.507468] [0m[drm:drm_atomic_check_only] checking ffff8801f1250aa8
>[32m[  247.507474] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  247.507478] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  247.507480] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.507483] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  247.507514] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  247.507539] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.507563] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  247.507586] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.507594] [0m[drm:drm_atomic_commit] committing ffff8801f1250aa8
>[32m[  247.516968] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1250aa8
>[32m[  247.517136] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1250aa8
>[32m[  247.554098] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  247.554200] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  247.569222] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  247.569258] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  247.569286] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  247.569307] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  247.607299] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  247.607372] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  247.607375] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  247.607378] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  247.607380] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  247.607382] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  247.607384] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  247.607386] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  247.607388] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  247.607391] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  247.607393] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  247.607395] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  247.607397] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  247.607399] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  247.607495] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  247.607525] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  247.682636] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  247.682658] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  247.684716] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  247.684722] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  247.684726] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  247.684742] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  247.684857] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  247.684859] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  247.684861] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  247.685197] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  247.685201] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  247.685204] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  247.685206] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  247.685220] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  247.685223] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  247.685225] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  247.685227] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  247.685229] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  247.685232] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  247.685234] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  247.685236] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  247.685238] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  247.685240] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  247.685242] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  247.685245] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  247.685247] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  247.685249] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  247.685251] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  247.685423] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  247.685431] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135aa748 state to ffff8801f5241548
>[32m[  247.685446] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121dd28 state to ffff8801f5241548
>[32m[  247.685449] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  247.685454] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.685457] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  247.685463] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  247.700313] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  247.700327] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  247.700354] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  247.700380] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  247.702954] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.705507] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.708079] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.710630] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.713182] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.715742] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.718295] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.720844] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.723395] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.725938] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.728490] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.731051] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.733624] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.736175] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.738725] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.741272] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.743822] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.746372] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.748923] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.751473] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.754114] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.756663] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.759217] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.761769] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.764322] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.766872] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.769423] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.771964] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.774521] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.777118] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.779670] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.782221] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  247.782229] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  247.782233] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  247.782386] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  247.782393] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802135ab058 state to ffff8801f5241548
>[32m[  247.782395] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  247.782398] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  247.782401] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  247.782404] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  247.782416] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  247.782430] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  247.782505] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest legacy-pipe-C-tiling-none
>[32m[  247.782735] [0m[drm:drm_mode_addfb2] [FB:97]
>[32m[  247.789382] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  247.789398] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  247.789404] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1299bf8 state to ffff8801f5241548
>[32m[  247.789409] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5ce758 state to ffff8801f5241548
>[32m[  247.789412] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f1299bf8
>[32m[  247.789414] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [NOCRTC]
>[32m[  247.789417] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce758
>[32m[  247.789420] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f5241548
>[32m[  247.789427] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff880211eb06c8 state to ffff8801f5241548
>[32m[  247.789431] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880211eb06c8 to [NOCRTC]
>[32m[  247.789433] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  247.789436] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  247.789438] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  247.789441] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  247.789443] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  247.789445] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  247.789448] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: n, active: n
>[32m[  247.789450] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f5241548
>[32m[  247.789481] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb -1
>[32m[  247.789504] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  247.789509] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  247.789573] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  247.813668] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 1, on? 1) for crtc 36
>[32m[  247.813696] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  247.813929] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  247.813952] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  247.813971] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  247.813991] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  247.814182] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.814220] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  247.814274] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  247.814283] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  247.814297] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  247.814348] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  247.814354] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ce9a8 state to ffff8801f1253528
>[32m[  247.814356] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce9a8 to [NOCRTC]
>[32m[  247.814358] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce9a8
>[32m[  247.814360] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  247.814364] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  247.814376] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  247.814390] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  247.814412] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  247.814417] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5cc6f8 state to ffff880211b85fa8
>[32m[  247.814419] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc6f8 to [NOCRTC]
>[32m[  247.814421] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc6f8
>[32m[  247.814423] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  247.814426] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  247.814435] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  247.814455] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  247.814470] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  247.814488] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  247.814493] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12992a8 state to ffff8801f5241548
>[32m[  247.814498] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cd4d8 state to ffff8801f5241548
>[32m[  247.814500] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f12992a8
>[32m[  247.814503] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [NOCRTC]
>[32m[  247.814505] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd4d8
>[32m[  247.814507] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f5241548
>[32m[  247.814515] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802135ab5c8 state to ffff8801f5241548
>[32m[  247.814519] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802135ab5c8 to [NOCRTC]
>[32m[  247.814521] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  247.814523] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  247.814525] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  247.814527] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  247.814530] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.814532] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  247.814534] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: n, active: n
>[32m[  247.814537] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f5241548
>[32m[  247.814561] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb -1
>[32m[  247.814582] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  247.814586] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  247.814639] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  247.835332] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 2, on? 1) for crtc 46
>[32m[  247.835360] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  247.835592] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  247.835612] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  247.835634] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  247.835654] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  247.835676] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.835700] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  247.835739] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  247.835769] [0m[drm:intel_power_well_disable [i915]] disabling always-on
>[32m[  247.835783] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  247.835796] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  247.835833] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  247.835838] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cf538 state to ffff880212118008
>[32m[  247.835841] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf538 to [NOCRTC]
>[32m[  247.835843] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf538
>[32m[  247.835845] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  247.835848] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  247.835859] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  247.835873] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  247.835894] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  247.835899] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cde18 state to ffff8801f1253528
>[32m[  247.835901] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cde18 to [NOCRTC]
>[32m[  247.835903] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cde18
>[32m[  247.835905] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  247.835908] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  247.835916] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  247.835927] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  247.835941] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  247.835961] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  247.835970] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  247.835975] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129b7e8 state to ffff880211b85fa8
>[32m[  247.835980] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5ce508 state to ffff880211b85fa8
>[32m[  247.835985] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129b7e8
>[32m[  247.836299] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [CRTC:56:pipe C]
>[32m[  247.836301] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:97] for plane state ffff8801fb5ce508
>[32m[  247.836305] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  247.836315] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff880211eb0a28 state to ffff880211b85fa8
>[32m[  247.836318] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880211eb0a28 to [CRTC:56:pipe C]
>[32m[  247.836322] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  247.836325] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  247.836328] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] enable changed
>[32m[  247.836330] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] active changed
>[32m[  247.836334] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  247.836337] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:56:pipe C]
>[32m[  247.836339] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  247.836342] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  247.836347] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  247.836373] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  247.836396] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  247.836419] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  247.836426] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ca88 state to ffff880211b85fa8
>[32m[  247.836447] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  247.836469] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  247.836491] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  247.836512] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  247.836533] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  247.836552] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  247.836556] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  247.836576] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  247.836579] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  247.836599] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  247.836619] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  247.836640] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  247.836659] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  247.836682] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  247.836701] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  247.836722] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] disabled, scaler_id = 0
>[32m[  247.836741] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] disabled, scaler_id = 0
>[32m[  247.836761] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] disabled, scaler_id = 0
>[32m[  247.836786] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 97
>[32m[  247.836807] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  247.836850] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  247.836871] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  247.836876] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  247.839417] [0m[drm:intel_power_well_enable [i915]] enabling always-on
>[32m[  247.839456] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  247.839476] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  247.839495] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  247.839515] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.839539] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  247.839571] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  247.840250] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  247.840434] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  247.840463] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  247.840483] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  247.840508] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  247.840528] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  247.840545] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  247.840568] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  247.840588] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  247.875323] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  247.875349] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  247.875387] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  247.875398] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  247.875415] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  247.875458] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  247.875463] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cc948 state to ffff8801f5241548
>[32m[  247.875466] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc948 to [NOCRTC]
>[32m[  247.875468] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc948
>[32m[  247.875470] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  247.875473] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  247.875484] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  247.875497] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  247.875518] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  247.875523] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cdbc8 state to ffff8801f5241548
>[32m[  247.875525] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [NOCRTC]
>[32m[  247.875527] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cdbc8
>[32m[  247.875529] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  247.875532] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  247.875540] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  247.875550] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  247.925426] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  247.925735] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  247.925877] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  247.932437] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  247.932452] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  247.932462] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  247.932468] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff8801f5241548
>[32m[  247.932473] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cd728 state to ffff8801f5241548
>[32m[  247.932478] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1268008
>[32m[  247.932481] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [CRTC:56:pipe C]
>[32m[  247.932483] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8801fb5cd728
>[32m[  247.932486] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5241548
>[32m[  247.932494] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd5ca878 state to ffff8801f5241548
>[32m[  247.932497] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5ca878 to [NOCRTC]
>[32m[  247.932500] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5ca878 to [CRTC:56:pipe C]
>[32m[  247.932504] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  247.932508] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  247.932511] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  247.932542] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 100
>[32m[  247.932564] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.932570] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  247.941805] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  247.941824] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  247.941861] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  247.941867] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff880212945978 state to ffff880212118008
>[32m[  247.941872] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126b7e8 state to ffff880212118008
>[32m[  247.941874] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212945978 to [CRTC:56:pipe C]
>[32m[  247.941876] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff880212945978
>[32m[  247.941878] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  247.941906] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 66
>[32m[  247.941929] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  247.941933] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  247.958430] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  247.958441] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  247.958476] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  247.958481] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212c4a8 state to ffff880211b85fa8
>[32m[  247.958486] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff880211b85fa8
>[32m[  247.958488] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c4a8 to [CRTC:56:pipe C]
>[32m[  247.958490] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff88021212c4a8
>[32m[  247.958493] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  247.958519] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 82
>[32m[  247.958542] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  247.958546] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  247.975051] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  247.975064] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  247.975091] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff88021212c6f8
>[32m[  247.975117] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 82
>[32m[  247.975140] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  247.992111] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5241548
>[32m[  247.992120] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211c5fd08 state to ffff8801f5241548
>[32m[  247.992123] [0m[drm:drm_atomic_check_only] checking ffff8801f5241548
>[32m[  247.992126] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.992128] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  247.992131] [0m[drm:drm_atomic_commit] committing ffff8801f5241548
>[32m[  247.992143] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5241548
>[32m[  247.992156] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5241548
>[32m[  247.992203] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  247.997944] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  247.997966] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  247.997975] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  247.997981] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff8801f5245508
>[32m[  247.997985] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212de18 state to ffff8801f5245508
>[32m[  247.998025] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1269bf8
>[32m[  247.998028] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [CRTC:56:pipe C]
>[32m[  247.998031] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff88021212de18
>[32m[  247.998035] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5245508
>[32m[  247.998044] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd5ca008 state to ffff8801f5245508
>[32m[  247.998048] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5ca008 to [NOCRTC]
>[32m[  247.998054] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211c5e1d8 state to ffff8801f5245508
>[32m[  247.998057] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880211c5e1d8 to [CRTC:56:pipe C]
>[32m[  247.998061] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  247.998065] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  247.998068] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  247.998071] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  247.998073] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  247.998076] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:56:pipe C]
>[32m[  247.998079] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  247.998083] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5245508
>[32m[  247.998090] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802135a0de8 state to ffff8801f5245508
>[32m[  247.998095] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802135a3098 state to ffff8801f5245508
>[32m[  247.998099] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5245508
>[32m[  247.998129] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  247.998155] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  247.998181] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  247.998203] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  247.998225] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  247.998232] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126d3d8 state to ffff8801f5245508
>[32m[  247.998254] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  247.998276] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  247.998298] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  247.998319] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  247.998342] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  247.998362] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  247.998366] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  247.998386] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  247.998389] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  247.998410] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  247.998430] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  247.998451] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  247.998471] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  247.998494] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  247.998514] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  247.998535] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  247.998555] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  247.998575] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:82, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  247.998601] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 102
>[32m[  247.998622] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  247.998645] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 66
>[32m[  247.998666] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  247.998687] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 82
>[32m[  247.998708] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  247.998750] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  247.998771] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  247.998776] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  248.001059] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  248.025765] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  248.025793] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  248.026052] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  248.026081] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  248.026102] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  248.026125] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  248.026149] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  248.026174] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  248.026206] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  248.026855] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  248.027041] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  248.027073] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  248.027095] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  248.027121] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  248.027141] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  248.027160] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  248.027186] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  248.027207] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  248.062055] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.062087] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  248.062127] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  248.062139] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  248.062165] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  248.062208] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.062213] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128eabf8 state to ffff8801f1253528
>[32m[  248.062219] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff88020ffbc138 state to ffff8801f1253528
>[32m[  248.062221] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [NOCRTC]
>[32m[  248.062223] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eabf8
>[32m[  248.062225] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.062248] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  248.062268] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  248.062272] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.078666] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.078678] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.078706] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  248.078712] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802128eb098 state to ffff880211b85fa8
>[32m[  248.078717] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f95e2548 state to ffff880211b85fa8
>[32m[  248.078719] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb098 to [NOCRTC]
>[32m[  248.078721] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb098
>[32m[  248.078723] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  248.078749] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  248.078771] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  248.078776] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  248.095326] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  248.095339] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  248.145499] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.145508] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f978d058 state to ffff8801f1253528
>[32m[  248.145513] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f121dd28 state to ffff8801f1253528
>[32m[  248.145516] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.145521] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.145524] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  248.145528] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.162004] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.162015] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.162076] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  248.162384] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  248.162554] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  248.168439] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  248.168460] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.168469] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.168475] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f121b7e8 state to ffff8801f1253528
>[32m[  248.168481] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cee48 state to ffff8801f1253528
>[32m[  248.168487] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121b7e8
>[32m[  248.168489] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cee48 to [CRTC:56:pipe C]
>[32m[  248.168491] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8802111cee48
>[32m[  248.168494] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  248.168503] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff8801f1253528
>[32m[  248.168506] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [NOCRTC]
>[32m[  248.168509] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0483a8 to [CRTC:56:pipe C]
>[32m[  248.168513] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.168518] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.168521] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  248.168552] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 108
>[32m[  248.168575] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  248.168580] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.178676] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.178694] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.178736] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  248.178741] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cf9d8 state to ffff880212118008
>[32m[  248.178747] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f9696678 state to ffff880212118008
>[32m[  248.178749] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cf9d8 to [CRTC:56:pipe C]
>[32m[  248.178751] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff8802111cf9d8
>[32m[  248.178753] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  248.178781] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 82
>[32m[  248.178803] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  248.178808] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  248.195339] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.195349] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  248.195383] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.195389] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cdbc8 state to ffff8801f1253528
>[32m[  248.195394] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129ae98 state to ffff8801f1253528
>[32m[  248.195396] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cdbc8 to [CRTC:56:pipe C]
>[32m[  248.195398] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802111cdbc8
>[32m[  248.195401] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.195427] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 109
>[32m[  248.195449] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  248.195454] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.212009] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.212021] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.212046] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802111cc948
>[32m[  248.212073] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 109
>[32m[  248.212096] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  248.228863] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  248.228872] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff880211b85fa8
>[32m[  248.228877] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129ca88 state to ffff880211b85fa8
>[32m[  248.228880] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  248.228885] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.228888] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  248.228892] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  248.245322] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  248.245334] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  248.245592] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  248.251980] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  248.252026] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  248.252036] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.252044] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129ae98 state to ffff8801f1253528
>[32m[  248.252049] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111cd288 state to ffff8801f1253528
>[32m[  248.252055] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129ae98
>[32m[  248.252057] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [CRTC:56:pipe C]
>[32m[  248.252060] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8802111cd288
>[32m[  248.252063] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  248.252072] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0493f8 state to ffff8801f1253528
>[32m[  248.252075] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e0493f8 to [NOCRTC]
>[32m[  248.252080] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd5ca878 state to ffff8801f1253528
>[32m[  248.252083] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5ca878 to [CRTC:56:pipe C]
>[32m[  248.252088] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.252091] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  248.252095] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  248.252099] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:56:pipe C]
>[32m[  248.252102] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.252104] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  248.252106] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  248.252110] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  248.252117] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111ccde8 state to ffff8801f1253528
>[32m[  248.252122] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cc4a8 state to ffff8801f1253528
>[32m[  248.252125] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  248.252157] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  248.252180] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  248.252204] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  248.252210] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129a548 state to ffff8801f1253528
>[32m[  248.252232] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  248.252254] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  248.252276] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  248.252317] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  248.252337] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  248.252359] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  248.252362] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  248.252382] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  248.252385] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  248.252405] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  248.252425] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  248.252446] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  248.252482] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  248.252504] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  248.252525] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  248.252545] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  248.252565] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:82, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  248.252585] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:109, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  248.252611] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 110
>[32m[  248.252647] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  248.252669] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 82
>[32m[  248.252690] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  248.252712] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 109
>[32m[  248.252732] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  248.252774] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  248.252809] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  248.252814] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.255601] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  248.279397] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  248.279425] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  248.279658] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  248.279678] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  248.279700] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  248.279720] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.279742] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  248.279765] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  248.279795] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  248.280467] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  248.280652] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  248.280681] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  248.280701] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  248.280726] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  248.280746] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  248.280763] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  248.280791] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  248.280811] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  248.315562] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  248.315593] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  248.315632] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  248.315645] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.315668] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.315704] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  248.315709] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ffdf2e8 state to ffff880212118008
>[32m[  248.315714] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126d3d8 state to ffff880212118008
>[32m[  248.315717] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdf2e8 to [NOCRTC]
>[32m[  248.315719] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdf2e8
>[32m[  248.315721] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  248.315744] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  248.315765] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  248.315769] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  248.332165] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.332176] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  248.332206] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.332211] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ffdee48 state to ffff8801f1253528
>[32m[  248.332216] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff8801f1253528
>[32m[  248.332219] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ffdee48 to [NOCRTC]
>[32m[  248.332221] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ffdee48
>[32m[  248.332223] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.332249] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  248.332271] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  248.332276] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.348785] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.348798] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.398858] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  248.399229] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  248.399386] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  248.405933] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  248.405955] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  248.405964] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  248.405970] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff880211b85fa8
>[32m[  248.405975] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f95332e8 state to ffff880211b85fa8
>[32m[  248.405981] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1268008
>[32m[  248.405983] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95332e8 to [CRTC:56:pipe C]
>[32m[  248.405985] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff8801f95332e8
>[32m[  248.406022] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  248.406031] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd5cb0e8 state to ffff880211b85fa8
>[32m[  248.406036] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5cb0e8 to [NOCRTC]
>[32m[  248.406040] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5cb0e8 to [CRTC:56:pipe C]
>[32m[  248.406045] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  248.406051] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  248.406055] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  248.406089] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 112
>[32m[  248.406113] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  248.406119] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  248.415298] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  248.415316] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  248.415359] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.415365] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f95306f8 state to ffff8801f1253528
>[32m[  248.415370] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff880211ec8958 state to ffff8801f1253528
>[32m[  248.415373] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [CRTC:56:pipe C]
>[32m[  248.415375] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801f95306f8
>[32m[  248.415377] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.415405] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 109
>[32m[  248.415427] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  248.415432] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.431925] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.431936] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.431970] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  248.431975] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9532bf8 state to ffff880211b85fa8
>[32m[  248.431980] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff88020f82dd28 state to ffff880211b85fa8
>[32m[  248.431983] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [CRTC:56:pipe C]
>[32m[  248.431985] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8801f9532bf8
>[32m[  248.432026] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  248.432055] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 113
>[32m[  248.432082] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  248.432089] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  248.448543] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  248.448557] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  248.448582] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8801f9530258
>[32m[  248.448608] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 113
>[32m[  248.448630] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  248.465586] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  248.465595] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048e88 state to ffff880212118008
>[32m[  248.465598] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  248.465601] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.465603] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  248.465606] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  248.465618] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.465632] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  248.465680] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  248.471446] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  248.471466] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.471475] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.471481] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1219bf8 state to ffff8801f1253528
>[32m[  248.471485] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f9531038 state to ffff8801f1253528
>[32m[  248.471491] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1219bf8
>[32m[  248.471493] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [CRTC:56:pipe C]
>[32m[  248.471496] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8801f9531038
>[32m[  248.471499] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  248.471506] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd5ca878 state to ffff8801f1253528
>[32m[  248.471510] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5ca878 to [NOCRTC]
>[32m[  248.471515] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048918 state to ffff8801f1253528
>[32m[  248.471517] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048918 to [CRTC:56:pipe C]
>[32m[  248.471521] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.471525] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  248.471528] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  248.471530] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  248.471532] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.471535] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:56:pipe C]
>[32m[  248.471538] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  248.471540] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  248.471546] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9531288 state to ffff8801f1253528
>[32m[  248.471550] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9532758 state to ffff8801f1253528
>[32m[  248.471553] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253528
>[32m[  248.471581] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  248.471603] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  248.471627] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  248.471647] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  248.471668] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  248.471674] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121e678 state to ffff8801f1253528
>[32m[  248.471695] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  248.471715] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  248.471735] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  248.471755] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  248.471774] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  248.471793] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  248.471796] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  248.471814] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  248.471817] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  248.471835] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  248.471854] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  248.471872] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  248.471890] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  248.471911] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  248.471929] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  248.471948] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:112, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  248.471967] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:109, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  248.471985] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:113, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  248.472043] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 114
>[32m[  248.472068] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  248.472091] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 109
>[32m[  248.472112] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  248.472134] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 113
>[32m[  248.472155] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  248.472198] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  248.472219] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  248.472225] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.474730] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  248.499437] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  248.499465] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  248.499698] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  248.499721] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  248.499740] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  248.499760] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  248.499781] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  248.499805] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  248.499836] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  248.500503] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  248.500695] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  248.500725] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  248.500745] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  248.500776] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  248.500795] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  248.500813] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  248.500836] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  248.500856] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  248.535680] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.535711] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  248.535752] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  248.535765] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.535789] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.535831] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  248.535837] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020e078258 state to ffff880212118008
>[32m[  248.535842] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff880212118008
>[32m[  248.535844] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078258 to [NOCRTC]
>[32m[  248.535846] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078258
>[32m[  248.535849] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  248.535872] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  248.535892] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  248.535896] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  248.552318] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.552332] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  248.552361] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.552367] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020e0794d8 state to ffff8801f1253528
>[32m[  248.552372] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126efc8 state to ffff8801f1253528
>[32m[  248.552374] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e0794d8 to [NOCRTC]
>[32m[  248.552376] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e0794d8
>[32m[  248.552378] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.552404] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  248.552426] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  248.552430] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.568979] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.569032] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.619187] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  248.619196] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e0483a8 state to ffff880211b85fa8
>[32m[  248.619201] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126c138 state to ffff880211b85fa8
>[32m[  248.619204] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  248.619209] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.619212] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  248.619217] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  248.635655] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  248.635666] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  248.635730] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  248.636139] [0m[drm:drm_mode_addfb2] [FB:115]
>[32m[  248.636315] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  248.642163] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  248.642186] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.642195] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  248.642201] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff880212118008
>[32m[  248.642206] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2cb98 state to ffff880212118008
>[32m[  248.642212] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1268008
>[32m[  248.642215] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cb98 to [CRTC:56:pipe C]
>[32m[  248.642217] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff88020ec2cb98
>[32m[  248.642220] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880212118008
>[32m[  248.642228] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e048e88 state to ffff880212118008
>[32m[  248.642231] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048e88 to [NOCRTC]
>[32m[  248.642234] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88020e048e88 to [CRTC:56:pipe C]
>[32m[  248.642238] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  248.642243] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.642246] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  248.642278] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 116
>[32m[  248.642300] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  248.642305] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  248.652328] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.652346] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  248.652391] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  248.652396] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2cde8 state to ffff880211b85fa8
>[32m[  248.652401] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126c138 state to ffff880211b85fa8
>[32m[  248.652403] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [CRTC:56:pipe C]
>[32m[  248.652406] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff88020ec2cde8
>[32m[  248.652408] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  248.652436] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 113
>[32m[  248.652458] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  248.652463] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  248.669014] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  248.669026] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  248.669068] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  248.669073] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2c008 state to ffff880212118008
>[32m[  248.669078] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff880212118008
>[32m[  248.669081] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [CRTC:56:pipe C]
>[32m[  248.669083] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff88020ec2c008
>[32m[  248.669085] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  248.669113] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 117
>[32m[  248.669135] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  248.669139] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  248.685654] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.685667] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  248.685691] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff88020ec2e758
>[32m[  248.685718] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 117
>[32m[  248.685740] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  248.702503] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253528
>[32m[  248.702511] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff88020e049058 state to ffff8801f1253528
>[32m[  248.702517] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268958 state to ffff8801f1253528
>[32m[  248.702519] [0m[drm:drm_atomic_check_only] checking ffff8801f1253528
>[32m[  248.702524] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.702527] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  248.702532] [0m[drm:drm_atomic_commit] committing ffff8801f1253528
>[32m[  248.718976] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253528
>[32m[  248.719026] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253528
>[32m[  248.719288] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  248.729367] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  248.729374] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2f098 state to ffff880212118008
>[32m[  248.729379] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2d038 state to ffff880212118008
>[32m[  248.729381] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d038 to [NOCRTC]
>[32m[  248.729383] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d038
>[32m[  248.729387] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212131288 state to ffff880212118008
>[32m[  248.729389] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [NOCRTC]
>[32m[  248.729391] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131288
>[32m[  248.729395] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff880212131978 state to ffff880212118008
>[32m[  248.729397] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.729410] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff880212131978 state to ffff880212118008
>[32m[  248.729414] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802121329a8 state to ffff880212118008
>[32m[  248.729416] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [NOCRTC]
>[32m[  248.729417] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121329a8
>[32m[  248.729421] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff880212131288 state to ffff880212118008
>[32m[  248.729423] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [NOCRTC]
>[32m[  248.729424] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131288
>[32m[  248.729426] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.729437] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff880212131288 state to ffff880212118008
>[32m[  248.729440] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802121314d8 state to ffff880212118008
>[32m[  248.729442] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [NOCRTC]
>[32m[  248.729443] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121314d8
>[32m[  248.729447] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802121329a8 state to ffff880212118008
>[32m[  248.729449] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121329a8 to [NOCRTC]
>[32m[  248.729450] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802121329a8
>[32m[  248.729454] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff880212131038 state to ffff880212118008
>[32m[  248.729458] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff880212131978 state to ffff880212118008
>[32m[  248.729460] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131978 to [NOCRTC]
>[32m[  248.729461] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212131978
>[32m[  248.729466] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ee529a8 state to ffff880212118008
>[32m[  248.729467] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee529a8 to [NOCRTC]
>[32m[  248.729469] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee529a8
>[32m[  248.729473] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ee52e48 state to ffff880212118008
>[32m[  248.729477] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff880212118008
>[32m[  248.729481] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ee51978 state to ffff880212118008
>[32m[  248.729483] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee51978 to [NOCRTC]
>[32m[  248.729484] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ee51978
>[32m[  248.729489] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cd728 state to ffff880212118008
>[32m[  248.729490] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [NOCRTC]
>[32m[  248.729492] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd728
>[32m[  248.729497] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126c138 state to ffff880212118008
>[32m[  248.729503] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126c138
>[32m[  248.729505] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212131288 to [CRTC:36:pipe A]
>[32m[  248.729507] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff880212131288
>[32m[  248.729509] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.729539] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801fb5cd728 state to ffff880212118008
>[32m[  248.729543] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801fb5ccb98 state to ffff880212118008
>[32m[  248.729545] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ccb98 to [NOCRTC]
>[32m[  248.729546] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ccb98
>[32m[  248.729550] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801fb5ce508 state to ffff880212118008
>[32m[  248.729552] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce508 to [NOCRTC]
>[32m[  248.729553] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5ce508
>[32m[  248.729557] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801fb5cf098 state to ffff880212118008
>[32m[  248.729561] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801fb5cf9d8 state to ffff880212118008
>[32m[  248.729562] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf9d8 to [NOCRTC]
>[32m[  248.729564] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cf9d8
>[32m[  248.729568] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801fb5cd978 state to ffff880212118008
>[32m[  248.729569] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd978 to [NOCRTC]
>[32m[  248.729571] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd978
>[32m[  248.729574] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cc948 state to ffff880212118008
>[32m[  248.729578] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1269bf8 state to ffff880212118008
>[32m[  248.729582] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cdbc8 state to ffff880212118008
>[32m[  248.729584] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cdbc8 to [NOCRTC]
>[32m[  248.729585] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cdbc8
>[32m[  248.729589] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff880212945978 state to ffff880212118008
>[32m[  248.729591] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880212945978 to [NOCRTC]
>[32m[  248.729592] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880212945978
>[32m[  248.729596] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f126b7e8 state to ffff880212118008
>[32m[  248.729601] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126b7e8
>[32m[  248.729603] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd728 to [CRTC:36:pipe A]
>[32m[  248.729604] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801fb5cd728
>[32m[  248.729607] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212118008
>[32m[  248.729614] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd5ca008 state to ffff880212118008
>[32m[  248.729616] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5ca008 to [CRTC:36:pipe A]
>[32m[  248.729621] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126c138 state to ffff880212118008
>[32m[  248.729626] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126c138
>[32m[  248.729627] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf098 to [CRTC:46:pipe B]
>[32m[  248.729629] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801fb5cf098
>[32m[  248.729631] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212118008
>[32m[  248.729637] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff880212118008
>[32m[  248.729638] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8cb8 to [CRTC:46:pipe B]
>[32m[  248.729640] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f1269bf8
>[32m[  248.729642] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f1269bf8
>[32m[  248.729644] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc948 to [NOCRTC]
>[32m[  248.729646] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cc948
>[32m[  248.729648] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880212118008
>[32m[  248.729650] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  248.729653] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  248.729655] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  248.729656] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  248.729658] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  248.729659] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  248.729661] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  248.729662] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  248.729664] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] enable changed
>[32m[  248.729665] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] active changed
>[32m[  248.729669] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  248.729672] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  248.729673] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.729675] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  248.729677] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  248.729679] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212118008
>[32m[  248.729682] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  248.729684] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212118008
>[32m[  248.729687] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: n, active: n
>[32m[  248.729689] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880212118008
>[32m[  248.729693] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880212118008
>[32m[  248.729721] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  248.729743] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  248.729764] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  248.729784] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  248.729805] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  248.729824] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  248.729844] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  248.729863] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  248.729881] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  248.729884] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  248.729902] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  248.729904] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  248.729922] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  248.729940] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  248.729958] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  248.729985] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  248.730034] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  248.730061] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  248.730079] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0
>[32m[  248.730097] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0
>[32m[  248.730115] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0
>[32m[  248.730118] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880212118008
>[32m[  248.730139] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  248.730159] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  248.730181] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  248.730200] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  248.730220] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  248.730239] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  248.730258] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  248.730276] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  248.730295] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  248.730312] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  248.730330] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  248.730332] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  248.730350] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  248.730352] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  248.730370] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  248.730387] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  248.730405] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  248.730435] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  248.730455] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  248.730472] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  248.730489] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0
>[32m[  248.730506] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  248.730523] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  248.730546] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  248.730565] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  248.730584] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  248.730603] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  248.730621] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb -1
>[32m[  248.730640] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  248.730658] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  248.730676] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  248.730694] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  248.730712] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  248.730749] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  248.730768] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  248.730805] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  248.730823] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  248.730827] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  248.730912] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  248.754237] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  248.754264] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  248.754496] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  248.754516] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  248.754535] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  248.754555] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  248.754578] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  248.754615] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  248.755246] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  248.755428] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  248.755457] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  248.755477] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  248.755502] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  248.755521] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  248.755538] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  248.755560] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  248.755579] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  248.773699] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  248.774365] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  248.774550] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  248.774580] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  248.774600] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  248.774626] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  248.774645] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  248.774663] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  248.774686] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  248.774705] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  248.809524] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  248.809550] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  248.809589] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  248.809619] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.809641] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  248.809677] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  248.809708] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  248.809721] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  248.809767] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  248.813788] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  248.819272] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1253a78
>[32m[  248.819279] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212fc28 state to ffff8801f1253a78
>[32m[  248.819286] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1268958 state to ffff8801f1253a78
>[32m[  248.819291] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212d978 state to ffff8801f1253a78
>[32m[  248.819294] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212d978 to [NOCRTC]
>[32m[  248.819296] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212d978
>[32m[  248.819302] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212c6f8 state to ffff8801f1253a78
>[32m[  248.819304] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  248.819306] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  248.819311] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212de18 state to ffff8801f1253a78
>[32m[  248.819314] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  248.819340] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212de18 state to ffff8801f1253a78
>[32m[  248.819345] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1268958 state to ffff8801f1253a78
>[32m[  248.819350] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212ebf8 state to ffff8801f1253a78
>[32m[  248.819352] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [NOCRTC]
>[32m[  248.819354] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212ebf8
>[32m[  248.819357] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  248.819368] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88021212ebf8 state to ffff8801f1253a78
>[32m[  248.819373] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1268958 state to ffff8801f1253a78
>[32m[  248.819378] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88021212c008 state to ffff8801f1253a78
>[32m[  248.819380] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [NOCRTC]
>[32m[  248.819382] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c008
>[32m[  248.819386] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88021212de18 state to ffff8801f1253a78
>[32m[  248.819389] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212de18 to [NOCRTC]
>[32m[  248.819391] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212de18
>[32m[  248.819396] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88021212c4a8 state to ffff8801f1253a78
>[32m[  248.819401] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1268008 state to ffff8801f1253a78
>[32m[  248.819406] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88021212c6f8 state to ffff8801f1253a78
>[32m[  248.819408] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [NOCRTC]
>[32m[  248.819410] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c6f8
>[32m[  248.819414] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88021212fc28 state to ffff8801f1253a78
>[32m[  248.819417] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212fc28 to [NOCRTC]
>[32m[  248.819419] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212fc28
>[32m[  248.819423] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212d978 state to ffff8801f1253a78
>[32m[  248.819428] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802135a3098 state to ffff8801f1253a78
>[32m[  248.819430] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [NOCRTC]
>[32m[  248.819432] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a3098
>[32m[  248.819437] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802135a0de8 state to ffff8801f1253a78
>[32m[  248.819439] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a0de8 to [NOCRTC]
>[32m[  248.819441] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802135a0de8
>[32m[  248.819449] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1268958
>[32m[  248.819451] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212ebf8 to [CRTC:36:pipe A]
>[32m[  248.819453] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff88021212ebf8
>[32m[  248.819457] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  248.819487] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8802128e86f8 state to ffff8801f1253a78
>[32m[  248.819492] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f1268008 state to ffff8801f1253a78
>[32m[  248.819497] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8802128ea2b8 state to ffff8801f1253a78
>[32m[  248.819499] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128ea2b8 to [NOCRTC]
>[32m[  248.819501] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128ea2b8
>[32m[  248.819506] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8802128eb538 state to ffff8801f1253a78
>[32m[  248.819508] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [NOCRTC]
>[32m[  248.819511] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb538
>[32m[  248.819515] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8802128eabf8 state to ffff8801f1253a78
>[32m[  248.819520] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126efc8 state to ffff8801f1253a78
>[32m[  248.819525] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8802128e8258 state to ffff8801f1253a78
>[32m[  248.819527] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e8258 to [NOCRTC]
>[32m[  248.819529] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e8258
>[32m[  248.819533] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8802128eb098 state to ffff8801f1253a78
>[32m[  248.819536] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb098 to [NOCRTC]
>[32m[  248.819538] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128eb098
>[32m[  248.819542] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128e9978 state to ffff8801f1253a78
>[32m[  248.819547] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec51728 state to ffff8801f1253a78
>[32m[  248.819550] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec51728 to [NOCRTC]
>[32m[  248.819552] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec51728
>[32m[  248.819557] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cd4d8 state to ffff8801f1253a78
>[32m[  248.819559] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd4d8 to [NOCRTC]
>[32m[  248.819561] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cd4d8
>[32m[  248.819567] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1268008
>[32m[  248.819569] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e86f8 to [CRTC:36:pipe A]
>[32m[  248.819571] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802128e86f8
>[32m[  248.819574] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f1253a78
>[32m[  248.819582] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801fd5cb7a8 state to ffff8801f1253a78
>[32m[  248.819586] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5cb7a8 to [NOCRTC]
>[32m[  248.819589] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801fd5cb7a8 to [CRTC:36:pipe A]
>[32m[  248.819595] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126efc8
>[32m[  248.819597] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eabf8 to [CRTC:46:pipe B]
>[32m[  248.819599] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8802128eabf8
>[32m[  248.819602] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f1253a78
>[32m[  248.819608] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880211d1d798 state to ffff8801f1253a78
>[32m[  248.819611] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880211d1d798 to [NOCRTC]
>[32m[  248.819614] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880211d1d798 to [CRTC:46:pipe B]
>[32m[  248.819619] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268958 state to ffff8801f1253a78
>[32m[  248.819621] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f1268958
>[32m[  248.819624] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [NOCRTC]
>[32m[  248.819626] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802128e9978
>[32m[  248.819629] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1253a78
>[32m[  248.819632] [0m[drm:drm_atomic_check_only] checking ffff8801f1253a78
>[32m[  248.819639] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  248.819642] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:36:pipe A]
>[32m[  248.819644] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.819647] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  248.819676] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  248.819699] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  248.819722] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  248.819743] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  248.819750] [0m[drm:drm_atomic_commit] committing ffff8801f1253a78
>[32m[  248.826127] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1253a78
>[32m[  248.826178] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1253a78
>[32m[  248.863461] [0m[33mConsole[0m: switching to colour dummy device 80x25
>[32m[  248.863561] [0m[33m[IGT] kms_plane_multiple[0m: executing
>[32m[  248.881137] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1]
>[32m[  248.881171] [0m[drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1
>[32m[  248.881198] [0m[drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1
>[32m[  248.881219] [0m[drm:intel_crt_detect [i915]] CRT detected via hotplug
>[32m[  248.919368] [0m[33m[drm:drm_edid_to_eld] ELD[0m: no CEA Extension found
>[32m[  248.919438] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes :
>[32m[  248.919442] [0m[drm:drm_mode_debug_printmodeline] Modeline 68:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  248.919444] [0m[drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[32m[  248.919446] [0m[drm:drm_mode_debug_printmodeline] Modeline 75:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[32m[  248.919448] [0m[drm:drm_mode_debug_printmodeline] Modeline 69:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[32m[  248.919450] [0m[drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  248.919452] [0m[drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  248.919455] [0m[drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[32m[  248.919457] [0m[drm:drm_mode_debug_printmodeline] Modeline 71:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[32m[  248.919459] [0m[drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  248.919461] [0m[drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  248.919463] [0m[drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  248.919465] [0m[drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  248.919566] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.919596] [0m[drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  248.994476] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  248.994499] [0m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[32m[  248.996546] [0m[33m[drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr[0m: 0040 w(1)
>[32m[  248.996552] [0m[33m[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID[0m:  (err -6)
>[32m[  248.996556] [0m[drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>[32m[  248.996572] [0m[33m[drm:drm_add_edid_modes] HDMI[0m: DVI dual 0, max TMDS clock 170000 kHz
>[32m[  248.996690] [0m[drm:drm_edid_to_eld] ELD monitor HP E232
>[32m[  248.996692] [0m[33m[drm:drm_edid_to_eld] HDMI[0m: latency present 0 0, video latency 0 0, audio latency 0 0
>[32m[  248.996694] [0m[drm:drm_edid_to_eld] ELD size 28, SAD count 0
>[32m[  248.996825] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] probed modes :
>[32m[  248.996829] [0m[drm:drm_mode_debug_printmodeline] Modeline 81:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  248.996831] [0m[drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[32m[  248.996833] [0m[drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[32m[  248.996835] [0m[drm:drm_mode_debug_printmodeline] Modeline 88:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[32m[  248.996837] [0m[drm:drm_mode_debug_printmodeline] Modeline 87:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[32m[  248.996839] [0m[drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[32m[  248.996841] [0m[drm:drm_mode_debug_printmodeline] Modeline 89:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[32m[  248.996843] [0m[drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[32m[  248.996845] [0m[drm:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  248.996847] [0m[drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[32m[  248.996850] [0m[drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[32m[  248.996852] [0m[drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[32m[  248.996854] [0m[drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[32m[  248.996856] [0m[drm:drm_mode_debug_printmodeline] Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[32m[  248.996858] [0m[drm:drm_mode_debug_printmodeline] Modeline 106:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  248.996860] [0m[drm:drm_mode_debug_printmodeline] Modeline 86:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[32m[  248.996862] [0m[drm:drm_mode_debug_printmodeline] Modeline 107:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  248.996864] [0m[drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[32m[  248.997498] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  248.997506] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8801f978ccb8 state to ffff880211b85fa8
>[32m[  248.997512] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f126dd28 state to ffff880211b85fa8
>[32m[  248.997515] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  248.997521] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  248.997524] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  248.997531] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.009492] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.009504] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.009532] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1]
>[32m[  249.009558] [0m[drm:intel_dp_detect [i915]] [CONNECTOR:65:DP-1]
>[32m[  249.012131] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.014682] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.017232] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.019781] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.022328] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.024874] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.027422] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.029969] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.032525] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.035100] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.037631] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.040158] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.042682] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.045207] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.047732] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.050256] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.052778] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.055302] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.057824] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.060348] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.062871] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.065394] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.067918] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.070441] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.072965] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.075489] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.078084] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.080606] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.083131] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.085654] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.088176] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.090698] [0m[drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7145003f
>[32m[  249.090706] [0m[33m[drm:drm_dp_dpcd_access] Too many retries, giving up. First error[0m: -110
>[32m[  249.090710] [0m[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:65:DP-1] disconnected
>[32m[  249.090864] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.090872] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:65:DP-1] ffff8802128b83a8 state to ffff880211b85fa8
>[32m[  249.090874] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.090878] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:65:DP-1]
>[32m[  249.090880] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:65:DP-1]
>[32m[  249.090883] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.090896] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.090910] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.091032] [0m[33m[IGT] kms_plane_multiple[0m: starting subtest legacy-pipe-C-tiling-x
>[32m[  249.091367] [0m[drm:drm_mode_addfb2] [FB:95]
>[32m[  249.098004] [0m[drm:drm_mode_setcrtc] [CRTC:36:pipe A]
>[32m[  249.098024] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.098030] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f12992a8 state to ffff880211b85fa8
>[32m[  249.098036] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020ec2cde8 state to ffff880211b85fa8
>[32m[  249.098039] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f12992a8
>[32m[  249.098041] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2cde8 to [NOCRTC]
>[32m[  249.098044] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2cde8
>[32m[  249.098046] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880211b85fa8
>[32m[  249.098056] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9467298 state to ffff880211b85fa8
>[32m[  249.098059] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467298 to [NOCRTC]
>[32m[  249.098062] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.098065] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  249.098067] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  249.098069] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  249.098072] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  249.098074] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  249.098076] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: n, active: n
>[32m[  249.098078] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880211b85fa8
>[32m[  249.098114] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb -1
>[32m[  249.098136] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  249.098141] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.098210] [0m[drm:intel_disable_pipe [i915]] disabling pipe A
>[32m[  249.124722] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 36
>[32m[  249.124750] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  249.124982] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  249.125055] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  249.125078] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  249.125100] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  249.125124] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.125150] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  249.125194] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  249.125204] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.125217] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.125347] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.125353] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020ec2f098 state to ffff8801f5245508
>[32m[  249.125357] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f098 to [NOCRTC]
>[32m[  249.125359] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f098
>[32m[  249.125361] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.125366] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.125379] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.125392] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.125429] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  249.125434] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020ec2f538 state to ffff880212118008
>[32m[  249.125436] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2f538 to [NOCRTC]
>[32m[  249.125438] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2f538
>[32m[  249.125440] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  249.125443] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  249.125452] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  249.125462] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  249.125476] [0m[drm:drm_mode_setcrtc] [CRTC:46:pipe B]
>[32m[  249.125494] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.125500] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ae98 state to ffff880211b85fa8
>[32m[  249.125505] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020ec2e9a8 state to ffff880211b85fa8
>[32m[  249.125507] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f129ae98
>[32m[  249.125510] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e9a8 to [NOCRTC]
>[32m[  249.125512] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e9a8
>[32m[  249.125515] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880211b85fa8
>[32m[  249.125535] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b95c8 state to ffff880211b85fa8
>[32m[  249.125538] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b95c8 to [NOCRTC]
>[32m[  249.125540] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.125543] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  249.125545] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  249.125547] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  249.125549] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.125551] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  249.125553] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: n, active: n
>[32m[  249.125556] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff880211b85fa8
>[32m[  249.125580] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb -1
>[32m[  249.125600] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  249.125604] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.125657] [0m[drm:intel_disable_pipe [i915]] disabling pipe B
>[32m[  249.144338] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 46
>[32m[  249.144366] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
>[32m[  249.144597] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  249.144617] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  249.144639] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  249.144659] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  249.144681] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.144704] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  249.144743] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  249.144763] [0m[drm:intel_power_well_disable [i915]] disabling always-on
>[32m[  249.144769] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.144782] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.144818] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  249.144823] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020ec2c008 state to ffff880212118008
>[32m[  249.144825] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c008 to [NOCRTC]
>[32m[  249.144828] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2c008
>[32m[  249.144830] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  249.144833] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  249.144844] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  249.144857] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  249.144878] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.144883] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020ec2d288 state to ffff8801f5245508
>[32m[  249.144885] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2d288 to [NOCRTC]
>[32m[  249.144887] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2d288
>[32m[  249.144889] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.144891] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.144900] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.144910] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.144924] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  249.144944] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  249.144952] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.144957] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1298008 state to ffff880211b85fa8
>[32m[  249.144962] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020ec2c4a8 state to ffff880211b85fa8
>[32m[  249.144967] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f1298008
>[32m[  249.144969] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2c4a8 to [CRTC:56:pipe C]
>[32m[  249.144972] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:95] for plane state ffff88020ec2c4a8
>[32m[  249.144974] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  249.144982] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f94661b8 state to ffff880211b85fa8
>[32m[  249.144984] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f94661b8 to [CRTC:56:pipe C]
>[32m[  249.145035] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.145039] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  249.145042] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] enable changed
>[32m[  249.145044] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] active changed
>[32m[  249.145048] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  249.145052] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:56:pipe C]
>[32m[  249.145054] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  249.145057] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  249.145062] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  249.145087] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  249.145108] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  249.145131] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  249.145138] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f1298958 state to ffff880211b85fa8
>[32m[  249.145159] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  249.145180] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  249.145202] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  249.145223] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  249.145244] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  249.145263] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  249.145267] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  249.145287] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  249.145290] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  249.145310] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  249.145329] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  249.145349] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  249.145368] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  249.145391] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  249.145410] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  249.145430] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] disabled, scaler_id = 0
>[32m[  249.145450] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] disabled, scaler_id = 0
>[32m[  249.145469] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] disabled, scaler_id = 0
>[32m[  249.145494] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 95
>[32m[  249.145515] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  249.145558] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  249.145579] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  249.145584] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.148260] [0m[drm:intel_power_well_enable [i915]] enabling always-on
>[32m[  249.148285] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  249.148304] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  249.148323] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  249.148343] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.148367] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  249.148397] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  249.149061] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  249.149260] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  249.149303] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  249.149324] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  249.149351] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  249.149383] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  249.149401] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  249.149424] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  249.149444] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  249.184201] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  249.184228] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  249.184267] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.184278] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.184296] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.184340] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.184345] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec2e758 state to ffff8801f5245508
>[32m[  249.184348] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e758 to [NOCRTC]
>[32m[  249.184350] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e758
>[32m[  249.184352] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.184355] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.184366] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.184380] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.184400] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  249.184405] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2e508 state to ffff880212118008
>[32m[  249.184407] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e508 to [NOCRTC]
>[32m[  249.184409] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e508
>[32m[  249.184411] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  249.184414] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  249.184422] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  249.184432] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  249.234505] [0m[drm:drm_mode_addfb2] [FB:66]
>[32m[  249.234650] [0m[drm:drm_mode_addfb2] [FB:99]
>[32m[  249.239247] [0m[drm:drm_mode_addfb2] [FB:100]
>[32m[  249.241280] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  249.241303] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  249.241312] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.241318] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f95e12a8 state to ffff8801f5245508
>[32m[  249.241323] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802121314d8 state to ffff8801f5245508
>[32m[  249.241328] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f95e12a8
>[32m[  249.241330] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802121314d8 to [CRTC:56:pipe C]
>[32m[  249.241333] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff8802121314d8
>[32m[  249.241336] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5245508
>[32m[  249.241343] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9467298 state to ffff8801f5245508
>[32m[  249.241347] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467298 to [NOCRTC]
>[32m[  249.241349] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467298 to [CRTC:56:pipe C]
>[32m[  249.241353] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.241358] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  249.241360] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  249.241392] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 100
>[32m[  249.241414] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  249.241420] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.250669] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.250697] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.250734] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.250740] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ee51978 state to ffff880211b85fa8
>[32m[  249.250745] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff880210694a88 state to ffff880211b85fa8
>[32m[  249.250747] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ee51978 to [CRTC:56:pipe C]
>[32m[  249.250750] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:66] for plane state ffff88020ee51978
>[32m[  249.250752] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.250780] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 66
>[32m[  249.250802] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  249.250807] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.267294] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.267315] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.267351] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.267357] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5ce758 state to ffff8801f5245508
>[32m[  249.267362] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8802144bc138 state to ffff8801f5245508
>[32m[  249.267365] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce758 to [CRTC:56:pipe C]
>[32m[  249.267367] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff8801fb5ce758
>[32m[  249.267369] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.267396] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 82
>[32m[  249.267419] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  249.267423] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.283929] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.283943] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.283971] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff8801fb5ce9a8
>[32m[  249.283997] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 82
>[32m[  249.284062] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  249.300929] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880212118008
>[32m[  249.300937] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8ae8 state to ffff880212118008
>[32m[  249.300940] [0m[drm:drm_atomic_check_only] checking ffff880212118008
>[32m[  249.300943] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.300945] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  249.300948] [0m[drm:drm_atomic_commit] committing ffff880212118008
>[32m[  249.300960] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880212118008
>[32m[  249.300974] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880212118008
>[32m[  249.301084] [0m[drm:drm_mode_addfb2] [FB:102]
>[32m[  249.307007] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  249.307030] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  249.307038] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.307045] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f121ae98 state to ffff8801f5245508
>[32m[  249.307050] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5cf538 state to ffff8801f5245508
>[32m[  249.307055] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f121ae98
>[32m[  249.307058] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cf538 to [CRTC:56:pipe C]
>[32m[  249.307060] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:102] for plane state ffff8801fb5cf538
>[32m[  249.307063] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5245508
>[32m[  249.307070] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f94677a8 state to ffff8801f5245508
>[32m[  249.307074] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f94677a8 to [NOCRTC]
>[32m[  249.307078] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff8801f5245508
>[32m[  249.307081] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b93f8 to [CRTC:56:pipe C]
>[32m[  249.307084] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.307088] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  249.307091] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  249.307093] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  249.307095] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.307098] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:56:pipe C]
>[32m[  249.307100] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  249.307103] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5245508
>[32m[  249.307109] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cd978 state to ffff8801f5245508
>[32m[  249.307113] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cde18 state to ffff8801f5245508
>[32m[  249.307116] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5245508
>[32m[  249.307145] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  249.307167] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  249.307191] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  249.307211] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  249.307231] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  249.307237] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f121c138 state to ffff8801f5245508
>[32m[  249.307257] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  249.307278] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  249.307298] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  249.307318] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  249.307337] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  249.307355] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  249.307358] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  249.307377] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  249.307379] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  249.307398] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  249.307416] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  249.307435] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  249.307453] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  249.307473] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  249.307491] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  249.307510] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  249.307529] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:66, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  249.307547] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:82, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  249.307571] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 102
>[32m[  249.307591] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.307611] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 66
>[32m[  249.307630] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.307649] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 82
>[32m[  249.307667] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.307706] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  249.307726] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  249.307730] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.310860] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  249.335579] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  249.335606] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  249.335839] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  249.335862] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  249.335881] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  249.335901] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  249.335922] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.335946] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  249.335976] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  249.336663] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  249.336845] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  249.336875] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  249.336895] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  249.336920] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  249.336940] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  249.336958] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  249.336981] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  249.337009] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  249.371875] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  249.371907] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  249.371947] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.371960] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.371984] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.372072] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.372078] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cd4d8 state to ffff8801f5245508
>[32m[  249.372084] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f12692a8 state to ffff8801f5245508
>[32m[  249.372087] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd4d8 to [NOCRTC]
>[32m[  249.372089] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd4d8
>[32m[  249.372091] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.372116] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  249.372138] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  249.372143] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.388514] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.388528] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.388556] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.388562] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cd978 state to ffff880211b85fa8
>[32m[  249.388567] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126d3d8 state to ffff880211b85fa8
>[32m[  249.388569] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cd978 to [NOCRTC]
>[32m[  249.388571] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801fb5cd978
>[32m[  249.388574] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.388600] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  249.388622] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  249.388626] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.405179] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.405192] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.455358] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.455367] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff880211b85fa8
>[32m[  249.455372] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126e678 state to ffff880211b85fa8
>[32m[  249.455375] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.455380] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.455383] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  249.455387] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.471834] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.471846] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.472150] [0m[drm:drm_mode_addfb2] [FB:82]
>[32m[  249.472354] [0m[drm:drm_mode_addfb2] [FB:104]
>[32m[  249.476405] [0m[drm:drm_mode_addfb2] [FB:108]
>[32m[  249.478192] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  249.478213] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  249.478222] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.478228] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126d3d8 state to ffff8801f5245508
>[32m[  249.478232] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5ccb98 state to ffff8801f5245508
>[32m[  249.478238] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f126d3d8
>[32m[  249.478240] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ccb98 to [CRTC:56:pipe C]
>[32m[  249.478242] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:108] for plane state ffff8801fb5ccb98
>[32m[  249.478245] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f5245508
>[32m[  249.478253] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8ae8 state to ffff8801f5245508
>[32m[  249.478256] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8ae8 to [NOCRTC]
>[32m[  249.478259] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8ae8 to [CRTC:56:pipe C]
>[32m[  249.478263] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.478267] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.478270] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  249.478302] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 108
>[32m[  249.478325] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  249.478330] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.488506] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.488522] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.488564] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.488569] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801fb5cfc28 state to ffff880211b85fa8
>[32m[  249.488574] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126e678 state to ffff880211b85fa8
>[32m[  249.488576] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cfc28 to [CRTC:56:pipe C]
>[32m[  249.488578] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:82] for plane state ffff8801fb5cfc28
>[32m[  249.488580] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.488608] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 82
>[32m[  249.488631] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  249.488635] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.505170] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.505182] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.505215] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.505220] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801fb5cc258 state to ffff8801f5245508
>[32m[  249.505225] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126d3d8 state to ffff8801f5245508
>[32m[  249.505227] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5cc258 to [CRTC:56:pipe C]
>[32m[  249.505229] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801fb5cc258
>[32m[  249.505231] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.505258] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 109
>[32m[  249.505280] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  249.505285] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.521831] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.521843] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.521867] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8801fb5cd978
>[32m[  249.521893] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 109
>[32m[  249.521915] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  249.538684] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f5245508
>[32m[  249.538692] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801f5245508
>[32m[  249.538697] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1268008 state to ffff8801f5245508
>[32m[  249.538700] [0m[drm:drm_atomic_check_only] checking ffff8801f5245508
>[32m[  249.538705] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.538708] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  249.538712] [0m[drm:drm_atomic_commit] committing ffff8801f5245508
>[32m[  249.555152] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f5245508
>[32m[  249.555164] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f5245508
>[32m[  249.555419] [0m[drm:drm_mode_addfb2] [FB:110]
>[32m[  249.561686] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  249.561701] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  249.561709] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff880211b85fa8
>[32m[  249.561715] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f126d3d8 state to ffff880211b85fa8
>[32m[  249.561720] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801fb5ce2b8 state to ffff880211b85fa8
>[32m[  249.561725] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f126d3d8
>[32m[  249.561728] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801fb5ce2b8 to [CRTC:56:pipe C]
>[32m[  249.561730] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801fb5ce2b8
>[32m[  249.561733] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  249.561741] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8cb8 state to ffff880211b85fa8
>[32m[  249.561744] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b8cb8 to [NOCRTC]
>[32m[  249.561748] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9466bd8 state to ffff880211b85fa8
>[32m[  249.561751] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9466bd8 to [CRTC:56:pipe C]
>[32m[  249.561754] [0m[drm:drm_atomic_check_only] checking ffff880211b85fa8
>[32m[  249.561757] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  249.561761] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  249.561764] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:56:pipe C]
>[32m[  249.561766] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.561768] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  249.561770] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  249.561772] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  249.561779] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212e9a8 state to ffff880211b85fa8
>[32m[  249.561783] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212ebf8 state to ffff880211b85fa8
>[32m[  249.561786] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff880211b85fa8
>[32m[  249.561815] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  249.561837] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  249.561859] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  249.561865] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f12692a8 state to ffff880211b85fa8
>[32m[  249.561885] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  249.561907] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  249.561927] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  249.561947] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  249.561966] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  249.561985] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  249.562021] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  249.562041] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  249.562046] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  249.562068] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  249.562090] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  249.562112] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  249.562133] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  249.562157] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  249.562179] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  249.562200] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[32m[  249.562222] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:82, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  249.562243] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:109, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  249.562270] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 110
>[32m[  249.562292] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.562316] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 82
>[32m[  249.562338] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.562360] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 109
>[32m[  249.562381] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.562425] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  249.562446] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  249.562452] [0m[drm:drm_atomic_commit] committing ffff880211b85fa8
>[32m[  249.564890] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  249.589602] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  249.589630] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  249.589863] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  249.589884] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  249.589906] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  249.589926] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  249.589948] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.589971] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  249.590002] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  249.590661] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  249.590844] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  249.590873] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  249.590893] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  249.590919] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  249.590938] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  249.590956] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  249.590979] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  249.591008] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  249.625765] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  249.625796] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  249.625835] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.625847] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff880211b85fa8
>[32m[  249.625871] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff880211b85fa8
>[32m[  249.625909] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.625914] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88021212c008 state to ffff8801f1258008
>[32m[  249.625920] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129a548 state to ffff8801f1258008
>[32m[  249.625922] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c008 to [NOCRTC]
>[32m[  249.625924] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212c008
>[32m[  249.625926] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.625949] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  249.625969] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  249.625974] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.642369] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.642381] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.642410] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.642415] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88021212e9a8 state to ffff8801f1258008
>[32m[  249.642420] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129dd28 state to ffff8801f1258008
>[32m[  249.642423] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212e9a8 to [NOCRTC]
>[32m[  249.642425] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88021212e9a8
>[32m[  249.642427] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.642453] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  249.642475] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  249.642480] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.659012] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.659025] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.709278] [0m[drm:drm_mode_addfb2] [FB:109]
>[32m[  249.709413] [0m[drm:drm_mode_addfb2] [FB:111]
>[32m[  249.713934] [0m[drm:drm_mode_addfb2] [FB:112]
>[32m[  249.715907] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  249.715928] [0m[drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1]
>[32m[  249.715937] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.715943] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129a548 state to ffff8801f1258008
>[32m[  249.715948] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88021212c6f8 state to ffff8801f1258008
>[32m[  249.715954] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129a548
>[32m[  249.715956] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88021212c6f8 to [CRTC:56:pipe C]
>[32m[  249.715958] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88021212c6f8
>[32m[  249.715961] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1258008
>[32m[  249.715969] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f94677a8 state to ffff8801f1258008
>[32m[  249.715972] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f94677a8 to [NOCRTC]
>[32m[  249.715975] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f94677a8 to [CRTC:56:pipe C]
>[32m[  249.715978] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.715983] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  249.715986] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] keeps [ENCODER:58:CRT], now on [CRTC:56:pipe C]
>[32m[  249.716051] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 112
>[32m[  249.716078] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  249.716086] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.725502] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.725519] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.725563] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.725568] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802135a3098 state to ffff8801f1258008
>[32m[  249.725573] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129dd28 state to ffff8801f1258008
>[32m[  249.725576] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802135a3098 to [CRTC:56:pipe C]
>[32m[  249.725578] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff8802135a3098
>[32m[  249.725580] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.725608] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 109
>[32m[  249.725630] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  249.725634] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.742127] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.742138] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.742172] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.742178] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802128e9978 state to ffff8801f1258008
>[32m[  249.742183] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129a548 state to ffff8801f1258008
>[32m[  249.742186] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128e9978 to [CRTC:56:pipe C]
>[32m[  249.742188] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802128e9978
>[32m[  249.742190] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.742217] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 113
>[32m[  249.742239] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  249.742244] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.758747] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.758759] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.758784] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802128eb098
>[32m[  249.758810] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 113
>[32m[  249.758832] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  249.775738] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.775747] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b9b38 state to ffff8801f1258008
>[32m[  249.775749] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.775752] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.775754] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:60:HDMI-A-1]
>[32m[  249.775757] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.775769] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.775783] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.775830] [0m[drm:drm_mode_addfb2] [FB:114]
>[32m[  249.781486] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  249.781506] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  249.781516] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.781521] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1299bf8 state to ffff8801f1258008
>[32m[  249.781526] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802128eb538 state to ffff8801f1258008
>[32m[  249.781532] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1299bf8
>[32m[  249.781534] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802128eb538 to [CRTC:56:pipe C]
>[32m[  249.781536] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff8802128eb538
>[32m[  249.781539] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1258008
>[32m[  249.781546] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9466bd8 state to ffff8801f1258008
>[32m[  249.781550] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9466bd8 to [NOCRTC]
>[32m[  249.781554] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b81d8 state to ffff8801f1258008
>[32m[  249.781557] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b81d8 to [CRTC:56:pipe C]
>[32m[  249.781561] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.781564] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  249.781568] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  249.781570] [0m[drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:57:VGA-1]
>[32m[  249.781572] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.781574] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] using [ENCODER:59:HDMI C] on [CRTC:56:pipe C]
>[32m[  249.781577] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: y, active: y
>[32m[  249.781579] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1258008
>[32m[  249.781585] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802128ea2b8 state to ffff8801f1258008
>[32m[  249.781591] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cd4d8 state to ffff8801f1258008
>[32m[  249.781594] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1258008
>[32m[  249.781622] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  249.781644] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  249.781667] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  249.781687] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  249.781708] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe C, lanes 2
>[32m[  249.781714] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129e678 state to ffff8801f1258008
>[32m[  249.781734] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  249.781755] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[32m[  249.781774] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: C, pipe bpp: 24, dithering: 0
>[32m[  249.781794] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  249.781813] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  249.781832] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  249.781835] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  249.781853] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  249.781855] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  249.781874] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  249.781892] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  249.781910] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  249.781928] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  249.781949] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  249.781967] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  249.781986] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:47:primary C] FB:112, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[32m[  249.782038] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:50:sprite C] FB:109, fb = 256x256 format = XR24 little-endian (0x34325258)
>[32m[  249.782059] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] FB:113, fb = 128x128 format = AR24 little-endian (0x34325241)
>[32m[  249.782086] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 114
>[32m[  249.782107] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.782130] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 109
>[32m[  249.782151] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.782172] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 113
>[32m[  249.782192] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 1, on 1, ms 1
>[32m[  249.782235] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated PCH DPLL A
>[32m[  249.782255] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe C
>[32m[  249.782261] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.784506] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  249.809213] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  249.809241] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  249.809473] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  249.809497] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  249.809516] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  249.809536] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  249.809558] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.809581] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  249.809612] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  249.810272] [0m[drm:intel_enable_pipe [i915]] enabling pipe C
>[32m[  249.810455] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  249.810484] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  249.810503] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  249.810529] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x200
>[32m[  249.810549] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  249.810566] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  249.810590] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 4, on? 0) for crtc 56
>[32m[  249.810609] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  249.845457] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  249.845488] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  249.845527] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  249.845540] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.845563] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.845607] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.845612] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cc4a8 state to ffff8801f1258008
>[32m[  249.845617] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129a548 state to ffff8801f1258008
>[32m[  249.845620] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc4a8 to [NOCRTC]
>[32m[  249.845622] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc4a8
>[32m[  249.845624] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.845647] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  249.845668] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  249.845672] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.862098] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.862109] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.862137] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.862143] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cc6f8 state to ffff8801f1258008
>[32m[  249.862148] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1299bf8 state to ffff8801f1258008
>[32m[  249.862150] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cc6f8 to [NOCRTC]
>[32m[  249.862152] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802111cc6f8
>[32m[  249.862154] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.862180] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  249.862202] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 0
>[32m[  249.862207] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.878759] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.878771] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.928961] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.928969] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b8ae8 state to ffff8801f1258008
>[32m[  249.928975] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129a548 state to ffff8801f1258008
>[32m[  249.928977] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.928983] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.928985] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  249.929030] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.945435] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.945447] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.945703] [0m[drm:drm_mode_addfb2] [FB:113]
>[32m[  249.945841] [0m[drm:drm_mode_addfb2] [FB:115]
>[32m[  249.949894] [0m[drm:drm_mode_addfb2] [FB:116]
>[32m[  249.951664] [0m[drm:drm_mode_setcrtc] [CRTC:56:pipe C]
>[32m[  249.951686] [0m[drm:drm_mode_setcrtc] [CONNECTOR:60:HDMI-A-1]
>[32m[  249.951695] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.951701] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1298008 state to ffff8801f1258008
>[32m[  249.951706] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8802111ccde8 state to ffff8801f1258008
>[32m[  249.951712] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f1298008
>[32m[  249.951714] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111ccde8 to [CRTC:56:pipe C]
>[32m[  249.951717] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:116] for plane state ffff8802111ccde8
>[32m[  249.951719] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f1258008
>[32m[  249.951727] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b9b38 state to ffff8801f1258008
>[32m[  249.951730] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b9b38 to [NOCRTC]
>[32m[  249.951733] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8802128b9b38 to [CRTC:56:pipe C]
>[32m[  249.951737] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.951741] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  249.951744] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  249.951776] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb 116
>[32m[  249.951798] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  249.951803] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.962107] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.962123] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.962168] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.962173] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8802111cdbc8 state to ffff8801f1258008
>[32m[  249.962178] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129a548 state to ffff8801f1258008
>[32m[  249.962181] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cdbc8 to [CRTC:56:pipe C]
>[32m[  249.962183] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:113] for plane state ffff8802111cdbc8
>[32m[  249.962185] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.962212] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb 113
>[32m[  249.962235] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  249.962239] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.978772] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.978783] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.978859] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  249.978865] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8802111cd288 state to ffff8801f1258008
>[32m[  249.978870] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f1298008 state to ffff8801f1258008
>[32m[  249.978872] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802111cd288 to [CRTC:56:pipe C]
>[32m[  249.978874] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff8802111cd288
>[32m[  249.978876] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  249.978903] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 117
>[32m[  249.978926] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 0 -> 1, off 0, on 1, ms 0
>[32m[  249.978930] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  249.995433] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  249.995446] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  249.995471] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:117] for plane state ffff88020ffdee48
>[32m[  249.995498] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb 117
>[32m[  249.995520] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 1, off 0, on 0, ms 0
>[32m[  250.012270] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f1258008
>[32m[  250.012278] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff8802128b93f8 state to ffff8801f1258008
>[32m[  250.012283] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129ae98 state to ffff8801f1258008
>[32m[  250.012286] [0m[drm:drm_atomic_check_only] checking ffff8801f1258008
>[32m[  250.012290] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  250.012293] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:56:pipe C]
>[32m[  250.012298] [0m[drm:drm_atomic_commit] committing ffff8801f1258008
>[32m[  250.028755] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f1258008
>[32m[  250.028766] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f1258008
>[32m[  250.028903] [0m[33m[IGT] kms_plane_multiple[0m: exiting, ret=0
>[32m[  250.038413] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f125da58
>[32m[  250.038420] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9533788 state to ffff8801f125da58
>[32m[  250.038425] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9531038 state to ffff8801f125da58
>[32m[  250.038427] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [NOCRTC]
>[32m[  250.038429] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531038
>[32m[  250.038433] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f95306f8 state to ffff8801f125da58
>[32m[  250.038435] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [NOCRTC]
>[32m[  250.038436] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95306f8
>[32m[  250.038439] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f125da58
>[32m[  250.038451] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f95306f8 state to ffff8801f125da58
>[32m[  250.038455] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f95314d8 state to ffff8801f125da58
>[32m[  250.038457] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95314d8 to [NOCRTC]
>[32m[  250.038458] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95314d8
>[32m[  250.038462] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9531038 state to ffff8801f125da58
>[32m[  250.038464] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [NOCRTC]
>[32m[  250.038466] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531038
>[32m[  250.038470] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9532bf8 state to ffff8801f125da58
>[32m[  250.038472] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f125da58
>[32m[  250.038484] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9532bf8 state to ffff8801f125da58
>[32m[  250.038489] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9533538 state to ffff8801f125da58
>[32m[  250.038490] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533538 to [NOCRTC]
>[32m[  250.038492] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533538
>[32m[  250.038496] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9531038 state to ffff8801f125da58
>[32m[  250.038497] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [NOCRTC]
>[32m[  250.038499] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531038
>[32m[  250.038503] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9530948 state to ffff8801f125da58
>[32m[  250.038506] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f95314d8 state to ffff8801f125da58
>[32m[  250.038508] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95314d8 to [NOCRTC]
>[32m[  250.038509] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95314d8
>[32m[  250.038513] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f95339d8 state to ffff8801f125da58
>[32m[  250.038515] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  250.038516] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  250.038520] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f95306f8 state to ffff8801f125da58
>[32m[  250.038525] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129efc8 state to ffff8801f125da58
>[32m[  250.038529] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9531288 state to ffff8801f125da58
>[32m[  250.038531] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [NOCRTC]
>[32m[  250.038532] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531288
>[32m[  250.038536] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f9533788 state to ffff8801f125da58
>[32m[  250.038538] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [NOCRTC]
>[32m[  250.038539] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533788
>[32m[  250.038544] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129dd28 state to ffff8801f125da58
>[32m[  250.038550] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129dd28
>[32m[  250.038551] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532bf8 to [CRTC:36:pipe A]
>[32m[  250.038554] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9532bf8
>[32m[  250.038556] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f125da58
>[32m[  250.038586] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9533788 state to ffff8801f125da58
>[32m[  250.038590] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9530258 state to ffff8801f125da58
>[32m[  250.038591] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530258 to [NOCRTC]
>[32m[  250.038593] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530258
>[32m[  250.038597] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9531288 state to ffff8801f125da58
>[32m[  250.038598] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531288 to [NOCRTC]
>[32m[  250.038600] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531288
>[32m[  250.038604] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9531728 state to ffff8801f125da58
>[32m[  250.038608] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f95306f8 state to ffff8801f125da58
>[32m[  250.038609] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95306f8 to [NOCRTC]
>[32m[  250.038611] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95306f8
>[32m[  250.038615] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f95304a8 state to ffff8801f125da58
>[32m[  250.038616] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95304a8 to [NOCRTC]
>[32m[  250.038618] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95304a8
>[32m[  250.038621] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff8801f95339d8 state to ffff8801f125da58
>[32m[  250.038626] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:56:pipe C] ffff8801f129efc8 state to ffff8801f125da58
>[32m[  250.038630] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff8801f9532758 state to ffff8801f125da58
>[32m[  250.038631] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9532758 to [NOCRTC]
>[32m[  250.038633] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9532758
>[32m[  250.038637] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff8801f95314d8 state to ffff8801f125da58
>[32m[  250.038638] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95314d8 to [NOCRTC]
>[32m[  250.038640] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95314d8
>[32m[  250.038644] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129a548 state to ffff8801f125da58
>[32m[  250.038648] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129a548
>[32m[  250.038649] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533788 to [CRTC:36:pipe A]
>[32m[  250.038651] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9533788
>[32m[  250.038653] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f125da58
>[32m[  250.038661] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:57:VGA-1] ffff8801f9467448 state to ffff8801f125da58
>[32m[  250.038663] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f9467448 to [CRTC:36:pipe A]
>[32m[  250.038667] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129dd28 state to ffff8801f125da58
>[32m[  250.038672] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801f129dd28
>[32m[  250.038673] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531728 to [CRTC:46:pipe B]
>[32m[  250.038675] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9531728
>[32m[  250.038677] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f125da58
>[32m[  250.038683] [0m[drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:HDMI-A-1] ffff880212b24918 state to ffff8801f125da58
>[32m[  250.038685] [0m[drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880212b24918 to [CRTC:46:pipe B]
>[32m[  250.038686] [0m[drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801f129efc8
>[32m[  250.038688] [0m[drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f129efc8
>[32m[  250.038690] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f95339d8 to [NOCRTC]
>[32m[  250.038691] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f95339d8
>[32m[  250.038693] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f125da58
>[32m[  250.038696] [0m[drm:drm_atomic_check_only] checking ffff8801f125da58
>[32m[  250.038699] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>[32m[  250.038701] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] enable changed
>[32m[  250.038702] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] active changed
>[32m[  250.038704] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] mode changed
>[32m[  250.038705] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] enable changed
>[32m[  250.038707] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] active changed
>[32m[  250.038708] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] mode changed
>[32m[  250.038709] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] enable changed
>[32m[  250.038711] [0m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] active changed
>[32m[  250.038715] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:57:VGA-1]
>[32m[  250.038717] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:57:VGA-1] using [ENCODER:58:CRT] on [CRTC:36:pipe A]
>[32m[  250.038719] [0m[drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:HDMI-A-1]
>[32m[  250.038721] [0m[drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:HDMI-A-1] keeps [ENCODER:59:HDMI C], now on [CRTC:46:pipe B]
>[32m[  250.038723] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable[0m: y, active: y
>[32m[  250.038725] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f125da58
>[32m[  250.038728] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:46:pipe B] needs all connectors, enable[0m: y, active: y
>[32m[  250.038730] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f125da58
>[32m[  250.038733] [0m[33m[drm:drm_atomic_helper_check_modeset] [CRTC:56:pipe C] needs all connectors, enable[0m: n, active: n
>[32m[  250.038735] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:56:pipe C] to ffff8801f125da58
>[32m[  250.038739] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801f125da58
>[32m[  250.038766] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains
>[32m[  250.038787] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[32m[  250.038809] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2
>[32m[  250.038829] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  250.038849] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[32m[  250.038869] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: A, pipe bpp: 24, dithering: 0
>[32m[  250.038889] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[32m[  250.038907] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 0
>[32m[  250.038926] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  250.038928] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  250.038946] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  250.038948] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[32m[  250.038966] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[32m[  250.038984] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 154000, pipe src size: 1920x1200, pixel rate 154000
>[32m[  250.039028] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  250.039054] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  250.039075] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
>[32m[  250.039093] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  250.039110] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0
>[32m[  250.039128] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0
>[32m[  250.039145] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0
>[32m[  250.039147] [0m[drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:pipe B] to ffff8801f125da58
>[32m[  250.039168] [0m[drm:intel_atomic_check [i915]] [CONNECTOR:60:HDMI-A-1] checking for sink bpp constrains
>[32m[  250.039187] [0m[drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[32m[  250.039208] [0m[drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[32m[  250.039227] [0m[drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[32m[  250.039246] [0m[drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
>[32m[  250.039264] [0m[33m[drm:intel_atomic_check [i915]] hw max bpp[0m: 36, pipe bpp: 24, dithering: 0
>[32m[  250.039282] [0m[drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[32m[  250.039300] [0m[33m[drm:intel_dump_pipe_config [i915]] cpu_transcoder[0m: B, pipe bpp: 24, dithering: 0
>[32m[  250.039318] [0m[33m[drm:intel_dump_pipe_config [i915]] fdi[0m: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[32m[  250.039335] [0m[33m[drm:intel_dump_pipe_config [i915]] audio[0m: 0, infoframes: 1
>[32m[  250.039351] [0m[drm:intel_dump_pipe_config [i915]] requested mode:
>[32m[  250.039354] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  250.039370] [0m[drm:intel_dump_pipe_config [i915]] adjusted mode:
>[32m[  250.039372] [0m[drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[32m[  250.039390] [0m[33m[drm:intel_dump_pipe_config [i915]] crtc timings[0m: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[32m[  250.039407] [0m[33m[drm:intel_dump_pipe_config [i915]] port clock[0m: 148500, pipe src size: 1920x1080, pixel rate 148500
>[32m[  250.039424] [0m[33m[drm:intel_dump_pipe_config [i915]] pch pfit[0m: pos: 0x00000000, size: 0x00000000, disabled
>[32m[  250.039441] [0m[33m[drm:intel_dump_pipe_config [i915]] ips[0m: 0, double wide: 0
>[32m[  250.039460] [0m[33m[drm:ibx_dump_hw_state [i915]] dpll_hw_state[0m: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x21007, fp1: 0x21007
>[32m[  250.039477] [0m[drm:intel_dump_pipe_config [i915]] planes on this crtc
>[32m[  250.039494] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0
>[32m[  250.039511] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0
>[32m[  250.039527] [0m[drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0
>[32m[  250.039550] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:27:primary A] with fb 96
>[32m[  250.039569] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:primary A] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  250.039588] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:46:pipe B] has [PLANE:37:primary B] with fb 96
>[32m[  250.039607] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:primary B] visible 0 -> 1, off 0, on 1, ms 1
>[32m[  250.039626] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:47:primary C] with fb -1
>[32m[  250.039644] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:47:primary C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  250.039662] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:50:sprite C] with fb -1
>[32m[  250.039680] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:50:sprite C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  250.039698] [0m[drm:intel_plane_atomic_calc_changes [i915]] [CRTC:56:pipe C] has [PLANE:53:cursor C] with fb -1
>[32m[  250.039716] [0m[drm:intel_plane_atomic_calc_changes [i915]] [PLANE:53:cursor C] visible 1 -> 0, off 1, on 0, ms 1
>[32m[  250.039753] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated PCH DPLL A
>[32m[  250.039772] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
>[32m[  250.039809] [0m[drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated PCH DPLL B
>[32m[  250.039827] [0m[drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
>[32m[  250.039831] [0m[drm:drm_atomic_commit] committing ffff8801f125da58
>[32m[  250.039906] [0m[drm:intel_disable_pipe [i915]] disabling pipe C
>[32m[  250.063655] [0m[drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 4, on? 1) for crtc 56
>[32m[  250.063682] [0m[drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
>[32m[  250.063915] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT]
>[32m[  250.063934] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:59:HDMI C]
>[32m[  250.063953] [0m[drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP C]
>[32m[  250.063972] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  250.063995] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  250.064069] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
>[32m[  250.064700] [0m[drm:intel_enable_pipe [i915]] enabling pipe A
>[32m[  250.064882] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  250.064911] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  250.064931] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  250.064955] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  250.064974] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  250.064991] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  250.065022] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 36
>[32m[  250.065041] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
>[32m[  250.083154] [0m[drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
>[32m[  250.083817] [0m[drm:intel_enable_pipe [i915]] enabling pipe B
>[32m[  250.084001] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x0
>[32m[  250.084057] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x100
>[32m[  250.084089] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
>[32m[  250.084115] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
>[32m[  250.084135] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
>[32m[  250.084152] [0m[drm:ivb_manual_fdi_link_train [i915]] FDI train done.
>[32m[  250.084176] [0m[drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 46
>[32m[  250.084195] [0m[drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
>[32m[  250.119037] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:57:VGA-1]
>[32m[  250.119076] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[32m[  250.119115] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
>[32m[  250.119145] [0m[drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:60:HDMI-A-1]
>[32m[  250.119168] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[32m[  250.119205] [0m[drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
>[32m[  250.119235] [0m[drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[32m[  250.119247] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f125da58
>[32m[  250.119292] [0m[drm:__drm_atomic_state_free] Freeing atomic state ffff8801f125da58
>[32m[  250.123267] [0m[33mConsole[0m: switching to colour frame buffer device 240x67
>[32m[  250.128734] [0m[drm:drm_atomic_state_init] Allocated atomic state ffff8801f125da58
>[32m[  250.128742] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9530008 state to ffff8801f125da58
>[32m[  250.128749] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129ae98 state to ffff8801f125da58
>[32m[  250.128754] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9533c28 state to ffff8801f125da58
>[32m[  250.128757] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533c28 to [NOCRTC]
>[32m[  250.128759] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533c28
>[32m[  250.128765] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9530948 state to ffff8801f125da58
>[32m[  250.128767] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [NOCRTC]
>[32m[  250.128769] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530948
>[32m[  250.128773] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f125da58
>[32m[  250.128788] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9530948 state to ffff8801f125da58
>[32m[  250.128793] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129ae98 state to ffff8801f125da58
>[32m[  250.128798] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9531038 state to ffff8801f125da58
>[32m[  250.128800] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [NOCRTC]
>[32m[  250.128802] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9531038
>[32m[  250.128805] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f125da58
>[32m[  250.128817] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff8801f9531038 state to ffff8801f125da58
>[32m[  250.128822] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129ae98 state to ffff8801f125da58
>[32m[  250.128827] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff8801f9533538 state to ffff8801f125da58
>[32m[  250.128830] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533538 to [NOCRTC]
>[32m[  250.128832] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533538
>[32m[  250.128837] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff8801f9530948 state to ffff8801f125da58
>[32m[  250.128839] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530948 to [NOCRTC]
>[32m[  250.128841] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530948
>[32m[  250.128846] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff8801f9532bf8 state to ffff8801f125da58
>[32m[  250.128851] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129b7e8 state to ffff8801f125da58
>[32m[  250.128856] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff8801f9533c28 state to ffff8801f125da58
>[32m[  250.128859] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9533c28 to [NOCRTC]
>[32m[  250.128861] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9533c28
>[32m[  250.128866] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff8801f9530008 state to ffff8801f125da58
>[32m[  250.128868] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9530008 to [NOCRTC]
>[32m[  250.128870] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f9530008
>[32m[  250.128875] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020e07a508 state to ffff8801f125da58
>[32m[  250.128880] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020e078de8 state to ffff8801f125da58
>[32m[  250.128882] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078de8 to [NOCRTC]
>[32m[  250.128884] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078de8
>[32m[  250.128889] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020e07a9a8 state to ffff8801f125da58
>[32m[  250.128892] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a9a8 to [NOCRTC]
>[32m[  250.128894] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a9a8
>[32m[  250.128901] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129ae98
>[32m[  250.128904] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f9531038 to [CRTC:36:pipe A]
>[32m[  250.128906] [0m[drm:drm_atomic_set_fb_for_plane] Set [FB:96] for plane state ffff8801f9531038
>[32m[  250.128909] [0m[drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801f125da58
>[32m[  250.128952] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:27:primary A] ffff88020e07a9a8 state to ffff8801f125da58
>[32m[  250.128957] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801f129b7e8 state to ffff8801f125da58
>[32m[  250.128962] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:30:sprite A] ffff88020e07b2e8 state to ffff8801f125da58
>[32m[  250.128964] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b2e8 to [NOCRTC]
>[32m[  250.128966] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b2e8
>[32m[  250.128971] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor A] ffff88020e078de8 state to ffff8801f125da58
>[32m[  250.128973] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e078de8 to [NOCRTC]
>[32m[  250.128975] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e078de8
>[32m[  250.128980] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:37:primary B] ffff88020e0794d8 state to ffff8801f125da58
>[32m[  250.128985] [0m[drm:drm_atomic_get_crtc_state] Added [CRTC:46:pipe B] ffff8801f129ca88 state to ffff8801f125da58
>[32m[  250.129016] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:40:sprite B] ffff88020e07a508 state to ffff8801f125da58
>[32m[  250.129018] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07a508 to [NOCRTC]
>[32m[  250.129021] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07a508
>[32m[  250.129026] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:43:cursor B] ffff88020e07b788 state to ffff8801f125da58
>[32m[  250.129028] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020e07b788 to [NOCRTC]
>[32m[  250.129030] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020e07b788
>[32m[  250.129037] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:47:primary C] ffff88020e078258 state to ffff8801f125da58
>[32m[  250.129043] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:50:sprite C] ffff88020ec51728 state to ffff8801f125da58
>[32m[  250.129047] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec51728 to [NOCRTC]
>[32m[  250.129050] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec51728
>[32m[  250.129056] [0m[drm:drm_atomic_get_plane_state] Added [PLANE:53:cursor C] ffff88020ec2e2b8 state to ffff8801f125da58
>[32m[  250.129060] [0m[drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88020ec2e2b8 to [NOCRTC]
>[32m[  250.129063] [0m[drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88020ec2e2b8
>[32m[  250.129069] [0m[drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f129b7e8
>[

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Attachments on bug 101907: 132934 | 132935 | 133295 | 133296

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