Attachment 133741 Details for Bug 102243 – dmesg snipped with logs where timeout is less than 1us

dmesg snipped with logs where timeout is less than 1us

pass.txt (text/plain), 12.26 KB, created by Marta Löfstedt on 2017-08-24 11:42:29 UTC

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Creator: Marta Löfstedt

Created: 2017-08-24 11:42:29 UTC

Size: 12.26 KB

patch

obsolete

> [drm:hsw_enable_pc8 [i915		 Enabling package C8+		
> PM: late suspend of devices complete after 20.035 msecs				
> PM: noirq suspend of devices complete after 39.907 msecs				
> ACPI: Preparing to enter system sleep state S3				
> PM: Saving platform NVS memory				
> Disabling non-boot CPUs ...				
> smpboot: CPU 1 is now offline				
> smpboot: CPU 2 is now offline				
> smpboot: CPU 3 is now offline				
> ACPI: Low-level resume complete				
> PM: Restoring platform NVS memory				
> Suspended for 15.908 seconds				
> Enabling non-boot CPUs ...				
> x86: Booting SMP configuration:				
> smpboot: Booting Node 0 Processor 1 APIC 0x2				
>  cache: parent cpu1 should not be sleeping				
> CPU1 is up				
> smpboot: Booting Node 0 Processor 2 APIC 0x1				
>  cache: parent cpu2 should not be sleeping				
> CPU2 is up				
> smpboot: Booting Node 0 Processor 3 APIC 0x3				
>  cache: parent cpu3 should not be sleeping				
> CPU3 is up				
> ACPI: Waking up from system sleep state S3				
> PM: noirq resume of devices complete after 41.511 msecs				
> [drm:hsw_disable_pc8 [i915		 Disabling package C8+		
> [drm:intel_power_well_enable [i915		 enabling always-on		
> [drm:intel_power_well_enable [i915		 enabling display		
> PM: early resume of devices complete after 2.205 msecs				
> [drm:intel_opregion_setup [i915		 graphic opregion physical addr: 0xa2c9a018		
> [drm:intel_opregion_setup [i915		 Public ACPI methods supported		
> [drm:intel_opregion_setup [i915		 SWSCI supported		
> sd 0:0:0:0: [sda	 Starting disk			
> nuvoton-cir 00:01: activated				
> [drm:intel_opregion_setup [i915		 SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483		
> [drm:intel_opregion_setup [i915		 ASLE supported		
> [drm:intel_opregion_setup [i915		 ASLE extension supported		
> [drm:intel_opregion_setup [i915		 Found valid VBT in ACPI OpRegion (Mailbox #4)		
> [drm:gen8_init_common_ring [i915		 Execlists enabled for rcs0		
> [drm:init_workarounds_ring [i915		 rcs0: Number of context specific w/a: 11		
> [drm:gen8_init_common_ring [i915		 Execlists enabled for bcs0		
> [drm:gen8_init_common_ring [i915		 Execlists enabled for vcs0		
> [drm:gen8_init_common_ring [i915		 Execlists enabled for vcs1		
> [drm:gen8_init_common_ring [i915		 Execlists enabled for vecs0		
> [drm:intel_update_cdclk [i915		 Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz		
> [drm:intel_set_plane_visible [i915		 pipe A active planes 0x0		
> [drm:intel_modeset_setup_hw_state [i915		 [CRTC:36:pipe A	 hw state readout: disabled	
> [drm:intel_set_plane_visible [i915		 pipe B active planes 0x0		
> [drm:intel_modeset_setup_hw_state [i915		 [CRTC:46:pipe B	 hw state readout: disabled	
> [drm:intel_set_plane_visible [i915		 pipe C active planes 0x0		
> [drm:intel_modeset_setup_hw_state [i915		 [CRTC:56:pipe C	 hw state readout: disabled	
> [drm:intel_modeset_setup_hw_state [i915		 WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0		
> [drm:intel_modeset_setup_hw_state [i915		 WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0		
> [drm:intel_modeset_setup_hw_state [i915		 SPLL hw state readout: crtc_mask 0x00000000, on 0		
> [drm:intel_modeset_setup_hw_state [i915		 LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1		
> [drm:intel_modeset_setup_hw_state [i915		 LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1		
> [drm:intel_modeset_setup_hw_state [i915		 LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1		
> [drm:intel_modeset_setup_hw_state [i915		 [ENCODER:57:DDI B	 hw state readout: disabled, pipe A	
> [drm:intel_modeset_setup_hw_state [i915		 [ENCODER:62:DDI C	 hw state readout: disabled, pipe A	
> [drm:intel_modeset_setup_hw_state [i915		 [ENCODER:64:DP-MST A	 hw state readout: disabled, pipe A	
> [drm:intel_modeset_setup_hw_state [i915		 [ENCODER:65:DP-MST B	 hw state readout: disabled, pipe B	
> [drm:intel_modeset_setup_hw_state [i915		 [ENCODER:66:DP-MST C	 hw state readout: disabled, pipe C	
> [drm:intel_modeset_setup_hw_state [i915		 [CONNECTOR:58:HDMI-A-1	 hw state readout: disabled	
> [drm:intel_modeset_setup_hw_state [i915		 [CONNECTOR:63:DP-1	 hw state readout: disabled	
> [drm:intel_modeset_setup_hw_state [i915		 [CONNECTOR:67:HDMI-A-2	 hw state readout: disabled	
> [drm:intel_dump_pipe_config [i915		 [CRTC:36:pipe A	[setup_hw_state	
> [drm:intel_dump_pipe_config [i915		 cpu_transcoder: A, pipe bpp: 0, dithering: 0		
> [drm:intel_dump_pipe_config [i915		 audio: 0, infoframes: 0		
> [drm:intel_dump_pipe_config [i915		 requested mode:		
> [drm:drm_mode_debug_printmodeline [drm		 Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0		
> [drm:intel_dump_pipe_config [i915		 adjusted mode:		
> [drm:drm_mode_debug_printmodeline [drm		 Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0		
> [drm:intel_dump_pipe_config [i915		 crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0		
> [drm:intel_dump_pipe_config [i915		 port clock: 0, pipe src size: 0x0, pixel rate 0		
> [drm:intel_dump_pipe_config [i915		 pch pfit: pos: 0x00000000, size: 0x00000000, disabled		
> [drm:intel_dump_pipe_config [i915		 ips: 0, double wide: 0		
> [drm:hsw_dump_hw_state [i915		 dpll_hw_state: wrpll: 0x0 spll: 0x0		
> [drm:intel_dump_pipe_config [i915		 planes on this crtc		
> [drm:intel_dump_pipe_config [i915		 [PLANE:27:primary A	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [PLANE:30:sprite A	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [PLANE:33:cursor A	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [CRTC:46:pipe B	[setup_hw_state	
> [drm:intel_dump_pipe_config [i915		 cpu_transcoder: B, pipe bpp: 0, dithering: 0		
> [drm:intel_dump_pipe_config [i915		 audio: 0, infoframes: 0		
> [drm:intel_dump_pipe_config [i915		 requested mode:		
> [drm:drm_mode_debug_printmodeline [drm		 Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0		
> [drm:intel_dump_pipe_config [i915		 adjusted mode:		
> [drm:drm_mode_debug_printmodeline [drm		 Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0		
> [drm:intel_dump_pipe_config [i915		 crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0		
> [drm:intel_dump_pipe_config [i915		 port clock: 0, pipe src size: 0x0, pixel rate 0		
> [drm:intel_dump_pipe_config [i915		 pch pfit: pos: 0x00000000, size: 0x00000000, disabled		
> [drm:intel_dump_pipe_config [i915		 ips: 0, double wide: 0		
> [drm:hsw_dump_hw_state [i915		 dpll_hw_state: wrpll: 0x0 spll: 0x0		
> [drm:intel_dump_pipe_config [i915		 planes on this crtc		
> [drm:intel_dump_pipe_config [i915		 [PLANE:37:primary B	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [PLANE:40:sprite B	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [PLANE:43:cursor B	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [CRTC:56:pipe C	[setup_hw_state	
> [drm:intel_dump_pipe_config [i915		 cpu_transcoder: C, pipe bpp: 0, dithering: 0		
> [drm:intel_dump_pipe_config [i915		 audio: 0, infoframes: 0		
> [drm:intel_dump_pipe_config [i915		 requested mode:		
> [drm:drm_mode_debug_printmodeline [drm		 Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0		
> [drm:intel_dump_pipe_config [i915		 adjusted mode:		
> [drm:drm_mode_debug_printmodeline [drm		 Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0		
> [drm:intel_dump_pipe_config [i915		 crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0		
> [drm:intel_dump_pipe_config [i915		 port clock: 0, pipe src size: 0x0, pixel rate 0		
> [drm:intel_dump_pipe_config [i915		 pch pfit: pos: 0x00000000, size: 0x00000000, disabled		
> [drm:intel_dump_pipe_config [i915		 ips: 0, double wide: 0		
> [drm:hsw_dump_hw_state [i915		 dpll_hw_state: wrpll: 0x0 spll: 0x0		
> [drm:intel_dump_pipe_config [i915		 planes on this crtc		
> [drm:intel_dump_pipe_config [i915		 [PLANE:47:primary C	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [PLANE:50:sprite C	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [PLANE:53:cursor C	 disabled, scaler_id = 0	
> [drm:intel_modeset_setup_hw_state [i915		 LCPLL 810 enabled but not in use, disabling		
> [drm:intel_modeset_setup_hw_state [i915		 LCPLL 1350 enabled but not in use, disabling		
> [drm:intel_modeset_setup_hw_state [i915		 LCPLL 2700 enabled but not in use, disabling		
> [drm:drm_atomic_check_only [drm		 checking ffff9f5a457af400		
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 [CRTC:36:pipe A	 mode changed	
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 [CRTC:36:pipe A	 enable changed	
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 [CRTC:36:pipe A	 active changed	
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 Updating routing for [CONNECTOR:58:HDMI-A-1		
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 Disabling [CONNECTOR:58:HDMI-A-1		
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 Updating routing for [CONNECTOR:63:DP-1		
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 Disabling [CONNECTOR:63:DP-1		
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 Updating routing for [CONNECTOR:67:HDMI-A-2		
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 [CONNECTOR:67:HDMI-A-2	 keeps [ENCODER:62:DDI C	, now on [CRTC:36:pipe A
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 [CRTC:36:pipe A	 needs all connectors, enable: y, active: y	
> [drm:drm_atomic_add_affected_connectors [drm		 Adding all current connectors for [CRTC:36:pipe A	 to ffff9f5a457af400	
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 [CRTC:46:pipe B	 needs all connectors, enable: n, active: n	
> [drm:drm_atomic_add_affected_connectors [drm		 Adding all current connectors for [CRTC:46:pipe B	 to ffff9f5a457af400	
> [drm:drm_atomic_helper_check_modeset [drm_kms_helper		 [CRTC:56:pipe C	 needs all connectors, enable: n, active: n	
> [drm:drm_atomic_add_affected_connectors [drm		 Adding all current connectors for [CRTC:56:pipe C	 to ffff9f5a457af400	
> [drm:drm_atomic_add_affected_connectors [drm		 Adding all current connectors for [CRTC:36:pipe A	 to ffff9f5a457af400	
> [drm:intel_atomic_check [i915		 [CONNECTOR:67:HDMI-A-2	 checking for sink bpp constrains	
> [drm:intel_atomic_check [i915		 clamping display bpp (was 36) to default limit of 24		
> [drm:intel_hdmi_compute_config [i915		 picking bpc to 8 for HDMI output		
> [drm:intel_hdmi_compute_config [i915		 forcing pipe bpp to 24 for HDMI		
> [drm:intel_atomic_check [i915		 hw max bpp: 36, pipe bpp: 24, dithering: 0		
> [drm:intel_dump_pipe_config [i915		 [CRTC:36:pipe A	[modeset	
> [drm:intel_dump_pipe_config [i915		 cpu_transcoder: A, pipe bpp: 24, dithering: 0		
> [drm:intel_dump_pipe_config [i915		 audio: 0, infoframes: 0		
> [drm:intel_dump_pipe_config [i915		 requested mode:		
> [drm:drm_mode_debug_printmodeline [drm		 Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9		
> [drm:intel_dump_pipe_config [i915		 adjusted mode:		
> [drm:drm_mode_debug_printmodeline [drm		 Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9		
> [drm:intel_dump_pipe_config [i915		 crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9		
> [drm:intel_dump_pipe_config [i915		 port clock: 154000, pipe src size: 1920x1200, pixel rate 154000		
> [drm:intel_dump_pipe_config [i915		 pch pfit: pos: 0x00000000, size: 0x00000000, disabled		
> [drm:intel_dump_pipe_config [i915		 ips: 1, double wide: 0		
> [drm:hsw_dump_hw_state [i915		 dpll_hw_state: wrpll: 0xb035061f spll: 0x0		
> [drm:intel_dump_pipe_config [i915		 planes on this crtc		
> [drm:intel_dump_pipe_config [i915		 [PLANE:27:primary A	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [PLANE:30:sprite A	 disabled, scaler_id = 0	
> [drm:intel_dump_pipe_config [i915		 [PLANE:33:cursor A	 disabled, scaler_id = 0	
> [drm:intel_atomic_check [i915		 New cdclk calculated to be logical 337500 kHz, actual 337500 kHz		
> [drm:intel_plane_atomic_calc_changes [i915		 [CRTC:36:pipe A	 has [PLANE:27:primary A	 with fb 84
> [drm:intel_plane_atomic_calc_changes [i915		 [PLANE:27:primary A	 visible 0 -> 1, off 0, on 1, ms 1	
> [drm:intel_plane_atomic_calc_changes [i915		 [CRTC:36:pipe A	 has [PLANE:33:cursor A	 with fb 83
> [drm:intel_plane_atomic_calc_changes [i915		 [PLANE:33:cursor A	 visible 0 -> 1, off 0, on 1, ms 1	
> [drm:intel_find_shared_dpll [i915		 [CRTC:36:pipe A	 allocated WRPLL 1	
> [drm:intel_reference_shared_dpll [i915		 using WRPLL 1 for pipe A		
> [drm:drm_atomic_commit [drm		 committing ffff9f5a457af400		
> [drm:intel_set_cdclk [i915		 Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz		
> bdw_set_cdclk ENTER				
> wait FCLK done timeout: 10000 base: 4121326546607 time: 199				
> [drm:intel_update_cdclk [i915		 Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz		
> bdw_set_cdclk EXIT				
>

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Attachments on bug 102243: 133739 | 133741 | 133742 | 133743 | 133744 | 133746

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