Attachment 134369 Details for Bug 102901 – Dmesg 4/4

Dmesg 4/4

KmsFlip2xVblankVsSuspendInterruptible-dmesg (text/plain), 1.03 MB, created by Hector Velazquez on 2017-09-20 14:57:44 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Hector Velazquez

Created: 2017-09-20 14:57:44 UTC

Size: 1.03 MB

patch

obsolete

>[    8.075020] pci 0000:01:00.0: reg 0x18: [mem 0xa1104000-0xa1104fff 64bit]
>[    8.075055] pci 0000:01:00.0: reg 0x20: [mem 0xa1100000-0xa1103fff 64bit]
>[    8.075091] pci 0000:01:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug
>[    8.075559] pci 0000:01:00.0: supports D1 D2
>[    8.075567] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    8.077814] pci 0000:00:13.0: PCI bridge to [bus 01]
>[    8.077827] pci 0000:00:13.0:   bridge window [io  0x1000-0x1fff]
>[    8.077840] pci 0000:00:13.0:   bridge window [mem 0xa1100000-0xa11fffff]
>[    8.077874] pci_bus 0000:00: on NUMA node 0
>[    8.673667] ACPI: PCI Interrupt Link [LNKA] (IRQs *3 4 5 6 10 11 12 14 15)
>[    8.679682] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 *4 5 6 10 11 12 14 15)
>[    8.685900] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15)
>[    8.691785] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 *6 10 11 12 14 15)
>[    8.697786] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 15) *7
>[    8.703768] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 15) *9
>[    8.709774] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 *10 11 12 14 15)
>[    8.715766] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    8.776917] ACPI: EC: interrupt unblocked
>[    8.776951] ACPI: EC: event unblocked
>[    8.777000] ACPI: \_SB_.PCI0.LPCB.H_EC: GPE=0x25, EC_CMD/EC_SC=0x66, EC_DATA=0x62
>[    8.777139] ACPI: \_SB_.PCI0.LPCB.H_EC: Used as boot DSDT EC to handle transactions and events
>[    8.781308] pci 0000:00:02.0: vgaarb: setting as boot VGA device
>[    8.781320] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
>[    8.781395] pci 0000:00:02.0: vgaarb: bridge control possible
>[    8.781402] vgaarb: loaded
>[    8.785701] SCSI subsystem initialized
>[    8.787390] libata version 3.00 loaded.
>[    8.787423] ACPI: bus type USB registered
>[    8.788080] usbcore: registered new interface driver usbfs
>[    8.788429] usbcore: registered new interface driver hub
>[    8.789035] usbcore: registered new device driver usb
>[    8.791465] Registered efivars operations
>[    8.801874] Advanced Linux Sound Architecture Driver Initialized.
>[    8.802301] PCI: Using ACPI for IRQ routing
>[    8.813419] PCI: pci_cache_line_size set to 64 bytes
>[    8.813773] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>[    8.813849] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
>[    8.813886] e820: reserve RAM buffer [mem 0x76bc2000-0x77ffffff]
>[    8.813921] e820: reserve RAM buffer [mem 0x7ac00000-0x7bffffff]
>[    8.818394] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>[    8.818455] hpet0: 8 comparators, 64-bit 19.200000 MHz counter
>[    8.820215] clocksource: Switched to clocksource hpet
>[    9.263728] pnp: PnP ACPI init
>[    9.269782] system 00:00: [io  0x06a4] has been reserved
>[    9.269826] system 00:00: [io  0x06a0] has been reserved
>[    9.269940] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    9.287630] pnp 00:01: disabling [io  0x164e-0x164f] because it overlaps 0000:00:13.0 BAR 7 [io  0x1000-0x1fff]
>[    9.288597] system 00:01: [io  0x0680-0x069f] has been reserved
>[    9.288641] system 00:01: [io  0x0400-0x047f] has been reserved
>[    9.288685] system 00:01: [io  0x0500-0x05fe] has been reserved
>[    9.288729] system 00:01: [io  0x0600-0x061f] has been reserved
>[    9.288820] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    9.292565] pnp 00:02: Plug and Play ACPI device, IDs PNP0303 (active)
>[    9.297498] pnp 00:03: Plug and Play ACPI device, IDs PNP0f13 (active)
>[    9.568288] system 00:04: [mem 0xe0000000-0xefffffff] could not be reserved
>[    9.568331] system 00:04: [mem 0xfea00000-0xfeafffff] has been reserved
>[    9.568372] system 00:04: [mem 0xfed01000-0xfed01fff] has been reserved
>[    9.568412] system 00:04: [mem 0xfed03000-0xfed03fff] has been reserved
>[    9.568451] system 00:04: [mem 0xfed06000-0xfed06fff] has been reserved
>[    9.568492] system 00:04: [mem 0xfed08000-0xfed09fff] has been reserved
>[    9.568532] system 00:04: [mem 0xfed80000-0xfedbffff] has been reserved
>[    9.568572] system 00:04: [mem 0xfed1c000-0xfed1cfff] has been reserved
>[    9.568611] system 00:04: [mem 0xfee00000-0xfeefffff] has been reserved
>[    9.568708] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    9.590426] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active)
>[    9.619159] pnp: PnP ACPI: found 6 devices
>[    9.686058] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
>[    9.686113] pci 0000:00:13.0: PCI bridge to [bus 01]
>[    9.686126] pci 0000:00:13.0:   bridge window [io  0x1000-0x1fff]
>[    9.686142] pci 0000:00:13.0:   bridge window [mem 0xa1100000-0xa11fffff]
>[    9.686168] pci_bus 0000:00: resource 4 [io  0x0070-0x0077]
>[    9.686177] pci_bus 0000:00: resource 5 [io  0x0000-0x006f window]
>[    9.686184] pci_bus 0000:00: resource 6 [io  0x0078-0x0cf7 window]
>[    9.686191] pci_bus 0000:00: resource 7 [io  0x0d00-0xffff window]
>[    9.686199] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window]
>[    9.686207] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window]
>[    9.686215] pci_bus 0000:00: resource 10 [mem 0x000e0000-0x000fffff window]
>[    9.686222] pci_bus 0000:00: resource 11 [mem 0x7c000001-0x7fffffff window]
>[    9.686230] pci_bus 0000:00: resource 12 [mem 0x80000000-0xbfffffff window]
>[    9.686237] pci_bus 0000:00: resource 13 [mem 0xe0000000-0xefffffff window]
>[    9.686244] pci_bus 0000:00: resource 14 [mem 0xfea00000-0xfeafffff window]
>[    9.686252] pci_bus 0000:00: resource 15 [mem 0xfed00000-0xfed003ff window]
>[    9.686259] pci_bus 0000:00: resource 16 [mem 0xfed01000-0xfed01fff window]
>[    9.686266] pci_bus 0000:00: resource 17 [mem 0xfed03000-0xfed03fff window]
>[    9.686274] pci_bus 0000:00: resource 18 [mem 0xfed06000-0xfed06fff window]
>[    9.686281] pci_bus 0000:00: resource 19 [mem 0xfed08000-0xfed09fff window]
>[    9.686288] pci_bus 0000:00: resource 20 [mem 0xfed80000-0xfedbffff window]
>[    9.686296] pci_bus 0000:00: resource 21 [mem 0xfed1c000-0xfed1cfff window]
>[    9.686303] pci_bus 0000:00: resource 22 [mem 0xfee00000-0xfeefffff window]
>[    9.686311] pci_bus 0000:01: resource 0 [io  0x1000-0x1fff]
>[    9.686318] pci_bus 0000:01: resource 1 [mem 0xa1100000-0xa11fffff]
>[    9.699774] NET: Registered protocol family 2
>[    9.703538] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
>[    9.704780] TCP bind hash table entries: 32768 (order: 9, 2359296 bytes)
>[    9.709585] TCP: Hash tables configured (established 65536 bind 32768)
>[    9.710474] UDP hash table entries: 4096 (order: 7, 655360 bytes)
>[    9.711746] UDP-Lite hash table entries: 4096 (order: 7, 655360 bytes)
>[    9.714088] NET: Registered protocol family 1
>[    9.714247] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
>[    9.729973] PCI: CLS 64 bytes, default 64
>[    9.732133] Unpacking initramfs...
>[   10.331650] Freeing initrd memory: 11344K
>[   10.331663] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[   10.331673] software IO TLB [mem 0x6ec00000-0x72c00000] (64MB) mapped at [ffff88006ec00000-ffff880072bfffff]
>[   10.331952] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x159647815e3, max_idle_ns: 440795269835 ns
>[   10.360376] workingset: timestamp_bits=46 max_order=21 bucket_order=0
>[   10.467519] ntfs: driver 2.1.32 [Flags: R/O].
>[   10.536711] NET: Registered protocol family 38
>[   10.537935] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
>[   10.537958] io scheduler noop registered
>[   10.539795] io scheduler cfq registered (default)
>[   10.539803] io scheduler mq-deadline registered
>[   10.539811] io scheduler kyber registered
>[   10.555861] pcieport 0000:00:13.0: Signaling PME with IRQ 120
>[   11.336855] clocksource: Switched to clocksource tsc
>[   15.840125] uvesafb: Getting VBE info block failed (eax=0x4f00, err=1)
>[   15.840207] uvesafb: vbe_init() failed with -22
>[   15.840369] uvesafb: probe of uvesafb.0 failed with error -22
>[   15.840811] intel_idle: MWAIT substates: 0x11242020
>[   15.840818] intel_idle: v0.4.1 model 0x7A
>[   15.848818] intel_idle: lapic_timer_reliable_states 0xffffffff
>[   15.851781] ACPI: AC Adapter [ADP1] (off-line)
>[   15.874840] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:01/PNP0C09:00/PNP0C0D:00/input/input0
>[   15.894498] ACPI: Lid Switch [LID0]
>[   15.896099] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
>[   15.896316] ACPI: Power Button [PWRB]
>[   15.899254] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
>[   15.899437] ACPI: Power Button [PWRF]
>[   16.044937] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info().
>[   16.155476] thermal LNXTHERM:00: registered as thermal_zone0
>[   16.155486] ACPI: Thermal Zone [TZ01] (41 C)
>[   16.158540] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
>[   16.166580] ACPI: Battery Slot [BAT0] (battery present)
>[   16.168927] ACPI: Battery Slot [BAT1] (battery absent)
>[   16.182779] serial8250: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
>[   16.194795] Non-volatile memory driver v1.3
>[   16.196660] Linux agpgart interface v0.103
>[   16.206701] loop: module loaded
>[   16.210844] ahci 0000:00:12.0: version 3.0
>[   16.228310] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
>[   16.228324] ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst 
>[   16.234290] scsi host0: ahci
>[   16.236855] ata1: SATA max UDMA/133 abar m2048@0xa123b000 port 0xa123b100 irq 121
>[   16.237985] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[   16.238094] ehci-pci: EHCI PCI platform driver
>[   16.238386] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>[   16.238438] ohci-pci: OHCI PCI platform driver
>[   16.238719] uhci_hcd: USB Universal Host Controller Interface driver
>[   16.247090] xhci_hcd 0000:00:15.0: xHCI Host Controller
>[   16.247321] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1
>[   16.249520] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810
>[   16.249541] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported
>[   16.251895] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[   16.251909] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[   16.251917] usb usb1: Product: xHCI Host Controller
>[   16.251924] usb usb1: Manufacturer: Linux 4.14.0-rc1-drm-tip-ww38-commit-ab2e3a0+ xhci-hcd
>[   16.251931] usb usb1: SerialNumber: 0000:00:15.0
>[   16.256925] hub 1-0:1.0: USB hub found
>[   16.257400] hub 1-0:1.0: 9 ports detected
>[   16.398461] xhci_hcd 0000:00:15.0: xHCI Host Controller
>[   16.398550] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2
>[   16.400212] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>[   16.400223] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[   16.400230] usb usb2: Product: xHCI Host Controller
>[   16.400237] usb usb2: Manufacturer: Linux 4.14.0-rc1-drm-tip-ww38-commit-ab2e3a0+ xhci-hcd
>[   16.400244] usb usb2: SerialNumber: 0000:00:15.0
>[   16.404913] hub 2-0:1.0: USB hub found
>[   16.405852] hub 2-0:1.0: 7 ports detected
>[   16.509114] usbcore: registered new interface driver usb-storage
>[   16.510527] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
>[   16.511542] i8042: Warning: Keylock active
>[   16.513416] serio: i8042 KBD port at 0x60,0x64 irq 1
>[   16.514618] serio: i8042 AUX port at 0x60,0x64 irq 12
>[   16.516664] mousedev: PS/2 mouse device common for all mice
>[   16.521547] rtc_cmos 00:05: RTC can wake from S4
>[   16.522250] rtc rtc0: invalid alarm value: 16526-1--3027 126462925:-1002158980:32
>[   16.523306] rtc_cmos 00:05: rtc core: registered rtc_cmos as rtc0
>[   16.523485] rtc_cmos 00:05: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>[   16.523825] IR NEC protocol handler initialized
>[   16.523834] IR RC5(x/sz) protocol handler initialized
>[   16.523841] IR RC6 protocol handler initialized
>[   16.523848] IR JVC protocol handler initialized
>[   16.523855] IR Sony protocol handler initialized
>[   16.523863] IR SANYO protocol handler initialized
>[   16.523870] IR Sharp protocol handler initialized
>[   16.523878] IR MCE Keyboard/mouse protocol handler initialized
>[   16.523885] IR XMP protocol handler initialized
>[   16.525864] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0)
>[   16.529288] device-mapper: uevent: version 1.0.3
>[   16.532080] device-mapper: ioctl: 4.36.0-ioctl (2017-06-09) initialised: dm-devel@redhat.com
>[   16.532097] intel_pstate: Intel P-state driver initializing
>[   16.546483] EFI Variables Facility v0.08 2004-May-17
>[   16.565910] hidraw: raw HID events driver (C) Jiri Kosina
>[   16.567498] usbcore: registered new interface driver usbhid
>[   16.567501] usbhid: USB HID core driver
>[   16.568585] intel_rapl: Found RAPL domain package
>[   16.568596] intel_rapl: Found RAPL domain core
>[   16.568601] intel_rapl: Found RAPL domain uncore
>[   16.568606] intel_rapl: Found RAPL domain dram
>[   16.572357] Initializing XFRM netlink socket
>[   16.575867] NET: Registered protocol family 10
>[   16.579732] Segment Routing with IPv6
>[   16.579840] mip6: Mobile IPv6
>[   16.579857] NET: Registered protocol family 17
>[   16.579905] NET: Registered protocol family 15
>[   16.579910] start plist test
>[   16.581257] end plist test
>[   16.584084] SSE version of gcm_enc/dec engaged.
>[   16.697128] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[   16.698159] alg: No test for pcbc(aes) (pcbc-aes-aesni)
>[   16.698258] sched_clock: Marking stable (16698175326, 0)->(16822085953, -123910627)
>[   16.700134] ata1.00: ATA-10: INTEL SSDSC2BW120H6, RG20, max UDMA/133
>[   16.700140] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>[   16.701236] registered taskstats version 1
>[   16.701700] kmemleak: Kernel memory leak detector initialized
>[   16.701734] kmemleak: Automatic memory scanning thread started
>[   16.712910] Btrfs loaded, crc32c=crc32c-generic
>[   16.713447] ata1.00: configured for UDMA/133
>[   16.715351] scsi 0:0:0:0: Direct-Access     ATA      INTEL SSDSC2BW12 RG20 PQ: 0 ANSI: 5
>[   16.719253] sd 0:0:0:0: Attached scsi generic sg0 type 0
>[   16.719584] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB)
>[   16.720120] sd 0:0:0:0: [sda] Write Protect is off
>[   16.720125] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[   16.720424] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[   16.724056] usb 1-4: new low-speed USB device number 2 using xhci_hcd
>[   16.726834]  sda: sda1 sda2 sda3
>[   16.732152] sd 0:0:0:0: [sda] Attached SCSI disk
>[   16.734467] rtc_cmos 00:05: setting system clock to 16517-09-16 20:18:00 UTC (459081375480)
>[   16.736431] PM: Image not found (code -22)
>[   16.736447] ALSA device list:
>[   16.736451]   No soundcards found.
>[   16.741614] Freeing unused kernel memory: 1764K
>[   16.741619] Write protecting the kernel read-only data: 14336k
>[   16.743801] Freeing unused kernel memory: 1176K
>[   16.744068] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[   16.746261] Freeing unused kernel memory: 472K
>[   16.860580] usb 1-4: New USB device found, idVendor=03f0, idProduct=0024
>[   16.860589] usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[   16.860594] usb 1-4: Product: HP Basic USB Keyboard
>[   16.860599] usb 1-4: Manufacturer: CHICONY
>[   16.871024] input: CHICONY HP Basic USB Keyboard as /devices/pci0000:00/0000:00:15.0/usb1/1-4/1-4:1.0/0003:03F0:0024.0001/input/input4
>[   16.926625] hid-generic 0003:03F0:0024.0001: input,hidraw0: USB HID v1.10 Keyboard [CHICONY HP Basic USB Keyboard] on usb-0000:00:15.0-4/input0
>[   17.042094] usb 1-8: new low-speed USB device number 3 using xhci_hcd
>[   17.120106] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[   17.120981] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3
>[   17.175217] usb 1-8: New USB device found, idVendor=046d, idProduct=c018
>[   17.175224] usb 1-8: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[   17.175229] usb 1-8: Product: USB Optical Mouse
>[   17.175233] usb 1-8: Manufacturer: Logitech
>[   17.181575] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:15.0/usb1/1-8/1-8:1.0/0003:046D:C018.0002/input/input6
>[   17.184295] hid-generic 0003:046D:C018.0002: input,hidraw1: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:15.0-8/input0
>[   17.738293] Setting dangerous option enable_guc_submission - tainting kernel
>[   17.738303] Setting dangerous option enable_guc_loading - tainting kernel
>[   17.738308] Setting dangerous option alpha_support - tainting kernel
>[   17.742641] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
>[   17.742798] r8169 0000:01:00.0: enabling device (0000 -> 0003)
>[   17.753853] [drm:i915_driver_load [i915]] No PCH found.
>[   17.753905] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>[   17.760037] [drm:intel_device_info_dump [i915]] i915 device info: platform=GEMINILAKE gen=9 pciid=0x3184 rev=0x03
>[   17.760130] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[   17.760171] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>[   17.760210] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[   17.760249] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[   17.760288] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[   17.760326] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[   17.760364] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[   17.760402] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[   17.760440] [drm:intel_device_info_dump [i915]] i915 device info: has_reset_engine: yes
>[   17.760478] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[   17.760515] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[   17.760552] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[   17.760589] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[   17.760627] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[   17.760663] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[   17.760701] [drm:intel_device_info_dump [i915]] i915 device info: has_guc_ct: no
>[   17.760738] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[   17.760775] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[   17.760812] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>[   17.760849] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[   17.760886] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[   17.760923] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[   17.760960] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[   17.760997] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>[   17.761104] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[   17.761141] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[   17.761178] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[   17.761215] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[   17.761252] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: yes
>[   17.761288] [drm:intel_device_info_dump [i915]] i915 device info: unfenced_needs_alignment: no
>[   17.761325] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[   17.761362] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[   17.761504] sdhci: Secure Digital Host Controller Interface driver
>[   17.761508] sdhci: Copyright(c) Pierre Ossman
>[   17.762794] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[   17.762832] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[   17.762870] [drm:intel_device_info_dump [i915]] i915 device info: has_ipc: yes
>[   17.766265] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[   17.766309] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[   17.766351] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[   17.766392] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[   17.766432] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[   17.766470] [drm:intel_device_info_runtime_init [i915]] EU total: 18
>[   17.766508] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6
>[   17.766546] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[   17.766583] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y
>[   17.766619] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[   17.766659] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[   17.766697] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[   17.766805] [drm] Memory usable by graphics device = 4078M
>[   17.766848] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[   17.766889] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[   17.766937] [drm] Replacing VGA console driver
>[   17.767450] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 57344K
>[   17.767506] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4
>[   17.767625] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x799eb018
>[   17.767727] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[   17.767771] [drm:intel_opregion_setup [i915]] ASLE supported
>[   17.767861] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[   17.768487] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[   17.768515] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[   17.768519] [drm] Driver supports precise vblank timestamp query.
>[   17.768565] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz
>[   17.768611] [drm:intel_bios_init [i915]] VBT signature "$VBT GEMINILAKE     ", BDB version 212
>[   17.768656] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[   17.770508] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[   17.770555] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19)
>[   17.770600] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[   17.770644] [drm:intel_bios_init [i915]] DRRS supported mode is seamless
>[   17.770700] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[   17.770710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[   17.770752] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[   17.770795] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180, controller 0
>[   17.770837] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[   17.770879] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 212 not known; assuming 38
>[   17.770936] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[   17.770979] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[   17.771021] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[   17.771086] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[   17.771128] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[   17.771169] [drm:intel_bios_init [i915]] Port C VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[   17.771210] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[   17.771669] r8169 0000:01:00.0 eth0: RTL8168h/8111h at 0xffffc90000010000, 90:49:fa:02:af:4f, XID 14100800 IRQ 123
>[   17.771674] r8169 0000:01:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko]
>[   17.772872] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[   17.772945] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[   17.773899] [drm:intel_power_well_enable [i915]] enabling power well 1
>[   17.773965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[   17.775201] [drm:intel_power_well_enable [i915]] enabling always-on
>[   17.775242] [drm:intel_power_well_enable [i915]] enabling DC off
>[   17.775284] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[   17.775339] [drm:intel_power_well_enable [i915]] enabling power well 2
>[   17.775365] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem
>[   17.775452] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[   17.775770] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[   17.775859] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[   17.775899] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[   17.776111] [drm:intel_power_well_enable [i915]] enabling AUX A
>[   17.776154] [drm:intel_power_well_enable [i915]] enabling AUX B
>[   17.776196] [drm:intel_power_well_enable [i915]] enabling AUX C
>[   17.776313] [drm:intel_csr_ucode_init [i915]] Loading i915/glk_dmc_ver1_04.bin
>[   17.776894] i915 0000:00:02.0: Direct firmware load for i915/glk_dmc_ver1_04.bin failed with error -2
>[   17.776951] i915 0000:00:02.0: Failed to load DMC firmware [https://01.org/linuxgraphics/downloads/firmware], disabling runtime power management.
>[   17.777792] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1b001819 hp_port:38
>[   17.781750] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[   17.781812] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec)
>[   17.781852] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec)
>[   17.781890] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec)
>[   17.781928] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec)
>[   17.781966] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec)
>[   17.782004] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec)
>[   17.782057] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec)
>[   17.782095] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec)
>[   17.782141] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[   17.784808] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[   17.784876] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 316800 kHz
>[   17.784919] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 627264 kHz
>[   17.785355] [drm:intel_ddi_init [i915]] BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing
>[   17.785432] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[   17.785543] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[   17.785639] [drm:intel_pps_dump_state [i915]] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 6000
>[   17.785686] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 6000
>[   17.785729] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 600
>[   17.785772] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[   17.785823] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[   17.785914] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[   17.785959] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[   17.868629] r8169 0000:01:00.0 enp1s0: renamed from eth0
>[   18.400734] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000062
>[   18.400835] [drm:wait_panel_status [i915]] Wait complete
>[   18.400935] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x0000006a
>[   18.401027] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[   18.609603] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[   18.610341] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[   18.611069] [drm:intel_dp_init_connector [i915]] Detected EDP PSR Panel.
>[   18.611841] [drm:intel_dp_init_connector [i915]] EDP DPCD : 02 fb e7
>[   18.618597] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   18.618900] [drm:intel_dp_init_connector [i915]] Downclock mode is not found. DRRS not supported
>[   18.619084] [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, disabled, brightness 0/96000
>[   18.619588] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[   18.619651] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[   18.619857] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[   18.619916] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port B (VBT)
>[   18.620088] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[   18.620156] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port C (VBT)
>[   18.620198] [drm:intel_dsi_init [i915]] 
>[   18.620397] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x1
>[   18.620446] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe A] hw state readout: enabled
>[   18.620507] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[   18.620551] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:58:pipe B] hw state readout: disabled
>[   18.620608] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[   18.620651] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:74:pipe C] hw state readout: disabled
>[   18.620702] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[   18.620786] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000001, on 1
>[   18.620833] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[   18.620880] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:75:DDI A] hw state readout: disabled, pipe A
>[   18.620951] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:83:DDI B] hw state readout: enabled, pipe A
>[   18.620995] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:85:DP-MST A] hw state readout: disabled, pipe A
>[   18.621037] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:86:DP-MST B] hw state readout: disabled, pipe B
>[   18.621098] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:87:DP-MST C] hw state readout: disabled, pipe C
>[   18.621144] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:90:DDI C] hw state readout: disabled, pipe A
>[   18.621226] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:76:eDP-1] hw state readout: disabled
>[   18.621284] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:84:DP-1] hw state readout: enabled
>[   18.621337] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:88:HDMI-A-1] hw state readout: disabled
>[   18.621386] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:91:HDMI-A-2] hw state readout: disabled
>[   18.621479] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[   18.621629] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][setup_hw_state]
>[   18.621673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[   18.621715] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   18.621756] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   18.621763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 105 270000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[   18.621804] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   18.621809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 105 270000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[   18.621851] [drm:intel_dump_pipe_config [i915]] crtc timings: 270000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x40 flags: 0x9
>[   18.621892] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1200, pixel rate 270000
>[   18.621933] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   18.621974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   18.622015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   18.622081] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   18.622122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   18.622165] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[   18.622208] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[   18.622252] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[   18.622295] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[   18.622337] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[   18.622381] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][setup_hw_state]
>[   18.622421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[   18.622460] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   18.622500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   18.622505] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[   18.622545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   18.622550] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[   18.622590] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[   18.622630] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[   18.622669] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   18.622709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   18.622748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   18.622791] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[   18.622830] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   18.622873] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[   18.622916] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[   18.622958] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[   18.623000] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[   18.623058] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[   18.623115] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][setup_hw_state]
>[   18.623154] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[   18.623193] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   18.623232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   18.623238] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[   18.623276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   18.623282] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[   18.623321] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[   18.623360] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[   18.623399] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   18.623439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   18.623478] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   18.623520] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[   18.623559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   18.623598] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[   18.623640] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[   18.623683] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[   18.623725] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[   18.623767] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[   18.624140] [drm:skylake_get_initial_plane_config [i915]] pipe A with fb: size=1920x1200@32, offset=0, pitch 7680, size 0x8ca000
>[   18.624191] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=8ca000
>[   18.624268] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] failed to allocate stolen space
>[   18.624384] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[   18.624433] [drm:fetch_uc_fw [i915]] before requesting firmware: uC fw fetch status PENDING
>[   18.624855] i915 0000:00:02.0: Direct firmware load for i915/glk_huc_ver02_00_1748.bin failed with error -2
>[   18.624887] [drm] Failed to fetch valid uC firmware from i915/glk_huc_ver02_00_1748.bin (error -2)
>[   18.624933] [drm:fetch_uc_fw [i915]] uC fw fetch status FAIL; err -2, fw           (null), obj           (null)
>[   18.624974] [drm:fetch_uc_fw [i915]] before requesting firmware: uC fw fetch status PENDING
>[   18.625313] i915 0000:00:02.0: Direct firmware load for i915/glk_guc_ver10_56.bin failed with error -2
>[   18.625342] [drm] Failed to fetch valid uC firmware from i915/glk_guc_ver10_56.bin (error -2)
>[   18.625384] [drm:fetch_uc_fw [i915]] uC fw fetch status FAIL; err -2, fw           (null), obj           (null)
>[   18.626386] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, fee00000]
>[   18.626565] [drm:i915_gem_contexts_init [i915]] logical context support initialized
>[   18.626769] [drm:intel_engine_create_scratch [i915]] rcs0 pipe control offset: 0xfedff000
>[   18.627976] [drm:intel_engine_init_common [i915]] rcs0 hws offset: 0x00001000
>[   18.628719] [drm:intel_engine_init_common [i915]] bcs0 hws offset: 0x00002000
>[   18.629450] [drm:intel_engine_init_common [i915]] vcs0 hws offset: 0x00003000
>[   18.630274] [drm:intel_engine_init_common [i915]] vecs0 hws offset: 0x00004000
>[   18.630453] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0
>[   18.630512] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 12
>[   18.630627] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0
>[   18.630745] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0
>[   18.630861] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0
>[   18.633350] [drm:intel_huc_init_hw [i915]] i915/glk_huc_ver02_00_1748.bin fw status: fetch FAIL, load NONE
>[   18.633395] [drm:intel_guc_init_hw [i915]] GuC fw status: path i915/glk_guc_ver10_56.bin, fetch FAIL, load NONE
>[   18.633523] [drm:intel_uc_init_hw [i915]] *ERROR* GuC init failed
>[   18.633546] [drm] Falling back from GuC submission to execlist mode
>[   18.633550] [drm] GuC firmware loading disabled
>[   18.633597] [drm:i915_gem_init [i915]] *ERROR* Failed to initialize GPU, declaring it wedged
>[   18.634421] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[   18.634465] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[   18.634507] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[   18.634552] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[   18.634776] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1a001818 hp_port:38
>[   18.638785] [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered
>[   18.638923] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1
>[   18.640763] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[   18.642995] [drm] Initialized i915 1.6.0 20170907 for 0000:00:02.0 on minor 0
>[   18.646723] [drm:intel_opregion_register [i915]] 4 outputs detected
>[   18.689154] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[   18.699896] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input8
>[   18.701821] [drm] DRM_I915_DEBUG enabled
>[   18.701826] [drm] DRM_I915_DEBUG_GEM enabled
>[   18.701901] [drm:drm_setup_crtcs] 
>[   18.701967] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[   18.702042] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[   18.702118] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   18.702162] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[   18.702201] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   18.702240] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   18.702692] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:31cc] (rev 3)
>[   18.702800] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[   18.704261] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] status updated from unknown to connected
>[   18.704471] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   18.704500] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[   18.704510] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[   18.704516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[   18.704584] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[   18.705602] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[   18.707104] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   18.707150] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[   18.707194] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   18.707238] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   18.708430] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[   18.708476] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[   18.714908] mmc0: SDHCI controller on PCI [0000:00:1c.0] using ADMA 64-bit
>[   18.715352] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:31d0] (rev 3)
>[   18.715865] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] status updated from unknown to connected
>[   18.716165] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   18.716227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[   18.716234] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   18.716240] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   18.716245] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   18.716250] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[   18.716255] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   18.716260] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   18.716266] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   18.716271] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   18.716276] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   18.716281] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   18.716289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[   18.716353] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[   18.718119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   18.718167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   18.720135] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   18.720144] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   18.721512] mmc1: SDHCI controller on PCI [0000:00:1e.0] using ADMA 64-bit
>[   18.722119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   18.722167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   18.724088] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   18.724099] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   18.724107] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] status updated from unknown to disconnected
>[   18.724113] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[   18.724121] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[   18.724168] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[   18.802659] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   18.802782] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   18.805246] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   18.805280] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   18.805302] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   18.805322] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] status updated from unknown to connected
>[   18.805412] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[   18.805427] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[   18.808147] [drm:drm_edid_to_eld] ELD monitor S277HK
>[   18.808165] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[   18.808179] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[   18.809774] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[   18.809794] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[   18.809811] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   18.809827] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   18.809842] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   18.809858] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   18.809873] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[   18.809888] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[   18.809904] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[   18.809919] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[   18.809934] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[   18.809950] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   18.809965] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   18.809981] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   18.809996] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   18.810061] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   18.810077] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   18.810093] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   18.810108] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   18.810124] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   18.810139] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   18.810154] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   18.810170] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   18.810185] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   18.810201] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   18.810216] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   18.810232] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   18.810247] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   18.810262] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   18.810278] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   18.810293] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   18.810308] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   18.810324] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   18.810339] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   18.810354] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   18.810369] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   18.810385] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   18.810400] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[   18.810415] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   18.810431] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   18.810446] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[   18.810461] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[   18.810477] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   18.810492] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   18.810507] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   18.810522] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   18.810538] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   18.810553] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   18.810572] [drm:drm_setup_crtcs] connector 76 enabled? yes
>[   18.810586] [drm:drm_setup_crtcs] connector 84 enabled? yes
>[   18.810600] [drm:drm_setup_crtcs] connector 88 enabled? no
>[   18.810613] [drm:drm_setup_crtcs] connector 91 enabled? yes
>[   18.810896] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[   18.811337] [drm:drm_setup_crtcs] looking for cmdline mode on connector 76
>[   18.811352] [drm:drm_setup_crtcs] looking for preferred mode on connector 76 0
>[   18.811365] [drm:drm_setup_crtcs] found mode 1920x1080
>[   18.811378] [drm:drm_setup_crtcs] looking for cmdline mode on connector 84
>[   18.811391] [drm:drm_setup_crtcs] looking for preferred mode on connector 84 0
>[   18.811405] [drm:drm_setup_crtcs] found mode 1920x1200
>[   18.811418] [drm:drm_setup_crtcs] looking for cmdline mode on connector 91
>[   18.811430] [drm:drm_setup_crtcs] looking for preferred mode on connector 91 0
>[   18.811443] [drm:drm_setup_crtcs] found mode 3840x2160
>[   18.811456] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[   18.812485] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0)
>[   18.812546] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 58 (0,0)
>[   18.812591] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 74 (0,0)
>[   18.813025] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[   18.854295] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x000c0000
>[   18.854391] [drm:drm_fb_helper_hotplug_event.part.18] 
>[   18.854452] [drm:drm_setup_crtcs] 
>[   18.854534] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[   18.854601] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[   18.854666] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   18.854712] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[   18.854755] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   18.854875] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   18.855444] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[   18.855551] fbcon: inteldrmfb (fb0) is primary device
>[   18.856453] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   18.856480] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[   18.856487] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[   18.856491] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[   18.856537] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[   18.857521] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[   18.858372] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   18.858413] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[   18.858453] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   18.858492] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   18.859549] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[   18.859588] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[   18.867308] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   18.867460] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[   18.867464] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   18.867467] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   18.867471] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   18.867474] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[   18.867477] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   18.867480] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   18.867484] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   18.867487] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   18.867490] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   18.867493] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   18.867498] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[   18.867544] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[   18.869122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   18.869166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   18.871105] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   18.871113] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   18.873179] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   18.873220] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   18.875432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   18.875443] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   18.875448] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[   18.875453] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[   18.875504] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[   18.951328] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   18.951380] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   18.953608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   18.953614] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   18.953621] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   18.953666] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[   18.953670] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[   18.955059] [drm:drm_edid_to_eld] ELD monitor S277HK
>[   18.955067] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[   18.955071] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[   18.956686] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[   18.956693] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[   18.956698] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   18.956703] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   18.956709] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   18.956714] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   18.956719] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[   18.956724] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[   18.956729] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[   18.956734] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[   18.956739] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[   18.956744] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   18.956749] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   18.956754] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   18.956760] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   18.956765] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   18.956770] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   18.956775] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   18.956780] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   18.956785] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   18.956790] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   18.956795] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   18.956800] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   18.956805] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   18.956810] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   18.956816] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   18.956821] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   18.956826] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   18.956831] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   18.956836] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   18.956841] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   18.956846] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   18.956851] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   18.956856] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   18.956861] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   18.956866] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   18.956871] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   18.956876] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[   18.956881] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   18.956886] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   18.956891] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[   18.956897] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[   18.956902] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   18.956907] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   18.956912] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   18.956917] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   18.956922] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   18.956927] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   18.956932] [drm:drm_setup_crtcs] connector 76 enabled? yes
>[   18.956936] [drm:drm_setup_crtcs] connector 84 enabled? yes
>[   18.956940] [drm:drm_setup_crtcs] connector 88 enabled? no
>[   18.956943] [drm:drm_setup_crtcs] connector 91 enabled? yes
>[   18.957117] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[   18.957225] [drm:drm_setup_crtcs] looking for cmdline mode on connector 76
>[   18.957229] [drm:drm_setup_crtcs] looking for preferred mode on connector 76 0
>[   18.957233] [drm:drm_setup_crtcs] found mode 1920x1080
>[   18.957237] [drm:drm_setup_crtcs] looking for cmdline mode on connector 84
>[   18.957241] [drm:drm_setup_crtcs] looking for preferred mode on connector 84 0
>[   18.957245] [drm:drm_setup_crtcs] found mode 1920x1200
>[   18.957248] [drm:drm_setup_crtcs] looking for cmdline mode on connector 91
>[   18.957252] [drm:drm_setup_crtcs] looking for preferred mode on connector 91 0
>[   18.957256] [drm:drm_setup_crtcs] found mode 3840x2160
>[   18.957260] [drm:drm_setup_crtcs] picking CRTCs for 3840x2160 config
>[   18.957889] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0)
>[   18.957910] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 58 (0,0)
>[   18.957929] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 74 (0,0)
>[   18.959670] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[   18.959744] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[   18.959752] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[   18.959825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[   18.959901] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   18.959968] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[   18.960038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   18.960141] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[   18.960211] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[   18.960278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[   18.960343] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   18.960408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   18.960414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[   18.960479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   18.960485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[   18.960550] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[   18.960614] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[   18.960679] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   18.960743] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   18.960807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   18.960879] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[   18.960943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   18.961010] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[   18.961101] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[   18.961168] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[   18.961234] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[   18.961300] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[   18.961372] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[   18.961437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[   18.961503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[   18.961577] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[   18.961641] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[   18.961707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   18.961773] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[   18.961836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[   18.961899] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[   18.961961] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[   18.962022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   18.962053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   18.962114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   18.962120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   18.962183] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[   18.962245] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[   18.962306] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   18.962367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   18.962428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   18.962493] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[   18.962555] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   18.962619] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[   18.962682] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[   18.962745] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[   18.962809] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[   18.962872] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[   18.962943] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[   18.963027] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[   18.963116] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[   18.963179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   18.963244] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[   18.963305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[   18.963365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[   18.963425] [drm:intel_dump_pipe_config [i915]] requested mode:
>[   18.963431] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[   18.963491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[   18.963497] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[   18.963558] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[   18.963618] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[   18.963678] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[   18.963738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   18.963797] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[   18.963864] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[   18.963923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[   18.963983] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[   18.964046] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[   18.964131] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[   18.964193] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[   18.964255] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[   18.964329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[   18.964406] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[   18.964468] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[   18.964533] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[   18.964595] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[   18.964662] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[   18.964724] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[   18.965444] [drm:intel_disable_pipe [i915]] disabling pipe A
>[   18.981820] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[   18.982005] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 42
>[   18.982277] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[   18.982400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[   18.982470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[   18.982538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[   18.982606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[   18.982673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[   18.982740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[   18.982805] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[   18.982878] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[   18.982948] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[   18.983106] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[   18.983171] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[   18.983773] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[   18.983851] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[   18.983935] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 0000006a
>[   18.984002] [drm:wait_panel_status [i915]] Wait complete
>[   18.984102] [drm:edp_panel_on [i915]] Wait for panel power on
>[   18.984177] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 0000006b
>[   19.185694] [drm:wait_panel_status [i915]] Wait complete
>[   19.185757] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[   19.187164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[   19.187211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   19.187264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[   19.188019] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[   19.188097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[   19.189159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[   19.189210] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[   19.190895] [drm:intel_enable_pipe [i915]] enabling pipe A
>[   19.190980] [drm:intel_edp_backlight_on [i915]] 
>[   19.191028] [drm:intel_panel_enable_backlight [i915]] pipe A
>[   19.191118] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[   19.191184] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[   19.191263] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[   19.191312] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[   19.208177] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[   19.208223] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[   19.208476] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[   19.210415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[   19.210459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[   19.210505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[   19.213156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[   19.213200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[   19.215069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[   19.217442] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[   19.219742] [drm:intel_enable_pipe [i915]] enabling pipe B
>[   19.219991] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[   19.220033] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[   19.220227] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[   19.221512] [drm:intel_enable_pipe [i915]] enabling pipe C
>[   19.221999] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[   19.241425] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[   19.241514] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[   19.241589] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[   19.241857] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[   19.241934] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[   19.242003] [drm:hsw_audio_config_update [i915]] using automatic N
>[   19.258965] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[   19.259164] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[   19.259465] [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>[   19.259593] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[   19.259948] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[   19.260042] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[   19.260274] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[   19.260521] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[   19.260614] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[   19.260804] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[   19.276197] [drm:drm_fb_helper_hotplug_event.part.18] 
>[   19.276202] Console: switching 
>[   19.276205] [drm:drm_setup_crtcs] 
>[   19.276209] to colour frame buffer device 240x67
>[   19.276306] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[   19.276416] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[   19.276501] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   19.276577] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[   19.276647] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   19.276715] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   19.277344] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[   19.278396] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   19.278437] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[   19.278446] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[   19.278454] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[   19.278529] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[   19.279663] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[   19.280604] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   19.280674] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[   19.280741] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   19.280809] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   19.281819] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[   19.281887] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[   19.290076] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   19.290225] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[   19.290229] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   19.290233] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   19.290236] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   19.290240] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[   19.290243] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   19.290246] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   19.290249] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   19.290253] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   19.290256] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   19.290259] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   19.290264] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[   19.290305] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[   19.292152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   19.292195] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   19.294376] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   19.294390] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   19.296357] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   19.296400] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   19.298460] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   19.298473] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   19.298480] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[   19.298489] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[   19.298542] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[   19.378892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   19.378996] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   19.381420] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   19.381442] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   19.381455] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   19.381565] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[   19.381572] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[   19.383850] [drm:drm_edid_to_eld] ELD monitor S277HK
>[   19.383858] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[   19.383865] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[   19.386224] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[   19.386231] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[   19.386236] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   19.386242] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   19.386247] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   19.386252] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   19.386257] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[   19.386262] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[   19.386267] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[   19.386272] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[   19.386277] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[   19.386282] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   19.386287] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   19.386293] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   19.386298] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   19.386303] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   19.386308] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   19.386313] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   19.386318] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   19.386323] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   19.386328] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   19.386333] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   19.386338] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   19.386344] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   19.386349] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   19.386354] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   19.386359] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   19.386364] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   19.386369] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   19.386374] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   19.386379] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   19.386384] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   19.386389] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   19.386394] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   19.386399] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   19.386404] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   19.386410] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   19.386415] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[   19.386420] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   19.386425] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   19.386430] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[   19.386435] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[   19.386440] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   19.386445] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   19.386450] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   19.386455] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   19.386460] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   19.386465] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   19.386471] [drm:drm_setup_crtcs] connector 76 enabled? yes
>[   19.386476] [drm:drm_setup_crtcs] connector 84 enabled? yes
>[   19.386480] [drm:drm_setup_crtcs] connector 88 enabled? no
>[   19.386484] [drm:drm_setup_crtcs] connector 91 enabled? yes
>[   19.386614] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[   19.386638] [drm:drm_setup_crtcs] looking for cmdline mode on connector 76
>[   19.386643] [drm:drm_setup_crtcs] looking for preferred mode on connector 76 0
>[   19.386646] [drm:drm_setup_crtcs] found mode 1920x1080
>[   19.386650] [drm:drm_setup_crtcs] looking for cmdline mode on connector 84
>[   19.386654] [drm:drm_setup_crtcs] looking for preferred mode on connector 84 0
>[   19.386658] [drm:drm_setup_crtcs] found mode 1920x1200
>[   19.386661] [drm:drm_setup_crtcs] looking for cmdline mode on connector 91
>[   19.386665] [drm:drm_setup_crtcs] looking for preferred mode on connector 91 0
>[   19.386668] [drm:drm_setup_crtcs] found mode 3840x2160
>[   19.386672] [drm:drm_setup_crtcs] picking CRTCs for 3840x2160 config
>[   19.387263] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0)
>[   19.387285] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 58 (0,0)
>[   19.387309] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 74 (0,0)
>[   19.434063] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[   19.665079] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
>[   19.935799] systemd[1]: System time before build time, advancing clock.
>[   20.023803] systemd[1]: systemd 231 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN)
>[   20.025169] systemd[1]: Detected architecture x86-64.
>[   20.025716] systemd[1]: Set hostname to <gfx-desktop>.
>[   20.331831] systemd[1]: Listening on udev Kernel Socket.
>[   20.332914] systemd[1]: Listening on udev Control Socket.
>[   20.334633] systemd[1]: Listening on Journal Socket.
>[   20.334972] systemd[1]: Listening on Syslog Socket.
>[   20.335114] systemd[1]: Reached target Remote File Systems.
>[   20.335723] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
>[   20.336784] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
>[   20.863904] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
>[   20.935183] systemd-journald[257]: Received request to flush runtime journal from PID 1
>[   21.397353] random: crng init done
>[   22.305506] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[   22.305557] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[   23.206399] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[   23.206485] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[   23.206572] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   23.206607] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[   23.206641] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   23.206674] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   23.206756] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[   23.206805] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[   23.207889] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[   23.208832] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   23.208864] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[   23.208878] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[   23.216421] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[   23.216480] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[   23.218610] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[   23.219804] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[   23.219840] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[   23.219874] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[   23.219907] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[   23.220848] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[   23.220882] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[   23.229240] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   23.229415] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[   23.229422] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[   23.229427] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[   23.229432] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   23.229437] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[   23.229442] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   23.229447] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   23.229453] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   23.229458] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   23.229463] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   23.229468] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   23.235524] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[   23.235588] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[   23.237093] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   23.237137] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   23.239331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   23.239343] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   23.241084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   23.241119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   23.243069] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   23.243081] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   23.243089] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[   23.243133] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[   23.243177] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[   23.317171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   23.317208] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   23.319165] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   23.319179] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   23.319188] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   23.319237] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[   23.319242] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[   23.320354] [drm:drm_edid_to_eld] ELD monitor S277HK
>[   23.320360] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[   23.320365] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[   23.321639] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[   23.321646] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[   23.321652] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   23.321657] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   23.321662] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   23.321667] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   23.321672] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[   23.321677] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[   23.321682] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[   23.321687] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[   23.321692] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[   23.321697] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   23.321702] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   23.321707] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   23.321712] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   23.321717] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   23.321722] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   23.321727] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   23.321732] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   23.321737] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   23.321742] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   23.321747] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   23.321752] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   23.321757] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   23.321762] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   23.321766] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   23.321771] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   23.321776] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   23.321781] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   23.321786] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   23.321791] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   23.321796] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   23.321801] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   23.321806] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   23.321811] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   23.321816] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   23.321821] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   23.321826] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[   23.321831] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   23.321836] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   23.321841] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[   23.321846] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[   23.321851] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   23.321856] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   23.321861] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   23.321866] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   23.321870] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   23.321875] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   23.346793] [drm:drm_mode_addfb2] [FB:93]
>[   23.556619] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[   23.597949] HDA: we are doing full chip reset now
>[   23.602422] HDA: LLCH offset is c00
>[   23.602469] HDA: cur_cap: 20800 for offset c00
>[   23.602504] snd_hda_intel 0000:00:0e.0: Capability version: 0x0
>[   23.602544] snd_hda_intel 0000:00:0e.0: HDA capability ID: 0x2
>[   23.602584] snd_hda_intel 0000:00:0e.0: Found ML capability
>[   23.602624] HDA: cur_cap: 30500 for offset 800
>[   23.602657] snd_hda_intel 0000:00:0e.0: Capability version: 0x0
>[   23.602696] snd_hda_intel 0000:00:0e.0: HDA capability ID: 0x3
>[   23.602736] snd_hda_intel 0000:00:0e.0: Found PP capability offset=800
>[   23.602782] HDA: cur_cap: 11f00 for offset 500
>[   23.602815] snd_hda_intel 0000:00:0e.0: Capability version: 0x0
>[   23.602854] snd_hda_intel 0000:00:0e.0: HDA capability ID: 0x1
>[   23.602894] snd_hda_intel 0000:00:0e.0: Found GTS capability offset=500
>[   23.602941] HDA: cur_cap: 50700 for offset 1f00
>[   23.602974] snd_hda_intel 0000:00:0e.0: Capability version: 0x0
>[   23.603041] snd_hda_intel 0000:00:0e.0: HDA capability ID: 0x5
>[   23.603081] snd_hda_intel 0000:00:0e.0: Found DRSM capability
>[   23.603123] HDA: cur_cap: 40000 for offset 700
>[   23.603155] snd_hda_intel 0000:00:0e.0: Capability version: 0x0
>[   23.603194] snd_hda_intel 0000:00:0e.0: HDA capability ID: 0x4
>[   23.603234] snd_hda_intel 0000:00:0e.0: Found SPB capability
>[   23.693966] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[   23.693972] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[   23.693977] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[   23.693981] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[   23.693984] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[   23.693989] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[   23.693992] snd_hda_codec_realtek hdaudioC0D0:      Internal Mic=0x12
>[   23.833956] [drm:drm_mode_addfb2] [FB:93]
>[   23.835237] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
>[   23.835374] [drm:drm_mode_setcrtc] [CONNECTOR:76:eDP-1]
>[   23.854428] [drm:drm_mode_addfb2] [FB:130]
>[   23.854495] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
>[   23.854553] [drm:drm_mode_setcrtc] [CONNECTOR:84:DP-1]
>[   23.875516] [drm:drm_mode_addfb2] [FB:143]
>[   23.875581] [drm:drm_mode_setcrtc] [CRTC:74:pipe C]
>[   23.875638] [drm:drm_mode_setcrtc] [CONNECTOR:91:HDMI-A-2]
>
>[   23.926121] ======================================================
>[   23.926123] WARNING: possible circular locking dependency detected
>[   23.926126] 4.14.0-rc1-drm-tip-ww38-commit-ab2e3a0+ #1 Tainted: G     U         
>[   23.926127] ------------------------------------------------------
>[   23.926128] plymouthd/336 is trying to acquire lock:
>[   23.926130]  (&dev->struct_mutex){+.+.}, at: [<ffffffffa005eacc>] i915_mutex_lock_interruptible+0x4c/0x130 [i915]
>[   23.926180] 
>               but task is already holding lock:
>[   23.926181]  (&mm->mmap_sem){++++}, at: [<ffffffff81048aa5>] __do_page_fault+0x105/0x560
>[   23.926189] 
>               which lock already depends on the new lock.
>
>[   23.926191] 
>               the existing dependency chain (in reverse order) is:
>[   23.926192] 
>               -> #6 (&mm->mmap_sem){++++}:
>[   23.926199]        __lock_acquire+0x11d6/0x1370
>[   23.926201]        lock_acquire+0x9e/0x1e0
>[   23.926203]        __might_fault+0x63/0x90
>[   23.926207]        _copy_to_user+0x23/0x70
>[   23.926209]        filldir+0xa0/0x120
>[   23.926211]        dcache_readdir+0xf4/0x170
>[   23.926213]        iterate_dir+0x7a/0x180
>[   23.926215]        SyS_getdents+0xa0/0x130
>[   23.926219]        entry_SYSCALL_64_fastpath+0x1c/0xb1
>[   23.926220] 
>               -> #5 (&sb->s_type->i_mutex_key#5){++++}:
>[   23.926225]        down_write+0x36/0x70
>[   23.926228]        handle_create+0xc5/0x1d0
>[   23.926230]        devtmpfsd+0x122/0x150
>[   23.926234]        kthread+0x14d/0x180
>[   23.926236]        ret_from_fork+0x27/0x40
>[   23.926237] 
>               -> #4 ((complete)&req.done){+.+.}:
>[   23.926241]        __lock_acquire+0x11d6/0x1370
>[   23.926243]        lock_acquire+0x9e/0x1e0
>[   23.926245]        wait_for_common+0x53/0x200
>[   23.926247]        wait_for_completion+0x18/0x20
>[   23.926249]        devtmpfs_create_node+0x136/0x170
>[   23.926251]        device_add+0x635/0x650
>[   23.926252]        device_create_groups_vargs+0xdb/0xf0
>[   23.926254]        device_create+0x35/0x40
>[   23.926257]        msr_device_create+0x26/0x40
>[   23.926259]        cpuhp_invoke_callback+0x9c/0x8a0
>[   23.926261]        cpuhp_thread_fun+0x75/0x150
>[   23.926264]        smpboot_thread_fn+0x180/0x280
>[   23.926266]        kthread+0x14d/0x180
>[   23.926268]        ret_from_fork+0x27/0x40
>[   23.926269] 
>               -> #3 (cpuhp_state){+.+.}:
>[   23.926274]        __lock_acquire+0x11d6/0x1370
>[   23.926275]        lock_acquire+0x9e/0x1e0
>[   23.926277]        cpuhp_issue_call+0xdd/0x150
>[   23.926279]        __cpuhp_setup_state_cpuslocked+0x133/0x2b0
>[   23.926281]        __cpuhp_setup_state+0x41/0x60
>[   23.926285]        page_writeback_init+0x3e/0x62
>[   23.926286]        pagecache_init+0x33/0x36
>[   23.926289]        start_kernel+0x3b7/0x40b
>[   23.926291]        x86_64_start_reservations+0x2a/0x2c
>[   23.926293]        x86_64_start_kernel+0x6d/0x70
>[   23.926296]        verify_cpu+0x0/0xfb
>[   23.926297] 
>               -> #2 (cpuhp_state_mutex){+.+.}:
>[   23.926302]        __lock_acquire+0x11d6/0x1370
>[   23.926304]        lock_acquire+0x9e/0x1e0
>[   23.926305]        __mutex_lock+0x83/0x980
>[   23.926307]        mutex_lock_nested+0x16/0x20
>[   23.926309]        __cpuhp_setup_state_cpuslocked+0x4e/0x2b0
>[   23.926310]        __cpuhp_setup_state+0x41/0x60
>[   23.926312]        page_alloc_init+0x23/0x2b
>[   23.926314]        start_kernel+0x140/0x40b
>[   23.926316]        x86_64_start_reservations+0x2a/0x2c
>[   23.926317]        x86_64_start_kernel+0x6d/0x70
>[   23.926320]        verify_cpu+0x0/0xfb
>[   23.926321] 
>               -> #1 (cpu_hotplug_lock.rw_sem){++++}:
>[   23.926325]        __lock_acquire+0x11d6/0x1370
>[   23.926327]        lock_acquire+0x9e/0x1e0
>[   23.926329]        cpus_read_lock+0x38/0xa0
>[   23.926332]        stop_machine+0x17/0x40
>[   23.926362]        i915_gem_init+0x103/0x110 [i915]
>[   23.926388]        i915_driver_load+0x9ed/0x16b0 [i915]
>[   23.926415]        i915_pci_probe+0x34/0xa0 [i915]
>[   23.926418]        pci_device_probe+0xa3/0x130
>[   23.926420]        driver_probe_device+0x299/0x440
>[   23.926422]        __driver_attach+0xde/0xe0
>[   23.926424]        bus_for_each_dev+0x61/0xa0
>[   23.926425]        driver_attach+0x19/0x20
>[   23.926427]        bus_add_driver+0x1f2/0x260
>[   23.926429]        driver_register+0x5b/0xd0
>[   23.926431]        __pci_register_driver+0x66/0x70
>[   23.926433]        lpc_ich_restore_config_space+0x6b/0x70 [lpc_ich]
>[   23.926435]        do_one_initcall+0x3f/0x160
>[   23.926438]        do_init_module+0x5a/0x1fa
>[   23.926440]        load_module+0x2205/0x25b0
>[   23.926441]        SyS_finit_module+0xbc/0xf0
>[   23.926443]        entry_SYSCALL_64_fastpath+0x1c/0xb1
>[   23.926444] 
>               -> #0 (&dev->struct_mutex){+.+.}:
>[   23.926449]        check_prev_add+0x410/0x810
>[   23.926451]        __lock_acquire+0x11d6/0x1370
>[   23.926452]        lock_acquire+0x9e/0x1e0
>[   23.926454]        __mutex_lock+0x83/0x980
>[   23.926456]        mutex_lock_interruptible_nested+0x16/0x20
>[   23.926484]        i915_mutex_lock_interruptible+0x4c/0x130 [i915]
>[   23.926513]        i915_gem_fault+0x207/0x660 [i915]
>[   23.926515]        __do_fault+0x19/0x70
>[   23.926517]        __handle_mm_fault+0x7fc/0xe40
>[   23.926518]        handle_mm_fault+0x151/0x300
>[   23.926521]        __do_page_fault+0x279/0x560
>[   23.926523]        do_page_fault+0x28/0x270
>[   23.926525]        page_fault+0x22/0x30
>[   23.926526] 
>               other info that might help us debug this:
>
>[   23.926528] Chain exists of:
>                 &dev->struct_mutex --> &sb->s_type->i_mutex_key#5 --> &mm->mmap_sem
>
>[   23.926533]  Possible unsafe locking scenario:
>
>[   23.926534]        CPU0                    CPU1
>[   23.926535]        ----                    ----
>[   23.926537]   lock(&mm->mmap_sem);
>[   23.926539]                                lock(&sb->s_type->i_mutex_key#5);
>[   23.926541]                                lock(&mm->mmap_sem);
>[   23.926543]   lock(&dev->struct_mutex);
>[   23.926545] 
>                *** DEADLOCK ***
>
>[   23.926547] 1 lock held by plymouthd/336:
>[   23.926548]  #0:  (&mm->mmap_sem){++++}, at: [<ffffffff81048aa5>] __do_page_fault+0x105/0x560
>[   23.926553] 
>               stack backtrace:
>[   23.926556] CPU: 0 PID: 336 Comm: plymouthd Tainted: G     U          4.14.0-rc1-drm-tip-ww38-commit-ab2e3a0+ #1
>[   23.926557] Hardware name: Intel Corp. Geminilake/GLK RVP1 DDR4 (05), BIOS GELKRVPA.X64.0062.B30.1708222146 08/22/2017
>[   23.926559] Call Trace:
>[   23.926562]  dump_stack+0x67/0x97
>[   23.926565]  print_circular_bug+0x21b/0x3a0
>[   23.926567]  ? lockdep_init_map_crosslock+0x20/0x20
>[   23.926569]  check_prev_add+0x410/0x810
>[   23.926572]  ? __save_stack_trace+0x7e/0xd0
>[   23.926575]  ? rcu_read_lock_sched_held+0x23/0x80
>[   23.926578]  __lock_acquire+0x11d6/0x1370
>[   23.926580]  ? __lock_acquire+0x11d6/0x1370
>[   23.926582]  ? lockdep_init_map_crosslock+0x20/0x20
>[   23.926584]  lock_acquire+0x9e/0x1e0
>[   23.926612]  ? i915_mutex_lock_interruptible+0x4c/0x130 [i915]
>[   23.926641]  ? i915_mutex_lock_interruptible+0x4c/0x130 [i915]
>[   23.926643]  __mutex_lock+0x83/0x980
>[   23.926671]  ? i915_mutex_lock_interruptible+0x4c/0x130 [i915]
>[   23.926673]  ? lockdep_init_map_crosslock+0x20/0x20
>[   23.926700]  ? i915_mutex_lock_interruptible+0x4c/0x130 [i915]
>[   23.926703]  mutex_lock_interruptible_nested+0x16/0x20
>[   23.926705]  ? mutex_lock_interruptible_nested+0x16/0x20
>[   23.926733]  i915_mutex_lock_interruptible+0x4c/0x130 [i915]
>[   23.926735]  ? __pm_runtime_resume+0x56/0x80
>[   23.926764]  i915_gem_fault+0x207/0x660 [i915]
>[   23.926766]  ? __might_fault+0x80/0x90
>[   23.926768]  __do_fault+0x19/0x70
>[   23.926770]  __handle_mm_fault+0x7fc/0xe40
>[   23.926772]  handle_mm_fault+0x151/0x300
>[   23.926775]  __do_page_fault+0x279/0x560
>[   23.926777]  do_page_fault+0x28/0x270
>[   23.926780]  page_fault+0x22/0x30
>[   23.926782] RIP: 0033:0x7f07f9b91e28
>[   23.926783] RSP: 002b:00007ffe64603758 EFLAGS: 00010206
>[   23.926785] RAX: 00007f07f0a58000 RBX: 0000563d901f1260 RCX: 0000000000080000
>[   23.926787] RDX: 00000000007e8ff0 RSI: 00007f07f7cc8030 RDI: 00007f07f0a58010
>[   23.926788] RBP: 0000000000000000 R08: 00007f07f0a58000 R09: 00007f07f7cc8020
>[   23.926789] R10: 000000000000000b R11: 00007f07f9bcf5b0 R12: 0000563d901efc40
>[   23.926791] R13: 0000563d901f10e0 R14: 0000563d901f1340 R15: 00007f07f0a58000
>[   23.929153] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
>[   23.929196] [drm:drm_mode_setcrtc] [CONNECTOR:76:eDP-1]
>[   23.939997] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
>[   23.940053] [drm:drm_mode_setcrtc] [CONNECTOR:84:DP-1]
>[   23.952524] [drm:drm_mode_setcrtc] [CRTC:74:pipe C]
>[   23.952565] [drm:drm_mode_setcrtc] [CONNECTOR:91:HDMI-A-2]
>[   24.265223] Adding 16642044k swap on /dev/sda3.  Priority:-2 extents:1 across:16642044k SSFS
>[   24.810448] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[   24.810486] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[   24.810519] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[   24.810560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[   24.810592] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[   24.810624] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[   24.810655] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[   24.810686] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[   24.846274] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input9
>[   24.847632] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input10
>[   24.848452] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input11
>[   24.849741] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input12
>[   24.850548] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input13
>[   24.861105] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input14
>[   24.862620] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input15
>[   24.899750] new mount options do not match the existing superblock, will be ignored
>[   25.928620] IPv6: ADDRCONF(NETDEV_UP): enp1s0: link is not ready
>[   25.950869] r8169 0000:01:00.0 enp1s0: link down
>[   25.950871] r8169 0000:01:00.0 enp1s0: link down
>[   25.951067] IPv6: ADDRCONF(NETDEV_UP): enp1s0: link is not ready
>[   26.272074] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[   26.272114] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[   29.726569] r8169 0000:01:00.0 enp1s0: link up
>[   29.726658] IPv6: ADDRCONF(NETDEV_CHANGE): enp1s0: link becomes ready
>[  663.385424] Console: switching to colour dummy device 80x25
>[  663.385607] [IGT] kms_cursor_legacy: executing
>[  663.443821] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[  663.443904] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[  663.443972] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  663.444035] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  663.444168] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  663.444255] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  663.444348] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  663.444426] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  663.444883] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[  663.445694] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  663.445733] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[  663.445746] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  663.446350] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[  663.446434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  663.446449] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  663.446530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[  663.446612] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  663.446688] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[  663.446768] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  663.446847] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[  663.446924] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  663.447002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[  663.447104] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  663.447188] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  663.447207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  663.447288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  663.447305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  663.447379] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[  663.447462] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[  663.447539] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  663.447613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  663.447688] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  663.447771] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  663.447846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  663.447924] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] FB:134, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  663.447999] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  663.448100] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[  663.448187] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[  663.448259] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[  663.448294] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[  663.448328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[  663.448368] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[  663.448401] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  663.448492] [drm:intel_edp_backlight_off [i915]] 
>[  663.656335] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  663.656385] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  663.663205] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[  663.663276] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[  663.663339] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  663.713691] [drm:wait_panel_status [i915]] Wait complete
>[  663.713760] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  663.716051] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  663.716165] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  663.716261] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  663.716345] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  663.716463] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[  663.716552] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  663.716768] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  663.716866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  663.716949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  663.717031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  663.717160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  663.717254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  663.717344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  663.717436] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  663.717529] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  663.717633] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  663.717802] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[  663.717888] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  663.718342] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  663.718437] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  664.288346] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  664.288443] [drm:wait_panel_status [i915]] Wait complete
>[  664.288528] [drm:edp_panel_on [i915]] Wait for panel power on
>[  664.288612] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  664.391824] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  664.391933] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  664.392030] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  664.392212] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  664.490678] [drm:wait_panel_status [i915]] Wait complete
>[  664.490794] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[  664.490978] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  664.491087] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  664.492501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  664.492603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  664.492703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  664.493535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  664.493650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  664.494689] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  664.494762] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  664.495386] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  664.495473] [drm:intel_edp_backlight_on [i915]] 
>[  664.495542] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  664.495610] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  664.495683] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  664.495765] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  664.495832] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  664.512504] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[  664.512601] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[  664.512916] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  664.513549] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[  664.513629] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[  664.514673] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  664.515563] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  664.515651] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  664.515732] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  664.515812] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  664.516735] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[  664.516828] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  664.524235] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  664.524465] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[  664.524478] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  664.524488] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  664.524497] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  664.524507] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  664.524516] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  664.524525] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  664.524535] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  664.524544] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  664.524556] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  664.524565] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  664.525244] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[  664.525310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  664.525346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  664.525380] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  664.525412] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  664.525447] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  664.525481] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[  664.525515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  664.525548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  664.525580] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  664.525612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  664.525618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  664.525648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  664.525653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  664.525683] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  664.525714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  664.525746] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  664.525777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  664.525808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  664.525842] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  664.525873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  664.525906] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:134, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  664.525938] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  664.525969] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[  664.526000] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[  664.526043] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[  664.526075] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[  664.526114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[  664.526161] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[  664.526197] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  664.526308] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  664.542853] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  664.544309] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[  664.544427] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  664.544469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  664.544499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  664.544528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  664.544557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  664.544586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  664.544614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  664.544644] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  664.544697] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  664.544726] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  664.544798] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[  664.544827] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  664.544976] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  664.546811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  664.546844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  664.546876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  664.549591] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  664.549652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  664.551419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  664.553313] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  664.554139] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  664.571214] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[  664.571272] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[  664.571372] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  664.571533] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[  664.571579] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[  664.573304] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  664.573359] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  664.575286] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  664.575305] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  664.577328] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  664.577383] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  664.579290] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  664.579308] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  664.579317] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[  664.579773] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[  664.579834] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[  664.657517] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  664.657602] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  664.659331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  664.659354] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  664.659366] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  664.659447] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[  664.659456] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[  664.660847] [drm:drm_edid_to_eld] ELD monitor S277HK
>[  664.660858] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[  664.660865] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  664.662174] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[  664.662186] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  664.662195] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  664.662204] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  664.662212] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  664.662220] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  664.662229] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[  664.662237] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[  664.662245] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[  664.662253] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[  664.662262] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  664.662270] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  664.662278] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  664.662287] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  664.662295] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  664.662304] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  664.662312] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  664.662320] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  664.662329] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  664.662337] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  664.662345] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  664.662354] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  664.662362] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  664.662370] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  664.662379] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  664.662387] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  664.662395] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  664.662404] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  664.662412] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  664.662420] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  664.662428] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  664.662437] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  664.662445] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  664.662453] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  664.662462] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  664.662470] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  664.662478] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  664.662487] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  664.662495] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  664.662503] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  664.662512] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  664.662520] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  664.662528] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  664.662537] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  664.662545] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  664.662553] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  664.662561] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  664.662570] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  664.663211] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[  664.663317] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  664.663406] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[  664.663497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  664.663585] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[  664.663673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  664.663758] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  664.663841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  664.663853] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  664.663929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  664.663950] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  664.664026] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  664.664157] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[  664.664249] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  664.664341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  664.664434] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  664.664535] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[  664.664630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  664.664728] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] FB:134, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  664.664822] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  664.664915] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[  664.665006] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[  664.665120] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[  664.665225] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[  664.665337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[  664.665459] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[  664.665556] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  664.665801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  664.665875] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  664.665926] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[  664.683594] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[  664.683663] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  664.695707] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  664.697337] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[  664.697562] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  664.697665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  664.697751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  664.697833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  664.697913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  664.697992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  664.698071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  664.698200] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  664.698420] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  664.698523] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  664.698668] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[  664.698750] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  664.698996] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  664.699603] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  664.699706] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[  664.717751] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[  664.717854] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[  664.717939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  664.718029] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[  664.718191] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  664.718280] [drm:hsw_audio_config_update [i915]] using automatic N
>[  664.734941] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[  664.735063] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[  664.735365] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  664.735877] [IGT] kms_cursor_legacy: starting subtest 2x-long-cursor-vs-flip-atomic
>[  664.745821] [drm:drm_mode_addfb2] [FB:132]
>[  665.038405] [drm:drm_mode_addfb2] [FB:137]
>[  665.060247] [drm:drm_mode_addfb2] [FB:143]
>[  665.061128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  665.061177] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[  665.061212] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  665.061250] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[  665.061285] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  665.061815] [drm:intel_edp_backlight_off [i915]] 
>[  665.264318] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  665.264397] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  665.278938] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[  665.279004] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[  665.279104] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  665.330992] [drm:wait_panel_status [i915]] Wait complete
>[  665.331113] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  665.331992] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  665.332084] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  665.332165] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  665.332325] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  665.333348] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  665.333443] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[  665.333650] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  665.333761] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  665.339774] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  665.341304] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[  665.341520] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  665.341620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  665.341702] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  665.341810] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[  665.359808] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[  665.359939] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  665.369361] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  665.369488] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[  665.369720] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  665.369866] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[  665.369991] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[  665.370089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  665.370242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  665.370343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  665.370445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  665.370540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  665.370632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  665.370739] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[  665.370840] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[  665.370935] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  665.371030] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  665.371153] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  665.371361] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[  665.371456] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  665.371785] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  665.373886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  665.373996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  665.374150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  665.376845] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  665.376951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  665.378839] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  665.380309] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  665.381138] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  665.398251] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[  665.398290] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  665.398479] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  665.398513] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  665.888358] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  665.926891] [drm:wait_panel_status [i915]] Wait complete
>[  665.927000] [drm:edp_panel_on [i915]] Wait for panel power on
>[  665.927176] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  666.030302] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  666.030412] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  666.030509] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  666.030704] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  666.128894] [drm:wait_panel_status [i915]] Wait complete
>[  666.129014] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[  666.129289] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  666.129401] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  666.130757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  666.130869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  666.130975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  666.132191] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  666.132296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  666.133413] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  666.133533] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  666.134508] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  666.134642] [drm:intel_edp_backlight_on [i915]] 
>[  666.134748] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  666.134853] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  666.134963] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  666.135086] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  666.135702] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  666.151579] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[  666.151688] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[  666.151992] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  666.152265] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[  666.152427] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[  666.152530] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  666.152621] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[  669.152134] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  669.152176] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  695.725414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  695.725629] [drm:intel_edp_backlight_off [i915]] 
>[  695.928229] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  695.928363] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  695.943758] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  695.943859] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  695.944243] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[  695.944366] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[  695.944482] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  695.995416] [drm:wait_panel_status [i915]] Wait complete
>[  695.995533] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  695.997334] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  695.997429] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  695.997542] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  695.997648] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  695.997772] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[  695.997882] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  695.998180] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  695.998373] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  696.009092] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  696.009264] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[  696.009509] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  696.009672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  696.009784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  696.009891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  696.009994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  696.010095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  696.010251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  696.010371] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[  696.010489] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[  696.010604] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[  696.010712] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  696.010826] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  696.010932] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  696.011185] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[  696.011336] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[  696.012569] [IGT] kms_cursor_legacy: exiting, ret=0
>[  696.040333] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[  696.040401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  696.040429] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  696.040504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[  696.040572] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  696.040636] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[  696.040700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  696.040763] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[  696.040822] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  696.040883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[  696.040947] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  696.041001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  696.041045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  696.041109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  696.041131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  696.041197] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[  696.041263] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[  696.041326] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  696.041386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  696.041447] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  696.041508] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  696.041583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  696.041642] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[  696.041703] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[  696.041765] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[  696.041824] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[  696.041886] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[  696.041951] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[  696.042011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  696.042086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  696.042154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  696.042217] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  696.042279] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  696.042341] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[  696.042397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  696.042456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  696.042521] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  696.042578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  696.042596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  696.042657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  696.042674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  696.042737] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  696.042801] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  696.042865] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  696.042926] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  696.042984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  696.043045] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  696.043135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  696.043190] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[  696.043248] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[  696.043306] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[  696.043364] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[  696.043425] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[  696.043491] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[  696.043568] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  696.043626] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[  696.043685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  696.043746] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[  696.043802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  696.043862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  696.043916] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  696.043936] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  696.043997] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  696.044027] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  696.044090] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  696.044156] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[  696.044217] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  696.044276] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  696.044335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  696.044396] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[  696.044473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  696.044529] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[  696.044589] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[  696.044649] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[  696.044710] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[  696.044772] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[  696.044835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[  696.044916] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[  696.044976] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  696.045038] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[  696.045106] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  696.045175] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[  696.045233] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  696.045453] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[  696.045546] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[  696.045616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  696.045673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  696.045729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  696.045786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  696.045842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  696.045898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  696.045955] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  696.046011] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  696.046087] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  696.046202] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[  696.046245] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  696.046448] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  696.046489] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  696.552325] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  696.552406] [drm:wait_panel_status [i915]] Wait complete
>[  696.552470] [drm:edp_panel_on [i915]] Wait for panel power on
>[  696.552531] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  696.655823] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  696.655943] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  696.656040] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  696.656222] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  696.754454] [drm:wait_panel_status [i915]] Wait complete
>[  696.754577] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[  696.754767] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  696.754882] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  696.756249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  696.756374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  696.756501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  696.757364] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  696.757482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  696.758586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  696.758717] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  696.759571] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  696.759752] [drm:intel_edp_backlight_on [i915]] 
>[  696.759864] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  696.759979] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  696.760137] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  696.760286] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  696.760422] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  696.760664] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[  696.760790] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  696.761117] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  696.763104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  696.763206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  696.763311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  696.765933] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  696.766038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  696.767837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  696.769327] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  696.770063] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  696.773381] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[  696.773432] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  696.773600] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  696.773889] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  696.773943] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[  696.775330] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[  696.775379] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  696.777290] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[  696.777324] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[  696.777379] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[  696.777438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[  696.777493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  696.777550] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[  696.777608] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  696.777662] [drm:hsw_audio_config_update [i915]] using automatic N
>[  696.794375] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[  696.794448] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[  696.794570] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  696.794682] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[  696.794742] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[  696.794834] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  696.794935] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[  696.795011] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[  696.795200] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  699.808382] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  699.808537] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  732.026444] [IGT] kms_cursor_legacy: executing
>[  732.310319] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[  732.310398] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[  732.310461] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  732.310520] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  732.310576] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  732.310630] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  732.310691] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  732.310749] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  732.311196] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[  732.311941] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  732.311971] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[  732.311980] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  732.313889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[  732.313923] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[  732.314827] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  732.315614] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  732.315660] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  732.315689] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  732.315718] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  732.316571] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[  732.316605] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  732.323337] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  732.323422] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[  732.323427] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  732.323430] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  732.323434] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  732.323437] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  732.323441] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  732.323444] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  732.323448] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  732.323451] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  732.323454] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  732.323458] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  732.333495] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[  732.333551] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[  732.335300] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  732.335340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  732.337300] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  732.337316] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  732.339308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  732.339348] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  732.341289] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  732.341306] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  732.341313] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[  732.341734] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[  732.341788] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[  732.421359] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  732.421432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  732.423310] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  732.423331] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  732.423342] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  732.423415] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[  732.423423] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[  732.424535] [drm:drm_edid_to_eld] ELD monitor S277HK
>[  732.424542] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[  732.424547] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  732.425437] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[  732.425445] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  732.425452] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  732.425457] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  732.425463] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  732.425469] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  732.425475] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[  732.425480] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[  732.425486] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[  732.425492] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[  732.425497] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  732.425503] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  732.425509] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  732.425515] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  732.425521] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  732.425526] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  732.425532] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  732.425538] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  732.425543] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  732.425549] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  732.425555] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  732.425561] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  732.425566] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  732.425572] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  732.425578] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  732.425584] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  732.425589] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  732.425595] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  732.425601] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  732.425606] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  732.425612] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  732.425618] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  732.425623] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  732.425629] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  732.425635] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  732.425640] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  732.425646] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  732.425652] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  732.425657] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  732.425663] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  732.425669] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  732.425675] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  732.425680] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  732.425686] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  732.425692] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  732.425697] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  732.425703] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  732.425709] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  732.430464] [IGT] kms_cursor_legacy: starting subtest 2x-long-cursor-vs-flip-legacy
>[  732.447512] [drm:drm_mode_addfb2] [FB:130]
>[  732.533606] [drm:drm_mode_addfb2] [FB:145]
>[  732.554908] [drm:drm_mode_addfb2] [FB:150]
>[  732.555818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  732.555861] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[  732.555893] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  732.555925] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[  732.555955] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  732.556431] [drm:intel_edp_backlight_off [i915]] 
>[  732.760342] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  732.760460] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.765190] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[  732.765310] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[  732.765421] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  732.817432] [drm:wait_panel_status [i915]] Wait complete
>[  732.817548] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  732.818251] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  732.818377] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  732.818499] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  732.818660] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  732.819867] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.819997] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[  732.820313] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  732.820468] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  732.835205] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  732.835335] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[  732.835574] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  732.835703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  732.835814] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.835960] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[  732.853377] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[  732.853521] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  732.863415] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  732.863556] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[  732.863802] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  732.863965] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[  732.864167] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[  732.864293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  732.864407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  732.864512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  732.864625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  732.864728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  732.864832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  732.864942] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[  732.865053] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[  732.865190] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  732.865312] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  732.865423] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  732.865649] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[  732.865754] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  732.866052] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  732.868135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.868248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.868357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.871279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.871404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.873305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.875342] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  732.876426] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  732.893515] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[  732.893559] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  732.893823] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  732.893862] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  733.368361] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  733.368442] [drm:wait_panel_status [i915]] Wait complete
>[  733.368514] [drm:edp_panel_on [i915]] Wait for panel power on
>[  733.368586] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  733.471801] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  733.471904] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  733.471993] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  733.472247] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  733.569967] [drm:wait_panel_status [i915]] Wait complete
>[  733.570073] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[  733.570319] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  733.570431] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  733.571779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.571882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.571983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.572824] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.572937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.574027] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.574208] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  733.575042] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.575220] [drm:intel_edp_backlight_on [i915]] 
>[  733.575331] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  733.575437] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  733.575553] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  733.575678] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.575784] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.592255] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[  733.592410] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[  733.592715] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  733.593202] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[  733.593342] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[  733.593588] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  733.593726] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[  736.608073] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  736.608164] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  763.870731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  763.870921] [drm:intel_edp_backlight_off [i915]] 
>[  764.072352] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  764.072406] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  764.084739] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  764.084831] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  764.085176] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[  764.085256] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[  764.085339] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  764.136140] [drm:wait_panel_status [i915]] Wait complete
>[  764.136228] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  764.138250] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  764.138351] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  764.138456] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[  764.138551] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  764.138646] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  764.138807] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  764.138905] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  764.139064] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  764.154917] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  764.155053] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[  764.155375] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  764.155542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  764.155663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  764.155776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  764.155882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  764.155988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  764.156091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  764.156229] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[  764.156355] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[  764.156474] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[  764.156583] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  764.156689] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  764.156797] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  764.157014] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[  764.157210] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[  764.158409] [IGT] kms_cursor_legacy: exiting, ret=0
>[  764.182156] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[  764.182226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  764.182255] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  764.182331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[  764.182400] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  764.182462] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[  764.182526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  764.182589] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[  764.182647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  764.182708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[  764.182772] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  764.182826] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  764.182842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  764.182903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  764.182919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  764.182982] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[  764.183074] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[  764.183143] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  764.183202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  764.183264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  764.183325] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  764.183401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  764.183458] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[  764.183519] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[  764.183580] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[  764.183644] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[  764.183703] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[  764.183767] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[  764.183827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  764.183892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  764.183960] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  764.184025] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  764.184097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  764.184179] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[  764.184218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  764.184261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  764.184307] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  764.184345] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  764.184358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  764.184401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  764.184416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  764.184460] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  764.184504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  764.184550] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  764.184591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  764.184635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  764.184676] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  764.184730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  764.184768] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[  764.184810] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[  764.184852] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[  764.184892] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[  764.184935] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[  764.184981] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[  764.185212] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  764.185255] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[  764.185296] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  764.185338] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[  764.185378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  764.185419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  764.185460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  764.185472] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  764.185515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  764.185528] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  764.185571] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  764.185616] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[  764.185662] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  764.185706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  764.185750] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  764.185793] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[  764.185846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  764.185884] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[  764.185925] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[  764.185969] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[  764.186009] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[  764.186059] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[  764.186107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[  764.186162] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[  764.186205] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  764.186248] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[  764.186290] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  764.186334] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[  764.186376] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  764.186536] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[  764.186611] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[  764.186658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  764.186697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[  764.186736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[  764.186775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[  764.186814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[  764.186853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[  764.186892] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  764.186932] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  764.186974] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  764.187069] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[  764.187113] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  764.187304] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  764.187348] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  764.688364] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  764.727384] [drm:wait_panel_status [i915]] Wait complete
>[  764.727470] [drm:edp_panel_on [i915]] Wait for panel power on
>[  764.727548] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  764.830799] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  764.830930] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  764.831034] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  764.831249] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  764.929603] [drm:wait_panel_status [i915]] Wait complete
>[  764.929737] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[  764.929938] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  764.930066] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  764.931821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  764.931938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  764.932059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  764.933201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  764.933331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  764.934699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  764.934844] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  764.936150] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  764.936352] [drm:intel_edp_backlight_on [i915]] 
>[  764.936477] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  764.936606] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  764.936752] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  764.936908] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  764.937053] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  764.937827] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[  764.937973] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  764.938325] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  764.940224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  764.940262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  764.940301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  764.942784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  764.942822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  764.944549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  764.946325] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  764.947061] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  764.950372] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[  764.950434] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  764.950615] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  764.950953] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  764.951017] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[  764.953245] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[  764.953304] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  764.955307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[  764.955339] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[  764.955392] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[  764.955449] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[  764.955502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  764.955557] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[  764.955612] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  764.955664] [drm:hsw_audio_config_update [i915]] using automatic N
>[  764.972549] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[  764.972651] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[  764.972958] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[  764.973291] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[  764.973379] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[  764.973519] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[  764.973661] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[  764.973761] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[  764.973893] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[  767.968376] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  767.968530] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1044.622604] [IGT] kms_cursor_legacy: executing
>[ 1044.912951] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1044.913053] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1044.913180] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1044.913279] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1044.913361] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1044.913437] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1044.913523] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1044.913606] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1044.914082] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1044.914795] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1044.914812] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1044.914817] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1044.923363] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1044.923418] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1044.924333] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1044.925127] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1044.925161] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1044.925192] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1044.925221] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1044.926080] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1044.926327] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1044.933209] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1044.933341] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1044.933349] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1044.933354] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1044.933360] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1044.933365] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1044.933370] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1044.933375] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1044.933380] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1044.933385] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1044.933390] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1044.933395] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1044.947447] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1044.947512] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1044.949312] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1044.949371] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1044.951293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1044.951312] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1044.953338] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1044.953398] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1044.955298] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1044.955321] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1044.955332] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1044.955949] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1044.956033] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1045.036354] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1045.036432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1045.038684] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1045.038710] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1045.038723] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1045.038811] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1045.038821] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1045.040396] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1045.040408] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1045.040416] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1045.041816] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1045.041829] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1045.041839] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1045.041848] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1045.041857] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1045.041867] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1045.041876] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1045.041885] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1045.041894] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1045.041903] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1045.041912] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1045.041921] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1045.041931] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1045.041940] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1045.041949] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1045.041958] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1045.041967] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1045.041977] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1045.041986] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1045.041995] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1045.042004] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1045.042043] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1045.042053] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1045.042062] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1045.042071] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1045.042080] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1045.042089] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1045.042099] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1045.042108] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1045.042117] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1045.042138] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1045.042158] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1045.042175] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1045.042192] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1045.042209] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1045.042228] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1045.042248] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1045.042264] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1045.042283] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1045.042300] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1045.042316] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1045.042327] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1045.042336] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1045.042345] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1045.042354] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1045.042363] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1045.042372] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1045.042384] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1045.055243] [IGT] kms_cursor_legacy: starting subtest 2x-long-nonblocking-modeset-vs-cursor-atomic
>[ 1045.056555] [drm:drm_mode_addfb2] [FB:92]
>[ 1045.131889] [drm:drm_mode_addfb2] [FB:145]
>[ 1045.152713] [drm:drm_mode_addfb2] [FB:150]
>[ 1045.153703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1045.153749] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1045.153781] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1045.153814] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1045.153844] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1045.154677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1045.154711] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1045.154742] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1045.154773] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1045.154802] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1045.155373] [drm:intel_edp_backlight_off [i915]] 
>[ 1045.360330] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1045.360418] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1045.375007] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1045.375140] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1045.375229] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[ 1045.426728] [drm:wait_panel_status [i915]] Wait complete
>[ 1045.426822] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1045.428251] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1045.428350] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1045.428456] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1045.428557] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1045.428654] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1045.428824] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1045.428912] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1045.429044] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1045.432886] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1045.434400] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1045.434635] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1045.434755] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1045.434855] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1045.434984] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1045.452572] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1045.452691] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1045.456311] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1045.456428] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1045.456649] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1045.456781] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1045.456898] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1045.456988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1045.457071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1045.457235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1045.457339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1045.457438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1045.457532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1045.457633] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1045.457744] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1045.457840] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1045.457935] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1045.458030] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1045.458251] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1045.458346] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1045.458640] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1045.460639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1045.460732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1045.460826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1045.463670] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1045.463782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1045.465559] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1045.467851] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1045.468681] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1045.485757] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1045.485799] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1045.486079] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1045.486121] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1045.984396] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1045.984485] [drm:wait_panel_status [i915]] Wait complete
>[ 1045.984564] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1045.984643] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1046.087816] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1046.087906] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1046.087984] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1046.088153] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1046.186698] [drm:wait_panel_status [i915]] Wait complete
>[ 1046.186806] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1046.186980] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1046.187080] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1046.188501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1046.188613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1046.188719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1046.189554] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1046.189668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1046.190756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1046.190866] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1046.191768] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1046.191898] [drm:intel_edp_backlight_on [i915]] 
>[ 1046.192003] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1046.192146] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1046.192273] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1046.192397] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1046.192503] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1046.208731] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1046.208879] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1046.209233] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.209518] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.209652] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.209807] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.209953] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1046.270669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.271224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.271666] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1046.287379] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1046.289657] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1046.289884] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1046.290014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.290166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.290264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.290350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.290437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.290520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.290606] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.290694] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.290903] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.290988] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.292217] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.326664] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1046.326743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1046.326825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1046.326899] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1046.326967] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1046.327041] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1046.327151] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1046.327233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1046.327310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1046.327382] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1046.327851] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1046.327869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.327935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1046.327952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.328019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1046.328114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1046.328193] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1046.328271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1046.328584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1046.328658] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1046.328724] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1046.328792] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1046.328858] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1046.328926] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1046.328994] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1046.329060] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1046.329159] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1046.329238] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1046.329319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.329406] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1046.329483] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1046.329792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.329872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.329946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.330017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.330177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.330271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.330365] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.330588] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.330683] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.342044] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1046.342142] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1046.342351] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1046.344393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1046.344453] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1046.344515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1046.347101] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1046.347159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1046.348987] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1046.350294] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1046.351208] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1046.368320] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.368386] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.368471] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.402175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.402494] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1046.419417] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1046.421331] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1046.421567] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1046.421711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.421805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.421899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.421987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.422076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.422216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.422322] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.422428] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.422647] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.422737] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.425389] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.459987] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1046.460066] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1046.460190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1046.460276] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1046.460348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1046.460428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1046.460503] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1046.460575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1046.460648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1046.460717] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1046.460788] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1046.460804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.460872] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1046.460883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.460952] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1046.461020] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1046.461117] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1046.461199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1046.461274] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1046.461358] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1046.461432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1046.461505] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1046.461574] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1046.461644] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1046.461712] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1046.461782] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1046.461856] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1046.461924] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1046.462000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.462101] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1046.462179] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1046.462683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.462790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.462894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.462988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.463079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.463201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.463305] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.463944] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.464040] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.475291] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1046.475372] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1046.475600] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1046.477582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1046.477652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1046.477725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1046.480576] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1046.480657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1046.482569] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1046.484308] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1046.485300] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1046.502434] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.502531] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.502654] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.536583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.537076] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1046.554827] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1046.554959] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1046.555274] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1046.555434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.555543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.555654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.555757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.555860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.555962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.556069] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.556211] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.556454] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.556559] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.558604] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.593431] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1046.593536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1046.593640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1046.593739] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1046.593831] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1046.593928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1046.594025] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1046.594176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1046.594269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1046.594374] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1046.594473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1046.594501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.594594] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1046.594609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.594710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1046.594805] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1046.594900] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1046.594992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1046.595086] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1046.595214] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1046.595318] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1046.595420] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1046.595513] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1046.595607] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1046.595698] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1046.595792] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1046.595886] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1046.595978] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1046.596081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.596217] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1046.596323] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1046.596813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.596868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.596921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.596973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.597026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.597099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.597161] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.597344] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.597444] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.608451] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1046.608511] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1046.608706] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1046.610642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1046.610719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1046.610795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1046.613605] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1046.613693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1046.615533] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1046.617290] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1046.618269] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1046.635373] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.635466] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.635582] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.669580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.669971] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1046.686417] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1046.688328] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1046.688564] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1046.688707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.688801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.688896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.688985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.689072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.689212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.689317] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.689421] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.689643] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.689737] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.691809] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.726218] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1046.726291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1046.726366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1046.726433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1046.726496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1046.726564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1046.726632] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1046.726697] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1046.726761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1046.726822] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1046.726882] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1046.726894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.726955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1046.726965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.727027] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1046.727133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1046.727206] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1046.727275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1046.727342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1046.727418] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1046.727489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1046.727556] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1046.727620] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1046.727690] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1046.727752] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1046.727815] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1046.727881] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1046.727944] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1046.728014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.728112] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1046.728187] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1046.728566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.728640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.728709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.728774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.728839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.728901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.728968] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.729196] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.729263] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.741690] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1046.741759] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1046.741970] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1046.743975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1046.744064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1046.744188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1046.747037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1046.747153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1046.748994] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1046.751317] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1046.752400] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1046.769551] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.769653] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.769836] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.803606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.804001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.804564] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1046.821364] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1046.823354] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1046.823589] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1046.823733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.823826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.823919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.824008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.824149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.824252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.824354] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.824459] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.824680] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.824774] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.841724] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.876716] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1046.876839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1046.876962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1046.877075] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1046.877250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1046.877378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1046.877499] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1046.877612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1046.877726] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1046.877829] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1046.877931] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1046.877953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.878053] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1046.878101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1046.878214] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1046.878326] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1046.878440] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1046.878543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1046.878643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1046.878757] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1046.878861] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1046.878973] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1046.879077] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1046.879206] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1046.879326] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1046.879438] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1046.879552] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1046.879655] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1046.879768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.879891] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1046.879997] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1046.880331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.880388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.880439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.880490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.880539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.880588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.880641] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.880817] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.880867] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.891511] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1046.891568] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1046.891761] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1046.893634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1046.893685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1046.893734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1046.896331] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1046.896406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1046.898223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1046.900303] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1046.901144] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1046.918223] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.918296] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1046.918392] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.951856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1046.952385] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1046.969353] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1046.971362] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1046.971599] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1046.971744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1046.971838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1046.971933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1046.972022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1046.972161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1046.972261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1046.972365] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1046.972465] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1046.973226] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1046.973318] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1046.974879] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.010018] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1047.010159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.010269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.010367] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.010459] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.010556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.010653] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1047.010748] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.010840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.010929] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1047.011017] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.011085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.011179] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.011203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.011299] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1047.011402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.011501] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1047.011595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.011688] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.011799] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1047.011891] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.011991] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1047.012083] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1047.012201] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1047.012308] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1047.012405] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1047.012502] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1047.012594] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1047.012696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.012812] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1047.012909] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1047.013394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.013450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.013504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.013557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.013609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.013661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.013714] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.013922] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.013977] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.024841] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1047.024929] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1047.025234] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1047.027176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.027254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.027332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.029927] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.030003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.031900] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.033306] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1047.034157] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.051236] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.051304] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.051396] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.084886] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.085429] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1047.102135] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1047.104343] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1047.104579] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1047.104723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.104817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.104911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.104999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.105131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.105235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.105336] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.105440] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.106078] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.106220] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.108176] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.142738] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1047.142844] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.142952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.143049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.143194] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.143306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.143409] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1047.143506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.143606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.143698] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1047.143791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.143811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.143925] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.143943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.144047] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1047.144181] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.144296] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1047.144407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.144514] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.144626] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1047.144730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.144839] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1047.144943] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1047.145046] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1047.145174] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1047.145288] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1047.145403] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1047.145509] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1047.145624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.145747] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1047.145856] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1047.146395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.146458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.146518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.146578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.146637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.146692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.146752] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.146955] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.147025] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.158070] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1047.158171] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1047.158400] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1047.160359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.160431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.160503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.163118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.163186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.165004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.167294] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1047.168129] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.185228] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.185320] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.185438] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.219101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.219528] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1047.236426] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1047.238369] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1047.238619] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1047.238779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.238885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.238991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.239092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.239254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.239366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.239483] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.239596] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.239826] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.239930] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.241384] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.275532] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1047.275602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.275673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.275736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.275794] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.275855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.275918] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1047.275980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.276040] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.276138] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1047.276204] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.276222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.276285] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.276298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.276359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1047.276418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.276484] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1047.276544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.276603] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.276670] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1047.276729] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.276792] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1047.276851] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1047.276910] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1047.276969] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1047.277029] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1047.277155] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1047.277250] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1047.277352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.277459] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1047.277546] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1047.277898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.277995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.278154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.278253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.278342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.278425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.278512] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.278725] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.278812] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.291286] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1047.291355] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1047.291568] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1047.293611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.293697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.293779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.296607] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.296705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.298550] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.300297] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1047.301323] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.318453] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.318529] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.318628] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.352324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.352688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.353080] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1047.370377] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1047.372345] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1047.372597] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1047.372758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.372863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.372969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.373070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.373220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.373331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.373446] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.373563] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.373794] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.373899] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.374473] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.409250] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1047.409356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.409463] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.409561] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.409654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.409752] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.409850] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1047.409944] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.410035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.410181] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1047.410269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.410307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.410403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.410422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.410520] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1047.410612] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.410714] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1047.410807] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.410899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.411005] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1047.411121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.411224] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1047.411321] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1047.411414] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1047.411508] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1047.411602] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1047.411697] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1047.411788] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1047.411890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.412005] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1047.412123] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1047.412510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.412571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.412627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.412680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.412733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.412785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.412839] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.413018] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.413090] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.424506] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1047.424569] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1047.424770] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1047.426753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.426809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.426898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.429671] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.429734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.431549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.433301] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1047.434215] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.451314] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.451424] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.451603] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.485280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.485721] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1047.502284] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1047.502416] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1047.502658] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1047.502815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.502919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.503024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.503204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.503317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.503432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.503541] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.503652] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.503889] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.503994] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.507843] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.542325] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1047.542406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.542490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.542563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.542632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.542706] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.542780] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1047.542852] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.542922] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.542988] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1047.543054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.543117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.543188] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.543205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.543279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1047.543356] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.543431] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1047.543504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.543572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.543656] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1047.543724] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.543801] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1047.543870] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1047.543939] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1047.544011] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1047.544100] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1047.544180] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1047.544254] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1047.544333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.544417] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1047.544486] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1047.544787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.544868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.544942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.545015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.545127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.545194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.545266] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.545467] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.545543] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.557652] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1047.557716] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1047.557919] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1047.559803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.559860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.559916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.562494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.562570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.564418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.566318] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1047.567337] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.584454] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.584555] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.584738] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.618363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.618794] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1047.635260] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1047.637362] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1047.637612] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1047.637772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.637876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.637982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.638081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.638237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.638352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.638466] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.638578] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.638810] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.638914] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.641042] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.675798] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1047.675918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.676039] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.676212] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.676334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.676450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.676561] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1047.676671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.676779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.676886] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1047.676991] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.677015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.677149] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.677182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.677292] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1047.677404] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.677507] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1047.677611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.677713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.677829] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1047.677931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.678040] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1047.678170] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1047.678290] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1047.678405] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1047.678514] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1047.678622] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1047.678725] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1047.678841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.678967] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1047.679077] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1047.679548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.679602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.679656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.679708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.679761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.679810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.679861] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.680041] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.680119] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.690938] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1047.691001] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1047.691300] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1047.693269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.693347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.693427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.695982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.696058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.697931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.699297] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1047.700204] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.717367] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.717490] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.717650] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.751459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.751885] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1047.768444] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1047.768577] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1047.768818] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1047.768974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.769078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.769263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.769375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.769490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.769591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.769704] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.769814] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.770044] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.770182] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.774323] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.808877] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1047.808972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.809064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.809200] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.809298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.809391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.809480] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1047.809570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.809656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.809741] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1047.809823] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.809842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.809921] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.809934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.810018] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1047.810178] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.810280] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1047.810378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.810478] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.810580] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1047.810675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.810773] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1047.810866] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1047.810960] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1047.811052] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1047.811166] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1047.811274] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1047.811376] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1047.811482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.811592] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1047.811690] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1047.812072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.812322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.812420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.812515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.812606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.812698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.812795] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.813018] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.813142] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.824230] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1047.824310] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1047.824539] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1047.826496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.826566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.826638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.829258] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.829334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.831146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.833297] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1047.834152] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.851272] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.851365] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.851479] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.885217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.885609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.885976] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1047.902274] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1047.904366] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1047.904615] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1047.904775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.904881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.904988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.905089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.905243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.905358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.905473] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.905586] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.905818] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.905923] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.907504] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.942533] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1047.942656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.942775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.942884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.942988] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.943096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.943263] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1047.943386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.943502] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.943609] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1047.943715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.943748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.943847] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.943873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1047.943975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1047.944088] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.944223] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1047.944325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.944429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.944545] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1047.944647] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.944773] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1047.944883] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1047.944987] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1047.945092] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1047.945220] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1047.945331] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1047.945450] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1047.945574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1047.945699] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1047.945809] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1047.946328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1047.946381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1047.946431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1047.946480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1047.946531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1047.946580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1047.946633] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1047.946808] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1047.946861] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1047.957385] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1047.957443] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1047.957697] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1047.959686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.959763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.959840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.962634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.962723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.964549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.966277] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1047.967147] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.984232] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1047.984326] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1047.984441] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.018339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.018764] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1048.035647] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1048.035780] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1048.036021] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1048.036246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.036368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.036484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.036587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.036690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.036792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.036899] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.037008] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.037300] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.037406] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.040700] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.075803] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1048.075909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1048.076017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1048.076180] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1048.076291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1048.076395] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1048.076496] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1048.076596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1048.076691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1048.076786] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1048.076879] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1048.076898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.076986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1048.077003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.077151] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1048.077270] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1048.077384] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1048.077499] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1048.077605] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1048.077721] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1048.077823] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1048.077935] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1048.078038] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1048.078169] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1048.078287] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1048.078397] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1048.078504] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1048.078608] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1048.078723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.078847] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1048.078958] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1048.079667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.079778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.079883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.079990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.080093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.080236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.080355] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.080595] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.080722] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.090516] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1048.090582] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1048.090783] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1048.092745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1048.092801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1048.092857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1048.095391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1048.095446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1048.097220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1048.099287] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1048.100180] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1048.117252] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.117335] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.117495] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.151146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.151488] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1048.168641] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1048.170333] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1048.170570] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1048.170716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.170809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.170904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.170992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.171080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.171218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.171324] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.171431] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.171651] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.171746] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.173941] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.208748] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1048.208853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1048.208960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1048.209058] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1048.209212] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1048.209326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1048.209429] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1048.209525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1048.209622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1048.209714] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1048.209806] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1048.209829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.209919] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1048.209934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.210027] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1048.210148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1048.210254] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1048.210355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1048.210457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1048.210562] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1048.210653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1048.210750] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1048.210842] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1048.210935] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1048.211025] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1048.211142] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1048.211248] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1048.211351] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1048.211457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.211568] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1048.211666] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1048.212057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.212129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.212185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.212241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.212302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.212358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.212415] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.212595] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.212648] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.223840] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1048.223901] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1048.224115] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1048.226106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1048.226160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1048.226238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1048.228784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1048.228836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1048.230653] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1048.232308] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1048.233280] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1048.250499] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.250643] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.250824] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.284814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.285392] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1048.302461] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1048.302593] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1048.302836] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1048.302994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.303099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.303285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.303398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.303514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.303616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.303730] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.303841] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.304073] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.304211] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.307242] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.342176] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1048.342293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1048.342414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1048.342524] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1048.342626] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1048.342733] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1048.342843] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1048.342949] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1048.343053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1048.343210] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1048.343330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1048.343360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.343468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1048.343490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.343597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1048.343698] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1048.343815] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1048.343919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1048.344023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1048.344167] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1048.344284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1048.344397] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1048.344501] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1048.344606] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1048.344710] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1048.344814] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1048.344921] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1048.345025] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1048.345152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.345228] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1048.345287] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1048.345664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.345722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.345778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.345834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.345888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.345944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.346001] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.346231] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.346289] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.357069] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1048.357181] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1048.357424] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1048.359382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1048.359460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1048.359538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1048.361283] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1048.361358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1048.363225] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1048.365129] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1048.366175] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1048.383269] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.383358] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.383524] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.417375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.417803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.418443] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1048.435615] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1048.437961] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1048.438294] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1048.438460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.438569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.438678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.438779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.438880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.438980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.439084] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.439223] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.439464] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.439569] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.440330] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.475059] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1048.475177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1048.475273] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1048.475361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1048.475444] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1048.475532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1048.475620] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1048.475706] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1048.475790] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1048.475870] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1048.475949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1048.475963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.476042] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1048.476111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.476194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1048.476289] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1048.476379] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1048.476468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1048.476563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1048.476663] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1048.476746] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1048.476841] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1048.476925] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1048.477009] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1048.477140] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1048.477257] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1048.477365] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1048.477470] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1048.477584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.477712] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1048.477820] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1048.479295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.479359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.479418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.479477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.479535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.479592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.479652] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.479834] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.479893] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.490277] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1048.490345] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1048.490550] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1048.492578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1048.492634] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1048.492692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1048.495577] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1048.495665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1048.497555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1048.499312] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1048.500192] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1048.517314] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.517435] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.517581] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.551339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.551712] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1048.568304] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1048.568423] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1048.568651] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1048.568792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.568883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.568976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.569064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.569228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.569326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.569430] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.569532] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.569751] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.569843] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.573593] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.608287] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1048.608366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1048.608449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1048.608522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1048.608591] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1048.608666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1048.608739] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1048.608811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1048.608881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1048.608948] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1048.609013] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1048.609078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.609148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1048.609157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.609225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1048.609302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1048.609380] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1048.609456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1048.609535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1048.609621] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1048.609692] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1048.609765] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1048.609842] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1048.609910] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1048.609980] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1048.610049] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1048.610180] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1048.610270] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1048.610372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.610496] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1048.610594] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1048.610985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.611090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.611228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.611323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.611417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.611508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.611606] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.611833] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.611928] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.623434] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1048.623503] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1048.623712] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1048.625722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1048.625810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1048.625895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1048.628695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1048.628793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1048.630623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1048.632134] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1048.632988] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1048.650075] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.650203] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.650332] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.683943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.684403] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1048.702362] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1048.704621] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1048.704871] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1048.705032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.705203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.705328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.705431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.705532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.705635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.705739] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.705850] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.706082] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.706230] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.723506] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.758440] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1048.758558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1048.758673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1048.758782] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1048.758885] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1048.758993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1048.759100] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1048.759261] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1048.759382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1048.759496] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1048.759603] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1048.759627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.759726] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1048.759754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.759855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1048.759969] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1048.760072] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1048.760198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1048.760267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1048.760344] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1048.760413] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1048.760492] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1048.760568] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1048.760637] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1048.760706] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1048.760774] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1048.760845] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1048.760911] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1048.760988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.761091] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1048.761172] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1048.761621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.761692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.761762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.761830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.761898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.761966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.762036] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.762286] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.762357] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.773492] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1048.773598] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1048.773869] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1048.775864] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1048.775952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1048.776040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1048.778891] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1048.778988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1048.780867] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1048.782296] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1048.783377] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1048.800457] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.800556] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.800678] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.834434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.834764] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1048.851393] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1048.851500] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1048.851718] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1048.851845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.851929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.852014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.852167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.852257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.852347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.852434] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.852522] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.852734] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.852818] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.856700] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.891063] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1048.891171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1048.891256] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1048.891336] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1048.891410] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1048.891491] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1048.891570] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1048.891648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1048.891723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1048.891796] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1048.891868] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1048.891882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.891953] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1048.891963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1048.892036] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1048.892159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1048.892246] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1048.892328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1048.892407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1048.892498] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1048.892584] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1048.892666] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1048.892741] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1048.892824] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1048.892901] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1048.892977] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1048.893072] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1048.893192] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1048.893303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.893415] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1048.893513] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1048.893898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.894005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.894253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.894352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.894445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.894538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.894633] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.894856] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.894952] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1048.906610] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1048.906673] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1048.906873] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1048.908915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1048.909001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1048.909126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1048.911797] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1048.911880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1048.913717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1048.915298] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1048.916381] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1048.933491] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.933607] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1048.933804] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.967469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.967912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1048.968567] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1048.985839] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1048.988203] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1048.988453] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1048.988614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1048.988718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1048.988824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1048.988924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1048.989025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1048.989200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1048.989318] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1048.989437] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1048.989715] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1048.989821] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.006589] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.041381] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1049.041500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1049.041622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1049.041731] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1049.041834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1049.041943] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1049.042052] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1049.042217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1049.042337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1049.042452] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1049.042562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1049.042587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.042687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1049.042716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.042820] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1049.042934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1049.043041] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1049.043174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1049.043279] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1049.043395] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1049.043511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1049.043624] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1049.043727] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1049.043833] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1049.043937] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1049.044041] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1049.044174] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1049.044292] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1049.044415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.044539] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1049.044650] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1049.045064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.045130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.045184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.045242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.045296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.045345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.045396] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.045576] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.045629] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.056449] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1049.056535] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1049.056775] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1049.058719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1049.058799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1049.058877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1049.061659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1049.061748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1049.063567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1049.065317] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1049.066336] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1049.083472] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.083589] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.083788] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.117331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.117754] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1049.134884] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1049.135017] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1049.135337] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1049.135501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.135611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.135724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.135827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.135931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.136033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.136169] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.136289] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.136529] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.136636] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.139857] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.174899] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1049.175018] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1049.175201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1049.175331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1049.175440] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1049.175550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1049.175661] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1049.175768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1049.175878] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1049.175983] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1049.176088] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1049.176141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.176241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1049.176275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.176385] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1049.176502] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1049.176611] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1049.176714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1049.176820] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1049.176932] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1049.177032] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1049.177168] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1049.177288] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1049.177395] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1049.177497] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1049.177596] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1049.177701] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1049.177802] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1049.177918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.178044] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1049.178227] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1049.178465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.178525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.178581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.178634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.178687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.178738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.178794] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.178973] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.179026] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.189703] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1049.189763] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1049.189964] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1049.191987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1049.192058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1049.192158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1049.194766] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1049.194835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1049.196663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1049.198295] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1049.199357] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1049.216459] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.216535] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.216634] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.248304] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1049.248403] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1049.250241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.250622] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1049.267193] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1049.267326] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1049.267566] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1049.267722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.267827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.267931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.268031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.268217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.268327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.268445] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.268562] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.268794] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.268898] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.273057] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.307513] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1049.307608] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1049.307706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1049.307794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1049.307876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1049.307965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1049.308052] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1049.308188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1049.308286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1049.308377] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1049.308464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1049.308482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.308563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1049.308586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.308667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1049.308755] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1049.308839] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1049.308925] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1049.309007] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1049.309159] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1049.309271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1049.309387] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1049.309491] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1049.309595] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1049.309697] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1049.309803] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1049.309910] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1049.310013] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1049.310153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.310292] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1049.310402] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1049.310828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.310947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.311059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.311300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.311404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.311510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.311620] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.311857] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.311967] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.322930] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1049.322991] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1049.323354] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1049.325273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1049.325351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1049.325431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1049.328025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1049.328124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1049.330015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1049.332081] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1049.332910] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1049.349979] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.350124] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.350299] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.383944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.384356] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1049.401389] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1049.403336] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1049.403572] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1049.403717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.403809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.403903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.403991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.404078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.404221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.404323] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.404429] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.404653] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.404747] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.406300] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.440546] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1049.440625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1049.440702] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1049.440775] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1049.440843] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1049.440916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1049.440989] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1049.441061] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1049.441175] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1049.441255] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1049.441329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1049.441349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.441415] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1049.441428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.441495] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1049.441575] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1049.441651] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1049.441720] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1049.441789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1049.441867] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1049.441935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1049.442007] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1049.442099] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1049.442176] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1049.442254] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1049.442324] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1049.442394] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1049.442463] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1049.442542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.442628] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1049.442700] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1049.443028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.443166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.443276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.443380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.443479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.443562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.443623] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.443810] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.443874] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.456225] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1049.456320] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1049.456575] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1049.458635] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1049.458723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1049.458808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1049.461633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1049.461729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1049.463569] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1049.465289] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1049.466137] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1049.483288] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.483412] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.483621] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.517203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.517649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.518085] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1049.535064] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1049.535224] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1049.535466] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1049.535623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.535728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.535834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.535933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.536030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.536183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.536301] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.536420] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.536656] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.536760] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.539552] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.574331] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1049.574438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1049.574546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1049.574644] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1049.574735] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1049.574833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1049.574929] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1049.575021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1049.575160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1049.575266] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1049.575365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1049.575392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.575484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1049.575499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.575592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1049.575701] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1049.575798] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1049.575892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1049.575982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1049.576085] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1049.576204] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1049.576301] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1049.576403] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1049.576503] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1049.576595] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1049.576687] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1049.576782] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1049.576874] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1049.576978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.577090] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1049.577248] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1049.577747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.577801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.577855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.577906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.577958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.578009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.578080] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.578288] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.578358] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.589379] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1049.589439] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1049.589638] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1049.591704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1049.591781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1049.591859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1049.594457] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1049.594534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1049.596363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1049.598369] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1049.599396] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1049.616509] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.616583] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.616679] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.650489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.650822] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1049.668647] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1049.668755] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1049.668973] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1049.669168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.669262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.669357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.669440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.669521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.669605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.669688] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.669776] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.669984] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.670070] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.672692] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.707793] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1049.707900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1049.708008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1049.708171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1049.708282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1049.708384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1049.708483] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1049.708582] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1049.708678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1049.708774] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1049.708866] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1049.708887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.708976] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1049.708993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.709105] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1049.709239] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1049.709357] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1049.709471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1049.709583] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1049.709705] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1049.709810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1049.709920] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1049.710024] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1049.710154] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1049.710266] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1049.710376] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1049.710484] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1049.710589] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1049.710707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.710833] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1049.710942] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1049.711420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.711473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.711524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.711573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.711625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.711673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.711726] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.711865] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.711917] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.722519] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1049.722577] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1049.722770] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1049.724687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1049.724762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1049.724833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1049.727617] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1049.727699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1049.729538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1049.731275] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1049.732191] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1049.749335] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.749449] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.749597] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.783382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.783815] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1049.800298] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1049.800429] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1049.800669] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1049.800826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.800929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.801034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.801214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.801325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.801439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.801547] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.801657] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.801894] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.801998] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.805984] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.840901] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1049.841021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1049.841213] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1049.841335] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1049.841449] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1049.841561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1049.841677] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1049.841786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1049.841895] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1049.841997] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1049.842134] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1049.842170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.842282] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1049.842305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.842407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1049.842519] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1049.842623] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1049.842727] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1049.842828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1049.842945] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1049.843047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1049.843185] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1049.843304] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1049.843419] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1049.843523] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1049.843626] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1049.843733] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1049.843837] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1049.843955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.844080] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1049.844252] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1049.844608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.844661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.844712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.844762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.844815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.844867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.844921] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.845122] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.845179] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.855826] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1049.855887] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1049.856136] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1049.858128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1049.858206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1049.858284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1049.860898] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1049.860973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1049.862802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1049.864323] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1049.865344] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1049.882453] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.882527] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.882623] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.916749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.917171] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1049.934406] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1049.934525] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1049.934752] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1049.934894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.934987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.935081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.935237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.935337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.935436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.935529] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1049.935624] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.935839] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.935928] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.939014] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1049.973630] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1049.973732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1049.973834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1049.973933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1049.974025] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1049.974161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1049.974265] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1049.974366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1049.974457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1049.974549] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1049.974636] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1049.974655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.974743] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1049.974755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1049.974847] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1049.974935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1049.975025] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1049.975149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1049.975247] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1049.975353] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1049.975448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1049.975547] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1049.975635] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1049.975725] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1049.975811] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1049.975900] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1049.975988] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1049.976079] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1049.976202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1049.976315] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1049.976409] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1049.976785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1049.976890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1049.976983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1049.977076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1049.977191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1049.977278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1049.977370] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1049.977587] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1049.977677] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1049.988941] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1049.989040] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1049.989341] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1049.991312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1049.991406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1049.991500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1049.994169] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1049.994260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1049.996130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1049.998301] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1049.999432] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1050.016517] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.016598] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.016703] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.050295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.050682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.051099] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1050.068592] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1050.070823] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1050.071073] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1050.071274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.071381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.071495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.071596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.071700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.071801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.071907] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.072013] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.072277] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.072380] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.088953] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.122553] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1050.122587] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1050.122622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1050.122654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1050.122685] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1050.122717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1050.122748] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1050.122779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1050.122809] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1050.122839] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1050.122867] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1050.122875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.122904] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1050.122908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.122938] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1050.122967] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1050.122997] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1050.123026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1050.123089] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1050.123126] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1050.123161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1050.123409] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1050.123440] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1050.123472] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1050.123504] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1050.123536] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1050.123568] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1050.123600] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1050.123634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.123673] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1050.123705] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1050.123834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.123871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.123907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.123942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.123975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.124008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.124058] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.124121] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.124154] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.138759] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1050.138809] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1050.138991] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1050.140878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1050.140928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1050.140977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1050.143500] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1050.143549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1050.145308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1050.147068] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1050.147894] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1050.164997] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.165095] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.165198] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.198690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.198899] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1050.217292] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1050.219336] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1050.219545] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1050.219656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.219726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.219798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.219864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.219929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.219995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.220062] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.220170] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.220735] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.220822] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.222254] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.257348] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1050.257455] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1050.257562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1050.257660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1050.257752] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1050.257847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1050.257945] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1050.258040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1050.258183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1050.258290] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1050.258389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1050.258415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.258508] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1050.259119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.259226] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1050.259328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1050.259426] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1050.259521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1050.259614] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1050.259721] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1050.259813] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1050.259912] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1050.260003] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1050.260170] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1050.260288] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1050.260400] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1050.260514] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1050.260623] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1050.260739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.260865] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1050.260975] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1050.261524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.261586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.261645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.261703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.261762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.261820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.261879] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.262087] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.262188] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.272224] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1050.272293] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1050.272502] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1050.274447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1050.274508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1050.274570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1050.277171] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1050.277230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1050.279098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1050.281281] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1050.282205] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1050.299314] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.299405] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.299575] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.333378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.333809] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1050.350716] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1050.350848] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1050.351088] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1050.351323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.351444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.351558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.351662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.351767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.351868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.351974] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.352084] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.352345] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.352449] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.355526] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.390485] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1050.390604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1050.390724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1050.390833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1050.390936] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1050.391042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1050.391212] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1050.391333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1050.391449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1050.391558] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1050.391663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1050.391695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.391794] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1050.391821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.391922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1050.392034] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1050.392166] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1050.392271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1050.392381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1050.392499] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1050.392601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1050.392713] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1050.392816] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1050.392922] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1050.393023] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1050.393153] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1050.393275] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1050.393389] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1050.393507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.393633] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1050.393743] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1050.394168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.394223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.394276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.394325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.394375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.394424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.394475] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.394651] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.394703] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.405378] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1050.405456] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1050.405682] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1050.407657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1050.407727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1050.407796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1050.410367] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1050.410435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1050.412233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1050.414310] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1050.415166] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1050.432293] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.432386] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.432556] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.466393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.466822] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1050.483417] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1050.483550] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1050.483791] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1050.483949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.484054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.484239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.484352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.484468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.484570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.484683] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.484793] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.485025] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.485163] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.488666] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.523709] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1050.523828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1050.523949] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1050.524058] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1050.524221] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1050.524346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1050.524465] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1050.524573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1050.524682] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1050.524786] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1050.524889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1050.524912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.525012] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1050.525058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.525168] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1050.525281] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1050.525399] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1050.525504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1050.525608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1050.525719] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1050.525823] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1050.525937] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1050.526041] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1050.526168] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1050.526287] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1050.526398] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1050.526507] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1050.526610] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1050.526726] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.526850] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1050.526957] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1050.527418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.527471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.527521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.527570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.527619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.527667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.527716] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.527855] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.527907] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.538517] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1050.538574] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1050.538765] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1050.540689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1050.540771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1050.540849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1050.543630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1050.543719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1050.545548] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1050.547316] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1050.548161] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1050.565311] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.565432] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.565586] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.599092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.599565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.599964] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1050.616173] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1050.616305] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1050.616546] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1050.616702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.616806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.616910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.617009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.617191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.617301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.617418] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.617532] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.617763] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.617868] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.621955] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.656708] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1050.656826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1050.656947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1050.657057] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1050.657228] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1050.657356] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1050.657472] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1050.657913] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1050.658021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1050.658160] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1050.658271] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1050.658299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.658398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1050.658805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.658913] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1050.659016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1050.659157] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1050.659276] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1050.659384] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1050.659499] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1050.659607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1050.659712] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1050.659817] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1050.659926] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1050.660034] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1050.660168] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1050.660228] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1050.660285] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1050.660346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.660411] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1050.660467] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1050.660715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.660773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.660831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.660884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.660937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.660989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.661041] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.661245] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.661302] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.671856] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1050.671945] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1050.672499] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1050.674527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1050.674605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1050.674681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1050.677452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1050.677536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1050.679322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1050.681277] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1050.682124] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1050.699205] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.699303] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.699426] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.733089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.733534] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1050.750608] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1050.752335] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1050.752572] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1050.752716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.752810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.752904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.752992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.753080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.753219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.753325] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.753430] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.753649] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.753741] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.755220] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.789557] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1050.789629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1050.789706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1050.789774] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1050.789838] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1050.789906] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1050.789975] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1050.790041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1050.790149] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1050.790224] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1050.790293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1050.790313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.790374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1050.790387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.790449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1050.790526] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1050.790592] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1050.790656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1050.790719] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1050.790790] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1050.790854] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1050.790926] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1050.790989] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1050.791075] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1050.791184] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1050.791280] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1050.791371] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1050.791461] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1050.791555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.791658] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1050.791746] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1050.792094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.792304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.792391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.792477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.792561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.792644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.792729] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.793015] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.793092] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.805070] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1050.805170] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1050.805373] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1050.807362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1050.807447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1050.807534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1050.810163] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1050.810244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1050.812108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1050.814297] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1050.815374] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1050.832434] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.832520] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.832631] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.866425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.866862] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1050.883868] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1050.884000] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1050.884321] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1050.884485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.884594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.884706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.884809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.884913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.885015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.885150] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.885267] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.885504] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.885609] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.888439] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.923137] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1050.923283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1050.923401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1050.923510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1050.923614] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1050.923722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1050.923831] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1050.923933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1050.924036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1050.924203] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1050.924316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1050.924349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.924456] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1050.924478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1050.924583] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1050.924687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1050.924798] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1050.924897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1050.924998] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1050.925138] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1050.925254] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1050.925361] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1050.925465] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1050.925566] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1050.925670] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1050.925773] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1050.925881] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1050.925983] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1050.926098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.926249] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1050.926374] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1050.926823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1050.926945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1050.927054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1050.927258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1050.927314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1050.927363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1050.927413] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1050.927588] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.927641] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1050.938265] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1050.938322] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1050.938524] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1050.940586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1050.940663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1050.940742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1050.943582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1050.943671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1050.945502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1050.947330] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1050.948360] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1050.965432] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1050.965516] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1050.965621] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1050.999509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1050.999884] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1051.016408] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1051.018365] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1051.018615] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1051.018775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.018879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.018985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.019085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.019236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.019353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.019467] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.019582] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.019816] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.019921] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.021599] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.055824] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1051.055898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1051.055976] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1051.056044] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1051.056146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1051.056223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1051.056297] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1051.056366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1051.056438] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1051.056502] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1051.056567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1051.056581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.056645] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1051.056655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.056719] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1051.056782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1051.056846] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1051.056911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1051.056975] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1051.057065] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1051.057223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1051.057330] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1051.057422] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1051.057515] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1051.057603] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1051.057686] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1051.057772] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1051.057855] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1051.057947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.058049] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1051.058156] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1051.058742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.058831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.058917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.059003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.059133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.059227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.059313] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.059546] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.059628] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.071434] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1051.071494] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1051.071747] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1051.073885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1051.073976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1051.074063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1051.076920] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1051.077016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1051.078893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1051.080296] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1051.081312] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1051.098383] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.098452] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.098544] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.132227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.132556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.132934] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1051.149420] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1051.149539] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1051.149768] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1051.149908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.150001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.150172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.150273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.150375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.150465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.150568] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.150666] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.150884] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.150977] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.154823] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.189072] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1051.189180] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1051.189258] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1051.189331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1051.189399] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1051.189471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1051.189542] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1051.189610] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1051.189678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1051.189744] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1051.189809] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1051.189822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.189887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1051.189896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.189963] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1051.190028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1051.190129] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1051.190208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1051.190282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1051.190361] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1051.190438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1051.190515] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1051.190590] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1051.190660] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1051.190728] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1051.190801] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1051.190871] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1051.190940] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1051.191016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.191118] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1051.191198] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1051.191507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.191607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.191703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.191798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.191890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.191981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.192078] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.192334] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.192428] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.204739] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1051.204818] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1051.205047] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1051.207034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1051.207152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1051.207246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1051.209987] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1051.210089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1051.212265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1051.214282] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1051.215132] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1051.232219] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.232302] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.232410] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.265896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.266377] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1051.284170] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1051.284289] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1051.284518] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1051.284659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.284751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.284845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.284933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.285021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.285181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.285283] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.285390] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.285613] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.285707] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.288013] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.322807] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1051.322893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1051.322982] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1051.323062] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1051.323187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1051.323280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1051.323366] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1051.323447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1051.323533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1051.323610] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1051.323686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1051.323706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.323779] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1051.323791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.323867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1051.323942] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1051.324018] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1051.324152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1051.324260] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1051.324372] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1051.324476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1051.324575] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1051.324667] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1051.324760] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1051.324851] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1051.324944] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1051.325038] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1051.325152] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1051.325268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.325389] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1051.325488] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1051.325970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.326035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.326110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.326169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.326233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.326293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.326353] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.326538] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.326593] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.337984] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1051.338080] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1051.338389] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1051.340403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1051.340489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1051.340575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1051.343182] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1051.343265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1051.345124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1051.347280] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1051.348128] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1051.365228] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.365312] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.365420] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.399168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.399524] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1051.416192] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1051.416310] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1051.416539] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1051.416679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.416771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.416864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.416951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.417038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.417200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.417301] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.417408] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.417629] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.417723] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.421340] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.456270] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1051.456389] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1051.456510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1051.456620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1051.456725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1051.456831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1051.456940] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1051.457045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1051.457216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1051.457336] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1051.457447] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1051.457476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.457579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1051.457597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.457710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1051.457817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1051.457923] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1051.458027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1051.458161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1051.458287] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1051.458391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1051.458501] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1051.458605] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1051.458710] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1051.458814] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1051.458918] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1051.459025] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1051.459156] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1051.459282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.459418] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1051.459530] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1051.459937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.459991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.460040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.460106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.460152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.460204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.460256] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.460403] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.460451] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.471230] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1051.471316] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1051.471556] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1051.473515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1051.473591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1051.473669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1051.476364] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1051.476447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1051.478273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1051.480306] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1051.481326] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1051.498424] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.498505] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.498605] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.532542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.532871] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1051.550565] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1051.552885] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1051.553197] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1051.553354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.553451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.553551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.553643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.553738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.553833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.553931] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.554028] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.554317] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.554409] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.571203] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.606120] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1051.606278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1051.606399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1051.606510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1051.606613] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1051.606720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1051.606829] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1051.606935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1051.607039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1051.607201] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1051.607299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1051.607324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.607410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1051.607425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.607510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1051.607593] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1051.607685] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1051.607768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1051.607851] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1051.607949] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1051.608035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1051.608145] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1051.608240] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1051.608331] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1051.608416] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1051.608501] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1051.608586] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1051.608669] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1051.608764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.608865] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1051.608953] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1051.609311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.609409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.609499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.609583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.609666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.609748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.609835] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.610167] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.610255] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.621094] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1051.621241] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1051.621496] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1051.623507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1051.623592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1051.623678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1051.626343] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1051.626434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1051.628289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1051.630319] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1051.631171] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1051.648257] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.648327] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.648419] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.682362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.682794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.683221] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1051.700400] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1051.700519] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1051.700747] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1051.700887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.700979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.701073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.701228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.701332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.701431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.701528] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.702043] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.702335] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.702440] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.704375] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.738923] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1051.739009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1051.739146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1051.739240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1051.739319] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1051.739399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1051.739480] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1051.739561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1051.739638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1051.739715] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1051.739792] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1051.739812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.739884] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1051.739896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.739973] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1051.740049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1051.740191] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1051.740299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1051.740402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1051.740510] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1051.740613] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1051.740715] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1051.740807] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1051.740899] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1051.740993] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1051.741084] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1051.741203] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1051.741306] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1051.741415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.741525] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1051.741623] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1051.742011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.742141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.742243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.742350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.742450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.742540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.742635] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.742858] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.742953] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.754289] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1051.754356] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1051.754558] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1051.756589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1051.756666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1051.756745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1051.759447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1051.759530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1051.761506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1051.763304] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1051.764321] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1051.781423] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.781507] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.781615] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.815491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.815869] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1051.832384] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1051.834336] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1051.834572] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1051.834716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.834810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.834906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.834994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.835083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.835220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.835327] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.835433] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.835653] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.835747] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.837565] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.872871] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1051.872989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1051.873104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1051.873275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1051.873397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1051.873514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1051.873625] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1051.873736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1051.873848] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1051.873952] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1051.874058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1051.874111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.874211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1051.874242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1051.874355] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1051.874468] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1051.874572] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1051.874677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1051.874778] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1051.874894] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1051.874996] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1051.875134] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1051.875252] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1051.875367] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1051.875471] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1051.875574] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1051.875682] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1051.875783] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1051.875900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.876026] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1051.876164] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1051.876429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.876486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.876538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.876591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.876640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.876690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.876744] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.876920] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.876972] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.887495] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1051.887553] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1051.887746] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1051.889811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1051.889891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1051.889971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1051.892756] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1051.892845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1051.894662] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1051.896332] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1051.897352] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1051.914529] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.914652] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1051.914854] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.948655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1051.949131] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1051.966414] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1051.966548] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1051.966788] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1051.966944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1051.967049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1051.967229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1051.967346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1051.967458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1051.967559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1051.967673] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1051.967782] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1051.968013] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1051.968159] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1051.970863] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.005648] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1052.005756] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1052.005863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1052.005961] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1052.006053] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1052.006214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1052.006324] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1052.006427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1052.006522] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1052.006624] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1052.006716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1052.006737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.006826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1052.006841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.006934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1052.007026] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1052.007175] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1052.007287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1052.007400] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1052.007519] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1052.007623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1052.007733] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1052.007838] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1052.007943] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1052.008047] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1052.008178] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1052.008296] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1052.008408] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1052.008526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.008651] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1052.008758] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1052.009179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.009300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.009411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.009523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.009641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.009758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.009867] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.010148] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.010257] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.020723] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1052.020790] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1052.020995] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1052.022979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1052.023036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1052.023126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1052.025678] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1052.025734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1052.027519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1052.029272] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1052.030162] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1052.047254] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.047324] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.047416] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.081380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.081749] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1052.098367] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1052.100338] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1052.100587] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1052.100748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.100852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.100959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.101060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.101220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.101336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.101450] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.101562] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.101795] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.101900] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.104064] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.138532] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1052.138639] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1052.138746] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1052.138843] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1052.138935] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1052.139032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1052.139182] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1052.139291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1052.139394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1052.139490] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1052.139584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1052.139611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.139699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1052.139723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.139813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1052.139914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1052.140005] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1052.140125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1052.140212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1052.140316] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1052.140421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1052.140519] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1052.140613] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1052.140704] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1052.140797] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1052.140889] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1052.140982] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1052.141071] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1052.141198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.141321] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1052.141419] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1052.142026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.142102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.142158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.142210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.142259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.142307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.142357] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.142506] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.142558] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.153936] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1052.153993] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1052.154218] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1052.156244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1052.156323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1052.156402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1052.158978] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1052.159054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1052.160931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1052.162303] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1052.163272] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1052.180363] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.180442] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.180543] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.214218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.214552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.214921] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1052.231044] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1052.233327] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1052.233564] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1052.233709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.233802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.233896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.233984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.234072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.234213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.234319] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.234426] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.234646] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.234736] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.237291] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.271819] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1052.271906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1052.271996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1052.272075] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1052.272203] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1052.272297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1052.272382] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1052.272463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1052.272548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1052.272625] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1052.272701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1052.272718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.272793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1052.272804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.272881] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1052.272958] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1052.273034] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1052.273134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1052.273219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1052.273312] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1052.273398] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1052.273480] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1052.273555] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1052.273631] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1052.273706] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1052.273783] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1052.273861] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1052.273940] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1052.274022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.274173] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1052.274283] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1052.274670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.274739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.274803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.274863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.274923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.274981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.275042] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.275315] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.275377] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.287182] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1052.287251] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1052.287461] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1052.289377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1052.289439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1052.289499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1052.292246] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1052.292329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1052.294167] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1052.296310] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1052.297143] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1052.314210] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.314297] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.314410] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.347809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.348104] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1052.365260] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1052.367282] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1052.367476] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1052.367567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.367623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.367681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.367733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.367786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.367838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.367892] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.367949] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.368150] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.368211] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.370449] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.405081] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1052.405188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1052.405276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1052.405356] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1052.405431] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1052.405512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1052.405592] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1052.405670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1052.405746] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1052.405818] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1052.405889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1052.405906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.405977] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1052.405987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.406060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1052.406174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1052.406261] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1052.406343] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1052.406423] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1052.406514] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1052.406601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1052.406683] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1052.406759] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1052.406842] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1052.406917] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1052.406993] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1052.407096] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1052.407216] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1052.407315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.407428] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1052.407531] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1052.408189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.408285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.408380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.408475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.408571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.408662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.408759] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.408982] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.409079] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.420379] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1052.420459] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1052.420683] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1052.422604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1052.422669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1052.422733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1052.425347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1052.425417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1052.427212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1052.429304] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1052.430216] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1052.447330] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.447434] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.447611] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.481102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.481522] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1052.498845] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1052.501205] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1052.501454] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1052.501615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.501722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.501830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.501930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.502029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.502200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.502318] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.502436] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.502668] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.502771] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.503647] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.538505] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1052.538623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1052.538744] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1052.538856] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1052.538959] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1052.539068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1052.539245] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1052.539367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1052.539483] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1052.539592] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1052.539697] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1052.539730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.539829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1052.539856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.539957] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1052.540071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1052.540207] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1052.540311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1052.540416] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1052.540529] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1052.540635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1052.540763] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1052.540875] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1052.540980] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1052.541086] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1052.541235] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1052.541352] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1052.541461] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1052.541576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.541701] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1052.541810] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1052.542197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.542254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.542307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.542358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.542407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.542454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.542505] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.542711] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.542764] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.553601] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1052.553697] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1052.553948] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1052.555921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1052.556007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1052.556138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1052.558764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1052.558847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1052.560679] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1052.562293] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1052.563219] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1052.580379] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.580485] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.580643] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.614495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.614983] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1052.632601] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1052.634942] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1052.635270] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1052.635433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.635546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.635659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.635762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.635864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.635965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.636073] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.636212] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.636460] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.636562] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.653663] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.688396] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1052.688514] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1052.688633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1052.688740] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1052.688842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1052.688951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1052.689059] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1052.689224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1052.689344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1052.689457] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1052.689567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1052.689592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.689692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1052.689722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.689825] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1052.689935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1052.690041] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1052.690176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1052.690282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1052.690392] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1052.690499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1052.690624] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1052.690734] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1052.690838] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1052.690942] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1052.691044] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1052.691178] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1052.691293] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1052.691414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.691537] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1052.691647] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1052.692056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.692124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.692177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.692235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.692289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.692340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.692390] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.692588] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.692641] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.703471] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1052.703565] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1052.703818] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1052.705778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1052.705868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1052.705954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1052.708764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1052.708862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1052.710703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1052.712281] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1052.713150] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1052.730252] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.730324] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.730420] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.763935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.764336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.764649] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1052.781623] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1052.781741] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1052.781969] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1052.782179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.782284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.782389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.782482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.782576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.782667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.782762] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.782859] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.783079] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.783206] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.786819] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.821219] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1052.821305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1052.821395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1052.821474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1052.821549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1052.821630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1052.821711] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1052.821789] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1052.821865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1052.821938] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1052.822010] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1052.822073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.822146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1052.822171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.822251] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1052.822334] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1052.822419] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1052.822499] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1052.822574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1052.822661] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1052.822735] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1052.822812] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1052.822887] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1052.822962] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1052.823036] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1052.823136] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1052.823222] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1052.823308] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1052.823395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.823488] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1052.823568] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1052.823892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.823980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.824062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.824207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.824299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.824386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.824480] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.824769] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.824865] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.836733] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1052.836819] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1052.837063] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1052.839055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1052.839154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1052.839232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1052.841876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1052.841951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1052.843789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1052.845305] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1052.846326] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1052.863428] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.863497] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.863588] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.897370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.897801] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1052.915646] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1052.917987] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1052.918315] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1052.918482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.918595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.918706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.918810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.918913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.919015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.919148] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1052.919277] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.919519] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.919622] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.936735] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1052.971785] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1052.971903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1052.972023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1052.972210] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1052.972327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1052.972449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1052.972560] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1052.972669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1052.972777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1052.972883] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1052.972986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1052.973010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.973140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1052.973173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1052.973283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1052.973392] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1052.973495] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1052.973599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1052.973701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1052.973816] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1052.973920] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1052.974030] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1052.974161] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1052.974279] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1052.974390] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1052.974500] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1052.974606] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1052.974708] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1052.974825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1052.974952] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1052.975062] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1052.975521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1052.975570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1052.975621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1052.975670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1052.975720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1052.975769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1052.975820] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1052.975985] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1052.976035] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1052.986614] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1052.986704] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1052.986947] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1052.988912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1052.988990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1052.989068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1052.991693] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1052.991768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1052.993603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1052.995306] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1052.996327] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1053.013436] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.013523] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.013634] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.047356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.047747] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1053.064268] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1053.064387] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1053.064617] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1053.064759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.064853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.064947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.065036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.065197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.065297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.065402] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.065505] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.065726] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.065820] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.069962] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.104871] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1053.104989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1053.105109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1053.105277] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1053.105399] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1053.105515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1053.105628] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1053.105739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1053.105845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1053.105950] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1053.106054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1053.106107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.106221] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1053.106247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.106355] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1053.106459] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1053.106563] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1053.106665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1053.106770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1053.106889] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1053.106991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1053.107132] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1053.107250] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1053.107365] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1053.107475] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1053.107576] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1053.107683] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1053.107783] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1053.107900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.108026] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1053.108164] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1053.108409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.108470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.108526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.108579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.108632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.108683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.108737] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.108917] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.108972] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.119807] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1053.119869] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1053.120105] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1053.122135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1053.122213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1053.122292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1053.125011] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1053.125109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1053.127104] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1053.129314] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1053.130349] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1053.147558] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.147691] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.147868] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.181845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.182443] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1053.199646] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1053.201990] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1053.202289] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1053.202460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.202567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.202677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.202777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.202879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.202980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.203082] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.203255] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.203498] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.203604] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.219862] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.254806] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1053.254925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1053.255046] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1053.255231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1053.255347] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1053.255468] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1053.255580] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1053.255692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1053.255799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1053.255905] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1053.256009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1053.256062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.256162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1053.256194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.256307] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1053.256418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1053.256520] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1053.256625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1053.256728] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1053.256845] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1053.256949] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1053.257059] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1053.257190] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1053.257311] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1053.257426] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1053.257537] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1053.257647] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1053.257751] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1053.257870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.257997] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1053.258183] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1053.258564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.258617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.258671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.258724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.258778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.258829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.258883] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.259084] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.259145] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.269656] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1053.269742] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1053.269979] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1053.271959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1053.272038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1053.272148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1053.274749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1053.274824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1053.276644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1053.278303] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1053.279291] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1053.296384] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.296451] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.296540] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.330387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.330719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.331053] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1053.348613] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1053.350331] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1053.350566] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1053.350711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.350804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.350899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.350988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.351076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.351209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.351314] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.351420] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.352054] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.352180] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.352930] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.387578] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1053.387665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1053.387754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1053.387834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1053.387909] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1053.387989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1053.388069] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1053.388200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1053.388289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1053.388372] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1053.388450] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1053.388467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.388541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1053.388562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.388635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1053.388717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1053.388799] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1053.388878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1053.388953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1053.389039] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1053.389171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1053.389283] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1053.389382] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1053.389476] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1053.389568] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1053.389659] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1053.389754] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1053.389846] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1053.389950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.390062] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1053.390187] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1053.390585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.390689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.390788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.390881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.390975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.391067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.391193] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.391417] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.391522] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.402935] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1053.403022] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1053.403532] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1053.405605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1053.405683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1053.405761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1053.408564] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1053.408634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1053.410445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1053.412283] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1053.413224] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1053.430358] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.430468] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.430653] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.464441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.464895] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1053.481300] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1053.483349] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1053.483600] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1053.483761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.483865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.483972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.484072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.484227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.484343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.484458] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.484572] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.484808] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.484911] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.486266] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.520775] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1053.520849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1053.520925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1053.520991] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1053.521055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1053.521185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1053.521285] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1053.521379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1053.521464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1053.521556] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1053.521639] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1053.521659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.521739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1053.521753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.521837] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1053.521921] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1053.522004] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1053.522113] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1053.522204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1053.522304] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1053.522394] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1053.522482] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1053.522565] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1053.522648] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1053.522730] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1053.522812] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1053.522896] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1053.522978] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1053.523071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.523191] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1053.523290] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1053.523773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.523836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.523896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.523956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.524015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.524093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.524161] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.524352] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.524413] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.536178] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1053.536246] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1053.536458] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1053.538437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1053.538497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1053.538560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1053.541216] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1053.541290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1053.543101] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1053.545285] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1053.546218] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1053.563292] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.563383] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.563552] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.597419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.597863] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1053.614338] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1053.614470] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1053.614710] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1053.614866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.614970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.615075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.615254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.615365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.615479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.615588] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.615697] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.615939] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.616045] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.619512] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.654467] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1053.654586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1053.654706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1053.654815] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1053.654919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1053.655026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1053.655192] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1053.655313] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1053.655429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1053.655538] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1053.655649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1053.655680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.655767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1053.655792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.655882] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1053.655985] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1053.656080] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1053.656199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1053.656291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1053.656396] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1053.656503] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1053.656605] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1053.656699] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1053.656790] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1053.656880] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1053.656973] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1053.657069] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1053.657187] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1053.657304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.657422] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1053.657521] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1053.657901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.657958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.658011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.658076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.658132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.658185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.658236] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.658461] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.658513] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.669354] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1053.669411] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1053.669606] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1053.671549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1053.671599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1053.671651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1053.674518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1053.674578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1053.676388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1053.678286] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1053.679175] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1053.696324] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.696440] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.696598] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.730498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.730879] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1053.747127] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1053.747225] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1053.747435] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1053.747552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.747628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.747705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.747777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.747848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.747919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.747993] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.748071] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.748325] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.748402] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.752670] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.787510] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1053.787617] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1053.787724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1053.787821] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1053.787912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1053.788009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1053.788166] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1053.788274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1053.788377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1053.788473] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1053.788564] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1053.788591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.788678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1053.788703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.788793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1053.788894] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1053.788986] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1053.789100] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1053.789232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1053.789349] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1053.789456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1053.789564] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1053.789667] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1053.789770] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1053.789872] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1053.789976] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1053.790083] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1053.790212] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1053.790339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.790471] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1053.790582] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1053.790985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.791042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.791107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.791165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.791218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.791266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.791318] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.791549] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.791605] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.802484] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1053.802541] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1053.802735] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1053.804687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1053.804768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1053.804845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1053.807650] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1053.807739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1053.809561] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1053.811303] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1053.812325] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1053.829481] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.829612] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.829808] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.863600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.864084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.864567] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1053.881612] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1053.883950] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1053.884287] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1053.884450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.884562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.884671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.884772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.884875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.884980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.885085] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.885244] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.885479] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.885570] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.902654] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.937580] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1053.937699] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1053.937819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1053.937927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1053.938031] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1053.938201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1053.938325] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1053.938441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1053.938549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1053.938662] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1053.938767] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1053.938792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.938891] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1053.938909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1053.939013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1053.939146] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1053.939264] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1053.939380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1053.939485] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1053.939601] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1053.939703] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1053.939816] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1053.939920] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1053.940027] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1053.940156] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1053.940272] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1053.940390] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1053.940497] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1053.940615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1053.940740] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1053.940850] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1053.941241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1053.941296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1053.941349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1053.941399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1053.941450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1053.941499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1053.941550] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1053.941718] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1053.941770] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1053.952454] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1053.952512] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1053.952705] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1053.954654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1053.954707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1053.954758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1053.957650] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1053.957732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1053.959547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1053.961298] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1053.962195] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1053.979338] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1053.979463] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1053.979617] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.013024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.013425] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1054.030402] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1054.032366] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1054.032617] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1054.032779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.032884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.032991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.033091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.033253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.033364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.033481] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.033594] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.033824] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.033928] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.035790] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.070363] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1054.070437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.070514] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.070582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.070646] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.070714] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.070782] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1054.070848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1054.070913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.070974] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1054.071034] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.071094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.071157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.071174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.071242] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1054.071315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.071381] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1054.071447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.071512] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1054.071584] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1054.071648] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.071720] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1054.071783] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1054.071847] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1054.071913] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1054.071976] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1054.072057] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1054.072168] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1054.072273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.072380] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1054.072467] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1054.072812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.072910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.073000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.073219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.073306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.073389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.073476] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.073735] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.073823] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.085608] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1054.085675] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1054.085874] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1054.087808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.087893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.087976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.090639] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.090730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.092576] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.094344] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1054.095423] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1054.112533] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.112610] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.112709] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.146380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.146778] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1054.163379] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1054.163486] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1054.163704] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1054.163832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.163915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.164000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.164146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.164240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.164329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.164417] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.164504] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.164720] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.164805] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.169016] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.203632] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1054.203738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.203845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.203942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.204033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.204183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.204294] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1054.204397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1054.204492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.204590] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1054.204681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.204703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.204791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.204806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.204899] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1054.204990] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.205107] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1054.205240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.205359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1054.205482] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1054.205595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.205704] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1054.205808] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1054.205913] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1054.206015] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1054.206144] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1054.206262] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1054.206375] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1054.206489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.206613] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1054.206723] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1054.207142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.207207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.207267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.207333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.207395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.207451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.207511] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.207694] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.207754] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.218923] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1054.218991] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1054.219425] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1054.221353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.221410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.221469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.224119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.224194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.226013] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.228175] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1054.229090] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1054.246210] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.246313] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.246442] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.280197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.280577] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1054.297633] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1054.297751] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1054.297980] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1054.298179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.298286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.298393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.298487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.298580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.298672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.298768] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.298866] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.299107] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.299251] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.302308] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.336855] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1054.336964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.337073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.337229] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.337340] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.337444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.337543] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1054.337640] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1054.337736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.337831] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1054.337922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.337944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.338032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.338076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.338167] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1054.338274] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.338376] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1054.338477] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.338572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1054.338675] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1054.338767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.338864] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1054.338956] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1054.339064] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1054.339193] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1054.339310] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1054.339425] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1054.339529] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1054.339647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.339776] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1054.339886] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1054.340387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.340446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.340504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.340563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.340621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.340676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.340735] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.340917] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.340975] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.352163] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1054.352227] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1054.352431] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1054.354399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.354455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.354528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.357202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.357270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.359103] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.361294] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1054.362165] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1054.379278] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.379396] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.379595] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.413105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.413573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.413989] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1054.431442] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1054.433352] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1054.433602] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1054.433763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.433868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.433975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.434075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.434231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.434347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.434461] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.434574] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.434809] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.434917] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.452099] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.486730] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1054.486835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.486941] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.487039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.487180] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.487290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.487395] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1054.487490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1054.487585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.487679] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1054.487770] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.487792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.487879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.487896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.487988] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1054.488094] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.488229] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1054.488349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.488460] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1054.488582] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1054.488693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.488801] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1054.488904] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1054.489007] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1054.489138] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1054.489251] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1054.489362] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1054.489467] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1054.489582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.489708] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1054.489817] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1054.490293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.490411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.490525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.490631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.490738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.490838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.490944] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.491206] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.491326] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.502008] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1054.502095] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1054.502299] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1054.504279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.504336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.504420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.506906] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.506962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.508737] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.510275] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1054.511164] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1054.528292] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.528400] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.528583] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.561959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.562349] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1054.580163] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1054.580281] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1054.580509] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1054.580650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.580743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.580836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.580924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.581012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.581147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.581253] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.581358] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.581584] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.581679] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.585369] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.620430] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1054.620549] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.620671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.620780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.620883] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.620992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.621101] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1054.621277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1054.621394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.621511] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1054.621619] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.621642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.621744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.621773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.621876] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1054.621991] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.622094] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1054.622228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.622330] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1054.622455] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1054.622561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.622670] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1054.622773] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1054.622877] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1054.622978] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1054.623078] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1054.623210] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1054.623314] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1054.623425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.623547] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1054.623656] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1054.624172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.624221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.624269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.624317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.624363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.624410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.624458] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.624613] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.624662] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.635260] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1054.635346] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1054.635592] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1054.637701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.637778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.637854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.640454] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.640532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.642374] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.644344] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1054.645190] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1054.662298] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.662403] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.662576] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.696119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.696578] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1054.714367] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1054.716624] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1054.716874] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1054.717034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.717206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.717331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.717435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.717541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.717640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.717748] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.717858] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.718092] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.718223] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.735241] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.769958] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1054.770076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.770272] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.770400] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.770509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.770622] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.770735] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1054.770844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1054.770954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.771057] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1054.771193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.771234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.771344] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.771367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.771469] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1054.771584] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.771688] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1054.771793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.771896] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1054.772011] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1054.772143] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.772268] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1054.772378] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1054.772480] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1054.772584] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1054.772683] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1054.772792] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1054.772895] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1054.773012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.773150] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1054.773217] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1054.773520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.773585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.773644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.773703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.773760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.773816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.773878] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.774151] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.774209] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.785140] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1054.785226] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1054.785465] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1054.787438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.787515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.787597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.790205] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.790280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.792116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.794288] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1054.795120] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1054.812222] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.812295] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.812389] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.846163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.846508] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1054.863397] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1054.865318] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1054.865543] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1054.865672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.865756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.865840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.865919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.865997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.866075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.866206] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.866304] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.866543] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.866639] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.868427] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.903291] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1054.903397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1054.903505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1054.903602] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1054.903693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1054.903791] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1054.903887] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1054.903979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1054.904071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1054.904211] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1054.904318] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1054.904345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.904440] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1054.904458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1054.904550] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1054.904645] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1054.904750] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1054.904841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1054.904934] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1054.905036] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1054.905176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1054.905287] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:145, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1054.905406] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[ 1054.905519] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1054.905621] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1054.905726] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1054.905829] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] FB:150, fb = 64x64 format = AR24 little-endian (0x34325241)
>[ 1054.905935] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>[ 1054.906048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1054.906198] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1054.906320] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1054.906759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1054.906815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1054.906867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1054.906917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1054.906968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1054.907017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1054.907083] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1054.907354] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1054.907405] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1054.918434] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1054.918535] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1054.918790] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1054.920812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1054.920897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1054.920983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1054.923596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1054.923681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1054.925571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1054.927703] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1054.928697] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1054.945843] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1054.945940] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1054.946160] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1055.117890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1055.118062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1055.118207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1055.130571] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1055.132055] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1055.132266] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1055.132342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1055.132395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1055.132447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1055.132496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1055.132546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1055.132595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1055.132642] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1055.132701] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1055.132813] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1055.132861] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1055.134661] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1055.169052] [IGT] kms_cursor_legacy: exiting, ret=99
>[ 1055.201832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1055.202005] [drm:intel_edp_backlight_off [i915]] 
>[ 1055.408172] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1055.408314] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1055.418497] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1055.418628] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1055.418939] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1055.419053] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1055.419223] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1055.470578] [drm:wait_panel_status [i915]] Wait complete
>[ 1055.470699] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1055.472104] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1055.472244] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1055.472357] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1055.472541] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1055.472929] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1055.473049] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1055.473318] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1055.473469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1055.473581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1055.473687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1055.473794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1055.473900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1055.474006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1055.474140] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1055.474261] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1055.474368] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1055.474473] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1055.474628] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1055.476254] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1055.476376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1055.476430] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1055.476566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1055.476693] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1055.476808] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1055.476928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1055.477039] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1055.477195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1055.477316] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1055.477440] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1055.477544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.477576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1055.477692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.477727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1055.477845] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1055.477966] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1055.478131] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1055.478248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.478361] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1055.478472] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1055.478613] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.478720] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1055.478832] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1055.478944] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1055.479056] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1055.479190] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1055.479314] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1055.479428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1055.479547] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1055.479672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1055.479791] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1055.479908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1055.480024] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1055.480147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1055.480265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1055.480387] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1055.480489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.480523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1055.480638] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.480670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1055.480787] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1055.480907] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1055.481020] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1055.484116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.484160] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1055.484201] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1055.484254] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.484292] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1055.484332] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1055.484371] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1055.484411] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1055.484450] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1055.484493] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1055.484545] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1055.484585] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1055.484625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1055.484665] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1055.484702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1055.484741] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1055.484778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1055.484789] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1055.484831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1055.484842] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1055.484886] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1055.484929] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1055.484970] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1055.485009] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1055.485113] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1055.485155] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1055.485207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1055.485245] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1055.485286] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1055.485327] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1055.485368] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1055.485409] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1055.485453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1055.485506] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1055.485548] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1055.485590] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1055.485631] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1055.485676] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1055.485716] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1055.485861] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1055.485935] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1055.485979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1055.486018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1055.486067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1055.486106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1055.486144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1055.486183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1055.486222] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1055.486262] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1055.486301] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1055.486378] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1055.486421] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1055.486619] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1055.486661] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1056.032322] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1056.032392] [drm:wait_panel_status [i915]] Wait complete
>[ 1056.032448] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1056.032500] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1056.135809] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1056.135928] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1056.136022] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1056.136222] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1056.234219] [drm:wait_panel_status [i915]] Wait complete
>[ 1056.234341] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1056.234533] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1056.234648] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1056.235976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1056.236102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1056.236213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1056.236971] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1056.237073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1056.238186] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1056.238283] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1056.238878] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1056.239009] [drm:intel_edp_backlight_on [i915]] 
>[ 1056.239116] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1056.239204] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1056.239300] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1056.239402] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1056.239494] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1056.239678] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1056.239766] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1056.239998] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1056.241932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1056.242012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1056.242124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1056.244761] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1056.244849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1056.246666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1056.248327] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1056.249096] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1056.252388] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1056.252439] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1056.252604] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1056.252893] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1056.252947] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1056.254330] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1056.254379] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1056.256239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1056.256293] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1056.256337] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1056.256384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1056.256426] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1056.256471] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1056.256516] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1056.256558] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1056.273410] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1056.273507] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1056.273769] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1056.273935] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1056.274032] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1056.274198] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1056.274329] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1056.274425] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1056.274542] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1059.296386] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1059.296542] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1116.276676] [IGT] kms_cursor_legacy: executing
>[ 1116.559496] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1116.559562] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1116.559613] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1116.559660] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1116.559704] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1116.559747] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1116.559796] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1116.559843] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1116.560283] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1116.560975] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1116.560999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1116.561006] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1116.573180] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1116.573281] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1116.574296] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1116.575175] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1116.575252] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1116.575323] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1116.575390] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1116.576304] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1116.576383] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1116.583725] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1116.583919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1116.583930] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1116.583938] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1116.583946] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1116.583954] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1116.583962] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1116.583969] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1116.583977] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1116.583985] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1116.583993] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1116.584000] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1116.599858] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1116.599913] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1116.601315] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1116.601368] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1116.603329] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1116.603344] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1116.605334] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1116.605369] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1116.607340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1116.607356] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1116.607362] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1116.607706] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1116.607748] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1116.686824] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1116.686891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1116.688297] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1116.688317] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1116.688327] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1116.688397] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1116.688404] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1116.689719] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1116.689728] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1116.689733] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1116.690908] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1116.690918] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1116.690925] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1116.690932] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1116.690939] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1116.690945] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1116.690952] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1116.690958] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1116.690965] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1116.690971] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1116.690978] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1116.690984] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1116.690991] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1116.690997] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1116.691004] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1116.691033] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1116.691040] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1116.691047] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1116.691053] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1116.691060] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1116.691069] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1116.691075] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1116.691090] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1116.691104] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1116.691116] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1116.691128] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1116.691141] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1116.691158] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1116.691170] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1116.691179] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1116.691188] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1116.691195] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1116.691689] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1116.691699] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1116.691706] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1116.691713] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1116.691721] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1116.691728] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1116.691734] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1116.691743] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1116.691750] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1116.691758] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1116.691764] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1116.691771] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1116.691777] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1116.691784] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1116.691794] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1116.691801] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1116.693635] [IGT] kms_cursor_legacy: starting subtest cursorA-vs-flipA-atomic-transitions
>[ 1116.706531] [drm:drm_mode_addfb2] [FB:93]
>[ 1116.784972] [drm:drm_mode_addfb2] [FB:145]
>[ 1116.793828] [drm:drm_mode_addfb2] [FB:150]
>[ 1116.794329] [drm:drm_mode_addfb2] [FB:151]
>[ 1116.815826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1116.815874] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1116.815906] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1116.816415] [drm:intel_edp_backlight_off [i915]] 
>[ 1117.024319] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1117.024401] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1117.039896] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1117.039984] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1117.040065] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1117.092171] [drm:wait_panel_status [i915]] Wait complete
>[ 1117.092275] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1117.093015] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1117.093127] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1117.093226] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1117.093412] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1117.094187] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1117.094303] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1117.094534] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1117.094673] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1117.100742] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1117.102382] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1117.102616] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1117.102762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1117.102862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1117.102995] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1117.121543] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1117.121675] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1117.127339] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1117.127479] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1117.127726] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1117.127888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1117.128024] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1117.128235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1117.128359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1117.128477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1117.128579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1117.128684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1117.128786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1117.128900] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1117.129011] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1117.129152] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1117.129275] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1117.129387] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1117.129491] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1117.129715] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1117.129823] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1117.130353] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1117.130464] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1117.664574] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1117.664696] [drm:wait_panel_status [i915]] Wait complete
>[ 1117.664807] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1117.664914] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1117.768038] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1117.768163] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1117.768276] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1117.768470] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1117.866940] [drm:wait_panel_status [i915]] Wait complete
>[ 1117.867061] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1117.867336] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1117.867453] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1117.868806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1117.868909] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1117.869013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1117.869869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1117.869982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1117.871157] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1117.871275] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1117.872190] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1117.872340] [drm:intel_edp_backlight_on [i915]] 
>[ 1117.872450] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1117.872563] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1117.872680] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1117.872811] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1117.872916] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1117.889325] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1117.889462] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1117.889746] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1117.889973] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1117.890176] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1120.928157] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1120.928197] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1128.664948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1128.665117] [drm:intel_edp_backlight_off [i915]] 
>[ 1128.872361] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1128.872487] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1128.880401] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1128.880508] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1128.880817] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1128.880914] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1128.881012] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1128.932898] [drm:wait_panel_status [i915]] Wait complete
>[ 1128.933018] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1128.933809] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1128.933926] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1128.934038] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1128.934231] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1128.935371] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1128.935506] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1128.935748] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1128.935911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1128.936023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1128.936172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1128.936289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1128.936402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1128.936963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1128.937070] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1128.937218] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1128.937338] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1128.937686] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1128.937789] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1128.937890] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1128.938076] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1128.939196] [IGT] kms_cursor_legacy: exiting, ret=0
>[ 1128.964760] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1128.964811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1128.964833] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1128.964885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1128.964932] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1128.964976] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1128.965022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1128.965087] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1128.965131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1128.965175] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1128.965223] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1128.965262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1128.965275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1128.965319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1128.965331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1128.965376] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1128.965421] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1128.965467] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1128.965512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1128.965554] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1128.965599] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1128.965651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1128.965691] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1128.965733] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1128.965774] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1128.965816] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1128.965860] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1128.965907] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1128.965952] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1128.965999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1128.966054] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1128.966101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1128.966145] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1128.966189] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1128.966228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1128.966270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1128.966317] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1128.966357] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1128.966369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1128.966412] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1128.966425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1128.966469] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1128.966514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1128.966559] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1128.966601] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1128.966643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1128.966686] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1128.966741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1128.966779] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1128.966821] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1128.966862] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1128.966903] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1128.966944] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1128.966995] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1128.967165] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1128.967206] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1128.967247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1128.967289] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1128.967328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1128.967369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1128.967407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1128.967419] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1128.967462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1128.967474] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1128.967518] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1128.967562] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1128.967610] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1128.967650] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1128.967694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1128.967734] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1128.967788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1128.967826] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1128.967869] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1128.967910] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1128.967953] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1128.967993] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1128.968050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1128.968102] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1128.968145] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1128.968187] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1128.968230] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1128.968274] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1128.968314] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1128.968470] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1128.968543] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1128.968587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1128.968627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1128.968667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1128.968708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1128.968748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1128.968789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1128.968829] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1128.968869] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1128.968907] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1128.968986] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1128.969027] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1128.970285] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1128.970327] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1129.504350] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[ 1129.527948] [drm:wait_panel_status [i915]] Wait complete
>[ 1129.528028] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1129.528155] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1129.631321] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1129.631461] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1129.631575] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1129.631764] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1129.729744] [drm:wait_panel_status [i915]] Wait complete
>[ 1129.729878] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1129.730082] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1129.730282] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1129.731649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1129.731780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.731917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1129.732740] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1129.732868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1129.733905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1129.733996] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1129.734626] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1129.734763] [drm:intel_edp_backlight_on [i915]] 
>[ 1129.734846] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1129.734927] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1129.735021] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1129.735152] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1129.735246] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1129.735428] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1129.735516] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1129.735780] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1129.739047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1129.739155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.739245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1129.742077] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1129.742173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1129.743962] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1129.746280] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1129.747058] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1129.750387] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1129.750446] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1129.750622] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1129.750949] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1129.751011] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1129.753334] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1129.753390] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1129.755304] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1129.755335] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1129.755387] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1129.755441] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1129.755492] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1129.755545] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1129.755597] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1129.755647] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1129.772554] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1129.772661] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1129.772980] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1129.773354] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1129.773459] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1129.773620] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1129.773793] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1129.773893] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1129.774021] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1132.768382] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1132.768536] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1148.910616] [IGT] kms_cursor_legacy: executing
>[ 1149.198509] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1149.198582] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1149.198638] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1149.198690] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1149.198740] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1149.198788] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1149.198842] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1149.198893] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1149.199315] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1149.200114] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1149.200150] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1149.200160] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1149.202441] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1149.202540] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1149.203531] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1149.204394] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1149.204467] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1149.204535] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1149.204601] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1149.205488] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1149.205557] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1149.212381] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1149.212470] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1149.212475] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1149.212479] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1149.212483] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1149.212486] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1149.212490] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1149.212493] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1149.212497] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1149.212500] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1149.212504] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1149.212507] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1149.213449] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1149.213486] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1149.215339] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1149.215375] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1149.217440] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1149.217455] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1149.219765] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1149.219802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1149.222097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1149.222131] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1149.222139] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1149.222520] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1149.222562] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1149.301978] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1149.302056] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1149.304294] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1149.304319] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1149.304331] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1149.304416] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1149.304426] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1149.305937] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1149.305949] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1149.305957] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1149.307392] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1149.307405] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1149.307415] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1149.307425] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1149.307434] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1149.307443] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1149.307452] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1149.307462] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1149.307471] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1149.307480] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1149.307489] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1149.307498] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1149.307507] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1149.307517] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1149.307526] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1149.307535] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1149.307545] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1149.307554] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1149.307563] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1149.307572] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1149.307581] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1149.307590] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1149.307599] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1149.307608] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1149.307618] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1149.307627] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1149.307636] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1149.307645] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1149.307654] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1149.307663] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1149.307672] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1149.307681] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1149.307690] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1149.307699] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1149.307708] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1149.307717] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1149.307727] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1149.307736] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1149.307745] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1149.307754] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1149.307763] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1149.307772] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1149.307781] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1149.307790] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1149.307799] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1149.307808] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1149.307818] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1149.307827] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1149.323813] [IGT] kms_cursor_legacy: starting subtest cursorA-vs-flipB-atomic-transitions
>[ 1149.335801] [drm:drm_mode_addfb2] [FB:144]
>[ 1149.413928] [drm:drm_mode_addfb2] [FB:145]
>[ 1149.432731] [drm:drm_mode_addfb2] [FB:150]
>[ 1149.440117] [drm:drm_mode_addfb2] [FB:151]
>[ 1149.440434] [drm:drm_mode_addfb2] [FB:152]
>[ 1149.458642] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1149.458677] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1149.458710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1149.458743] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1149.458773] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1149.458805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1149.458836] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1149.458867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1149.458898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1149.458927] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1149.458956] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1149.458964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1149.458992] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1149.458996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1149.459026] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1149.459094] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1149.459126] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1149.459162] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1149.459197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1149.459235] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1149.459271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1149.459308] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] FB:134, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 1149.459340] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 1149.459375] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1149.459407] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1149.459438] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1149.459469] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1149.459503] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1149.459535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1149.459541] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1149.459574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1149.459607] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1149.459638] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1149.459671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1149.459704] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1149.459735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1149.459767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1149.459799] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1149.459831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1149.459836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1149.459867] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1149.459872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1149.459903] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1149.459935] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1149.459966] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1149.459997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1149.460028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1149.460070] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1149.460107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1149.460143] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:134, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 1149.460178] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 1149.460213] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1149.460248] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1149.460282] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1149.460318] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1149.460356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1149.460397] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL B
>[ 1149.460431] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A
>[ 1149.460464] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL A
>[ 1149.460496] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[ 1149.460945] [drm:intel_edp_backlight_off [i915]] 
>[ 1149.664334] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1149.664408] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1149.670471] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1149.670530] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1149.670583] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[ 1149.721280] [drm:wait_panel_status [i915]] Wait complete
>[ 1149.721350] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1149.723362] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1149.723466] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1149.723542] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1149.723630] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1149.723713] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1149.723831] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1149.723930] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1149.724054] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1149.732709] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1149.734303] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1149.734528] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1149.734636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1149.734726] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1149.734843] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1149.752403] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1149.752534] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1149.758340] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1149.758481] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1149.758727] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1149.758890] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1149.759029] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1149.759198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1149.759318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1149.759430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1149.759535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1149.759646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1149.759748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1149.759860] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1149.759969] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1149.760077] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1149.760236] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1149.760358] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1149.760572] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 58
>[ 1149.760681] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1149.761068] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1149.761212] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1150.304451] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1150.304573] [drm:wait_panel_status [i915]] Wait complete
>[ 1150.304685] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1150.304793] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1150.408005] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1150.408132] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1150.408244] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1150.408477] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1150.505970] [drm:wait_panel_status [i915]] Wait complete
>[ 1150.506092] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1150.506356] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1150.506478] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1150.507833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1150.507935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1150.508039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1150.508889] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1150.509004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1150.510194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1150.510312] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1150.511233] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1150.511378] [drm:intel_edp_backlight_on [i915]] 
>[ 1150.511492] [drm:intel_panel_enable_backlight [i915]] pipe B
>[ 1150.511601] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1150.511718] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1150.528304] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 42
>[ 1150.528373] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1150.528589] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1150.530597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1150.530658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1150.530720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1150.533386] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1150.533468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1150.535312] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1150.537508] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1150.538563] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1150.538695] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1150.538778] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1150.555693] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1150.555823] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1150.556010] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1150.556220] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1150.556349] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1150.556688] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1150.556977] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1153.568155] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1153.568195] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1161.349354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1161.349544] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1161.365886] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1161.367320] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1161.367408] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 42
>[ 1161.367609] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1161.367721] [drm:intel_edp_backlight_off [i915]] 
>[ 1161.576439] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1161.576576] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1161.587682] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1161.587800] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1161.588182] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1161.588288] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1161.588388] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1161.639431] [drm:wait_panel_status [i915]] Wait complete
>[ 1161.639550] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1161.641270] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1161.641384] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 58
>[ 1161.641507] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1161.641618] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1161.641727] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1161.641887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1161.641999] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1161.642148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1161.642260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1161.642365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1161.642466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1161.642569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1161.642678] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1161.642791] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1161.642905] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1161.643012] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1161.643152] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1161.643226] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1161.643404] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1161.643522] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1161.644456] [IGT] kms_cursor_legacy: exiting, ret=0
>[ 1161.668456] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1161.668505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.668527] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1161.668577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1161.668623] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1161.668666] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1161.668711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.668755] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1161.668796] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1161.668838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1161.668882] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1161.668918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.668929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1161.668971] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.668982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1161.669039] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1161.669106] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1161.669152] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1161.669445] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.669489] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.669534] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1161.669588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.669628] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1161.669670] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1161.669711] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1161.669753] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1161.669797] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1161.669842] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1161.669884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1161.669932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1161.669980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1161.670027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1161.670106] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.670164] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1161.670215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1161.670270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1161.670330] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1161.670380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.670397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1161.670452] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.670468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1161.670524] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1161.670584] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1161.670640] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1161.670696] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.670749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.670803] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1161.670870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.670922] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1161.670979] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1161.671032] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1161.671098] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1161.671158] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1161.671217] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1161.671285] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1161.671338] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1161.671392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1161.671448] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1161.671498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1161.671550] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1161.671601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1161.671617] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1161.671672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1161.671687] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1161.671743] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1161.671801] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1161.671858] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1161.671913] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1161.671966] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1161.672020] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1161.672101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1161.672153] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1161.672205] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1161.672257] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1161.672309] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1161.672362] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1161.672419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1161.672487] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1161.672543] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1161.672599] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1161.672653] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1161.672710] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1161.672764] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1161.672958] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1161.673066] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1161.673128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1161.673178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1161.673226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1161.673274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1161.673322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1161.673371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1161.673421] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1161.673472] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1161.673520] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1161.673610] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1161.673662] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1161.673937] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1161.673991] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1162.208376] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[ 1162.227379] [drm:wait_panel_status [i915]] Wait complete
>[ 1162.227493] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1162.227597] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1162.330792] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1162.330949] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1162.331074] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1162.331304] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1162.427883] [drm:wait_panel_status [i915]] Wait complete
>[ 1162.428031] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1162.428327] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1162.428474] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1162.429856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.429987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.430165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.430988] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.431155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.432213] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.432294] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1162.432834] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1162.432944] [drm:intel_edp_backlight_on [i915]] 
>[ 1162.433013] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1162.433123] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1162.433208] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1162.433293] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1162.433373] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1162.433539] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1162.433616] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1162.433832] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1162.435729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1162.435800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1162.435869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1162.438436] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1162.438504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1162.440295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1162.442516] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1162.443269] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1162.446399] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1162.446452] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1162.446619] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1162.446917] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1162.446972] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1162.449050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1162.449095] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1162.451308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1162.451363] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1162.451408] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1162.451456] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1162.451502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1162.451549] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1162.451596] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1162.451640] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1162.468580] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1162.468649] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1162.468765] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1162.468893] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1162.468961] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1162.469094] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1162.469357] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1162.469454] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1162.469577] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1165.472379] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1165.472503] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1187.755661] [IGT] kms_cursor_legacy: executing
>[ 1188.061007] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1188.061124] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1188.061210] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1188.061290] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1188.061367] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1188.061441] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1188.061523] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1188.061602] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1188.062077] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1188.062879] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1188.062919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1188.062931] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1188.078883] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1188.078940] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1188.079977] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1188.080886] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1188.080975] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1188.081059] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1188.081182] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1188.082107] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1188.082200] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1188.089622] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1188.089814] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1188.089825] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1188.089834] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1188.089842] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1188.089850] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1188.089858] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1188.089865] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1188.089873] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1188.089881] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1188.089888] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1188.089896] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1188.098147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1188.098186] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1188.100109] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1188.100142] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1188.102289] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1188.102307] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1188.104288] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1188.104347] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1188.106283] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1188.106302] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1188.106310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1188.106816] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1188.106881] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1188.185214] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1188.185292] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1188.187321] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1188.187343] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1188.187355] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1188.187429] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1188.187437] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1188.188730] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1188.188740] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1188.188747] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1188.189937] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1188.189948] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1188.189956] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1188.189964] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1188.189972] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1188.189979] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1188.189987] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1188.189995] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1188.190002] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1188.190035] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1188.190044] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1188.190051] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1188.190059] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1188.190067] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1188.190078] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1188.190086] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1188.190102] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1188.190116] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1188.190131] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1188.190148] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1188.190162] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1188.190177] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1188.190186] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1188.190196] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1188.190204] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1188.190211] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1188.190219] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1188.190229] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1188.190236] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1188.190244] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1188.190258] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1188.190272] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1188.190290] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1188.190303] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1188.190311] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1188.190318] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1188.190326] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1188.190334] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1188.190350] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1188.190364] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1188.190374] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1188.190384] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1188.190392] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1188.190402] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1188.190418] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1188.190430] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1188.190438] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1188.190445] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1188.203728] [IGT] kms_cursor_legacy: starting subtest cursorA-vs-flipB-atomic-transitions-varying-size
>[ 1188.212335] [drm:drm_mode_addfb2] [FB:143]
>[ 1188.298712] [drm:drm_mode_addfb2] [FB:145]
>[ 1188.322036] [drm:drm_mode_addfb2] [FB:150]
>[ 1188.329309] [drm:drm_mode_addfb2] [FB:151]
>[ 1188.329613] [drm:drm_mode_addfb2] [FB:152]
>[ 1188.329951] [drm:drm_mode_addfb2] [FB:156]
>[ 1188.348104] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1188.348139] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1188.348173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1188.348205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1188.348235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1188.348267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1188.348298] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1188.348329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1188.348360] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1188.348390] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1188.348419] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1188.348426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1188.348455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1188.348459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1188.348489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1188.348518] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1188.348548] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1188.348577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1188.348606] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1188.348638] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1188.348667] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1188.348697] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] FB:134, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 1188.348727] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 1188.348756] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1188.348784] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1188.348813] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1188.348841] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1188.348872] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1188.348901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1188.348906] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1188.348937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1188.348968] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1188.348997] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1188.349026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1188.349096] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1188.349128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1188.349164] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1188.349198] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1188.349233] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1188.349243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1188.349275] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1188.349285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1188.349319] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1188.349353] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1188.349387] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1188.349422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1188.349456] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1188.349493] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1188.349525] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1188.349557] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:134, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 1188.349593] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 1188.349624] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1188.349655] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1188.349686] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1188.349717] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1188.349752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1188.349794] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL B
>[ 1188.349826] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A
>[ 1188.349860] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL A
>[ 1188.349893] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[ 1188.350364] [drm:intel_edp_backlight_off [i915]] 
>[ 1188.552326] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1188.552401] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1188.562608] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1188.562668] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1188.562721] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1188.614104] [drm:wait_panel_status [i915]] Wait complete
>[ 1188.614162] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1188.615577] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1188.615634] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1188.615685] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1188.615787] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1188.616279] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1188.616347] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1188.616734] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1188.616822] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1188.633178] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1188.635309] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1188.635524] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1188.635623] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1188.635705] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1188.635814] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1188.653544] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1188.653663] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1188.671888] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1188.672004] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1188.672335] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1188.672504] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1188.672645] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1188.672759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1188.672866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1188.672970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1188.673073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1188.673210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1188.673327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1188.673443] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1188.673556] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1188.673662] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1188.673767] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1188.673871] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1188.674080] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 58
>[ 1188.674218] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1188.675065] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1188.675218] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1189.168361] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1189.168458] [drm:wait_panel_status [i915]] Wait complete
>[ 1189.168548] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1189.168635] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1189.271918] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1189.272044] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1189.272155] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1189.272395] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1189.370084] [drm:wait_panel_status [i915]] Wait complete
>[ 1189.370252] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1189.370443] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1189.370558] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1189.372209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1189.372313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1189.372417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1189.373208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1189.373318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1189.374336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1189.374399] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1189.374946] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1189.375022] [drm:intel_edp_backlight_on [i915]] 
>[ 1189.375103] [drm:intel_panel_enable_backlight [i915]] pipe B
>[ 1189.375175] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1189.375243] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1189.392044] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 42
>[ 1189.392168] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1189.392427] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1189.394451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1189.394535] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1189.394620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1189.397334] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1189.397425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1189.399274] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1189.401302] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1189.402265] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1189.402377] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1189.402446] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1189.419379] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1189.419499] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1189.419619] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1189.419744] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1189.419830] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1189.420149] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1189.420368] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1192.416117] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1192.416159] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1200.214073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1200.214396] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1200.228748] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1200.228875] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1200.228953] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 42
>[ 1200.229255] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1200.229362] [drm:intel_edp_backlight_off [i915]] 
>[ 1200.432393] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1200.432519] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1200.434363] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1200.434480] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1200.434780] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1200.434877] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1200.434975] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1200.486556] [drm:wait_panel_status [i915]] Wait complete
>[ 1200.486664] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1200.487829] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1200.487935] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1200.488035] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1200.488208] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1200.488302] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 58
>[ 1200.488526] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1200.488675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1200.488782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1200.488882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1200.488978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1200.489072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1200.489233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1200.489351] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1200.489467] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1200.489577] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1200.489686] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1200.489792] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1200.489899] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1200.490144] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1200.490319] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1200.491605] [IGT] kms_cursor_legacy: exiting, ret=0
>[ 1200.516484] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1200.516535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1200.516557] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1200.516608] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1200.516655] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1200.516698] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1200.516744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1200.516789] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1200.516831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1200.516876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1200.516921] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1200.516959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1200.516970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1200.517013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1200.517048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1200.517093] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1200.517138] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1200.517184] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1200.517227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1200.517271] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1200.517315] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1200.517369] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1200.517408] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1200.517450] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1200.517492] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1200.517537] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1200.517581] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1200.517628] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1200.517671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1200.517716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1200.517766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1200.517812] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1200.517855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1200.517897] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1200.517936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1200.517978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1200.518026] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1200.518072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1200.518089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1200.518133] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1200.518145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1200.518189] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1200.518234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1200.518277] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1200.518321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1200.518363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1200.518404] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1200.518457] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1200.518496] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1200.518537] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1200.518580] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1200.518621] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1200.518663] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1200.518713] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1200.518769] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1200.518811] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1200.518853] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1200.518893] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1200.518932] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1200.518973] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1200.519012] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1200.519032] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1200.519076] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1200.519091] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1200.519135] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1200.519180] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1200.519223] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1200.519266] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1200.519310] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1200.519352] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1200.519405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1200.519443] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1200.519485] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1200.519528] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1200.519569] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1200.519612] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1200.519661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1200.519714] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1200.519757] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1200.519800] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1200.519843] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1200.519889] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1200.519932] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1200.520100] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1200.520174] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1200.520219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1200.520259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1200.520301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1200.520342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1200.520381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1200.520420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1200.520458] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1200.520499] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1200.520541] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1200.520618] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1200.520662] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1200.520893] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1200.520936] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1201.056332] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1201.056413] [drm:wait_panel_status [i915]] Wait complete
>[ 1201.056477] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1201.056539] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1201.159788] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1201.159918] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1201.160021] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1201.160217] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1201.257413] [drm:wait_panel_status [i915]] Wait complete
>[ 1201.257525] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1201.257705] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1201.257810] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1201.259202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1201.259319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1201.259442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1201.260463] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1201.260581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1201.261748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1201.261832] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1201.262554] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1201.262674] [drm:intel_edp_backlight_on [i915]] 
>[ 1201.262747] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1201.262820] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1201.262905] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1201.263000] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1201.263110] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1201.263539] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1201.263622] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1201.263845] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1201.265741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1201.265814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1201.265889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1201.268458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1201.268531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1201.270323] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1201.272408] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1201.273146] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1201.276414] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1201.276465] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1201.276632] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1201.276922] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1201.276975] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1201.278330] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1201.278379] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1201.280105] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1201.280132] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1201.280175] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1201.280221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1201.280264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1201.280309] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1201.280355] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1201.280397] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1201.297349] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1201.297449] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1201.297763] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1201.298041] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1201.298194] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1201.298325] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1201.298477] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1201.298577] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1201.298713] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1204.320353] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1204.320478] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1221.554347] [IGT] kms_cursor_legacy: executing
>[ 1221.847553] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1221.847654] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1221.847739] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1221.847819] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1221.847895] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1221.847968] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1221.848049] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1221.848170] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1221.848615] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1221.849451] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1221.849491] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1221.849502] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1221.862623] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1221.862680] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1221.863594] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1221.864383] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1221.864416] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1221.864446] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1221.864476] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1221.865327] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1221.865358] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1221.872167] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1221.872282] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1221.872289] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1221.872294] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1221.872299] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1221.872304] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1221.872308] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1221.872313] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1221.872318] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1221.872322] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1221.872327] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1221.872331] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1221.874073] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1221.874141] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1221.876322] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1221.876358] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1221.878331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1221.878346] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1221.880331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1221.880368] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1221.882338] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1221.882353] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1221.882359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1221.882707] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1221.882749] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1221.962239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1221.962319] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1221.964520] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1221.964545] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1221.964557] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1221.964642] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1221.964652] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1221.966208] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1221.966219] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1221.966227] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1221.967621] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1221.967634] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1221.967644] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1221.967654] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1221.967663] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1221.967672] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1221.967681] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1221.967690] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1221.967700] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1221.967709] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1221.967718] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1221.967727] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1221.967736] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1221.967745] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1221.967755] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1221.967764] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1221.967773] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1221.967782] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1221.967792] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1221.967801] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1221.967810] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1221.967819] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1221.967828] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1221.967837] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1221.967847] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1221.967856] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1221.967865] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1221.967874] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1221.967883] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1221.967892] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1221.967901] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1221.967910] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1221.967919] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1221.967928] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1221.967937] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1221.967946] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1221.967955] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1221.967965] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1221.967974] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1221.967983] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1221.967992] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1221.968001] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1221.968038] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1221.968048] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1221.968057] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1221.968066] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1221.968075] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1221.968088] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1221.982153] [IGT] kms_cursor_legacy: starting subtest cursorB-vs-flipA-atomic-transitions
>[ 1221.996302] [drm:drm_mode_addfb2] [FB:137]
>[ 1222.091272] [drm:drm_mode_addfb2] [FB:145]
>[ 1222.115754] [drm:drm_mode_addfb2] [FB:150]
>[ 1222.124045] [drm:drm_mode_addfb2] [FB:151]
>[ 1222.124394] [drm:drm_mode_addfb2] [FB:152]
>[ 1222.145166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1222.145213] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1222.145245] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1222.145278] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1222.145309] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1222.145819] [drm:intel_edp_backlight_off [i915]] 
>[ 1222.352383] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1222.352461] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.362558] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1222.362646] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1222.362728] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[ 1222.413868] [drm:wait_panel_status [i915]] Wait complete
>[ 1222.413955] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1222.415340] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.415454] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1222.415636] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1222.415723] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1222.415827] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1222.415917] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1222.416015] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1222.416148] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1222.425853] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1222.427340] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1222.427575] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1222.427694] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1222.427794] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.427922] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1222.445393] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1222.445503] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1222.449316] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1222.449423] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1222.449636] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1222.449756] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1222.449863] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1222.449943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1222.450022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1222.450148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1222.450231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1222.450313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1222.450391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1222.450958] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1222.451037] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1222.451147] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1222.451232] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1222.451493] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1222.451660] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1222.451733] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1222.451970] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1222.454032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.454130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.454211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.456996] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.457067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.458835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.461168] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1222.462014] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1222.479181] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1222.479254] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1222.479610] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1222.479676] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1222.968387] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1222.968495] [drm:wait_panel_status [i915]] Wait complete
>[ 1222.968590] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1222.968685] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1223.071829] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1223.071951] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1223.072059] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1223.072244] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1223.170808] [drm:wait_panel_status [i915]] Wait complete
>[ 1223.170927] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1223.171195] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1223.171326] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1223.172658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.172761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.172862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.173684] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.173797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.174879] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.174987] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1223.175860] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.175990] [drm:intel_edp_backlight_on [i915]] 
>[ 1223.176093] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1223.176239] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1223.176365] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1223.176491] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.176596] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.192931] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1223.193039] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1223.193370] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1223.193788] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1223.193902] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1223.194038] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1223.194205] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1226.208185] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1226.208226] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1233.973531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1233.973730] [drm:intel_edp_backlight_off [i915]] 
>[ 1234.176346] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1234.176442] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1234.184376] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1234.184477] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1234.184769] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1234.184855] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1234.184941] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1234.236156] [drm:wait_panel_status [i915]] Wait complete
>[ 1234.236250] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1234.237828] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1234.237923] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1234.238010] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1234.238224] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1234.238343] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1234.238445] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1234.238728] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1234.238897] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.257994] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1234.258171] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1234.258416] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1234.258577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1234.258689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1234.258796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1234.258898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1234.258999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1234.259143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1234.259262] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1234.259382] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1234.259496] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1234.259605] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1234.259722] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1234.259828] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1234.260052] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1234.260253] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1234.261484] [IGT] kms_cursor_legacy: exiting, ret=0
>[ 1234.285871] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1234.285949] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.285982] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1234.286089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1234.286167] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1234.286239] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1234.286310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.286382] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1234.286450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1234.286521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1234.286595] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1234.286661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.286683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1234.286753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.286775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1234.286846] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1234.286919] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1234.286990] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1234.287073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.287143] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.287210] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1234.287294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.287355] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1234.287420] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1234.287488] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1234.287558] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1234.287626] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1234.287698] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1234.287765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.287838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.287913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.287984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.288070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.288141] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1234.288203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1234.288268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.288340] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1234.288400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.288422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1234.288490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.288512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1234.288581] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1234.288654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.288723] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1234.288790] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.288858] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.288923] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1234.289008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.289079] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1234.289152] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1234.289219] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1234.289283] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1234.289348] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1234.289418] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1234.289502] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1234.289567] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1234.289634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.289705] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1234.289766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1234.289833] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1234.289895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.289915] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1234.289983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.290005] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1234.290087] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1234.290162] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1234.290231] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1234.290298] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.290365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.290429] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1234.290512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.290575] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1234.290643] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1234.290707] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1234.290770] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1234.290837] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1234.290911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1234.290993] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1234.291078] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1234.291150] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1234.291216] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1234.291260] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1234.291301] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1234.291476] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1234.291546] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1234.291593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1234.291631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1234.291669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1234.291708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1234.291746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1234.291784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1234.291823] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1234.291861] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1234.291897] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1234.291964] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1234.292003] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1234.292546] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1234.292589] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1234.792386] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[ 1234.827658] [drm:wait_panel_status [i915]] Wait complete
>[ 1234.827772] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1234.827878] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1234.931104] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1234.931257] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1234.931380] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1234.931592] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1235.028739] [drm:wait_panel_status [i915]] Wait complete
>[ 1235.028872] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1235.029076] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1235.029277] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1235.030630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.030755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.030882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.031668] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.031784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.032905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.033035] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1235.033880] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1235.034059] [drm:intel_edp_backlight_on [i915]] 
>[ 1235.034259] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1235.034388] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1235.034536] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1235.034693] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1235.034842] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1235.035133] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1235.035281] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1235.035597] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1235.037667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.037796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.037925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.040558] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.040599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.042349] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.044542] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1235.045274] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1235.048411] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1235.048462] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1235.048627] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1235.048916] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.048971] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1235.050329] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1235.050379] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1235.052295] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1235.052328] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1235.052384] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1235.052443] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1235.052498] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1235.052555] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1235.052612] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1235.052667] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1235.069550] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1235.069621] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1235.069740] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1235.069885] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1235.069943] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1235.070091] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1235.070193] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1235.070264] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1235.070353] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1238.048337] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1238.048443] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1252.165785] [IGT] kms_cursor_legacy: executing
>[ 1252.230354] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1252.230434] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1252.230496] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1252.230556] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1252.230612] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1252.230667] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1252.230729] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1252.230786] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1252.231201] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1252.231964] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1252.232000] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1252.232047] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1252.236919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1252.237022] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1252.238073] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1252.239039] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1252.239140] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1252.239218] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1252.239286] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1252.240218] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1252.240253] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1252.247198] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1252.247299] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1252.247305] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1252.247309] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1252.247313] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1252.247317] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1252.247321] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1252.247325] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1252.247329] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1252.247333] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1252.247336] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1252.247340] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1252.260105] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1252.260165] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1252.262300] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1252.262340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1252.264315] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1252.264330] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1252.266308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1252.266348] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1252.268313] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1252.268329] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1252.268335] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1252.268710] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1252.268756] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1252.349378] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1252.349437] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1252.351295] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1252.351314] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1252.351323] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1252.351387] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1252.351393] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1252.352495] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1252.352505] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1252.352511] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1252.353685] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1252.353696] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1252.353704] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1252.353712] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1252.353720] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1252.353728] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1252.353735] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1252.353743] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1252.353751] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1252.353758] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1252.353766] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1252.353773] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1252.353781] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1252.353789] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1252.353797] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1252.353804] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1252.353812] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1252.353820] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1252.353828] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1252.353835] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1252.353843] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1252.353851] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1252.353858] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1252.353866] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1252.353874] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1252.353881] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1252.353889] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1252.353897] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1252.353904] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1252.353912] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1252.353919] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1252.353927] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1252.353935] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1252.353942] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1252.353950] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1252.353958] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1252.353965] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1252.353973] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1252.353981] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1252.353988] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1252.353996] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1252.354004] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1252.354036] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1252.354043] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1252.354051] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1252.354058] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1252.354066] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1252.354077] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1252.370753] [IGT] kms_cursor_legacy: starting subtest cursorB-vs-flipA-atomic-transitions-varying-size
>[ 1252.387212] [drm:drm_mode_addfb2] [FB:132]
>[ 1252.477097] [drm:drm_mode_addfb2] [FB:145]
>[ 1252.500762] [drm:drm_mode_addfb2] [FB:150]
>[ 1252.508963] [drm:drm_mode_addfb2] [FB:151]
>[ 1252.509364] [drm:drm_mode_addfb2] [FB:152]
>[ 1252.509766] [drm:drm_mode_addfb2] [FB:156]
>[ 1252.530757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1252.530805] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1252.530837] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1252.530873] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1252.530903] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1252.531535] [drm:intel_edp_backlight_off [i915]] 
>[ 1252.736339] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1252.736414] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1252.753292] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1252.753389] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1252.753477] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1252.805418] [drm:wait_panel_status [i915]] Wait complete
>[ 1252.805512] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1252.806293] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1252.806402] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1252.806493] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1252.806638] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1252.807191] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1252.807332] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1252.807558] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1252.807688] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1252.811811] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1252.813321] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1252.813557] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1252.813676] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1252.813777] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1252.813906] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1252.831356] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1252.831486] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1252.837336] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1252.837478] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1252.837724] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1252.837887] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1252.838024] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1252.838196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1252.838311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1252.838428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1252.839011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1252.839164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1252.839278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1252.839613] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1252.839721] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1252.839825] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1252.839925] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1252.840024] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1252.840743] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1252.840846] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1252.841175] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1252.843191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1252.843268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1252.843346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1252.845927] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1252.846002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1252.847855] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1252.849314] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1252.850149] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1252.867295] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1252.867375] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1252.867743] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1252.867815] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1253.360400] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1253.360507] [drm:wait_panel_status [i915]] Wait complete
>[ 1253.360602] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1253.360696] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1253.463825] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1253.463934] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1253.464031] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1253.464205] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1253.561238] [drm:wait_panel_status [i915]] Wait complete
>[ 1253.561357] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1253.561542] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1253.561651] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1253.563018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1253.563145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1253.563246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1253.564017] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1253.564161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1253.565283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1253.565401] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1253.566294] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1253.566431] [drm:intel_edp_backlight_on [i915]] 
>[ 1253.566540] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1253.566646] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1253.566761] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1253.566884] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1253.566989] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1253.583388] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1253.583523] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1253.583835] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1253.584160] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1253.584320] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1253.584473] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1253.584616] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1256.608103] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1256.608145] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1264.361570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1264.361737] [drm:intel_edp_backlight_off [i915]] 
>[ 1264.568367] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1264.568521] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1264.575236] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1264.575326] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1264.575589] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1264.575662] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1264.575736] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1264.627337] [drm:wait_panel_status [i915]] Wait complete
>[ 1264.627435] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1264.628613] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1264.628709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1264.628800] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1264.628950] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1264.629407] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1264.629523] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1264.629801] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1264.629968] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1264.643928] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1264.645304] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1264.645504] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1264.645606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1264.645672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1264.645736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1264.645795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1264.645855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1264.645913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1264.645974] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1264.646037] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1264.646142] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1264.646211] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1264.646273] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1264.646336] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1264.646855] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1264.646951] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1264.647770] [IGT] kms_cursor_legacy: exiting, ret=0
>[ 1264.674210] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1264.674260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.674282] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1264.674331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1264.674378] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1264.674421] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1264.674470] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.674515] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1264.674557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1264.674601] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1264.674646] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1264.674684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.674695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1264.674738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.674749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1264.674793] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1264.674837] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1264.674879] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1264.674919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.674960] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.675005] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1264.675082] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.675122] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1264.675165] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1264.675207] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1264.675247] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1264.675289] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1264.675332] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1264.675374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1264.675418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1264.675464] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1264.675510] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1264.675555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.675602] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1264.675641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1264.675683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1264.675730] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1264.675770] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.675783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1264.675825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.675838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1264.675882] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1264.675926] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1264.675971] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1264.676015] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.676066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.676111] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1264.676165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.676202] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1264.676243] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1264.676282] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1264.676324] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1264.676363] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1264.676406] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1264.676460] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1264.676502] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1264.676543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1264.676587] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1264.676627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1264.676668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1264.676705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1264.676718] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1264.676761] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1264.676773] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1264.676816] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1264.676861] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1264.676904] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1264.676946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1264.676990] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1264.677031] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1264.677392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1264.677431] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1264.677475] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1264.677518] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1264.677559] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1264.677602] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1264.677650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1264.677708] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1264.677750] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1264.677795] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1264.677838] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1264.677884] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1264.677927] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1264.678140] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1264.678244] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1264.678310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1264.678367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1264.678424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1264.678484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1264.678544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1264.678602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1264.678664] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1264.678725] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1264.678785] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1264.678905] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1264.678968] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1264.679307] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1264.679368] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1265.184402] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1265.184514] [drm:wait_panel_status [i915]] Wait complete
>[ 1265.184603] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1265.184690] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1265.287917] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1265.288037] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1265.288131] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1265.288318] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1265.385117] [drm:wait_panel_status [i915]] Wait complete
>[ 1265.385291] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1265.385496] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1265.385623] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1265.387078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.387249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.387371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.388161] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.388281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.389383] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.389511] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1265.390360] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1265.390542] [drm:intel_edp_backlight_on [i915]] 
>[ 1265.390652] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1265.390768] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1265.390901] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1265.391041] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1265.391212] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1265.391454] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1265.391579] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1265.391876] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1265.393875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.393990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.394146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.396828] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.396942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.398730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.400321] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1265.401060] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1265.404385] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1265.404436] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1265.404601] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1265.404890] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.404943] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1265.406057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1265.406100] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1265.408342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1265.408371] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1265.408414] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1265.408465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1265.408511] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1265.408560] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1265.408607] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1265.408650] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1265.425429] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1265.425515] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1265.425713] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1265.425849] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1265.425920] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1265.426024] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1265.426182] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1265.426506] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1265.426614] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1268.448348] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1268.448503] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1285.380472] [IGT] kms_cursor_legacy: executing
>[ 1285.666909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1285.666984] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1285.667042] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1285.667332] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1285.667388] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1285.667441] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1285.667501] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1285.667556] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1285.667971] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1285.669077] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1285.669110] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1285.669119] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1285.674473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1285.674569] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1285.675574] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1285.676462] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1285.676530] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1285.676593] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1285.676654] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1285.677567] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1285.677630] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1285.684674] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1285.684763] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1285.684768] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1285.684772] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1285.684776] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1285.684779] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1285.684783] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1285.684786] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1285.684790] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1285.684793] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1285.684796] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1285.684800] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1285.701787] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1285.701849] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1285.703299] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1285.703342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1285.705306] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1285.705322] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1285.707291] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1285.707358] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1285.709279] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1285.709300] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1285.709310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1285.709871] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1285.709945] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1285.788142] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1285.788210] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1285.790299] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1285.790319] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1285.790329] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1285.790399] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1285.790405] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1285.791916] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1285.791927] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1285.791934] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1285.793424] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1285.793436] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1285.793445] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1285.793454] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1285.793463] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1285.793471] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1285.793479] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1285.793488] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1285.793496] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1285.793504] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1285.793513] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1285.793521] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1285.793529] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1285.793538] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1285.793546] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1285.793554] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1285.793563] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1285.793571] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1285.793579] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1285.793588] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1285.793596] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1285.793604] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1285.793613] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1285.793621] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1285.793629] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1285.793638] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1285.793646] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1285.793654] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1285.793663] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1285.793671] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1285.793679] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1285.793687] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1285.793696] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1285.793704] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1285.793712] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1285.793720] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1285.793729] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1285.793737] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1285.793745] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1285.793754] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1285.793762] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1285.793770] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1285.793778] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1285.793787] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1285.793795] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1285.793803] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1285.793811] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1285.793819] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1285.810374] [IGT] kms_cursor_legacy: starting subtest cursorB-vs-flipB-atomic-transitions
>[ 1285.824357] [drm:drm_mode_addfb2] [FB:144]
>[ 1285.902096] [drm:drm_mode_addfb2] [FB:145]
>[ 1285.910892] [drm:drm_mode_addfb2] [FB:150]
>[ 1285.911265] [drm:drm_mode_addfb2] [FB:151]
>[ 1285.932644] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1285.932680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1285.932692] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1285.932726] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1285.932758] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1285.932789] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1285.932822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1285.932856] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1285.932887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1285.932918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1285.932947] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1285.932977] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1285.932981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1285.933010] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1285.933062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1285.933094] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1285.933130] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1285.933164] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1285.933199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1285.933233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1285.933271] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1285.933304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1285.933338] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] FB:134, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 1285.933375] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 1285.933406] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1285.933438] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1285.933470] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1285.933502] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1285.933537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1285.933580] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL A
>[ 1285.933615] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[ 1285.933928] [drm:intel_edp_backlight_off [i915]] 
>[ 1286.136357] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1286.136445] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1286.140510] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1286.140598] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1286.140679] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1286.192024] [drm:wait_panel_status [i915]] Wait complete
>[ 1286.192142] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1286.193465] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1286.193554] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1286.193634] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1286.193777] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1286.194198] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1286.194302] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1286.194520] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1286.194667] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1286.203917] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1286.204035] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1286.204653] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1286.204774] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1286.204874] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1286.205003] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1286.223973] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1286.224198] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1286.228332] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1286.228458] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1286.228691] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1286.228836] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1286.228961] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1286.229055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1286.229197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1286.229306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1286.229404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1286.230010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1286.230134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1286.230240] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1286.230543] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1286.230641] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1286.230733] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1286.230822] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1286.230911] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1286.231163] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 58
>[ 1286.231270] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1286.232006] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1286.232138] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1286.752492] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1286.752598] [drm:wait_panel_status [i915]] Wait complete
>[ 1286.752696] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1286.752790] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1286.855924] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1286.856036] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1286.856139] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1286.856318] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1286.953343] [drm:wait_panel_status [i915]] Wait complete
>[ 1286.953464] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1286.953655] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1286.953772] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1286.955162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1286.955264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1286.955368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1286.956166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1286.956283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1286.957400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1286.957519] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1286.958444] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1286.958581] [drm:intel_edp_backlight_on [i915]] 
>[ 1286.958691] [drm:intel_panel_enable_backlight [i915]] pipe B
>[ 1286.958796] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1286.958912] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1286.975621] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1286.975821] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1286.975960] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1286.976359] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1286.976627] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1290.016128] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1290.016167] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1297.752020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1297.752224] [drm:intel_edp_backlight_off [i915]] 
>[ 1297.960353] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1297.960480] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1297.966327] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1297.966444] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1297.966745] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1297.966840] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1297.966939] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1298.018659] [drm:wait_panel_status [i915]] Wait complete
>[ 1298.018779] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1298.019744] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1298.019863] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1298.019975] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1298.020198] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1298.020379] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 58
>[ 1298.020627] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1298.020792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1298.020910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1298.021019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1298.021162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1298.021282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1298.021390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1298.021498] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1298.021608] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1298.021718] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1298.021826] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1298.021933] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1298.022040] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1298.022270] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1298.023419] [IGT] kms_cursor_legacy: exiting, ret=0
>[ 1298.047941] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1298.048028] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1298.048100] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1298.048191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1298.048276] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1298.048355] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1298.048439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1298.048519] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1298.048593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1298.048671] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1298.048756] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1298.048829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1298.048851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1298.048931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1298.048955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1298.049036] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1298.049133] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1298.049217] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1298.049293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1298.049368] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1298.049442] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1298.049536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1298.049611] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1298.049689] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1298.049766] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1298.049845] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1298.049922] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1298.050004] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1298.050093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1298.050175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1298.050258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1298.050335] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1298.050409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1298.050486] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1298.050557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1298.050631] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1298.050714] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1298.050785] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1298.050810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1298.050887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1298.050911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1298.050990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1298.051294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1298.051371] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1298.051444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1298.051518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1298.051594] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1298.051689] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1298.051763] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1298.051839] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1298.051912] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1298.051984] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1298.052078] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1298.052161] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1298.052253] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1298.052325] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1298.052398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1298.052473] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1298.052543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1298.052619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1298.052687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1298.052712] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1298.052789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1298.052813] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1298.052891] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1298.052972] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1298.053048] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1298.054180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1298.054259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1298.054332] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1298.054428] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1298.054497] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1298.054569] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1298.054640] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1298.054711] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1298.054781] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1298.054860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1298.054930] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1298.054972] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1298.055013] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1298.055075] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1298.055118] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1298.055162] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1298.055322] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1298.055397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1298.055442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1298.055483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1298.055522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1298.055562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1298.055602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1298.055641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1298.055681] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1298.055722] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1298.055762] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1298.055840] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1298.055883] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1298.056114] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1298.056155] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1298.592349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1298.592411] [drm:wait_panel_status [i915]] Wait complete
>[ 1298.592460] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1298.592506] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1298.695726] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1298.695866] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1298.695981] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1298.696167] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1298.793060] [drm:wait_panel_status [i915]] Wait complete
>[ 1298.793238] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1298.793443] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1298.793570] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1298.794969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1298.795130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1298.795266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1298.796083] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1298.796252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1298.797394] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1298.797538] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1298.798487] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1298.798687] [drm:intel_edp_backlight_on [i915]] 
>[ 1298.798814] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1298.798946] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1298.799092] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1298.799288] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1298.799441] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1298.799700] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1298.799841] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1298.800158] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1298.803216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1298.803259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1298.803304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1298.805799] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1298.805837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1298.807575] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1298.809822] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1298.810575] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1298.810707] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1298.810749] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1298.810910] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1298.811217] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1298.811266] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1298.813456] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1298.813513] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1298.815318] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1298.815348] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1298.815398] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1298.815455] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1298.815508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1298.815564] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1298.815619] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1298.815669] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1298.832380] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1298.832463] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1298.832591] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1298.832696] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1298.832747] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1298.832840] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1298.832932] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1298.832995] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1298.833182] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1301.856353] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1301.856478] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1333.732949] [IGT] tools_test: executing
>[ 1333.762544] [IGT] tools_test: starting subtest sysfs_l3_parity
>[ 1333.853513] [IGT] tools_test: exiting, ret=77
>[ 1392.880824] [IGT] kms_atomic_transition: executing
>[ 1392.948455] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1392.948557] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1392.948642] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1392.948722] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1392.948799] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1392.948874] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1392.948956] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1392.949035] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1392.949773] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1392.950563] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1392.950603] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1392.950614] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1392.954962] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1392.955019] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1392.956033] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1392.956851] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1392.956884] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1392.956915] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1392.956945] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1392.957803] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1392.957834] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1392.964722] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1392.964812] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1392.964818] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1392.964822] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1392.964825] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1392.964829] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1392.964832] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1392.964836] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1392.964839] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1392.964843] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1392.964846] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1392.964849] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1392.972483] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1392.972523] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1392.974309] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1392.974348] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1392.976316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1392.976332] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1392.978346] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1392.978392] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1392.980289] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1392.980307] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1392.980314] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1392.980719] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1392.980771] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1393.059234] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1393.059307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1393.061293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1393.061314] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1393.061325] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1393.061397] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1393.061404] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1393.062602] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1393.062611] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1393.062617] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1393.063712] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1393.063722] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1393.063730] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1393.063737] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1393.063744] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1393.063751] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1393.063759] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1393.063766] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1393.063773] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1393.063780] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1393.063787] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1393.063794] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1393.063801] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1393.063808] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1393.063815] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1393.063822] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1393.063829] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1393.063836] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1393.063843] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1393.063850] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1393.063857] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1393.063864] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1393.063871] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1393.063879] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1393.063886] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1393.063893] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1393.063900] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1393.063907] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1393.063914] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1393.063921] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1393.063928] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1393.063935] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1393.063942] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1393.063949] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1393.063956] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1393.063963] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1393.063970] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1393.063977] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1393.063984] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1393.063991] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1393.063998] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1393.064005] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1393.064036] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1393.064043] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1393.064050] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1393.064057] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1393.064064] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1393.064074] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1393.071481] [IGT] kms_atomic_transition: starting subtest plane-all-transition-nonblocking
>[ 1393.071779] [drm:drm_mode_addfb2] [FB:132]
>[ 1393.090030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1393.090166] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1393.090254] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1393.090577] [drm:intel_edp_backlight_off [i915]] 
>[ 1393.296358] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1393.296487] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1393.305615] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1393.305737] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1393.305848] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1393.356021] [drm:wait_panel_status [i915]] Wait complete
>[ 1393.356180] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1393.358409] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1393.358537] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1393.358631] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1393.358741] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1393.358847] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1393.358990] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1393.359088] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1393.359299] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1393.374319] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1393.374450] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1393.374690] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1393.374848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1393.374960] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1393.375103] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1393.393871] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1393.394018] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1393.404421] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1393.404563] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1393.404809] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1393.404970] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1393.405170] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1393.405295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1393.405409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1393.405521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1393.405632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1393.405735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1393.405838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1393.405947] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1393.406060] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1393.406201] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1393.406320] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1393.406431] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1393.406537] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1393.406765] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1393.406871] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1393.407331] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1393.407445] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1393.912411] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[ 1393.926866] [drm:wait_panel_status [i915]] Wait complete
>[ 1393.926992] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1393.927177] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1394.030327] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1394.030452] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1394.030565] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1394.030795] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1394.128217] [drm:wait_panel_status [i915]] Wait complete
>[ 1394.128340] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1394.128532] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1394.128650] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1394.130007] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1394.130139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1394.130244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1394.131017] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1394.131163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1394.132537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1394.132647] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1394.133806] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1394.133936] [drm:intel_edp_backlight_on [i915]] 
>[ 1394.134043] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1394.134192] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1394.134321] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1394.134349] drm: not enough stolen space for compressed buffer (need 0 more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.
>[ 1394.150884] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1394.150981] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1394.151597] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1394.151849] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1394.151978] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1394.152933] [drm:drm_mode_addfb2] [FB:143]
>[ 1394.153113] [drm:drm_mode_addfb2] [FB:144]
>[ 1394.153538] [drm:drm_mode_addfb2] [FB:144]
>[ 1394.154896] [drm:drm_mode_addfb2] [FB:144]
>[ 1394.156262] [drm:drm_mode_addfb2] [FB:144]
>[ 1394.157567] [drm:drm_mode_addfb2] [FB:144]
>[ 1394.158478] [drm:drm_mode_addfb2] [FB:144]
>[ 1394.159497] [drm:drm_mode_addfb2] [FB:144]
>[ 1394.160822] [drm:drm_mode_addfb2] [FB:144]
>[ 1397.152331] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1397.152456] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1410.755295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1410.755695] [drm:intel_edp_backlight_off [i915]] 
>[ 1410.960390] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1410.960544] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1410.970521] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1410.970650] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1410.970968] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1410.971075] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1410.971243] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1411.023253] [drm:wait_panel_status [i915]] Wait complete
>[ 1411.023372] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1411.024135] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1411.024260] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1411.024387] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1411.024580] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1411.025228] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1411.025480] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1411.025642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1411.025758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1411.025865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1411.025968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1411.026067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1411.026225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1411.026339] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1411.026457] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1411.026564] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1411.026673] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1411.026871] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1411.027697] [drm:drm_mode_addfb2] [FB:132]
>[ 1411.029423] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1411.029528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1411.029641] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1411.029749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1411.029852] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1411.029958] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1411.030063] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1411.030215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1411.030330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1411.030445] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1411.030558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1411.030577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1411.030679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1411.030695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1411.030800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1411.030903] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1411.031007] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1411.031134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1411.031250] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1411.031382] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1411.031490] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1411.031596] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1411.031700] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1411.031806] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1411.031911] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1411.032016] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1411.032150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1411.032277] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL B
>[ 1411.032393] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A
>[ 1411.032739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1411.032848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1411.032954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1411.033058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1411.033187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1411.033305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1411.033417] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1411.033524] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1411.033629] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1411.033807] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 42
>[ 1411.033914] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1411.034308] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1411.037491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1411.037530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1411.037568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1411.040164] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1411.040206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1411.041939] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1411.043049] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1411.043899] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1411.060979] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1411.061032] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1411.061161] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1411.061516] [drm:drm_mode_addfb2] [FB:143]
>[ 1411.061585] [drm:drm_mode_addfb2] [FB:144]
>[ 1411.061679] [drm:drm_mode_addfb2] [FB:144]
>[ 1411.062171] [drm:drm_mode_addfb2] [FB:144]
>[ 1411.062595] [drm:drm_mode_addfb2] [FB:144]
>[ 1411.062999] [drm:drm_mode_addfb2] [FB:144]
>[ 1411.063440] [drm:drm_mode_addfb2] [FB:144]
>[ 1411.063825] [drm:drm_mode_addfb2] [FB:144]
>[ 1411.064260] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.859387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1427.859830] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1427.876672] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1427.876808] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 42
>[ 1427.877053] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1427.877289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1427.877411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1427.877525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1427.877634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1427.877738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1427.877845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1427.877954] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1427.878065] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1427.878212] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1427.878335] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1427.878541] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1427.879432] [drm:drm_mode_addfb2] [FB:132]
>[ 1427.880748] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1427.880828] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1427.880886] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1427.880949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1427.881007] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1427.881097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1427.881164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1427.881226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1427.881237] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1427.881295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1427.881307] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1427.881367] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1427.881426] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1427.881485] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1427.881546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1427.881604] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1427.881671] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1427.881729] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1427.881791] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1427.881849] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1427.881907] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1427.881966] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1427.882025] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1427.882141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1427.882218] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL C
>[ 1427.882287] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[ 1427.882467] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1427.882559] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1427.882622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1427.882681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1427.882740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1427.882797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1427.882856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1427.882913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1427.882971] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1427.883032] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1427.883113] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1427.883242] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 42
>[ 1427.883304] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1427.883548] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1427.884014] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1427.884643] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1427.886292] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1427.886361] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1427.888141] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1427.888159] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1427.888221] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1427.888288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1427.888348] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[ 1427.888415] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1427.888472] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1427.888528] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1427.905392] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1427.905445] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1427.905532] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1427.905895] [drm:drm_mode_addfb2] [FB:143]
>[ 1427.905962] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.906102] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.906620] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.907061] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.907528] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.907964] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.908456] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.908803] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.909165] [drm:drm_mode_addfb2] [FB:144]
>[ 1427.909503] [drm:drm_mode_addfb2] [FB:144]
>[ 1444.690673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1444.691034] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1444.691194] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1444.691693] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1444.709366] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1444.709508] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1444.723689] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1444.723831] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 42
>[ 1444.724077] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1444.724316] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1444.724471] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1444.724579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1444.724689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1444.725502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1444.725604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1444.725705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1444.725805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1444.725914] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1444.726019] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1444.726165] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1444.726284] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1444.726883] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1444.727732] [drm:drm_mode_addfb2] [FB:132]
>[ 1444.729422] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1444.729516] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1444.729533] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1444.729631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1444.729726] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1444.729815] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1444.729911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1444.730005] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1444.730177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1444.730285] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1444.730380] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1444.730479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1444.730494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1444.730584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1444.730601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1444.730692] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1444.730782] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1444.730874] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1444.730965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1444.731056] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1444.731183] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1444.731286] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1444.731391] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1444.731490] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1444.731585] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1444.731675] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1444.731766] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1444.731867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1444.731967] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL A
>[ 1444.732066] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[ 1444.732534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1444.732630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1444.732720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1444.732813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1444.732904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1444.732994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1444.733084] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1444.733206] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1444.733308] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1444.733482] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 58
>[ 1444.733576] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1444.733952] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1444.733989] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1444.734025] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1444.734066] [drm:wait_panel_status [i915]] Wait complete
>[ 1444.734099] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1444.734132] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[ 1444.837369] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1444.837435] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1444.837492] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1444.837599] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1444.934503] [drm:wait_panel_status [i915]] Wait complete
>[ 1444.934594] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1444.934751] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1444.934837] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1444.936171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1444.936245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1444.936322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1444.937029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1444.937131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1444.938184] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1444.938271] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1444.938942] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1444.939041] [drm:intel_edp_backlight_on [i915]] 
>[ 1444.939153] [drm:intel_panel_enable_backlight [i915]] pipe B
>[ 1444.939242] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1444.939330] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1444.956035] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1444.956175] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1444.956460] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1444.957120] [drm:drm_mode_addfb2] [FB:143]
>[ 1444.957255] [drm:drm_mode_addfb2] [FB:144]
>[ 1444.957417] [drm:drm_mode_addfb2] [FB:144]
>[ 1444.958284] [drm:drm_mode_addfb2] [FB:144]
>[ 1444.959005] [drm:drm_mode_addfb2] [FB:144]
>[ 1444.959781] [drm:drm_mode_addfb2] [FB:144]
>[ 1444.960444] [drm:drm_mode_addfb2] [FB:144]
>[ 1444.961004] [drm:drm_mode_addfb2] [FB:144]
>[ 1444.961614] [drm:drm_mode_addfb2] [FB:144]
>[ 1447.968349] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1447.968475] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1461.743015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1461.743465] [drm:intel_edp_backlight_off [i915]] 
>[ 1461.952394] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1461.952546] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1461.960413] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1461.960541] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1461.960863] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1461.960972] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1461.961081] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1462.013135] [drm:wait_panel_status [i915]] Wait complete
>[ 1462.013305] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1462.014031] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1462.014156] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1462.014272] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1462.014456] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1462.015199] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 58
>[ 1462.015455] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1462.015619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1462.015736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1462.015841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1462.015946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1462.016047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1462.016196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1462.016316] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1462.016433] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1462.016540] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1462.016648] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1462.016850] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1462.017578] [drm:drm_mode_addfb2] [FB:132]
>[ 1462.018744] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1462.018814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1462.018891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1462.018963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1462.019032] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1462.019136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1462.019215] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1462.019290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1462.019360] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1462.019430] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1462.019500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1462.019514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1462.019579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1462.019592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1462.019661] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1462.019729] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1462.019800] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1462.019869] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1462.019937] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1462.020015] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1462.020098] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1462.020179] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1462.020254] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1462.020330] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1462.020405] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1462.020480] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1462.020557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1462.020633] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1462.020708] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1462.020944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1462.021013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1462.021189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1462.021263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1462.021331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1462.021400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1462.021469] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1462.021540] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1462.021610] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1462.021742] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1462.021814] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1462.022043] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1462.025671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1462.025750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1462.025821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1462.028338] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1462.028372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1462.030099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1462.032360] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1462.033198] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1462.050281] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1462.050348] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1462.050456] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1462.050875] [drm:drm_mode_addfb2] [FB:143]
>[ 1462.050957] [drm:drm_mode_addfb2] [FB:144]
>[ 1462.051123] [drm:drm_mode_addfb2] [FB:144]
>[ 1462.051765] [drm:drm_mode_addfb2] [FB:144]
>[ 1462.052332] [drm:drm_mode_addfb2] [FB:144]
>[ 1462.052897] [drm:drm_mode_addfb2] [FB:144]
>[ 1462.053493] [drm:drm_mode_addfb2] [FB:144]
>[ 1462.054107] [drm:drm_mode_addfb2] [FB:144]
>[ 1462.054554] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.665519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1478.666075] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1478.681211] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1478.681347] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1478.681592] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1478.681752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1478.681858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1478.681965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1478.682067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1478.682240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1478.682356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1478.682470] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1478.682586] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1478.683233] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1478.683353] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1478.683560] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1478.684456] [drm:drm_mode_addfb2] [FB:132]
>[ 1478.686028] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1478.686187] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1478.686293] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1478.686402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1478.686506] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1478.686613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1478.686713] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1478.686811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1478.686829] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1478.686927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1478.686940] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1478.687041] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1478.687215] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1478.687331] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1478.687443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1478.687554] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1478.687677] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1478.687781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1478.687890] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1478.687994] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1478.688097] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1478.688234] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1478.688352] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1478.688911] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1478.689041] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1478.689162] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1478.689224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1478.689280] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1478.689336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1478.689390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1478.689444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1478.689453] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1478.689505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1478.689516] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1478.689570] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1478.689624] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1478.689679] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1478.689732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1478.689786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1478.689844] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1478.689899] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1478.689952] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1478.690006] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1478.690072] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1478.690131] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1478.690190] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1478.690282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1478.690348] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL C
>[ 1478.690409] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[ 1478.690572] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1478.690659] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1478.690714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1478.690771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1478.690826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1478.690882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1478.690936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1478.690990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1478.691045] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1478.691118] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1478.691183] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1478.691273] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 58
>[ 1478.691315] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1478.691519] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1478.691858] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1478.692416] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1478.694366] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1478.694402] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1478.696475] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1478.696487] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1478.696519] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1478.696556] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1478.696588] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[ 1478.696623] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1478.696653] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1478.696682] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1478.713527] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1478.713605] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1478.713722] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1478.714231] [drm:drm_mode_addfb2] [FB:143]
>[ 1478.714335] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.714568] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.715112] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.715665] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.716216] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.716747] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.717291] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.717813] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.718347] [drm:drm_mode_addfb2] [FB:144]
>[ 1478.718865] [drm:drm_mode_addfb2] [FB:144]
>[ 1495.515683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1495.516023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1495.516211] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1495.516742] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1495.534358] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1495.534487] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1495.548673] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1495.548800] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 58
>[ 1495.549032] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1495.549239] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1495.549379] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1495.549478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1495.549575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1495.549668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1495.549761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1495.549854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1495.549948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1495.550044] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1495.550207] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1495.550330] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1495.550444] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1495.550648] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1495.551512] [drm:drm_mode_addfb2] [FB:132]
>[ 1495.552900] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1495.552993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1495.553010] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1495.553149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1495.553256] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1495.553354] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1495.553453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1495.553549] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1495.553645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1495.553739] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1495.553828] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1495.553918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1495.553935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1495.554022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1495.554061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1495.554150] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1495.554256] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1495.554357] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1495.554459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1495.554555] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1495.554654] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1495.554745] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1495.554840] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1495.554931] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1495.555023] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1495.555131] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1495.555187] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1495.555259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1495.555327] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL A
>[ 1495.555390] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[ 1495.555593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1495.555656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1495.555714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1495.555776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1495.555833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1495.555892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1495.555951] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1495.556012] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1495.556095] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1495.556223] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 74
>[ 1495.556285] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1495.556668] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1495.556735] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1495.556804] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1495.556866] [drm:wait_panel_status [i915]] Wait complete
>[ 1495.556932] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1495.556993] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[ 1495.660149] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1495.660224] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1495.660286] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1495.660414] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1495.757752] [drm:wait_panel_status [i915]] Wait complete
>[ 1495.757849] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1495.758011] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1495.758199] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1495.759525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1495.759608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1495.759692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1495.760627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1495.760709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1495.761893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1495.761980] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1495.762621] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1495.762719] [drm:intel_edp_backlight_on [i915]] 
>[ 1495.762793] [drm:intel_panel_enable_backlight [i915]] pipe C
>[ 1495.762863] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1495.762943] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1495.779576] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1495.779680] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1495.779950] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1495.780749] [drm:drm_mode_addfb2] [FB:143]
>[ 1495.780868] [drm:drm_mode_addfb2] [FB:144]
>[ 1495.781051] [drm:drm_mode_addfb2] [FB:144]
>[ 1495.781915] [drm:drm_mode_addfb2] [FB:144]
>[ 1495.782703] [drm:drm_mode_addfb2] [FB:144]
>[ 1495.783573] [drm:drm_mode_addfb2] [FB:144]
>[ 1495.784626] [drm:drm_mode_addfb2] [FB:144]
>[ 1495.785538] [drm:drm_mode_addfb2] [FB:144]
>[ 1495.786470] [drm:drm_mode_addfb2] [FB:144]
>[ 1498.784286] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1498.784355] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1501.302489] [IGT] kms_atomic_transition: exiting, ret=99
>[ 1501.342653] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1501.342753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1501.342796] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1501.342902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1501.342998] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1501.343125] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1501.343215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1501.343309] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1501.343391] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1501.343478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1501.343572] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1501.343649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1501.343673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1501.343763] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1501.343790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1501.343882] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1501.343973] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1501.344085] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1501.344173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1501.344259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1501.344345] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1501.344456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1501.344536] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1501.344621] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1501.344705] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1501.344790] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1501.344875] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1501.344965] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1501.345053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1501.345160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1501.345265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1501.345358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1501.345446] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1501.345533] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1501.345613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1501.345700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1501.345794] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1501.345874] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1501.345900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1501.345989] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1501.346033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1501.346128] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1501.346223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1501.346312] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1501.346397] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1501.346484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1501.346570] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1501.346682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1501.346763] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1501.346849] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1501.346935] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1501.347022] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1501.347120] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1501.347215] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1501.347323] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1501.347408] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1501.347493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1501.347581] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1501.347661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1501.347747] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1501.347825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1501.347850] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1501.347938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1501.347963] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1501.348053] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1501.348162] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1501.348253] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1501.348338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1501.348425] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1501.348509] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1501.348618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1501.348702] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1501.348788] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1501.348874] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1501.348960] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1501.349044] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1501.349151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1501.349255] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1501.349340] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1501.349427] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1501.349511] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1501.349601] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1501.349685] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1501.349983] [drm:intel_edp_backlight_off [i915]] 
>[ 1501.552144] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1501.552216] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1501.558635] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1501.558699] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1501.558920] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1501.558969] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1501.559017] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1501.610211] [drm:wait_panel_status [i915]] Wait complete
>[ 1501.610322] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1501.612011] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1501.612138] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1501.612222] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 74
>[ 1501.612352] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1501.612433] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1501.612542] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1501.612624] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1501.612787] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1501.612898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1501.612995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1501.613122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1501.613222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1501.613316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1501.613409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1501.613531] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1501.613636] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1501.613740] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1501.613920] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1501.614031] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1501.614371] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1501.615004] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1501.615165] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1501.633531] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1501.633680] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1501.633816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1501.633951] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1501.634090] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1501.634290] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1501.650725] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1501.650868] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1501.651616] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1501.651738] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1502.176394] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1502.176539] [drm:wait_panel_status [i915]] Wait complete
>[ 1502.176655] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1502.176770] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1502.279824] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1502.279993] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1502.280129] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1502.280342] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1502.377129] [drm:wait_panel_status [i915]] Wait complete
>[ 1502.377318] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1502.377532] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1502.377669] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1502.379034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1502.379190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1502.379323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1502.380165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1502.380298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1502.381391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1502.381478] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1502.382038] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1502.382190] [drm:intel_edp_backlight_on [i915]] 
>[ 1502.382264] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1502.382339] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1502.382425] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1502.382515] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1502.382600] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1502.382766] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1502.382847] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1502.383121] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1502.386129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1502.386210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1502.386288] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1502.389054] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1502.389111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1502.390848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1502.392311] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1502.393036] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1502.410167] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1502.410257] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1502.410406] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1502.410535] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1502.410604] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1502.410699] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1502.410817] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1502.410899] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1502.411004] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1505.440380] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1505.440533] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1591.793969] [IGT] kms_flip: executing
>[ 1591.849721] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1591.849785] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1591.849827] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1591.849868] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1591.849911] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1591.849948] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1591.849990] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1591.850046] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1591.850477] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1591.851200] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1591.851224] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1591.851239] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1591.851266] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1591.851309] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1591.852223] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1591.853022] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1591.853123] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1591.853168] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1591.853208] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1591.854068] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1591.854111] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1591.860947] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1591.861054] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1591.861070] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1591.861088] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1591.861106] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1591.861124] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1591.861141] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1591.861159] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1591.861177] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1591.861194] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1591.861211] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1591.861228] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1591.861256] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1591.861299] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1591.863127] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1591.863171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1591.865375] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1591.865402] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1591.867602] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1591.867651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1591.869971] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1591.870000] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1591.870050] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1591.870099] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1591.870150] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1591.950325] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1591.950392] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1591.952308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1591.952351] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1591.952379] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1591.952464] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1591.952491] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1591.953909] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1591.953932] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1591.953961] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1591.955318] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1591.955352] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1591.955389] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1591.955426] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1591.955463] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1591.955500] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1591.955536] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1591.955573] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1591.955610] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1591.955646] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1591.955683] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1591.955720] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1591.955757] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1591.955793] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1591.955830] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1591.955867] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1591.955904] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1591.955941] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1591.955978] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1591.956037] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1591.956076] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1591.956117] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1591.956156] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1591.956593] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1591.956632] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1591.956668] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1591.956704] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1591.956742] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1591.956778] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1591.956815] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1591.956850] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1591.956886] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1591.956921] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1591.956956] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1591.956993] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1591.957048] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1591.957088] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1591.957125] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1591.957480] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1591.957517] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1591.957552] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1591.957587] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1591.957625] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1591.957662] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1591.957700] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1591.957734] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1591.957769] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1591.957805] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1591.958856] [IGT] kms_flip: starting subtest 2x-vblank-vs-suspend
>[ 1591.960396] [drm:drm_mode_addfb2] [FB:130]
>[ 1591.960501] [drm:drm_mode_addfb2] [FB:145]
>[ 1592.047222] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
>[ 1592.047363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1592.047503] [drm:intel_edp_backlight_off [i915]] 
>[ 1592.256357] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1592.256451] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1592.258954] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1592.259052] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1592.259187] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1592.309458] [drm:wait_panel_status [i915]] Wait complete
>[ 1592.309563] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1592.311322] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1592.311436] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1592.311662] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1592.311801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1592.311898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1592.311988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1592.312071] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1592.312170] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1592.312270] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1592.312375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1592.312474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1592.312567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1592.312738] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1592.313077] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1592.313229] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1592.313352] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1592.313640] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1592.322401] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1592.322652] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
>[ 1592.322873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1592.323188] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1592.336852] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1592.336971] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1592.337404] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1592.337544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1592.337638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1592.337736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1592.337826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1592.337916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1592.338005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1592.338128] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1592.338237] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1592.338339] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1592.338429] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1592.339024] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1592.339308] [drm:drm_mode_setcrtc] [CRTC:74:pipe C]
>[ 1592.339637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1592.339892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1592.339994] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1592.340200] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1592.358625] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1592.358726] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1592.372630] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1592.372756] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1592.372990] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1592.373197] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1592.373339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1592.373441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1592.373542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1592.373639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1592.373734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1592.373825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1592.373919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1592.374018] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1592.374140] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1592.374245] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1592.374344] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1592.374515] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1592.374779] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
>[ 1592.374875] [drm:drm_mode_setcrtc] [CONNECTOR:84:DP-1]
>[ 1592.375197] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1592.375294] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1592.375396] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 1592.375496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1592.375589] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 1592.375688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1592.375783] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1592.375880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1592.375975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 1592.376066] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1592.376199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1592.376225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1592.376311] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1592.376335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1592.376419] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[ 1592.376500] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 1592.376583] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1592.376664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1592.376746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1592.376839] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1592.376920] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1592.377006] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1592.377118] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1592.377206] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1592.377297] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1592.377385] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1592.377475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1592.377574] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1592.377661] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1592.378202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1592.378284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1592.378365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1592.378442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1592.378522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1592.378604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1592.378684] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1592.378767] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1592.378847] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1592.378992] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1592.379072] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1592.379769] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1592.381744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1592.381828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1592.381910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1592.384463] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1592.384510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1592.386240] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1592.388385] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1592.389225] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1592.406352] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1592.406417] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1592.406503] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1592.406674] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
>[ 1592.406716] [drm:drm_mode_setcrtc] [CONNECTOR:76:eDP-1]
>[ 1592.406836] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1592.406867] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1592.406874] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1592.406912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1592.406944] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1592.406974] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1592.407008] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1592.407105] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1592.407143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1592.407180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1592.407215] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1592.407250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1592.407259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1592.407290] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1592.407296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1592.407329] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1592.407361] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1592.407397] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1592.407432] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1592.407463] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1592.407499] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1592.407532] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1592.407565] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1592.407597] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1592.407630] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1592.407662] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1592.407696] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1592.407733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1592.407774] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1592.407809] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1592.407960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1592.407995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1592.408028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1592.408111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1592.408169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1592.408226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1592.408280] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1592.408341] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1592.408414] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1592.423027] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1592.423120] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1592.423467] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1592.423533] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1592.864426] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1592.864522] [drm:wait_panel_status [i915]] Wait complete
>[ 1592.864608] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1592.864694] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1592.967813] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1592.967923] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1592.968020] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1592.968196] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1593.065336] [drm:wait_panel_status [i915]] Wait complete
>[ 1593.065455] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1593.065641] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1593.065752] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1593.067133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1593.067235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1593.067336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1593.068145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1593.068261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1593.069392] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1593.069509] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1593.070434] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1593.070568] [drm:intel_edp_backlight_on [i915]] 
>[ 1593.070672] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1593.070776] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1593.070887] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1593.071009] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1593.071152] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1593.087525] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1593.087611] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1593.087876] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1593.418264] [IGT] kms_flip: exiting, ret=99
>[ 1593.445373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1593.445570] [drm:intel_edp_backlight_off [i915]] 
>[ 1593.648335] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1593.648445] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1593.654478] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1593.654571] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1593.654655] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1593.705776] [drm:wait_panel_status [i915]] Wait complete
>[ 1593.705886] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1593.707334] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1593.707453] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1593.707522] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1593.707602] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1593.707680] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1593.707782] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1593.708010] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1593.708211] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1593.723337] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1593.723478] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1593.723733] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1593.723885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1593.723998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1593.724176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1593.724289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1593.724762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1593.724870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1593.724979] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1593.725160] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1593.725290] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1593.725412] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1593.725531] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1593.725743] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1593.725894] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1593.727907] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1593.728042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1593.728149] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1593.728296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1593.728440] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1593.728575] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1593.728709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1593.728836] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1593.728961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1593.729098] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1593.729247] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1593.729350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1593.729384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1593.729502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1593.729535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1593.729656] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1593.729777] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1593.729893] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1593.730009] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1593.730141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1593.730260] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1593.730403] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1593.730507] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1593.730620] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1593.730733] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1593.730848] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1593.730960] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1593.731077] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1593.734527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1593.734650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1593.734775] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1593.734890] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1593.735003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1593.735207] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1593.735286] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1593.735327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1593.735373] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1593.735412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1593.735425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1593.735468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1593.735481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1593.735525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1593.735571] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1593.735614] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1593.735655] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1593.735698] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1593.735739] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1593.735793] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1593.735832] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1593.735872] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1593.735914] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1593.735955] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1593.735995] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1593.736057] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1593.736112] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1593.736152] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1593.736194] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1593.736235] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1593.736274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1593.736314] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1593.736352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1593.736365] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1593.736407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1593.736420] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1593.736463] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1593.736508] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1593.736550] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1593.736591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1593.736632] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1593.736674] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1593.736727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1593.736765] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1593.736806] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1593.736846] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1593.736887] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1593.736927] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1593.736972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1593.737024] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1593.737071] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1593.737114] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1593.737156] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1593.737200] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1593.737240] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1593.737390] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1593.737464] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1593.737507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1593.737545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1593.737582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1593.737619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1593.737656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1593.737692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1593.737729] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1593.737767] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1593.737805] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1593.737881] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1593.737921] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1593.738398] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1593.738440] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1594.272411] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1594.272534] [drm:wait_panel_status [i915]] Wait complete
>[ 1594.272632] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1594.272727] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1594.375983] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1594.376140] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1594.376267] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1594.376494] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1594.474954] [drm:wait_panel_status [i915]] Wait complete
>[ 1594.475086] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1594.475404] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1594.475542] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1594.476915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1594.477047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1594.477222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1594.478048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1594.478212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1594.479373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1594.479515] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1594.480091] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1594.480208] [drm:intel_edp_backlight_on [i915]] 
>[ 1594.480276] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1594.480346] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1594.480426] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1594.480516] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1594.480600] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1594.480767] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1594.480846] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1594.481082] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1594.482972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1594.483041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1594.483135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1594.485700] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1594.485768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1594.487562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1594.489279] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1594.490088] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1594.490246] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1594.490288] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1594.490449] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1594.490727] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1594.490776] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1594.508331] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1594.508434] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1594.508524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1594.508616] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1594.508710] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1594.508797] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1594.525445] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1594.525578] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1594.525889] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1594.526225] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1594.526342] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1594.526502] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1594.526674] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1594.526805] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1594.526959] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1597.536357] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1597.536500] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1623.716837] [IGT] kms_flip: executing
>[ 1624.004849] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1]
>[ 1624.004941] [drm:intel_dp_detect [i915]] [CONNECTOR:76:eDP-1]
>[ 1624.005007] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1624.005109] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1624.005184] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1624.005249] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1624.005318] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1624.005383] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1624.005809] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 1624.006654] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1624.006709] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:76:eDP-1] probed modes :
>[ 1624.006745] [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1624.006806] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1]
>[ 1624.006904] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1]
>[ 1624.007912] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 1624.008806] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1624.008904] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[ 1624.009003] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1624.009132] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1624.010066] [drm:drm_dp_read_desc] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 1624.010164] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1624.017226] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1624.017316] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:84:DP-1] probed modes :
>[ 1624.017330] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1624.017348] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1624.017365] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1624.017382] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1624.017399] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1624.017416] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1624.017433] [drm:drm_mode_debug_printmodeline] Modeline 103:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1624.017449] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1624.017465] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1624.017481] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1624.017508] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1]
>[ 1624.017550] [drm:intel_hdmi_detect [i915]] [CONNECTOR:88:HDMI-A-1]
>[ 1624.019073] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1624.019128] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1624.021338] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1624.021365] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1624.023379] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1624.023425] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1624.025329] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1624.025355] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1624.025368] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:88:HDMI-A-1] disconnected
>[ 1624.025415] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2]
>[ 1624.025464] [drm:intel_hdmi_detect [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1624.104151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1624.104198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1624.106333] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1624.106359] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1624.106373] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[ 1624.106431] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 600000 kHz
>[ 1624.106444] [drm:drm_add_edid_modes] HF-VSDB: max TMDS clock 600000 kHz
>[ 1624.107088] [drm:drm_edid_to_eld] ELD monitor S277HK
>[ 1624.107099] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 1624.107114] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[ 1624.107819] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:91:HDMI-A-2] probed modes :
>[ 1624.107835] [drm:drm_mode_debug_printmodeline] Modeline 105:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1624.107853] [drm:drm_mode_debug_printmodeline] Modeline 146:"3840x2160" 60 594000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1624.107870] [drm:drm_mode_debug_printmodeline] Modeline 165:"3840x2160" 60 593407 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1624.107887] [drm:drm_mode_debug_printmodeline] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1624.107904] [drm:drm_mode_debug_printmodeline] Modeline 167:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 1624.107921] [drm:drm_mode_debug_printmodeline] Modeline 148:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 1624.107938] [drm:drm_mode_debug_printmodeline] Modeline 147:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1624.107955] [drm:drm_mode_debug_printmodeline] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 1624.107972] [drm:drm_mode_debug_printmodeline] Modeline 108:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[ 1624.107989] [drm:drm_mode_debug_printmodeline] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[ 1624.108007] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1624.108056] [drm:drm_mode_debug_printmodeline] Modeline 153:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1624.108074] [drm:drm_mode_debug_printmodeline] Modeline 131:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1624.108094] [drm:drm_mode_debug_printmodeline] Modeline 157:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1624.108307] [drm:drm_mode_debug_printmodeline] Modeline 138:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1624.108326] [drm:drm_mode_debug_printmodeline] Modeline 141:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1624.108345] [drm:drm_mode_debug_printmodeline] Modeline 142:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1624.108364] [drm:drm_mode_debug_printmodeline] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1624.108381] [drm:drm_mode_debug_printmodeline] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1624.108399] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1624.108417] [drm:drm_mode_debug_printmodeline] Modeline 111:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1624.108435] [drm:drm_mode_debug_printmodeline] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1624.108453] [drm:drm_mode_debug_printmodeline] Modeline 110:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1624.108470] [drm:drm_mode_debug_printmodeline] Modeline 109:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1624.108489] [drm:drm_mode_debug_printmodeline] Modeline 112:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1624.108506] [drm:drm_mode_debug_printmodeline] Modeline 154:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1624.108523] [drm:drm_mode_debug_printmodeline] Modeline 140:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1624.108541] [drm:drm_mode_debug_printmodeline] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1624.108558] [drm:drm_mode_debug_printmodeline] Modeline 124:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1624.108575] [drm:drm_mode_debug_printmodeline] Modeline 125:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1624.108594] [drm:drm_mode_debug_printmodeline] Modeline 126:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 1624.108611] [drm:drm_mode_debug_printmodeline] Modeline 127:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1624.108629] [drm:drm_mode_debug_printmodeline] Modeline 128:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1624.108647] [drm:drm_mode_debug_printmodeline] Modeline 115:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1624.108665] [drm:drm_mode_debug_printmodeline] Modeline 116:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1624.108683] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1624.108701] [drm:drm_mode_debug_printmodeline] Modeline 136:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1624.108719] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1624.108736] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1624.108754] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1624.108771] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1624.108789] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1624.108807] [drm:drm_mode_debug_printmodeline] Modeline 118:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1624.108826] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 1624.108842] [drm:drm_mode_debug_printmodeline] Modeline 155:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1624.108859] [drm:drm_mode_debug_printmodeline] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1624.108876] [drm:drm_mode_debug_printmodeline] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1624.114581] [IGT] kms_flip: starting subtest 2x-vblank-vs-suspend-interruptible
>[ 1624.115401] [drm:drm_mode_addfb2] [FB:93]
>[ 1624.115462] [drm:drm_mode_addfb2] [FB:145]
>[ 1624.201785] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
>[ 1624.201931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1624.202115] [drm:intel_edp_backlight_off [i915]] 
>[ 1624.408311] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1624.408394] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1624.423855] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1624.423943] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1624.424024] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[ 1624.475715] [drm:wait_panel_status [i915]] Wait complete
>[ 1624.475820] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1624.477000] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1624.477112] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1624.477214] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1624.477396] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1624.477558] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1624.477665] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1624.477917] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1624.478061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1624.478253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1624.478372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1624.478483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1624.478586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1624.478689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1624.478798] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1624.478908] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1624.479014] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1624.479186] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1624.493885] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1624.494502] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
>[ 1624.494765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1624.495153] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1624.499819] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1624.499950] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1624.500245] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1624.500413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1624.500526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1624.500638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1624.500741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1624.500844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1624.500946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1624.501052] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1624.501190] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1624.501310] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1624.501425] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1624.510393] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1624.510624] [drm:drm_mode_setcrtc] [CRTC:74:pipe C]
>[ 1624.510841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1624.511002] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1624.511106] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1624.511202] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1624.529474] [drm:intel_hdmi_handle_sink_scrambling [i915]] sink scrambling handled
>[ 1624.529592] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1624.545563] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 1624.545704] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 74
>[ 1624.545950] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[ 1624.546107] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1624.546333] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1624.546452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1624.546566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1624.547091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1624.547219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1624.547323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1624.547645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1624.547743] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1624.547836] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1624.547926] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1624.548015] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1624.548214] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1624.548514] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
>[ 1624.548606] [drm:drm_mode_setcrtc] [CONNECTOR:84:DP-1]
>[ 1624.548895] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1624.548985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1624.549082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 1624.549234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1624.549313] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 1624.549390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1624.549461] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1624.549532] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1624.549604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 1624.549672] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1624.549740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1624.549753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1624.549820] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1624.549833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 1624.549901] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[ 1624.549971] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 1624.550041] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1624.550125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1624.550203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1624.550285] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1624.550358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1624.550436] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1624.550506] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1624.550574] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1624.550643] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1624.550711] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1624.550787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1624.550865] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1624.550938] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1624.551405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1624.551469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1624.551532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1624.551592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1624.551651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1624.551709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1624.551769] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1624.551831] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1624.551890] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1624.552011] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1624.552091] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1624.552311] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1624.554223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1624.554283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1624.554344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1624.557045] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1624.557118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1624.558902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1624.560322] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1624.561158] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1624.578182] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1624.578277] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1624.578395] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1624.578641] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
>[ 1624.578698] [drm:drm_mode_setcrtc] [CONNECTOR:76:eDP-1]
>[ 1624.578857] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1624.578909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1624.578919] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1624.578975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1624.579030] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1624.579127] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1624.579187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1624.579247] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1624.579303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1624.579358] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1624.579757] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1624.579810] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1624.579819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1624.579869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1624.579877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1624.579929] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1624.579980] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1624.580048] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1624.580134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1624.580206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1624.580281] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1624.580350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1624.580417] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1624.580480] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1624.580544] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1624.580607] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1624.580671] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1624.580741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1624.580817] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1624.580884] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1624.581200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1624.581271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1624.581341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1624.581410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1624.581478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1624.581545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1624.581614] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1624.581684] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1624.581771] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1624.594910] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1624.594992] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1624.595400] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1624.595480] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1625.032298] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1625.032405] [drm:wait_panel_status [i915]] Wait complete
>[ 1625.032500] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1625.032595] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1625.135684] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1625.135794] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1625.135890] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1625.136072] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1625.234602] [drm:wait_panel_status [i915]] Wait complete
>[ 1625.234722] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1625.234909] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1625.235020] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1625.236462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1625.236574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1625.236681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1625.237472] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1625.237579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1625.238661] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1625.238767] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1625.239673] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1625.239801] [drm:intel_edp_backlight_on [i915]] 
>[ 1625.239903] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1625.240006] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1625.240171] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1625.240307] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1625.240409] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1625.256665] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1625.256771] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1625.257041] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1628.256127] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1628.256168] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1715.996471] [IGT] kms_flip: exiting, ret=99
>[ 1716.029773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[ 1716.030020] [drm:intel_edp_backlight_off [i915]] 
>[ 1716.232355] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1716.232484] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1716.249077] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1716.249219] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1716.249498] [drm:intel_edp_panel_off.part.27 [i915]] Turn eDP port A panel power off
>[ 1716.249591] [drm:intel_edp_panel_off.part.27 [i915]] Wait for panel power off time
>[ 1716.249684] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1716.300973] [drm:wait_panel_status [i915]] Wait complete
>[ 1716.301129] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[ 1716.302493] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1716.302629] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1716.302740] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1716.302922] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1716.303168] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1716.303306] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 42
>[ 1716.303565] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[ 1716.303749] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1716.313912] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1716.314066] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 58
>[ 1716.314655] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[ 1716.314826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1716.314952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1716.315072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1716.315227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1716.315345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1716.315462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1716.315582] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1716.315709] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1716.315830] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1716.315949] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1716.316068] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1716.316353] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1716.316524] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1716.318478] [drm:intel_atomic_check [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[ 1716.318565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1716.318604] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1716.318705] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[ 1716.318797] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1716.318880] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[ 1716.318967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1716.319047] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[ 1716.319160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1716.319243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[ 1716.319332] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1716.319407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1716.319431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1716.319515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1716.319541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 1716.319626] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[ 1716.319715] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[ 1716.319804] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1716.319887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1716.319967] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1716.320047] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1716.320178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1716.320254] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 1716.320334] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 1716.320413] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[ 1716.320492] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[ 1716.320573] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[ 1716.320657] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains
>[ 1716.320740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1716.320825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1716.320916] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1716.320999] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1716.321136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1716.321217] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe B][modeset]
>[ 1716.321292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1716.321372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1716.321460] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1716.321535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1716.321559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1716.321642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1716.321665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 1716.321749] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 1716.321837] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1716.321919] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1716.321999] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1716.322098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1716.322186] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[ 1716.322291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1716.322364] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1B] disabled, scaler_id = -1
>[ 1716.322443] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2B] disabled, scaler_id = -1
>[ 1716.322523] [drm:intel_dump_pipe_config [i915]] [PLANE:49:plane 3B] disabled, scaler_id = -1
>[ 1716.322604] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 4B] disabled, scaler_id = -1
>[ 1716.322684] [drm:intel_dump_pipe_config [i915]] [PLANE:55:cursor B] disabled, scaler_id = -1
>[ 1716.322772] [drm:intel_atomic_check [i915]] [CONNECTOR:91:HDMI-A-2] checking for sink bpp constrains
>[ 1716.322873] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1716.322952] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>[ 1716.323034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1716.323126] [drm:intel_dump_pipe_config [i915]] [CRTC:74:pipe C][modeset]
>[ 1716.323205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1716.323284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[ 1716.323357] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1716.323380] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1716.323463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1716.323486] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[ 1716.323569] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[ 1716.323655] [drm:intel_dump_pipe_config [i915]] port clock: 533250, pipe src size: 3840x2160, pixel rate 533250
>[ 1716.323738] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 1716.323816] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1716.323898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1716.323978] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1a, pll1: 0x100, pll2: 0x2a6666, pll3: 0x10000, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58
>[ 1716.326211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1716.326279] [drm:intel_dump_pipe_config [i915]] [PLANE:59:plane 1C] disabled, scaler_id = -1
>[ 1716.326321] [drm:intel_dump_pipe_config [i915]] [PLANE:62:plane 2C] disabled, scaler_id = -1
>[ 1716.326362] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 3C] disabled, scaler_id = -1
>[ 1716.326402] [drm:intel_dump_pipe_config [i915]] [PLANE:68:plane 4C] disabled, scaler_id = -1
>[ 1716.326442] [drm:intel_dump_pipe_config [i915]] [PLANE:71:cursor C] disabled, scaler_id = -1
>[ 1716.326486] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz
>[ 1716.326537] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe A] using pre-allocated PORT PLL A
>[ 1716.326578] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[ 1716.326620] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe B] using pre-allocated PORT PLL B
>[ 1716.326660] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[ 1716.326703] [drm:bxt_get_dpll [i915]] [CRTC:74:pipe C] using pre-allocated PORT PLL C
>[ 1716.326743] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[ 1716.326891] [drm:intel_set_cdclk [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz
>[ 1716.326965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>[ 1716.327007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[ 1716.327106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B]
>[ 1716.327146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A]
>[ 1716.327186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B]
>[ 1716.327223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C]
>[ 1716.327262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DDI C]
>[ 1716.327301] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1716.327341] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1716.327380] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1716.327456] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 42
>[ 1716.327499] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[ 1716.327704] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1716.327745] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1716.896403] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1716.896467] [drm:wait_panel_status [i915]] Wait complete
>[ 1716.896518] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1716.896566] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[ 1716.999905] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[ 1717.000002] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1717.000079] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1717.000288] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1717.098562] [drm:wait_panel_status [i915]] Wait complete
>[ 1717.098673] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[ 1717.098854] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1717.098959] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1717.100617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1717.100723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1717.100830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1717.101743] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1717.101847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1717.102897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1717.102989] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1717.103596] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1717.103732] [drm:intel_edp_backlight_on [i915]] 
>[ 1717.103814] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1717.103895] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[ 1717.103989] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 1717.104149] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1717.104245] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1717.104426] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 58
>[ 1717.104514] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[ 1717.104785] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1717.106713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1717.106798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1717.106881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1717.109468] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1717.109547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1717.111545] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1717.113329] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1717.114251] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1717.114435] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 74
>[ 1717.114495] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[ 1717.114669] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 1717.114979] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1717.115034] [drm:intel_hdmi_handle_sink_scrambling [i915]] Setting sink scrambling for enc:DDI C connector:HDMI-A-2
>[ 1717.117308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1717.117362] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1717.119305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0054 w(1)
>[ 1717.119336] [drm:drm_scdc_set_high_tmds_clock_ratio] *ERROR* Failed to read TMDS config: -6
>[ 1717.119385] [drm:intel_hdmi_handle_sink_scrambling [i915]] *ERROR* Set TMDS ratio failed
>[ 1717.119440] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:91:HDMI-A-2], [ENCODER:90:DDI C]
>[ 1717.119491] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[ 1717.119545] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 533250 not found, falling back to defaults
>[ 1717.119598] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[ 1717.119648] [drm:hsw_audio_config_update [i915]] using automatic N
>[ 1717.136380] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:76:eDP-1]
>[ 1717.136453] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[ 1717.136576] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL A
>[ 1717.136688] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:84:DP-1]
>[ 1717.136748] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe B]
>[ 1717.136840] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL B
>[ 1717.136941] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:91:HDMI-A-2]
>[ 1717.137018] [drm:intel_atomic_commit_tail [i915]] [CRTC:74:pipe C]
>[ 1717.137204] [drm:verify_single_dpll_state.isra.72 [i915]] PORT PLL C
>[ 1720.160372] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1720.160527] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067

Actions: View

Attachments on bug 102901: 134362 | 134363 | 134364 | 134365 | 134366 | 134367 | 134368 | 134369 | 134371 | 134372

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.