Attachment 135191 Details for Bug 103404 – [PATCH 1/2] drm/amd: Add DCE12 resource strap registers

[patch] [PATCH 1/2] drm/amd: Add DCE12 resource strap registers

0001-drm-amd-Add-DCE12-resource-strap-registers.patch (text/plain), 3.59 KB, created by Leo Li on 2017-10-31 20:33:59 UTC

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Creator: Leo Li

Created: 2017-10-31 20:33:59 UTC

Size: 3.59 KB

patch

obsolete

>From 3e2e1d02bac994ef0cd11c15e70c79db16b270f0 Mon Sep 17 00:00:00 2001
>From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>Date: Thu, 26 Oct 2017 16:24:54 -0400
>Subject: [PATCH 1/2] drm/amd: Add DCE12 resource strap registers
>
>We need them for initializing audio properly.
>
>Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
>Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>Acked-by: Alex Deucher <alexander.deucher@amd.com>
>---
> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h  | 4 ++++
> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 8 ++++++++
> 2 files changed, 12 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
>index 75b660d..f730d06 100644
>--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
>+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
>@@ -1841,6 +1841,10 @@
> #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
> #define mmDCIO_WRCMD_DELAY                                                                             0x2094
> #define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
>+#define mmDC_PINSTRAPS                                                                                 0x2096
>+#define mmDC_PINSTRAPS_BASE_IDX                                                                        2
>+#define mmCC_DC_MISC_STRAPS                                                                            0x2097
>+#define mmCC_DC_MISC_STRAPS_BASE_IDX                                                                   2
> #define mmDC_DVODATA_CONFIG                                                                            0x2098
> #define mmDC_DVODATA_CONFIG_BASE_IDX                                                                   2
> #define mmLVTMA_PWRSEQ_CNTL                                                                            0x2099
>diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
>index d8ad862..6d3162c 100644
>--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
>+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
>@@ -2447,6 +2447,14 @@
> //DCCG_CBUS_WRCMD_DELAY
> #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT                                                    0x0
> #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK                                                      0x0000000FL
>+//DC_PINSTRAPS
>+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
>+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
>+//CC_DC_MISC_STRAPS
>+#define CC_DC_MISC_STRAPS__HDMI_DISABLE__SHIFT                                                                0x6
>+#define CC_DC_MISC_STRAPS__AUDIO_STREAM_NUMBER__SHIFT                                                         0x8
>+#define CC_DC_MISC_STRAPS__HDMI_DISABLE_MASK                                                                  0x00000040L
>+#define CC_DC_MISC_STRAPS__AUDIO_STREAM_NUMBER_MASK                                                           0x00000700L
> //DCCG_DS_DTO_INCR
> #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
> #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
>-- 
>2.7.4
>

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