Attachment 137240 Details for Bug 104931 – debug.patch

[patch] debug.patch

0001-DEBUG-HACK.patch (text/plain), 3.47 KB, created by Rodrigo Vivi on 2018-02-09 07:42:58 UTC

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Creator: Rodrigo Vivi

Created: 2018-02-09 07:42:58 UTC

Size: 3.47 KB

patch

obsolete

>From 51d1e6dae033d3ea7390f3c246aef7c1b363409e Mon Sep 17 00:00:00 2001
>From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Date: Thu, 8 Feb 2018 23:39:51 -0800
>Subject: [PATCH] DEBUG HACK
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 42 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 36 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index e9feffdea899..ec6ff25ff851 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -521,7 +521,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> 	dev_priv->psr.enable_source(intel_dp, crtc_state);
> 	dev_priv->psr.enabled = intel_dp;
> 
>-	if (INTEL_GEN(dev_priv) >= 9) {
>+	if (false) { //INTEL_GEN(dev_priv) >= 9) {
> 		intel_psr_activate(intel_dp);
> 	} else {
> 		/*
>@@ -534,8 +534,12 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> 		 *     - On HSW/BDW we get a recoverable frozen screen until
> 		 *       next exit-activate sequence.
> 		 */
>+		DRM_ERROR("I915-DEBUG: Scheduling 10s\n");
> 		schedule_delayed_work(&dev_priv->psr.work,
>-				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
>+				      msecs_to_jiffies(10000));
>+
>+		msleep(10);
>+		intel_psr_activate(intel_dp);
> 	}
> 
> unlock:
>@@ -664,6 +668,8 @@ static void intel_psr_work(struct work_struct *work)
> 	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 
>+	DRM_ERROR("I915-DEBUG: Work running\n");
>+
> 	/* We have to make sure PSR is ready for re-enable
> 	 * otherwise it keeps disabled until next full enable/disable cycle.
> 	 * PSR might take some time to get fully disabled
>@@ -728,6 +734,15 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
> 	if (!dev_priv->psr.active)
> 		return;
> 
>+	if (intel_wait_for_register(dev_priv,
>+				    EDP_PSR_STATUS,
>+				    EDP_PSR_STATUS_STATE_MASK,
>+				    0,
>+				    50)) {
>+		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>+		return;
>+	}
>+
> 	if (HAS_DDI(dev_priv)) {
> 		if (dev_priv->psr.aux_frame_sync)
> 			drm_dp_dpcd_writeb(&intel_dp->aux,
>@@ -769,6 +784,15 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
> 				   DP_SET_POWER_D0);
> 	}
> 
>+	if (intel_wait_for_register(dev_priv,
>+				    EDP_PSR_STATUS,
>+				    EDP_PSR_STATUS_STATE_MASK,
>+				    0,
>+				    50)) {
>+		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>+		return;
>+	}
>+
> 	dev_priv->psr.active = false;
> }
> 
>@@ -897,10 +921,16 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> 	if (frontbuffer_bits)
> 		intel_psr_exit(dev_priv);
> 
>-	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
>-		if (!work_busy(&dev_priv->psr.work.work))
>+	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) {
>+		if (!work_busy(&dev_priv->psr.work.work)) {
>+			DRM_ERROR("I915-DEBUG: Scheduling normal 100ms\n");
> 			schedule_delayed_work(&dev_priv->psr.work,
> 					      msecs_to_jiffies(100));
>+		}
>+		else {
>+			DRM_ERROR("I915-DEBUG: Work busy!\n");
>+		}
>+	}
> 	mutex_unlock(&dev_priv->psr.lock);
> }
> 
>@@ -922,9 +952,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> 	if (!dev_priv->psr.sink_support)
> 		return;
> 
>-	/* Per platform default: all disabled. */
>+	/* Per platform default: all enabled. */
> 	if (i915_modparams.enable_psr == -1)
>-		i915_modparams.enable_psr = 0;
>+		i915_modparams.enable_psr = 1;
> 
> 	/* Set link_standby x link_off defaults */
> 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>-- 
>2.13.6
>

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