Attachment 140520 Details for Bug 107159 – i965: flush render target before ISP disable

[patch] i965: flush render target before ISP disable

0001-i965-flush-render-target-before-ISP-disable.patch (text/plain), 2.22 KB, created by Lionel Landwerlin on 2018-07-09 08:45:46 UTC

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Creator: Lionel Landwerlin

Created: 2018-07-09 08:45:46 UTC

Size: 2.22 KB

patch

obsolete

>From 85d6c1b140df0e919a3fcb1a9a56168f8e2367ed Mon Sep 17 00:00:00 2001
>From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Date: Mon, 9 Jul 2018 09:39:53 +0100
>Subject: [PATCH] i965: flush render target before ISP disable
>
>In bug https://bugs.freedesktop.org/show_bug.cgi?id=106243 we intended
>to fix a hang that seems to happen right after a ISP disable. The
>error state seemly indicating that the EUs were still running while
>the ISP disable pipe control was applied. The theory was that threads
>were still being dispatched while we tried to disable the constants
>and we tried to fix the issue by stalling on scoreboard to make sure
>all PS threads had been dispatch before disabling the constants.
>
>Newer bugs seems to imply this problem is still happening. This patch
>tries to stall harder (with a render target flush) before doing the
>ISP disable.
>
>Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107159
>Fixes: f536097f675211 ("i965: require pixel scoreboard stall prior to ISP disable")
>---
> src/mesa/drivers/dri/i965/brw_pipe_control.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
>index 122ac260703..9efb54f7023 100644
>--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
>+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
>@@ -350,7 +350,7 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
>  * software must program push constant commands for all stages prior to
>  * rendering anything, so we flag them as dirty.
>  *
>- * Finally, we also make sure to stall at pixel scoreboard to make sure the
>+ * Finally, we also make sure to flush the render target to make sure the
>  * constants have been loaded into the EUs prior to disable the push constants
>  * so that it doesn't hang a previous 3DPRIMITIVE.
>  */
>@@ -358,7 +358,7 @@ void
> gen10_emit_isp_disable(struct brw_context *brw)
> {
>    brw_emit_pipe_control(brw,
>-                         PIPE_CONTROL_STALL_AT_SCOREBOARD |
>+                         PIPE_CONTROL_RENDER_TARGET_FLUSH |
>                          PIPE_CONTROL_CS_STALL,
>                          NULL, 0, 0);
>    brw_emit_pipe_control(brw,
>-- 
>2.18.0
>

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