Attachment 141060 Details for Bug 107476 – drm/i915: set DP Main Stream Attribute for color range on DDI platforms

[patch] drm/i915: set DP Main Stream Attribute for color range on DDI platforms

0001-drm-i915-set-DP-Main-Stream-Attribute-for-color-rang.patch (text/plain), 3.26 KB, created by Jani Nikula on 2018-08-13 10:04:05 UTC

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Creator: Jani Nikula

Created: 2018-08-13 10:04:05 UTC

Size: 3.26 KB

patch

obsolete

>From 3116e301fb8daee68022b71716c4acc095d0bd4b Mon Sep 17 00:00:00 2001
>From: Jani Nikula <jani.nikula@intel.com>
>Date: Mon, 13 Aug 2018 12:19:48 +0300
>Subject: [PATCH] drm/i915: set DP Main Stream Attribute for color range on DDI
> platforms
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
>Cc: Jani Nikula <jani.nikula@intel.com>
>
>Since Haswell we have no color range indication either in the pipe or
>port registers for DP. Instead, there's a separate register for setting
>the DP Main Stream Attributes (MSA) directly. The MSA register
>definition makes no references to colorimetry, just a vague reference to
>the DP spec. The connection to the color range was lost.
>
>Apparently we've failed to set the proper MSA bit for limited, or CEA,
>range ever since the first DDI platfroms. We've started setting other
>MSA parameters since commit dae847991a43 ("drm/i915: add
>intel_ddi_set_pipe_settings").
>
>Without the crucial bit of information, the DP sink has no way of
>knowing the source is actually transmitting limited range RGB, leading
>to "washed out" colors. With the colorimetry information, compliant
>sinks should be able to handle the limited range properly. Native
>(i.e. non-LSPCON) HDMI was not affected because we do pass the color
>range via AVI infoframes.
>
>Though not the root cause, the problem was made worse for DDI platforms
>with commit 55bc60db5988 ("drm/i915: Add "Automatic" mode for the
>"Broadcast RGB" property"), which selects limited range RGB
>automatically based on the mode, as per the DP, HDMI and CEA specs.
>
>After all these years, the fix boils down to flipping one bit.
>
>Reported-by: MichaÅ KopeÄ <mkopec12@gmail.com>
>Reported-by: N. W. <nw9165-3201@yahoo.com>
>Reported-by: Nicholas Stommel <nicholas.stommel@gmail.com>
>Reported-by: Tom Yan <tom.ty89@gmail.com>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100023
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107476
>Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=94921
>Cc: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>Cc: <stable@vger.kernel.org> # v3.9+
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h  | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 17575cfc22b5..0c9f03dda569 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9246,6 +9246,7 @@ enum skl_power_gate {
> #define  TRANS_MSA_10_BPC		(2 << 5)
> #define  TRANS_MSA_12_BPC		(3 << 5)
> #define  TRANS_MSA_16_BPC		(4 << 5)
>+#define  TRANS_MSA_CEA_RANGE		(1 << 3)
> 
> /* LCPLL Control */
> #define LCPLL_CTL			_MMIO(0x130040)
>diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>index 0adc043529f2..6f7be066c8f2 100644
>--- a/drivers/gpu/drm/i915/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/intel_ddi.c
>@@ -1685,6 +1685,10 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
> 	WARN_ON(transcoder_is_dsi(cpu_transcoder));
> 
> 	temp = TRANS_MSA_SYNC_CLK;
>+
>+	if (crtc_state->limited_color_range)
>+		temp |= TRANS_MSA_CEA_RANGE;
>+
> 	switch (crtc_state->pipe_bpp) {
> 	case 18:
> 		temp |= TRANS_MSA_6_BPC;
>-- 
>2.11.0
>

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Attachments on bug 107476: 140958 | 141017 | 141018 | 141019 | 141020 | 141021 | 141022 | 141060 | 142444

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