Attachment 143047 Details for Bug 108820 – INTEL_DEBUG=cs,do32 output for the 64 local workgroup size case (working)

INTEL_DEBUG=cs,do32 output for the 64 local workgroup size case (working)

do32-working.txt (text/plain), 201.50 KB, created by Jakub Okoński on 2019-01-09 21:51:16 UTC

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Creator: Jakub Okoński

Created: 2019-01-09 21:51:16 UTC

Size: 201.50 KB

patch

obsolete

>NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader:
>shader: MESA_SHADER_COMPUTE
>local-size: 64, 1, 1
>shared-size: 1
>inputs: 0
>outputs: 0
>uniforms: 20
>shared: 4
>decl_var system INTERP_MODE_NONE uvec3 gl_GlobalInvocationID
>decl_var system INTERP_MODE_NONE uvec3 gl_LocalInvocationID
>decl_function main (0 params)
>
>impl main {
>	decl_var  INTERP_MODE_NONE uint ix0
>	decl_var  INTERP_MODE_NONE uint ix1
>	decl_var  INTERP_MODE_NONE uint ix2
>	decl_var  INTERP_MODE_NONE vec4 input0
>	decl_var  INTERP_MODE_NONE vec4 input1
>	decl_var  INTERP_MODE_NONE vec4 input2
>	decl_var  INTERP_MODE_NONE vec4 vertex0
>	decl_var  INTERP_MODE_NONE vec4 vertex1
>	decl_var  INTERP_MODE_NONE vec4 vertex2
>	decl_var  INTERP_MODE_NONE bool cull
>	decl_var  INTERP_MODE_NONE vec3 ndc0
>	decl_var  INTERP_MODE_NONE vec3 ndc1
>	decl_var  INTERP_MODE_NONE vec3 ndc2
>	decl_var  INTERP_MODE_NONE uint local_offset
>	decl_var  INTERP_MODE_NONE bool phi
>	decl_var  INTERP_MODE_NONE bool phi@0
>	decl_var  INTERP_MODE_NONE bool phi@1
>	decl_var  INTERP_MODE_NONE bool phi@2
>	decl_var  INTERP_MODE_NONE bool phi@3
>	decl_var  INTERP_MODE_NONE bool phi@4
>	decl_var  INTERP_MODE_NONE bool phi@5
>	decl_var  INTERP_MODE_NONE bool phi@6
>	decl_var  INTERP_MODE_NONE bool phi@7
>	decl_var  INTERP_MODE_NONE bool phi@8
>	decl_var  INTERP_MODE_NONE bool phi@9
>	decl_var  INTERP_MODE_NONE bool phi@10
>	decl_var  INTERP_MODE_NONE bool phi@11
>	decl_var  INTERP_MODE_NONE bool phi@12
>	decl_var  INTERP_MODE_NONE bool phi@13
>	decl_var  INTERP_MODE_NONE bool phi@14
>	decl_var  INTERP_MODE_NONE bool phi@15
>	decl_var  INTERP_MODE_NONE bool phi@16
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_777 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_755 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_715 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_711 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_702 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_693 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_683 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_679 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_670 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_661 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_651 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_647 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_638 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_629 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_619 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_615 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_606 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_597 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_587 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_583 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_574 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_565 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_555 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_551 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_542 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_533 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_490 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_367 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_304 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_241 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_127 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_114 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_112 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_40 = load_const (0x00000001 /* 0.000000 */)
>	vec1 32 ssa_23 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_5 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_0 = deref_var &gl_GlobalInvocationID (system uvec3) 
>	vec3 32 ssa_3 = intrinsic load_deref (ssa_0) ()
>	vec1 32 ssa_4 = imov ssa_3.x
>	vec1 32 ssa_6 = ieq ssa_4, ssa_5
>	/* succs: block_1 block_2 */
>	if ssa_6 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_7 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_8 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_9 = iadd ssa_7, ssa_8
>		vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_11 = isub ssa_9, ssa_10
>		vec1 32 ssa_12 = intrinsic load_push_constant (ssa_11) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_13 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_14 = intrinsic vulkan_resource_index (ssa_13) (1, 0) /* desc-set=1 */ /* binding=0 */
>		vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_16 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_17 = iadd ssa_15, ssa_16
>		vec1 32 ssa_18 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_19 = imul ssa_12, ssa_18
>		vec1 32 ssa_20 = iadd ssa_17, ssa_19
>		vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_22 = iadd ssa_20, ssa_21
>		intrinsic store_ssbo (ssa_23, ssa_14, ssa_22) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_24 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_25 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_26 = iadd ssa_24, ssa_25
>		vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_28 = isub ssa_26, ssa_27
>		vec1 32 ssa_29 = intrinsic load_push_constant (ssa_28) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_30 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_31 = intrinsic vulkan_resource_index (ssa_30) (1, 0) /* desc-set=1 */ /* binding=0 */
>		vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_33 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_34 = iadd ssa_32, ssa_33
>		vec1 32 ssa_35 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_36 = imul ssa_29, ssa_35
>		vec1 32 ssa_37 = iadd ssa_34, ssa_36
>		vec1 32 ssa_38 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_39 = iadd ssa_37, ssa_38
>		intrinsic store_ssbo (ssa_40, ssa_31, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_41 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_42 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_43 = iadd ssa_41, ssa_42
>		vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_45 = isub ssa_43, ssa_44
>		vec1 32 ssa_46 = intrinsic load_push_constant (ssa_45) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_47 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_48 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_49 = iadd ssa_47, ssa_48
>		vec1 32 ssa_50 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_51 = isub ssa_49, ssa_50
>		vec1 32 ssa_52 = intrinsic load_push_constant (ssa_51) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_53 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_54 = intrinsic vulkan_resource_index (ssa_53) (1, 0) /* desc-set=1 */ /* binding=0 */
>		vec1 32 ssa_55 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_56 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_57 = iadd ssa_55, ssa_56
>		vec1 32 ssa_58 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_59 = imul ssa_46, ssa_58
>		vec1 32 ssa_60 = iadd ssa_57, ssa_59
>		vec1 32 ssa_61 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_62 = iadd ssa_60, ssa_61
>		intrinsic store_ssbo (ssa_52, ssa_54, ssa_62) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_64 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_65 = iadd ssa_63, ssa_64
>		vec1 32 ssa_66 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_67 = isub ssa_65, ssa_66
>		vec1 32 ssa_68 = intrinsic load_push_constant (ssa_67) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_69 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_70 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_71 = iadd ssa_69, ssa_70
>		vec1 32 ssa_72 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_73 = isub ssa_71, ssa_72
>		vec1 32 ssa_74 = intrinsic load_push_constant (ssa_73) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_75 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_76 = intrinsic vulkan_resource_index (ssa_75) (1, 0) /* desc-set=1 */ /* binding=0 */
>		vec1 32 ssa_77 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_79 = iadd ssa_77, ssa_78
>		vec1 32 ssa_80 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_81 = imul ssa_68, ssa_80
>		vec1 32 ssa_82 = iadd ssa_79, ssa_81
>		vec1 32 ssa_83 = load_const (0x00000008 /* 0.000000 */)
>		vec1 32 ssa_84 = iadd ssa_82, ssa_83
>		intrinsic store_ssbo (ssa_74, ssa_76, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_85 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_86 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_87 = iadd ssa_85, ssa_86
>		vec1 32 ssa_88 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_89 = isub ssa_87, ssa_88
>		vec1 32 ssa_90 = intrinsic load_push_constant (ssa_89) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_92 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_93 = iadd ssa_91, ssa_92
>		vec1 32 ssa_94 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_95 = isub ssa_93, ssa_94
>		vec1 32 ssa_96 = intrinsic load_push_constant (ssa_95) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_97 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_98 = intrinsic vulkan_resource_index (ssa_97) (1, 0) /* desc-set=1 */ /* binding=0 */
>		vec1 32 ssa_99 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_100 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_101 = iadd ssa_99, ssa_100
>		vec1 32 ssa_102 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_103 = imul ssa_90, ssa_102
>		vec1 32 ssa_104 = iadd ssa_101, ssa_103
>		vec1 32 ssa_105 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_106 = iadd ssa_104, ssa_105
>		intrinsic store_ssbo (ssa_96, ssa_98, ssa_106) (1, 0) /* wrmask=x */ /* access=0 */
>		/* succs: block_3 */
>	} else {
>		block block_2:
>		/* preds: block_0 */
>		/* succs: block_3 */
>	}
>	block block_3:
>	/* preds: block_1 block_2 */
>	vec1 32 ssa_107 = deref_var &gl_LocalInvocationID (system uvec3) 
>	vec3 32 ssa_110 = intrinsic load_deref (ssa_107) ()
>	vec1 32 ssa_111 = imov ssa_110.x
>	vec1 32 ssa_113 = ieq ssa_111, ssa_112
>	/* succs: block_4 block_5 */
>	if ssa_113 {
>		block block_4:
>		/* preds: block_3 */
>		vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */)
>		intrinsic store_shared (ssa_114, ssa_115) (0, 1) /* base=0 */ /* wrmask=x */
>		/* succs: block_6 */
>	} else {
>		block block_5:
>		/* preds: block_3 */
>		/* succs: block_6 */
>	}
>	block block_6:
>	/* preds: block_4 block_5 */
>	intrinsic memory_barrier_shared () ()
>	vec1 32 ssa_116 = deref_var &gl_GlobalInvocationID (system uvec3) 
>	vec3 32 ssa_119 = intrinsic load_deref (ssa_116) ()
>	vec1 32 ssa_120 = imov ssa_119.x
>	vec1 32 ssa_121 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_122 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_123 = iadd ssa_121, ssa_122
>	vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_125 = isub ssa_123, ssa_124
>	vec1 32 ssa_126 = intrinsic load_push_constant (ssa_125) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_128 = udiv ssa_126, ssa_127
>	vec1 32 ssa_129 = uge ssa_120, ssa_128
>	/* succs: block_7 block_8 */
>	if ssa_129 {
>		block block_7:
>		/* preds: block_6 */
>		return
>		/* succs: block_88 */
>	} else {
>		block block_8:
>		/* preds: block_6 */
>		/* succs: block_9 */
>	}
>	block block_9:
>	/* preds: block_8 */
>	vec1 32 ssa_130 = deref_var &gl_GlobalInvocationID (system uvec3) 
>	vec3 32 ssa_133 = intrinsic load_deref (ssa_130) ()
>	vec1 32 ssa_134 = imov ssa_133.x
>	vec1 32 ssa_135 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_136 = intrinsic vulkan_resource_index (ssa_135) (1, 1) /* desc-set=1 */ /* binding=1 */
>	vec1 32 ssa_137 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_138 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_139 = iadd ssa_137, ssa_138
>	vec1 32 ssa_140 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_141 = imul ssa_134, ssa_140
>	vec1 32 ssa_142 = iadd ssa_139, ssa_141
>	vec1 32 ssa_143 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_144 = iadd ssa_142, ssa_143
>	vec1 32 ssa_145 = intrinsic load_ssbo (ssa_136, ssa_144) (16) /* access=16 */
>	vec1 32 ssa_146 = deref_var &ix0 (local uint) 
>	intrinsic store_deref (ssa_146, ssa_145) (1) /* wrmask=x */
>	vec1 32 ssa_147 = deref_var &gl_GlobalInvocationID (system uvec3) 
>	vec3 32 ssa_150 = intrinsic load_deref (ssa_147) ()
>	vec1 32 ssa_151 = imov ssa_150.x
>	vec1 32 ssa_152 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_153 = intrinsic vulkan_resource_index (ssa_152) (1, 1) /* desc-set=1 */ /* binding=1 */
>	vec1 32 ssa_154 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_156 = iadd ssa_154, ssa_155
>	vec1 32 ssa_157 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_158 = imul ssa_151, ssa_157
>	vec1 32 ssa_159 = iadd ssa_156, ssa_158
>	vec1 32 ssa_160 = load_const (0x00000004 /* 0.000000 */)
>	vec1 32 ssa_161 = iadd ssa_159, ssa_160
>	vec1 32 ssa_162 = intrinsic load_ssbo (ssa_153, ssa_161) (16) /* access=16 */
>	vec1 32 ssa_163 = deref_var &ix1 (local uint) 
>	intrinsic store_deref (ssa_163, ssa_162) (1) /* wrmask=x */
>	vec1 32 ssa_164 = deref_var &gl_GlobalInvocationID (system uvec3) 
>	vec3 32 ssa_167 = intrinsic load_deref (ssa_164) ()
>	vec1 32 ssa_168 = imov ssa_167.x
>	vec1 32 ssa_169 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_170 = intrinsic vulkan_resource_index (ssa_169) (1, 1) /* desc-set=1 */ /* binding=1 */
>	vec1 32 ssa_171 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_172 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_173 = iadd ssa_171, ssa_172
>	vec1 32 ssa_174 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_175 = imul ssa_168, ssa_174
>	vec1 32 ssa_176 = iadd ssa_173, ssa_175
>	vec1 32 ssa_177 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_178 = iadd ssa_176, ssa_177
>	vec1 32 ssa_179 = intrinsic load_ssbo (ssa_170, ssa_178) (16) /* access=16 */
>	vec1 32 ssa_180 = deref_var &ix2 (local uint) 
>	intrinsic store_deref (ssa_180, ssa_179) (1) /* wrmask=x */
>	vec1 32 ssa_181 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_182 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_183 = iadd ssa_181, ssa_182
>	vec1 32 ssa_184 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_185 = isub ssa_183, ssa_184
>	vec1 32 ssa_186 = intrinsic load_push_constant (ssa_185) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_187 = deref_var &ix0 (local uint) 
>	vec1 32 ssa_188 = intrinsic load_deref (ssa_187) ()
>	vec1 32 ssa_189 = iadd ssa_186, ssa_188
>	vec1 32 ssa_190 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_191 = intrinsic vulkan_resource_index (ssa_190) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_192 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_193 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_194 = iadd ssa_192, ssa_193
>	vec1 32 ssa_195 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_196 = imul ssa_189, ssa_195
>	vec1 32 ssa_197 = iadd ssa_194, ssa_196
>	vec1 32 ssa_198 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_199 = iadd ssa_197, ssa_198
>	vec1 32 ssa_200 = intrinsic load_ssbo (ssa_191, ssa_199) (16) /* access=16 */
>	vec1 32 ssa_201 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_202 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_203 = iadd ssa_201, ssa_202
>	vec1 32 ssa_204 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_205 = isub ssa_203, ssa_204
>	vec1 32 ssa_206 = intrinsic load_push_constant (ssa_205) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_207 = deref_var &ix0 (local uint) 
>	vec1 32 ssa_208 = intrinsic load_deref (ssa_207) ()
>	vec1 32 ssa_209 = iadd ssa_206, ssa_208
>	vec1 32 ssa_210 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_211 = intrinsic vulkan_resource_index (ssa_210) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_212 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_213 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_214 = iadd ssa_212, ssa_213
>	vec1 32 ssa_215 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_216 = imul ssa_209, ssa_215
>	vec1 32 ssa_217 = iadd ssa_214, ssa_216
>	vec1 32 ssa_218 = load_const (0x00000004 /* 0.000000 */)
>	vec1 32 ssa_219 = iadd ssa_217, ssa_218
>	vec1 32 ssa_220 = intrinsic load_ssbo (ssa_211, ssa_219) (16) /* access=16 */
>	vec1 32 ssa_221 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_222 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_223 = iadd ssa_221, ssa_222
>	vec1 32 ssa_224 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_225 = isub ssa_223, ssa_224
>	vec1 32 ssa_226 = intrinsic load_push_constant (ssa_225) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_227 = deref_var &ix0 (local uint) 
>	vec1 32 ssa_228 = intrinsic load_deref (ssa_227) ()
>	vec1 32 ssa_229 = iadd ssa_226, ssa_228
>	vec1 32 ssa_230 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_231 = intrinsic vulkan_resource_index (ssa_230) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_232 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_233 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_234 = iadd ssa_232, ssa_233
>	vec1 32 ssa_235 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_236 = imul ssa_229, ssa_235
>	vec1 32 ssa_237 = iadd ssa_234, ssa_236
>	vec1 32 ssa_238 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_239 = iadd ssa_237, ssa_238
>	vec1 32 ssa_240 = intrinsic load_ssbo (ssa_231, ssa_239) (16) /* access=16 */
>	vec4 32 ssa_242 = vec4 ssa_200, ssa_220, ssa_240, ssa_241
>	vec1 32 ssa_243 = deref_var &input0 (local vec4) 
>	intrinsic store_deref (ssa_243, ssa_242) (15) /* wrmask=xyzw */
>	vec1 32 ssa_244 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_245 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_246 = iadd ssa_244, ssa_245
>	vec1 32 ssa_247 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_248 = isub ssa_246, ssa_247
>	vec1 32 ssa_249 = intrinsic load_push_constant (ssa_248) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_250 = deref_var &ix1 (local uint) 
>	vec1 32 ssa_251 = intrinsic load_deref (ssa_250) ()
>	vec1 32 ssa_252 = iadd ssa_249, ssa_251
>	vec1 32 ssa_253 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_254 = intrinsic vulkan_resource_index (ssa_253) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_255 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_256 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_257 = iadd ssa_255, ssa_256
>	vec1 32 ssa_258 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_259 = imul ssa_252, ssa_258
>	vec1 32 ssa_260 = iadd ssa_257, ssa_259
>	vec1 32 ssa_261 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_262 = iadd ssa_260, ssa_261
>	vec1 32 ssa_263 = intrinsic load_ssbo (ssa_254, ssa_262) (16) /* access=16 */
>	vec1 32 ssa_264 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_265 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_266 = iadd ssa_264, ssa_265
>	vec1 32 ssa_267 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_268 = isub ssa_266, ssa_267
>	vec1 32 ssa_269 = intrinsic load_push_constant (ssa_268) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_270 = deref_var &ix1 (local uint) 
>	vec1 32 ssa_271 = intrinsic load_deref (ssa_270) ()
>	vec1 32 ssa_272 = iadd ssa_269, ssa_271
>	vec1 32 ssa_273 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_274 = intrinsic vulkan_resource_index (ssa_273) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_275 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_276 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_277 = iadd ssa_275, ssa_276
>	vec1 32 ssa_278 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_279 = imul ssa_272, ssa_278
>	vec1 32 ssa_280 = iadd ssa_277, ssa_279
>	vec1 32 ssa_281 = load_const (0x00000004 /* 0.000000 */)
>	vec1 32 ssa_282 = iadd ssa_280, ssa_281
>	vec1 32 ssa_283 = intrinsic load_ssbo (ssa_274, ssa_282) (16) /* access=16 */
>	vec1 32 ssa_284 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_285 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_286 = iadd ssa_284, ssa_285
>	vec1 32 ssa_287 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_288 = isub ssa_286, ssa_287
>	vec1 32 ssa_289 = intrinsic load_push_constant (ssa_288) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_290 = deref_var &ix1 (local uint) 
>	vec1 32 ssa_291 = intrinsic load_deref (ssa_290) ()
>	vec1 32 ssa_292 = iadd ssa_289, ssa_291
>	vec1 32 ssa_293 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_294 = intrinsic vulkan_resource_index (ssa_293) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_295 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_296 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_297 = iadd ssa_295, ssa_296
>	vec1 32 ssa_298 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_299 = imul ssa_292, ssa_298
>	vec1 32 ssa_300 = iadd ssa_297, ssa_299
>	vec1 32 ssa_301 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_302 = iadd ssa_300, ssa_301
>	vec1 32 ssa_303 = intrinsic load_ssbo (ssa_294, ssa_302) (16) /* access=16 */
>	vec4 32 ssa_305 = vec4 ssa_263, ssa_283, ssa_303, ssa_304
>	vec1 32 ssa_306 = deref_var &input1 (local vec4) 
>	intrinsic store_deref (ssa_306, ssa_305) (15) /* wrmask=xyzw */
>	vec1 32 ssa_307 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_308 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_309 = iadd ssa_307, ssa_308
>	vec1 32 ssa_310 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_311 = isub ssa_309, ssa_310
>	vec1 32 ssa_312 = intrinsic load_push_constant (ssa_311) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_313 = deref_var &ix2 (local uint) 
>	vec1 32 ssa_314 = intrinsic load_deref (ssa_313) ()
>	vec1 32 ssa_315 = iadd ssa_312, ssa_314
>	vec1 32 ssa_316 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_317 = intrinsic vulkan_resource_index (ssa_316) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_318 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_319 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_320 = iadd ssa_318, ssa_319
>	vec1 32 ssa_321 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_322 = imul ssa_315, ssa_321
>	vec1 32 ssa_323 = iadd ssa_320, ssa_322
>	vec1 32 ssa_324 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_325 = iadd ssa_323, ssa_324
>	vec1 32 ssa_326 = intrinsic load_ssbo (ssa_317, ssa_325) (16) /* access=16 */
>	vec1 32 ssa_327 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_328 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_329 = iadd ssa_327, ssa_328
>	vec1 32 ssa_330 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_331 = isub ssa_329, ssa_330
>	vec1 32 ssa_332 = intrinsic load_push_constant (ssa_331) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_333 = deref_var &ix2 (local uint) 
>	vec1 32 ssa_334 = intrinsic load_deref (ssa_333) ()
>	vec1 32 ssa_335 = iadd ssa_332, ssa_334
>	vec1 32 ssa_336 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_337 = intrinsic vulkan_resource_index (ssa_336) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_338 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_339 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_340 = iadd ssa_338, ssa_339
>	vec1 32 ssa_341 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_342 = imul ssa_335, ssa_341
>	vec1 32 ssa_343 = iadd ssa_340, ssa_342
>	vec1 32 ssa_344 = load_const (0x00000004 /* 0.000000 */)
>	vec1 32 ssa_345 = iadd ssa_343, ssa_344
>	vec1 32 ssa_346 = intrinsic load_ssbo (ssa_337, ssa_345) (16) /* access=16 */
>	vec1 32 ssa_347 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_348 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_349 = iadd ssa_347, ssa_348
>	vec1 32 ssa_350 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_351 = isub ssa_349, ssa_350
>	vec1 32 ssa_352 = intrinsic load_push_constant (ssa_351) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_353 = deref_var &ix2 (local uint) 
>	vec1 32 ssa_354 = intrinsic load_deref (ssa_353) ()
>	vec1 32 ssa_355 = iadd ssa_352, ssa_354
>	vec1 32 ssa_356 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_357 = intrinsic vulkan_resource_index (ssa_356) (1, 2) /* desc-set=1 */ /* binding=2 */
>	vec1 32 ssa_358 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_359 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_360 = iadd ssa_358, ssa_359
>	vec1 32 ssa_361 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_362 = imul ssa_355, ssa_361
>	vec1 32 ssa_363 = iadd ssa_360, ssa_362
>	vec1 32 ssa_364 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_365 = iadd ssa_363, ssa_364
>	vec1 32 ssa_366 = intrinsic load_ssbo (ssa_357, ssa_365) (16) /* access=16 */
>	vec4 32 ssa_368 = vec4 ssa_326, ssa_346, ssa_366, ssa_367
>	vec1 32 ssa_369 = deref_var &input2 (local vec4) 
>	intrinsic store_deref (ssa_369, ssa_368) (15) /* wrmask=xyzw */
>	vec1 32 ssa_370 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_371 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_372 = iadd ssa_370, ssa_371
>	vec1 32 ssa_373 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_374 = isub ssa_372, ssa_373
>	vec1 32 ssa_375 = intrinsic load_push_constant (ssa_374) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_376 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_377 = intrinsic vulkan_resource_index (ssa_376) (0, 0) /* desc-set=0 */ /* binding=0 */
>	vec1 32 ssa_378 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_379 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_380 = iadd ssa_378, ssa_379
>	vec1 32 ssa_381 = load_const (0x00000040 /* 0.000000 */)
>	vec1 32 ssa_382 = imul ssa_375, ssa_381
>	vec1 32 ssa_383 = iadd ssa_380, ssa_382
>	vec1 32 ssa_384 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_385 = iadd ssa_383, ssa_384
>	vec4 32 ssa_386 = intrinsic load_ubo (ssa_377, ssa_385) ()
>	vec1 32 ssa_387 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_388 = iadd ssa_383, ssa_387
>	vec4 32 ssa_389 = intrinsic load_ubo (ssa_377, ssa_388) ()
>	vec1 32 ssa_390 = load_const (0x00000020 /* 0.000000 */)
>	vec1 32 ssa_391 = iadd ssa_383, ssa_390
>	vec4 32 ssa_392 = intrinsic load_ubo (ssa_377, ssa_391) ()
>	vec1 32 ssa_393 = load_const (0x00000030 /* 0.000000 */)
>	vec1 32 ssa_394 = iadd ssa_383, ssa_393
>	vec4 32 ssa_395 = intrinsic load_ubo (ssa_377, ssa_394) ()
>	vec1 32 ssa_396 = deref_var &input0 (local vec4) 
>	vec4 32 ssa_397 = intrinsic load_deref (ssa_396) ()
>	vec1 32 ssa_398 = imov ssa_397.x
>	vec4 32 ssa_399 = fmul ssa_386, ssa_398.xxxx
>	vec1 32 ssa_400 = imov ssa_397.y
>	vec4 32 ssa_401 = fmul ssa_389, ssa_400.xxxx
>	vec4 32 ssa_402 = fadd ssa_399, ssa_401
>	vec1 32 ssa_403 = imov ssa_397.z
>	vec4 32 ssa_404 = fmul ssa_392, ssa_403.xxxx
>	vec4 32 ssa_405 = fadd ssa_402, ssa_404
>	vec1 32 ssa_406 = imov ssa_397.w
>	vec4 32 ssa_407 = fmul ssa_395, ssa_406.xxxx
>	vec4 32 ssa_408 = fadd ssa_405, ssa_407
>	vec1 32 ssa_409 = deref_var &vertex0 (local vec4) 
>	intrinsic store_deref (ssa_409, ssa_408) (15) /* wrmask=xyzw */
>	vec1 32 ssa_410 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_411 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_412 = iadd ssa_410, ssa_411
>	vec1 32 ssa_413 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_414 = isub ssa_412, ssa_413
>	vec1 32 ssa_415 = intrinsic load_push_constant (ssa_414) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_416 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_417 = intrinsic vulkan_resource_index (ssa_416) (0, 0) /* desc-set=0 */ /* binding=0 */
>	vec1 32 ssa_418 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_419 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_420 = iadd ssa_418, ssa_419
>	vec1 32 ssa_421 = load_const (0x00000040 /* 0.000000 */)
>	vec1 32 ssa_422 = imul ssa_415, ssa_421
>	vec1 32 ssa_423 = iadd ssa_420, ssa_422
>	vec1 32 ssa_424 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_425 = iadd ssa_423, ssa_424
>	vec4 32 ssa_426 = intrinsic load_ubo (ssa_417, ssa_425) ()
>	vec1 32 ssa_427 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_428 = iadd ssa_423, ssa_427
>	vec4 32 ssa_429 = intrinsic load_ubo (ssa_417, ssa_428) ()
>	vec1 32 ssa_430 = load_const (0x00000020 /* 0.000000 */)
>	vec1 32 ssa_431 = iadd ssa_423, ssa_430
>	vec4 32 ssa_432 = intrinsic load_ubo (ssa_417, ssa_431) ()
>	vec1 32 ssa_433 = load_const (0x00000030 /* 0.000000 */)
>	vec1 32 ssa_434 = iadd ssa_423, ssa_433
>	vec4 32 ssa_435 = intrinsic load_ubo (ssa_417, ssa_434) ()
>	vec1 32 ssa_436 = deref_var &input1 (local vec4) 
>	vec4 32 ssa_437 = intrinsic load_deref (ssa_436) ()
>	vec1 32 ssa_438 = imov ssa_437.x
>	vec4 32 ssa_439 = fmul ssa_426, ssa_438.xxxx
>	vec1 32 ssa_440 = imov ssa_437.y
>	vec4 32 ssa_441 = fmul ssa_429, ssa_440.xxxx
>	vec4 32 ssa_442 = fadd ssa_439, ssa_441
>	vec1 32 ssa_443 = imov ssa_437.z
>	vec4 32 ssa_444 = fmul ssa_432, ssa_443.xxxx
>	vec4 32 ssa_445 = fadd ssa_442, ssa_444
>	vec1 32 ssa_446 = imov ssa_437.w
>	vec4 32 ssa_447 = fmul ssa_435, ssa_446.xxxx
>	vec4 32 ssa_448 = fadd ssa_445, ssa_447
>	vec1 32 ssa_449 = deref_var &vertex1 (local vec4) 
>	intrinsic store_deref (ssa_449, ssa_448) (15) /* wrmask=xyzw */
>	vec1 32 ssa_450 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_451 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_452 = iadd ssa_450, ssa_451
>	vec1 32 ssa_453 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_454 = isub ssa_452, ssa_453
>	vec1 32 ssa_455 = intrinsic load_push_constant (ssa_454) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_456 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_457 = intrinsic vulkan_resource_index (ssa_456) (0, 0) /* desc-set=0 */ /* binding=0 */
>	vec1 32 ssa_458 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_459 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_460 = iadd ssa_458, ssa_459
>	vec1 32 ssa_461 = load_const (0x00000040 /* 0.000000 */)
>	vec1 32 ssa_462 = imul ssa_455, ssa_461
>	vec1 32 ssa_463 = iadd ssa_460, ssa_462
>	vec1 32 ssa_464 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_465 = iadd ssa_463, ssa_464
>	vec4 32 ssa_466 = intrinsic load_ubo (ssa_457, ssa_465) ()
>	vec1 32 ssa_467 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_468 = iadd ssa_463, ssa_467
>	vec4 32 ssa_469 = intrinsic load_ubo (ssa_457, ssa_468) ()
>	vec1 32 ssa_470 = load_const (0x00000020 /* 0.000000 */)
>	vec1 32 ssa_471 = iadd ssa_463, ssa_470
>	vec4 32 ssa_472 = intrinsic load_ubo (ssa_457, ssa_471) ()
>	vec1 32 ssa_473 = load_const (0x00000030 /* 0.000000 */)
>	vec1 32 ssa_474 = iadd ssa_463, ssa_473
>	vec4 32 ssa_475 = intrinsic load_ubo (ssa_457, ssa_474) ()
>	vec1 32 ssa_476 = deref_var &input2 (local vec4) 
>	vec4 32 ssa_477 = intrinsic load_deref (ssa_476) ()
>	vec1 32 ssa_478 = imov ssa_477.x
>	vec4 32 ssa_479 = fmul ssa_466, ssa_478.xxxx
>	vec1 32 ssa_480 = imov ssa_477.y
>	vec4 32 ssa_481 = fmul ssa_469, ssa_480.xxxx
>	vec4 32 ssa_482 = fadd ssa_479, ssa_481
>	vec1 32 ssa_483 = imov ssa_477.z
>	vec4 32 ssa_484 = fmul ssa_472, ssa_483.xxxx
>	vec4 32 ssa_485 = fadd ssa_482, ssa_484
>	vec1 32 ssa_486 = imov ssa_477.w
>	vec4 32 ssa_487 = fmul ssa_475, ssa_486.xxxx
>	vec4 32 ssa_488 = fadd ssa_485, ssa_487
>	vec1 32 ssa_489 = deref_var &vertex2 (local vec4) 
>	intrinsic store_deref (ssa_489, ssa_488) (15) /* wrmask=xyzw */
>	vec1 32 ssa_491 = deref_var &cull (local bool) 
>	intrinsic store_deref (ssa_491, ssa_490) (1) /* wrmask=x */
>	vec1 32 ssa_492 = deref_var &vertex0 (local vec4) 
>	vec4 32 ssa_493 = intrinsic load_deref (ssa_492) ()
>	vec3 32 ssa_494 = vec3 ssa_493.x, ssa_493.y, ssa_493.z
>	vec1 32 ssa_495 = deref_var &vertex0 (local vec4) 
>	vec4 32 ssa_498 = intrinsic load_deref (ssa_495) ()
>	vec1 32 ssa_499 = imov ssa_498.w
>	vec3 32 ssa_500 = vec3 ssa_499, ssa_499, ssa_499
>	vec3 32 ssa_501 = fdiv ssa_494, ssa_500
>	vec1 32 ssa_502 = deref_var &ndc0 (local vec3) 
>	intrinsic store_deref (ssa_502, ssa_501) (7) /* wrmask=xyz */
>	vec1 32 ssa_503 = deref_var &vertex1 (local vec4) 
>	vec4 32 ssa_504 = intrinsic load_deref (ssa_503) ()
>	vec3 32 ssa_505 = vec3 ssa_504.x, ssa_504.y, ssa_504.z
>	vec1 32 ssa_506 = deref_var &vertex1 (local vec4) 
>	vec4 32 ssa_509 = intrinsic load_deref (ssa_506) ()
>	vec1 32 ssa_510 = imov ssa_509.w
>	vec3 32 ssa_511 = vec3 ssa_510, ssa_510, ssa_510
>	vec3 32 ssa_512 = fdiv ssa_505, ssa_511
>	vec1 32 ssa_513 = deref_var &ndc1 (local vec3) 
>	intrinsic store_deref (ssa_513, ssa_512) (7) /* wrmask=xyz */
>	vec1 32 ssa_514 = deref_var &vertex2 (local vec4) 
>	vec4 32 ssa_515 = intrinsic load_deref (ssa_514) ()
>	vec3 32 ssa_516 = vec3 ssa_515.x, ssa_515.y, ssa_515.z
>	vec1 32 ssa_517 = deref_var &vertex2 (local vec4) 
>	vec4 32 ssa_520 = intrinsic load_deref (ssa_517) ()
>	vec1 32 ssa_521 = imov ssa_520.w
>	vec3 32 ssa_522 = vec3 ssa_521, ssa_521, ssa_521
>	vec3 32 ssa_523 = fdiv ssa_516, ssa_522
>	vec1 32 ssa_524 = deref_var &ndc2 (local vec3) 
>	intrinsic store_deref (ssa_524, ssa_523) (7) /* wrmask=xyz */
>	vec1 32 ssa_525 = deref_var &cull (local bool) 
>	vec1 32 ssa_526 = intrinsic load_deref (ssa_525) ()
>	vec1 32 ssa_527 = inot ssa_526
>	vec1 32 ssa_822 = deref_var &phi (local bool) 
>	intrinsic store_deref (ssa_822, ssa_527) (1) /* wrmask=x */
>	/* succs: block_10 block_11 */
>	if ssa_527 {
>		block block_10:
>		/* preds: block_9 */
>		vec1 32 ssa_528 = deref_var &ndc0 (local vec3) 
>		vec3 32 ssa_531 = intrinsic load_deref (ssa_528) ()
>		vec1 32 ssa_532 = imov ssa_531.z
>		vec1 32 ssa_534 = flt ssa_533, ssa_532
>		vec1 32 ssa_823 = deref_var &phi (local bool) 
>		intrinsic store_deref (ssa_823, ssa_534) (1) /* wrmask=x */
>		/* succs: block_12 */
>	} else {
>		block block_11:
>		/* preds: block_9 */
>		/* succs: block_12 */
>	}
>	block block_12:
>	/* preds: block_10 block_11 */
>	vec1 32 ssa_535 = deref_var &phi (local bool) 
>	vec1 32 ssa_536 = intrinsic load_deref (ssa_535) ()
>	vec1 32 ssa_824 = deref_var &phi@0 (local bool) 
>	intrinsic store_deref (ssa_824, ssa_536) (1) /* wrmask=x */
>	/* succs: block_13 block_14 */
>	if ssa_536 {
>		block block_13:
>		/* preds: block_12 */
>		vec1 32 ssa_537 = deref_var &ndc1 (local vec3) 
>		vec3 32 ssa_540 = intrinsic load_deref (ssa_537) ()
>		vec1 32 ssa_541 = imov ssa_540.z
>		vec1 32 ssa_543 = flt ssa_542, ssa_541
>		vec1 32 ssa_825 = deref_var &phi@0 (local bool) 
>		intrinsic store_deref (ssa_825, ssa_543) (1) /* wrmask=x */
>		/* succs: block_15 */
>	} else {
>		block block_14:
>		/* preds: block_12 */
>		/* succs: block_15 */
>	}
>	block block_15:
>	/* preds: block_13 block_14 */
>	vec1 32 ssa_544 = deref_var &phi@0 (local bool) 
>	vec1 32 ssa_545 = intrinsic load_deref (ssa_544) ()
>	vec1 32 ssa_826 = deref_var &phi@1 (local bool) 
>	intrinsic store_deref (ssa_826, ssa_545) (1) /* wrmask=x */
>	/* succs: block_16 block_17 */
>	if ssa_545 {
>		block block_16:
>		/* preds: block_15 */
>		vec1 32 ssa_546 = deref_var &ndc2 (local vec3) 
>		vec3 32 ssa_549 = intrinsic load_deref (ssa_546) ()
>		vec1 32 ssa_550 = imov ssa_549.z
>		vec1 32 ssa_552 = flt ssa_551, ssa_550
>		vec1 32 ssa_827 = deref_var &phi@1 (local bool) 
>		intrinsic store_deref (ssa_827, ssa_552) (1) /* wrmask=x */
>		/* succs: block_18 */
>	} else {
>		block block_17:
>		/* preds: block_15 */
>		/* succs: block_18 */
>	}
>	block block_18:
>	/* preds: block_16 block_17 */
>	vec1 32 ssa_553 = deref_var &phi@1 (local bool) 
>	vec1 32 ssa_554 = intrinsic load_deref (ssa_553) ()
>	/* succs: block_19 block_20 */
>	if ssa_554 {
>		block block_19:
>		/* preds: block_18 */
>		vec1 32 ssa_556 = deref_var &cull (local bool) 
>		intrinsic store_deref (ssa_556, ssa_555) (1) /* wrmask=x */
>		/* succs: block_21 */
>	} else {
>		block block_20:
>		/* preds: block_18 */
>		/* succs: block_21 */
>	}
>	block block_21:
>	/* preds: block_19 block_20 */
>	vec1 32 ssa_557 = deref_var &cull (local bool) 
>	vec1 32 ssa_558 = intrinsic load_deref (ssa_557) ()
>	vec1 32 ssa_559 = inot ssa_558
>	vec1 32 ssa_828 = deref_var &phi@2 (local bool) 
>	intrinsic store_deref (ssa_828, ssa_559) (1) /* wrmask=x */
>	/* succs: block_22 block_23 */
>	if ssa_559 {
>		block block_22:
>		/* preds: block_21 */
>		vec1 32 ssa_560 = deref_var &ndc0 (local vec3) 
>		vec3 32 ssa_563 = intrinsic load_deref (ssa_560) ()
>		vec1 32 ssa_564 = imov ssa_563.z
>		vec1 32 ssa_566 = flt ssa_564, ssa_565
>		vec1 32 ssa_829 = deref_var &phi@2 (local bool) 
>		intrinsic store_deref (ssa_829, ssa_566) (1) /* wrmask=x */
>		/* succs: block_24 */
>	} else {
>		block block_23:
>		/* preds: block_21 */
>		/* succs: block_24 */
>	}
>	block block_24:
>	/* preds: block_22 block_23 */
>	vec1 32 ssa_567 = deref_var &phi@2 (local bool) 
>	vec1 32 ssa_568 = intrinsic load_deref (ssa_567) ()
>	vec1 32 ssa_830 = deref_var &phi@3 (local bool) 
>	intrinsic store_deref (ssa_830, ssa_568) (1) /* wrmask=x */
>	/* succs: block_25 block_26 */
>	if ssa_568 {
>		block block_25:
>		/* preds: block_24 */
>		vec1 32 ssa_569 = deref_var &ndc1 (local vec3) 
>		vec3 32 ssa_572 = intrinsic load_deref (ssa_569) ()
>		vec1 32 ssa_573 = imov ssa_572.z
>		vec1 32 ssa_575 = flt ssa_573, ssa_574
>		vec1 32 ssa_831 = deref_var &phi@3 (local bool) 
>		intrinsic store_deref (ssa_831, ssa_575) (1) /* wrmask=x */
>		/* succs: block_27 */
>	} else {
>		block block_26:
>		/* preds: block_24 */
>		/* succs: block_27 */
>	}
>	block block_27:
>	/* preds: block_25 block_26 */
>	vec1 32 ssa_576 = deref_var &phi@3 (local bool) 
>	vec1 32 ssa_577 = intrinsic load_deref (ssa_576) ()
>	vec1 32 ssa_832 = deref_var &phi@4 (local bool) 
>	intrinsic store_deref (ssa_832, ssa_577) (1) /* wrmask=x */
>	/* succs: block_28 block_29 */
>	if ssa_577 {
>		block block_28:
>		/* preds: block_27 */
>		vec1 32 ssa_578 = deref_var &ndc2 (local vec3) 
>		vec3 32 ssa_581 = intrinsic load_deref (ssa_578) ()
>		vec1 32 ssa_582 = imov ssa_581.z
>		vec1 32 ssa_584 = flt ssa_582, ssa_583
>		vec1 32 ssa_833 = deref_var &phi@4 (local bool) 
>		intrinsic store_deref (ssa_833, ssa_584) (1) /* wrmask=x */
>		/* succs: block_30 */
>	} else {
>		block block_29:
>		/* preds: block_27 */
>		/* succs: block_30 */
>	}
>	block block_30:
>	/* preds: block_28 block_29 */
>	vec1 32 ssa_585 = deref_var &phi@4 (local bool) 
>	vec1 32 ssa_586 = intrinsic load_deref (ssa_585) ()
>	/* succs: block_31 block_32 */
>	if ssa_586 {
>		block block_31:
>		/* preds: block_30 */
>		vec1 32 ssa_588 = deref_var &cull (local bool) 
>		intrinsic store_deref (ssa_588, ssa_587) (1) /* wrmask=x */
>		/* succs: block_33 */
>	} else {
>		block block_32:
>		/* preds: block_30 */
>		/* succs: block_33 */
>	}
>	block block_33:
>	/* preds: block_31 block_32 */
>	vec1 32 ssa_589 = deref_var &cull (local bool) 
>	vec1 32 ssa_590 = intrinsic load_deref (ssa_589) ()
>	vec1 32 ssa_591 = inot ssa_590
>	vec1 32 ssa_834 = deref_var &phi@5 (local bool) 
>	intrinsic store_deref (ssa_834, ssa_591) (1) /* wrmask=x */
>	/* succs: block_34 block_35 */
>	if ssa_591 {
>		block block_34:
>		/* preds: block_33 */
>		vec1 32 ssa_592 = deref_var &ndc0 (local vec3) 
>		vec3 32 ssa_595 = intrinsic load_deref (ssa_592) ()
>		vec1 32 ssa_596 = imov ssa_595.x
>		vec1 32 ssa_598 = flt ssa_596, ssa_597
>		vec1 32 ssa_835 = deref_var &phi@5 (local bool) 
>		intrinsic store_deref (ssa_835, ssa_598) (1) /* wrmask=x */
>		/* succs: block_36 */
>	} else {
>		block block_35:
>		/* preds: block_33 */
>		/* succs: block_36 */
>	}
>	block block_36:
>	/* preds: block_34 block_35 */
>	vec1 32 ssa_599 = deref_var &phi@5 (local bool) 
>	vec1 32 ssa_600 = intrinsic load_deref (ssa_599) ()
>	vec1 32 ssa_836 = deref_var &phi@6 (local bool) 
>	intrinsic store_deref (ssa_836, ssa_600) (1) /* wrmask=x */
>	/* succs: block_37 block_38 */
>	if ssa_600 {
>		block block_37:
>		/* preds: block_36 */
>		vec1 32 ssa_601 = deref_var &ndc1 (local vec3) 
>		vec3 32 ssa_604 = intrinsic load_deref (ssa_601) ()
>		vec1 32 ssa_605 = imov ssa_604.x
>		vec1 32 ssa_607 = flt ssa_605, ssa_606
>		vec1 32 ssa_837 = deref_var &phi@6 (local bool) 
>		intrinsic store_deref (ssa_837, ssa_607) (1) /* wrmask=x */
>		/* succs: block_39 */
>	} else {
>		block block_38:
>		/* preds: block_36 */
>		/* succs: block_39 */
>	}
>	block block_39:
>	/* preds: block_37 block_38 */
>	vec1 32 ssa_608 = deref_var &phi@6 (local bool) 
>	vec1 32 ssa_609 = intrinsic load_deref (ssa_608) ()
>	vec1 32 ssa_838 = deref_var &phi@7 (local bool) 
>	intrinsic store_deref (ssa_838, ssa_609) (1) /* wrmask=x */
>	/* succs: block_40 block_41 */
>	if ssa_609 {
>		block block_40:
>		/* preds: block_39 */
>		vec1 32 ssa_610 = deref_var &ndc2 (local vec3) 
>		vec3 32 ssa_613 = intrinsic load_deref (ssa_610) ()
>		vec1 32 ssa_614 = imov ssa_613.x
>		vec1 32 ssa_616 = flt ssa_614, ssa_615
>		vec1 32 ssa_839 = deref_var &phi@7 (local bool) 
>		intrinsic store_deref (ssa_839, ssa_616) (1) /* wrmask=x */
>		/* succs: block_42 */
>	} else {
>		block block_41:
>		/* preds: block_39 */
>		/* succs: block_42 */
>	}
>	block block_42:
>	/* preds: block_40 block_41 */
>	vec1 32 ssa_617 = deref_var &phi@7 (local bool) 
>	vec1 32 ssa_618 = intrinsic load_deref (ssa_617) ()
>	/* succs: block_43 block_44 */
>	if ssa_618 {
>		block block_43:
>		/* preds: block_42 */
>		vec1 32 ssa_620 = deref_var &cull (local bool) 
>		intrinsic store_deref (ssa_620, ssa_619) (1) /* wrmask=x */
>		/* succs: block_45 */
>	} else {
>		block block_44:
>		/* preds: block_42 */
>		/* succs: block_45 */
>	}
>	block block_45:
>	/* preds: block_43 block_44 */
>	vec1 32 ssa_621 = deref_var &cull (local bool) 
>	vec1 32 ssa_622 = intrinsic load_deref (ssa_621) ()
>	vec1 32 ssa_623 = inot ssa_622
>	vec1 32 ssa_840 = deref_var &phi@8 (local bool) 
>	intrinsic store_deref (ssa_840, ssa_623) (1) /* wrmask=x */
>	/* succs: block_46 block_47 */
>	if ssa_623 {
>		block block_46:
>		/* preds: block_45 */
>		vec1 32 ssa_624 = deref_var &ndc0 (local vec3) 
>		vec3 32 ssa_627 = intrinsic load_deref (ssa_624) ()
>		vec1 32 ssa_628 = imov ssa_627.x
>		vec1 32 ssa_630 = flt ssa_629, ssa_628
>		vec1 32 ssa_841 = deref_var &phi@8 (local bool) 
>		intrinsic store_deref (ssa_841, ssa_630) (1) /* wrmask=x */
>		/* succs: block_48 */
>	} else {
>		block block_47:
>		/* preds: block_45 */
>		/* succs: block_48 */
>	}
>	block block_48:
>	/* preds: block_46 block_47 */
>	vec1 32 ssa_631 = deref_var &phi@8 (local bool) 
>	vec1 32 ssa_632 = intrinsic load_deref (ssa_631) ()
>	vec1 32 ssa_842 = deref_var &phi@9 (local bool) 
>	intrinsic store_deref (ssa_842, ssa_632) (1) /* wrmask=x */
>	/* succs: block_49 block_50 */
>	if ssa_632 {
>		block block_49:
>		/* preds: block_48 */
>		vec1 32 ssa_633 = deref_var &ndc1 (local vec3) 
>		vec3 32 ssa_636 = intrinsic load_deref (ssa_633) ()
>		vec1 32 ssa_637 = imov ssa_636.x
>		vec1 32 ssa_639 = flt ssa_638, ssa_637
>		vec1 32 ssa_843 = deref_var &phi@9 (local bool) 
>		intrinsic store_deref (ssa_843, ssa_639) (1) /* wrmask=x */
>		/* succs: block_51 */
>	} else {
>		block block_50:
>		/* preds: block_48 */
>		/* succs: block_51 */
>	}
>	block block_51:
>	/* preds: block_49 block_50 */
>	vec1 32 ssa_640 = deref_var &phi@9 (local bool) 
>	vec1 32 ssa_641 = intrinsic load_deref (ssa_640) ()
>	vec1 32 ssa_844 = deref_var &phi@10 (local bool) 
>	intrinsic store_deref (ssa_844, ssa_641) (1) /* wrmask=x */
>	/* succs: block_52 block_53 */
>	if ssa_641 {
>		block block_52:
>		/* preds: block_51 */
>		vec1 32 ssa_642 = deref_var &ndc2 (local vec3) 
>		vec3 32 ssa_645 = intrinsic load_deref (ssa_642) ()
>		vec1 32 ssa_646 = imov ssa_645.x
>		vec1 32 ssa_648 = flt ssa_647, ssa_646
>		vec1 32 ssa_845 = deref_var &phi@10 (local bool) 
>		intrinsic store_deref (ssa_845, ssa_648) (1) /* wrmask=x */
>		/* succs: block_54 */
>	} else {
>		block block_53:
>		/* preds: block_51 */
>		/* succs: block_54 */
>	}
>	block block_54:
>	/* preds: block_52 block_53 */
>	vec1 32 ssa_649 = deref_var &phi@10 (local bool) 
>	vec1 32 ssa_650 = intrinsic load_deref (ssa_649) ()
>	/* succs: block_55 block_56 */
>	if ssa_650 {
>		block block_55:
>		/* preds: block_54 */
>		vec1 32 ssa_652 = deref_var &cull (local bool) 
>		intrinsic store_deref (ssa_652, ssa_651) (1) /* wrmask=x */
>		/* succs: block_57 */
>	} else {
>		block block_56:
>		/* preds: block_54 */
>		/* succs: block_57 */
>	}
>	block block_57:
>	/* preds: block_55 block_56 */
>	vec1 32 ssa_653 = deref_var &cull (local bool) 
>	vec1 32 ssa_654 = intrinsic load_deref (ssa_653) ()
>	vec1 32 ssa_655 = inot ssa_654
>	vec1 32 ssa_846 = deref_var &phi@11 (local bool) 
>	intrinsic store_deref (ssa_846, ssa_655) (1) /* wrmask=x */
>	/* succs: block_58 block_59 */
>	if ssa_655 {
>		block block_58:
>		/* preds: block_57 */
>		vec1 32 ssa_656 = deref_var &ndc0 (local vec3) 
>		vec3 32 ssa_659 = intrinsic load_deref (ssa_656) ()
>		vec1 32 ssa_660 = imov ssa_659.y
>		vec1 32 ssa_662 = flt ssa_660, ssa_661
>		vec1 32 ssa_847 = deref_var &phi@11 (local bool) 
>		intrinsic store_deref (ssa_847, ssa_662) (1) /* wrmask=x */
>		/* succs: block_60 */
>	} else {
>		block block_59:
>		/* preds: block_57 */
>		/* succs: block_60 */
>	}
>	block block_60:
>	/* preds: block_58 block_59 */
>	vec1 32 ssa_663 = deref_var &phi@11 (local bool) 
>	vec1 32 ssa_664 = intrinsic load_deref (ssa_663) ()
>	vec1 32 ssa_848 = deref_var &phi@12 (local bool) 
>	intrinsic store_deref (ssa_848, ssa_664) (1) /* wrmask=x */
>	/* succs: block_61 block_62 */
>	if ssa_664 {
>		block block_61:
>		/* preds: block_60 */
>		vec1 32 ssa_665 = deref_var &ndc1 (local vec3) 
>		vec3 32 ssa_668 = intrinsic load_deref (ssa_665) ()
>		vec1 32 ssa_669 = imov ssa_668.y
>		vec1 32 ssa_671 = flt ssa_669, ssa_670
>		vec1 32 ssa_849 = deref_var &phi@12 (local bool) 
>		intrinsic store_deref (ssa_849, ssa_671) (1) /* wrmask=x */
>		/* succs: block_63 */
>	} else {
>		block block_62:
>		/* preds: block_60 */
>		/* succs: block_63 */
>	}
>	block block_63:
>	/* preds: block_61 block_62 */
>	vec1 32 ssa_672 = deref_var &phi@12 (local bool) 
>	vec1 32 ssa_673 = intrinsic load_deref (ssa_672) ()
>	vec1 32 ssa_850 = deref_var &phi@13 (local bool) 
>	intrinsic store_deref (ssa_850, ssa_673) (1) /* wrmask=x */
>	/* succs: block_64 block_65 */
>	if ssa_673 {
>		block block_64:
>		/* preds: block_63 */
>		vec1 32 ssa_674 = deref_var &ndc2 (local vec3) 
>		vec3 32 ssa_677 = intrinsic load_deref (ssa_674) ()
>		vec1 32 ssa_678 = imov ssa_677.y
>		vec1 32 ssa_680 = flt ssa_678, ssa_679
>		vec1 32 ssa_851 = deref_var &phi@13 (local bool) 
>		intrinsic store_deref (ssa_851, ssa_680) (1) /* wrmask=x */
>		/* succs: block_66 */
>	} else {
>		block block_65:
>		/* preds: block_63 */
>		/* succs: block_66 */
>	}
>	block block_66:
>	/* preds: block_64 block_65 */
>	vec1 32 ssa_681 = deref_var &phi@13 (local bool) 
>	vec1 32 ssa_682 = intrinsic load_deref (ssa_681) ()
>	/* succs: block_67 block_68 */
>	if ssa_682 {
>		block block_67:
>		/* preds: block_66 */
>		vec1 32 ssa_684 = deref_var &cull (local bool) 
>		intrinsic store_deref (ssa_684, ssa_683) (1) /* wrmask=x */
>		/* succs: block_69 */
>	} else {
>		block block_68:
>		/* preds: block_66 */
>		/* succs: block_69 */
>	}
>	block block_69:
>	/* preds: block_67 block_68 */
>	vec1 32 ssa_685 = deref_var &cull (local bool) 
>	vec1 32 ssa_686 = intrinsic load_deref (ssa_685) ()
>	vec1 32 ssa_687 = inot ssa_686
>	vec1 32 ssa_852 = deref_var &phi@14 (local bool) 
>	intrinsic store_deref (ssa_852, ssa_687) (1) /* wrmask=x */
>	/* succs: block_70 block_71 */
>	if ssa_687 {
>		block block_70:
>		/* preds: block_69 */
>		vec1 32 ssa_688 = deref_var &ndc0 (local vec3) 
>		vec3 32 ssa_691 = intrinsic load_deref (ssa_688) ()
>		vec1 32 ssa_692 = imov ssa_691.y
>		vec1 32 ssa_694 = flt ssa_693, ssa_692
>		vec1 32 ssa_853 = deref_var &phi@14 (local bool) 
>		intrinsic store_deref (ssa_853, ssa_694) (1) /* wrmask=x */
>		/* succs: block_72 */
>	} else {
>		block block_71:
>		/* preds: block_69 */
>		/* succs: block_72 */
>	}
>	block block_72:
>	/* preds: block_70 block_71 */
>	vec1 32 ssa_695 = deref_var &phi@14 (local bool) 
>	vec1 32 ssa_696 = intrinsic load_deref (ssa_695) ()
>	vec1 32 ssa_854 = deref_var &phi@15 (local bool) 
>	intrinsic store_deref (ssa_854, ssa_696) (1) /* wrmask=x */
>	/* succs: block_73 block_74 */
>	if ssa_696 {
>		block block_73:
>		/* preds: block_72 */
>		vec1 32 ssa_697 = deref_var &ndc1 (local vec3) 
>		vec3 32 ssa_700 = intrinsic load_deref (ssa_697) ()
>		vec1 32 ssa_701 = imov ssa_700.y
>		vec1 32 ssa_703 = flt ssa_702, ssa_701
>		vec1 32 ssa_855 = deref_var &phi@15 (local bool) 
>		intrinsic store_deref (ssa_855, ssa_703) (1) /* wrmask=x */
>		/* succs: block_75 */
>	} else {
>		block block_74:
>		/* preds: block_72 */
>		/* succs: block_75 */
>	}
>	block block_75:
>	/* preds: block_73 block_74 */
>	vec1 32 ssa_704 = deref_var &phi@15 (local bool) 
>	vec1 32 ssa_705 = intrinsic load_deref (ssa_704) ()
>	vec1 32 ssa_856 = deref_var &phi@16 (local bool) 
>	intrinsic store_deref (ssa_856, ssa_705) (1) /* wrmask=x */
>	/* succs: block_76 block_77 */
>	if ssa_705 {
>		block block_76:
>		/* preds: block_75 */
>		vec1 32 ssa_706 = deref_var &ndc2 (local vec3) 
>		vec3 32 ssa_709 = intrinsic load_deref (ssa_706) ()
>		vec1 32 ssa_710 = imov ssa_709.y
>		vec1 32 ssa_712 = flt ssa_711, ssa_710
>		vec1 32 ssa_857 = deref_var &phi@16 (local bool) 
>		intrinsic store_deref (ssa_857, ssa_712) (1) /* wrmask=x */
>		/* succs: block_78 */
>	} else {
>		block block_77:
>		/* preds: block_75 */
>		/* succs: block_78 */
>	}
>	block block_78:
>	/* preds: block_76 block_77 */
>	vec1 32 ssa_713 = deref_var &phi@16 (local bool) 
>	vec1 32 ssa_714 = intrinsic load_deref (ssa_713) ()
>	/* succs: block_79 block_80 */
>	if ssa_714 {
>		block block_79:
>		/* preds: block_78 */
>		vec1 32 ssa_716 = deref_var &cull (local bool) 
>		intrinsic store_deref (ssa_716, ssa_715) (1) /* wrmask=x */
>		/* succs: block_81 */
>	} else {
>		block block_80:
>		/* preds: block_78 */
>		/* succs: block_81 */
>	}
>	block block_81:
>	/* preds: block_79 block_80 */
>	vec1 32 ssa_717 = deref_var &cull (local bool) 
>	vec1 32 ssa_718 = intrinsic load_deref (ssa_717) ()
>	vec1 32 ssa_719 = inot ssa_718
>	/* succs: block_82 block_83 */
>	if ssa_719 {
>		block block_82:
>		/* preds: block_81 */
>		vec1 32 ssa_720 = deref_var &vertex0 (local vec4) 
>		vec4 32 ssa_721 = intrinsic load_deref (ssa_720) ()
>		vec3 32 ssa_722 = vec3 ssa_721.x, ssa_721.y, ssa_721.w
>		vec1 32 ssa_723 = deref_var &vertex1 (local vec4) 
>		vec4 32 ssa_724 = intrinsic load_deref (ssa_723) ()
>		vec3 32 ssa_725 = vec3 ssa_724.x, ssa_724.y, ssa_724.w
>		vec1 32 ssa_726 = deref_var &vertex2 (local vec4) 
>		vec4 32 ssa_727 = intrinsic load_deref (ssa_726) ()
>		vec3 32 ssa_728 = vec3 ssa_727.x, ssa_727.y, ssa_727.w
>		vec1 32 ssa_729 = imov ssa_722.x
>		vec1 32 ssa_730 = imov ssa_722.y
>		vec1 32 ssa_731 = imov ssa_722.z
>		vec1 32 ssa_732 = imov ssa_725.x
>		vec1 32 ssa_733 = imov ssa_725.y
>		vec1 32 ssa_734 = imov ssa_725.z
>		vec1 32 ssa_735 = imov ssa_728.x
>		vec1 32 ssa_736 = imov ssa_728.y
>		vec1 32 ssa_737 = imov ssa_728.z
>		vec3 32 ssa_738 = vec3 ssa_729, ssa_730, ssa_731
>		vec3 32 ssa_739 = vec3 ssa_732, ssa_733, ssa_734
>		vec3 32 ssa_740 = vec3 ssa_735, ssa_736, ssa_737
>		vec3 32 ssa_741 = fmov ssa_740.zxy
>		vec3 32 ssa_742 = fmov ssa_739.yzx
>		vec3 32 ssa_743 = fmul ssa_742, ssa_741
>		vec3 32 ssa_744 = fmul ssa_738, ssa_743
>		vec3 32 ssa_745 = fmov ssa_740.yzx
>		vec3 32 ssa_746 = fmov ssa_739.zxy
>		vec3 32 ssa_747 = fmul ssa_746, ssa_745
>		vec3 32 ssa_748 = fmul ssa_738, ssa_747
>		vec3 32 ssa_749 = fsub ssa_744, ssa_748
>		vec1 32 ssa_750 = imov ssa_749.z
>		vec1 32 ssa_751 = imov ssa_749.y
>		vec1 32 ssa_752 = fadd ssa_751, ssa_750
>		vec1 32 ssa_753 = imov ssa_749.x
>		vec1 32 ssa_754 = fadd ssa_753, ssa_752
>		vec1 32 ssa_756 = flt ssa_755, ssa_754
>		vec1 32 ssa_757 = deref_var &cull (local bool) 
>		intrinsic store_deref (ssa_757, ssa_756) (1) /* wrmask=x */
>		/* succs: block_84 */
>	} else {
>		block block_83:
>		/* preds: block_81 */
>		/* succs: block_84 */
>	}
>	block block_84:
>	/* preds: block_82 block_83 */
>	intrinsic barrier () ()
>	intrinsic group_memory_barrier () ()
>	vec1 32 ssa_758 = deref_var &cull (local bool) 
>	vec1 32 ssa_759 = intrinsic load_deref (ssa_758) ()
>	vec1 32 ssa_760 = inot ssa_759
>	/* succs: block_85 block_86 */
>	if ssa_760 {
>		block block_85:
>		/* preds: block_84 */
>		vec1 32 ssa_761 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_762 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_763 = iadd ssa_761, ssa_762
>		vec1 32 ssa_764 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_765 = isub ssa_763, ssa_764
>		vec1 32 ssa_766 = intrinsic load_push_constant (ssa_765) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_767 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_768 = intrinsic vulkan_resource_index (ssa_767) (1, 0) /* desc-set=1 */ /* binding=0 */
>		vec1 32 ssa_769 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_770 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_771 = iadd ssa_769, ssa_770
>		vec1 32 ssa_772 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_773 = imul ssa_766, ssa_772
>		vec1 32 ssa_774 = iadd ssa_771, ssa_773
>		vec1 32 ssa_775 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_776 = iadd ssa_774, ssa_775
>		vec1 32 ssa_778 = intrinsic ssbo_atomic_add (ssa_768, ssa_776, ssa_777) ()
>		vec1 32 ssa_779 = deref_var &local_offset (local uint) 
>		intrinsic store_deref (ssa_779, ssa_778) (1) /* wrmask=x */
>		vec1 32 ssa_780 = deref_var &local_offset (local uint) 
>		vec1 32 ssa_781 = intrinsic load_deref (ssa_780) ()
>		vec1 32 ssa_782 = deref_var &ix0 (local uint) 
>		vec1 32 ssa_783 = intrinsic load_deref (ssa_782) ()
>		vec1 32 ssa_784 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_785 = intrinsic vulkan_resource_index (ssa_784) (1, 3) /* desc-set=1 */ /* binding=3 */
>		vec1 32 ssa_786 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_787 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_788 = iadd ssa_786, ssa_787
>		vec1 32 ssa_789 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_790 = imul ssa_781, ssa_789
>		vec1 32 ssa_791 = iadd ssa_788, ssa_790
>		vec1 32 ssa_792 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_793 = iadd ssa_791, ssa_792
>		intrinsic store_ssbo (ssa_783, ssa_785, ssa_793) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_794 = deref_var &local_offset (local uint) 
>		vec1 32 ssa_795 = intrinsic load_deref (ssa_794) ()
>		vec1 32 ssa_796 = deref_var &ix1 (local uint) 
>		vec1 32 ssa_797 = intrinsic load_deref (ssa_796) ()
>		vec1 32 ssa_798 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_799 = intrinsic vulkan_resource_index (ssa_798) (1, 3) /* desc-set=1 */ /* binding=3 */
>		vec1 32 ssa_800 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_801 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_802 = iadd ssa_800, ssa_801
>		vec1 32 ssa_803 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_804 = imul ssa_795, ssa_803
>		vec1 32 ssa_805 = iadd ssa_802, ssa_804
>		vec1 32 ssa_806 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_807 = iadd ssa_805, ssa_806
>		intrinsic store_ssbo (ssa_797, ssa_799, ssa_807) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_808 = deref_var &local_offset (local uint) 
>		vec1 32 ssa_809 = intrinsic load_deref (ssa_808) ()
>		vec1 32 ssa_810 = deref_var &ix2 (local uint) 
>		vec1 32 ssa_811 = intrinsic load_deref (ssa_810) ()
>		vec1 32 ssa_812 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_813 = intrinsic vulkan_resource_index (ssa_812) (1, 3) /* desc-set=1 */ /* binding=3 */
>		vec1 32 ssa_814 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_815 = load_const (0x00000000 /* 0.000000 */)
>		vec1 32 ssa_816 = iadd ssa_814, ssa_815
>		vec1 32 ssa_817 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_818 = imul ssa_809, ssa_817
>		vec1 32 ssa_819 = iadd ssa_816, ssa_818
>		vec1 32 ssa_820 = load_const (0x00000008 /* 0.000000 */)
>		vec1 32 ssa_821 = iadd ssa_819, ssa_820
>		intrinsic store_ssbo (ssa_811, ssa_813, ssa_821) (1, 0) /* wrmask=x */ /* access=0 */
>		/* succs: block_87 */
>	} else {
>		block block_86:
>		/* preds: block_84 */
>		/* succs: block_87 */
>	}
>	block block_87:
>	/* preds: block_85 block_86 */
>	return
>	/* succs: block_88 */
>	block block_88:
>}
>
>NIR (SSA form) for compute shader:
>shader: MESA_SHADER_COMPUTE
>local-size: 64, 1, 1
>shared-size: 1
>inputs: 0
>outputs: 0
>uniforms: 140
>shared: 4
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_2 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_3 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_4 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */)
>	vec3 32 ssa_6 = intrinsic load_work_group_id () ()
>	vec3 32 ssa_7 = intrinsic load_uniform (ssa_1) (128, 12) /* base=128 */ /* range=12 */
>	vec1 32 ssa_8 = iadd ssa_6.x, ssa_7.x
>	vec1 32 ssa_9 = intrinsic load_subgroup_id () ()
>	vec1 32 ssa_10 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_11 = ishl ssa_9, ssa_0
>	vec1 32 ssa_12 = intrinsic load_subgroup_invocation () ()
>	vec1 32 ssa_13 = iadd ssa_12, ssa_11
>	vec1 32 ssa_14 = load_const (0x0000003f /* 0.000000 */)
>	vec1 32 ssa_15 = iand ssa_13, ssa_14
>	vec1 32 ssa_16 = load_const (0x00000006 /* 0.000000 */)
>	vec1 32 ssa_17 = ishl ssa_8, ssa_16
>	vec1 32 ssa_18 = iadd ssa_17, ssa_15
>	vec1 32 ssa_19 = ieq ssa_18, ssa_1
>	/* succs: block_1 block_2 */
>	if ssa_19 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_20 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_21 = intrinsic load_uniform (ssa_20) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_22 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_23 = imul ssa_21, ssa_22
>		intrinsic store_ssbo (ssa_1, ssa_5, ssa_23) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_24 = iadd ssa_20, ssa_23
>		intrinsic store_ssbo (ssa_5, ssa_5, ssa_24) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_25 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_26 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_27 = iadd ssa_26, ssa_23
>		intrinsic store_ssbo (ssa_25, ssa_5, ssa_27) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_28 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_29 = intrinsic load_uniform (ssa_28) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_30 = iadd ssa_10, ssa_23
>		intrinsic store_ssbo (ssa_29, ssa_5, ssa_30) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_31 = intrinsic load_uniform (ssa_26) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_32 = iadd ssa_28, ssa_23
>		intrinsic store_ssbo (ssa_31, ssa_5, ssa_32) (1, 0) /* wrmask=x */ /* access=0 */
>		/* succs: block_3 */
>	} else {
>		block block_2:
>		/* preds: block_0 */
>		/* succs: block_3 */
>	}
>	block block_3:
>	/* preds: block_1 block_2 */
>	vec1 32 ssa_33 = ieq ssa_15, ssa_1
>	/* succs: block_4 block_5 */
>	if ssa_33 {
>		block block_4:
>		/* preds: block_3 */
>		intrinsic store_shared (ssa_1, ssa_1) (0, 1) /* base=0 */ /* wrmask=x */
>		/* succs: block_6 */
>	} else {
>		block block_5:
>		/* preds: block_3 */
>		/* succs: block_6 */
>	}
>	block block_6:
>	/* preds: block_4 block_5 */
>	intrinsic memory_barrier_shared () ()
>	vec1 32 ssa_34 = intrinsic load_uniform (ssa_10) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_35 = udiv ssa_34, ssa_0
>	vec1 32 ssa_36 = ult ssa_18, ssa_35
>	/* succs: block_7 block_65 */
>	if ssa_36 {
>		block block_7:
>		/* preds: block_6 */
>		vec1 32 ssa_37 = load_const (0x00000002 /* 0.000000 */)
>		vec1 32 ssa_38 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_39 = imul ssa_18, ssa_38
>		vec1 32 ssa_40 = intrinsic load_ssbo (ssa_37, ssa_39) (16) /* access=16 */
>		vec1 32 ssa_41 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_42 = iadd ssa_41, ssa_39
>		vec1 32 ssa_43 = intrinsic load_ssbo (ssa_37, ssa_42) (16) /* access=16 */
>		vec1 32 ssa_44 = iadd ssa_10, ssa_39
>		vec1 32 ssa_45 = intrinsic load_ssbo (ssa_37, ssa_44) (16) /* access=16 */
>		vec1 32 ssa_46 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_47 = intrinsic load_uniform (ssa_46) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_48 = iadd ssa_47, ssa_40
>		vec1 32 ssa_49 = imul ssa_48, ssa_38
>		vec1 32 ssa_50 = intrinsic load_ssbo (ssa_0, ssa_49) (16) /* access=16 */
>		vec1 32 ssa_51 = iadd ssa_41, ssa_49
>		vec1 32 ssa_52 = intrinsic load_ssbo (ssa_0, ssa_51) (16) /* access=16 */
>		vec1 32 ssa_53 = iadd ssa_10, ssa_49
>		vec1 32 ssa_54 = intrinsic load_ssbo (ssa_0, ssa_53) (16) /* access=16 */
>		vec1 32 ssa_55 = iadd ssa_47, ssa_43
>		vec1 32 ssa_56 = imul ssa_55, ssa_38
>		vec1 32 ssa_57 = intrinsic load_ssbo (ssa_0, ssa_56) (16) /* access=16 */
>		vec1 32 ssa_58 = iadd ssa_41, ssa_56
>		vec1 32 ssa_59 = intrinsic load_ssbo (ssa_0, ssa_58) (16) /* access=16 */
>		vec1 32 ssa_60 = iadd ssa_10, ssa_56
>		vec1 32 ssa_61 = intrinsic load_ssbo (ssa_0, ssa_60) (16) /* access=16 */
>		vec1 32 ssa_62 = iadd ssa_47, ssa_45
>		vec1 32 ssa_63 = imul ssa_62, ssa_38
>		vec1 32 ssa_64 = intrinsic load_ssbo (ssa_0, ssa_63) (16) /* access=16 */
>		vec1 32 ssa_65 = iadd ssa_41, ssa_63
>		vec1 32 ssa_66 = intrinsic load_ssbo (ssa_0, ssa_65) (16) /* access=16 */
>		vec1 32 ssa_67 = iadd ssa_10, ssa_63
>		vec1 32 ssa_68 = intrinsic load_ssbo (ssa_0, ssa_67) (16) /* access=16 */
>		vec1 32 ssa_69 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_70 = ishl ssa_69, ssa_16
>		vec4 32 ssa_71 = intrinsic load_ubo (ssa_1, ssa_70) ()
>		vec1 32 ssa_72 = iadd ssa_46, ssa_70
>		vec4 32 ssa_73 = intrinsic load_ubo (ssa_1, ssa_72) ()
>		vec1 32 ssa_74 = load_const (0x00000020 /* 0.000000 */)
>		vec1 32 ssa_75 = iadd ssa_74, ssa_70
>		vec4 32 ssa_76 = intrinsic load_ubo (ssa_1, ssa_75) ()
>		vec1 32 ssa_77 = load_const (0x00000030 /* 0.000000 */)
>		vec1 32 ssa_78 = iadd ssa_77, ssa_70
>		vec4 32 ssa_79 = intrinsic load_ubo (ssa_1, ssa_78) ()
>		vec1 32 ssa_80 = fmul ssa_73.x, ssa_52
>		vec1 32 ssa_81 = fmul ssa_73.y, ssa_52
>		vec1 32 ssa_82 = fmul ssa_73.z, ssa_52
>		vec1 32 ssa_83 = fmul ssa_73.w, ssa_52
>		vec1 32 ssa_84 = ffma ssa_71.x, ssa_50, ssa_80
>		vec1 32 ssa_85 = ffma ssa_71.y, ssa_50, ssa_81
>		vec1 32 ssa_86 = ffma ssa_71.z, ssa_50, ssa_82
>		vec1 32 ssa_87 = ffma ssa_71.w, ssa_50, ssa_83
>		vec1 32 ssa_88 = ffma ssa_76.x, ssa_54, ssa_84
>		vec1 32 ssa_89 = ffma ssa_76.y, ssa_54, ssa_85
>		vec1 32 ssa_90 = ffma ssa_76.z, ssa_54, ssa_86
>		vec1 32 ssa_91 = ffma ssa_76.w, ssa_54, ssa_87
>		vec1 32 ssa_92 = fadd ssa_88, ssa_79.x
>		vec1 32 ssa_93 = fadd ssa_89, ssa_79.y
>		vec1 32 ssa_94 = fadd ssa_90, ssa_79.z
>		vec1 32 ssa_95 = fadd ssa_91, ssa_79.w
>		vec1 32 ssa_96 = fmul ssa_73.x, ssa_59
>		vec1 32 ssa_97 = fmul ssa_73.y, ssa_59
>		vec1 32 ssa_98 = fmul ssa_73.z, ssa_59
>		vec1 32 ssa_99 = fmul ssa_73.w, ssa_59
>		vec1 32 ssa_100 = ffma ssa_71.x, ssa_57, ssa_96
>		vec1 32 ssa_101 = ffma ssa_71.y, ssa_57, ssa_97
>		vec1 32 ssa_102 = ffma ssa_71.z, ssa_57, ssa_98
>		vec1 32 ssa_103 = ffma ssa_71.w, ssa_57, ssa_99
>		vec1 32 ssa_104 = ffma ssa_76.x, ssa_61, ssa_100
>		vec1 32 ssa_105 = ffma ssa_76.y, ssa_61, ssa_101
>		vec1 32 ssa_106 = ffma ssa_76.z, ssa_61, ssa_102
>		vec1 32 ssa_107 = ffma ssa_76.w, ssa_61, ssa_103
>		vec1 32 ssa_108 = fadd ssa_104, ssa_79.x
>		vec1 32 ssa_109 = fadd ssa_105, ssa_79.y
>		vec1 32 ssa_110 = fadd ssa_106, ssa_79.z
>		vec1 32 ssa_111 = fadd ssa_107, ssa_79.w
>		vec1 32 ssa_112 = fmul ssa_73.x, ssa_66
>		vec1 32 ssa_113 = fmul ssa_73.y, ssa_66
>		vec1 32 ssa_114 = fmul ssa_73.z, ssa_66
>		vec1 32 ssa_115 = fmul ssa_73.w, ssa_66
>		vec1 32 ssa_116 = ffma ssa_71.x, ssa_64, ssa_112
>		vec1 32 ssa_117 = ffma ssa_71.y, ssa_64, ssa_113
>		vec1 32 ssa_118 = ffma ssa_71.z, ssa_64, ssa_114
>		vec1 32 ssa_119 = ffma ssa_71.w, ssa_64, ssa_115
>		vec1 32 ssa_120 = ffma ssa_76.x, ssa_68, ssa_116
>		vec1 32 ssa_121 = ffma ssa_76.y, ssa_68, ssa_117
>		vec1 32 ssa_122 = ffma ssa_76.z, ssa_68, ssa_118
>		vec1 32 ssa_123 = ffma ssa_76.w, ssa_68, ssa_119
>		vec1 32 ssa_124 = fadd ssa_120, ssa_79.x
>		vec1 32 ssa_125 = fadd ssa_121, ssa_79.y
>		vec1 32 ssa_126 = fadd ssa_122, ssa_79.z
>		vec1 32 ssa_127 = fadd ssa_123, ssa_79.w
>		vec1 32 ssa_128 = frcp ssa_95
>		vec1 32 ssa_129 = fmul ssa_92, ssa_128
>		vec1 32 ssa_130 = fmul ssa_93, ssa_128
>		vec1 32 ssa_131 = fmul ssa_94, ssa_128
>		vec1 32 ssa_132 = frcp ssa_111
>		vec1 32 ssa_133 = fmul ssa_108, ssa_132
>		vec1 32 ssa_134 = fmul ssa_109, ssa_132
>		vec1 32 ssa_135 = fmul ssa_110, ssa_132
>		vec1 32 ssa_136 = frcp ssa_127
>		vec1 32 ssa_137 = fmul ssa_124, ssa_136
>		vec1 32 ssa_138 = fmul ssa_125, ssa_136
>		vec1 32 ssa_139 = fmul ssa_126, ssa_136
>		vec1 32 ssa_140 = flt ssa_3, ssa_131
>		/* succs: block_8 block_9 */
>		if ssa_140 {
>			block block_8:
>			/* preds: block_7 */
>			vec1 32 ssa_141 = flt ssa_3, ssa_135
>			/* succs: block_10 */
>		} else {
>			block block_9:
>			/* preds: block_7 */
>			/* succs: block_10 */
>		}
>		block block_10:
>		/* preds: block_8 block_9 */
>		vec1 32 ssa_142 = phi block_8: ssa_141, block_9: ssa_1
>		/* succs: block_11 block_12 */
>		if ssa_142 {
>			block block_11:
>			/* preds: block_10 */
>			vec1 32 ssa_143 = flt ssa_3, ssa_139
>			/* succs: block_13 */
>		} else {
>			block block_12:
>			/* preds: block_10 */
>			/* succs: block_13 */
>		}
>		block block_13:
>		/* preds: block_11 block_12 */
>		vec1 32 ssa_144 = phi block_11: ssa_143, block_12: ssa_1
>		vec1 32 ssa_145 = inot ssa_144
>		/* succs: block_14 block_15 */
>		if ssa_145 {
>			block block_14:
>			/* preds: block_13 */
>			vec1 32 ssa_146 = flt ssa_131, ssa_1
>			/* succs: block_16 */
>		} else {
>			block block_15:
>			/* preds: block_13 */
>			/* succs: block_16 */
>		}
>		block block_16:
>		/* preds: block_14 block_15 */
>		vec1 32 ssa_147 = phi block_14: ssa_146, block_15: ssa_1
>		/* succs: block_17 block_18 */
>		if ssa_147 {
>			block block_17:
>			/* preds: block_16 */
>			vec1 32 ssa_148 = flt ssa_135, ssa_1
>			/* succs: block_19 */
>		} else {
>			block block_18:
>			/* preds: block_16 */
>			/* succs: block_19 */
>		}
>		block block_19:
>		/* preds: block_17 block_18 */
>		vec1 32 ssa_149 = phi block_17: ssa_148, block_18: ssa_1
>		/* succs: block_20 block_21 */
>		if ssa_149 {
>			block block_20:
>			/* preds: block_19 */
>			vec1 32 ssa_150 = flt ssa_139, ssa_1
>			/* succs: block_22 */
>		} else {
>			block block_21:
>			/* preds: block_19 */
>			/* succs: block_22 */
>		}
>		block block_22:
>		/* preds: block_20 block_21 */
>		vec1 32 ssa_151 = phi block_20: ssa_150, block_21: ssa_1
>		vec1 32 ssa_152 = bcsel ssa_151, ssa_2, ssa_144
>		vec1 32 ssa_153 = inot ssa_152
>		/* succs: block_23 block_24 */
>		if ssa_153 {
>			block block_23:
>			/* preds: block_22 */
>			vec1 32 ssa_154 = flt ssa_129, ssa_4
>			/* succs: block_25 */
>		} else {
>			block block_24:
>			/* preds: block_22 */
>			/* succs: block_25 */
>		}
>		block block_25:
>		/* preds: block_23 block_24 */
>		vec1 32 ssa_155 = phi block_23: ssa_154, block_24: ssa_1
>		/* succs: block_26 block_27 */
>		if ssa_155 {
>			block block_26:
>			/* preds: block_25 */
>			vec1 32 ssa_156 = flt ssa_133, ssa_4
>			/* succs: block_28 */
>		} else {
>			block block_27:
>			/* preds: block_25 */
>			/* succs: block_28 */
>		}
>		block block_28:
>		/* preds: block_26 block_27 */
>		vec1 32 ssa_157 = phi block_26: ssa_156, block_27: ssa_1
>		/* succs: block_29 block_30 */
>		if ssa_157 {
>			block block_29:
>			/* preds: block_28 */
>			vec1 32 ssa_158 = flt ssa_137, ssa_4
>			/* succs: block_31 */
>		} else {
>			block block_30:
>			/* preds: block_28 */
>			/* succs: block_31 */
>		}
>		block block_31:
>		/* preds: block_29 block_30 */
>		vec1 32 ssa_159 = phi block_29: ssa_158, block_30: ssa_1
>		vec1 32 ssa_160 = bcsel ssa_159, ssa_2, ssa_152
>		vec1 32 ssa_161 = inot ssa_160
>		/* succs: block_32 block_33 */
>		if ssa_161 {
>			block block_32:
>			/* preds: block_31 */
>			vec1 32 ssa_162 = flt ssa_3, ssa_129
>			/* succs: block_34 */
>		} else {
>			block block_33:
>			/* preds: block_31 */
>			/* succs: block_34 */
>		}
>		block block_34:
>		/* preds: block_32 block_33 */
>		vec1 32 ssa_163 = phi block_32: ssa_162, block_33: ssa_1
>		/* succs: block_35 block_36 */
>		if ssa_163 {
>			block block_35:
>			/* preds: block_34 */
>			vec1 32 ssa_164 = flt ssa_3, ssa_133
>			/* succs: block_37 */
>		} else {
>			block block_36:
>			/* preds: block_34 */
>			/* succs: block_37 */
>		}
>		block block_37:
>		/* preds: block_35 block_36 */
>		vec1 32 ssa_165 = phi block_35: ssa_164, block_36: ssa_1
>		/* succs: block_38 block_39 */
>		if ssa_165 {
>			block block_38:
>			/* preds: block_37 */
>			vec1 32 ssa_166 = flt ssa_3, ssa_137
>			/* succs: block_40 */
>		} else {
>			block block_39:
>			/* preds: block_37 */
>			/* succs: block_40 */
>		}
>		block block_40:
>		/* preds: block_38 block_39 */
>		vec1 32 ssa_167 = phi block_38: ssa_166, block_39: ssa_1
>		vec1 32 ssa_168 = bcsel ssa_167, ssa_2, ssa_160
>		vec1 32 ssa_169 = inot ssa_168
>		/* succs: block_41 block_42 */
>		if ssa_169 {
>			block block_41:
>			/* preds: block_40 */
>			vec1 32 ssa_170 = flt ssa_130, ssa_4
>			/* succs: block_43 */
>		} else {
>			block block_42:
>			/* preds: block_40 */
>			/* succs: block_43 */
>		}
>		block block_43:
>		/* preds: block_41 block_42 */
>		vec1 32 ssa_171 = phi block_41: ssa_170, block_42: ssa_1
>		/* succs: block_44 block_45 */
>		if ssa_171 {
>			block block_44:
>			/* preds: block_43 */
>			vec1 32 ssa_172 = flt ssa_134, ssa_4
>			/* succs: block_46 */
>		} else {
>			block block_45:
>			/* preds: block_43 */
>			/* succs: block_46 */
>		}
>		block block_46:
>		/* preds: block_44 block_45 */
>		vec1 32 ssa_173 = phi block_44: ssa_172, block_45: ssa_1
>		/* succs: block_47 block_48 */
>		if ssa_173 {
>			block block_47:
>			/* preds: block_46 */
>			vec1 32 ssa_174 = flt ssa_138, ssa_4
>			/* succs: block_49 */
>		} else {
>			block block_48:
>			/* preds: block_46 */
>			/* succs: block_49 */
>		}
>		block block_49:
>		/* preds: block_47 block_48 */
>		vec1 32 ssa_175 = phi block_47: ssa_174, block_48: ssa_1
>		vec1 32 ssa_176 = bcsel ssa_175, ssa_2, ssa_168
>		vec1 32 ssa_177 = inot ssa_176
>		/* succs: block_50 block_51 */
>		if ssa_177 {
>			block block_50:
>			/* preds: block_49 */
>			vec1 32 ssa_178 = flt ssa_3, ssa_130
>			/* succs: block_52 */
>		} else {
>			block block_51:
>			/* preds: block_49 */
>			/* succs: block_52 */
>		}
>		block block_52:
>		/* preds: block_50 block_51 */
>		vec1 32 ssa_179 = phi block_50: ssa_178, block_51: ssa_1
>		/* succs: block_53 block_54 */
>		if ssa_179 {
>			block block_53:
>			/* preds: block_52 */
>			vec1 32 ssa_180 = flt ssa_3, ssa_134
>			/* succs: block_55 */
>		} else {
>			block block_54:
>			/* preds: block_52 */
>			/* succs: block_55 */
>		}
>		block block_55:
>		/* preds: block_53 block_54 */
>		vec1 32 ssa_181 = phi block_53: ssa_180, block_54: ssa_1
>		/* succs: block_56 block_57 */
>		if ssa_181 {
>			block block_56:
>			/* preds: block_55 */
>			vec1 32 ssa_182 = flt ssa_3, ssa_138
>			/* succs: block_58 */
>		} else {
>			block block_57:
>			/* preds: block_55 */
>			/* succs: block_58 */
>		}
>		block block_58:
>		/* preds: block_56 block_57 */
>		vec1 32 ssa_183 = phi block_56: ssa_182, block_57: ssa_1
>		vec1 32 ssa_184 = bcsel ssa_183, ssa_2, ssa_176
>		vec1 32 ssa_185 = inot ssa_184
>		/* succs: block_59 block_60 */
>		if ssa_185 {
>			block block_59:
>			/* preds: block_58 */
>			vec1 32 ssa_186 = fmul ssa_109, ssa_127
>			vec1 32 ssa_187 = fmul ssa_111, ssa_124
>			vec1 32 ssa_188 = fmul ssa_108, ssa_125
>			vec1 32 ssa_189 = fmul ssa_111, ssa_125
>			vec1 32 ssa_190 = fmul ssa_108, ssa_127
>			vec1 32 ssa_191 = fmul ssa_109, ssa_124
>			vec1 32 ssa_192 = fmul ssa_92, ssa_189
>			vec1 32 ssa_193 = fmul ssa_93, ssa_190
>			vec1 32 ssa_194 = fmul ssa_95, ssa_191
>			vec1 32 ssa_195 = ffma ssa_92, ssa_186, -ssa_192
>			vec1 32 ssa_196 = ffma ssa_93, ssa_187, -ssa_193
>			vec1 32 ssa_197 = ffma ssa_95, ssa_188, -ssa_194
>			vec1 32 ssa_198 = fadd ssa_196, ssa_197
>			vec1 32 ssa_199 = fadd ssa_195, ssa_198
>			vec1 32 ssa_200 = flt ssa_1, ssa_199
>			/* succs: block_61 */
>		} else {
>			block block_60:
>			/* preds: block_58 */
>			/* succs: block_61 */
>		}
>		block block_61:
>		/* preds: block_59 block_60 */
>		vec1 32 ssa_201 = phi block_59: ssa_200, block_60: ssa_184
>		intrinsic barrier () ()
>		intrinsic group_memory_barrier () ()
>		vec1 32 ssa_202 = inot ssa_201
>		/* succs: block_62 block_63 */
>		if ssa_202 {
>			block block_62:
>			/* preds: block_61 */
>			vec1 32 ssa_203 = intrinsic load_uniform (ssa_41) (0, 20) /* base=0 */ /* range=20 */
>			vec1 32 ssa_204 = load_const (0x00000014 /* 0.000000 */)
>			vec1 32 ssa_205 = imul ssa_203, ssa_204
>			vec1 32 ssa_206 = intrinsic ssbo_atomic_add (ssa_5, ssa_205, ssa_0) ()
>			vec1 32 ssa_207 = imul ssa_206, ssa_38
>			intrinsic store_ssbo (ssa_40, ssa_41, ssa_207) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_208 = iadd ssa_41, ssa_207
>			intrinsic store_ssbo (ssa_43, ssa_41, ssa_208) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_209 = iadd ssa_10, ssa_207
>			intrinsic store_ssbo (ssa_45, ssa_41, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */
>			/* succs: block_64 */
>		} else {
>			block block_63:
>			/* preds: block_61 */
>			/* succs: block_64 */
>		}
>		block block_64:
>		/* preds: block_62 block_63 */
>		/* succs: block_66 */
>	} else {
>		block block_65:
>		/* preds: block_6 */
>		/* succs: block_66 */
>	}
>	block block_66:
>	/* preds: block_64 block_65 */
>	/* succs: block_67 */
>	block block_67:
>}
>
>NIR (final form) for compute shader:
>shader: MESA_SHADER_COMPUTE
>local-size: 64, 1, 1
>shared-size: 1
>inputs: 0
>outputs: 0
>uniforms: 140
>shared: 4
>decl_function main (0 params)
>
>impl main {
>	decl_reg vec1 32 r0
>	decl_reg vec1 32 r1
>	decl_reg vec1 32 r2
>	decl_reg vec1 32 r3
>	decl_reg vec1 32 r4
>	decl_reg vec1 32 r5
>	decl_reg vec1 32 r6
>	decl_reg vec1 32 r7
>	decl_reg vec1 32 r8
>	decl_reg vec1 32 r9
>	decl_reg vec1 32 r10
>	decl_reg vec1 32 r11
>	decl_reg vec1 32 r12
>	decl_reg vec1 32 r13
>	decl_reg vec1 32 r14
>	decl_reg vec1 32 r15
>	decl_reg vec1 32 r16
>	decl_reg vec1 32 r17
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_2 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_3 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_4 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */)
>	vec3 32 ssa_6 = intrinsic load_work_group_id () ()
>	vec3 32 ssa_7 = intrinsic load_uniform (ssa_1) (128, 12) /* base=128 */ /* range=12 */
>	vec1 32 ssa_8 = iadd ssa_6.x, ssa_7.x
>	vec1 32 ssa_9 = intrinsic load_subgroup_id () ()
>	vec1 32 ssa_10 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_11 = ishl ssa_9, ssa_0
>	vec1 32 ssa_12 = intrinsic load_subgroup_invocation () ()
>	vec1 32 ssa_13 = iadd ssa_12, ssa_11
>	vec1 32 ssa_14 = load_const (0x0000003f /* 0.000000 */)
>	vec1 32 ssa_15 = iand ssa_13, ssa_14
>	vec1 32 ssa_16 = load_const (0x00000006 /* 0.000000 */)
>	vec1 32 ssa_17 = ishl ssa_8, ssa_16
>	vec1 32 ssa_18 = iadd ssa_17, ssa_15
>	vec1 32 ssa_19 = ieq ssa_18, ssa_1
>	/* succs: block_1 block_2 */
>	if ssa_19 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_20 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_21 = intrinsic load_uniform (ssa_20) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_22 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_23 = imul ssa_21, ssa_22
>		intrinsic store_ssbo (ssa_1, ssa_5, ssa_23) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_24 = iadd ssa_20, ssa_23
>		intrinsic store_ssbo (ssa_5, ssa_5, ssa_24) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_25 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_26 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_27 = iadd ssa_26, ssa_23
>		intrinsic store_ssbo (ssa_25, ssa_5, ssa_27) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_28 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_29 = intrinsic load_uniform (ssa_28) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_30 = iadd ssa_10, ssa_23
>		intrinsic store_ssbo (ssa_29, ssa_5, ssa_30) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_31 = intrinsic load_uniform (ssa_26) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_32 = iadd ssa_28, ssa_23
>		intrinsic store_ssbo (ssa_31, ssa_5, ssa_32) (1, 0) /* wrmask=x */ /* access=0 */
>		/* succs: block_3 */
>	} else {
>		block block_2:
>		/* preds: block_0 */
>		/* succs: block_3 */
>	}
>	block block_3:
>	/* preds: block_1 block_2 */
>	vec1 32 ssa_33 = ieq ssa_15, ssa_1
>	/* succs: block_4 block_5 */
>	if ssa_33 {
>		block block_4:
>		/* preds: block_3 */
>		intrinsic store_shared (ssa_1, ssa_1) (0, 1) /* base=0 */ /* wrmask=x */
>		/* succs: block_6 */
>	} else {
>		block block_5:
>		/* preds: block_3 */
>		/* succs: block_6 */
>	}
>	block block_6:
>	/* preds: block_4 block_5 */
>	intrinsic memory_barrier_shared () ()
>	vec1 32 ssa_34 = intrinsic load_uniform (ssa_10) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_35 = udiv ssa_34, ssa_0
>	vec1 32 ssa_36 = ult ssa_18, ssa_35
>	/* succs: block_7 block_65 */
>	if ssa_36 {
>		block block_7:
>		/* preds: block_6 */
>		vec1 32 ssa_37 = load_const (0x00000002 /* 0.000000 */)
>		vec1 32 ssa_38 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_39 = imul ssa_18, ssa_38
>		vec1 32 ssa_40 = intrinsic load_ssbo (ssa_37, ssa_39) (16) /* access=16 */
>		vec1 32 ssa_41 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_42 = iadd ssa_41, ssa_39
>		vec1 32 ssa_43 = intrinsic load_ssbo (ssa_37, ssa_42) (16) /* access=16 */
>		vec1 32 ssa_44 = iadd ssa_10, ssa_39
>		vec1 32 ssa_45 = intrinsic load_ssbo (ssa_37, ssa_44) (16) /* access=16 */
>		vec1 32 ssa_46 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_47 = intrinsic load_uniform (ssa_46) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_48 = iadd ssa_47, ssa_40
>		vec1 32 ssa_49 = imul ssa_48, ssa_38
>		vec1 32 ssa_50 = intrinsic load_ssbo (ssa_0, ssa_49) (16) /* access=16 */
>		vec1 32 ssa_51 = iadd ssa_41, ssa_49
>		vec1 32 ssa_52 = intrinsic load_ssbo (ssa_0, ssa_51) (16) /* access=16 */
>		vec1 32 ssa_53 = iadd ssa_10, ssa_49
>		vec1 32 ssa_54 = intrinsic load_ssbo (ssa_0, ssa_53) (16) /* access=16 */
>		vec1 32 ssa_55 = iadd ssa_47, ssa_43
>		vec1 32 ssa_56 = imul ssa_55, ssa_38
>		vec1 32 ssa_57 = intrinsic load_ssbo (ssa_0, ssa_56) (16) /* access=16 */
>		vec1 32 ssa_58 = iadd ssa_41, ssa_56
>		vec1 32 ssa_59 = intrinsic load_ssbo (ssa_0, ssa_58) (16) /* access=16 */
>		vec1 32 ssa_60 = iadd ssa_10, ssa_56
>		vec1 32 ssa_61 = intrinsic load_ssbo (ssa_0, ssa_60) (16) /* access=16 */
>		vec1 32 ssa_62 = iadd ssa_47, ssa_45
>		vec1 32 ssa_63 = imul ssa_62, ssa_38
>		vec1 32 ssa_64 = intrinsic load_ssbo (ssa_0, ssa_63) (16) /* access=16 */
>		vec1 32 ssa_65 = iadd ssa_41, ssa_63
>		vec1 32 ssa_66 = intrinsic load_ssbo (ssa_0, ssa_65) (16) /* access=16 */
>		vec1 32 ssa_67 = iadd ssa_10, ssa_63
>		vec1 32 ssa_68 = intrinsic load_ssbo (ssa_0, ssa_67) (16) /* access=16 */
>		vec1 32 ssa_69 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_70 = ishl ssa_69, ssa_16
>		vec4 32 ssa_71 = intrinsic load_ubo (ssa_1, ssa_70) ()
>		vec1 32 ssa_72 = iadd ssa_46, ssa_70
>		vec4 32 ssa_73 = intrinsic load_ubo (ssa_1, ssa_72) ()
>		vec1 32 ssa_74 = load_const (0x00000020 /* 0.000000 */)
>		vec1 32 ssa_75 = iadd ssa_74, ssa_70
>		vec4 32 ssa_76 = intrinsic load_ubo (ssa_1, ssa_75) ()
>		vec1 32 ssa_77 = load_const (0x00000030 /* 0.000000 */)
>		vec1 32 ssa_78 = iadd ssa_77, ssa_70
>		vec4 32 ssa_79 = intrinsic load_ubo (ssa_1, ssa_78) ()
>		vec1 32 ssa_80 = fmul ssa_73.x, ssa_52
>		vec1 32 ssa_81 = fmul ssa_73.y, ssa_52
>		vec1 32 ssa_82 = fmul ssa_73.z, ssa_52
>		vec1 32 ssa_83 = fmul ssa_73.w, ssa_52
>		vec1 32 ssa_84 = ffma ssa_71.x, ssa_50, ssa_80
>		vec1 32 ssa_85 = ffma ssa_71.y, ssa_50, ssa_81
>		vec1 32 ssa_86 = ffma ssa_71.z, ssa_50, ssa_82
>		vec1 32 ssa_87 = ffma ssa_71.w, ssa_50, ssa_83
>		vec1 32 ssa_88 = ffma ssa_76.x, ssa_54, ssa_84
>		vec1 32 ssa_89 = ffma ssa_76.y, ssa_54, ssa_85
>		vec1 32 ssa_90 = ffma ssa_76.z, ssa_54, ssa_86
>		vec1 32 ssa_91 = ffma ssa_76.w, ssa_54, ssa_87
>		vec1 32 ssa_92 = fadd ssa_88, ssa_79.x
>		vec1 32 ssa_93 = fadd ssa_89, ssa_79.y
>		vec1 32 ssa_94 = fadd ssa_90, ssa_79.z
>		vec1 32 ssa_95 = fadd ssa_91, ssa_79.w
>		vec1 32 ssa_96 = fmul ssa_73.x, ssa_59
>		vec1 32 ssa_97 = fmul ssa_73.y, ssa_59
>		vec1 32 ssa_98 = fmul ssa_73.z, ssa_59
>		vec1 32 ssa_99 = fmul ssa_73.w, ssa_59
>		vec1 32 ssa_100 = ffma ssa_71.x, ssa_57, ssa_96
>		vec1 32 ssa_101 = ffma ssa_71.y, ssa_57, ssa_97
>		vec1 32 ssa_102 = ffma ssa_71.z, ssa_57, ssa_98
>		vec1 32 ssa_103 = ffma ssa_71.w, ssa_57, ssa_99
>		vec1 32 ssa_104 = ffma ssa_76.x, ssa_61, ssa_100
>		vec1 32 ssa_105 = ffma ssa_76.y, ssa_61, ssa_101
>		vec1 32 ssa_106 = ffma ssa_76.z, ssa_61, ssa_102
>		vec1 32 ssa_107 = ffma ssa_76.w, ssa_61, ssa_103
>		vec1 32 ssa_108 = fadd ssa_104, ssa_79.x
>		vec1 32 ssa_109 = fadd ssa_105, ssa_79.y
>		vec1 32 ssa_110 = fadd ssa_106, ssa_79.z
>		vec1 32 ssa_111 = fadd ssa_107, ssa_79.w
>		vec1 32 ssa_112 = fmul ssa_73.x, ssa_66
>		vec1 32 ssa_113 = fmul ssa_73.y, ssa_66
>		vec1 32 ssa_114 = fmul ssa_73.z, ssa_66
>		vec1 32 ssa_115 = fmul ssa_73.w, ssa_66
>		vec1 32 ssa_116 = ffma ssa_71.x, ssa_64, ssa_112
>		vec1 32 ssa_117 = ffma ssa_71.y, ssa_64, ssa_113
>		vec1 32 ssa_118 = ffma ssa_71.z, ssa_64, ssa_114
>		vec1 32 ssa_119 = ffma ssa_71.w, ssa_64, ssa_115
>		vec1 32 ssa_120 = ffma ssa_76.x, ssa_68, ssa_116
>		vec1 32 ssa_121 = ffma ssa_76.y, ssa_68, ssa_117
>		vec1 32 ssa_122 = ffma ssa_76.z, ssa_68, ssa_118
>		vec1 32 ssa_123 = ffma ssa_76.w, ssa_68, ssa_119
>		vec1 32 ssa_124 = fadd ssa_120, ssa_79.x
>		vec1 32 ssa_125 = fadd ssa_121, ssa_79.y
>		vec1 32 ssa_126 = fadd ssa_122, ssa_79.z
>		vec1 32 ssa_127 = fadd ssa_123, ssa_79.w
>		vec1 32 ssa_128 = frcp ssa_95
>		vec1 32 ssa_129 = fmul ssa_92, ssa_128
>		vec1 32 ssa_130 = fmul ssa_93, ssa_128
>		vec1 32 ssa_131 = fmul ssa_94, ssa_128
>		vec1 32 ssa_132 = frcp ssa_111
>		vec1 32 ssa_133 = fmul ssa_108, ssa_132
>		vec1 32 ssa_134 = fmul ssa_109, ssa_132
>		vec1 32 ssa_135 = fmul ssa_110, ssa_132
>		vec1 32 ssa_136 = frcp ssa_127
>		vec1 32 ssa_137 = fmul ssa_124, ssa_136
>		vec1 32 ssa_138 = fmul ssa_125, ssa_136
>		vec1 32 ssa_139 = fmul ssa_126, ssa_136
>		vec1 32 ssa_140 = flt ssa_3, ssa_131
>		/* succs: block_8 block_9 */
>		if ssa_140 {
>			block block_8:
>			/* preds: block_7 */
>			r0 = flt ssa_3, ssa_135
>			/* succs: block_10 */
>		} else {
>			block block_9:
>			/* preds: block_7 */
>			r0 = imov ssa_1
>			/* succs: block_10 */
>		}
>		block block_10:
>		/* preds: block_8 block_9 */
>		/* succs: block_11 block_12 */
>		if r0 {
>			block block_11:
>			/* preds: block_10 */
>			r1 = flt ssa_3, ssa_139
>			/* succs: block_13 */
>		} else {
>			block block_12:
>			/* preds: block_10 */
>			r1 = imov ssa_1
>			/* succs: block_13 */
>		}
>		block block_13:
>		/* preds: block_11 block_12 */
>		vec1 32 ssa_145 = inot r1
>		/* succs: block_14 block_15 */
>		if ssa_145 {
>			block block_14:
>			/* preds: block_13 */
>			r2 = flt ssa_131, ssa_1
>			/* succs: block_16 */
>		} else {
>			block block_15:
>			/* preds: block_13 */
>			r2 = imov ssa_1
>			/* succs: block_16 */
>		}
>		block block_16:
>		/* preds: block_14 block_15 */
>		/* succs: block_17 block_18 */
>		if r2 {
>			block block_17:
>			/* preds: block_16 */
>			r3 = flt ssa_135, ssa_1
>			/* succs: block_19 */
>		} else {
>			block block_18:
>			/* preds: block_16 */
>			r3 = imov ssa_1
>			/* succs: block_19 */
>		}
>		block block_19:
>		/* preds: block_17 block_18 */
>		/* succs: block_20 block_21 */
>		if r3 {
>			block block_20:
>			/* preds: block_19 */
>			r4 = flt ssa_139, ssa_1
>			/* succs: block_22 */
>		} else {
>			block block_21:
>			/* preds: block_19 */
>			r4 = imov ssa_1
>			/* succs: block_22 */
>		}
>		block block_22:
>		/* preds: block_20 block_21 */
>		vec1 32 ssa_152 = bcsel r4, ssa_2, r1
>		vec1 32 ssa_153 = inot ssa_152
>		/* succs: block_23 block_24 */
>		if ssa_153 {
>			block block_23:
>			/* preds: block_22 */
>			r5 = flt ssa_129, ssa_4
>			/* succs: block_25 */
>		} else {
>			block block_24:
>			/* preds: block_22 */
>			r5 = imov ssa_1
>			/* succs: block_25 */
>		}
>		block block_25:
>		/* preds: block_23 block_24 */
>		/* succs: block_26 block_27 */
>		if r5 {
>			block block_26:
>			/* preds: block_25 */
>			r6 = flt ssa_133, ssa_4
>			/* succs: block_28 */
>		} else {
>			block block_27:
>			/* preds: block_25 */
>			r6 = imov ssa_1
>			/* succs: block_28 */
>		}
>		block block_28:
>		/* preds: block_26 block_27 */
>		/* succs: block_29 block_30 */
>		if r6 {
>			block block_29:
>			/* preds: block_28 */
>			r7 = flt ssa_137, ssa_4
>			/* succs: block_31 */
>		} else {
>			block block_30:
>			/* preds: block_28 */
>			r7 = imov ssa_1
>			/* succs: block_31 */
>		}
>		block block_31:
>		/* preds: block_29 block_30 */
>		vec1 32 ssa_160 = bcsel r7, ssa_2, ssa_152
>		vec1 32 ssa_161 = inot ssa_160
>		/* succs: block_32 block_33 */
>		if ssa_161 {
>			block block_32:
>			/* preds: block_31 */
>			r8 = flt ssa_3, ssa_129
>			/* succs: block_34 */
>		} else {
>			block block_33:
>			/* preds: block_31 */
>			r8 = imov ssa_1
>			/* succs: block_34 */
>		}
>		block block_34:
>		/* preds: block_32 block_33 */
>		/* succs: block_35 block_36 */
>		if r8 {
>			block block_35:
>			/* preds: block_34 */
>			r9 = flt ssa_3, ssa_133
>			/* succs: block_37 */
>		} else {
>			block block_36:
>			/* preds: block_34 */
>			r9 = imov ssa_1
>			/* succs: block_37 */
>		}
>		block block_37:
>		/* preds: block_35 block_36 */
>		/* succs: block_38 block_39 */
>		if r9 {
>			block block_38:
>			/* preds: block_37 */
>			r10 = flt ssa_3, ssa_137
>			/* succs: block_40 */
>		} else {
>			block block_39:
>			/* preds: block_37 */
>			r10 = imov ssa_1
>			/* succs: block_40 */
>		}
>		block block_40:
>		/* preds: block_38 block_39 */
>		vec1 32 ssa_168 = bcsel r10, ssa_2, ssa_160
>		vec1 32 ssa_169 = inot ssa_168
>		/* succs: block_41 block_42 */
>		if ssa_169 {
>			block block_41:
>			/* preds: block_40 */
>			r11 = flt ssa_130, ssa_4
>			/* succs: block_43 */
>		} else {
>			block block_42:
>			/* preds: block_40 */
>			r11 = imov ssa_1
>			/* succs: block_43 */
>		}
>		block block_43:
>		/* preds: block_41 block_42 */
>		/* succs: block_44 block_45 */
>		if r11 {
>			block block_44:
>			/* preds: block_43 */
>			r12 = flt ssa_134, ssa_4
>			/* succs: block_46 */
>		} else {
>			block block_45:
>			/* preds: block_43 */
>			r12 = imov ssa_1
>			/* succs: block_46 */
>		}
>		block block_46:
>		/* preds: block_44 block_45 */
>		/* succs: block_47 block_48 */
>		if r12 {
>			block block_47:
>			/* preds: block_46 */
>			r13 = flt ssa_138, ssa_4
>			/* succs: block_49 */
>		} else {
>			block block_48:
>			/* preds: block_46 */
>			r13 = imov ssa_1
>			/* succs: block_49 */
>		}
>		block block_49:
>		/* preds: block_47 block_48 */
>		vec1 32 ssa_176 = bcsel r13, ssa_2, ssa_168
>		vec1 32 ssa_177 = inot ssa_176
>		/* succs: block_50 block_51 */
>		if ssa_177 {
>			block block_50:
>			/* preds: block_49 */
>			r14 = flt ssa_3, ssa_130
>			/* succs: block_52 */
>		} else {
>			block block_51:
>			/* preds: block_49 */
>			r14 = imov ssa_1
>			/* succs: block_52 */
>		}
>		block block_52:
>		/* preds: block_50 block_51 */
>		/* succs: block_53 block_54 */
>		if r14 {
>			block block_53:
>			/* preds: block_52 */
>			r15 = flt ssa_3, ssa_134
>			/* succs: block_55 */
>		} else {
>			block block_54:
>			/* preds: block_52 */
>			r15 = imov ssa_1
>			/* succs: block_55 */
>		}
>		block block_55:
>		/* preds: block_53 block_54 */
>		/* succs: block_56 block_57 */
>		if r15 {
>			block block_56:
>			/* preds: block_55 */
>			r16 = flt ssa_3, ssa_138
>			/* succs: block_58 */
>		} else {
>			block block_57:
>			/* preds: block_55 */
>			r16 = imov ssa_1
>			/* succs: block_58 */
>		}
>		block block_58:
>		/* preds: block_56 block_57 */
>		r17 = bcsel r16, ssa_2, ssa_176
>		vec1 32 ssa_185 = inot r17
>		/* succs: block_59 block_60 */
>		if ssa_185 {
>			block block_59:
>			/* preds: block_58 */
>			vec1 32 ssa_186 = fmul ssa_109, ssa_127
>			vec1 32 ssa_187 = fmul ssa_111, ssa_124
>			vec1 32 ssa_188 = fmul ssa_108, ssa_125
>			vec1 32 ssa_189 = fmul ssa_111, ssa_125
>			vec1 32 ssa_190 = fmul ssa_108, ssa_127
>			vec1 32 ssa_191 = fmul ssa_109, ssa_124
>			vec1 32 ssa_192 = fmul ssa_92, ssa_189
>			vec1 32 ssa_193 = fmul ssa_93, ssa_190
>			vec1 32 ssa_194 = fmul ssa_95, ssa_191
>			vec1 32 ssa_195 = ffma ssa_92, ssa_186, -ssa_192
>			vec1 32 ssa_196 = ffma ssa_93, ssa_187, -ssa_193
>			vec1 32 ssa_197 = ffma ssa_95, ssa_188, -ssa_194
>			vec1 32 ssa_198 = fadd ssa_196, ssa_197
>			vec1 32 ssa_199 = fadd ssa_195, ssa_198
>			r17 = flt ssa_1, ssa_199
>			/* succs: block_61 */
>		} else {
>			block block_60:
>			/* preds: block_58 */
>			/* succs: block_61 */
>		}
>		block block_61:
>		/* preds: block_59 block_60 */
>		intrinsic barrier () ()
>		intrinsic group_memory_barrier () ()
>		vec1 32 ssa_202 = inot r17
>		/* succs: block_62 block_63 */
>		if ssa_202 {
>			block block_62:
>			/* preds: block_61 */
>			vec1 32 ssa_203 = intrinsic load_uniform (ssa_41) (0, 20) /* base=0 */ /* range=20 */
>			vec1 32 ssa_204 = load_const (0x00000014 /* 0.000000 */)
>			vec1 32 ssa_205 = imul ssa_203, ssa_204
>			vec1 32 ssa_206 = intrinsic ssbo_atomic_add (ssa_5, ssa_205, ssa_0) ()
>			vec1 32 ssa_207 = imul ssa_206, ssa_38
>			intrinsic store_ssbo (ssa_40, ssa_41, ssa_207) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_208 = iadd ssa_41, ssa_207
>			intrinsic store_ssbo (ssa_43, ssa_41, ssa_208) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_209 = iadd ssa_10, ssa_207
>			intrinsic store_ssbo (ssa_45, ssa_41, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */
>			/* succs: block_64 */
>		} else {
>			block block_63:
>			/* preds: block_61 */
>			/* succs: block_64 */
>		}
>		block block_64:
>		/* preds: block_62 block_63 */
>		/* succs: block_66 */
>	} else {
>		block block_65:
>		/* preds: block_6 */
>		/* succs: block_66 */
>	}
>	block block_66:
>	/* preds: block_64 block_65 */
>	/* succs: block_67 */
>	block block_67:
>}
>
>NIR (SSA form) for compute shader:
>shader: MESA_SHADER_COMPUTE
>local-size: 64, 1, 1
>shared-size: 1
>inputs: 0
>outputs: 0
>uniforms: 140
>shared: 4
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_2 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_3 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_4 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */)
>	vec3 32 ssa_6 = intrinsic load_work_group_id () ()
>	vec3 32 ssa_7 = intrinsic load_uniform (ssa_1) (128, 12) /* base=128 */ /* range=12 */
>	vec1 32 ssa_8 = iadd ssa_6.x, ssa_7.x
>	vec1 32 ssa_9 = intrinsic load_subgroup_id () ()
>	vec1 32 ssa_10 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */)
>	vec1 32 ssa_12 = ishl ssa_9, ssa_11
>	vec1 32 ssa_13 = intrinsic load_subgroup_invocation () ()
>	vec1 32 ssa_14 = iadd ssa_13, ssa_12
>	vec1 32 ssa_15 = load_const (0x0000003f /* 0.000000 */)
>	vec1 32 ssa_16 = iand ssa_14, ssa_15
>	vec1 32 ssa_17 = load_const (0x00000006 /* 0.000000 */)
>	vec1 32 ssa_18 = ishl ssa_8, ssa_17
>	vec1 32 ssa_19 = iadd ssa_18, ssa_16
>	vec1 32 ssa_20 = ieq ssa_19, ssa_1
>	/* succs: block_1 block_2 */
>	if ssa_20 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_21 = intrinsic load_uniform (ssa_11) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_22 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_23 = imul ssa_21, ssa_22
>		intrinsic store_ssbo (ssa_1, ssa_5, ssa_23) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_24 = iadd ssa_11, ssa_23
>		intrinsic store_ssbo (ssa_5, ssa_5, ssa_24) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_25 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_26 = iadd ssa_10, ssa_23
>		intrinsic store_ssbo (ssa_25, ssa_5, ssa_26) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_27 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_28 = intrinsic load_uniform (ssa_27) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_29 = load_const (0x00000008 /* 0.000000 */)
>		vec1 32 ssa_30 = iadd ssa_29, ssa_23
>		intrinsic store_ssbo (ssa_28, ssa_5, ssa_30) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_31 = intrinsic load_uniform (ssa_10) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_32 = iadd ssa_27, ssa_23
>		intrinsic store_ssbo (ssa_31, ssa_5, ssa_32) (1, 0) /* wrmask=x */ /* access=0 */
>		/* succs: block_3 */
>	} else {
>		block block_2:
>		/* preds: block_0 */
>		/* succs: block_3 */
>	}
>	block block_3:
>	/* preds: block_1 block_2 */
>	vec1 32 ssa_33 = ieq ssa_16, ssa_1
>	/* succs: block_4 block_5 */
>	if ssa_33 {
>		block block_4:
>		/* preds: block_3 */
>		intrinsic store_shared (ssa_1, ssa_1) (0, 1) /* base=0 */ /* wrmask=x */
>		/* succs: block_6 */
>	} else {
>		block block_5:
>		/* preds: block_3 */
>		/* succs: block_6 */
>	}
>	block block_6:
>	/* preds: block_4 block_5 */
>	intrinsic memory_barrier_shared () ()
>	vec1 32 ssa_34 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_35 = intrinsic load_uniform (ssa_34) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_36 = udiv ssa_35, ssa_0
>	vec1 32 ssa_37 = ult ssa_19, ssa_36
>	/* succs: block_7 block_65 */
>	if ssa_37 {
>		block block_7:
>		/* preds: block_6 */
>		vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */)
>		vec1 32 ssa_39 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_40 = imul ssa_19, ssa_39
>		vec1 32 ssa_41 = intrinsic load_ssbo (ssa_38, ssa_40) (16) /* access=16 */
>		vec1 32 ssa_42 = iadd ssa_11, ssa_40
>		vec1 32 ssa_43 = intrinsic load_ssbo (ssa_38, ssa_42) (16) /* access=16 */
>		vec1 32 ssa_44 = iadd ssa_34, ssa_40
>		vec1 32 ssa_45 = intrinsic load_ssbo (ssa_38, ssa_44) (16) /* access=16 */
>		vec1 32 ssa_46 = intrinsic load_uniform (ssa_10) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_47 = iadd ssa_46, ssa_41
>		vec1 32 ssa_48 = imul ssa_47, ssa_39
>		vec1 32 ssa_49 = intrinsic load_ssbo (ssa_0, ssa_48) (16) /* access=16 */
>		vec1 32 ssa_50 = iadd ssa_11, ssa_48
>		vec1 32 ssa_51 = intrinsic load_ssbo (ssa_0, ssa_50) (16) /* access=16 */
>		vec1 32 ssa_52 = iadd ssa_34, ssa_48
>		vec1 32 ssa_53 = intrinsic load_ssbo (ssa_0, ssa_52) (16) /* access=16 */
>		vec1 32 ssa_54 = iadd ssa_46, ssa_43
>		vec1 32 ssa_55 = imul ssa_54, ssa_39
>		vec1 32 ssa_56 = intrinsic load_ssbo (ssa_0, ssa_55) (16) /* access=16 */
>		vec1 32 ssa_57 = iadd ssa_11, ssa_55
>		vec1 32 ssa_58 = intrinsic load_ssbo (ssa_0, ssa_57) (16) /* access=16 */
>		vec1 32 ssa_59 = iadd ssa_34, ssa_55
>		vec1 32 ssa_60 = intrinsic load_ssbo (ssa_0, ssa_59) (16) /* access=16 */
>		vec1 32 ssa_61 = iadd ssa_46, ssa_45
>		vec1 32 ssa_62 = imul ssa_61, ssa_39
>		vec1 32 ssa_63 = intrinsic load_ssbo (ssa_0, ssa_62) (16) /* access=16 */
>		vec1 32 ssa_64 = iadd ssa_11, ssa_62
>		vec1 32 ssa_65 = intrinsic load_ssbo (ssa_0, ssa_64) (16) /* access=16 */
>		vec1 32 ssa_66 = iadd ssa_34, ssa_62
>		vec1 32 ssa_67 = intrinsic load_ssbo (ssa_0, ssa_66) (16) /* access=16 */
>		vec1 32 ssa_68 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_69 = ishl ssa_68, ssa_17
>		vec4 32 ssa_70 = intrinsic load_ubo (ssa_1, ssa_69) ()
>		vec1 32 ssa_71 = iadd ssa_10, ssa_69
>		vec4 32 ssa_72 = intrinsic load_ubo (ssa_1, ssa_71) ()
>		vec1 32 ssa_73 = load_const (0x00000020 /* 0.000000 */)
>		vec1 32 ssa_74 = iadd ssa_73, ssa_69
>		vec4 32 ssa_75 = intrinsic load_ubo (ssa_1, ssa_74) ()
>		vec1 32 ssa_76 = load_const (0x00000030 /* 0.000000 */)
>		vec1 32 ssa_77 = iadd ssa_76, ssa_69
>		vec4 32 ssa_78 = intrinsic load_ubo (ssa_1, ssa_77) ()
>		vec1 32 ssa_79 = fmul ssa_72.x, ssa_51
>		vec1 32 ssa_80 = fmul ssa_72.y, ssa_51
>		vec1 32 ssa_81 = fmul ssa_72.z, ssa_51
>		vec1 32 ssa_82 = fmul ssa_72.w, ssa_51
>		vec1 32 ssa_83 = ffma ssa_70.x, ssa_49, ssa_79
>		vec1 32 ssa_84 = ffma ssa_70.y, ssa_49, ssa_80
>		vec1 32 ssa_85 = ffma ssa_70.z, ssa_49, ssa_81
>		vec1 32 ssa_86 = ffma ssa_70.w, ssa_49, ssa_82
>		vec1 32 ssa_87 = ffma ssa_75.x, ssa_53, ssa_83
>		vec1 32 ssa_88 = ffma ssa_75.y, ssa_53, ssa_84
>		vec1 32 ssa_89 = ffma ssa_75.z, ssa_53, ssa_85
>		vec1 32 ssa_90 = ffma ssa_75.w, ssa_53, ssa_86
>		vec1 32 ssa_91 = fadd ssa_87, ssa_78.x
>		vec1 32 ssa_92 = fadd ssa_88, ssa_78.y
>		vec1 32 ssa_93 = fadd ssa_89, ssa_78.z
>		vec1 32 ssa_94 = fadd ssa_90, ssa_78.w
>		vec1 32 ssa_95 = fmul ssa_72.x, ssa_58
>		vec1 32 ssa_96 = fmul ssa_72.y, ssa_58
>		vec1 32 ssa_97 = fmul ssa_72.z, ssa_58
>		vec1 32 ssa_98 = fmul ssa_72.w, ssa_58
>		vec1 32 ssa_99 = ffma ssa_70.x, ssa_56, ssa_95
>		vec1 32 ssa_100 = ffma ssa_70.y, ssa_56, ssa_96
>		vec1 32 ssa_101 = ffma ssa_70.z, ssa_56, ssa_97
>		vec1 32 ssa_102 = ffma ssa_70.w, ssa_56, ssa_98
>		vec1 32 ssa_103 = ffma ssa_75.x, ssa_60, ssa_99
>		vec1 32 ssa_104 = ffma ssa_75.y, ssa_60, ssa_100
>		vec1 32 ssa_105 = ffma ssa_75.z, ssa_60, ssa_101
>		vec1 32 ssa_106 = ffma ssa_75.w, ssa_60, ssa_102
>		vec1 32 ssa_107 = fadd ssa_103, ssa_78.x
>		vec1 32 ssa_108 = fadd ssa_104, ssa_78.y
>		vec1 32 ssa_109 = fadd ssa_105, ssa_78.z
>		vec1 32 ssa_110 = fadd ssa_106, ssa_78.w
>		vec1 32 ssa_111 = fmul ssa_72.x, ssa_65
>		vec1 32 ssa_112 = fmul ssa_72.y, ssa_65
>		vec1 32 ssa_113 = fmul ssa_72.z, ssa_65
>		vec1 32 ssa_114 = fmul ssa_72.w, ssa_65
>		vec1 32 ssa_115 = ffma ssa_70.x, ssa_63, ssa_111
>		vec1 32 ssa_116 = ffma ssa_70.y, ssa_63, ssa_112
>		vec1 32 ssa_117 = ffma ssa_70.z, ssa_63, ssa_113
>		vec1 32 ssa_118 = ffma ssa_70.w, ssa_63, ssa_114
>		vec1 32 ssa_119 = ffma ssa_75.x, ssa_67, ssa_115
>		vec1 32 ssa_120 = ffma ssa_75.y, ssa_67, ssa_116
>		vec1 32 ssa_121 = ffma ssa_75.z, ssa_67, ssa_117
>		vec1 32 ssa_122 = ffma ssa_75.w, ssa_67, ssa_118
>		vec1 32 ssa_123 = fadd ssa_119, ssa_78.x
>		vec1 32 ssa_124 = fadd ssa_120, ssa_78.y
>		vec1 32 ssa_125 = fadd ssa_121, ssa_78.z
>		vec1 32 ssa_126 = fadd ssa_122, ssa_78.w
>		vec1 32 ssa_127 = frcp ssa_94
>		vec1 32 ssa_128 = fmul ssa_91, ssa_127
>		vec1 32 ssa_129 = fmul ssa_92, ssa_127
>		vec1 32 ssa_130 = fmul ssa_93, ssa_127
>		vec1 32 ssa_131 = frcp ssa_110
>		vec1 32 ssa_132 = fmul ssa_107, ssa_131
>		vec1 32 ssa_133 = fmul ssa_108, ssa_131
>		vec1 32 ssa_134 = fmul ssa_109, ssa_131
>		vec1 32 ssa_135 = frcp ssa_126
>		vec1 32 ssa_136 = fmul ssa_123, ssa_135
>		vec1 32 ssa_137 = fmul ssa_124, ssa_135
>		vec1 32 ssa_138 = fmul ssa_125, ssa_135
>		vec1 32 ssa_139 = flt ssa_3, ssa_130
>		/* succs: block_8 block_9 */
>		if ssa_139 {
>			block block_8:
>			/* preds: block_7 */
>			vec1 32 ssa_140 = flt ssa_3, ssa_134
>			/* succs: block_10 */
>		} else {
>			block block_9:
>			/* preds: block_7 */
>			/* succs: block_10 */
>		}
>		block block_10:
>		/* preds: block_8 block_9 */
>		vec1 32 ssa_141 = phi block_8: ssa_140, block_9: ssa_1
>		/* succs: block_11 block_12 */
>		if ssa_141 {
>			block block_11:
>			/* preds: block_10 */
>			vec1 32 ssa_142 = flt ssa_3, ssa_138
>			/* succs: block_13 */
>		} else {
>			block block_12:
>			/* preds: block_10 */
>			/* succs: block_13 */
>		}
>		block block_13:
>		/* preds: block_11 block_12 */
>		vec1 32 ssa_143 = phi block_11: ssa_142, block_12: ssa_1
>		vec1 32 ssa_144 = inot ssa_143
>		/* succs: block_14 block_15 */
>		if ssa_144 {
>			block block_14:
>			/* preds: block_13 */
>			vec1 32 ssa_145 = flt ssa_130, ssa_1
>			/* succs: block_16 */
>		} else {
>			block block_15:
>			/* preds: block_13 */
>			/* succs: block_16 */
>		}
>		block block_16:
>		/* preds: block_14 block_15 */
>		vec1 32 ssa_146 = phi block_14: ssa_145, block_15: ssa_1
>		/* succs: block_17 block_18 */
>		if ssa_146 {
>			block block_17:
>			/* preds: block_16 */
>			vec1 32 ssa_147 = flt ssa_134, ssa_1
>			/* succs: block_19 */
>		} else {
>			block block_18:
>			/* preds: block_16 */
>			/* succs: block_19 */
>		}
>		block block_19:
>		/* preds: block_17 block_18 */
>		vec1 32 ssa_148 = phi block_17: ssa_147, block_18: ssa_1
>		/* succs: block_20 block_21 */
>		if ssa_148 {
>			block block_20:
>			/* preds: block_19 */
>			vec1 32 ssa_149 = flt ssa_138, ssa_1
>			/* succs: block_22 */
>		} else {
>			block block_21:
>			/* preds: block_19 */
>			/* succs: block_22 */
>		}
>		block block_22:
>		/* preds: block_20 block_21 */
>		vec1 32 ssa_150 = phi block_20: ssa_149, block_21: ssa_1
>		vec1 32 ssa_151 = bcsel ssa_150, ssa_2, ssa_143
>		vec1 32 ssa_152 = inot ssa_151
>		/* succs: block_23 block_24 */
>		if ssa_152 {
>			block block_23:
>			/* preds: block_22 */
>			vec1 32 ssa_153 = flt ssa_128, ssa_4
>			/* succs: block_25 */
>		} else {
>			block block_24:
>			/* preds: block_22 */
>			/* succs: block_25 */
>		}
>		block block_25:
>		/* preds: block_23 block_24 */
>		vec1 32 ssa_154 = phi block_23: ssa_153, block_24: ssa_1
>		/* succs: block_26 block_27 */
>		if ssa_154 {
>			block block_26:
>			/* preds: block_25 */
>			vec1 32 ssa_155 = flt ssa_132, ssa_4
>			/* succs: block_28 */
>		} else {
>			block block_27:
>			/* preds: block_25 */
>			/* succs: block_28 */
>		}
>		block block_28:
>		/* preds: block_26 block_27 */
>		vec1 32 ssa_156 = phi block_26: ssa_155, block_27: ssa_1
>		/* succs: block_29 block_30 */
>		if ssa_156 {
>			block block_29:
>			/* preds: block_28 */
>			vec1 32 ssa_157 = flt ssa_136, ssa_4
>			/* succs: block_31 */
>		} else {
>			block block_30:
>			/* preds: block_28 */
>			/* succs: block_31 */
>		}
>		block block_31:
>		/* preds: block_29 block_30 */
>		vec1 32 ssa_158 = phi block_29: ssa_157, block_30: ssa_1
>		vec1 32 ssa_159 = bcsel ssa_158, ssa_2, ssa_151
>		vec1 32 ssa_160 = inot ssa_159
>		/* succs: block_32 block_33 */
>		if ssa_160 {
>			block block_32:
>			/* preds: block_31 */
>			vec1 32 ssa_161 = flt ssa_3, ssa_128
>			/* succs: block_34 */
>		} else {
>			block block_33:
>			/* preds: block_31 */
>			/* succs: block_34 */
>		}
>		block block_34:
>		/* preds: block_32 block_33 */
>		vec1 32 ssa_162 = phi block_32: ssa_161, block_33: ssa_1
>		/* succs: block_35 block_36 */
>		if ssa_162 {
>			block block_35:
>			/* preds: block_34 */
>			vec1 32 ssa_163 = flt ssa_3, ssa_132
>			/* succs: block_37 */
>		} else {
>			block block_36:
>			/* preds: block_34 */
>			/* succs: block_37 */
>		}
>		block block_37:
>		/* preds: block_35 block_36 */
>		vec1 32 ssa_164 = phi block_35: ssa_163, block_36: ssa_1
>		/* succs: block_38 block_39 */
>		if ssa_164 {
>			block block_38:
>			/* preds: block_37 */
>			vec1 32 ssa_165 = flt ssa_3, ssa_136
>			/* succs: block_40 */
>		} else {
>			block block_39:
>			/* preds: block_37 */
>			/* succs: block_40 */
>		}
>		block block_40:
>		/* preds: block_38 block_39 */
>		vec1 32 ssa_166 = phi block_38: ssa_165, block_39: ssa_1
>		vec1 32 ssa_167 = bcsel ssa_166, ssa_2, ssa_159
>		vec1 32 ssa_168 = inot ssa_167
>		/* succs: block_41 block_42 */
>		if ssa_168 {
>			block block_41:
>			/* preds: block_40 */
>			vec1 32 ssa_169 = flt ssa_129, ssa_4
>			/* succs: block_43 */
>		} else {
>			block block_42:
>			/* preds: block_40 */
>			/* succs: block_43 */
>		}
>		block block_43:
>		/* preds: block_41 block_42 */
>		vec1 32 ssa_170 = phi block_41: ssa_169, block_42: ssa_1
>		/* succs: block_44 block_45 */
>		if ssa_170 {
>			block block_44:
>			/* preds: block_43 */
>			vec1 32 ssa_171 = flt ssa_133, ssa_4
>			/* succs: block_46 */
>		} else {
>			block block_45:
>			/* preds: block_43 */
>			/* succs: block_46 */
>		}
>		block block_46:
>		/* preds: block_44 block_45 */
>		vec1 32 ssa_172 = phi block_44: ssa_171, block_45: ssa_1
>		/* succs: block_47 block_48 */
>		if ssa_172 {
>			block block_47:
>			/* preds: block_46 */
>			vec1 32 ssa_173 = flt ssa_137, ssa_4
>			/* succs: block_49 */
>		} else {
>			block block_48:
>			/* preds: block_46 */
>			/* succs: block_49 */
>		}
>		block block_49:
>		/* preds: block_47 block_48 */
>		vec1 32 ssa_174 = phi block_47: ssa_173, block_48: ssa_1
>		vec1 32 ssa_175 = bcsel ssa_174, ssa_2, ssa_167
>		vec1 32 ssa_176 = inot ssa_175
>		/* succs: block_50 block_51 */
>		if ssa_176 {
>			block block_50:
>			/* preds: block_49 */
>			vec1 32 ssa_177 = flt ssa_3, ssa_129
>			/* succs: block_52 */
>		} else {
>			block block_51:
>			/* preds: block_49 */
>			/* succs: block_52 */
>		}
>		block block_52:
>		/* preds: block_50 block_51 */
>		vec1 32 ssa_178 = phi block_50: ssa_177, block_51: ssa_1
>		/* succs: block_53 block_54 */
>		if ssa_178 {
>			block block_53:
>			/* preds: block_52 */
>			vec1 32 ssa_179 = flt ssa_3, ssa_133
>			/* succs: block_55 */
>		} else {
>			block block_54:
>			/* preds: block_52 */
>			/* succs: block_55 */
>		}
>		block block_55:
>		/* preds: block_53 block_54 */
>		vec1 32 ssa_180 = phi block_53: ssa_179, block_54: ssa_1
>		/* succs: block_56 block_57 */
>		if ssa_180 {
>			block block_56:
>			/* preds: block_55 */
>			vec1 32 ssa_181 = flt ssa_3, ssa_137
>			/* succs: block_58 */
>		} else {
>			block block_57:
>			/* preds: block_55 */
>			/* succs: block_58 */
>		}
>		block block_58:
>		/* preds: block_56 block_57 */
>		vec1 32 ssa_182 = phi block_56: ssa_181, block_57: ssa_1
>		vec1 32 ssa_183 = bcsel ssa_182, ssa_2, ssa_175
>		vec1 32 ssa_184 = inot ssa_183
>		/* succs: block_59 block_60 */
>		if ssa_184 {
>			block block_59:
>			/* preds: block_58 */
>			vec1 32 ssa_185 = fmul ssa_108, ssa_126
>			vec1 32 ssa_186 = fmul ssa_110, ssa_123
>			vec1 32 ssa_187 = fmul ssa_107, ssa_124
>			vec1 32 ssa_188 = fmul ssa_110, ssa_124
>			vec1 32 ssa_189 = fmul ssa_107, ssa_126
>			vec1 32 ssa_190 = fmul ssa_108, ssa_123
>			vec1 32 ssa_191 = fmul ssa_91, ssa_188
>			vec1 32 ssa_192 = fmul ssa_92, ssa_189
>			vec1 32 ssa_193 = fmul ssa_94, ssa_190
>			vec1 32 ssa_194 = ffma ssa_91, ssa_185, -ssa_191
>			vec1 32 ssa_195 = ffma ssa_92, ssa_186, -ssa_192
>			vec1 32 ssa_196 = ffma ssa_94, ssa_187, -ssa_193
>			vec1 32 ssa_197 = fadd ssa_195, ssa_196
>			vec1 32 ssa_198 = fadd ssa_194, ssa_197
>			vec1 32 ssa_199 = flt ssa_1, ssa_198
>			/* succs: block_61 */
>		} else {
>			block block_60:
>			/* preds: block_58 */
>			/* succs: block_61 */
>		}
>		block block_61:
>		/* preds: block_59 block_60 */
>		vec1 32 ssa_200 = phi block_59: ssa_199, block_60: ssa_183
>		intrinsic barrier () ()
>		intrinsic group_memory_barrier () ()
>		vec1 32 ssa_201 = inot ssa_200
>		/* succs: block_62 block_63 */
>		if ssa_201 {
>			block block_62:
>			/* preds: block_61 */
>			vec1 32 ssa_202 = intrinsic load_uniform (ssa_11) (0, 20) /* base=0 */ /* range=20 */
>			vec1 32 ssa_203 = load_const (0x00000014 /* 0.000000 */)
>			vec1 32 ssa_204 = imul ssa_202, ssa_203
>			vec1 32 ssa_205 = intrinsic ssbo_atomic_add (ssa_5, ssa_204, ssa_0) ()
>			vec1 32 ssa_206 = imul ssa_205, ssa_39
>			intrinsic store_ssbo (ssa_41, ssa_11, ssa_206) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_207 = iadd ssa_11, ssa_206
>			intrinsic store_ssbo (ssa_43, ssa_11, ssa_207) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_208 = iadd ssa_34, ssa_206
>			intrinsic store_ssbo (ssa_45, ssa_11, ssa_208) (1, 0) /* wrmask=x */ /* access=0 */
>			/* succs: block_64 */
>		} else {
>			block block_63:
>			/* preds: block_61 */
>			/* succs: block_64 */
>		}
>		block block_64:
>		/* preds: block_62 block_63 */
>		/* succs: block_66 */
>	} else {
>		block block_65:
>		/* preds: block_6 */
>		/* succs: block_66 */
>	}
>	block block_66:
>	/* preds: block_64 block_65 */
>	/* succs: block_67 */
>	block block_67:
>}
>
>NIR (final form) for compute shader:
>shader: MESA_SHADER_COMPUTE
>local-size: 64, 1, 1
>shared-size: 1
>inputs: 0
>outputs: 0
>uniforms: 140
>shared: 4
>decl_function main (0 params)
>
>impl main {
>	decl_reg vec1 32 r0
>	decl_reg vec1 32 r1
>	decl_reg vec1 32 r2
>	decl_reg vec1 32 r3
>	decl_reg vec1 32 r4
>	decl_reg vec1 32 r5
>	decl_reg vec1 32 r6
>	decl_reg vec1 32 r7
>	decl_reg vec1 32 r8
>	decl_reg vec1 32 r9
>	decl_reg vec1 32 r10
>	decl_reg vec1 32 r11
>	decl_reg vec1 32 r12
>	decl_reg vec1 32 r13
>	decl_reg vec1 32 r14
>	decl_reg vec1 32 r15
>	decl_reg vec1 32 r16
>	decl_reg vec1 32 r17
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_2 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_3 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_4 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */)
>	vec3 32 ssa_6 = intrinsic load_work_group_id () ()
>	vec3 32 ssa_7 = intrinsic load_uniform (ssa_1) (128, 12) /* base=128 */ /* range=12 */
>	vec1 32 ssa_8 = iadd ssa_6.x, ssa_7.x
>	vec1 32 ssa_9 = intrinsic load_subgroup_id () ()
>	vec1 32 ssa_10 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */)
>	vec1 32 ssa_12 = ishl ssa_9, ssa_11
>	vec1 32 ssa_13 = intrinsic load_subgroup_invocation () ()
>	vec1 32 ssa_14 = iadd ssa_13, ssa_12
>	vec1 32 ssa_15 = load_const (0x0000003f /* 0.000000 */)
>	vec1 32 ssa_16 = iand ssa_14, ssa_15
>	vec1 32 ssa_17 = load_const (0x00000006 /* 0.000000 */)
>	vec1 32 ssa_18 = ishl ssa_8, ssa_17
>	vec1 32 ssa_19 = iadd ssa_18, ssa_16
>	vec1 32 ssa_20 = ieq ssa_19, ssa_1
>	/* succs: block_1 block_2 */
>	if ssa_20 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_21 = intrinsic load_uniform (ssa_11) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_22 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_23 = imul ssa_21, ssa_22
>		intrinsic store_ssbo (ssa_1, ssa_5, ssa_23) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_24 = iadd ssa_11, ssa_23
>		intrinsic store_ssbo (ssa_5, ssa_5, ssa_24) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_25 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_26 = iadd ssa_10, ssa_23
>		intrinsic store_ssbo (ssa_25, ssa_5, ssa_26) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_27 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_28 = intrinsic load_uniform (ssa_27) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_29 = load_const (0x00000008 /* 0.000000 */)
>		vec1 32 ssa_30 = iadd ssa_29, ssa_23
>		intrinsic store_ssbo (ssa_28, ssa_5, ssa_30) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_31 = intrinsic load_uniform (ssa_10) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_32 = iadd ssa_27, ssa_23
>		intrinsic store_ssbo (ssa_31, ssa_5, ssa_32) (1, 0) /* wrmask=x */ /* access=0 */
>		/* succs: block_3 */
>	} else {
>		block block_2:
>		/* preds: block_0 */
>		/* succs: block_3 */
>	}
>	block block_3:
>	/* preds: block_1 block_2 */
>	vec1 32 ssa_33 = ieq ssa_16, ssa_1
>	/* succs: block_4 block_5 */
>	if ssa_33 {
>		block block_4:
>		/* preds: block_3 */
>		intrinsic store_shared (ssa_1, ssa_1) (0, 1) /* base=0 */ /* wrmask=x */
>		/* succs: block_6 */
>	} else {
>		block block_5:
>		/* preds: block_3 */
>		/* succs: block_6 */
>	}
>	block block_6:
>	/* preds: block_4 block_5 */
>	intrinsic memory_barrier_shared () ()
>	vec1 32 ssa_34 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_35 = intrinsic load_uniform (ssa_34) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_36 = udiv ssa_35, ssa_0
>	vec1 32 ssa_37 = ult ssa_19, ssa_36
>	/* succs: block_7 block_65 */
>	if ssa_37 {
>		block block_7:
>		/* preds: block_6 */
>		vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */)
>		vec1 32 ssa_39 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_40 = imul ssa_19, ssa_39
>		vec1 32 ssa_41 = intrinsic load_ssbo (ssa_38, ssa_40) (16) /* access=16 */
>		vec1 32 ssa_42 = iadd ssa_11, ssa_40
>		vec1 32 ssa_43 = intrinsic load_ssbo (ssa_38, ssa_42) (16) /* access=16 */
>		vec1 32 ssa_44 = iadd ssa_34, ssa_40
>		vec1 32 ssa_45 = intrinsic load_ssbo (ssa_38, ssa_44) (16) /* access=16 */
>		vec1 32 ssa_46 = intrinsic load_uniform (ssa_10) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_47 = iadd ssa_46, ssa_41
>		vec1 32 ssa_48 = imul ssa_47, ssa_39
>		vec1 32 ssa_49 = intrinsic load_ssbo (ssa_0, ssa_48) (16) /* access=16 */
>		vec1 32 ssa_50 = iadd ssa_11, ssa_48
>		vec1 32 ssa_51 = intrinsic load_ssbo (ssa_0, ssa_50) (16) /* access=16 */
>		vec1 32 ssa_52 = iadd ssa_34, ssa_48
>		vec1 32 ssa_53 = intrinsic load_ssbo (ssa_0, ssa_52) (16) /* access=16 */
>		vec1 32 ssa_54 = iadd ssa_46, ssa_43
>		vec1 32 ssa_55 = imul ssa_54, ssa_39
>		vec1 32 ssa_56 = intrinsic load_ssbo (ssa_0, ssa_55) (16) /* access=16 */
>		vec1 32 ssa_57 = iadd ssa_11, ssa_55
>		vec1 32 ssa_58 = intrinsic load_ssbo (ssa_0, ssa_57) (16) /* access=16 */
>		vec1 32 ssa_59 = iadd ssa_34, ssa_55
>		vec1 32 ssa_60 = intrinsic load_ssbo (ssa_0, ssa_59) (16) /* access=16 */
>		vec1 32 ssa_61 = iadd ssa_46, ssa_45
>		vec1 32 ssa_62 = imul ssa_61, ssa_39
>		vec1 32 ssa_63 = intrinsic load_ssbo (ssa_0, ssa_62) (16) /* access=16 */
>		vec1 32 ssa_64 = iadd ssa_11, ssa_62
>		vec1 32 ssa_65 = intrinsic load_ssbo (ssa_0, ssa_64) (16) /* access=16 */
>		vec1 32 ssa_66 = iadd ssa_34, ssa_62
>		vec1 32 ssa_67 = intrinsic load_ssbo (ssa_0, ssa_66) (16) /* access=16 */
>		vec1 32 ssa_68 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_69 = ishl ssa_68, ssa_17
>		vec4 32 ssa_70 = intrinsic load_ubo (ssa_1, ssa_69) ()
>		vec1 32 ssa_71 = iadd ssa_10, ssa_69
>		vec4 32 ssa_72 = intrinsic load_ubo (ssa_1, ssa_71) ()
>		vec1 32 ssa_73 = load_const (0x00000020 /* 0.000000 */)
>		vec1 32 ssa_74 = iadd ssa_73, ssa_69
>		vec4 32 ssa_75 = intrinsic load_ubo (ssa_1, ssa_74) ()
>		vec1 32 ssa_76 = load_const (0x00000030 /* 0.000000 */)
>		vec1 32 ssa_77 = iadd ssa_76, ssa_69
>		vec4 32 ssa_78 = intrinsic load_ubo (ssa_1, ssa_77) ()
>		vec1 32 ssa_79 = fmul ssa_72.x, ssa_51
>		vec1 32 ssa_80 = fmul ssa_72.y, ssa_51
>		vec1 32 ssa_81 = fmul ssa_72.z, ssa_51
>		vec1 32 ssa_82 = fmul ssa_72.w, ssa_51
>		vec1 32 ssa_83 = ffma ssa_70.x, ssa_49, ssa_79
>		vec1 32 ssa_84 = ffma ssa_70.y, ssa_49, ssa_80
>		vec1 32 ssa_85 = ffma ssa_70.z, ssa_49, ssa_81
>		vec1 32 ssa_86 = ffma ssa_70.w, ssa_49, ssa_82
>		vec1 32 ssa_87 = ffma ssa_75.x, ssa_53, ssa_83
>		vec1 32 ssa_88 = ffma ssa_75.y, ssa_53, ssa_84
>		vec1 32 ssa_89 = ffma ssa_75.z, ssa_53, ssa_85
>		vec1 32 ssa_90 = ffma ssa_75.w, ssa_53, ssa_86
>		vec1 32 ssa_91 = fadd ssa_87, ssa_78.x
>		vec1 32 ssa_92 = fadd ssa_88, ssa_78.y
>		vec1 32 ssa_93 = fadd ssa_89, ssa_78.z
>		vec1 32 ssa_94 = fadd ssa_90, ssa_78.w
>		vec1 32 ssa_95 = fmul ssa_72.x, ssa_58
>		vec1 32 ssa_96 = fmul ssa_72.y, ssa_58
>		vec1 32 ssa_97 = fmul ssa_72.z, ssa_58
>		vec1 32 ssa_98 = fmul ssa_72.w, ssa_58
>		vec1 32 ssa_99 = ffma ssa_70.x, ssa_56, ssa_95
>		vec1 32 ssa_100 = ffma ssa_70.y, ssa_56, ssa_96
>		vec1 32 ssa_101 = ffma ssa_70.z, ssa_56, ssa_97
>		vec1 32 ssa_102 = ffma ssa_70.w, ssa_56, ssa_98
>		vec1 32 ssa_103 = ffma ssa_75.x, ssa_60, ssa_99
>		vec1 32 ssa_104 = ffma ssa_75.y, ssa_60, ssa_100
>		vec1 32 ssa_105 = ffma ssa_75.z, ssa_60, ssa_101
>		vec1 32 ssa_106 = ffma ssa_75.w, ssa_60, ssa_102
>		vec1 32 ssa_107 = fadd ssa_103, ssa_78.x
>		vec1 32 ssa_108 = fadd ssa_104, ssa_78.y
>		vec1 32 ssa_109 = fadd ssa_105, ssa_78.z
>		vec1 32 ssa_110 = fadd ssa_106, ssa_78.w
>		vec1 32 ssa_111 = fmul ssa_72.x, ssa_65
>		vec1 32 ssa_112 = fmul ssa_72.y, ssa_65
>		vec1 32 ssa_113 = fmul ssa_72.z, ssa_65
>		vec1 32 ssa_114 = fmul ssa_72.w, ssa_65
>		vec1 32 ssa_115 = ffma ssa_70.x, ssa_63, ssa_111
>		vec1 32 ssa_116 = ffma ssa_70.y, ssa_63, ssa_112
>		vec1 32 ssa_117 = ffma ssa_70.z, ssa_63, ssa_113
>		vec1 32 ssa_118 = ffma ssa_70.w, ssa_63, ssa_114
>		vec1 32 ssa_119 = ffma ssa_75.x, ssa_67, ssa_115
>		vec1 32 ssa_120 = ffma ssa_75.y, ssa_67, ssa_116
>		vec1 32 ssa_121 = ffma ssa_75.z, ssa_67, ssa_117
>		vec1 32 ssa_122 = ffma ssa_75.w, ssa_67, ssa_118
>		vec1 32 ssa_123 = fadd ssa_119, ssa_78.x
>		vec1 32 ssa_124 = fadd ssa_120, ssa_78.y
>		vec1 32 ssa_125 = fadd ssa_121, ssa_78.z
>		vec1 32 ssa_126 = fadd ssa_122, ssa_78.w
>		vec1 32 ssa_127 = frcp ssa_94
>		vec1 32 ssa_128 = fmul ssa_91, ssa_127
>		vec1 32 ssa_129 = fmul ssa_92, ssa_127
>		vec1 32 ssa_130 = fmul ssa_93, ssa_127
>		vec1 32 ssa_131 = frcp ssa_110
>		vec1 32 ssa_132 = fmul ssa_107, ssa_131
>		vec1 32 ssa_133 = fmul ssa_108, ssa_131
>		vec1 32 ssa_134 = fmul ssa_109, ssa_131
>		vec1 32 ssa_135 = frcp ssa_126
>		vec1 32 ssa_136 = fmul ssa_123, ssa_135
>		vec1 32 ssa_137 = fmul ssa_124, ssa_135
>		vec1 32 ssa_138 = fmul ssa_125, ssa_135
>		vec1 32 ssa_139 = flt ssa_3, ssa_130
>		/* succs: block_8 block_9 */
>		if ssa_139 {
>			block block_8:
>			/* preds: block_7 */
>			r0 = flt ssa_3, ssa_134
>			/* succs: block_10 */
>		} else {
>			block block_9:
>			/* preds: block_7 */
>			r0 = imov ssa_1
>			/* succs: block_10 */
>		}
>		block block_10:
>		/* preds: block_8 block_9 */
>		/* succs: block_11 block_12 */
>		if r0 {
>			block block_11:
>			/* preds: block_10 */
>			r1 = flt ssa_3, ssa_138
>			/* succs: block_13 */
>		} else {
>			block block_12:
>			/* preds: block_10 */
>			r1 = imov ssa_1
>			/* succs: block_13 */
>		}
>		block block_13:
>		/* preds: block_11 block_12 */
>		vec1 32 ssa_144 = inot r1
>		/* succs: block_14 block_15 */
>		if ssa_144 {
>			block block_14:
>			/* preds: block_13 */
>			r2 = flt ssa_130, ssa_1
>			/* succs: block_16 */
>		} else {
>			block block_15:
>			/* preds: block_13 */
>			r2 = imov ssa_1
>			/* succs: block_16 */
>		}
>		block block_16:
>		/* preds: block_14 block_15 */
>		/* succs: block_17 block_18 */
>		if r2 {
>			block block_17:
>			/* preds: block_16 */
>			r3 = flt ssa_134, ssa_1
>			/* succs: block_19 */
>		} else {
>			block block_18:
>			/* preds: block_16 */
>			r3 = imov ssa_1
>			/* succs: block_19 */
>		}
>		block block_19:
>		/* preds: block_17 block_18 */
>		/* succs: block_20 block_21 */
>		if r3 {
>			block block_20:
>			/* preds: block_19 */
>			r4 = flt ssa_138, ssa_1
>			/* succs: block_22 */
>		} else {
>			block block_21:
>			/* preds: block_19 */
>			r4 = imov ssa_1
>			/* succs: block_22 */
>		}
>		block block_22:
>		/* preds: block_20 block_21 */
>		vec1 32 ssa_151 = bcsel r4, ssa_2, r1
>		vec1 32 ssa_152 = inot ssa_151
>		/* succs: block_23 block_24 */
>		if ssa_152 {
>			block block_23:
>			/* preds: block_22 */
>			r5 = flt ssa_128, ssa_4
>			/* succs: block_25 */
>		} else {
>			block block_24:
>			/* preds: block_22 */
>			r5 = imov ssa_1
>			/* succs: block_25 */
>		}
>		block block_25:
>		/* preds: block_23 block_24 */
>		/* succs: block_26 block_27 */
>		if r5 {
>			block block_26:
>			/* preds: block_25 */
>			r6 = flt ssa_132, ssa_4
>			/* succs: block_28 */
>		} else {
>			block block_27:
>			/* preds: block_25 */
>			r6 = imov ssa_1
>			/* succs: block_28 */
>		}
>		block block_28:
>		/* preds: block_26 block_27 */
>		/* succs: block_29 block_30 */
>		if r6 {
>			block block_29:
>			/* preds: block_28 */
>			r7 = flt ssa_136, ssa_4
>			/* succs: block_31 */
>		} else {
>			block block_30:
>			/* preds: block_28 */
>			r7 = imov ssa_1
>			/* succs: block_31 */
>		}
>		block block_31:
>		/* preds: block_29 block_30 */
>		vec1 32 ssa_159 = bcsel r7, ssa_2, ssa_151
>		vec1 32 ssa_160 = inot ssa_159
>		/* succs: block_32 block_33 */
>		if ssa_160 {
>			block block_32:
>			/* preds: block_31 */
>			r8 = flt ssa_3, ssa_128
>			/* succs: block_34 */
>		} else {
>			block block_33:
>			/* preds: block_31 */
>			r8 = imov ssa_1
>			/* succs: block_34 */
>		}
>		block block_34:
>		/* preds: block_32 block_33 */
>		/* succs: block_35 block_36 */
>		if r8 {
>			block block_35:
>			/* preds: block_34 */
>			r9 = flt ssa_3, ssa_132
>			/* succs: block_37 */
>		} else {
>			block block_36:
>			/* preds: block_34 */
>			r9 = imov ssa_1
>			/* succs: block_37 */
>		}
>		block block_37:
>		/* preds: block_35 block_36 */
>		/* succs: block_38 block_39 */
>		if r9 {
>			block block_38:
>			/* preds: block_37 */
>			r10 = flt ssa_3, ssa_136
>			/* succs: block_40 */
>		} else {
>			block block_39:
>			/* preds: block_37 */
>			r10 = imov ssa_1
>			/* succs: block_40 */
>		}
>		block block_40:
>		/* preds: block_38 block_39 */
>		vec1 32 ssa_167 = bcsel r10, ssa_2, ssa_159
>		vec1 32 ssa_168 = inot ssa_167
>		/* succs: block_41 block_42 */
>		if ssa_168 {
>			block block_41:
>			/* preds: block_40 */
>			r11 = flt ssa_129, ssa_4
>			/* succs: block_43 */
>		} else {
>			block block_42:
>			/* preds: block_40 */
>			r11 = imov ssa_1
>			/* succs: block_43 */
>		}
>		block block_43:
>		/* preds: block_41 block_42 */
>		/* succs: block_44 block_45 */
>		if r11 {
>			block block_44:
>			/* preds: block_43 */
>			r12 = flt ssa_133, ssa_4
>			/* succs: block_46 */
>		} else {
>			block block_45:
>			/* preds: block_43 */
>			r12 = imov ssa_1
>			/* succs: block_46 */
>		}
>		block block_46:
>		/* preds: block_44 block_45 */
>		/* succs: block_47 block_48 */
>		if r12 {
>			block block_47:
>			/* preds: block_46 */
>			r13 = flt ssa_137, ssa_4
>			/* succs: block_49 */
>		} else {
>			block block_48:
>			/* preds: block_46 */
>			r13 = imov ssa_1
>			/* succs: block_49 */
>		}
>		block block_49:
>		/* preds: block_47 block_48 */
>		vec1 32 ssa_175 = bcsel r13, ssa_2, ssa_167
>		vec1 32 ssa_176 = inot ssa_175
>		/* succs: block_50 block_51 */
>		if ssa_176 {
>			block block_50:
>			/* preds: block_49 */
>			r14 = flt ssa_3, ssa_129
>			/* succs: block_52 */
>		} else {
>			block block_51:
>			/* preds: block_49 */
>			r14 = imov ssa_1
>			/* succs: block_52 */
>		}
>		block block_52:
>		/* preds: block_50 block_51 */
>		/* succs: block_53 block_54 */
>		if r14 {
>			block block_53:
>			/* preds: block_52 */
>			r15 = flt ssa_3, ssa_133
>			/* succs: block_55 */
>		} else {
>			block block_54:
>			/* preds: block_52 */
>			r15 = imov ssa_1
>			/* succs: block_55 */
>		}
>		block block_55:
>		/* preds: block_53 block_54 */
>		/* succs: block_56 block_57 */
>		if r15 {
>			block block_56:
>			/* preds: block_55 */
>			r16 = flt ssa_3, ssa_137
>			/* succs: block_58 */
>		} else {
>			block block_57:
>			/* preds: block_55 */
>			r16 = imov ssa_1
>			/* succs: block_58 */
>		}
>		block block_58:
>		/* preds: block_56 block_57 */
>		r17 = bcsel r16, ssa_2, ssa_175
>		vec1 32 ssa_184 = inot r17
>		/* succs: block_59 block_60 */
>		if ssa_184 {
>			block block_59:
>			/* preds: block_58 */
>			vec1 32 ssa_185 = fmul ssa_108, ssa_126
>			vec1 32 ssa_186 = fmul ssa_110, ssa_123
>			vec1 32 ssa_187 = fmul ssa_107, ssa_124
>			vec1 32 ssa_188 = fmul ssa_110, ssa_124
>			vec1 32 ssa_189 = fmul ssa_107, ssa_126
>			vec1 32 ssa_190 = fmul ssa_108, ssa_123
>			vec1 32 ssa_191 = fmul ssa_91, ssa_188
>			vec1 32 ssa_192 = fmul ssa_92, ssa_189
>			vec1 32 ssa_193 = fmul ssa_94, ssa_190
>			vec1 32 ssa_194 = ffma ssa_91, ssa_185, -ssa_191
>			vec1 32 ssa_195 = ffma ssa_92, ssa_186, -ssa_192
>			vec1 32 ssa_196 = ffma ssa_94, ssa_187, -ssa_193
>			vec1 32 ssa_197 = fadd ssa_195, ssa_196
>			vec1 32 ssa_198 = fadd ssa_194, ssa_197
>			r17 = flt ssa_1, ssa_198
>			/* succs: block_61 */
>		} else {
>			block block_60:
>			/* preds: block_58 */
>			/* succs: block_61 */
>		}
>		block block_61:
>		/* preds: block_59 block_60 */
>		intrinsic barrier () ()
>		intrinsic group_memory_barrier () ()
>		vec1 32 ssa_201 = inot r17
>		/* succs: block_62 block_63 */
>		if ssa_201 {
>			block block_62:
>			/* preds: block_61 */
>			vec1 32 ssa_202 = intrinsic load_uniform (ssa_11) (0, 20) /* base=0 */ /* range=20 */
>			vec1 32 ssa_203 = load_const (0x00000014 /* 0.000000 */)
>			vec1 32 ssa_204 = imul ssa_202, ssa_203
>			vec1 32 ssa_205 = intrinsic ssbo_atomic_add (ssa_5, ssa_204, ssa_0) ()
>			vec1 32 ssa_206 = imul ssa_205, ssa_39
>			intrinsic store_ssbo (ssa_41, ssa_11, ssa_206) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_207 = iadd ssa_11, ssa_206
>			intrinsic store_ssbo (ssa_43, ssa_11, ssa_207) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_208 = iadd ssa_34, ssa_206
>			intrinsic store_ssbo (ssa_45, ssa_11, ssa_208) (1, 0) /* wrmask=x */ /* access=0 */
>			/* succs: block_64 */
>		} else {
>			block block_63:
>			/* preds: block_61 */
>			/* succs: block_64 */
>		}
>		block block_64:
>		/* preds: block_62 block_63 */
>		/* succs: block_66 */
>	} else {
>		block block_65:
>		/* preds: block_6 */
>		/* succs: block_66 */
>	}
>	block block_66:
>	/* preds: block_64 block_65 */
>	/* succs: block_67 */
>	block block_67:
>}
>
>NIR (SSA form) for compute shader:
>shader: MESA_SHADER_COMPUTE
>local-size: 64, 1, 1
>shared-size: 1
>inputs: 0
>outputs: 0
>uniforms: 140
>shared: 4
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_2 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_3 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_4 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */)
>	vec3 32 ssa_6 = intrinsic load_work_group_id () ()
>	vec3 32 ssa_7 = intrinsic load_uniform (ssa_1) (128, 12) /* base=128 */ /* range=12 */
>	vec1 32 ssa_8 = iadd ssa_6.x, ssa_7.x
>	vec1 32 ssa_9 = intrinsic load_subgroup_id () ()
>	vec1 32 ssa_10 = load_const (0x00000020 /* 0.000000 */)
>	vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */)
>	vec1 32 ssa_12 = ishl ssa_9, ssa_11
>	vec1 32 ssa_13 = intrinsic load_subgroup_invocation () ()
>	vec1 32 ssa_14 = iadd ssa_13, ssa_12
>	vec1 32 ssa_15 = load_const (0x0000003f /* 0.000000 */)
>	vec1 32 ssa_16 = iand ssa_14, ssa_15
>	vec1 32 ssa_17 = load_const (0x00000006 /* 0.000000 */)
>	vec1 32 ssa_18 = ishl ssa_8, ssa_17
>	vec1 32 ssa_19 = iadd ssa_18, ssa_16
>	vec1 32 ssa_20 = ieq ssa_19, ssa_1
>	/* succs: block_1 block_2 */
>	if ssa_20 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_21 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_22 = intrinsic load_uniform (ssa_21) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_23 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_24 = imul ssa_22, ssa_23
>		intrinsic store_ssbo (ssa_1, ssa_5, ssa_24) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_25 = iadd ssa_21, ssa_24
>		intrinsic store_ssbo (ssa_5, ssa_5, ssa_25) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_26 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_27 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_28 = iadd ssa_27, ssa_24
>		intrinsic store_ssbo (ssa_26, ssa_5, ssa_28) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_29 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_30 = intrinsic load_uniform (ssa_29) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_31 = load_const (0x00000008 /* 0.000000 */)
>		vec1 32 ssa_32 = iadd ssa_31, ssa_24
>		intrinsic store_ssbo (ssa_30, ssa_5, ssa_32) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_33 = intrinsic load_uniform (ssa_27) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_34 = iadd ssa_29, ssa_24
>		intrinsic store_ssbo (ssa_33, ssa_5, ssa_34) (1, 0) /* wrmask=x */ /* access=0 */
>		/* succs: block_3 */
>	} else {
>		block block_2:
>		/* preds: block_0 */
>		/* succs: block_3 */
>	}
>	block block_3:
>	/* preds: block_1 block_2 */
>	vec1 32 ssa_35 = ieq ssa_16, ssa_1
>	/* succs: block_4 block_5 */
>	if ssa_35 {
>		block block_4:
>		/* preds: block_3 */
>		intrinsic store_shared (ssa_1, ssa_1) (0, 1) /* base=0 */ /* wrmask=x */
>		/* succs: block_6 */
>	} else {
>		block block_5:
>		/* preds: block_3 */
>		/* succs: block_6 */
>	}
>	block block_6:
>	/* preds: block_4 block_5 */
>	intrinsic memory_barrier_shared () ()
>	vec1 32 ssa_36 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_37 = intrinsic load_uniform (ssa_36) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_38 = udiv ssa_37, ssa_0
>	vec1 32 ssa_39 = ult ssa_19, ssa_38
>	/* succs: block_7 block_65 */
>	if ssa_39 {
>		block block_7:
>		/* preds: block_6 */
>		vec1 32 ssa_40 = load_const (0x00000002 /* 0.000000 */)
>		vec1 32 ssa_41 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_42 = imul ssa_19, ssa_41
>		vec1 32 ssa_43 = intrinsic load_ssbo (ssa_40, ssa_42) (16) /* access=16 */
>		vec1 32 ssa_44 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_45 = iadd ssa_44, ssa_42
>		vec1 32 ssa_46 = intrinsic load_ssbo (ssa_40, ssa_45) (16) /* access=16 */
>		vec1 32 ssa_47 = iadd ssa_36, ssa_42
>		vec1 32 ssa_48 = intrinsic load_ssbo (ssa_40, ssa_47) (16) /* access=16 */
>		vec1 32 ssa_49 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_50 = intrinsic load_uniform (ssa_49) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_51 = iadd ssa_50, ssa_43
>		vec1 32 ssa_52 = imul ssa_51, ssa_41
>		vec1 32 ssa_53 = intrinsic load_ssbo (ssa_0, ssa_52) (16) /* access=16 */
>		vec1 32 ssa_54 = iadd ssa_44, ssa_52
>		vec1 32 ssa_55 = intrinsic load_ssbo (ssa_0, ssa_54) (16) /* access=16 */
>		vec1 32 ssa_56 = iadd ssa_36, ssa_52
>		vec1 32 ssa_57 = intrinsic load_ssbo (ssa_0, ssa_56) (16) /* access=16 */
>		vec1 32 ssa_58 = iadd ssa_50, ssa_46
>		vec1 32 ssa_59 = imul ssa_58, ssa_41
>		vec1 32 ssa_60 = intrinsic load_ssbo (ssa_0, ssa_59) (16) /* access=16 */
>		vec1 32 ssa_61 = iadd ssa_44, ssa_59
>		vec1 32 ssa_62 = intrinsic load_ssbo (ssa_0, ssa_61) (16) /* access=16 */
>		vec1 32 ssa_63 = iadd ssa_36, ssa_59
>		vec1 32 ssa_64 = intrinsic load_ssbo (ssa_0, ssa_63) (16) /* access=16 */
>		vec1 32 ssa_65 = iadd ssa_50, ssa_48
>		vec1 32 ssa_66 = imul ssa_65, ssa_41
>		vec1 32 ssa_67 = intrinsic load_ssbo (ssa_0, ssa_66) (16) /* access=16 */
>		vec1 32 ssa_68 = iadd ssa_44, ssa_66
>		vec1 32 ssa_69 = intrinsic load_ssbo (ssa_0, ssa_68) (16) /* access=16 */
>		vec1 32 ssa_70 = iadd ssa_36, ssa_66
>		vec1 32 ssa_71 = intrinsic load_ssbo (ssa_0, ssa_70) (16) /* access=16 */
>		vec1 32 ssa_72 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_73 = ishl ssa_72, ssa_17
>		vec4 32 ssa_74 = intrinsic load_ubo (ssa_1, ssa_73) ()
>		vec1 32 ssa_75 = iadd ssa_49, ssa_73
>		vec4 32 ssa_76 = intrinsic load_ubo (ssa_1, ssa_75) ()
>		vec1 32 ssa_77 = iadd ssa_10, ssa_73
>		vec4 32 ssa_78 = intrinsic load_ubo (ssa_1, ssa_77) ()
>		vec1 32 ssa_79 = load_const (0x00000030 /* 0.000000 */)
>		vec1 32 ssa_80 = iadd ssa_79, ssa_73
>		vec4 32 ssa_81 = intrinsic load_ubo (ssa_1, ssa_80) ()
>		vec1 32 ssa_82 = fmul ssa_76.x, ssa_55
>		vec1 32 ssa_83 = fmul ssa_76.y, ssa_55
>		vec1 32 ssa_84 = fmul ssa_76.z, ssa_55
>		vec1 32 ssa_85 = fmul ssa_76.w, ssa_55
>		vec1 32 ssa_86 = ffma ssa_74.x, ssa_53, ssa_82
>		vec1 32 ssa_87 = ffma ssa_74.y, ssa_53, ssa_83
>		vec1 32 ssa_88 = ffma ssa_74.z, ssa_53, ssa_84
>		vec1 32 ssa_89 = ffma ssa_74.w, ssa_53, ssa_85
>		vec1 32 ssa_90 = ffma ssa_78.x, ssa_57, ssa_86
>		vec1 32 ssa_91 = ffma ssa_78.y, ssa_57, ssa_87
>		vec1 32 ssa_92 = ffma ssa_78.z, ssa_57, ssa_88
>		vec1 32 ssa_93 = ffma ssa_78.w, ssa_57, ssa_89
>		vec1 32 ssa_94 = fadd ssa_90, ssa_81.x
>		vec1 32 ssa_95 = fadd ssa_91, ssa_81.y
>		vec1 32 ssa_96 = fadd ssa_92, ssa_81.z
>		vec1 32 ssa_97 = fadd ssa_93, ssa_81.w
>		vec1 32 ssa_98 = fmul ssa_76.x, ssa_62
>		vec1 32 ssa_99 = fmul ssa_76.y, ssa_62
>		vec1 32 ssa_100 = fmul ssa_76.z, ssa_62
>		vec1 32 ssa_101 = fmul ssa_76.w, ssa_62
>		vec1 32 ssa_102 = ffma ssa_74.x, ssa_60, ssa_98
>		vec1 32 ssa_103 = ffma ssa_74.y, ssa_60, ssa_99
>		vec1 32 ssa_104 = ffma ssa_74.z, ssa_60, ssa_100
>		vec1 32 ssa_105 = ffma ssa_74.w, ssa_60, ssa_101
>		vec1 32 ssa_106 = ffma ssa_78.x, ssa_64, ssa_102
>		vec1 32 ssa_107 = ffma ssa_78.y, ssa_64, ssa_103
>		vec1 32 ssa_108 = ffma ssa_78.z, ssa_64, ssa_104
>		vec1 32 ssa_109 = ffma ssa_78.w, ssa_64, ssa_105
>		vec1 32 ssa_110 = fadd ssa_106, ssa_81.x
>		vec1 32 ssa_111 = fadd ssa_107, ssa_81.y
>		vec1 32 ssa_112 = fadd ssa_108, ssa_81.z
>		vec1 32 ssa_113 = fadd ssa_109, ssa_81.w
>		vec1 32 ssa_114 = fmul ssa_76.x, ssa_69
>		vec1 32 ssa_115 = fmul ssa_76.y, ssa_69
>		vec1 32 ssa_116 = fmul ssa_76.z, ssa_69
>		vec1 32 ssa_117 = fmul ssa_76.w, ssa_69
>		vec1 32 ssa_118 = ffma ssa_74.x, ssa_67, ssa_114
>		vec1 32 ssa_119 = ffma ssa_74.y, ssa_67, ssa_115
>		vec1 32 ssa_120 = ffma ssa_74.z, ssa_67, ssa_116
>		vec1 32 ssa_121 = ffma ssa_74.w, ssa_67, ssa_117
>		vec1 32 ssa_122 = ffma ssa_78.x, ssa_71, ssa_118
>		vec1 32 ssa_123 = ffma ssa_78.y, ssa_71, ssa_119
>		vec1 32 ssa_124 = ffma ssa_78.z, ssa_71, ssa_120
>		vec1 32 ssa_125 = ffma ssa_78.w, ssa_71, ssa_121
>		vec1 32 ssa_126 = fadd ssa_122, ssa_81.x
>		vec1 32 ssa_127 = fadd ssa_123, ssa_81.y
>		vec1 32 ssa_128 = fadd ssa_124, ssa_81.z
>		vec1 32 ssa_129 = fadd ssa_125, ssa_81.w
>		vec1 32 ssa_130 = frcp ssa_97
>		vec1 32 ssa_131 = fmul ssa_94, ssa_130
>		vec1 32 ssa_132 = fmul ssa_95, ssa_130
>		vec1 32 ssa_133 = fmul ssa_96, ssa_130
>		vec1 32 ssa_134 = frcp ssa_113
>		vec1 32 ssa_135 = fmul ssa_110, ssa_134
>		vec1 32 ssa_136 = fmul ssa_111, ssa_134
>		vec1 32 ssa_137 = fmul ssa_112, ssa_134
>		vec1 32 ssa_138 = frcp ssa_129
>		vec1 32 ssa_139 = fmul ssa_126, ssa_138
>		vec1 32 ssa_140 = fmul ssa_127, ssa_138
>		vec1 32 ssa_141 = fmul ssa_128, ssa_138
>		vec1 32 ssa_142 = flt ssa_3, ssa_133
>		/* succs: block_8 block_9 */
>		if ssa_142 {
>			block block_8:
>			/* preds: block_7 */
>			vec1 32 ssa_143 = flt ssa_3, ssa_137
>			/* succs: block_10 */
>		} else {
>			block block_9:
>			/* preds: block_7 */
>			/* succs: block_10 */
>		}
>		block block_10:
>		/* preds: block_8 block_9 */
>		vec1 32 ssa_144 = phi block_8: ssa_143, block_9: ssa_1
>		/* succs: block_11 block_12 */
>		if ssa_144 {
>			block block_11:
>			/* preds: block_10 */
>			vec1 32 ssa_145 = flt ssa_3, ssa_141
>			/* succs: block_13 */
>		} else {
>			block block_12:
>			/* preds: block_10 */
>			/* succs: block_13 */
>		}
>		block block_13:
>		/* preds: block_11 block_12 */
>		vec1 32 ssa_146 = phi block_11: ssa_145, block_12: ssa_1
>		vec1 32 ssa_147 = inot ssa_146
>		/* succs: block_14 block_15 */
>		if ssa_147 {
>			block block_14:
>			/* preds: block_13 */
>			vec1 32 ssa_148 = flt ssa_133, ssa_1
>			/* succs: block_16 */
>		} else {
>			block block_15:
>			/* preds: block_13 */
>			/* succs: block_16 */
>		}
>		block block_16:
>		/* preds: block_14 block_15 */
>		vec1 32 ssa_149 = phi block_14: ssa_148, block_15: ssa_1
>		/* succs: block_17 block_18 */
>		if ssa_149 {
>			block block_17:
>			/* preds: block_16 */
>			vec1 32 ssa_150 = flt ssa_137, ssa_1
>			/* succs: block_19 */
>		} else {
>			block block_18:
>			/* preds: block_16 */
>			/* succs: block_19 */
>		}
>		block block_19:
>		/* preds: block_17 block_18 */
>		vec1 32 ssa_151 = phi block_17: ssa_150, block_18: ssa_1
>		/* succs: block_20 block_21 */
>		if ssa_151 {
>			block block_20:
>			/* preds: block_19 */
>			vec1 32 ssa_152 = flt ssa_141, ssa_1
>			/* succs: block_22 */
>		} else {
>			block block_21:
>			/* preds: block_19 */
>			/* succs: block_22 */
>		}
>		block block_22:
>		/* preds: block_20 block_21 */
>		vec1 32 ssa_153 = phi block_20: ssa_152, block_21: ssa_1
>		vec1 32 ssa_154 = bcsel ssa_153, ssa_2, ssa_146
>		vec1 32 ssa_155 = inot ssa_154
>		/* succs: block_23 block_24 */
>		if ssa_155 {
>			block block_23:
>			/* preds: block_22 */
>			vec1 32 ssa_156 = flt ssa_131, ssa_4
>			/* succs: block_25 */
>		} else {
>			block block_24:
>			/* preds: block_22 */
>			/* succs: block_25 */
>		}
>		block block_25:
>		/* preds: block_23 block_24 */
>		vec1 32 ssa_157 = phi block_23: ssa_156, block_24: ssa_1
>		/* succs: block_26 block_27 */
>		if ssa_157 {
>			block block_26:
>			/* preds: block_25 */
>			vec1 32 ssa_158 = flt ssa_135, ssa_4
>			/* succs: block_28 */
>		} else {
>			block block_27:
>			/* preds: block_25 */
>			/* succs: block_28 */
>		}
>		block block_28:
>		/* preds: block_26 block_27 */
>		vec1 32 ssa_159 = phi block_26: ssa_158, block_27: ssa_1
>		/* succs: block_29 block_30 */
>		if ssa_159 {
>			block block_29:
>			/* preds: block_28 */
>			vec1 32 ssa_160 = flt ssa_139, ssa_4
>			/* succs: block_31 */
>		} else {
>			block block_30:
>			/* preds: block_28 */
>			/* succs: block_31 */
>		}
>		block block_31:
>		/* preds: block_29 block_30 */
>		vec1 32 ssa_161 = phi block_29: ssa_160, block_30: ssa_1
>		vec1 32 ssa_162 = bcsel ssa_161, ssa_2, ssa_154
>		vec1 32 ssa_163 = inot ssa_162
>		/* succs: block_32 block_33 */
>		if ssa_163 {
>			block block_32:
>			/* preds: block_31 */
>			vec1 32 ssa_164 = flt ssa_3, ssa_131
>			/* succs: block_34 */
>		} else {
>			block block_33:
>			/* preds: block_31 */
>			/* succs: block_34 */
>		}
>		block block_34:
>		/* preds: block_32 block_33 */
>		vec1 32 ssa_165 = phi block_32: ssa_164, block_33: ssa_1
>		/* succs: block_35 block_36 */
>		if ssa_165 {
>			block block_35:
>			/* preds: block_34 */
>			vec1 32 ssa_166 = flt ssa_3, ssa_135
>			/* succs: block_37 */
>		} else {
>			block block_36:
>			/* preds: block_34 */
>			/* succs: block_37 */
>		}
>		block block_37:
>		/* preds: block_35 block_36 */
>		vec1 32 ssa_167 = phi block_35: ssa_166, block_36: ssa_1
>		/* succs: block_38 block_39 */
>		if ssa_167 {
>			block block_38:
>			/* preds: block_37 */
>			vec1 32 ssa_168 = flt ssa_3, ssa_139
>			/* succs: block_40 */
>		} else {
>			block block_39:
>			/* preds: block_37 */
>			/* succs: block_40 */
>		}
>		block block_40:
>		/* preds: block_38 block_39 */
>		vec1 32 ssa_169 = phi block_38: ssa_168, block_39: ssa_1
>		vec1 32 ssa_170 = bcsel ssa_169, ssa_2, ssa_162
>		vec1 32 ssa_171 = inot ssa_170
>		/* succs: block_41 block_42 */
>		if ssa_171 {
>			block block_41:
>			/* preds: block_40 */
>			vec1 32 ssa_172 = flt ssa_132, ssa_4
>			/* succs: block_43 */
>		} else {
>			block block_42:
>			/* preds: block_40 */
>			/* succs: block_43 */
>		}
>		block block_43:
>		/* preds: block_41 block_42 */
>		vec1 32 ssa_173 = phi block_41: ssa_172, block_42: ssa_1
>		/* succs: block_44 block_45 */
>		if ssa_173 {
>			block block_44:
>			/* preds: block_43 */
>			vec1 32 ssa_174 = flt ssa_136, ssa_4
>			/* succs: block_46 */
>		} else {
>			block block_45:
>			/* preds: block_43 */
>			/* succs: block_46 */
>		}
>		block block_46:
>		/* preds: block_44 block_45 */
>		vec1 32 ssa_175 = phi block_44: ssa_174, block_45: ssa_1
>		/* succs: block_47 block_48 */
>		if ssa_175 {
>			block block_47:
>			/* preds: block_46 */
>			vec1 32 ssa_176 = flt ssa_140, ssa_4
>			/* succs: block_49 */
>		} else {
>			block block_48:
>			/* preds: block_46 */
>			/* succs: block_49 */
>		}
>		block block_49:
>		/* preds: block_47 block_48 */
>		vec1 32 ssa_177 = phi block_47: ssa_176, block_48: ssa_1
>		vec1 32 ssa_178 = bcsel ssa_177, ssa_2, ssa_170
>		vec1 32 ssa_179 = inot ssa_178
>		/* succs: block_50 block_51 */
>		if ssa_179 {
>			block block_50:
>			/* preds: block_49 */
>			vec1 32 ssa_180 = flt ssa_3, ssa_132
>			/* succs: block_52 */
>		} else {
>			block block_51:
>			/* preds: block_49 */
>			/* succs: block_52 */
>		}
>		block block_52:
>		/* preds: block_50 block_51 */
>		vec1 32 ssa_181 = phi block_50: ssa_180, block_51: ssa_1
>		/* succs: block_53 block_54 */
>		if ssa_181 {
>			block block_53:
>			/* preds: block_52 */
>			vec1 32 ssa_182 = flt ssa_3, ssa_136
>			/* succs: block_55 */
>		} else {
>			block block_54:
>			/* preds: block_52 */
>			/* succs: block_55 */
>		}
>		block block_55:
>		/* preds: block_53 block_54 */
>		vec1 32 ssa_183 = phi block_53: ssa_182, block_54: ssa_1
>		/* succs: block_56 block_57 */
>		if ssa_183 {
>			block block_56:
>			/* preds: block_55 */
>			vec1 32 ssa_184 = flt ssa_3, ssa_140
>			/* succs: block_58 */
>		} else {
>			block block_57:
>			/* preds: block_55 */
>			/* succs: block_58 */
>		}
>		block block_58:
>		/* preds: block_56 block_57 */
>		vec1 32 ssa_185 = phi block_56: ssa_184, block_57: ssa_1
>		vec1 32 ssa_186 = bcsel ssa_185, ssa_2, ssa_178
>		vec1 32 ssa_187 = inot ssa_186
>		/* succs: block_59 block_60 */
>		if ssa_187 {
>			block block_59:
>			/* preds: block_58 */
>			vec1 32 ssa_188 = fmul ssa_111, ssa_129
>			vec1 32 ssa_189 = fmul ssa_113, ssa_126
>			vec1 32 ssa_190 = fmul ssa_110, ssa_127
>			vec1 32 ssa_191 = fmul ssa_113, ssa_127
>			vec1 32 ssa_192 = fmul ssa_110, ssa_129
>			vec1 32 ssa_193 = fmul ssa_111, ssa_126
>			vec1 32 ssa_194 = fmul ssa_94, ssa_191
>			vec1 32 ssa_195 = fmul ssa_95, ssa_192
>			vec1 32 ssa_196 = fmul ssa_97, ssa_193
>			vec1 32 ssa_197 = ffma ssa_94, ssa_188, -ssa_194
>			vec1 32 ssa_198 = ffma ssa_95, ssa_189, -ssa_195
>			vec1 32 ssa_199 = ffma ssa_97, ssa_190, -ssa_196
>			vec1 32 ssa_200 = fadd ssa_198, ssa_199
>			vec1 32 ssa_201 = fadd ssa_197, ssa_200
>			vec1 32 ssa_202 = flt ssa_1, ssa_201
>			/* succs: block_61 */
>		} else {
>			block block_60:
>			/* preds: block_58 */
>			/* succs: block_61 */
>		}
>		block block_61:
>		/* preds: block_59 block_60 */
>		vec1 32 ssa_203 = phi block_59: ssa_202, block_60: ssa_186
>		intrinsic barrier () ()
>		intrinsic group_memory_barrier () ()
>		vec1 32 ssa_204 = inot ssa_203
>		/* succs: block_62 block_63 */
>		if ssa_204 {
>			block block_62:
>			/* preds: block_61 */
>			vec1 32 ssa_205 = intrinsic load_uniform (ssa_44) (0, 20) /* base=0 */ /* range=20 */
>			vec1 32 ssa_206 = load_const (0x00000014 /* 0.000000 */)
>			vec1 32 ssa_207 = imul ssa_205, ssa_206
>			vec1 32 ssa_208 = intrinsic ssbo_atomic_add (ssa_5, ssa_207, ssa_0) ()
>			vec1 32 ssa_209 = imul ssa_208, ssa_41
>			intrinsic store_ssbo (ssa_43, ssa_44, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_210 = iadd ssa_44, ssa_209
>			intrinsic store_ssbo (ssa_46, ssa_44, ssa_210) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_211 = iadd ssa_36, ssa_209
>			intrinsic store_ssbo (ssa_48, ssa_44, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */
>			/* succs: block_64 */
>		} else {
>			block block_63:
>			/* preds: block_61 */
>			/* succs: block_64 */
>		}
>		block block_64:
>		/* preds: block_62 block_63 */
>		/* succs: block_66 */
>	} else {
>		block block_65:
>		/* preds: block_6 */
>		/* succs: block_66 */
>	}
>	block block_66:
>	/* preds: block_64 block_65 */
>	/* succs: block_67 */
>	block block_67:
>}
>
>NIR (final form) for compute shader:
>shader: MESA_SHADER_COMPUTE
>local-size: 64, 1, 1
>shared-size: 1
>inputs: 0
>outputs: 0
>uniforms: 140
>shared: 4
>decl_function main (0 params)
>
>impl main {
>	decl_reg vec1 32 r0
>	decl_reg vec1 32 r1
>	decl_reg vec1 32 r2
>	decl_reg vec1 32 r3
>	decl_reg vec1 32 r4
>	decl_reg vec1 32 r5
>	decl_reg vec1 32 r6
>	decl_reg vec1 32 r7
>	decl_reg vec1 32 r8
>	decl_reg vec1 32 r9
>	decl_reg vec1 32 r10
>	decl_reg vec1 32 r11
>	decl_reg vec1 32 r12
>	decl_reg vec1 32 r13
>	decl_reg vec1 32 r14
>	decl_reg vec1 32 r15
>	decl_reg vec1 32 r16
>	decl_reg vec1 32 r17
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_2 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_3 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_4 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */)
>	vec3 32 ssa_6 = intrinsic load_work_group_id () ()
>	vec3 32 ssa_7 = intrinsic load_uniform (ssa_1) (128, 12) /* base=128 */ /* range=12 */
>	vec1 32 ssa_8 = iadd ssa_6.x, ssa_7.x
>	vec1 32 ssa_9 = intrinsic load_subgroup_id () ()
>	vec1 32 ssa_10 = load_const (0x00000020 /* 0.000000 */)
>	vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */)
>	vec1 32 ssa_12 = ishl ssa_9, ssa_11
>	vec1 32 ssa_13 = intrinsic load_subgroup_invocation () ()
>	vec1 32 ssa_14 = iadd ssa_13, ssa_12
>	vec1 32 ssa_15 = load_const (0x0000003f /* 0.000000 */)
>	vec1 32 ssa_16 = iand ssa_14, ssa_15
>	vec1 32 ssa_17 = load_const (0x00000006 /* 0.000000 */)
>	vec1 32 ssa_18 = ishl ssa_8, ssa_17
>	vec1 32 ssa_19 = iadd ssa_18, ssa_16
>	vec1 32 ssa_20 = ieq ssa_19, ssa_1
>	/* succs: block_1 block_2 */
>	if ssa_20 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_21 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_22 = intrinsic load_uniform (ssa_21) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_23 = load_const (0x00000014 /* 0.000000 */)
>		vec1 32 ssa_24 = imul ssa_22, ssa_23
>		intrinsic store_ssbo (ssa_1, ssa_5, ssa_24) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_25 = iadd ssa_21, ssa_24
>		intrinsic store_ssbo (ssa_5, ssa_5, ssa_25) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_26 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_27 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_28 = iadd ssa_27, ssa_24
>		intrinsic store_ssbo (ssa_26, ssa_5, ssa_28) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_29 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_30 = intrinsic load_uniform (ssa_29) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_31 = load_const (0x00000008 /* 0.000000 */)
>		vec1 32 ssa_32 = iadd ssa_31, ssa_24
>		intrinsic store_ssbo (ssa_30, ssa_5, ssa_32) (1, 0) /* wrmask=x */ /* access=0 */
>		vec1 32 ssa_33 = intrinsic load_uniform (ssa_27) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_34 = iadd ssa_29, ssa_24
>		intrinsic store_ssbo (ssa_33, ssa_5, ssa_34) (1, 0) /* wrmask=x */ /* access=0 */
>		/* succs: block_3 */
>	} else {
>		block block_2:
>		/* preds: block_0 */
>		/* succs: block_3 */
>	}
>	block block_3:
>	/* preds: block_1 block_2 */
>	vec1 32 ssa_35 = ieq ssa_16, ssa_1
>	/* succs: block_4 block_5 */
>	if ssa_35 {
>		block block_4:
>		/* preds: block_3 */
>		intrinsic store_shared (ssa_1, ssa_1) (0, 1) /* base=0 */ /* wrmask=x */
>		/* succs: block_6 */
>	} else {
>		block block_5:
>		/* preds: block_3 */
>		/* succs: block_6 */
>	}
>	block block_6:
>	/* preds: block_4 block_5 */
>	intrinsic memory_barrier_shared () ()
>	vec1 32 ssa_36 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_37 = intrinsic load_uniform (ssa_36) (0, 20) /* base=0 */ /* range=20 */
>	vec1 32 ssa_38 = udiv ssa_37, ssa_0
>	vec1 32 ssa_39 = ult ssa_19, ssa_38
>	/* succs: block_7 block_65 */
>	if ssa_39 {
>		block block_7:
>		/* preds: block_6 */
>		vec1 32 ssa_40 = load_const (0x00000002 /* 0.000000 */)
>		vec1 32 ssa_41 = load_const (0x0000000c /* 0.000000 */)
>		vec1 32 ssa_42 = imul ssa_19, ssa_41
>		vec1 32 ssa_43 = intrinsic load_ssbo (ssa_40, ssa_42) (16) /* access=16 */
>		vec1 32 ssa_44 = load_const (0x00000004 /* 0.000000 */)
>		vec1 32 ssa_45 = iadd ssa_44, ssa_42
>		vec1 32 ssa_46 = intrinsic load_ssbo (ssa_40, ssa_45) (16) /* access=16 */
>		vec1 32 ssa_47 = iadd ssa_36, ssa_42
>		vec1 32 ssa_48 = intrinsic load_ssbo (ssa_40, ssa_47) (16) /* access=16 */
>		vec1 32 ssa_49 = load_const (0x00000010 /* 0.000000 */)
>		vec1 32 ssa_50 = intrinsic load_uniform (ssa_49) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_51 = iadd ssa_50, ssa_43
>		vec1 32 ssa_52 = imul ssa_51, ssa_41
>		vec1 32 ssa_53 = intrinsic load_ssbo (ssa_0, ssa_52) (16) /* access=16 */
>		vec1 32 ssa_54 = iadd ssa_44, ssa_52
>		vec1 32 ssa_55 = intrinsic load_ssbo (ssa_0, ssa_54) (16) /* access=16 */
>		vec1 32 ssa_56 = iadd ssa_36, ssa_52
>		vec1 32 ssa_57 = intrinsic load_ssbo (ssa_0, ssa_56) (16) /* access=16 */
>		vec1 32 ssa_58 = iadd ssa_50, ssa_46
>		vec1 32 ssa_59 = imul ssa_58, ssa_41
>		vec1 32 ssa_60 = intrinsic load_ssbo (ssa_0, ssa_59) (16) /* access=16 */
>		vec1 32 ssa_61 = iadd ssa_44, ssa_59
>		vec1 32 ssa_62 = intrinsic load_ssbo (ssa_0, ssa_61) (16) /* access=16 */
>		vec1 32 ssa_63 = iadd ssa_36, ssa_59
>		vec1 32 ssa_64 = intrinsic load_ssbo (ssa_0, ssa_63) (16) /* access=16 */
>		vec1 32 ssa_65 = iadd ssa_50, ssa_48
>		vec1 32 ssa_66 = imul ssa_65, ssa_41
>		vec1 32 ssa_67 = intrinsic load_ssbo (ssa_0, ssa_66) (16) /* access=16 */
>		vec1 32 ssa_68 = iadd ssa_44, ssa_66
>		vec1 32 ssa_69 = intrinsic load_ssbo (ssa_0, ssa_68) (16) /* access=16 */
>		vec1 32 ssa_70 = iadd ssa_36, ssa_66
>		vec1 32 ssa_71 = intrinsic load_ssbo (ssa_0, ssa_70) (16) /* access=16 */
>		vec1 32 ssa_72 = intrinsic load_uniform (ssa_1) (0, 20) /* base=0 */ /* range=20 */
>		vec1 32 ssa_73 = ishl ssa_72, ssa_17
>		vec4 32 ssa_74 = intrinsic load_ubo (ssa_1, ssa_73) ()
>		vec1 32 ssa_75 = iadd ssa_49, ssa_73
>		vec4 32 ssa_76 = intrinsic load_ubo (ssa_1, ssa_75) ()
>		vec1 32 ssa_77 = iadd ssa_10, ssa_73
>		vec4 32 ssa_78 = intrinsic load_ubo (ssa_1, ssa_77) ()
>		vec1 32 ssa_79 = load_const (0x00000030 /* 0.000000 */)
>		vec1 32 ssa_80 = iadd ssa_79, ssa_73
>		vec4 32 ssa_81 = intrinsic load_ubo (ssa_1, ssa_80) ()
>		vec1 32 ssa_82 = fmul ssa_76.x, ssa_55
>		vec1 32 ssa_83 = fmul ssa_76.y, ssa_55
>		vec1 32 ssa_84 = fmul ssa_76.z, ssa_55
>		vec1 32 ssa_85 = fmul ssa_76.w, ssa_55
>		vec1 32 ssa_86 = ffma ssa_74.x, ssa_53, ssa_82
>		vec1 32 ssa_87 = ffma ssa_74.y, ssa_53, ssa_83
>		vec1 32 ssa_88 = ffma ssa_74.z, ssa_53, ssa_84
>		vec1 32 ssa_89 = ffma ssa_74.w, ssa_53, ssa_85
>		vec1 32 ssa_90 = ffma ssa_78.x, ssa_57, ssa_86
>		vec1 32 ssa_91 = ffma ssa_78.y, ssa_57, ssa_87
>		vec1 32 ssa_92 = ffma ssa_78.z, ssa_57, ssa_88
>		vec1 32 ssa_93 = ffma ssa_78.w, ssa_57, ssa_89
>		vec1 32 ssa_94 = fadd ssa_90, ssa_81.x
>		vec1 32 ssa_95 = fadd ssa_91, ssa_81.y
>		vec1 32 ssa_96 = fadd ssa_92, ssa_81.z
>		vec1 32 ssa_97 = fadd ssa_93, ssa_81.w
>		vec1 32 ssa_98 = fmul ssa_76.x, ssa_62
>		vec1 32 ssa_99 = fmul ssa_76.y, ssa_62
>		vec1 32 ssa_100 = fmul ssa_76.z, ssa_62
>		vec1 32 ssa_101 = fmul ssa_76.w, ssa_62
>		vec1 32 ssa_102 = ffma ssa_74.x, ssa_60, ssa_98
>		vec1 32 ssa_103 = ffma ssa_74.y, ssa_60, ssa_99
>		vec1 32 ssa_104 = ffma ssa_74.z, ssa_60, ssa_100
>		vec1 32 ssa_105 = ffma ssa_74.w, ssa_60, ssa_101
>		vec1 32 ssa_106 = ffma ssa_78.x, ssa_64, ssa_102
>		vec1 32 ssa_107 = ffma ssa_78.y, ssa_64, ssa_103
>		vec1 32 ssa_108 = ffma ssa_78.z, ssa_64, ssa_104
>		vec1 32 ssa_109 = ffma ssa_78.w, ssa_64, ssa_105
>		vec1 32 ssa_110 = fadd ssa_106, ssa_81.x
>		vec1 32 ssa_111 = fadd ssa_107, ssa_81.y
>		vec1 32 ssa_112 = fadd ssa_108, ssa_81.z
>		vec1 32 ssa_113 = fadd ssa_109, ssa_81.w
>		vec1 32 ssa_114 = fmul ssa_76.x, ssa_69
>		vec1 32 ssa_115 = fmul ssa_76.y, ssa_69
>		vec1 32 ssa_116 = fmul ssa_76.z, ssa_69
>		vec1 32 ssa_117 = fmul ssa_76.w, ssa_69
>		vec1 32 ssa_118 = ffma ssa_74.x, ssa_67, ssa_114
>		vec1 32 ssa_119 = ffma ssa_74.y, ssa_67, ssa_115
>		vec1 32 ssa_120 = ffma ssa_74.z, ssa_67, ssa_116
>		vec1 32 ssa_121 = ffma ssa_74.w, ssa_67, ssa_117
>		vec1 32 ssa_122 = ffma ssa_78.x, ssa_71, ssa_118
>		vec1 32 ssa_123 = ffma ssa_78.y, ssa_71, ssa_119
>		vec1 32 ssa_124 = ffma ssa_78.z, ssa_71, ssa_120
>		vec1 32 ssa_125 = ffma ssa_78.w, ssa_71, ssa_121
>		vec1 32 ssa_126 = fadd ssa_122, ssa_81.x
>		vec1 32 ssa_127 = fadd ssa_123, ssa_81.y
>		vec1 32 ssa_128 = fadd ssa_124, ssa_81.z
>		vec1 32 ssa_129 = fadd ssa_125, ssa_81.w
>		vec1 32 ssa_130 = frcp ssa_97
>		vec1 32 ssa_131 = fmul ssa_94, ssa_130
>		vec1 32 ssa_132 = fmul ssa_95, ssa_130
>		vec1 32 ssa_133 = fmul ssa_96, ssa_130
>		vec1 32 ssa_134 = frcp ssa_113
>		vec1 32 ssa_135 = fmul ssa_110, ssa_134
>		vec1 32 ssa_136 = fmul ssa_111, ssa_134
>		vec1 32 ssa_137 = fmul ssa_112, ssa_134
>		vec1 32 ssa_138 = frcp ssa_129
>		vec1 32 ssa_139 = fmul ssa_126, ssa_138
>		vec1 32 ssa_140 = fmul ssa_127, ssa_138
>		vec1 32 ssa_141 = fmul ssa_128, ssa_138
>		vec1 32 ssa_142 = flt ssa_3, ssa_133
>		/* succs: block_8 block_9 */
>		if ssa_142 {
>			block block_8:
>			/* preds: block_7 */
>			r0 = flt ssa_3, ssa_137
>			/* succs: block_10 */
>		} else {
>			block block_9:
>			/* preds: block_7 */
>			r0 = imov ssa_1
>			/* succs: block_10 */
>		}
>		block block_10:
>		/* preds: block_8 block_9 */
>		/* succs: block_11 block_12 */
>		if r0 {
>			block block_11:
>			/* preds: block_10 */
>			r1 = flt ssa_3, ssa_141
>			/* succs: block_13 */
>		} else {
>			block block_12:
>			/* preds: block_10 */
>			r1 = imov ssa_1
>			/* succs: block_13 */
>		}
>		block block_13:
>		/* preds: block_11 block_12 */
>		vec1 32 ssa_147 = inot r1
>		/* succs: block_14 block_15 */
>		if ssa_147 {
>			block block_14:
>			/* preds: block_13 */
>			r2 = flt ssa_133, ssa_1
>			/* succs: block_16 */
>		} else {
>			block block_15:
>			/* preds: block_13 */
>			r2 = imov ssa_1
>			/* succs: block_16 */
>		}
>		block block_16:
>		/* preds: block_14 block_15 */
>		/* succs: block_17 block_18 */
>		if r2 {
>			block block_17:
>			/* preds: block_16 */
>			r3 = flt ssa_137, ssa_1
>			/* succs: block_19 */
>		} else {
>			block block_18:
>			/* preds: block_16 */
>			r3 = imov ssa_1
>			/* succs: block_19 */
>		}
>		block block_19:
>		/* preds: block_17 block_18 */
>		/* succs: block_20 block_21 */
>		if r3 {
>			block block_20:
>			/* preds: block_19 */
>			r4 = flt ssa_141, ssa_1
>			/* succs: block_22 */
>		} else {
>			block block_21:
>			/* preds: block_19 */
>			r4 = imov ssa_1
>			/* succs: block_22 */
>		}
>		block block_22:
>		/* preds: block_20 block_21 */
>		vec1 32 ssa_154 = bcsel r4, ssa_2, r1
>		vec1 32 ssa_155 = inot ssa_154
>		/* succs: block_23 block_24 */
>		if ssa_155 {
>			block block_23:
>			/* preds: block_22 */
>			r5 = flt ssa_131, ssa_4
>			/* succs: block_25 */
>		} else {
>			block block_24:
>			/* preds: block_22 */
>			r5 = imov ssa_1
>			/* succs: block_25 */
>		}
>		block block_25:
>		/* preds: block_23 block_24 */
>		/* succs: block_26 block_27 */
>		if r5 {
>			block block_26:
>			/* preds: block_25 */
>			r6 = flt ssa_135, ssa_4
>			/* succs: block_28 */
>		} else {
>			block block_27:
>			/* preds: block_25 */
>			r6 = imov ssa_1
>			/* succs: block_28 */
>		}
>		block block_28:
>		/* preds: block_26 block_27 */
>		/* succs: block_29 block_30 */
>		if r6 {
>			block block_29:
>			/* preds: block_28 */
>			r7 = flt ssa_139, ssa_4
>			/* succs: block_31 */
>		} else {
>			block block_30:
>			/* preds: block_28 */
>			r7 = imov ssa_1
>			/* succs: block_31 */
>		}
>		block block_31:
>		/* preds: block_29 block_30 */
>		vec1 32 ssa_162 = bcsel r7, ssa_2, ssa_154
>		vec1 32 ssa_163 = inot ssa_162
>		/* succs: block_32 block_33 */
>		if ssa_163 {
>			block block_32:
>			/* preds: block_31 */
>			r8 = flt ssa_3, ssa_131
>			/* succs: block_34 */
>		} else {
>			block block_33:
>			/* preds: block_31 */
>			r8 = imov ssa_1
>			/* succs: block_34 */
>		}
>		block block_34:
>		/* preds: block_32 block_33 */
>		/* succs: block_35 block_36 */
>		if r8 {
>			block block_35:
>			/* preds: block_34 */
>			r9 = flt ssa_3, ssa_135
>			/* succs: block_37 */
>		} else {
>			block block_36:
>			/* preds: block_34 */
>			r9 = imov ssa_1
>			/* succs: block_37 */
>		}
>		block block_37:
>		/* preds: block_35 block_36 */
>		/* succs: block_38 block_39 */
>		if r9 {
>			block block_38:
>			/* preds: block_37 */
>			r10 = flt ssa_3, ssa_139
>			/* succs: block_40 */
>		} else {
>			block block_39:
>			/* preds: block_37 */
>			r10 = imov ssa_1
>			/* succs: block_40 */
>		}
>		block block_40:
>		/* preds: block_38 block_39 */
>		vec1 32 ssa_170 = bcsel r10, ssa_2, ssa_162
>		vec1 32 ssa_171 = inot ssa_170
>		/* succs: block_41 block_42 */
>		if ssa_171 {
>			block block_41:
>			/* preds: block_40 */
>			r11 = flt ssa_132, ssa_4
>			/* succs: block_43 */
>		} else {
>			block block_42:
>			/* preds: block_40 */
>			r11 = imov ssa_1
>			/* succs: block_43 */
>		}
>		block block_43:
>		/* preds: block_41 block_42 */
>		/* succs: block_44 block_45 */
>		if r11 {
>			block block_44:
>			/* preds: block_43 */
>			r12 = flt ssa_136, ssa_4
>			/* succs: block_46 */
>		} else {
>			block block_45:
>			/* preds: block_43 */
>			r12 = imov ssa_1
>			/* succs: block_46 */
>		}
>		block block_46:
>		/* preds: block_44 block_45 */
>		/* succs: block_47 block_48 */
>		if r12 {
>			block block_47:
>			/* preds: block_46 */
>			r13 = flt ssa_140, ssa_4
>			/* succs: block_49 */
>		} else {
>			block block_48:
>			/* preds: block_46 */
>			r13 = imov ssa_1
>			/* succs: block_49 */
>		}
>		block block_49:
>		/* preds: block_47 block_48 */
>		vec1 32 ssa_178 = bcsel r13, ssa_2, ssa_170
>		vec1 32 ssa_179 = inot ssa_178
>		/* succs: block_50 block_51 */
>		if ssa_179 {
>			block block_50:
>			/* preds: block_49 */
>			r14 = flt ssa_3, ssa_132
>			/* succs: block_52 */
>		} else {
>			block block_51:
>			/* preds: block_49 */
>			r14 = imov ssa_1
>			/* succs: block_52 */
>		}
>		block block_52:
>		/* preds: block_50 block_51 */
>		/* succs: block_53 block_54 */
>		if r14 {
>			block block_53:
>			/* preds: block_52 */
>			r15 = flt ssa_3, ssa_136
>			/* succs: block_55 */
>		} else {
>			block block_54:
>			/* preds: block_52 */
>			r15 = imov ssa_1
>			/* succs: block_55 */
>		}
>		block block_55:
>		/* preds: block_53 block_54 */
>		/* succs: block_56 block_57 */
>		if r15 {
>			block block_56:
>			/* preds: block_55 */
>			r16 = flt ssa_3, ssa_140
>			/* succs: block_58 */
>		} else {
>			block block_57:
>			/* preds: block_55 */
>			r16 = imov ssa_1
>			/* succs: block_58 */
>		}
>		block block_58:
>		/* preds: block_56 block_57 */
>		r17 = bcsel r16, ssa_2, ssa_178
>		vec1 32 ssa_187 = inot r17
>		/* succs: block_59 block_60 */
>		if ssa_187 {
>			block block_59:
>			/* preds: block_58 */
>			vec1 32 ssa_188 = fmul ssa_111, ssa_129
>			vec1 32 ssa_189 = fmul ssa_113, ssa_126
>			vec1 32 ssa_190 = fmul ssa_110, ssa_127
>			vec1 32 ssa_191 = fmul ssa_113, ssa_127
>			vec1 32 ssa_192 = fmul ssa_110, ssa_129
>			vec1 32 ssa_193 = fmul ssa_111, ssa_126
>			vec1 32 ssa_194 = fmul ssa_94, ssa_191
>			vec1 32 ssa_195 = fmul ssa_95, ssa_192
>			vec1 32 ssa_196 = fmul ssa_97, ssa_193
>			vec1 32 ssa_197 = ffma ssa_94, ssa_188, -ssa_194
>			vec1 32 ssa_198 = ffma ssa_95, ssa_189, -ssa_195
>			vec1 32 ssa_199 = ffma ssa_97, ssa_190, -ssa_196
>			vec1 32 ssa_200 = fadd ssa_198, ssa_199
>			vec1 32 ssa_201 = fadd ssa_197, ssa_200
>			r17 = flt ssa_1, ssa_201
>			/* succs: block_61 */
>		} else {
>			block block_60:
>			/* preds: block_58 */
>			/* succs: block_61 */
>		}
>		block block_61:
>		/* preds: block_59 block_60 */
>		intrinsic barrier () ()
>		intrinsic group_memory_barrier () ()
>		vec1 32 ssa_204 = inot r17
>		/* succs: block_62 block_63 */
>		if ssa_204 {
>			block block_62:
>			/* preds: block_61 */
>			vec1 32 ssa_205 = intrinsic load_uniform (ssa_44) (0, 20) /* base=0 */ /* range=20 */
>			vec1 32 ssa_206 = load_const (0x00000014 /* 0.000000 */)
>			vec1 32 ssa_207 = imul ssa_205, ssa_206
>			vec1 32 ssa_208 = intrinsic ssbo_atomic_add (ssa_5, ssa_207, ssa_0) ()
>			vec1 32 ssa_209 = imul ssa_208, ssa_41
>			intrinsic store_ssbo (ssa_43, ssa_44, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_210 = iadd ssa_44, ssa_209
>			intrinsic store_ssbo (ssa_46, ssa_44, ssa_210) (1, 0) /* wrmask=x */ /* access=0 */
>			vec1 32 ssa_211 = iadd ssa_36, ssa_209
>			intrinsic store_ssbo (ssa_48, ssa_44, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */
>			/* succs: block_64 */
>		} else {
>			block block_63:
>			/* preds: block_61 */
>			/* succs: block_64 */
>		}
>		block block_64:
>		/* preds: block_62 block_63 */
>		/* succs: block_66 */
>	} else {
>		block block_65:
>		/* preds: block_6 */
>		/* succs: block_66 */
>	}
>	block block_66:
>	/* preds: block_64 block_65 */
>	/* succs: block_67 */
>	block block_67:
>}
>
>Native code for unnamed compute shader (null)
>SIMD32 shader: 496 instructions. 0 loops. 19586 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 7936 to 6560 bytes (17%)
>   START B0 (162 cycles)
>mov(8)          g4<1>UW         0x76543210V                     { align1 WE_all 1Q };
>mov(16)         g60<1>UD        g0.1<0,1,0>UD                   { align1 1H compacted };
>mov(16)         g8<1>UD         g0.1<0,1,0>UD                   { align1 2H };
>add(8)          g4.8<1>UW       g4<8,8,1>UW     0x0008UW        { align1 WE_all 1Q };
>add(16)         g55<1>D         g60<8,8,1>D     g1.5<0,1,0>D    { align1 1H compacted };
>add(16)         g63<1>D         g8<8,8,1>D      g1.5<0,1,0>D    { align1 2H };
>add(16)         g3<1>UW         g4<16,16,1>UW   0x0010UW        { align1 WE_all 1H };
>mov(16)         g58<1>D         g4<8,8,1>UW                     { align1 1H };
>shl(16)         g68<1>D         g55<8,8,1>D     0x00000006UD    { align1 1H };
>shl(16)         g46<1>D         g63<8,8,1>D     0x00000006UD    { align1 2H };
>shl(16)         g56<1>D         g2<0,1,0>D      0x00000005UD    { align1 1H };
>shl(16)         g64<1>D         g2<0,1,0>D      0x00000005UD    { align1 2H };
>mov(16)         g66<1>D         g3<8,8,1>UW                     { align1 2H };
>add(16)         g60<1>D         g58<8,8,1>D     g56<8,8,1>D     { align1 1H compacted };
>and(16)         g62<1>UD        g60<8,8,1>UD    0x0000003fUD    { align1 1H compacted };
>add.z.f0(16)    g76<1>D         g68<8,8,1>D     g62<8,8,1>D     { align1 1H compacted };
>add(16)         g68<1>D         g66<8,8,1>D     g64<8,8,1>D     { align1 2H };
>and(16)         g70<1>UD        g68<8,8,1>UD    0x0000003fUD    { align1 2H };
>add.z.f0(16)    g50<1>D         g46<8,8,1>D     g70<8,8,1>D     { align1 2H };
>(+f0) if(32)    JIP: 416        UIP: 416                        { align1 };
>   END B0 ->B1 ->B2
>   START B1 <-B0 (260 cycles)
>mul(16)         g2<1>D          g1.1<0,1,0>D    20D             { align1 1H compacted };
>mul(16)         g6<1>D          g1.1<0,1,0>D    20D             { align1 2H };
>mov(16)         g4<1>UD         0x00000000UD                    { align1 1H compacted };
>send(16)        null<1>UW       g2<8,8,1>UD     0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>mov(16)         g8<1>D          0D                              { align1 2H };
>send(16)        null<1>UW       g6<8,8,1>UD     0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>add(16)         g10<1>D         g2<8,8,1>D      4D              { align1 1H compacted };
>add(16)         g14<1>D         g6<8,8,1>D      4D              { align1 2H };
>mov(16)         g12<1>UD        0x00000001UD                    { align1 1H compacted };
>send(16)        null<1>UW       g10<8,8,1>UD    0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>mov(16)         g16<1>D         1D                              { align1 2H };
>send(16)        null<1>UW       g14<8,8,1>UD    0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>add(16)         g15<1>D         g2<8,8,1>D      16D             { align1 1H compacted };
>add(16)         g19<1>D         g6<8,8,1>D      16D             { align1 2H };
>mov(16)         g17<1>D         g1<0,1,0>D                      { align1 1H compacted };
>send(16)        null<1>UW       g15<8,8,1>UD    0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>mov(16)         g21<1>D         g1<0,1,0>D                      { align1 2H };
>send(16)        null<1>UW       g19<8,8,1>UD    0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>add(16)         g20<1>D         g2<8,8,1>D      8D              { align1 1H compacted };
>add(16)         g24<1>D         g6<8,8,1>D      8D              { align1 2H };
>mov(16)         g22<1>D         g1.3<0,1,0>D                    { align1 1H compacted };
>send(16)        null<1>UW       g20<8,8,1>UD    0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>mov(16)         g26<1>D         g1.3<0,1,0>D                    { align1 2H };
>send(16)        null<1>UW       g24<8,8,1>UD    0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>add(16)         g25<1>D         g2<8,8,1>D      12D             { align1 1H compacted };
>add(16)         g29<1>D         g6<8,8,1>D      12D             { align1 2H };
>mov(16)         g27<1>D         g1.4<0,1,0>D                    { align1 1H compacted };
>send(16)        null<1>UW       g25<8,8,1>UD    0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>mov(16)         g31<1>D         g1.4<0,1,0>D                    { align1 2H };
>send(16)        null<1>UW       g29<8,8,1>UD    0x08025e02
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>   END B1 ->B2
>   START B2 <-B0 <-B1 (26 cycles)
>endif(32)       JIP: 16                                         { align1 };
>cmp.z.f0(16)    null<1>D        g62<8,8,1>D     0D              { align1 1H compacted };
>cmp.z.f0(16)    null<1>D        g70<8,8,1>D     0D              { align1 2H };
>(+f0) if(32)    JIP: 96         UIP: 96                         { align1 };
>   END B2 ->B3 ->B4
>   START B3 <-B2 (52 cycles)
>mov(16)         g30<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g32<1>UD        0x00000000UD                    { align1 1H compacted };
>send(16)        null<1>UW       g30<8,8,1>UD    0x08025efe
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>mov(16)         g31<1>UD        0x00000000UD                    { align1 2H };
>mov(16)         g33<1>D         0D                              { align1 2H };
>send(16)        null<1>UW       g31<8,8,1>UD    0x08025efe
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>   END B3 ->B4
>   START B4 <-B2 <-B3 (62 cycles)
>endif(32)       JIP: 16                                         { align1 };
>send(1)         g80<1>UW        g80<0,1,0>UW    0x0209c000
>                            data MsgDesc: ( DC mfence, 0, 0) mlen 1 rlen 0  { align1 WE_all 1N };
>math intdiv(8)  g82<1>UD        g1.2<0,1,0>UD   0x00000003UD    { align1 1Q compacted };
>math intdiv(8)  g83<1>UD        g1.2<0,1,0>UD   0x00000003UD    { align1 2Q compacted };
>math intdiv(8)  g81<1>UD        g1.2<0,1,0>UD   0x00000003UD    { align1 3Q };
>cmp.l.f0(16)    null<1>UD       g76<8,8,1>UD    g82<8,8,1>UD    { align1 1H compacted };
>math intdiv(8)  g82<1>UD        g1.2<0,1,0>UD   0x00000003UD    { align1 4Q };
>cmp.l.f0(16)    null<1>UD       g50<8,8,1>UD    g81<8,8,1>UD    { align1 2H };
>(+f0) if(32)    JIP: 5592       UIP: 5592                       { align1 };
>   END B4 ->B5 ->B61
>   START B5 <-B4 (3626 cycles)
>mul(16)         g83<1>D         g76<8,8,1>D     12D             { align1 1H compacted };
>shl(16)         g44<1>D         g1<0,1,0>D      0x00000006UD    { align1 1H };
>send(16)        g12<1>UW        g83<8,8,1>UD    0x04205e03
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>add(16)         g85<1>D         g83<8,8,1>D     4D              { align1 1H compacted };
>add(16)         g87<1>D         g83<8,8,1>D     8D              { align1 1H compacted };
>mul(16)         g82<1>D         g50<8,8,1>D     12D             { align1 2H };
>send(16)        g20<1>UW        g85<8,8,1>UD    0x04205e03
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>send(16)        g28<1>UW        g87<8,8,1>UD    0x04205e03
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>add(16)         g86<1>D         g82<8,8,1>D     4D              { align1 2H };
>send(16)        g16<1>UW        g82<8,8,1>UD    0x04205e03
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>send(16)        g24<1>UW        g86<8,8,1>UD    0x04205e03
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>add(16)         g89<1>D         g1.4<0,1,0>D    g12<8,8,1>D     { align1 1H compacted };
>mul(16)         g94<1>D         g89<8,8,1>D     12D             { align1 1H compacted };
>add(16)         g90<1>D         g82<8,8,1>D     8D              { align1 2H };
>add(16)         g38<1>D         g94<8,8,1>D     4D              { align1 1H compacted };
>send(16)        g52<1>UW        g94<8,8,1>UD    0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>send(16)        g32<1>UW        g90<8,8,1>UD    0x04205e03
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>send(16)        g92<1>UW        g38<8,8,1>UD    0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>add(16)         g39<1>D         g94<8,8,1>D     8D              { align1 1H compacted };
>send(16)        g96<1>UW        g39<8,8,1>UD    0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>add(16)         g38<1>D         g1.4<0,1,0>D    g16<8,8,1>D     { align1 2H };
>add(16)         g40<1>D         g1.4<0,1,0>D    g20<8,8,1>D     { align1 1H compacted };
>mul(16)         g100<1>D        g40<8,8,1>D     12D             { align1 1H compacted };
>mul(16)         g40<1>D         g38<8,8,1>D     12D             { align1 2H };
>add(16)         g102<1>D        g100<8,8,1>D    4D              { align1 1H compacted };
>send(16)        g74<1>UW        g100<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>send(16)        g76<1>UW        g40<8,8,1>UD    0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>send(16)        g108<1>UW       g102<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>add(16)         g103<1>D        g100<8,8,1>D    8D              { align1 1H compacted };
>add(16)         g100<1>D        g40<8,8,1>D     4D              { align1 2H };
>send(16)        g72<1>UW        g103<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>add(16)         g104<1>D        g1.4<0,1,0>D    g28<8,8,1>D     { align1 1H compacted };
>send(16)        g84<1>UW        g100<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>add(16)         g101<1>D        g40<8,8,1>D     8D              { align1 2H };
>mul(16)         g106<1>D        g104<8,8,1>D    12D             { align1 1H compacted };
>send(16)        g66<1>UW        g101<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>add(16)         g102<1>D        g1.4<0,1,0>D    g24<8,8,1>D     { align1 2H };
>add(16)         g110<1>D        g106<8,8,1>D    4D              { align1 1H compacted };
>send(16)        g58<1>UW        g106<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>mul(16)         g104<1>D        g102<8,8,1>D    12D             { align1 2H };
>send(16)        g94<1>UW        g110<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>add(16)         g111<1>D        g106<8,8,1>D    8D              { align1 1H compacted };
>add(16)         g106<1>D        g104<8,8,1>D    4D              { align1 2H };
>send(16)        g78<1>UW        g104<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>send(16)        g34<1>UW        g111<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
>add(16)         g110<1>D        g104<8,8,1>D    8D              { align1 2H };
>send(16)        g88<1>UW        g106<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>send(16)        g68<1>UW        g110<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>add(16)         g111<1>D        g1.4<0,1,0>D    g32<8,8,1>D     { align1 2H };
>mul(16)         g113<1>D        g111<8,8,1>D    12D             { align1 2H };
>add(16)         g115<1>D        g113<8,8,1>D    4D              { align1 2H };
>send(16)        g80<1>UW        g113<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>send(16)        g86<1>UW        g115<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>add(16)         g116<1>D        g113<8,8,1>D    8D              { align1 2H };
>add(16)         g112<1>D        g44<8,8,1>D     16D             { align1 1H compacted };
>send(16)        g70<1>UW        g116<8,8,1>UD   0x04205e04
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 2H };
>send(16)        g2<1>UW         g112<0,1,0>UD   0x04847001
>                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
>add(16)         g113<1>D        g44<8,8,1>D     32D             { align1 1H compacted };
>mul(16)         g46<1>F         g8<8,8,1>F      g92<8,8,1>F     { align1 1H compacted };
>mul(16)         g54<1>F         g8<8,8,1>F      g108<8,8,1>F    { align1 1H compacted };
>mul(16)         g56<1>F         g8<8,8,1>F      g94<8,8,1>F     { align1 1H compacted };
>mul(16)         g60<1>F         g6<8,8,1>F      g92<8,8,1>F     { align1 1H compacted };
>mul(16)         g50<1>F         g2<8,8,1>F      g108<8,8,1>F    { align1 1H compacted };
>mul(16)         g98<1>F         g4<8,8,1>F      g108<8,8,1>F    { align1 1H compacted };
>mul(16)         g42<1>F         g6<8,8,1>F      g108<8,8,1>F    { align1 1H compacted };
>mul(16)         g82<1>F         g2<8,8,1>F      g94<8,8,1>F     { align1 1H compacted };
>mul(16)         g64<1>F         g4<8,8,1>F      g94<8,8,1>F     { align1 1H compacted };
>mul(16)         g48<1>F         g6<8,8,1>F      g94<8,8,1>F     { align1 1H compacted };
>mul(16)         g90<1>F         g2<8,8,1>F      g92<8,8,1>F     { align1 1H compacted };
>mul(16)         g62<1>F         g4<8,8,1>F      g92<8,8,1>F     { align1 1H compacted };
>send(16)        g2<1>UW         g44<0,1,0>UD    0x04847001
>                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
>mad(16)         g36<1>F         g46<4,4,1>F     g52<4,4,1>F     g8<4,4,1>F { align16 1H compacted };
>mad(16)         g46<1>F         g56<4,4,1>F     g58<4,4,1>F     g8<4,4,1>F { align16 1H compacted };
>mad(16)         g56<1>F         g54<4,4,1>F     g74<4,4,1>F     g8<4,4,1>F { align16 1H compacted };
>mad(16)         g54<1>F         g60<4,4,1>F     g52<4,4,1>F     g6<4,4,1>F { align16 1H compacted };
>mad(16)         g60<1>F         g62<4,4,1>F     g52<4,4,1>F     g4<4,4,1>F { align16 1H compacted };
>mad(16)         g62<1>F         g90<4,4,1>F     g52<4,4,1>F     g2<4,4,1>F { align16 1H compacted };
>mad(16)         g52<1>F         g48<4,4,1>F     g58<4,4,1>F     g6<4,4,1>F { align16 1H compacted };
>mad(16)         g48<1>F         g64<4,4,1>F     g58<4,4,1>F     g4<4,4,1>F { align16 1H compacted };
>mad(16)         g64<1>F         g82<4,4,1>F     g58<4,4,1>F     g2<4,4,1>F { align16 1H compacted };
>mad(16)         g58<1>F         g42<4,4,1>F     g74<4,4,1>F     g6<4,4,1>F { align16 1H compacted };
>mad(16)         g42<1>F         g98<4,4,1>F     g74<4,4,1>F     g4<4,4,1>F { align16 1H compacted };
>mad(16)         g98<1>F         g50<4,4,1>F     g74<4,4,1>F     g2<4,4,1>F { align16 1H compacted };
>send(16)        g2<1>UW         g113<0,1,0>UD   0x04847001
>                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
>add(16)         g114<1>D        g44<8,8,1>D     48D             { align1 1H compacted };
>mad(16)         g74<1>F         g36<4,4,1>F     g96<4,4,1>F     g8<4,4,1>F { align16 1H compacted };
>mad(16)         g36<1>F         g54<4,4,1>F     g96<4,4,1>F     g6<4,4,1>F { align16 1H compacted };
>mad(16)         g54<1>F         g56<4,4,1>F     g72<4,4,1>F     g8<4,4,1>F { align16 1H compacted };
>mad(16)         g56<1>F         g46<4,4,1>F     g34<4,4,1>F     g8<4,4,1>F { align16 1H compacted };
>mad(16)         g46<1>F         g98<4,4,1>F     g72<4,4,1>F     g2<4,4,1>F { align16 1H compacted };
>mad(16)         g98<1>F         g42<4,4,1>F     g72<4,4,1>F     g4<4,4,1>F { align16 1H compacted };
>mad(16)         g42<1>F         g58<4,4,1>F     g72<4,4,1>F     g6<4,4,1>F { align16 1H compacted };
>mad(16)         g58<1>F         g64<4,4,1>F     g34<4,4,1>F     g2<4,4,1>F { align16 1H compacted };
>mad(16)         g72<1>F         g48<4,4,1>F     g34<4,4,1>F     g4<4,4,1>F { align16 1H compacted };
>mad(16)         g48<1>F         g52<4,4,1>F     g34<4,4,1>F     g6<4,4,1>F { align16 1H compacted };
>mad(16)         g52<1>F         g62<4,4,1>F     g96<4,4,1>F     g2<4,4,1>F { align16 1H compacted };
>mad(16)         g34<1>F         g60<4,4,1>F     g96<4,4,1>F     g4<4,4,1>F { align16 1H compacted };
>send(16)        g2<1>UW         g114<0,1,0>UD   0x04847001
>                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
>add(16)         g96<1>F         g74<8,8,1>F     g8<8,8,1>F      { align1 1H compacted };
>add(16)         g44<1>F         g54<8,8,1>F     g8<8,8,1>F      { align1 1H compacted };
>add(16)         g115<1>F        g36<8,8,1>F     g6<8,8,1>F      { align1 1H compacted };
>add(16)         g117<1>F        g48<8,8,1>F     g6<8,8,1>F      { align1 1H compacted };
>add(16)         g74<1>F         g56<8,8,1>F     g8<8,8,1>F      { align1 1H compacted };
>add(16)         g36<1>F         g34<8,8,1>F     g4<8,8,1>F      { align1 1H compacted };
>add(16)         g48<1>F         g72<8,8,1>F     g4<8,8,1>F      { align1 1H compacted };
>math inv(16)    g60<1>F         g96<8,8,1>F     null<8,8,1>F    { align1 1H compacted };
>math inv(16)    g82<1>F         g44<8,8,1>F     null<8,8,1>F    { align1 1H compacted };
>add(16)         g34<1>F         g52<8,8,1>F     g2<8,8,1>F      { align1 1H compacted };
>add(16)         g72<1>F         g58<8,8,1>F     g2<8,8,1>F      { align1 1H compacted };
>math inv(16)    g50<1>F         g74<8,8,1>F     null<8,8,1>F    { align1 1H compacted };
>mul(16)         g56<1>F         g115<8,8,1>F    g60<8,8,1>F     { align1 1H compacted };
>mul(16)         g54<1>F         g36<8,8,1>F     g60<8,8,1>F     { align1 1H compacted };
>mul(16)         g52<1>F         g34<8,8,1>F     g60<8,8,1>F     { align1 1H compacted };
>mul(16)         g60<1>F         g72<8,8,1>F     g50<8,8,1>F     { align1 1H compacted };
>mul(16)         g64<1>F         g117<8,8,1>F    g50<8,8,1>F     { align1 1H compacted };
>mul(16)         g62<1>F         g48<8,8,1>F     g50<8,8,1>F     { align1 1H compacted };
>cmp.g.f0(16)    null<1>F        g56<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>add(16)         g116<1>F        g42<8,8,1>F     g6<8,8,1>F      { align1 1H compacted };
>add(16)         g42<1>F         g98<8,8,1>F     g4<8,8,1>F      { align1 1H compacted };
>add(16)         g98<1>F         g46<8,8,1>F     g2<8,8,1>F      { align1 1H compacted };
>mul(16)         g58<1>F         g116<8,8,1>F    g82<8,8,1>F     { align1 1H compacted };
>mul(16)         g50<1>F         g42<8,8,1>F     g82<8,8,1>F     { align1 1H compacted };
>mul(16)         g46<1>F         g98<8,8,1>F     g82<8,8,1>F     { align1 1H compacted };
>shl(16)         g82<1>D         g1<0,1,0>D      0x00000006UD    { align1 2H };
>add(16)         g90<1>D         g82<8,8,1>D     16D             { align1 2H };
>send(16)        g2<1>UW         g90<0,1,0>UD    0x04847001
>                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 2H };
>mul(16)         g92<1>F         g8<8,8,1>F      g84<8,8,1>F     { align1 2H };
>mul(16)         g100<1>F        g8<8,8,1>F      g88<8,8,1>F     { align1 2H };
>mul(16)         g108<1>F        g8<8,8,1>F      g86<8,8,1>F     { align1 2H };
>mul(16)         g90<1>F         g6<8,8,1>F      g84<8,8,1>F     { align1 2H };
>mul(16)         g94<1>F         g2<8,8,1>F      g88<8,8,1>F     { align1 2H };
>mul(16)         g38<1>F         g4<8,8,1>F      g88<8,8,1>F     { align1 2H };
>mul(16)         g40<1>F         g6<8,8,1>F      g88<8,8,1>F     { align1 2H };
>mul(16)         g102<1>F        g2<8,8,1>F      g86<8,8,1>F     { align1 2H };
>mul(16)         g104<1>F        g4<8,8,1>F      g86<8,8,1>F     { align1 2H };
>mul(16)         g106<1>F        g6<8,8,1>F      g86<8,8,1>F     { align1 2H };
>mul(16)         g88<1>F         g4<8,8,1>F      g84<8,8,1>F     { align1 2H };
>mul(16)         g86<1>F         g2<8,8,1>F      g84<8,8,1>F     { align1 2H };
>send(16)        g2<1>UW         g82<0,1,0>UD    0x04847001
>                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 2H };
>mad(16)         g84<1>F         g92<4,4,1>F     g76<4,4,1>F     g8<4,4,1>F { align16 2H compacted };
>mad(16)         g92<1>F         g108<4,4,1>F    g80<4,4,1>F     g8<4,4,1>F { align16 2H compacted };
>mad(16)         g108<1>F        g100<4,4,1>F    g78<4,4,1>F     g8<4,4,1>F { align16 2H compacted };
>mad(16)         g100<1>F        g90<4,4,1>F     g76<4,4,1>F     g6<4,4,1>F { align16 2H compacted };
>mad(16)         g90<1>F         g88<4,4,1>F     g76<4,4,1>F     g4<4,4,1>F { align16 2H compacted };
>mad(16)         g88<1>F         g86<4,4,1>F     g76<4,4,1>F     g2<4,4,1>F { align16 2H compacted };
>mad(16)         g86<1>F         g104<4,4,1>F    g80<4,4,1>F     g4<4,4,1>F { align16 2H compacted };
>mad(16)         g76<1>F         g106<4,4,1>F    g80<4,4,1>F     g6<4,4,1>F { align16 2H compacted };
>mad(16)         g104<1>F        g102<4,4,1>F    g80<4,4,1>F     g2<4,4,1>F { align16 2H compacted };
>mad(16)         g80<1>F         g40<4,4,1>F     g78<4,4,1>F     g6<4,4,1>F { align16 2H compacted };
>mad(16)         g40<1>F         g38<4,4,1>F     g78<4,4,1>F     g4<4,4,1>F { align16 2H compacted };
>mad(16)         g38<1>F         g94<4,4,1>F     g78<4,4,1>F     g2<4,4,1>F { align16 2H compacted };
>add(16)         g78<1>D         g82<8,8,1>D     32D             { align1 2H };
>send(16)        g2<1>UW         g78<0,1,0>UD    0x04847001
>                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 2H };
>mad(16)         g78<1>F         g84<4,4,1>F     g66<4,4,1>F     g8<4,4,1>F { align16 2H compacted };
>mad(16)         g94<1>F         g108<4,4,1>F    g68<4,4,1>F     g8<4,4,1>F { align16 2H compacted };
>mad(16)         g84<1>F         g100<4,4,1>F    g66<4,4,1>F     g6<4,4,1>F { align16 2H compacted };
>mad(16)         g100<1>F        g92<4,4,1>F     g70<4,4,1>F     g8<4,4,1>F { align16 2H compacted };
>mad(16)         g92<1>F         g38<4,4,1>F     g68<4,4,1>F     g2<4,4,1>F { align16 2H compacted };
>mad(16)         g38<1>F         g40<4,4,1>F     g68<4,4,1>F     g4<4,4,1>F { align16 2H compacted };
>mad(16)         g40<1>F         g80<4,4,1>F     g68<4,4,1>F     g6<4,4,1>F { align16 2H compacted };
>mad(16)         g80<1>F         g86<4,4,1>F     g70<4,4,1>F     g4<4,4,1>F { align16 2H compacted };
>mad(16)         g68<1>F         g104<4,4,1>F    g70<4,4,1>F     g2<4,4,1>F { align16 2H compacted };
>mad(16)         g86<1>F         g76<4,4,1>F     g70<4,4,1>F     g6<4,4,1>F { align16 2H compacted };
>mad(16)         g76<1>F         g90<4,4,1>F     g66<4,4,1>F     g4<4,4,1>F { align16 2H compacted };
>mad(16)         g70<1>F         g88<4,4,1>F     g66<4,4,1>F     g2<4,4,1>F { align16 2H compacted };
>add(16)         g66<1>D         g82<8,8,1>D     48D             { align1 2H };
>send(16)        g2<1>UW         g66<0,1,0>UD    0x04847001
>                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 2H };
>add(16)         g66<1>F         g78<8,8,1>F     g8<8,8,1>F      { align1 2H };
>add(16)         g88<1>F         g94<8,8,1>F     g8<8,8,1>F      { align1 2H };
>add(16)         g102<1>F        g84<8,8,1>F     g6<8,8,1>F      { align1 2H };
>add(16)         g78<1>F         g100<8,8,1>F    g8<8,8,1>F      { align1 2H };
>add(16)         g84<1>F         g76<8,8,1>F     g4<8,8,1>F      { align1 2H };
>math inv(16)    g82<1>F         g66<8,8,1>F     null<8,8,1>F    { align1 2H };
>add(16)         g76<1>F         g70<8,8,1>F     g2<8,8,1>F      { align1 2H };
>math inv(16)    g94<1>F         g88<8,8,1>F     null<8,8,1>F    { align1 2H };
>math inv(16)    g90<1>F         g78<8,8,1>F     null<8,8,1>F    { align1 2H };
>mul(16)         g100<1>F        g102<8,8,1>F    g82<8,8,1>F     { align1 2H };
>mul(16)         g70<1>F         g76<8,8,1>F     g82<8,8,1>F     { align1 2H };
>mul(16)         g102<1>F        g84<8,8,1>F     g82<8,8,1>F     { align1 2H };
>add(16)         g82<1>F         g86<8,8,1>F     g6<8,8,1>F      { align1 2H };
>cmp.g.f0(16)    null<1>F        g100<8,8,1>F    0x3f800000F  /* 1F */ { align1 2H };
>mul(16)         g86<1>F         g82<8,8,1>F     g90<8,8,1>F     { align1 2H };
>add(16)         g82<1>F         g80<8,8,1>F     g4<8,8,1>F      { align1 2H };
>add(16)         g80<1>F         g68<8,8,1>F     g2<8,8,1>F      { align1 2H };
>mul(16)         g104<1>F        g82<8,8,1>F     g90<8,8,1>F     { align1 2H };
>mul(16)         g68<1>F         g80<8,8,1>F     g90<8,8,1>F     { align1 2H };
>add(16)         g90<1>F         g40<8,8,1>F     g6<8,8,1>F      { align1 2H };
>mul(16)         g40<1>F         g90<8,8,1>F     g94<8,8,1>F     { align1 2H };
>add(16)         g90<1>F         g38<8,8,1>F     g4<8,8,1>F      { align1 2H };
>add(16)         g38<1>F         g92<8,8,1>F     g2<8,8,1>F      { align1 2H };
>mul(16)         g4<1>F          g90<8,8,1>F     g94<8,8,1>F     { align1 2H };
>mul(16)         g2<1>F          g38<8,8,1>F     g94<8,8,1>F     { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B5 ->B6 ->B7
>   START B6 <-B5 (10 cycles)
>cmp.g.f0(16)    g8<1>F          g58<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>cmp.g.f0(16)    g6<1>F          g40<8,8,1>F     0x3f800000F  /* 1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B6 ->B8
>   START B7 <-B5 (8 cycles)
>mov(16)         g8<1>UD         0x00000000UD                    { align1 1H compacted };
>mov(16)         g6<1>D          0D                              { align1 2H };
>   END B7 ->B8
>   START B8 <-B7 <-B6 (26 cycles)
>endif(32)       JIP: 3232                                       { align1 };
>mov.nz.f0(16)   null<1>D        g8<8,8,1>D                      { align1 1H };
>mov.nz.f0(16)   null<1>D        g6<8,8,1>D                      { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B8 ->B9 ->B10
>   START B9 <-B8 (10 cycles)
>cmp.g.f0(16)    g8<1>F          g64<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>cmp.g.f0(16)    g6<1>F          g86<8,8,1>F     0x3f800000F  /* 1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B9 ->B11
>   START B10 <-B8 (8 cycles)
>mov(16)         g8<1>UD         0x00000000UD                    { align1 1H compacted };
>mov(16)         g6<1>D          0D                              { align1 2H };
>   END B10 ->B11
>   START B11 <-B10 <-B9 (26 cycles)
>endif(32)       JIP: 3096                                       { align1 };
>not.nz.f0(16)   null<1>D        g8<8,8,1>D                      { align1 1H };
>not.nz.f0(16)   null<1>D        g6<8,8,1>D                      { align1 2H };
>(+f0) if(32)    JIP: 56         UIP: 80                         { align1 };
>   END B11 ->B12 ->B13
>   START B12 <-B11 (10 cycles)
>cmp.l.f0(16)    g92<1>F         g56<8,8,1>F     0x0F  /* 0F */  { align1 1H compacted };
>cmp.l.f0(16)    g56<1>F         g100<8,8,1>F    0x0F  /* 0F */  { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B12 ->B14
>   START B13 <-B11 (8 cycles)
>mov(16)         g92<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g56<1>D         0D                              { align1 2H };
>   END B13 ->B14
>   START B14 <-B13 <-B12 (26 cycles)
>endif(32)       JIP: 2968                                       { align1 };
>mov.nz.f0(16)   null<1>D        g92<8,8,1>D                     { align1 1H };
>mov.nz.f0(16)   null<1>D        g56<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 56         UIP: 80                         { align1 };
>   END B14 ->B15 ->B16
>   START B15 <-B14 (10 cycles)
>cmp.l.f0(16)    g56<1>F         g58<8,8,1>F     0x0F  /* 0F */  { align1 1H compacted };
>cmp.l.f0(16)    g58<1>F         g40<8,8,1>F     0x0F  /* 0F */  { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B15 ->B17
>   START B16 <-B14 (8 cycles)
>mov(16)         g56<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g58<1>D         0D                              { align1 2H };
>   END B16 ->B17
>   START B17 <-B16 <-B15 (26 cycles)
>endif(32)       JIP: 2840                                       { align1 };
>mov.nz.f0(16)   null<1>D        g56<8,8,1>D                     { align1 1H };
>mov.nz.f0(16)   null<1>D        g58<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 56         UIP: 80                         { align1 };
>   END B17 ->B18 ->B19
>   START B18 <-B17 (10 cycles)
>cmp.l.f0(16)    g56<1>F         g64<8,8,1>F     0x0F  /* 0F */  { align1 1H compacted };
>cmp.l.f0(16)    g58<1>F         g86<8,8,1>F     0x0F  /* 0F */  { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B18 ->B20
>   START B19 <-B17 (8 cycles)
>mov(16)         g56<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g58<1>D         0D                              { align1 2H };
>   END B19 ->B20
>   START B20 <-B19 <-B18 (66 cycles)
>endif(32)       JIP: 2712                                       { align1 };
>cmp.nz.f0(16)   null<1>D        g56<8,8,1>D     0D              { align1 1H compacted };
>cmp.nz.f0(16)   null<1>D        g58<8,8,1>D     0D              { align1 2H };
>(-f0) sel(16)   g56<1>UD        g6<8,8,1>UD     0xffffffffUD    { align1 2H };
>(-f0) sel(16)   g6<1>UD         g8<8,8,1>UD     0xffffffffUD    { align1 1H };
>not.nz.f0(16)   null<1>D        g56<8,8,1>D                     { align1 2H };
>not.nz.f0(16)   null<1>D        g6<8,8,1>D                      { align1 1H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B20 ->B21 ->B22
>   START B21 <-B20 (10 cycles)
>cmp.l.f0(16)    g58<1>F         g52<8,8,1>F     0xbf800000F  /* -1F */ { align1 1H };
>cmp.l.f0(16)    g8<1>F          g70<8,8,1>F     0xbf800000F  /* -1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B21 ->B23
>   START B22 <-B20 (8 cycles)
>mov(16)         g58<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g8<1>D          0D                              { align1 2H };
>   END B22 ->B23
>   START B23 <-B22 <-B21 (26 cycles)
>endif(32)       JIP: 2520                                       { align1 };
>mov.nz.f0(16)   null<1>D        g58<8,8,1>D                     { align1 1H };
>mov.nz.f0(16)   null<1>D        g8<8,8,1>D                      { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B23 ->B24 ->B25
>   START B24 <-B23 (10 cycles)
>cmp.l.f0(16)    g58<1>F         g46<8,8,1>F     0xbf800000F  /* -1F */ { align1 1H };
>cmp.l.f0(16)    g8<1>F          g2<8,8,1>F      0xbf800000F  /* -1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B24 ->B26
>   START B25 <-B23 (8 cycles)
>mov(16)         g58<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g8<1>D          0D                              { align1 2H };
>   END B25 ->B26
>   START B26 <-B25 <-B24 (26 cycles)
>endif(32)       JIP: 2384                                       { align1 };
>mov.nz.f0(16)   null<1>D        g58<8,8,1>D                     { align1 1H };
>mov.nz.f0(16)   null<1>D        g8<8,8,1>D                      { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B26 ->B27 ->B28
>   START B27 <-B26 (10 cycles)
>cmp.l.f0(16)    g58<1>F         g60<8,8,1>F     0xbf800000F  /* -1F */ { align1 1H };
>cmp.l.f0(16)    g8<1>F          g68<8,8,1>F     0xbf800000F  /* -1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B27 ->B29
>   START B28 <-B26 (8 cycles)
>mov(16)         g58<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g8<1>D          0D                              { align1 2H };
>   END B28 ->B29
>   START B29 <-B28 <-B27 (66 cycles)
>endif(32)       JIP: 2248                                       { align1 };
>cmp.nz.f0(16)   null<1>D        g58<8,8,1>D     0D              { align1 1H compacted };
>cmp.nz.f0(16)   null<1>D        g8<8,8,1>D      0D              { align1 2H };
>(-f0) sel(16)   g8<1>UD         g56<8,8,1>UD    0xffffffffUD    { align1 2H };
>(-f0) sel(16)   g56<1>UD        g6<8,8,1>UD     0xffffffffUD    { align1 1H };
>not.nz.f0(16)   null<1>D        g8<8,8,1>D                      { align1 2H };
>not.nz.f0(16)   null<1>D        g56<8,8,1>D                     { align1 1H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B29 ->B30 ->B31
>   START B30 <-B29 (10 cycles)
>cmp.g.f0(16)    g6<1>F          g52<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>cmp.g.f0(16)    g52<1>F         g70<8,8,1>F     0x3f800000F  /* 1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B30 ->B32
>   START B31 <-B29 (8 cycles)
>mov(16)         g6<1>UD         0x00000000UD                    { align1 1H compacted };
>mov(16)         g52<1>D         0D                              { align1 2H };
>   END B31 ->B32
>   START B32 <-B31 <-B30 (26 cycles)
>endif(32)       JIP: 2056                                       { align1 };
>mov.nz.f0(16)   null<1>D        g6<8,8,1>D                      { align1 1H };
>mov.nz.f0(16)   null<1>D        g52<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B32 ->B33 ->B34
>   START B33 <-B32 (10 cycles)
>cmp.g.f0(16)    g106<1>F        g46<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>cmp.g.f0(16)    g6<1>F          g2<8,8,1>F      0x3f800000F  /* 1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B33 ->B35
>   START B34 <-B32 (8 cycles)
>mov(16)         g106<1>UD       0x00000000UD                    { align1 1H compacted };
>mov(16)         g6<1>D          0D                              { align1 2H };
>   END B34 ->B35
>   START B35 <-B34 <-B33 (26 cycles)
>endif(32)       JIP: 1920                                       { align1 };
>mov.nz.f0(16)   null<1>D        g106<8,8,1>D                    { align1 1H };
>mov.nz.f0(16)   null<1>D        g6<8,8,1>D                      { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B35 ->B36 ->B37
>   START B36 <-B35 (10 cycles)
>cmp.g.f0(16)    g2<1>F          g60<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>cmp.g.f0(16)    g52<1>F         g68<8,8,1>F     0x3f800000F  /* 1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B36 ->B38
>   START B37 <-B35 (8 cycles)
>mov(16)         g2<1>UD         0x00000000UD                    { align1 1H compacted };
>mov(16)         g52<1>D         0D                              { align1 2H };
>   END B37 ->B38
>   START B38 <-B37 <-B36 (62 cycles)
>endif(32)       JIP: 1784                                       { align1 };
>cmp.nz.f0(16)   null<1>D        g2<8,8,1>D      0D              { align1 1H compacted };
>cmp.nz.f0(16)   null<1>D        g52<8,8,1>D     0D              { align1 2H };
>(-f0) sel(16)   g109<1>UD       g56<8,8,1>UD    0xffffffffUD    { align1 1H };
>(-f0) sel(16)   g40<1>UD        g8<8,8,1>UD     0xffffffffUD    { align1 2H };
>not.nz.f0(16)   null<1>D        g109<8,8,1>D                    { align1 1H };
>not.nz.f0(16)   null<1>D        g40<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B38 ->B39 ->B40
>   START B39 <-B38 (10 cycles)
>cmp.l.f0(16)    g6<1>F          g54<8,8,1>F     0xbf800000F  /* -1F */ { align1 1H };
>cmp.l.f0(16)    g56<1>F         g102<8,8,1>F    0xbf800000F  /* -1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B39 ->B41
>   START B40 <-B38 (8 cycles)
>mov(16)         g6<1>UD         0x00000000UD                    { align1 1H compacted };
>mov(16)         g56<1>D         0D                              { align1 2H };
>   END B40 ->B41
>   START B41 <-B40 <-B39 (26 cycles)
>endif(32)       JIP: 1592                                       { align1 };
>mov.nz.f0(16)   null<1>D        g6<8,8,1>D                      { align1 1H };
>mov.nz.f0(16)   null<1>D        g56<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B41 ->B42 ->B43
>   START B42 <-B41 (10 cycles)
>cmp.l.f0(16)    g7<1>F          g50<8,8,1>F     0xbf800000F  /* -1F */ { align1 1H };
>cmp.l.f0(16)    g57<1>F         g4<8,8,1>F      0xbf800000F  /* -1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B42 ->B44
>   START B43 <-B41 (8 cycles)
>mov(16)         g7<1>UD         0x00000000UD                    { align1 1H compacted };
>mov(16)         g57<1>D         0D                              { align1 2H };
>   END B43 ->B44
>   START B44 <-B43 <-B42 (26 cycles)
>endif(32)       JIP: 1456                                       { align1 };
>mov.nz.f0(16)   null<1>D        g7<8,8,1>D                      { align1 1H };
>mov.nz.f0(16)   null<1>D        g57<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B44 ->B45 ->B46
>   START B45 <-B44 (10 cycles)
>cmp.l.f0(16)    g8<1>F          g62<8,8,1>F     0xbf800000F  /* -1F */ { align1 1H };
>cmp.l.f0(16)    g58<1>F         g104<8,8,1>F    0xbf800000F  /* -1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B45 ->B47
>   START B46 <-B44 (8 cycles)
>mov(16)         g8<1>UD         0x00000000UD                    { align1 1H compacted };
>mov(16)         g58<1>D         0D                              { align1 2H };
>   END B46 ->B47
>   START B47 <-B46 <-B45 (62 cycles)
>endif(32)       JIP: 1320                                       { align1 };
>cmp.nz.f0(16)   null<1>D        g8<8,8,1>D      0D              { align1 1H compacted };
>cmp.nz.f0(16)   null<1>D        g58<8,8,1>D     0D              { align1 2H };
>(-f0) sel(16)   g111<1>UD       g109<8,8,1>UD   0xffffffffUD    { align1 1H };
>(-f0) sel(16)   g100<1>UD       g40<8,8,1>UD    0xffffffffUD    { align1 2H };
>not.nz.f0(16)   null<1>D        g111<8,8,1>D                    { align1 1H };
>not.nz.f0(16)   null<1>D        g100<8,8,1>D                    { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B47 ->B48 ->B49
>   START B48 <-B47 (10 cycles)
>cmp.g.f0(16)    g52<1>F         g54<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>cmp.g.f0(16)    g59<1>F         g102<8,8,1>F    0x3f800000F  /* 1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B48 ->B50
>   START B49 <-B47 (8 cycles)
>mov(16)         g52<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g59<1>D         0D                              { align1 2H };
>   END B49 ->B50
>   START B50 <-B49 <-B48 (26 cycles)
>endif(32)       JIP: 1128                                       { align1 };
>mov.nz.f0(16)   null<1>D        g52<8,8,1>D                     { align1 1H };
>mov.nz.f0(16)   null<1>D        g59<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B50 ->B51 ->B52
>   START B51 <-B50 (10 cycles)
>cmp.g.f0(16)    g53<1>F         g50<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>cmp.g.f0(16)    g60<1>F         g4<8,8,1>F      0x3f800000F  /* 1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B51 ->B53
>   START B52 <-B50 (8 cycles)
>mov(16)         g53<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g60<1>D         0D                              { align1 2H };
>   END B52 ->B53
>   START B53 <-B52 <-B51 (26 cycles)
>endif(32)       JIP: 992                                        { align1 };
>mov.nz.f0(16)   null<1>D        g53<8,8,1>D                     { align1 1H };
>mov.nz.f0(16)   null<1>D        g60<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 64         UIP: 88                         { align1 };
>   END B53 ->B54 ->B55
>   START B54 <-B53 (10 cycles)
>cmp.g.f0(16)    g54<1>F         g62<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
>cmp.g.f0(16)    g61<1>F         g104<8,8,1>F    0x3f800000F  /* 1F */ { align1 2H };
>else(32)        JIP: 40         UIP: 40                         { align1 };
>   END B54 ->B56
>   START B55 <-B53 (8 cycles)
>mov(16)         g54<1>UD        0x00000000UD                    { align1 1H compacted };
>mov(16)         g61<1>D         0D                              { align1 2H };
>   END B55 ->B56
>   START B56 <-B55 <-B54 (62 cycles)
>endif(32)       JIP: 856                                        { align1 };
>cmp.nz.f0(16)   null<1>D        g54<8,8,1>D     0D              { align1 1H compacted };
>cmp.nz.f0(16)   null<1>D        g61<8,8,1>D     0D              { align1 2H };
>(-f0) sel(16)   g107<1>UD       g111<8,8,1>UD   0xffffffffUD    { align1 1H };
>(-f0) sel(16)   g62<1>UD        g100<8,8,1>UD   0xffffffffUD    { align1 2H };
>not.nz.f0(16)   null<1>D        g107<8,8,1>D                    { align1 1H };
>not.nz.f0(16)   null<1>D        g62<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 352        UIP: 352                        { align1 };
>   END B56 ->B57 ->B58
>   START B57 <-B56 (252 cycles)
>mul(16)         g126<1>F        g98<8,8,1>F     g74<8,8,1>F     { align1 1H compacted };
>mul(16)         g122<1>F        g38<8,8,1>F     g78<8,8,1>F     { align1 2H };
>mul(16)         g2<1>F          g42<8,8,1>F     g72<8,8,1>F     { align1 1H compacted };
>mul(16)         g117<1>F        g90<8,8,1>F     g78<8,8,1>F     { align1 2H };
>mul(16)         g119<1>F        g88<8,8,1>F     g80<8,8,1>F     { align1 2H };
>mul(16)         g7<1>F          g36<8,8,1>F     g126<8,8,1>F    { align1 1H compacted };
>mul(16)         g125<1>F        g84<8,8,1>F     g122<8,8,1>F    { align1 2H };
>mul(16)         g121<1>F        g42<8,8,1>F     g74<8,8,1>F     { align1 1H compacted };
>mul(16)         g123<1>F        g90<8,8,1>F     g80<8,8,1>F     { align1 2H };
>mul(16)         g42<1>F         g96<8,8,1>F     g2<8,8,1>F      { align1 1H compacted };
>mad(16)         g4<1>F          -g125<4,4,1>F   g119<4,4,1>F    g84<4,4,1>F { align16 2H compacted };
>mul(16)         g2<1>F          g66<8,8,1>F     g123<8,8,1>F    { align1 2H };
>mul(16)         g123<1>F        g44<8,8,1>F     g72<8,8,1>F     { align1 1H compacted };
>mad(16)         g72<1>F         -g7<4,4,1>F     g123<4,4,1>F    g36<4,4,1>F { align16 1H compacted };
>mul(16)         g124<1>F        g98<8,8,1>F     g48<8,8,1>F     { align1 1H compacted };
>mad(16)         g74<1>F         -g42<4,4,1>F    g124<4,4,1>F    g96<4,4,1>F { align16 1H compacted };
>mul(16)         g125<1>F        g44<8,8,1>F     g48<8,8,1>F     { align1 1H compacted };
>mul(16)         g6<1>F          g34<8,8,1>F     g125<8,8,1>F    { align1 1H compacted };
>add(16)         g52<1>F         g72<8,8,1>F     g74<8,8,1>F     { align1 1H compacted };
>mad(16)         g43<1>F         -g6<4,4,1>F     g121<4,4,1>F    g34<4,4,1>F { align16 1H compacted };
>mul(16)         g120<1>F        g38<8,8,1>F     g82<8,8,1>F     { align1 2H };
>mad(16)         g6<1>F          -g2<4,4,1>F     g120<4,4,1>F    g66<4,4,1>F { align16 2H compacted };
>add(16)         g54<1>F         g43<8,8,1>F     g52<8,8,1>F     { align1 1H compacted };
>mul(16)         g121<1>F        g88<8,8,1>F     g82<8,8,1>F     { align1 2H };
>cmp.g.f0(16)    g107<1>F        g54<8,8,1>F     0x0F  /* 0F */  { align1 1H compacted };
>add(16)         g8<1>F          g4<8,8,1>F      g6<8,8,1>F      { align1 2H };
>mul(16)         g124<1>F        g76<8,8,1>F     g121<8,8,1>F    { align1 2H };
>mad(16)         g3<1>F          -g124<4,4,1>F   g117<4,4,1>F    g76<4,4,1>F { align16 2H compacted };
>add(16)         g34<1>F         g3<8,8,1>F      g8<8,8,1>F      { align1 2H };
>cmp.g.f0(16)    g62<1>F         g34<8,8,1>F     0x0F  /* 0F */  { align1 2H };
>   END B57 ->B58
>   START B58 <-B56 <-B57 (62 cycles)
>endif(32)       JIP: 400                                        { align1 };
>mov(8)          g2<1>UD         0x00000000UD                    { align1 WE_all 1Q compacted };
>and(1)          g2.2<1>UD       g0.2<0,1,0>UD   0x8f000000UD    { align1 WE_all 1N };
>send(32)        null<1>UW       g2<0,1,0>UD     0x02008004
>                            gateway MsgDesc: (barrier msg) mlen 1 rlen 0    { align1 WE_all };
>wait(1)                         n0<0,1,0>UD                     { align1 WE_all 1N };
>send(1)         g2<1>UW         g2<0,1,0>UW     0x0209c000
>                            data MsgDesc: ( DC mfence, 0, 0) mlen 1 rlen 0  { align1 WE_all 1N };
>not.nz.f0(16)   null<1>D        g107<8,8,1>D                    { align1 1H };
>not.nz.f0(16)   null<1>D        g62<8,8,1>D                     { align1 2H };
>(+f0) if(32)    JIP: 264        UIP: 264                        { align1 };
>   END B58 ->B59 ->B60
>   START B59 <-B58 (14126 cycles)
>mul(16)         g34<1>D         g1.1<0,1,0>D    20D             { align1 1H compacted };
>mul(16)         g96<1>D         g1.1<0,1,0>D    20D             { align1 2H };
>mov(16)         g36<1>UD        0x00000003UD                    { align1 1H compacted };
>send(16)        g56<1>UW        g34<8,8,1>UD    0x0820a702
>                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, add) mlen 4 rlen 2 { align1 1H };
>mov(16)         g98<1>UD        0x00000003UD                    { align1 2H };
>send(16)        g4<1>UW         g96<8,8,1>UD    0x0820a702
>                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, add) mlen 4 rlen 2 { align1 2H };
>mul(16)         g10<1>D         g56<8,8,1>D     12D             { align1 1H compacted };
>mul(16)         g14<1>D         g4<8,8,1>D      12D             { align1 2H };
>send(16)        null<1>UW       g10<8,8,1>UD    0x08025e05
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 5, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>send(16)        null<1>UW       g14<8,8,1>UD    0x08025e05
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 5, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>add(16)         g18<1>D         g10<8,8,1>D     4D              { align1 1H compacted };
>add(16)         g22<1>D         g14<8,8,1>D     4D              { align1 2H };
>send(16)        null<1>UW       g18<8,8,1>UD    0x08025e05
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 5, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>send(16)        null<1>UW       g22<8,8,1>UD    0x08025e05
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 5, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>add(16)         g26<1>D         g10<8,8,1>D     8D              { align1 1H compacted };
>add(16)         g30<1>D         g14<8,8,1>D     8D              { align1 2H };
>send(16)        null<1>UW       g26<8,8,1>UD    0x08025e05
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 5, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
>send(16)        null<1>UW       g30<8,8,1>UD    0x08025e05
>                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 5, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 2H };
>   END B59 ->B60
>   START B60 <-B58 <-B59 (2 cycles)
>endif(32)       JIP: 16                                         { align1 };
>   END B60 ->B61
>   START B61 <-B4 <-B60 (20 cycles)
>endif(32)       JIP: 16                                         { align1 };
>mov(8)          g127<1>UD       g0<8,8,1>UD                     { align1 WE_all 1Q compacted };
>send(32)        null<1>UW       g127<8,8,1>UW   0x82000010
>                            thread_spawner MsgDesc: mlen 1 rlen 0           { align1 WE_all EOT };
>   END B61
>

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Attachments on bug 108820: 142952 | 143046 | 143047 | 143060 | 143061 | 143062 | 143303 | 143305 | 143739

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