Attachment 143526 Details for Bug 104054 – Experiment 2. Crop link rate to 270000

[patch] Experiment 2. Crop link rate to 270000

0001-Bug-104054-Experiment-2.-Crop-link-rate-to-270000.patch (text/plain), 3.57 KB, created by Rodrigo Vivi on 2019-03-05 00:59:58 UTC

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Creator: Rodrigo Vivi

Created: 2019-03-05 00:59:58 UTC

Size: 3.57 KB

patch

obsolete

>From 217a48e90d726b48abfbd50d9dc19ec695582366 Mon Sep 17 00:00:00 2001
>From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Date: Mon, 4 Mar 2019 16:52:57 -0800
>Subject: [PATCH] Bug 104054: Experiment 2. Crop link rate to 270000
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_dp.c | 23 ++++++++++-------------
> 1 file changed, 10 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index e1a051c0fbfe..6687a1620973 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -324,7 +324,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> 		162000, 216000, 243000, 270000, 324000, 432000, 540000
> 	};
> 	static const int skl_rates[] = {
>-		162000, 216000, 270000, 324000, 432000, 540000
>+		162000, 270000
> 	};
> 	static const int hsw_rates[] = {
> 		162000, 270000, 540000
>@@ -949,8 +949,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> 	regs->pp_stat = PP_STATUS(pps_idx);
> 	regs->pp_on = PP_ON_DELAYS(pps_idx);
> 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
>-	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
>-	    !HAS_PCH_ICP(dev_priv))
>+	if (INTEL_PCH_TYPE(dev_priv) > PCH_NONE &&
>+	    INTEL_PCH_TYPE(dev_priv) < PCH_CNP)
> 		regs->pp_div = PP_DIVISOR(pps_idx);
> }
> 
>@@ -6431,8 +6431,8 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
> 
> 	pp_on = I915_READ(regs.pp_on);
> 	pp_off = I915_READ(regs.pp_off);
>-	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
>-	    !HAS_PCH_ICP(dev_priv)) {
>+	if (INTEL_PCH_TYPE(dev_priv) > PCH_NONE &&
>+	    INTEL_PCH_TYPE(dev_priv) < PCH_CNP) {
> 		I915_WRITE(regs.pp_ctrl, pp_ctl);
> 		pp_div = I915_READ(regs.pp_div);
> 	}
>@@ -6450,8 +6450,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
> 	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> 		   PANEL_POWER_DOWN_DELAY_SHIFT;
> 
>-	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>-	    HAS_PCH_ICP(dev_priv)) {
>+	if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) {
> 		seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> 				BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
> 	} else {
>@@ -6622,8 +6621,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> 		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> 	/* Compute the divisor for the pp clock, simply match the Bspec
> 	 * formula. */
>-	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>-	    HAS_PCH_ICP(dev_priv)) {
>+	if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) {
> 		pp_div = I915_READ(regs.pp_ctrl);
> 		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> 		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
>@@ -6659,8 +6657,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> 
> 	I915_WRITE(regs.pp_on, pp_on);
> 	I915_WRITE(regs.pp_off, pp_off);
>-	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>-	    HAS_PCH_ICP(dev_priv))
>+	if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> 		I915_WRITE(regs.pp_ctrl, pp_div);
> 	else
> 		I915_WRITE(regs.pp_div, pp_div);
>@@ -6668,8 +6665,8 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> 	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> 		      I915_READ(regs.pp_on),
> 		      I915_READ(regs.pp_off),
>-		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
>-		       HAS_PCH_ICP(dev_priv)) ?
>+		      (IS_GEN9_LP(dev_priv) ||
>+		       INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) ?
> 		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> 		      I915_READ(regs.pp_div));
> }
>-- 
>2.20.1
>

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