Attachment 143703 Details for Bug 110135 – i965: make sure to have cs stall before vf cache invalidate

[patch] i965: make sure to have cs stall before vf cache invalidate

0001-i965-make-sure-to-have-cs-stall-before-vf-cache-inva.patch (text/plain), 2.42 KB, created by Lionel Landwerlin on 2019-03-17 11:57:04 UTC

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Creator: Lionel Landwerlin

Created: 2019-03-17 11:57:04 UTC

Size: 2.42 KB

patch

obsolete

>From 9f66e6e584a9480aa7168ce5cc4f87f102143dba Mon Sep 17 00:00:00 2001
>From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Date: Sat, 16 Mar 2019 22:54:32 +0000
>Subject: [PATCH] i965: make sure to have cs stall before vf cache invalidate
>
>The error state of bug 110135 shows that cs stall is in the same pipe
>control as vf cache invalidate. But we use cs stall as a top of the
>pipe flush meaning that it is an operation that does no complete
>immediately, unlike the vf cache invalidate. This means that vf cache
>invalidate might complete before the vf operations have completed,
>leaving the cache still containing stale entries.
>
>We also apply the 31e4c9ce400341 workaround to the index buffer.
>
>Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110135
>Fixes: 31e4c9ce400341 ("i965: add CS stall on VF invalidation workaround")
>---
> src/mesa/drivers/dri/i965/brw_pipe_control.h  | 5 ++++-
> src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
>diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.h b/src/mesa/drivers/dri/i965/brw_pipe_control.h
>index e213f43a4f7..f4145b81d0f 100644
>--- a/src/mesa/drivers/dri/i965/brw_pipe_control.h
>+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.h
>@@ -65,8 +65,11 @@ enum pipe_control_flags
>    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
> };
> 
>+/* We consider CS_STALL as top of the pipe flush. */
> #define PIPE_CONTROL_CACHE_FLUSH_BITS \
>-   (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \
>+   (PIPE_CONTROL_CS_STALL | \
>+    PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
>+    PIPE_CONTROL_DATA_CACHE_FLUSH | \
>     PIPE_CONTROL_RENDER_TARGET_FLUSH)
> 
> #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
>diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
>index e904c4c0cf9..0aab68861c3 100644
>--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
>+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
>@@ -454,7 +454,7 @@ vf_invalidate_for_ib_48bit_transition(struct brw_context *brw)
>    uint16_t high_bits = pinned_bo_high_bits(brw->ib.bo);
> 
>    if (high_bits != brw->ib.last_bo_high_bits) {
>-      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE);
>+      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL);
>       brw->ib.last_bo_high_bits = high_bits;
>    }
> #endif
>-- 
>2.20.1
>

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Attachments on bug 110135: 143685 | 143686 | 143703 | 143741 | 143758 | 143942 | 143943 | 144324

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