Attachment 143865 Details for Bug 109959 – *really* corrected rediffed 5.0.6 patch

[patch] *really* corrected rediffed 5.0.6 patch

kernel-5.0-edp-max-lane-count.patch (text/plain), 4.48 KB, created by Adam Williamson on 2019-04-04 23:46:16 UTC

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Creator: Adam Williamson

Created: 2019-04-04 23:46:16 UTC

Size: 4.48 KB

patch

obsolete

>From 818c68a8396ccf1c486d4208471b993d375b7ebd Mon Sep 17 00:00:00 2001
>From: Mark Weiman <mark.weiman@markzz.com>
>Date: Thu, 4 Apr 2019 11:40:46 -0400
>Subject: [PATCH] Certain eDP panels fail to link train with optimized settings
> for link rate and lane count and need the max link parameters to be used for
> link training to pass. So in on link training failure for eDP, retry the link
> training with max link parameters first since this tends to fix link failures
> on most eDP 1.4 panels
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>v2:
>* Forgot to ammend the previous patch with the fixes. This is
>a clean fixed patch
>
>Suggested-by: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>Cc: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>Cc: Albert Astals Cid <aacid@kde.org>
>Cc: Emanuele Panigati <ilpanich@gmail.com>
>Cc: Ralgor <ralgorfdb@compuspex.org>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959
>Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
>Signed-off-by: Mark Weiman <mark.weiman@markzz.com>
>---
> drivers/gpu/drm/i915/intel_dp.c  | 45 +++++++++++++++++++++++---------
> drivers/gpu/drm/i915/intel_drv.h |  3 +++
> 2 files changed, 35 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index 22a74608c6e4..48dc25711713 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -464,6 +464,14 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
> 	return true;
> }
> 
>+static bool intel_dp_uses_max_link_params(struct intel_dp *intel_dp,
>+					  int link_rate,
>+					  u8 lane_count)
>+{
>+	return link_rate == intel_dp->max_link_rate &&
>+		lane_count == intel_dp->max_link_lane_count;
>+}
>+
> int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> 					    int link_rate, uint8_t lane_count)
> {
>@@ -472,24 +488,24 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> 	index = intel_dp_rate_index(intel_dp->common_rates,
> 				    intel_dp->num_common_rates,
> 				    link_rate);
>-	if (index > 0) {
>-		if (intel_dp_is_edp(intel_dp) &&
>-		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
>-							      intel_dp->common_rates[index - 1],
>-							      lane_count)) {
>+
>+	if (intel_dp_is_edp(intel_dp)) {
>+		if (!intel_dp_uses_max_link_params(intel_dp, link_rate,
>+						   lane_count)) {
>+			intel_dp->retry_with_max_link_params = true;
>+			DRM_DEBUG_KMS("Retrying Link training for eDP with max link parameters\n");
>+			return 0;
>+		} else if (!intel_dp_can_link_train_fallback_for_edp(intel_dp,
>+								     intel_dp->common_rates[index - 1],
>+								     lane_count)) {
> 			DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
> 			return 0;
> 		}
>+	}
>+	if (index > 0) {
> 		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
> 		intel_dp->max_link_lane_count = lane_count;
> 	} else if (lane_count > 1) {
>-		if (intel_dp_is_edp(intel_dp) &&
>-		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
>-							      intel_dp_max_common_rate(intel_dp),
>-							      lane_count >> 1)) {
>-			DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
>-			return 0;
>-		}
> 		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> 		intel_dp->max_link_lane_count = lane_count >> 1;
> 	} else {
>@@ -2013,7 +2029,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> 	limits.min_bpp = 6 * 3;
> 	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
> 
>-	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
>+	if ((intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) ||
>+	    intel_dp->retry_with_max_link_params) {
> 		/*
> 		 * Use the maximum clock and number of lanes the eDP panel
> 		 * advertizes being capable of. The eDP 1.3 and earlier panels
>@@ -5345,6 +5362,8 @@ intel_dp_detect(struct drm_connector *connector,
> 		/* Initial max link rate */
> 		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> 
>+		intel_dp->retry_with_max_link_params = false;
>+
> 		intel_dp->reset_link_params = false;
> 	}
> 
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index e9ddeaf05a14..ae6c6aa28595 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -1219,6 +1219,9 @@ struct intel_dp {
> 
> 	/* Displayport compliance testing */
> 	struct intel_dp_compliance compliance;
>+
>+	/* Some panels need max link params for link training */
>+	bool retry_with_max_link_params;
> };
> 
> enum lspcon_vendor {
>-- 
>2.21.0
>

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Attachments on bug 109959: 143621 | 143624 | 143729 | 143776 | 143782 | 143783 | 143791 | 143792 | 143793 | 143794 | 143795 | 143796 | 143797 | 143801 | 143817 | 143862 | 143865 | 143874 | 143967 | 143987 | 143988 | 143990 | 143993 | 144000 | 144002

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