Attachment 144444 Details for Bug 108773 – [PATCH] drm/i915: Do not touch the PCH SSC reference if a PLL is using it

[patch] [PATCH] drm/i915: Do not touch the PCH SSC reference if a PLL is using it

0001-drm-i915-Do-not-touch-the-PCH-SSC-reference-if-a-PLL.patch (text/plain), 4.45 KB, created by Ville Syrjala on 2019-06-04 16:54:21 UTC

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Creator: Ville Syrjala

Created: 2019-06-04 16:54:21 UTC

Size: 4.45 KB

patch

obsolete

>From 020c1b5a20fa94338a9fbc156c5b6babd5b2ae4b Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
>Date: Tue, 4 Jun 2019 17:48:57 +0300
>Subject: [PATCH] drm/i915: Do not touch the PCH SSC reference if a PLL is
> using it
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>Our PCH refclk init code currently assumes that the PCH SSC reference
>can only be used for FDI. That is not true and it can be used by
>SPLL/WRPLL for eDP SSC or clock bending as well. Before we go
>reconfiguring it let's make sure no PLL is currently using the PCH
>SSC reference.
>
>This will mean that we won't reconfigure the PCH SSC reference
>properly for FDI in case the BIOS has decided to use it for eg.
>clock bending. But hopefully that won't happen in practive.
>
>We really should move this code to be part of the modeset seqeuence
>and properly deal with the potentially conflicting requirements
>imposed on PLL reference clocks. But that requires actual work.
>
>Signed-off-by: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h      |  1 +
> drivers/gpu/drm/i915/intel_display.c | 79 ++++++++++++++++++++++++++--
> 2 files changed, 77 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 07e3f861a92e..d5fee72fc079 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7511,6 +7511,7 @@ enum {
> #define  ILK_eDP_A_DISABLE		(1 << 24)
> #define  HSW_CDCLK_LIMIT		(1 << 24)
> #define  ILK_DESKTOP			(1 << 23)
>+#define  HSW_CPU_SSC_ENABLE		(1 << 21)
> 
> #define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
> #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index fc47ed0247c5..75ca2030ffb0 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -9121,22 +9121,95 @@ static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
> 
> #undef BEND_IDX
> 
>+static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
>+{
>+	u32 fuse_strap = I915_READ(FUSE_STRAP);
>+	u32 ctl = I915_READ(SPLL_CTL);
>+
>+	if ((ctl & SPLL_PLL_ENABLE) == 0)
>+		return false;
>+
>+	if ((ctl & SPLL_PLL_REF_MASK) == SPLL_PLL_SSC &&
>+	    (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
>+		return true;
>+
>+	if (IS_BROADWELL(dev_priv) &&
>+	    (ctl & SPLL_PLL_REF_MASK) == SPLL_PLL_NON_SSC)
>+		return true;
>+
>+	return false;
>+}
>+
>+static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
>+			       enum intel_dpll_id id)
>+{
>+	u32 fuse_strap = I915_READ(FUSE_STRAP);
>+	u32 ctl = I915_READ(WRPLL_CTL(id));
>+
>+	if ((ctl & WRPLL_PLL_ENABLE) == 0)
>+		return false;
>+
>+	if ((ctl & WRPLL_PLL_REF_MASK) == WRPLL_PLL_SSC)
>+		return true;
>+
>+	if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
>+	    (ctl & WRPLL_PLL_REF_MASK) == WRPLL_PLL_NON_SSC &&
>+	    (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
>+		return true;
>+
>+	return false;
>+}
>+
> static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
> {
> 	struct intel_encoder *encoder;
>-	bool has_vga = false;
>+	bool pch_ssc_in_use = false;
>+	bool has_fdi = false;
> 
> 	for_each_intel_encoder(&dev_priv->drm, encoder) {
> 		switch (encoder->type) {
> 		case INTEL_OUTPUT_ANALOG:
>-			has_vga = true;
>+			has_fdi = true;
> 			break;
> 		default:
> 			break;
> 		}
> 	}
> 
>-	if (has_vga) {
>+	/*
>+	 * The BIOS may have decided to use the PCH SSC
>+	 * reference so we must not disable it until the
>+	 * relevant PLLs have stopped relying on it. We'll
>+	 * just leave the PCH SSC reference enabled in case
>+	 * any active PLL is using it. It will get disabled
>+	 * after runtime suspend if we don't have FDI.
>+	 *
>+	 * TODO: Move the whole reference clock handling
>+	 * to the modeset sequence proper so that we can
>+	 * actually enable/disable/reconfigure these things
>+	 * safely. To do that we need to introduce a real
>+	 * clock hierarchy. That would also allow us to do
>+	 * clock bending finally.
>+	 */
>+	if (spll_uses_pch_ssc(dev_priv)) {
>+		DRM_DEBUG_KMS("SPLL using PCH SSC\n");
>+		pch_ssc_in_use = true;
>+	}
>+
>+	if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
>+		DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
>+		pch_ssc_in_use = true;
>+	}
>+
>+	if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
>+		DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
>+		pch_ssc_in_use = true;
>+	}
>+
>+	if (pch_ssc_in_use)
>+		return;
>+
>+	if (has_fdi) {
> 		lpt_bend_clkout_dp(dev_priv, 0);
> 		lpt_enable_clkout_dp(dev_priv, true, true);
> 	} else {
>-- 
>2.21.0
>

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Attachments on bug 108773: 142523 | 142648 | 142659 | 144306 | 144307 | 144308 | 144309 | 144310 | 144328 | 144329 | 144444 | 144452

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