Bugzilla – Attachment 145225 Details for
Bug 111481
AMD Navi GPU frequent freezes on both Manjaro/Ubuntu with kernel 5.3 and mesa 19.2 -git/llvm9
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Merge last adg5f code
merge_last_amdgpu-for-5.3-rc6.patch (text/plain), 22.82 MB, created by
Mathieu Belanger
on 2019-08-31 22:15:36 UTC
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Description:
Merge last adg5f code
Filename:
MIME Type:
Creator:
Mathieu Belanger
Created:
2019-08-31 22:15:36 UTC
Size:
22.82 MB
patch
obsolete
>diff -Naur linux-5.3-rc6/arch/x86/kernel/early-quirks.c linux-5.3-rc6-agd5fed/arch/x86/kernel/early-quirks.c >--- linux-5.3-rc6/arch/x86/kernel/early-quirks.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/arch/x86/kernel/early-quirks.c 2019-08-31 15:01:11.825736165 -0500 >@@ -549,6 +549,7 @@ > INTEL_CNL_IDS(&gen9_early_ops), > INTEL_ICL_11_IDS(&gen11_early_ops), > INTEL_EHL_IDS(&gen11_early_ops), >+ INTEL_TGL_12_IDS(&gen11_early_ops), > }; > > struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); >diff -Naur linux-5.3-rc6/.clang-format linux-5.3-rc6-agd5fed/.clang-format >--- linux-5.3-rc6/.clang-format 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/.clang-format 1969-12-31 18:00:00.000000000 -0600 >@@ -1,493 +0,0 @@ >-# SPDX-License-Identifier: GPL-2.0 >-# >-# clang-format configuration file. Intended for clang-format >= 4. >-# >-# For more information, see: >-# >-# Documentation/process/clang-format.rst >-# https://clang.llvm.org/docs/ClangFormat.html >-# https://clang.llvm.org/docs/ClangFormatStyleOptions.html >-# >---- >-AccessModifierOffset: -4 >-AlignAfterOpenBracket: Align >-AlignConsecutiveAssignments: false >-AlignConsecutiveDeclarations: false >-#AlignEscapedNewlines: Left # Unknown to clang-format-4.0 >-AlignOperands: true >-AlignTrailingComments: false >-AllowAllParametersOfDeclarationOnNextLine: false >-AllowShortBlocksOnASingleLine: false >-AllowShortCaseLabelsOnASingleLine: false >-AllowShortFunctionsOnASingleLine: None >-AllowShortIfStatementsOnASingleLine: false >-AllowShortLoopsOnASingleLine: false >-AlwaysBreakAfterDefinitionReturnType: None >-AlwaysBreakAfterReturnType: None >-AlwaysBreakBeforeMultilineStrings: false >-AlwaysBreakTemplateDeclarations: false >-BinPackArguments: true >-BinPackParameters: true >-BraceWrapping: >- AfterClass: false >- AfterControlStatement: false >- AfterEnum: false >- AfterFunction: true >- AfterNamespace: true >- AfterObjCDeclaration: false >- AfterStruct: false >- AfterUnion: false >- #AfterExternBlock: false # Unknown to clang-format-5.0 >- BeforeCatch: false >- BeforeElse: false >- IndentBraces: false >- #SplitEmptyFunction: true # Unknown to clang-format-4.0 >- #SplitEmptyRecord: true # Unknown to clang-format-4.0 >- #SplitEmptyNamespace: true # Unknown to clang-format-4.0 >-BreakBeforeBinaryOperators: None >-BreakBeforeBraces: Custom >-#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0 >-BreakBeforeTernaryOperators: false >-BreakConstructorInitializersBeforeComma: false >-#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0 >-BreakAfterJavaFieldAnnotations: false >-BreakStringLiterals: false >-ColumnLimit: 80 >-CommentPragmas: '^ IWYU pragma:' >-#CompactNamespaces: false # Unknown to clang-format-4.0 >-ConstructorInitializerAllOnOneLineOrOnePerLine: false >-ConstructorInitializerIndentWidth: 8 >-ContinuationIndentWidth: 8 >-Cpp11BracedListStyle: false >-DerivePointerAlignment: false >-DisableFormat: false >-ExperimentalAutoDetectBinPacking: false >-#FixNamespaceComments: false # Unknown to clang-format-4.0 >- >-# Taken from: >-# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \ >-# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \ >-# | sort | uniq >-ForEachMacros: >- - 'apei_estatus_for_each_section' >- - 'ata_for_each_dev' >- - 'ata_for_each_link' >- - '__ata_qc_for_each' >- - 'ata_qc_for_each' >- - 'ata_qc_for_each_raw' >- - 'ata_qc_for_each_with_internal' >- - 'ax25_for_each' >- - 'ax25_uid_for_each' >- - '__bio_for_each_bvec' >- - 'bio_for_each_bvec' >- - 'bio_for_each_integrity_vec' >- - '__bio_for_each_segment' >- - 'bio_for_each_segment' >- - 'bio_for_each_segment_all' >- - 'bio_list_for_each' >- - 'bip_for_each_vec' >- - 'blkg_for_each_descendant_post' >- - 'blkg_for_each_descendant_pre' >- - 'blk_queue_for_each_rl' >- - 'bond_for_each_slave' >- - 'bond_for_each_slave_rcu' >- - 'bpf_for_each_spilled_reg' >- - 'btree_for_each_safe128' >- - 'btree_for_each_safe32' >- - 'btree_for_each_safe64' >- - 'btree_for_each_safel' >- - 'card_for_each_dev' >- - 'cgroup_taskset_for_each' >- - 'cgroup_taskset_for_each_leader' >- - 'cpufreq_for_each_entry' >- - 'cpufreq_for_each_entry_idx' >- - 'cpufreq_for_each_valid_entry' >- - 'cpufreq_for_each_valid_entry_idx' >- - 'css_for_each_child' >- - 'css_for_each_descendant_post' >- - 'css_for_each_descendant_pre' >- - 'device_for_each_child_node' >- - 'drm_atomic_crtc_for_each_plane' >- - 'drm_atomic_crtc_state_for_each_plane' >- - 'drm_atomic_crtc_state_for_each_plane_state' >- - 'drm_atomic_for_each_plane_damage' >- - 'drm_connector_for_each_possible_encoder' >- - 'drm_for_each_connector_iter' >- - 'drm_for_each_crtc' >- - 'drm_for_each_encoder' >- - 'drm_for_each_encoder_mask' >- - 'drm_for_each_fb' >- - 'drm_for_each_legacy_plane' >- - 'drm_for_each_plane' >- - 'drm_for_each_plane_mask' >- - 'drm_for_each_privobj' >- - 'drm_mm_for_each_hole' >- - 'drm_mm_for_each_node' >- - 'drm_mm_for_each_node_in_range' >- - 'drm_mm_for_each_node_safe' >- - 'flow_action_for_each' >- - 'for_each_active_drhd_unit' >- - 'for_each_active_iommu' >- - 'for_each_available_child_of_node' >- - 'for_each_bio' >- - 'for_each_board_func_rsrc' >- - 'for_each_bvec' >- - 'for_each_card_components' >- - 'for_each_card_links' >- - 'for_each_card_links_safe' >- - 'for_each_card_prelinks' >- - 'for_each_card_rtds' >- - 'for_each_card_rtds_safe' >- - 'for_each_cgroup_storage_type' >- - 'for_each_child_of_node' >- - 'for_each_clear_bit' >- - 'for_each_clear_bit_from' >- - 'for_each_cmsghdr' >- - 'for_each_compatible_node' >- - 'for_each_component_dais' >- - 'for_each_component_dais_safe' >- - 'for_each_comp_order' >- - 'for_each_console' >- - 'for_each_cpu' >- - 'for_each_cpu_and' >- - 'for_each_cpu_not' >- - 'for_each_cpu_wrap' >- - 'for_each_dev_addr' >- - 'for_each_dma_cap_mask' >- - 'for_each_dpcm_be' >- - 'for_each_dpcm_be_rollback' >- - 'for_each_dpcm_be_safe' >- - 'for_each_dpcm_fe' >- - 'for_each_drhd_unit' >- - 'for_each_dss_dev' >- - 'for_each_efi_memory_desc' >- - 'for_each_efi_memory_desc_in_map' >- - 'for_each_element' >- - 'for_each_element_extid' >- - 'for_each_element_id' >- - 'for_each_endpoint_of_node' >- - 'for_each_evictable_lru' >- - 'for_each_fib6_node_rt_rcu' >- - 'for_each_fib6_walker_rt' >- - 'for_each_free_mem_range' >- - 'for_each_free_mem_range_reverse' >- - 'for_each_func_rsrc' >- - 'for_each_hstate' >- - 'for_each_if' >- - 'for_each_iommu' >- - 'for_each_ip_tunnel_rcu' >- - 'for_each_irq_nr' >- - 'for_each_link_codecs' >- - 'for_each_lru' >- - 'for_each_matching_node' >- - 'for_each_matching_node_and_match' >- - 'for_each_memblock' >- - 'for_each_memblock_type' >- - 'for_each_memcg_cache_index' >- - 'for_each_mem_pfn_range' >- - 'for_each_mem_range' >- - 'for_each_mem_range_rev' >- - 'for_each_migratetype_order' >- - 'for_each_msi_entry' >- - 'for_each_msi_entry_safe' >- - 'for_each_net' >- - 'for_each_netdev' >- - 'for_each_netdev_continue' >- - 'for_each_netdev_continue_rcu' >- - 'for_each_netdev_feature' >- - 'for_each_netdev_in_bond_rcu' >- - 'for_each_netdev_rcu' >- - 'for_each_netdev_reverse' >- - 'for_each_netdev_safe' >- - 'for_each_net_rcu' >- - 'for_each_new_connector_in_state' >- - 'for_each_new_crtc_in_state' >- - 'for_each_new_mst_mgr_in_state' >- - 'for_each_new_plane_in_state' >- - 'for_each_new_private_obj_in_state' >- - 'for_each_node' >- - 'for_each_node_by_name' >- - 'for_each_node_by_type' >- - 'for_each_node_mask' >- - 'for_each_node_state' >- - 'for_each_node_with_cpus' >- - 'for_each_node_with_property' >- - 'for_each_of_allnodes' >- - 'for_each_of_allnodes_from' >- - 'for_each_of_cpu_node' >- - 'for_each_of_pci_range' >- - 'for_each_old_connector_in_state' >- - 'for_each_old_crtc_in_state' >- - 'for_each_old_mst_mgr_in_state' >- - 'for_each_oldnew_connector_in_state' >- - 'for_each_oldnew_crtc_in_state' >- - 'for_each_oldnew_mst_mgr_in_state' >- - 'for_each_oldnew_plane_in_state' >- - 'for_each_oldnew_plane_in_state_reverse' >- - 'for_each_oldnew_private_obj_in_state' >- - 'for_each_old_plane_in_state' >- - 'for_each_old_private_obj_in_state' >- - 'for_each_online_cpu' >- - 'for_each_online_node' >- - 'for_each_online_pgdat' >- - 'for_each_pci_bridge' >- - 'for_each_pci_dev' >- - 'for_each_pci_msi_entry' >- - 'for_each_populated_zone' >- - 'for_each_possible_cpu' >- - 'for_each_present_cpu' >- - 'for_each_prime_number' >- - 'for_each_prime_number_from' >- - 'for_each_process' >- - 'for_each_process_thread' >- - 'for_each_property_of_node' >- - 'for_each_registered_fb' >- - 'for_each_reserved_mem_region' >- - 'for_each_rtd_codec_dai' >- - 'for_each_rtd_codec_dai_rollback' >- - 'for_each_rtdcom' >- - 'for_each_rtdcom_safe' >- - 'for_each_set_bit' >- - 'for_each_set_bit_from' >- - 'for_each_sg' >- - 'for_each_sg_dma_page' >- - 'for_each_sg_page' >- - 'for_each_sibling_event' >- - 'for_each_subelement' >- - 'for_each_subelement_extid' >- - 'for_each_subelement_id' >- - '__for_each_thread' >- - 'for_each_thread' >- - 'for_each_zone' >- - 'for_each_zone_zonelist' >- - 'for_each_zone_zonelist_nodemask' >- - 'fwnode_for_each_available_child_node' >- - 'fwnode_for_each_child_node' >- - 'fwnode_graph_for_each_endpoint' >- - 'gadget_for_each_ep' >- - 'genradix_for_each' >- - 'genradix_for_each_from' >- - 'hash_for_each' >- - 'hash_for_each_possible' >- - 'hash_for_each_possible_rcu' >- - 'hash_for_each_possible_rcu_notrace' >- - 'hash_for_each_possible_safe' >- - 'hash_for_each_rcu' >- - 'hash_for_each_safe' >- - 'hctx_for_each_ctx' >- - 'hlist_bl_for_each_entry' >- - 'hlist_bl_for_each_entry_rcu' >- - 'hlist_bl_for_each_entry_safe' >- - 'hlist_for_each' >- - 'hlist_for_each_entry' >- - 'hlist_for_each_entry_continue' >- - 'hlist_for_each_entry_continue_rcu' >- - 'hlist_for_each_entry_continue_rcu_bh' >- - 'hlist_for_each_entry_from' >- - 'hlist_for_each_entry_from_rcu' >- - 'hlist_for_each_entry_rcu' >- - 'hlist_for_each_entry_rcu_bh' >- - 'hlist_for_each_entry_rcu_notrace' >- - 'hlist_for_each_entry_safe' >- - '__hlist_for_each_rcu' >- - 'hlist_for_each_safe' >- - 'hlist_nulls_for_each_entry' >- - 'hlist_nulls_for_each_entry_from' >- - 'hlist_nulls_for_each_entry_rcu' >- - 'hlist_nulls_for_each_entry_safe' >- - 'i3c_bus_for_each_i2cdev' >- - 'i3c_bus_for_each_i3cdev' >- - 'ide_host_for_each_port' >- - 'ide_port_for_each_dev' >- - 'ide_port_for_each_present_dev' >- - 'idr_for_each_entry' >- - 'idr_for_each_entry_continue' >- - 'idr_for_each_entry_ul' >- - 'inet_bind_bucket_for_each' >- - 'inet_lhash2_for_each_icsk_rcu' >- - 'key_for_each' >- - 'key_for_each_safe' >- - 'klp_for_each_func' >- - 'klp_for_each_func_safe' >- - 'klp_for_each_func_static' >- - 'klp_for_each_object' >- - 'klp_for_each_object_safe' >- - 'klp_for_each_object_static' >- - 'kvm_for_each_memslot' >- - 'kvm_for_each_vcpu' >- - 'list_for_each' >- - 'list_for_each_codec' >- - 'list_for_each_codec_safe' >- - 'list_for_each_entry' >- - 'list_for_each_entry_continue' >- - 'list_for_each_entry_continue_rcu' >- - 'list_for_each_entry_continue_reverse' >- - 'list_for_each_entry_from' >- - 'list_for_each_entry_from_rcu' >- - 'list_for_each_entry_from_reverse' >- - 'list_for_each_entry_lockless' >- - 'list_for_each_entry_rcu' >- - 'list_for_each_entry_reverse' >- - 'list_for_each_entry_safe' >- - 'list_for_each_entry_safe_continue' >- - 'list_for_each_entry_safe_from' >- - 'list_for_each_entry_safe_reverse' >- - 'list_for_each_prev' >- - 'list_for_each_prev_safe' >- - 'list_for_each_safe' >- - 'llist_for_each' >- - 'llist_for_each_entry' >- - 'llist_for_each_entry_safe' >- - 'llist_for_each_safe' >- - 'media_device_for_each_entity' >- - 'media_device_for_each_intf' >- - 'media_device_for_each_link' >- - 'media_device_for_each_pad' >- - 'mp_bvec_for_each_page' >- - 'mp_bvec_for_each_segment' >- - 'nanddev_io_for_each_page' >- - 'netdev_for_each_lower_dev' >- - 'netdev_for_each_lower_private' >- - 'netdev_for_each_lower_private_rcu' >- - 'netdev_for_each_mc_addr' >- - 'netdev_for_each_uc_addr' >- - 'netdev_for_each_upper_dev_rcu' >- - 'netdev_hw_addr_list_for_each' >- - 'nft_rule_for_each_expr' >- - 'nla_for_each_attr' >- - 'nla_for_each_nested' >- - 'nlmsg_for_each_attr' >- - 'nlmsg_for_each_msg' >- - 'nr_neigh_for_each' >- - 'nr_neigh_for_each_safe' >- - 'nr_node_for_each' >- - 'nr_node_for_each_safe' >- - 'of_for_each_phandle' >- - 'of_property_for_each_string' >- - 'of_property_for_each_u32' >- - 'pci_bus_for_each_resource' >- - 'ping_portaddr_for_each_entry' >- - 'plist_for_each' >- - 'plist_for_each_continue' >- - 'plist_for_each_entry' >- - 'plist_for_each_entry_continue' >- - 'plist_for_each_entry_safe' >- - 'plist_for_each_safe' >- - 'pnp_for_each_card' >- - 'pnp_for_each_dev' >- - 'protocol_for_each_card' >- - 'protocol_for_each_dev' >- - 'queue_for_each_hw_ctx' >- - 'radix_tree_for_each_slot' >- - 'radix_tree_for_each_tagged' >- - 'rbtree_postorder_for_each_entry_safe' >- - 'rdma_for_each_port' >- - 'resource_list_for_each_entry' >- - 'resource_list_for_each_entry_safe' >- - 'rhl_for_each_entry_rcu' >- - 'rhl_for_each_rcu' >- - 'rht_for_each' >- - 'rht_for_each_from' >- - 'rht_for_each_entry' >- - 'rht_for_each_entry_from' >- - 'rht_for_each_entry_rcu' >- - 'rht_for_each_entry_rcu_from' >- - 'rht_for_each_entry_safe' >- - 'rht_for_each_rcu' >- - 'rht_for_each_rcu_from' >- - '__rq_for_each_bio' >- - 'rq_for_each_bvec' >- - 'rq_for_each_segment' >- - 'scsi_for_each_prot_sg' >- - 'scsi_for_each_sg' >- - 'sctp_for_each_hentry' >- - 'sctp_skb_for_each' >- - 'shdma_for_each_chan' >- - '__shost_for_each_device' >- - 'shost_for_each_device' >- - 'sk_for_each' >- - 'sk_for_each_bound' >- - 'sk_for_each_entry_offset_rcu' >- - 'sk_for_each_from' >- - 'sk_for_each_rcu' >- - 'sk_for_each_safe' >- - 'sk_nulls_for_each' >- - 'sk_nulls_for_each_from' >- - 'sk_nulls_for_each_rcu' >- - 'snd_array_for_each' >- - 'snd_pcm_group_for_each_entry' >- - 'snd_soc_dapm_widget_for_each_path' >- - 'snd_soc_dapm_widget_for_each_path_safe' >- - 'snd_soc_dapm_widget_for_each_sink_path' >- - 'snd_soc_dapm_widget_for_each_source_path' >- - 'tb_property_for_each' >- - 'tcf_exts_for_each_action' >- - 'udp_portaddr_for_each_entry' >- - 'udp_portaddr_for_each_entry_rcu' >- - 'usb_hub_for_each_child' >- - 'v4l2_device_for_each_subdev' >- - 'v4l2_m2m_for_each_dst_buf' >- - 'v4l2_m2m_for_each_dst_buf_safe' >- - 'v4l2_m2m_for_each_src_buf' >- - 'v4l2_m2m_for_each_src_buf_safe' >- - 'virtio_device_for_each_vq' >- - 'xa_for_each' >- - 'xa_for_each_marked' >- - 'xa_for_each_start' >- - 'xas_for_each' >- - 'xas_for_each_conflict' >- - 'xas_for_each_marked' >- - 'zorro_for_each_dev' >- >-#IncludeBlocks: Preserve # Unknown to clang-format-5.0 >-IncludeCategories: >- - Regex: '.*' >- Priority: 1 >-IncludeIsMainRegex: '(Test)?$' >-IndentCaseLabels: false >-#IndentPPDirectives: None # Unknown to clang-format-5.0 >-IndentWidth: 8 >-IndentWrappedFunctionNames: false >-JavaScriptQuotes: Leave >-JavaScriptWrapImports: true >-KeepEmptyLinesAtTheStartOfBlocks: false >-MacroBlockBegin: '' >-MacroBlockEnd: '' >-MaxEmptyLinesToKeep: 1 >-NamespaceIndentation: Inner >-#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0 >-ObjCBlockIndentWidth: 8 >-ObjCSpaceAfterProperty: true >-ObjCSpaceBeforeProtocolList: true >- >-# Taken from git's rules >-#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0 >-PenaltyBreakBeforeFirstCallParameter: 30 >-PenaltyBreakComment: 10 >-PenaltyBreakFirstLessLess: 0 >-PenaltyBreakString: 10 >-PenaltyExcessCharacter: 100 >-PenaltyReturnTypeOnItsOwnLine: 60 >- >-PointerAlignment: Right >-ReflowComments: false >-SortIncludes: false >-#SortUsingDeclarations: false # Unknown to clang-format-4.0 >-SpaceAfterCStyleCast: false >-SpaceAfterTemplateKeyword: true >-SpaceBeforeAssignmentOperators: true >-#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0 >-#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0 >-SpaceBeforeParens: ControlStatements >-#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0 >-SpaceInEmptyParentheses: false >-SpacesBeforeTrailingComments: 1 >-SpacesInAngles: false >-SpacesInContainerLiterals: false >-SpacesInCStyleCastParentheses: false >-SpacesInParentheses: false >-SpacesInSquareBrackets: false >-Standard: Cpp03 >-TabWidth: 8 >-UseTab: Always >-... >diff -Naur linux-5.3-rc6/.cocciconfig linux-5.3-rc6-agd5fed/.cocciconfig >--- linux-5.3-rc6/.cocciconfig 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/.cocciconfig 1969-12-31 18:00:00.000000000 -0600 >@@ -1,3 +0,0 @@ >-[spatch] >- options = --timeout 200 >- options = --use-gitgrep >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/arm,pl11x.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/arm,pl11x.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/arm,pl11x.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/arm,pl11x.txt 2019-08-31 15:01:11.823736165 -0500 >@@ -39,9 +39,11 @@ > > - port: describes LCD panel signals, following the common binding > for video transmitter interfaces; see >- Documentation/devicetree/bindings/media/video-interfaces.txt; >- when it is a TFT panel, the port's endpoint must define the >- following property: >+ Documentation/devicetree/bindings/media/video-interfaces.txt >+ >+Deprecated properties: >+ The port's endbpoint subnode had this, now deprecated property >+ in the past. Drivers should be able to survive without it: > > - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values, > defining the way CLD pads are wired up; first value >@@ -80,7 +82,6 @@ > port { > clcd_pads: endpoint { > remote-endpoint = <&clcd_panel>; >- arm,pl11x,tft-r0g0b0-pads = <0 8 16>; > }; > }; > >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/bridge/sii902x.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/bridge/sii902x.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/bridge/sii902x.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/bridge/sii902x.txt 2019-08-31 15:01:11.823736165 -0500 >@@ -26,9 +26,8 @@ > - clocks: phandle and clock specifier for each clock listed in > the clock-names property > - clock-names: "mclk" >- Describes SII902x MCLK input. MCLK is used to produce >- HDMI audio CTS values. This property is required if >- "#sound-dai-cells"-property is present. This property follows >+ Describes SII902x MCLK input. MCLK can be used to produce >+ HDMI audio CTS values. This property follows > Documentation/devicetree/bindings/clock/clock-bindings.txt > consumer binding. > >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,26 +0,0 @@ >-Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel >- >-This binding is compatible with the simple-panel binding, which is specified >-in simple-panel.txt in this directory. >- >-Required properties: >-- compatible: should be "ampire,am-480272h3tmqw-t01h" >- >-Optional properties: >-- power-supply: regulator to provide the supply voltage >-- enable-gpios: GPIO pin to enable or disable the panel >-- backlight: phandle of the backlight device attached to the panel >- >-Optional nodes: >-- Video port for RGB input. >- >-Example: >- panel_rgb: panel-rgb { >- compatible = "ampire,am-480272h3tmqw-t01h"; >- enable-gpios = <&gpioa 8 1>; >- port { >- panel_in_rgb: endpoint { >- remote-endpoint = <&controller_out_rgb>; >- }; >- }; >- }; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml 2019-08-31 15:01:11.823736165 -0500 >@@ -0,0 +1,42 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/ampire,am-480272h3tmqw-t01h.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel >+ >+maintainers: >+ - Yannick Fertre <yannick.fertre@st.com> >+ - Thierry Reding <treding@nvidia.com> >+ >+allOf: >+ - $ref: panel-common.yaml# >+ >+properties: >+ compatible: >+ const: ampire,am-480272h3tmqw-t01h >+ >+ power-supply: true >+ enable-gpios: true >+ backlight: true >+ port: true >+ >+required: >+ - compatible >+ >+additionalProperties: false >+ >+examples: >+ - | >+ panel_rgb: panel { >+ compatible = "ampire,am-480272h3tmqw-t01h"; >+ enable-gpios = <&gpioa 8 1>; >+ port { >+ panel_in_rgb: endpoint { >+ remote-endpoint = <&controller_out_rgb>; >+ }; >+ }; >+ }; >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,9 +0,0 @@ >-Armadeus ST0700 Adapt. A Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT with >-an adapter board. >- >-Required properties: >-- compatible: "armadeus,st0700-adapt" >-- power-supply: see panel-common.txt >- >-Optional properties: >-- backlight: see panel-common.txt >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.yaml 2019-08-31 15:01:11.823736165 -0500 >@@ -0,0 +1,33 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/armadeus,st0700-adapt.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Armadeus ST0700 Adapter >+ >+description: >+ A Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT with an adapter board. >+ >+maintainers: >+ - '"Sébastien Szymanski" <sebastien.szymanski@armadeus.com>' >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+allOf: >+ - $ref: panel-common.yaml# >+ >+properties: >+ compatible: >+ const: armadeus,st0700-adapt >+ >+ power-supply: true >+ backlight: true >+ port: true >+ >+additionalProperties: false >+ >+required: >+ - compatible >+ - power-supply >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt 2019-08-31 15:01:11.823736165 -0500 >@@ -10,7 +10,7 @@ > - compatible: should be "arm,versatile-tft-panel" > > Required subnodes: >-- port: see display/panel/panel-common.txt, graph.txt >+- port: see display/panel/panel-common.yaml, graph.txt > > > Example: >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,12 +0,0 @@ >-Banana Pi 7" (S070WV20-CT16) TFT LCD Panel >- >-Required properties: >-- compatible: should be "bananapi,s070wv20-ct16" >-- power-supply: see ./panel-common.txt >- >-Optional properties: >-- enable-gpios: see ./simple-panel.txt >-- backlight: see ./simple-panel.txt >- >-This binding is compatible with the simple-panel binding, which is specified >-in ./simple-panel.txt. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.yaml 2019-08-31 15:01:11.823736165 -0500 >@@ -0,0 +1,31 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/bananapi,s070wv20-ct16.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Banana Pi 7" (S070WV20-CT16) TFT LCD Panel >+ >+maintainers: >+ - Chen-Yu Tsai <wens@csie.org> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+allOf: >+ - $ref: panel-common.yaml# >+ >+properties: >+ compatible: >+ const: bananapi,s070wv20-ct16 >+ >+ power-supply: true >+ backlight: true >+ enable-gpios: true >+ port: true >+ >+additionalProperties: false >+ >+required: >+ - compatible >+ - power-supply >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt 2019-08-31 15:01:11.823736165 -0500 >@@ -0,0 +1,24 @@ >+Boe Himax8279d 1200x1920 TFT LCD panel >+ >+Required properties: >+- compatible: should be "boe,himax8279d8p" and one of: "boe,himax8279d10p" >+- reg: DSI virtual channel of the peripheral >+- enable-gpios: panel enable gpio >+- pp33-gpios: a GPIO phandle for the 3.3v pin that provides the supply voltage >+- pp18-gpios: a GPIO phandle for the 1.8v pin that provides the supply voltage >+ >+Optional properties: >+- backlight: phandle of the backlight device attached to the panel >+ >+Example: >+ >+ &mipi_dsi { >+ panel { >+ compatible = "boe,himax8279d8p", "boe,himax8279d10p"; >+ reg = <0>; >+ backlight = <&backlight>; >+ enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; >+ pp33-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; >+ pp18-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; >+ }; >+ }; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,13 +0,0 @@ >-DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel >- >-Required properties: >-- compatible: should be "dlc,dlc0700yzg-1" >-- power-supply: See simple-panel.txt >- >-Optional properties: >-- reset-gpios: See panel-common.txt >-- enable-gpios: See simple-panel.txt >-- backlight: See simple-panel.txt >- >-This binding is compatible with the simple-panel binding, which is specified >-in simple-panel.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.yaml 2019-08-31 15:01:11.823736165 -0500 >@@ -0,0 +1,31 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/dlc,dlc0700yzg-1.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel >+ >+maintainers: >+ - Philipp Zabel <p.zabel@pengutronix.de> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+allOf: >+ - $ref: panel-common.yaml# >+ >+properties: >+ compatible: >+ const: dlc,dlc0700yzg-1 >+ >+ reset-gpios: true >+ enable-gpios: true >+ backlight: true >+ port: true >+ >+additionalProperties: false >+ >+required: >+ - compatible >+ - power-supply >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/edt,et-series.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/edt,et-series.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/edt,et-series.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/edt,et-series.txt 2019-08-31 15:01:11.823736165 -0500 >@@ -40,7 +40,7 @@ > | Identifier | compatbile | description | > +=================+=====================+=====================================+ > | ETM0700G0DH6 | edt,etm070080dh6 | WVGA TFT Display with capacitive | >-| | | Touchscreen | >+| | edt,etm0700g0dh6 | Touchscreen | > +-----------------+---------------------+-------------------------------------+ > | ETM0700G0BDH6 | edt,etm070080bdh6 | Same as ETM0700G0DH6 but with | > | | | inverted pixel clock. | >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt 2019-08-31 15:01:11.823736165 -0500 >@@ -0,0 +1,12 @@ >+GiantPlus 3.0" (320x240 pixels) 24-bit TFT LCD panel >+ >+Required properties: >+- compatible: should be "giantplus,gpm940b0" >+- power-supply: as specified in the base binding >+ >+Optional properties: >+- backlight: as specified in the base binding >+- enable-gpios: as specified in the base binding >+ >+This binding is compatible with the simple-panel binding, which is specified >+in simple-panel.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,7 +0,0 @@ >-Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel >- >-Required properties: >-- compatible: should be "innolux,ee101ia-01d" >- >-This binding is compatible with the lvds-panel binding, which is specified >-in panel-lvds.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,31 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/innolux,ee101ia-01d.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel >+ >+maintainers: >+ - Heiko Stuebner <heiko.stuebner@bq.com> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+allOf: >+ - $ref: lvds.yaml# >+ >+properties: >+ compatible: >+ items: >+ - const: innolux,ee101ia-01d >+ - {} # panel-lvds, but not listed here to avoid false select >+ >+ backlight: true >+ enable-gpios: true >+ power-supply: true >+ width-mm: true >+ height-mm: true >+ panel-timing: true >+ port: true >+ >+additionalProperties: false >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/kingdisplay,kd035g6-54nt.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/kingdisplay,kd035g6-54nt.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/kingdisplay,kd035g6-54nt.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/kingdisplay,kd035g6-54nt.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,42 @@ >+King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel >+ >+Required properties: >+- compatible: should be "kingdisplay,kd035g6-54nt" >+- power-supply: See panel-common.txt >+- reset-gpios: See panel-common.txt >+ >+Optional properties: >+- backlight: see panel-common.txt >+ >+The generic bindings for the SPI slaves documented in [1] also apply. >+ >+The device node can contain one 'port' child node with one child >+'endpoint' node, according to the bindings defined in [2]. This >+node should describe panel's video bus. >+ >+[1]: Documentation/devicetree/bindings/spi/spi-bus.txt >+[2]: Documentation/devicetree/bindings/graph.txt >+ >+Example: >+ >+&spi { >+ panel@0 { >+ compatible = "kingdisplay,kd035g6-54nt"; >+ reg = <0>; >+ >+ spi-max-frequency = <3125000>; >+ spi-3wire; >+ spi-cs-high; >+ >+ reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>; >+ >+ backlight = <&backlight>; >+ power-supply = <&ldo6>; >+ >+ port { >+ panel_input: endpoint { >+ remote-endpoint = <&panel_output>; >+ }; >+ }; >+ }; >+}; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/lvds.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/lvds.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/lvds.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/lvds.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,107 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/lvds.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: LVDS Display Panel >+ >+maintainers: >+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+description: |+ >+ LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple >+ incompatible data link layers have been used over time to transmit image data >+ to LVDS panels. This bindings supports display panels compatible with the >+ following specifications. >+ >+ [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February >+ 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) >+ [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National >+ Semiconductor >+ [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video >+ Electronics Standards Association (VESA) >+ >+ Device compatible with those specifications have been marketed under the >+ FPD-Link and FlatLink brands. >+ >+allOf: >+ - $ref: panel-common.yaml# >+ >+properties: >+ compatible: >+ contains: >+ const: panel-lvds >+ description: >+ Shall contain "panel-lvds" in addition to a mandatory panel-specific >+ compatible string defined in individual panel bindings. The "panel-lvds" >+ value shall never be used on its own. >+ >+ data-mapping: >+ enum: >+ - jeida-18 >+ - jeida-24 >+ - vesa-24 >+ description: | >+ The color signals mapping order. >+ >+ LVDS data mappings are defined as follows. >+ >+ - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and >+ [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. >+ >+ Slot 0 1 2 3 4 5 6 >+ ________________ _________________ >+ Clock \_______________________/ >+ ______ ______ ______ ______ ______ ______ ______ >+ DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< >+ DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< >+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< >+ >+ - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] >+ specifications. Data are transferred as follows on 4 LVDS lanes. >+ >+ Slot 0 1 2 3 4 5 6 >+ ________________ _________________ >+ Clock \_______________________/ >+ ______ ______ ______ ______ ______ ______ ______ >+ DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< >+ DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< >+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< >+ DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< >+ >+ - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. >+ Data are transferred as follows on 4 LVDS lanes. >+ >+ Slot 0 1 2 3 4 5 6 >+ ________________ _________________ >+ Clock \_______________________/ >+ ______ ______ ______ ______ ______ ______ ______ >+ DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< >+ DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< >+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< >+ DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< >+ >+ Control signals are mapped as follows. >+ >+ CTL0: HSync >+ CTL1: VSync >+ CTL2: Data Enable >+ CTL3: 0 >+ >+ data-mirror: >+ type: boolean >+ description: >+ If set, reverse the bit order described in the data mappings below on all >+ data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6. >+ >+required: >+ - compatible >+ - data-mapping >+ - width-mm >+ - height-mm >+ - panel-timing >+ - port >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,47 +0,0 @@ >-Mitsubishi AA204XD12 LVDS Display Panel >-======================================= >- >-The AA104XD12 is a 10.4" XGA TFT-LCD display panel. >- >-These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt >-with the following device-specific properties. >- >- >-Required properties: >- >-- compatible: Shall contain "mitsubishi,aa121td01" and "panel-lvds", in that >- order. >-- vcc-supply: Reference to the regulator powering the panel VCC pins. >- >- >-Example >-------- >- >-panel { >- compatible = "mitsubishi,aa104xd12", "panel-lvds"; >- vcc-supply = <&vcc_3v3>; >- >- width-mm = <210>; >- height-mm = <158>; >- >- data-mapping = "jeida-24"; >- >- panel-timing { >- /* 1024x768 @65Hz */ >- clock-frequency = <65000000>; >- hactive = <1024>; >- vactive = <768>; >- hsync-len = <136>; >- hfront-porch = <20>; >- hback-porch = <160>; >- vfront-porch = <3>; >- vback-porch = <29>; >- vsync-len = <6>; >- }; >- >- port { >- panel_in: endpoint { >- remote-endpoint = <&lvds_encoder>; >- }; >- }; >-}; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,75 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/mitsubishi,aa104xd12.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Mitsubishi AA104XD12 10.4" XGA LVDS Display Panel >+ >+maintainers: >+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+allOf: >+ - $ref: lvds.yaml# >+ >+properties: >+ compatible: >+ items: >+ - const: mitsubishi,aa104xd12 >+ - {} # panel-lvds, but not listed here to avoid false select >+ >+ vcc-supply: >+ description: Reference to the regulator powering the panel VCC pins. >+ >+ data-mapping: >+ const: jeida-24 >+ >+ width-mm: >+ const: 210 >+ >+ height-mm: >+ const: 158 >+ >+ panel-timing: true >+ port: true >+ >+additionalProperties: false >+ >+required: >+ - compatible >+ - vcc-supply >+ >+examples: >+ - |+ >+ >+ panel { >+ compatible = "mitsubishi,aa104xd12", "panel-lvds"; >+ vcc-supply = <&vcc_3v3>; >+ >+ width-mm = <210>; >+ height-mm = <158>; >+ >+ data-mapping = "jeida-24"; >+ >+ panel-timing { >+ /* 1024x768 @65Hz */ >+ clock-frequency = <65000000>; >+ hactive = <1024>; >+ vactive = <768>; >+ hsync-len = <136>; >+ hfront-porch = <20>; >+ hback-porch = <160>; >+ vfront-porch = <3>; >+ vback-porch = <29>; >+ vsync-len = <6>; >+ }; >+ >+ port { >+ panel_in: endpoint { >+ remote-endpoint = <&lvds_encoder>; >+ }; >+ }; >+ }; >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,47 +0,0 @@ >-Mitsubishi AA121TD01 LVDS Display Panel >-======================================= >- >-The AA121TD01 is a 12.1" WXGA TFT-LCD display panel. >- >-These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt >-with the following device-specific properties. >- >- >-Required properties: >- >-- compatible: Shall contain "mitsubishi,aa121td01" and "panel-lvds", in that >- order. >-- vcc-supply: Reference to the regulator powering the panel VCC pins. >- >- >-Example >-------- >- >-panel { >- compatible = "mitsubishi,aa121td01", "panel-lvds"; >- vcc-supply = <&vcc_3v3>; >- >- width-mm = <261>; >- height-mm = <163>; >- >- data-mapping = "jeida-24"; >- >- panel-timing { >- /* 1280x800 @60Hz */ >- clock-frequency = <71000000>; >- hactive = <1280>; >- vactive = <800>; >- hsync-len = <70>; >- hfront-porch = <20>; >- hback-porch = <70>; >- vsync-len = <5>; >- vfront-porch = <3>; >- vback-porch = <15>; >- }; >- >- port { >- panel_in: endpoint { >- remote-endpoint = <&lvds_encoder>; >- }; >- }; >-}; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,74 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/mitsubishi,aa121td01.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Mitsubishi AA121TD01 12.1" WXGA LVDS Display Panel >+ >+maintainers: >+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+allOf: >+ - $ref: lvds.yaml# >+ >+properties: >+ compatible: >+ items: >+ - const: mitsubishi,aa121td01 >+ - {} # panel-lvds, but not listed here to avoid false select >+ >+ vcc-supply: >+ description: Reference to the regulator powering the panel VCC pins. >+ >+ data-mapping: >+ const: jeida-24 >+ >+ width-mm: >+ const: 261 >+ >+ height-mm: >+ const: 163 >+ >+ panel-timing: true >+ port: true >+ >+additionalProperties: false >+ >+required: >+ - compatible >+ - vcc-supply >+ >+examples: >+ - |+ >+ panel { >+ compatible = "mitsubishi,aa121td01", "panel-lvds"; >+ vcc-supply = <&vcc_3v3>; >+ >+ width-mm = <261>; >+ height-mm = <163>; >+ >+ data-mapping = "jeida-24"; >+ >+ panel-timing { >+ /* 1280x800 @60Hz */ >+ clock-frequency = <71000000>; >+ hactive = <1280>; >+ vactive = <800>; >+ hsync-len = <70>; >+ hfront-porch = <20>; >+ hback-porch = <70>; >+ vsync-len = <5>; >+ vfront-porch = <3>; >+ vback-porch = <15>; >+ }; >+ >+ port { >+ panel_in: endpoint { >+ remote-endpoint = <&lvds_encoder>; >+ }; >+ }; >+ }; >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m05dtc.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m05dtc.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m05dtc.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m05dtc.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,12 @@ >+OrtusTech COM37H3M05DTC Blanview 3.7" VGA portrait TFT-LCD panel >+ >+Required properties: >+- compatible: should be "ortustech,com37h3m05dtc" >+ >+Optional properties: >+- enable-gpios: GPIO pin to enable or disable the panel >+- backlight: phandle of the backlight device attached to the panel >+- power-supply: phandle of the regulator that provides the supply voltage >+ >+This binding is compatible with the simple-panel binding, which is specified >+in simple-panel.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m99dtc.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m99dtc.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m99dtc.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m99dtc.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,12 @@ >+OrtusTech COM37H3M99DTC Blanview 3.7" VGA portrait TFT-LCD panel >+ >+Required properties: >+- compatible: should be "ortustech,com37h3m99dtc" >+ >+Optional properties: >+- enable-gpios: GPIO pin to enable or disable the panel >+- backlight: phandle of the backlight device attached to the panel >+- power-supply: phandle of the regulator that provides the supply voltage >+ >+This binding is compatible with the simple-panel binding, which is specified >+in simple-panel.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-common.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-common.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-common.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-common.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,101 +0,0 @@ >-Common Properties for Display Panel >-=================================== >- >-This document defines device tree properties common to several classes of >-display panels. It doesn't constitue a device tree binding specification by >-itself but is meant to be referenced by device tree bindings. >- >-When referenced from panel device tree bindings the properties defined in this >-document are defined as follows. The panel device tree bindings are >-responsible for defining whether each property is required or optional. >- >- >-Descriptive Properties >----------------------- >- >-- width-mm, >-- height-mm: The width-mm and height-mm specify the width and height of the >- physical area where images are displayed. These properties are expressed in >- millimeters and rounded to the closest unit. >- >-- label: The label property specifies a symbolic name for the panel as a >- string suitable for use by humans. It typically contains a name inscribed on >- the system (e.g. as an affixed label) or specified in the system's >- documentation (e.g. in the user's manual). >- >- If no such name exists, and unless the property is mandatory according to >- device tree bindings, it shall rather be omitted than constructed of >- non-descriptive information. For instance an LCD panel in a system that >- contains a single panel shall not be labelled "LCD" if that name is not >- inscribed on the system or used in a descriptive fashion in system >- documentation. >- >- >-Display Timings >---------------- >- >-- panel-timing: Most display panels are restricted to a single resolution and >- require specific display timings. The panel-timing subnode expresses those >- timings as specified in the timing subnode section of the display timing >- bindings defined in >- Documentation/devicetree/bindings/display/panel/display-timing.txt. >- >- >-Connectivity >------------- >- >-- ports: Panels receive video data through one or multiple connections. While >- the nature of those connections is specific to the panel type, the >- connectivity is expressed in a standard fashion using ports as specified in >- the device graph bindings defined in >- Documentation/devicetree/bindings/graph.txt. >- >-- ddc-i2c-bus: Some panels expose EDID information through an I2C-compatible >- bus such as DDC2 or E-DDC. For such panels the ddc-i2c-bus contains a >- phandle to the system I2C controller connected to that bus. >- >- >-Control I/Os >------------- >- >-Many display panels can be controlled through pins driven by GPIOs. The nature >-and timing of those control signals are device-specific and left for panel >-device tree bindings to specify. The following GPIO specifiers can however be >-used for panels that implement compatible control signals. >- >-- enable-gpios: Specifier for a GPIO connected to the panel enable control >- signal. The enable signal is active high and enables operation of the panel. >- This property can also be used for panels implementing an active low power >- down signal, which is a negated version of the enable signal. Active low >- enable signals (or active high power down signals) can be supported by >- inverting the GPIO specifier polarity flag. >- >- Note that the enable signal control panel operation only and must not be >- confused with a backlight enable signal. >- >-- reset-gpios: Specifier for a GPIO coonnected to the panel reset control >- signal. The reset signal is active low and resets the panel internal logic >- while active. Active high reset signals can be supported by inverting the >- GPIO specifier polarity flag. >- >-Power >------ >- >-- power-supply: display panels require power to be supplied. While several >- panels need more than one power supply with panel-specific constraints >- governing the order and timings of the power supplies, in many cases a single >- power supply is sufficient, either because the panel has a single power rail, >- or because all its power rails can be driven by the same supply. In that case >- the power-supply property specifies the supply powering the panel as a phandle >- to a regulator. >- >-Backlight >---------- >- >-Most display panels include a backlight. Some of them also include a backlight >-controller exposed through a control bus such as I2C or DSI. Others expose >-backlight control through GPIO, PWM or other signals connected to an external >-backlight controller. >- >-- backlight: For panels whose backlight is controlled by an external backlight >- controller, this property contains a phandle that references the controller. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-common.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-common.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-common.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-common.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,149 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/panel-common.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Common Properties for Display Panels >+ >+maintainers: >+ - Thierry Reding <thierry.reding@gmail.com> >+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> >+ >+description: | >+ This document defines device tree properties common to several classes of >+ display panels. It doesn't constitue a device tree binding specification by >+ itself but is meant to be referenced by device tree bindings. >+ >+ When referenced from panel device tree bindings the properties defined in this >+ document are defined as follows. The panel device tree bindings are >+ responsible for defining whether each property is required or optional. >+ >+properties: >+ # Descriptive Properties >+ width-mm: >+ description: >+ Specifies the width of the physical area where images are displayed. This >+ property is expressed in millimeters and rounded to the closest unit. >+ >+ height-mm: >+ description: >+ Specifies the height of the physical area where images are displayed. This >+ property is expressed in millimeters and rounded to the closest unit. >+ >+ label: >+ description: | >+ The label property specifies a symbolic name for the panel as a >+ string suitable for use by humans. It typically contains a name inscribed >+ on the system (e.g. as an affixed label) or specified in the system's >+ documentation (e.g. in the user's manual). >+ >+ If no such name exists, and unless the property is mandatory according to >+ device tree bindings, it shall rather be omitted than constructed of >+ non-descriptive information. For instance an LCD panel in a system that >+ contains a single panel shall not be labelled "LCD" if that name is not >+ inscribed on the system or used in a descriptive fashion in system >+ documentation. >+ >+ rotation: >+ description: >+ Display rotation in degrees counter clockwise (0,90,180,270) >+ allOf: >+ - $ref: /schemas/types.yaml#/definitions/uint32 >+ - enum: [ 0, 90, 180, 270 ] >+ >+ # Display Timings >+ panel-timing: >+ type: object >+ description: >+ Most display panels are restricted to a single resolution and >+ require specific display timings. The panel-timing subnode expresses those >+ timings as specified in the timing subnode section of the display timing >+ bindings defined in >+ Documentation/devicetree/bindings/display/panel/display-timing.txt. >+ >+ # Connectivity >+ port: >+ type: object >+ >+ ports: >+ type: object >+ description: >+ Panels receive video data through one or multiple connections. While >+ the nature of those connections is specific to the panel type, the >+ connectivity is expressed in a standard fashion using ports as specified >+ in the device graph bindings defined in >+ Documentation/devicetree/bindings/graph.txt. >+ >+ ddc-i2c-bus: >+ $ref: /schemas/types.yaml#/definitions/phandle >+ description: >+ Some panels expose EDID information through an I2C-compatible >+ bus such as DDC2 or E-DDC. For such panels the ddc-i2c-bus contains a >+ phandle to the system I2C controller connected to that bus. >+ >+ no-hpd: >+ type: boolean >+ description: >+ This panel is supposed to communicate that it's ready via HPD >+ (hot plug detect) signal, but the signal isn't hooked up so we should >+ hardcode the max delay from the panel spec when powering up the panel. >+ >+ # Control I/Os >+ >+ # Many display panels can be controlled through pins driven by GPIOs. The nature >+ # and timing of those control signals are device-specific and left for panel >+ # device tree bindings to specify. The following GPIO specifiers can however be >+ # used for panels that implement compatible control signals. >+ >+ enable-gpios: >+ maxItems: 1 >+ description: | >+ Specifier for a GPIO connected to the panel enable control signal. The >+ enable signal is active high and enables operation of the panel. This >+ property can also be used for panels implementing an active low power down >+ signal, which is a negated version of the enable signal. Active low enable >+ signals (or active high power down signals) can be supported by inverting >+ the GPIO specifier polarity flag. >+ >+ Note that the enable signal control panel operation only and must not be >+ confused with a backlight enable signal. >+ >+ reset-gpios: >+ maxItems: 1 >+ description: >+ Specifier for a GPIO connected to the panel reset control signal. >+ The reset signal is active low and resets the panel internal logic >+ while active. Active high reset signals can be supported by inverting the >+ GPIO specifier polarity flag. >+ >+ # Power >+ power-supply: >+ description: >+ Display panels require power to be supplied. While several panels need >+ more than one power supply with panel-specific constraints governing the >+ order and timings of the power supplies, in many cases a single power >+ supply is sufficient, either because the panel has a single power rail, or >+ because all its power rails can be driven by the same supply. In that case >+ the power-supply property specifies the supply powering the panel as a >+ phandle to a regulator. >+ >+ # Backlight >+ >+ # Most display panels include a backlight. Some of them also include a backlight >+ # controller exposed through a control bus such as I2C or DSI. Others expose >+ # backlight control through GPIO, PWM or other signals connected to an external >+ # backlight controller. >+ >+ backlight: >+ $ref: /schemas/types.yaml#/definitions/phandle >+ description: >+ For panels whose backlight is controlled by an external backlight >+ controller, this property contains a phandle that references the >+ controller. >+ >+dependencies: >+ width-mm: [ height-mm ] >+ height-mm: [ width-mm ] >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-lvds.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-lvds.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-lvds.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-lvds.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,121 +0,0 @@ >-LVDS Display Panel >-================== >- >-LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple >-incompatible data link layers have been used over time to transmit image data >-to LVDS panels. This bindings supports display panels compatible with the >-following specifications. >- >-[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February >-1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) >-[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National >-Semiconductor >-[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video >-Electronics Standards Association (VESA) >- >-Device compatible with those specifications have been marketed under the >-FPD-Link and FlatLink brands. >- >- >-Required properties: >- >-- compatible: Shall contain "panel-lvds" in addition to a mandatory >- panel-specific compatible string defined in individual panel bindings. The >- "panel-lvds" value shall never be used on its own. >-- width-mm: See panel-common.txt. >-- height-mm: See panel-common.txt. >-- data-mapping: The color signals mapping order, "jeida-18", "jeida-24" >- or "vesa-24". >- >-Optional properties: >- >-- label: See panel-common.txt. >-- gpios: See panel-common.txt. >-- backlight: See panel-common.txt. >-- power-supply: See panel-common.txt. >-- data-mirror: If set, reverse the bit order described in the data mappings >- below on all data lanes, transmitting bits for slots 6 to 0 instead of >- 0 to 6. >- >-Required nodes: >- >-- panel-timing: See panel-common.txt. >-- ports: See panel-common.txt. These bindings require a single port subnode >- corresponding to the panel LVDS input. >- >- >-LVDS data mappings are defined as follows. >- >-- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and >- [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. >- >-Slot 0 1 2 3 4 5 6 >- ________________ _________________ >-Clock \_______________________/ >- ______ ______ ______ ______ ______ ______ ______ >-DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< >-DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< >-DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< >- >-- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] >- specifications. Data are transferred as follows on 4 LVDS lanes. >- >-Slot 0 1 2 3 4 5 6 >- ________________ _________________ >-Clock \_______________________/ >- ______ ______ ______ ______ ______ ______ ______ >-DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< >-DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< >-DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< >-DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< >- >-- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. >- Data are transferred as follows on 4 LVDS lanes. >- >-Slot 0 1 2 3 4 5 6 >- ________________ _________________ >-Clock \_______________________/ >- ______ ______ ______ ______ ______ ______ ______ >-DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< >-DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< >-DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< >-DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< >- >-Control signals are mapped as follows. >- >-CTL0: HSync >-CTL1: VSync >-CTL2: Data Enable >-CTL3: 0 >- >- >-Example >-------- >- >-panel { >- compatible = "mitsubishi,aa121td01", "panel-lvds"; >- >- width-mm = <261>; >- height-mm = <163>; >- >- data-mapping = "jeida-24"; >- >- panel-timing { >- /* 1280x800 @60Hz */ >- clock-frequency = <71000000>; >- hactive = <1280>; >- vactive = <800>; >- hsync-len = <70>; >- hfront-porch = <20>; >- hback-porch = <70>; >- vsync-len = <5>; >- vfront-porch = <3>; >- vback-porch = <15>; >- }; >- >- port { >- panel_in: endpoint { >- remote-endpoint = <&lvds_encoder>; >- }; >- }; >-}; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,4 +0,0 @@ >-Common display properties >-------------------------- >- >-- rotation: Display rotation in degrees counter clockwise (0,90,180,270) >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,14 +0,0 @@ >-PDA 91-00156-A0 5.0" WVGA TFT LCD panel >- >-Required properties: >-- compatible: should be "pda,91-00156-a0" >-- power-supply: this panel requires a single power supply. A phandle to a >-regulator needs to be specified here. Compatible with panel-common binding which >-is specified in the panel-common.txt in this directory. >-- backlight: this panel's backlight is controlled by an external backlight >-controller. A phandle to this controller needs to be specified here. >-Compatible with panel-common binding which is specified in the panel-common.txt >-in this directory. >- >-This binding is compatible with the simple-panel binding, which is specified >-in simple-panel.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,31 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/pda,91-00156-a0.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: PDA 91-00156-A0 5.0" WVGA TFT LCD panel >+ >+maintainers: >+ - Cristian Birsan <cristian.birsan@microchip.com> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+allOf: >+ - $ref: panel-common.yaml# >+ >+properties: >+ compatible: >+ const: pda,91-00156-a0 >+ >+ power-supply: true >+ backlight: true >+ port: true >+ >+additionalProperties: false >+ >+required: >+ - compatible >+ - power-supply >+ - backlight >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,49 +0,0 @@ >-This binding covers the official 7" (800x480) Raspberry Pi touchscreen >-panel. >- >-This DSI panel contains: >- >-- TC358762 DSI->DPI bridge >-- Atmel microcontroller on I2C for power sequencing the DSI bridge and >- controlling backlight >-- Touchscreen controller on I2C for touch input >- >-and this binding covers the DSI display parts but not its touch input. >- >-Required properties: >-- compatible: Must be "raspberrypi,7inch-touchscreen-panel" >-- reg: Must be "45" >-- port: See panel-common.txt >- >-Example: >- >-dsi1: dsi@7e700000 { >- #address-cells = <1>; >- #size-cells = <0>; >- <...> >- >- port { >- dsi_out_port: endpoint { >- remote-endpoint = <&panel_dsi_port>; >- }; >- }; >-}; >- >-i2c_dsi: i2c { >- compatible = "i2c-gpio"; >- #address-cells = <1>; >- #size-cells = <0>; >- gpios = <&gpio 28 0 >- &gpio 29 0>; >- >- lcd@45 { >- compatible = "raspberrypi,7inch-touchscreen-panel"; >- reg = <0x45>; >- >- port { >- panel_dsi_port: endpoint { >- remote-endpoint = <&dsi_out_port>; >- }; >- }; >- }; >-}; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,71 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/raspberrypi,7inch-touchscreen.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: The official 7" (800x480) Raspberry Pi touchscreen >+ >+maintainers: >+ - Eric Anholt <eric@anholt.net> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+description: |+ >+ This DSI panel contains: >+ >+ - TC358762 DSI->DPI bridge >+ - Atmel microcontroller on I2C for power sequencing the DSI bridge and >+ controlling backlight >+ - Touchscreen controller on I2C for touch input >+ >+ and this binding covers the DSI display parts but not its touch input. >+ >+properties: >+ compatible: >+ const: raspberrypi,7inch-touchscreen-panel >+ >+ reg: >+ const: 0x45 >+ >+ port: true >+ >+required: >+ - compatible >+ - reg >+ - port >+ >+additionalProperties: false >+ >+examples: >+ - |+ >+ dsi1: dsi { >+ #address-cells = <1>; >+ #size-cells = <0>; >+ >+ port { >+ dsi_out_port: endpoint { >+ remote-endpoint = <&panel_dsi_port>; >+ }; >+ }; >+ }; >+ >+ i2c_dsi: i2c { >+ compatible = "i2c-gpio"; >+ #address-cells = <1>; >+ #size-cells = <0>; >+ scl-gpios = <&gpio 28 0>; >+ sda-gpios = <&gpio 29 0>; >+ >+ lcd@45 { >+ compatible = "raspberrypi,7inch-touchscreen-panel"; >+ reg = <0x45>; >+ >+ port { >+ panel_dsi_port: endpoint { >+ remote-endpoint = <&dsi_out_port>; >+ }; >+ }; >+ }; >+ }; >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,41 @@ >+Raydium RM67171 OLED LCD panel with MIPI-DSI protocol >+ >+Required properties: >+- compatible: "raydium,rm67191" >+- reg: virtual channel for MIPI-DSI protocol >+ must be <0> >+- dsi-lanes: number of DSI lanes to be used >+ must be <3> or <4> >+- port: input port node with endpoint definition as >+ defined in Documentation/devicetree/bindings/graph.txt; >+ the input port should be connected to a MIPI-DSI device >+ driver >+ >+Optional properties: >+- reset-gpios: a GPIO spec for the RST_B GPIO pin >+- v3p3-supply: phandle to 3.3V regulator that powers the VDD_3V3 pin >+- v1p8-supply: phandle to 1.8V regulator that powers the VDD_1V8 pin >+- width-mm: see panel-common.txt >+- height-mm: see panel-common.txt >+- video-mode: 0 - burst-mode >+ 1 - non-burst with sync event >+ 2 - non-burst with sync pulse >+ >+Example: >+ >+ panel@0 { >+ compatible = "raydium,rm67191"; >+ reg = <0>; >+ pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; >+ pinctrl-names = "default"; >+ reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; >+ dsi-lanes = <4>; >+ width-mm = <68>; >+ height-mm = <121>; >+ >+ port { >+ panel_in: endpoint { >+ remote-endpoint = <&mipi_out>; >+ }; >+ }; >+ }; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -5,6 +5,9 @@ > - reg: DSI virtual channel of the peripheral > - reset-gpios: panel reset gpio > - backlight: phandle of the backlight device attached to the panel >+- vcc-supply: phandle of the regulator that provides the vcc supply voltage. >+- iovcc-supply: phandle of the regulator that provides the iovcc supply >+ voltage. > > Example: > >@@ -14,5 +17,7 @@ > reg = <0>; > backlight = <&backlight>; > reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; >+ vcc-supply = <®_2v8_p>; >+ iovcc-supply = <®_1v8_p>; > }; > }; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,41 +0,0 @@ >-Solomon Goldentek Display GKTW70SDAE4SE LVDS Display Panel >-========================================================== >- >-The GKTW70SDAE4SE is a 7" WVGA TFT-LCD display panel. >- >-These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt >-with the following device-specific properties. >- >-Required properties: >- >-- compatible: Shall contain "sgd,gktw70sdae4se" and "panel-lvds", in that order. >- >-Example >-------- >- >-panel { >- compatible = "sgd,gktw70sdae4se", "panel-lvds"; >- >- width-mm = <153>; >- height-mm = <86>; >- >- data-mapping = "jeida-18"; >- >- panel-timing { >- clock-frequency = <32000000>; >- hactive = <800>; >- vactive = <480>; >- hback-porch = <39>; >- hfront-porch = <39>; >- vback-porch = <29>; >- vfront-porch = <13>; >- hsync-len = <47>; >- vsync-len = <2>; >- }; >- >- port { >- panel_in: endpoint { >- remote-endpoint = <&lvds_encoder>; >- }; >- }; >-}; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,68 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/sgd,gktw70sdae4se.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel >+ >+maintainers: >+ - Neil Armstrong <narmstrong@baylibre.com> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+allOf: >+ - $ref: lvds.yaml# >+ >+properties: >+ compatible: >+ items: >+ - const: sgd,gktw70sdae4se >+ - {} # panel-lvds, but not listed here to avoid false select >+ >+ data-mapping: >+ const: jeida-18 >+ >+ width-mm: >+ const: 153 >+ >+ height-mm: >+ const: 86 >+ >+ panel-timing: true >+ port: true >+ >+additionalProperties: false >+ >+required: >+ - compatible >+ >+examples: >+ - |+ >+ panel { >+ compatible = "sgd,gktw70sdae4se", "panel-lvds"; >+ >+ width-mm = <153>; >+ height-mm = <86>; >+ >+ data-mapping = "jeida-18"; >+ >+ panel-timing { >+ clock-frequency = <32000000>; >+ hactive = <800>; >+ vactive = <480>; >+ hback-porch = <39>; >+ hfront-porch = <39>; >+ vback-porch = <29>; >+ vfront-porch = <13>; >+ hsync-len = <47>; >+ vsync-len = <2>; >+ }; >+ >+ port { >+ panel_in: endpoint { >+ remote-endpoint = <&lvds_encoder>; >+ }; >+ }; >+ }; >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,26 @@ >+Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel >+ >+Required properties: >+- compatible: should be "sharp,ld-d5116z01b" >+- power-supply: regulator to provide the VCC supply voltage (3.3 volts) >+ >+This binding is compatible with the simple-panel binding. >+ >+The device node can contain one 'port' child node with one child >+'endpoint' node, according to the bindings defined in [1]. This >+node should describe panel's video bus. >+ >+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt >+ >+Example: >+ >+ panel: panel { >+ compatible = "sharp,ld-d5116z01b"; >+ power-supply = <&vlcd_3v3>; >+ >+ port { >+ panel_ep: endpoint { >+ remote-endpoint = <&bridge_out_ep>; >+ }; >+ }; >+ }; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,lq070y3dg3b.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,lq070y3dg3b.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,lq070y3dg3b.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,lq070y3dg3b.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,12 @@ >+Sharp LQ070Y3DG3B 7.0" WVGA landscape TFT LCD panel >+ >+Required properties: >+- compatible: should be "sharp,lq070y3dg3b" >+ >+Optional properties: >+- enable-gpios: GPIO pin to enable or disable the panel >+- backlight: phandle of the backlight device attached to the panel >+- power-supply: phandle of the regulator that provides the supply voltage >+ >+This binding is compatible with the simple-panel binding, which is specified >+in simple-panel.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,12 @@ >+Sharp 2.0" (240x160 pixels) 16-bit TFT LCD panel >+ >+Required properties: >+- compatible: should be "sharp,ls020b1dd01d" >+- power-supply: as specified in the base binding >+ >+Optional properties: >+- backlight: as specified in the base binding >+- enable-gpios: as specified in the base binding >+ >+This binding is compatible with the simple-panel binding, which is specified >+in simple-panel.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/simple-panel.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/simple-panel.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/simple-panel.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/simple-panel.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -1,28 +1 @@ >-Simple display panel >-==================== >- >-panel node >----------- >- >-Required properties: >-- power-supply: See panel-common.txt >- >-Optional properties: >-- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing >-- enable-gpios: GPIO pin to enable or disable the panel >-- backlight: phandle of the backlight device attached to the panel >-- no-hpd: This panel is supposed to communicate that it's ready via HPD >- (hot plug detect) signal, but the signal isn't hooked up so we should >- hardcode the max delay from the panel spec when powering up the panel. >- >-Example: >- >- panel: panel { >- compatible = "cptt,claa101wb01"; >- ddc-i2c-bus = <&panelddc>; >- >- power-supply = <&vdd_pnl_reg>; >- enable-gpios = <&gpio 90 0>; >- >- backlight = <&backlight>; >- }; >+See panel-common.yaml in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,15 +0,0 @@ >-TFC S9700RTWV43TR-01B 7" Three Five Corp 800x480 LCD panel with >-resistive touch >- >-The panel is found on TI AM335x-evm. >- >-Required properties: >-- compatible: should be "tfc,s9700rtwv43tr-01b" >-- power-supply: See panel-common.txt >- >-Optional properties: >-- enable-gpios: GPIO pin to enable or disable the panel, if there is one >-- backlight: phandle of the backlight device attached to the panel >- >-This binding is compatible with the simple-panel binding, which is specified >-in simple-panel.txt in this directory. >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,33 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/tfc,s9700rtwv43tr-01b.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: TFC S9700RTWV43TR-01B 7" Three Five Corp 800x480 LCD panel with resistive touch >+ >+maintainers: >+ - Jyri Sarha <jsarha@ti.com> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+description: |+ >+ The panel is found on TI AM335x-evm. >+ >+allOf: >+ - $ref: panel-common.yaml# >+ >+properties: >+ compatible: >+ const: tfc,s9700rtwv43tr-01b >+ >+ enable-gpios: true >+ backlight: true >+ port: true >+ >+additionalProperties: false >+ >+required: >+ - compatible >+ - power-supply >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt 1969-12-31 18:00:00.000000000 -0600 >@@ -1,70 +0,0 @@ >-TPO TPG110 Panel >-================ >- >-This panel driver is a component that acts as an intermediary >-between an RGB output and a variety of panels. The panel >-driver is strapped up in electronics to the desired resolution >-and other properties, and has a control interface over 3WIRE >-SPI. By talking to the TPG110 over SPI, the strapped properties >-can be discovered and the hardware is therefore mostly >-self-describing. >- >- +--------+ >-SPI -> | TPO | -> physical display >-RGB -> | TPG110 | >- +--------+ >- >-If some electrical strap or alternate resolution is desired, >-this can be set up by taking software control of the display >-over the SPI interface. The interface can also adjust >-for properties of the display such as gamma correction and >-certain electrical driving levels. >- >-The TPG110 does not know the physical dimensions of the panel >-connected, so this needs to be specified in the device tree. >- >-It requires a GPIO line for control of its reset line. >- >-The serial protocol has line names that resemble I2C but the >-protocol is not I2C but 3WIRE SPI. >- >-Required properties: >-- compatible : one of: >- "ste,nomadik-nhk15-display", "tpo,tpg110" >- "tpo,tpg110" >-- grestb-gpios : panel reset GPIO >-- width-mm : see display/panel/panel-common.txt >-- height-mm : see display/panel/panel-common.txt >- >-The device needs to be a child of an SPI bus, see >-spi/spi-bus.txt. The SPI child must set the following >-properties: >-- spi-3wire >-- spi-max-frequency = <3000000>; >-as these are characteristics of this device. >- >-The device node can contain one 'port' child node with one child >-'endpoint' node, according to the bindings defined in >-media/video-interfaces.txt. This node should describe panel's video bus. >- >-Example >-------- >- >-panel: display@0 { >- compatible = "tpo,tpg110"; >- reg = <0>; >- spi-3wire; >- /* 320 ns min period ~= 3 MHz */ >- spi-max-frequency = <3000000>; >- /* Width and height from data sheet */ >- width-mm = <116>; >- height-mm = <87>; >- grestb-gpios = <&foo_gpio 5 GPIO_ACTIVE_LOW>; >- backlight = <&bl>; >- >- port { >- nomadik_clcd_panel: endpoint { >- remote-endpoint = <&foo>; >- }; >- }; >-}; >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml 2019-08-31 15:01:11.824736165 -0500 >@@ -0,0 +1,101 @@ >+# SPDX-License-Identifier: GPL-2.0 >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/display/panel/tpo,tpg110.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: TPO TPG110 Panel >+ >+maintainers: >+ - Linus Walleij <linus.walleij@linaro.org> >+ - Thierry Reding <thierry.reding@gmail.com> >+ >+description: |+ >+ This panel driver is a component that acts as an intermediary >+ between an RGB output and a variety of panels. The panel >+ driver is strapped up in electronics to the desired resolution >+ and other properties, and has a control interface over 3WIRE >+ SPI. By talking to the TPG110 over SPI, the strapped properties >+ can be discovered and the hardware is therefore mostly >+ self-describing. >+ >+ +--------+ >+ SPI -> | TPO | -> physical display >+ RGB -> | TPG110 | >+ +--------+ >+ >+ If some electrical strap or alternate resolution is desired, >+ this can be set up by taking software control of the display >+ over the SPI interface. The interface can also adjust >+ for properties of the display such as gamma correction and >+ certain electrical driving levels. >+ >+ The TPG110 does not know the physical dimensions of the panel >+ connected, so this needs to be specified in the device tree. >+ >+ It requires a GPIO line for control of its reset line. >+ >+ The serial protocol has line names that resemble I2C but the >+ protocol is not I2C but 3WIRE SPI. >+ >+ >+allOf: >+ - $ref: panel-common.yaml# >+ >+properties: >+ compatible: >+ oneOf: >+ - items: >+ - enum: >+ - ste,nomadik-nhk15-display >+ - const: tpo,tpg110 >+ - const: tpo,tpg110 >+ >+ reg: true >+ >+ grestb-gpios: >+ maxItems: 1 >+ description: panel reset GPIO >+ >+ spi-3wire: true >+ >+ spi-max-frequency: >+ const: 3000000 >+ >+required: >+ - compatible >+ - reg >+ - grestb-gpios >+ - width-mm >+ - height-mm >+ - spi-3wire >+ - spi-max-frequency >+ - port >+ >+examples: >+ - |+ >+ spi { >+ #address-cells = <1>; >+ #size-cells = <0>; >+ >+ panel: display@0 { >+ compatible = "tpo,tpg110"; >+ reg = <0>; >+ spi-3wire; >+ /* 320 ns min period ~= 3 MHz */ >+ spi-max-frequency = <3000000>; >+ /* Width and height from data sheet */ >+ width-mm = <116>; >+ height-mm = <87>; >+ grestb-gpios = <&foo_gpio 5 1>; >+ backlight = <&bl>; >+ >+ port { >+ nomadik_clcd_panel: endpoint { >+ remote-endpoint = <&foo>; >+ }; >+ }; >+ }; >+ }; >+ >+... >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -32,17 +32,6 @@ > - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl > - video port 1 for either a panel or subsequent encoder > >-the lvds panel described by >- Documentation/devicetree/bindings/display/panel/simple-panel.txt >- >-Panel required properties: >-- ports for remote LVDS output >- >-Panel optional properties: >-- data-mapping: should be "vesa-24","jeida-24" or "jeida-18". >-This describes decribed by: >- Documentation/devicetree/bindings/display/panel/panel-lvds.txt >- > Example: > > lvds_panel: lvds-panel { >diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/ssd1307fb.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/ssd1307fb.txt >--- linux-5.3-rc6/Documentation/devicetree/bindings/display/ssd1307fb.txt 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/ssd1307fb.txt 2019-08-31 15:01:11.824736165 -0500 >@@ -27,6 +27,15 @@ > - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles. > This needs to be the higher, the higher the capacitance > of the OLED's pixels is >+ - solomon,dclk-div: Clock divisor 1 to 16 >+ - solomon,dclk-frq: Clock frequency 0 to 15, higher value means higher >+ frequency >+ - solomon,lookup-table: 8 bit value array of current drive pulse widths for >+ BANK0, and colors A, B, and C. Each value in range >+ of 31 to 63 for pulse widths of 32 to 64. Color D >+ is always width 64. >+ - solomon,area-color-enable: Display uses color mode >+ - solomon,low-power. Display runs in low power mode > > [0]: Documentation/devicetree/bindings/pwm/pwm.txt > >@@ -46,4 +55,5 @@ > solomon,com-lrremap; > solomon,com-invdir; > solomon,com-offset = <32>; >+ solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>; > }; >diff -Naur linux-5.3-rc6/Documentation/gpu/drivers.rst linux-5.3-rc6-agd5fed/Documentation/gpu/drivers.rst >--- linux-5.3-rc6/Documentation/gpu/drivers.rst 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/gpu/drivers.rst 2019-08-31 15:01:11.824736165 -0500 >@@ -11,7 +11,6 @@ > meson > pl111 > tegra >- tinydrm > tve200 > v3d > vc4 >diff -Naur linux-5.3-rc6/Documentation/gpu/drm-kms-helpers.rst linux-5.3-rc6-agd5fed/Documentation/gpu/drm-kms-helpers.rst >--- linux-5.3-rc6/Documentation/gpu/drm-kms-helpers.rst 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/gpu/drm-kms-helpers.rst 2019-08-31 15:01:11.824736165 -0500 >@@ -263,6 +263,18 @@ > drm_dp_mst_topology_put_port > drm_dp_mst_get_mstb_malloc drm_dp_mst_put_mstb_malloc > >+MIPI DBI Helper Functions Reference >+=================================== >+ >+.. kernel-doc:: drivers/gpu/drm/drm_mipi_dbi.c >+ :doc: overview >+ >+.. kernel-doc:: include/drm/drm_mipi_dbi.h >+ :internal: >+ >+.. kernel-doc:: drivers/gpu/drm/drm_mipi_dbi.c >+ :export: >+ > MIPI DSI Helper Functions Reference > =================================== > >diff -Naur linux-5.3-rc6/Documentation/gpu/drm-mm.rst linux-5.3-rc6-agd5fed/Documentation/gpu/drm-mm.rst >--- linux-5.3-rc6/Documentation/gpu/drm-mm.rst 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/gpu/drm-mm.rst 2019-08-31 15:01:11.825736165 -0500 >@@ -433,43 +433,11 @@ > created for the OPTIMUS range of multi-gpu platforms. To userspace PRIME > buffers are dma-buf based file descriptors. > >-Overview and Driver Interface >------------------------------ >+Overview and Lifetime Rules >+--------------------------- > >-Similar to GEM global names, PRIME file descriptors are also used to >-share buffer objects across processes. They offer additional security: >-as file descriptors must be explicitly sent over UNIX domain sockets to >-be shared between applications, they can't be guessed like the globally >-unique GEM names. >- >-Drivers that support the PRIME API must set the DRIVER_PRIME bit in the >-struct :c:type:`struct drm_driver <drm_driver>` >-driver_features field, and implement the prime_handle_to_fd and >-prime_fd_to_handle operations. >- >-int (\*prime_handle_to_fd)(struct drm_device \*dev, struct drm_file >-\*file_priv, uint32_t handle, uint32_t flags, int \*prime_fd); int >-(\*prime_fd_to_handle)(struct drm_device \*dev, struct drm_file >-\*file_priv, int prime_fd, uint32_t \*handle); Those two operations >-convert a handle to a PRIME file descriptor and vice versa. Drivers must >-use the kernel dma-buf buffer sharing framework to manage the PRIME file >-descriptors. Similar to the mode setting API PRIME is agnostic to the >-underlying buffer object manager, as long as handles are 32bit unsigned >-integers. >- >-While non-GEM drivers must implement the operations themselves, GEM >-drivers must use the :c:func:`drm_gem_prime_handle_to_fd()` and >-:c:func:`drm_gem_prime_fd_to_handle()` helper functions. Those >-helpers rely on the driver gem_prime_export and gem_prime_import >-operations to create a dma-buf instance from a GEM object (dma-buf >-exporter role) and to create a GEM object from a dma-buf instance >-(dma-buf importer role). >- >-struct dma_buf \* (\*gem_prime_export)(struct drm_device \*dev, >-struct drm_gem_object \*obj, int flags); struct drm_gem_object \* >-(\*gem_prime_import)(struct drm_device \*dev, struct dma_buf >-\*dma_buf); These two operations are mandatory for GEM drivers that >-support PRIME. >+.. kernel-doc:: drivers/gpu/drm/drm_prime.c >+ :doc: overview and lifetime rules > > PRIME Helper Functions > ---------------------- >diff -Naur linux-5.3-rc6/Documentation/gpu/i915.rst linux-5.3-rc6-agd5fed/Documentation/gpu/i915.rst >--- linux-5.3-rc6/Documentation/gpu/i915.rst 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/gpu/i915.rst 2019-08-31 15:01:11.825736165 -0500 >@@ -430,31 +430,31 @@ > GuC > === > >+Firmware Layout >+------------------- >+ >+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h >+ :doc: Firmware Layout >+ > GuC-specific firmware loader > ---------------------------- > >-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c >+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c > :internal: > > GuC-based command submission > ---------------------------- > >-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c >+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > :doc: GuC-based command submission > >-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c >+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > :internal: > >-GuC Firmware Layout >-------------------- >- >-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h >- :doc: GuC Firmware Layout >- > GuC Address Space > ----------------- > >-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c >+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c > :doc: GuC Address Space > > Tracing >diff -Naur linux-5.3-rc6/Documentation/gpu/introduction.rst linux-5.3-rc6-agd5fed/Documentation/gpu/introduction.rst >--- linux-5.3-rc6/Documentation/gpu/introduction.rst 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/gpu/introduction.rst 2019-08-31 15:01:11.825736165 -0500 >@@ -51,6 +51,22 @@ > > Also read the :ref:`guidelines for the kernel documentation at large <doc_guide>`. > >+Documentation Requirements for kAPI >+----------------------------------- >+ >+All kernel APIs exported to other modules must be documented, including their >+datastructures and at least a short introductory section explaining the overall >+concepts. Documentation should be put into the code itself as kerneldoc comments >+as much as reasonable. >+ >+Do not blindly document everything, but document only what's relevant for driver >+authors: Internal functions of drm.ko and definitely static functions should not >+have formal kerneldoc comments. Use normal C comments if you feel like a comment >+is warranted. You may use kerneldoc syntax in the comment, but it shall not >+start with a /** kerneldoc marker. Similar for data structures, annotate >+anything entirely private with ``/* private: */`` comments as per the >+documentation guide. >+ > Getting Started > =============== > >diff -Naur linux-5.3-rc6/Documentation/gpu/tinydrm.rst linux-5.3-rc6-agd5fed/Documentation/gpu/tinydrm.rst >--- linux-5.3-rc6/Documentation/gpu/tinydrm.rst 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/gpu/tinydrm.rst 1969-12-31 18:00:00.000000000 -0600 >@@ -1,30 +0,0 @@ >-============================ >-drm/tinydrm Tiny DRM drivers >-============================ >- >-tinydrm is a collection of DRM drivers that are so small they can fit in a >-single source file. >- >-Helpers >-======= >- >-.. kernel-doc:: include/drm/tinydrm/tinydrm-helpers.h >- :internal: >- >-.. kernel-doc:: drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c >- :export: >- >-.. kernel-doc:: drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c >- :export: >- >-MIPI DBI Compatible Controllers >-=============================== >- >-.. kernel-doc:: drivers/gpu/drm/tinydrm/mipi-dbi.c >- :doc: overview >- >-.. kernel-doc:: include/drm/tinydrm/mipi-dbi.h >- :internal: >- >-.. kernel-doc:: drivers/gpu/drm/tinydrm/mipi-dbi.c >- :export: >diff -Naur linux-5.3-rc6/Documentation/gpu/todo.rst linux-5.3-rc6-agd5fed/Documentation/gpu/todo.rst >--- linux-5.3-rc6/Documentation/gpu/todo.rst 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/gpu/todo.rst 2019-08-31 15:01:11.825736165 -0500 >@@ -162,7 +162,7 @@ > > A lot of drivers forward gem mmap calls to dma-buf mmap for imported buffers. > And also a lot of them forward dma-buf mmap to the gem mmap implementations. >-Would be great to refactor this all into a set of small common helpers. >+There's drm_gem_prime_mmap() for this now, but still needs to be rolled out. > > Contact: Daniel Vetter > >@@ -196,15 +196,6 @@ > > Contact: Daniel Vetter, Noralf Tronnes > >-Remove the ->gem_prime_res_obj callback >--------------------------------------------- >- >-The ->gem_prime_res_obj callback can be removed from drivers by using the >-reservation_object in the drm_gem_object. It may also be possible to use the >-generic drm_gem_reservation_object_wait helper for waiting for a bo. >- >-Contact: Daniel Vetter >- > idr_init_base() > --------------- > >@@ -215,22 +206,13 @@ > > Contact: Daniel Vetter > >-Defaults for .gem_prime_import and export >------------------------------------------ >- >-Most drivers don't need to set drm_driver->gem_prime_import and >-->gem_prime_export now that drm_gem_prime_import() and drm_gem_prime_export() >-are the default. >- > struct drm_gem_object_funcs > --------------------------- > > GEM objects can now have a function table instead of having the callbacks on the > DRM driver struct. This is now the preferred way and drivers can be moved over. > >-DRM_GEM_CMA_VMAP_DRIVER_OPS, DRM_GEM_SHMEM_DRIVER_OPS already support this, but >-DRM_GEM_VRAM_DRIVER_PRIME does not yet and needs to be aligned with the previous >-two. We also need a 2nd version of the CMA define that doesn't require the >+We also need a 2nd version of the CMA define that doesn't require the > vmapping to be present (different hook for prime importing). Plus this needs to > be rolled out to all drivers using their own implementations, too. > >@@ -317,19 +299,6 @@ > > Contact: Daniel Vetter > >-Add missing kerneldoc for exported functions >--------------------------------------------- >- >-The DRM reference documentation is still lacking kerneldoc in a few areas. The >-task would be to clean up interfaces like moving functions around between >-files to better group them and improving the interfaces like dropping return >-values for functions that never fail. Then write kerneldoc for all exported >-functions and an overview section and integrate it all into the drm book. >- >-See https://dri.freedesktop.org/docs/drm/ for what's there already. >- >-Contact: Daniel Vetter >- > Make panic handling work > ------------------------ > >@@ -393,6 +362,9 @@ > this (together with the drm_minor->drm_device move) would allow us to remove > debugfs_init. > >+- Drop the return code and error checking from all debugfs functions. Greg KH is >+ working on this already. >+ > Contact: Daniel Vetter > > KMS cleanups >@@ -440,38 +412,21 @@ > > Contact: Daniel Vetter > >-Driver Specific >-=============== >+Backlight Refactoring >+--------------------- > >-tinydrm >-------- >+Backlight drivers have a triple enable/disable state, which is a bit overkill. >+Plan to fix this: > >-Tinydrm is the helper driver for really simple fb drivers. The goal is to make >-those drivers as simple as possible, so lots of room for refactoring: >+1. Roll out backlight_enable() and backlight_disable() helpers everywhere. This >+ has started already. >+2. In all, only look at one of the three status bits set by the above helpers. >+3. Remove the other two status bits. > >-- backlight helpers, probably best to put them into a new drm_backlight.c. >- This is because drivers/video is de-facto unmaintained. We could also >- move drivers/video/backlight to drivers/gpu/backlight and take it all >- over within drm-misc, but that's more work. Backlight helpers require a fair >- bit of reworking and refactoring. A simple example is the enabling of a backlight. >- Tinydrm has helpers for this. It would be good if other drivers can also use the >- helper. However, there are various cases we need to consider i.e different >- drivers seem to have different ways of enabling/disabling a backlight. >- We also need to consider the backlight drivers (like gpio_backlight). The situation >- is further complicated by the fact that the backlight is tied to fbdev >- via fb_notifier_callback() which has complicated logic. For further details, refer >- to the following discussion thread: >- https://groups.google.com/forum/#!topic/outreachy-kernel/8rBe30lwtdA >- >-- spi helpers, probably best put into spi core/helper code. Thierry said >- the spi maintainer is fast&reactive, so shouldn't be a big issue. >- >-- extract the mipi-dbi helper (well, the non-tinydrm specific parts at >- least) into a separate helper, like we have for mipi-dsi already. Or follow >- one of the ideas for having a shared dsi/dbi helper, abstracting away the >- transport details more. >+Contact: Daniel Vetter > >-Contact: Noralf Trønnes, Daniel Vetter >+Driver Specific >+=============== > > AMD DC Display Driver > --------------------- >diff -Naur linux-5.3-rc6/Documentation/media/uapi/v4l/subdev-formats.rst linux-5.3-rc6-agd5fed/Documentation/media/uapi/v4l/subdev-formats.rst >--- linux-5.3-rc6/Documentation/media/uapi/v4l/subdev-formats.rst 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/Documentation/media/uapi/v4l/subdev-formats.rst 2019-08-31 15:01:11.825736165 -0500 >@@ -1305,6 +1305,113 @@ > - g\ :sub:`6` > - g\ :sub:`5` > - g\ :sub:`4` >+ * .. _MEDIA-BUS-FMT-RGB888-3X8: >+ >+ - MEDIA_BUS_FMT_RGB888_3X8 >+ - 0x101c >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - r\ :sub:`7` >+ - r\ :sub:`6` >+ - r\ :sub:`5` >+ - r\ :sub:`4` >+ - r\ :sub:`3` >+ - r\ :sub:`2` >+ - r\ :sub:`1` >+ - r\ :sub:`0` >+ * - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - g\ :sub:`7` >+ - g\ :sub:`6` >+ - g\ :sub:`5` >+ - g\ :sub:`4` >+ - g\ :sub:`3` >+ - g\ :sub:`2` >+ - g\ :sub:`1` >+ - g\ :sub:`0` >+ * - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - >+ - b\ :sub:`7` >+ - b\ :sub:`6` >+ - b\ :sub:`5` >+ - b\ :sub:`4` >+ - b\ :sub:`3` >+ - b\ :sub:`2` >+ - b\ :sub:`1` >+ - b\ :sub:`0` > * .. _MEDIA-BUS-FMT-ARGB888-1X32: > > - MEDIA_BUS_FMT_ARGB888_1X32 >diff -Naur linux-5.3-rc6/drivers/dma-buf/dma-fence-chain.c linux-5.3-rc6-agd5fed/drivers/dma-buf/dma-fence-chain.c >--- linux-5.3-rc6/drivers/dma-buf/dma-fence-chain.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/dma-buf/dma-fence-chain.c 2019-08-31 15:01:11.833736166 -0500 >@@ -178,8 +178,30 @@ > static void dma_fence_chain_release(struct dma_fence *fence) > { > struct dma_fence_chain *chain = to_dma_fence_chain(fence); >+ struct dma_fence *prev; >+ >+ /* Manually unlink the chain as much as possible to avoid recursion >+ * and potential stack overflow. >+ */ >+ while ((prev = rcu_dereference_protected(chain->prev, true))) { >+ struct dma_fence_chain *prev_chain; >+ >+ if (kref_read(&prev->refcount) > 1) >+ break; >+ >+ prev_chain = to_dma_fence_chain(prev); >+ if (!prev_chain) >+ break; >+ >+ /* No need for atomic operations since we hold the last >+ * reference to prev_chain. >+ */ >+ chain->prev = prev_chain->prev; >+ RCU_INIT_POINTER(prev_chain->prev, NULL); >+ dma_fence_put(prev); >+ } >+ dma_fence_put(prev); > >- dma_fence_put(rcu_dereference_protected(chain->prev, true)); > dma_fence_put(chain->fence); > dma_fence_free(fence); > } >diff -Naur linux-5.3-rc6/drivers/dma-buf/reservation.c linux-5.3-rc6-agd5fed/drivers/dma-buf/reservation.c >--- linux-5.3-rc6/drivers/dma-buf/reservation.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/dma-buf/reservation.c 2019-08-31 15:01:11.838736166 -0500 >@@ -56,6 +56,85 @@ > EXPORT_SYMBOL(reservation_seqcount_string); > > /** >+ * reservation_object_list_alloc - allocate fence list >+ * @shared_max: number of fences we need space for >+ * >+ * Allocate a new reservation_object_list and make sure to correctly initialize >+ * shared_max. >+ */ >+static struct reservation_object_list * >+reservation_object_list_alloc(unsigned int shared_max) >+{ >+ struct reservation_object_list *list; >+ >+ list = kmalloc(offsetof(typeof(*list), shared[shared_max]), GFP_KERNEL); >+ if (!list) >+ return NULL; >+ >+ list->shared_max = (ksize(list) - offsetof(typeof(*list), shared)) / >+ sizeof(*list->shared); >+ >+ return list; >+} >+ >+/** >+ * reservation_object_list_free - free fence list >+ * @list: list to free >+ * >+ * Free a reservation_object_list and make sure to drop all references. >+ */ >+static void reservation_object_list_free(struct reservation_object_list *list) >+{ >+ unsigned int i; >+ >+ if (!list) >+ return; >+ >+ for (i = 0; i < list->shared_count; ++i) >+ dma_fence_put(rcu_dereference_protected(list->shared[i], true)); >+ >+ kfree_rcu(list, rcu); >+} >+ >+/** >+ * reservation_object_init - initialize a reservation object >+ * @obj: the reservation object >+ */ >+void reservation_object_init(struct reservation_object *obj) >+{ >+ ww_mutex_init(&obj->lock, &reservation_ww_class); >+ >+ __seqcount_init(&obj->seq, reservation_seqcount_string, >+ &reservation_seqcount_class); >+ RCU_INIT_POINTER(obj->fence, NULL); >+ RCU_INIT_POINTER(obj->fence_excl, NULL); >+} >+EXPORT_SYMBOL(reservation_object_init); >+ >+/** >+ * reservation_object_fini - destroys a reservation object >+ * @obj: the reservation object >+ */ >+void reservation_object_fini(struct reservation_object *obj) >+{ >+ struct reservation_object_list *fobj; >+ struct dma_fence *excl; >+ >+ /* >+ * This object should be dead and all references must have >+ * been released to it, so no need to be protected with rcu. >+ */ >+ excl = rcu_dereference_protected(obj->fence_excl, 1); >+ if (excl) >+ dma_fence_put(excl); >+ >+ fobj = rcu_dereference_protected(obj->fence, 1); >+ reservation_object_list_free(fobj); >+ ww_mutex_destroy(&obj->lock); >+} >+EXPORT_SYMBOL(reservation_object_fini); >+ >+/** > * reservation_object_reserve_shared - Reserve space to add shared fences to > * a reservation_object. > * @obj: reservation object >@@ -87,7 +166,7 @@ > max = 4; > } > >- new = kmalloc(offsetof(typeof(*new), shared[max]), GFP_KERNEL); >+ new = reservation_object_list_alloc(max); > if (!new) > return -ENOMEM; > >@@ -108,23 +187,22 @@ > RCU_INIT_POINTER(new->shared[j++], fence); > } > new->shared_count = j; >- new->shared_max = max; > >- preempt_disable(); >- write_seqcount_begin(&obj->seq); > /* >- * RCU_INIT_POINTER can be used here, >- * seqcount provides the necessary barriers >+ * We are not changing the effective set of fences here so can >+ * merely update the pointer to the new array; both existing >+ * readers and new readers will see exactly the same set of >+ * active (unsignaled) shared fences. Individual fences and the >+ * old array are protected by RCU and so will not vanish under >+ * the gaze of the rcu_read_lock() readers. > */ >- RCU_INIT_POINTER(obj->fence, new); >- write_seqcount_end(&obj->seq); >- preempt_enable(); >+ rcu_assign_pointer(obj->fence, new); > > if (!old) > return 0; > > /* Drop the references to the signaled fences */ >- for (i = k; i < new->shared_max; ++i) { >+ for (i = k; i < max; ++i) { > struct dma_fence *fence; > > fence = rcu_dereference_protected(new->shared[i], >@@ -149,6 +227,7 @@ > struct dma_fence *fence) > { > struct reservation_object_list *fobj; >+ struct dma_fence *old; > unsigned int i, count; > > dma_fence_get(fence); >@@ -162,18 +241,16 @@ > write_seqcount_begin(&obj->seq); > > for (i = 0; i < count; ++i) { >- struct dma_fence *old_fence; > >- old_fence = rcu_dereference_protected(fobj->shared[i], >- reservation_object_held(obj)); >- if (old_fence->context == fence->context || >- dma_fence_is_signaled(old_fence)) { >- dma_fence_put(old_fence); >+ old = rcu_dereference_protected(fobj->shared[i], >+ reservation_object_held(obj)); >+ if (old->context == fence->context || >+ dma_fence_is_signaled(old)) > goto replace; >- } > } > > BUG_ON(fobj->shared_count >= fobj->shared_max); >+ old = NULL; > count++; > > replace: >@@ -183,6 +260,7 @@ > > write_seqcount_end(&obj->seq); > preempt_enable(); >+ dma_fence_put(old); > } > EXPORT_SYMBOL(reservation_object_add_shared_fence); > >@@ -239,7 +317,6 @@ > { > struct reservation_object_list *src_list, *dst_list; > struct dma_fence *old, *new; >- size_t size; > unsigned i; > > reservation_object_assert_held(dst); >@@ -251,10 +328,9 @@ > if (src_list) { > unsigned shared_count = src_list->shared_count; > >- size = offsetof(typeof(*src_list), shared[shared_count]); > rcu_read_unlock(); > >- dst_list = kmalloc(size, GFP_KERNEL); >+ dst_list = reservation_object_list_alloc(shared_count); > if (!dst_list) > return -ENOMEM; > >@@ -266,7 +342,6 @@ > } > > dst_list->shared_count = 0; >- dst_list->shared_max = shared_count; > for (i = 0; i < src_list->shared_count; ++i) { > struct dma_fence *fence; > >@@ -276,7 +351,7 @@ > continue; > > if (!dma_fence_get_rcu(fence)) { >- kfree(dst_list); >+ reservation_object_list_free(dst_list); > src_list = rcu_dereference(src->fence); > goto retry; > } >@@ -306,8 +381,7 @@ > write_seqcount_end(&dst->seq); > preempt_enable(); > >- if (src_list) >- kfree_rcu(src_list, rcu); >+ reservation_object_list_free(src_list); > dma_fence_put(old); > > return 0; >@@ -385,13 +459,6 @@ > if (!dma_fence_get_rcu(shared[i])) > break; > } >- >- if (!pfence_excl && fence_excl) { >- shared[i] = fence_excl; >- fence_excl = NULL; >- ++i; >- ++shared_count; >- } > } > > if (i != shared_count || read_seqcount_retry(&obj->seq, seq)) { >@@ -406,6 +473,11 @@ > rcu_read_unlock(); > } while (ret); > >+ if (pfence_excl) >+ *pfence_excl = fence_excl; >+ else if (fence_excl) >+ shared[++shared_count] = fence_excl; >+ > if (!shared_count) { > kfree(shared); > shared = NULL; >@@ -413,9 +485,6 @@ > > *pshared_count = shared_count; > *pshared = shared; >- if (pfence_excl) >- *pfence_excl = fence_excl; >- > return ret; > } > EXPORT_SYMBOL_GPL(reservation_object_get_fences_rcu); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 2019-08-31 15:01:11.839736167 -0500 >@@ -0,0 +1,323 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ */ >+ >+#undef pr_fmt >+#define pr_fmt(fmt) "kfd2kgd: " fmt >+ >+#include <linux/module.h> >+#include <linux/fdtable.h> >+#include <linux/uaccess.h> >+#include <linux/mmu_context.h> >+#include <linux/firmware.h> >+#include "amdgpu.h" >+#include "amdgpu_amdkfd.h" >+#include "sdma0/sdma0_4_2_2_offset.h" >+#include "sdma0/sdma0_4_2_2_sh_mask.h" >+#include "sdma1/sdma1_4_2_2_offset.h" >+#include "sdma1/sdma1_4_2_2_sh_mask.h" >+#include "sdma2/sdma2_4_2_2_offset.h" >+#include "sdma2/sdma2_4_2_2_sh_mask.h" >+#include "sdma3/sdma3_4_2_2_offset.h" >+#include "sdma3/sdma3_4_2_2_sh_mask.h" >+#include "sdma4/sdma4_4_2_2_offset.h" >+#include "sdma4/sdma4_4_2_2_sh_mask.h" >+#include "sdma5/sdma5_4_2_2_offset.h" >+#include "sdma5/sdma5_4_2_2_sh_mask.h" >+#include "sdma6/sdma6_4_2_2_offset.h" >+#include "sdma6/sdma6_4_2_2_sh_mask.h" >+#include "sdma7/sdma7_4_2_2_offset.h" >+#include "sdma7/sdma7_4_2_2_sh_mask.h" >+#include "v9_structs.h" >+#include "soc15.h" >+#include "soc15d.h" >+#include "amdgpu_amdkfd_gfx_v9.h" >+ >+#define HQD_N_REGS 56 >+#define DUMP_REG(addr) do { \ >+ if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ >+ break; \ >+ (*dump)[i][0] = (addr) << 2; \ >+ (*dump)[i++][1] = RREG32(addr); \ >+ } while (0) >+ >+static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) >+{ >+ return (struct amdgpu_device *)kgd; >+} >+ >+static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) >+{ >+ return (struct v9_sdma_mqd *)mqd; >+} >+ >+static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, >+ unsigned int engine_id, >+ unsigned int queue_id) >+{ >+ uint32_t base[8] = { >+ SOC15_REG_OFFSET(SDMA0, 0, >+ mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, >+ SOC15_REG_OFFSET(SDMA1, 0, >+ mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL, >+ SOC15_REG_OFFSET(SDMA2, 0, >+ mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL, >+ SOC15_REG_OFFSET(SDMA3, 0, >+ mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL, >+ SOC15_REG_OFFSET(SDMA4, 0, >+ mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL, >+ SOC15_REG_OFFSET(SDMA5, 0, >+ mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL, >+ SOC15_REG_OFFSET(SDMA6, 0, >+ mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL, >+ SOC15_REG_OFFSET(SDMA7, 0, >+ mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL >+ }; >+ uint32_t retval; >+ >+ retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - >+ mmSDMA0_RLC0_RB_CNTL); >+ >+ pr_debug("sdma base address: 0x%x\n", retval); >+ >+ return retval; >+} >+ >+static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, >+ u32 instance, u32 offset) >+{ >+ switch (instance) { >+ case 0: >+ return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); >+ case 1: >+ return (adev->reg_offset[SDMA1_HWIP][0][1] + offset); >+ case 2: >+ return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); >+ case 3: >+ return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); >+ case 4: >+ return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); >+ case 5: >+ return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); >+ case 6: >+ return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); >+ case 7: >+ return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); >+ default: >+ break; >+ } >+ return 0; >+} >+ >+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, >+ uint32_t __user *wptr, struct mm_struct *mm) >+{ >+ struct amdgpu_device *adev = get_amdgpu_device(kgd); >+ struct v9_sdma_mqd *m; >+ uint32_t sdma_base_addr, sdmax_gfx_context_cntl; >+ unsigned long end_jiffies; >+ uint32_t data; >+ uint64_t data64; >+ uint64_t __user *wptr64 = (uint64_t __user *)wptr; >+ >+ m = get_sdma_mqd(mqd); >+ sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, >+ m->sdma_queue_id); >+ sdmax_gfx_context_cntl = sdma_v4_0_get_reg_offset(adev, >+ m->sdma_engine_id, mmSDMA0_GFX_CONTEXT_CNTL); >+ >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, >+ m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); >+ >+ end_jiffies = msecs_to_jiffies(2000) + jiffies; >+ while (true) { >+ data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); >+ if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) >+ break; >+ if (time_after(jiffies, end_jiffies)) >+ return -ETIME; >+ usleep_range(500, 1000); >+ } >+ data = RREG32(sdmax_gfx_context_cntl); >+ data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, >+ RESUME_CTX, 0); >+ WREG32(sdmax_gfx_context_cntl, data); >+ >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, >+ m->sdmax_rlcx_doorbell_offset); >+ >+ data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, >+ ENABLE, 1); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, >+ m->sdmax_rlcx_rb_rptr_hi); >+ >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); >+ if (read_user_wptr(mm, wptr64, data64)) { >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, >+ lower_32_bits(data64)); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, >+ upper_32_bits(data64)); >+ } else { >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, >+ m->sdmax_rlcx_rb_rptr); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, >+ m->sdmax_rlcx_rb_rptr_hi); >+ } >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); >+ >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, >+ m->sdmax_rlcx_rb_base_hi); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, >+ m->sdmax_rlcx_rb_rptr_addr_lo); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, >+ m->sdmax_rlcx_rb_rptr_addr_hi); >+ >+ data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, >+ RB_ENABLE, 1); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); >+ >+ return 0; >+} >+ >+static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, >+ uint32_t engine_id, uint32_t queue_id, >+ uint32_t (**dump)[2], uint32_t *n_regs) >+{ >+ struct amdgpu_device *adev = get_amdgpu_device(kgd); >+ uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); >+ uint32_t i = 0, reg; >+#undef HQD_N_REGS >+#define HQD_N_REGS (19+6+7+10) >+ >+ *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); >+ if (*dump == NULL) >+ return -ENOMEM; >+ >+ for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) >+ DUMP_REG(sdma_base_addr + reg); >+ for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) >+ DUMP_REG(sdma_base_addr + reg); >+ for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; >+ reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) >+ DUMP_REG(sdma_base_addr + reg); >+ for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; >+ reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) >+ DUMP_REG(sdma_base_addr + reg); >+ >+ WARN_ON_ONCE(i != HQD_N_REGS); >+ *n_regs = i; >+ >+ return 0; >+} >+ >+static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) >+{ >+ struct amdgpu_device *adev = get_amdgpu_device(kgd); >+ struct v9_sdma_mqd *m; >+ uint32_t sdma_base_addr; >+ uint32_t sdma_rlc_rb_cntl; >+ >+ m = get_sdma_mqd(mqd); >+ sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, >+ m->sdma_queue_id); >+ >+ sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); >+ >+ if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) >+ return true; >+ >+ return false; >+} >+ >+static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, >+ unsigned int utimeout) >+{ >+ struct amdgpu_device *adev = get_amdgpu_device(kgd); >+ struct v9_sdma_mqd *m; >+ uint32_t sdma_base_addr; >+ uint32_t temp; >+ unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; >+ >+ m = get_sdma_mqd(mqd); >+ sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, >+ m->sdma_queue_id); >+ >+ temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); >+ temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); >+ >+ while (true) { >+ temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); >+ if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) >+ break; >+ if (time_after(jiffies, end_jiffies)) >+ return -ETIME; >+ usleep_range(500, 1000); >+ } >+ >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); >+ WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, >+ RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | >+ SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); >+ >+ m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); >+ m->sdmax_rlcx_rb_rptr_hi = >+ RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); >+ >+ return 0; >+} >+ >+static const struct kfd2kgd_calls kfd2kgd = { >+ .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, >+ .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, >+ .init_interrupts = kgd_gfx_v9_init_interrupts, >+ .hqd_load = kgd_gfx_v9_hqd_load, >+ .hqd_sdma_load = kgd_hqd_sdma_load, >+ .hqd_dump = kgd_gfx_v9_hqd_dump, >+ .hqd_sdma_dump = kgd_hqd_sdma_dump, >+ .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, >+ .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, >+ .hqd_destroy = kgd_gfx_v9_hqd_destroy, >+ .hqd_sdma_destroy = kgd_hqd_sdma_destroy, >+ .address_watch_disable = kgd_gfx_v9_address_watch_disable, >+ .address_watch_execute = kgd_gfx_v9_address_watch_execute, >+ .wave_control_execute = kgd_gfx_v9_wave_control_execute, >+ .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset, >+ .get_atc_vmid_pasid_mapping_pasid = >+ kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid, >+ .get_atc_vmid_pasid_mapping_valid = >+ kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid, >+ .set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va, >+ .get_tile_config = kgd_gfx_v9_get_tile_config, >+ .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, >+ .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs, >+ .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid, >+ .get_hive_id = amdgpu_amdkfd_get_hive_id, >+}; >+ >+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void) >+{ >+ return (struct kfd2kgd_calls *)&kfd2kgd; >+} >+ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 2019-08-31 15:01:11.839736167 -0500 >@@ -87,7 +87,12 @@ > case CHIP_RAVEN: > kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions(); > break; >+ case CHIP_ARCTURUS: >+ kfd2kgd = amdgpu_amdkfd_arcturus_get_functions(); >+ break; > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions(); > break; > default: >@@ -651,8 +656,12 @@ > { > struct amdgpu_device *adev = (struct amdgpu_device *)kgd; > >- if (adev->powerplay.pp_funcs && >- adev->powerplay.pp_funcs->switch_power_profile) >+ if (is_support_sw_smu(adev)) >+ smu_switch_power_profile(&adev->smu, >+ PP_SMC_POWER_PROFILE_COMPUTE, >+ !idle); >+ else if (adev->powerplay.pp_funcs && >+ adev->powerplay.pp_funcs->switch_power_profile) > amdgpu_dpm_switch_power_profile(adev, > PP_SMC_POWER_PROFILE_COMPUTE, > !idle); >@@ -714,6 +723,11 @@ > { > return NULL; > } >+ >+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void) >+{ >+ return NULL; >+} > > struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void) > { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 2019-08-31 15:01:11.839736167 -0500 >@@ -27,7 +27,6 @@ > #include <linux/uaccess.h> > #include <linux/firmware.h> > #include <linux/mmu_context.h> >-#include <drm/drmP.h> > #include "amdgpu.h" > #include "amdgpu_amdkfd.h" > #include "amdgpu_ucode.h" >@@ -802,42 +801,6 @@ > return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; > } > >-static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) >-{ >- struct amdgpu_device *adev = (struct amdgpu_device *) kgd; >- uint32_t req = (1 << vmid) | >- (0 << GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT) |/* legacy */ >- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK | >- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK | >- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK | >- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK | >- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK; >- >- mutex_lock(&adev->srbm_mutex); >- >- /* Use light weight invalidation. >- * >- * TODO 1: agree on the right set of invalidation registers for >- * KFD use. Use the last one for now. Invalidate only GCHUB as >- * SDMA is now moved to GCHUB >- * >- * TODO 2: support range-based invalidation, requires kfg2kgd >- * interface change >- */ >- WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32), >- 0xffffffff); >- WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32), >- 0x0000001f); >- >- WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ), req); >- >- while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK)) & >- (1 << vmid))) >- cpu_relax(); >- >- mutex_unlock(&adev->srbm_mutex); >-} >- > static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid) > { > signed long r; >@@ -878,7 +841,8 @@ > if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { > if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid) > == pasid) { >- write_vmid_invalidate_request(kgd, vmid); >+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, >+ AMDGPU_GFXHUB_0, 0); > break; > } > } >@@ -896,7 +860,7 @@ > return 0; > } > >- write_vmid_invalidate_request(kgd, vmid); >+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); > return 0; > } > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 2019-08-31 15:01:11.839736167 -0500 >@@ -47,6 +47,7 @@ > #include "soc15d.h" > #include "mmhub_v1_0.h" > #include "gfxhub_v1_0.h" >+#include "gmc_v9_0.h" > > > #define V9_PIPE_PER_MEC (4) >@@ -58,66 +59,11 @@ > RESET_WAVES > }; > >-/* >- * Register access functions >- */ >- >-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, >- uint32_t sh_mem_config, >- uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, >- uint32_t sh_mem_bases); >-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, >- unsigned int vmid); >-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); >-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, >- uint32_t queue_id, uint32_t __user *wptr, >- uint32_t wptr_shift, uint32_t wptr_mask, >- struct mm_struct *mm); >-static int kgd_hqd_dump(struct kgd_dev *kgd, >- uint32_t pipe_id, uint32_t queue_id, >- uint32_t (**dump)[2], uint32_t *n_regs); >-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, >- uint32_t __user *wptr, struct mm_struct *mm); >-static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, >- uint32_t engine_id, uint32_t queue_id, >- uint32_t (**dump)[2], uint32_t *n_regs); >-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, >- uint32_t pipe_id, uint32_t queue_id); >-static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); >-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, >- enum kfd_preempt_type reset_type, >- unsigned int utimeout, uint32_t pipe_id, >- uint32_t queue_id); >-static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, >- unsigned int utimeout); >-static int kgd_address_watch_disable(struct kgd_dev *kgd); >-static int kgd_address_watch_execute(struct kgd_dev *kgd, >- unsigned int watch_point_id, >- uint32_t cntl_val, >- uint32_t addr_hi, >- uint32_t addr_lo); >-static int kgd_wave_control_execute(struct kgd_dev *kgd, >- uint32_t gfx_index_val, >- uint32_t sq_cmd); >-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, >- unsigned int watch_point_id, >- unsigned int reg_offset); >- >-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, >- uint8_t vmid); >-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, >- uint8_t vmid); >-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, >- uint64_t page_table_base); >-static void set_scratch_backing_va(struct kgd_dev *kgd, >- uint64_t va, uint32_t vmid); >-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); >-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); > > /* Because of REG_GET_FIELD() being used, we put this function in the > * asic specific file. > */ >-static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, >+int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd, > struct tile_config *config) > { > struct amdgpu_device *adev = (struct amdgpu_device *)kgd; >@@ -135,39 +81,6 @@ > return 0; > } > >-static const struct kfd2kgd_calls kfd2kgd = { >- .program_sh_mem_settings = kgd_program_sh_mem_settings, >- .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, >- .init_interrupts = kgd_init_interrupts, >- .hqd_load = kgd_hqd_load, >- .hqd_sdma_load = kgd_hqd_sdma_load, >- .hqd_dump = kgd_hqd_dump, >- .hqd_sdma_dump = kgd_hqd_sdma_dump, >- .hqd_is_occupied = kgd_hqd_is_occupied, >- .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, >- .hqd_destroy = kgd_hqd_destroy, >- .hqd_sdma_destroy = kgd_hqd_sdma_destroy, >- .address_watch_disable = kgd_address_watch_disable, >- .address_watch_execute = kgd_address_watch_execute, >- .wave_control_execute = kgd_wave_control_execute, >- .address_watch_get_offset = kgd_address_watch_get_offset, >- .get_atc_vmid_pasid_mapping_pasid = >- get_atc_vmid_pasid_mapping_pasid, >- .get_atc_vmid_pasid_mapping_valid = >- get_atc_vmid_pasid_mapping_valid, >- .set_scratch_backing_va = set_scratch_backing_va, >- .get_tile_config = amdgpu_amdkfd_get_tile_config, >- .set_vm_context_page_table_base = set_vm_context_page_table_base, >- .invalidate_tlbs = invalidate_tlbs, >- .invalidate_tlbs_vmid = invalidate_tlbs_vmid, >- .get_hive_id = amdgpu_amdkfd_get_hive_id, >-}; >- >-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) >-{ >- return (struct kfd2kgd_calls *)&kfd2kgd; >-} >- > static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) > { > return (struct amdgpu_device *)kgd; >@@ -215,7 +128,7 @@ > unlock_srbm(kgd); > } > >-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, >+void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, > uint32_t sh_mem_config, > uint32_t sh_mem_ape1_base, > uint32_t sh_mem_ape1_limit, >@@ -232,7 +145,7 @@ > unlock_srbm(kgd); > } > >-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, >+int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, > unsigned int vmid) > { > struct amdgpu_device *adev = get_amdgpu_device(kgd); >@@ -293,7 +206,7 @@ > * but still works > */ > >-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) >+int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) > { > struct amdgpu_device *adev = get_amdgpu_device(kgd); > uint32_t mec; >@@ -343,7 +256,7 @@ > return (struct v9_sdma_mqd *)mqd; > } > >-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, >+int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, > uint32_t queue_id, uint32_t __user *wptr, > uint32_t wptr_shift, uint32_t wptr_mask, > struct mm_struct *mm) >@@ -438,7 +351,7 @@ > return 0; > } > >-static int kgd_hqd_dump(struct kgd_dev *kgd, >+int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd, > uint32_t pipe_id, uint32_t queue_id, > uint32_t (**dump)[2], uint32_t *n_regs) > { >@@ -575,7 +488,7 @@ > return 0; > } > >-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, >+bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, > uint32_t pipe_id, uint32_t queue_id) > { > struct amdgpu_device *adev = get_amdgpu_device(kgd); >@@ -616,7 +529,7 @@ > return false; > } > >-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, >+int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd, > enum kfd_preempt_type reset_type, > unsigned int utimeout, uint32_t pipe_id, > uint32_t queue_id) >@@ -704,7 +617,7 @@ > return 0; > } > >-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, >+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, > uint8_t vmid) > { > uint32_t reg; >@@ -715,7 +628,7 @@ > return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; > } > >-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, >+uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, > uint8_t vmid) > { > uint32_t reg; >@@ -754,10 +667,10 @@ > return 0; > } > >-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) >+int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) > { > struct amdgpu_device *adev = (struct amdgpu_device *) kgd; >- int vmid; >+ int vmid, i; > struct amdgpu_ring *ring = &adev->gfx.kiq.ring; > uint32_t flush_type = 0; > >@@ -773,11 +686,12 @@ > for (vmid = 0; vmid < 16; vmid++) { > if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) > continue; >- if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { >- if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid) >+ if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { >+ if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(kgd, vmid) > == pasid) { >- amdgpu_gmc_flush_gpu_tlb(adev, vmid, >- flush_type); >+ for (i = 0; i < adev->num_vmhubs; i++) >+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, >+ i, flush_type); > break; > } > } >@@ -786,9 +700,10 @@ > return 0; > } > >-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) >+int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) > { > struct amdgpu_device *adev = (struct amdgpu_device *) kgd; >+ int i; > > if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { > pr_err("non kfd vmid %d\n", vmid); >@@ -810,16 +725,18 @@ > * TODO 2: support range-based invalidation, requires kfg2kgd > * interface change > */ >- amdgpu_gmc_flush_gpu_tlb(adev, vmid, 0); >+ for (i = 0; i < adev->num_vmhubs; i++) >+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); >+ > return 0; > } > >-static int kgd_address_watch_disable(struct kgd_dev *kgd) >+int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd) > { > return 0; > } > >-static int kgd_address_watch_execute(struct kgd_dev *kgd, >+int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd, > unsigned int watch_point_id, > uint32_t cntl_val, > uint32_t addr_hi, >@@ -828,7 +745,7 @@ > return 0; > } > >-static int kgd_wave_control_execute(struct kgd_dev *kgd, >+int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd, > uint32_t gfx_index_val, > uint32_t sq_cmd) > { >@@ -853,14 +770,14 @@ > return 0; > } > >-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, >+uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd, > unsigned int watch_point_id, > unsigned int reg_offset) > { > return 0; > } > >-static void set_scratch_backing_va(struct kgd_dev *kgd, >+void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd, > uint64_t va, uint32_t vmid) > { > /* No longer needed on GFXv9. The scratch base address is >@@ -869,7 +786,7 @@ > */ > } > >-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, >+void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, > uint64_t page_table_base) > { > struct amdgpu_device *adev = get_amdgpu_device(kgd); >@@ -884,7 +801,45 @@ > * now, all processes share the same address space size, like > * on GFX8 and older. > */ >- mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); >+ if (adev->asic_type == CHIP_ARCTURUS) { >+ /* Two MMHUBs */ >+ mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base); >+ mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base); >+ } else >+ mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); > > gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); > } >+ >+static const struct kfd2kgd_calls kfd2kgd = { >+ .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, >+ .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, >+ .init_interrupts = kgd_gfx_v9_init_interrupts, >+ .hqd_load = kgd_gfx_v9_hqd_load, >+ .hqd_sdma_load = kgd_hqd_sdma_load, >+ .hqd_dump = kgd_gfx_v9_hqd_dump, >+ .hqd_sdma_dump = kgd_hqd_sdma_dump, >+ .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, >+ .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, >+ .hqd_destroy = kgd_gfx_v9_hqd_destroy, >+ .hqd_sdma_destroy = kgd_hqd_sdma_destroy, >+ .address_watch_disable = kgd_gfx_v9_address_watch_disable, >+ .address_watch_execute = kgd_gfx_v9_address_watch_execute, >+ .wave_control_execute = kgd_gfx_v9_wave_control_execute, >+ .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset, >+ .get_atc_vmid_pasid_mapping_pasid = >+ kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid, >+ .get_atc_vmid_pasid_mapping_valid = >+ kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid, >+ .set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va, >+ .get_tile_config = kgd_gfx_v9_get_tile_config, >+ .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, >+ .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs, >+ .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid, >+ .get_hive_id = amdgpu_amdkfd_get_hive_id, >+}; >+ >+struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) >+{ >+ return (struct kfd2kgd_calls *)&kfd2kgd; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h 2019-08-31 15:01:11.839736167 -0500 >@@ -0,0 +1,69 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ */ >+ >+ >+ >+void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, >+ uint32_t sh_mem_config, >+ uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, >+ uint32_t sh_mem_bases); >+int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, >+ unsigned int vmid); >+int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); >+int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, >+ uint32_t queue_id, uint32_t __user *wptr, >+ uint32_t wptr_shift, uint32_t wptr_mask, >+ struct mm_struct *mm); >+int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd, >+ uint32_t pipe_id, uint32_t queue_id, >+ uint32_t (**dump)[2], uint32_t *n_regs); >+bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, >+ uint32_t pipe_id, uint32_t queue_id); >+int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd, >+ enum kfd_preempt_type reset_type, >+ unsigned int utimeout, uint32_t pipe_id, >+ uint32_t queue_id); >+int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd); >+int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd, >+ unsigned int watch_point_id, >+ uint32_t cntl_val, >+ uint32_t addr_hi, >+ uint32_t addr_lo); >+int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd, >+ uint32_t gfx_index_val, >+ uint32_t sq_cmd); >+uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd, >+ unsigned int watch_point_id, >+ unsigned int reg_offset); >+ >+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, >+ uint8_t vmid); >+uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, >+ uint8_t vmid); >+void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, >+ uint64_t page_table_base); >+void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd, >+ uint64_t va, uint32_t vmid); >+int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); >+int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); >+int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd, >+ struct tile_config *config); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 2019-08-31 15:01:11.840736167 -0500 >@@ -218,7 +218,7 @@ > static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, > struct amdgpu_amdkfd_fence *ef) > { >- struct reservation_object *resv = bo->tbo.resv; >+ struct reservation_object *resv = bo->tbo.base.resv; > struct reservation_object_list *old, *new; > unsigned int i, j, k; > >@@ -812,7 +812,7 @@ > struct amdgpu_bo *pd = peer_vm->root.base.bo; > > ret = amdgpu_sync_resv(NULL, >- sync, pd->tbo.resv, >+ sync, pd->tbo.base.resv, > AMDGPU_FENCE_OWNER_KFD, false); > if (ret) > return ret; >@@ -887,7 +887,7 @@ > AMDGPU_FENCE_OWNER_KFD, false); > if (ret) > goto wait_pd_fail; >- ret = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv, 1); >+ ret = reservation_object_reserve_shared(vm->root.base.bo->tbo.base.resv, 1); > if (ret) > goto reserve_shared_fail; > amdgpu_bo_fence(vm->root.base.bo, >@@ -1090,7 +1090,7 @@ > */ > if (flags & ALLOC_MEM_FLAGS_VRAM) { > domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM; >- alloc_flags = AMDGPU_GEM_CREATE_VRAM_CLEARED; >+ alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; > alloc_flags |= (flags & ALLOC_MEM_FLAGS_PUBLIC) ? > AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : > AMDGPU_GEM_CREATE_NO_CPU_ACCESS; >@@ -2133,7 +2133,7 @@ > * Add process eviction fence to bo so they can > * evict each other. > */ >- ret = reservation_object_reserve_shared(gws_bo->tbo.resv, 1); >+ ret = reservation_object_reserve_shared(gws_bo->tbo.base.resv, 1); > if (ret) > goto reserve_shared_fail; > amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 2019-08-31 15:01:11.839736167 -0500 >@@ -140,6 +140,7 @@ > struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void); > struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void); > struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void); >+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void); > struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void); > > bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c 2019-08-31 15:01:11.840736167 -0500 >@@ -574,6 +574,7 @@ > { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX }, > { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX }, > { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX }, >+ { 0x1002, 0x699f, 0x1028, 0x0814, AMDGPU_PX_QUIRK_FORCE_ATPX }, > { 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX }, > { 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX }, > { 0, 0, 0, 0, 0 }, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 2019-08-31 15:01:11.840736167 -0500 >@@ -1505,6 +1505,7 @@ > struct amdgpu_connector_atom_dig *amdgpu_dig_connector; > struct drm_encoder *encoder; > struct amdgpu_encoder *amdgpu_encoder; >+ struct i2c_adapter *ddc = NULL; > uint32_t subpixel_order = SubPixelNone; > bool shared_ddc = false; > bool is_dp_bridge = false; >@@ -1574,17 +1575,21 @@ > amdgpu_connector->con_priv = amdgpu_dig_connector; > if (i2c_bus->valid) { > amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); >- if (amdgpu_connector->ddc_bus) >+ if (amdgpu_connector->ddc_bus) { > has_aux = true; >- else >+ ddc = &amdgpu_connector->ddc_bus->adapter; >+ } else { > DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); >+ } > } > switch (connector_type) { > case DRM_MODE_CONNECTOR_VGA: > case DRM_MODE_CONNECTOR_DVIA: > default: >- drm_connector_init(dev, &amdgpu_connector->base, >- &amdgpu_connector_dp_funcs, connector_type); >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_dp_funcs, >+ connector_type, >+ ddc); > drm_connector_helper_add(&amdgpu_connector->base, > &amdgpu_connector_dp_helper_funcs); > connector->interlace_allowed = true; >@@ -1602,8 +1607,10 @@ > case DRM_MODE_CONNECTOR_HDMIA: > case DRM_MODE_CONNECTOR_HDMIB: > case DRM_MODE_CONNECTOR_DisplayPort: >- drm_connector_init(dev, &amdgpu_connector->base, >- &amdgpu_connector_dp_funcs, connector_type); >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_dp_funcs, >+ connector_type, >+ ddc); > drm_connector_helper_add(&amdgpu_connector->base, > &amdgpu_connector_dp_helper_funcs); > drm_object_attach_property(&amdgpu_connector->base.base, >@@ -1644,8 +1651,10 @@ > break; > case DRM_MODE_CONNECTOR_LVDS: > case DRM_MODE_CONNECTOR_eDP: >- drm_connector_init(dev, &amdgpu_connector->base, >- &amdgpu_connector_edp_funcs, connector_type); >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_edp_funcs, >+ connector_type, >+ ddc); > drm_connector_helper_add(&amdgpu_connector->base, > &amdgpu_connector_dp_helper_funcs); > drm_object_attach_property(&amdgpu_connector->base.base, >@@ -1659,13 +1668,18 @@ > } else { > switch (connector_type) { > case DRM_MODE_CONNECTOR_VGA: >- drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); >- drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); > if (i2c_bus->valid) { > amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); > if (!amdgpu_connector->ddc_bus) > DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); >+ else >+ ddc = &amdgpu_connector->ddc_bus->adapter; > } >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_vga_funcs, >+ connector_type, >+ ddc); >+ drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); > amdgpu_connector->dac_load_detect = true; > drm_object_attach_property(&amdgpu_connector->base.base, > adev->mode_info.load_detect_property, >@@ -1679,13 +1693,18 @@ > connector->doublescan_allowed = true; > break; > case DRM_MODE_CONNECTOR_DVIA: >- drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); >- drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); > if (i2c_bus->valid) { > amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); > if (!amdgpu_connector->ddc_bus) > DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); >+ else >+ ddc = &amdgpu_connector->ddc_bus->adapter; > } >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_vga_funcs, >+ connector_type, >+ ddc); >+ drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); > amdgpu_connector->dac_load_detect = true; > drm_object_attach_property(&amdgpu_connector->base.base, > adev->mode_info.load_detect_property, >@@ -1704,13 +1723,18 @@ > if (!amdgpu_dig_connector) > goto failed; > amdgpu_connector->con_priv = amdgpu_dig_connector; >- drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); >- drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); > if (i2c_bus->valid) { > amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); > if (!amdgpu_connector->ddc_bus) > DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); >+ else >+ ddc = &amdgpu_connector->ddc_bus->adapter; > } >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_dvi_funcs, >+ connector_type, >+ ddc); >+ drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); > subpixel_order = SubPixelHorizontalRGB; > drm_object_attach_property(&amdgpu_connector->base.base, > adev->mode_info.coherent_mode_property, >@@ -1754,13 +1778,18 @@ > if (!amdgpu_dig_connector) > goto failed; > amdgpu_connector->con_priv = amdgpu_dig_connector; >- drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); >- drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); > if (i2c_bus->valid) { > amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); > if (!amdgpu_connector->ddc_bus) > DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); >+ else >+ ddc = &amdgpu_connector->ddc_bus->adapter; > } >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_dvi_funcs, >+ connector_type, >+ ddc); >+ drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); > drm_object_attach_property(&amdgpu_connector->base.base, > adev->mode_info.coherent_mode_property, > 1); >@@ -1796,15 +1825,20 @@ > if (!amdgpu_dig_connector) > goto failed; > amdgpu_connector->con_priv = amdgpu_dig_connector; >- drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); >- drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); > if (i2c_bus->valid) { > amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); >- if (amdgpu_connector->ddc_bus) >+ if (amdgpu_connector->ddc_bus) { > has_aux = true; >- else >+ ddc = &amdgpu_connector->ddc_bus->adapter; >+ } else { > DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); >+ } > } >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_dp_funcs, >+ connector_type, >+ ddc); >+ drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); > subpixel_order = SubPixelHorizontalRGB; > drm_object_attach_property(&amdgpu_connector->base.base, > adev->mode_info.coherent_mode_property, >@@ -1838,15 +1872,20 @@ > if (!amdgpu_dig_connector) > goto failed; > amdgpu_connector->con_priv = amdgpu_dig_connector; >- drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); >- drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); > if (i2c_bus->valid) { > amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); >- if (amdgpu_connector->ddc_bus) >+ if (amdgpu_connector->ddc_bus) { > has_aux = true; >- else >+ ddc = &amdgpu_connector->ddc_bus->adapter; >+ } else { > DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); >+ } > } >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_edp_funcs, >+ connector_type, >+ ddc); >+ drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); > drm_object_attach_property(&amdgpu_connector->base.base, > dev->mode_config.scaling_mode_property, > DRM_MODE_SCALE_FULLSCREEN); >@@ -1859,13 +1898,18 @@ > if (!amdgpu_dig_connector) > goto failed; > amdgpu_connector->con_priv = amdgpu_dig_connector; >- drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); >- drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); > if (i2c_bus->valid) { > amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); > if (!amdgpu_connector->ddc_bus) > DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); >+ else >+ ddc = &amdgpu_connector->ddc_bus->adapter; > } >+ drm_connector_init_with_ddc(dev, &amdgpu_connector->base, >+ &amdgpu_connector_lvds_funcs, >+ connector_type, >+ ddc); >+ drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); > drm_object_attach_property(&amdgpu_connector->base.base, > dev->mode_config.scaling_mode_property, > DRM_MODE_SCALE_FULLSCREEN); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 2019-08-31 15:01:12.278736205 -0500 >@@ -402,7 +402,7 @@ > struct ttm_operation_ctx ctx = { > .interruptible = true, > .no_wait_gpu = false, >- .resv = bo->tbo.resv, >+ .resv = bo->tbo.base.resv, > .flags = 0 > }; > uint32_t domain; >@@ -730,7 +730,7 @@ > > list_for_each_entry(e, &p->validated, tv.head) { > struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); >- struct reservation_object *resv = bo->tbo.resv; >+ struct reservation_object *resv = bo->tbo.base.resv; > > r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp, > amdgpu_bo_explicit_sync(bo)); >@@ -1732,7 +1732,7 @@ > *map = mapping; > > /* Double check that the BO is reserved by this CS */ >- if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket) >+ if (reservation_object_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket) > return -EINVAL; > > if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 2019-08-31 15:01:11.840736167 -0500 >@@ -42,7 +42,7 @@ > [AMDGPU_HW_IP_VCN_JPEG] = 1, > }; > >-static int amdgput_ctx_total_num_entities(void) >+static int amdgpu_ctx_total_num_entities(void) > { > unsigned i, num_entities = 0; > >@@ -73,8 +73,8 @@ > struct drm_file *filp, > struct amdgpu_ctx *ctx) > { >- unsigned num_entities = amdgput_ctx_total_num_entities(); >- unsigned i, j; >+ unsigned num_entities = amdgpu_ctx_total_num_entities(); >+ unsigned i, j, k; > int r; > > if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX) >@@ -123,7 +123,7 @@ > for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { > struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; > struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS]; >- unsigned num_rings; >+ unsigned num_rings = 0; > unsigned num_rqs = 0; > > switch (i) { >@@ -154,16 +154,26 @@ > num_rings = 1; > break; > case AMDGPU_HW_IP_VCN_DEC: >- rings[0] = &adev->vcn.ring_dec; >- num_rings = 1; >+ for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ rings[num_rings++] = &adev->vcn.inst[j].ring_dec; >+ } > break; > case AMDGPU_HW_IP_VCN_ENC: >- rings[0] = &adev->vcn.ring_enc[0]; >- num_rings = 1; >+ for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ for (k = 0; k < adev->vcn.num_enc_rings; ++k) >+ rings[num_rings++] = &adev->vcn.inst[j].ring_enc[k]; >+ } > break; > case AMDGPU_HW_IP_VCN_JPEG: >- rings[0] = &adev->vcn.ring_jpeg; >- num_rings = 1; >+ for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ rings[num_rings++] = &adev->vcn.inst[j].ring_jpeg; >+ } > break; > } > >@@ -197,7 +207,7 @@ > static void amdgpu_ctx_fini(struct kref *ref) > { > struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); >- unsigned num_entities = amdgput_ctx_total_num_entities(); >+ unsigned num_entities = amdgpu_ctx_total_num_entities(); > struct amdgpu_device *adev = ctx->adev; > unsigned i, j; > >@@ -279,10 +289,7 @@ > > ctx = container_of(ref, struct amdgpu_ctx, refcount); > >- num_entities = 0; >- for (i = 0; i < AMDGPU_HW_IP_NUM; i++) >- num_entities += amdgpu_ctx_num_entities[i]; >- >+ num_entities = amdgpu_ctx_total_num_entities(); > for (i = 0; i < num_entities; i++) > drm_sched_entity_destroy(&ctx->entities[0][i].entity); > >@@ -344,7 +351,7 @@ > { > struct amdgpu_ctx *ctx; > struct amdgpu_ctx_mgr *mgr; >- uint32_t ras_counter; >+ unsigned long ras_counter; > > if (!fpriv) > return -EINVAL; >@@ -514,7 +521,7 @@ > void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, > enum drm_sched_priority priority) > { >- unsigned num_entities = amdgput_ctx_total_num_entities(); >+ unsigned num_entities = amdgpu_ctx_total_num_entities(); > enum drm_sched_priority ctx_prio; > unsigned i; > >@@ -534,21 +541,24 @@ > struct drm_sched_entity *entity) > { > struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); >- unsigned idx = centity->sequence & (amdgpu_sched_jobs - 1); >- struct dma_fence *other = centity->fences[idx]; >+ struct dma_fence *other; >+ unsigned idx; >+ long r; > >- if (other) { >- signed long r; >- r = dma_fence_wait(other, true); >- if (r < 0) { >- if (r != -ERESTARTSYS) >- DRM_ERROR("Error (%ld) waiting for fence!\n", r); >+ spin_lock(&ctx->ring_lock); >+ idx = centity->sequence & (amdgpu_sched_jobs - 1); >+ other = dma_fence_get(centity->fences[idx]); >+ spin_unlock(&ctx->ring_lock); > >- return r; >- } >- } >+ if (!other) >+ return 0; > >- return 0; >+ r = dma_fence_wait(other, true); >+ if (r < 0 && r != -ERESTARTSYS) >+ DRM_ERROR("Error (%ld) waiting for fence!\n", r); >+ >+ dma_fence_put(other); >+ return r; > } > > void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) >@@ -559,7 +569,7 @@ > > long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) > { >- unsigned num_entities = amdgput_ctx_total_num_entities(); >+ unsigned num_entities = amdgpu_ctx_total_num_entities(); > struct amdgpu_ctx *ctx; > struct idr *idp; > uint32_t id, i; >@@ -581,7 +591,7 @@ > > void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) > { >- unsigned num_entities = amdgput_ctx_total_num_entities(); >+ unsigned num_entities = amdgpu_ctx_total_num_entities(); > struct amdgpu_ctx *ctx; > struct idr *idp; > uint32_t id, i; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h 2019-08-31 15:01:11.840736167 -0500 >@@ -49,8 +49,8 @@ > enum drm_sched_priority override_priority; > struct mutex lock; > atomic_t guilty; >- uint32_t ras_counter_ce; >- uint32_t ras_counter_ue; >+ unsigned long ras_counter_ce; >+ unsigned long ras_counter_ue; > }; > > struct amdgpu_ctx_mgr { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 2019-08-31 15:01:11.841736167 -0500 >@@ -70,7 +70,11 @@ > MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); > MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); > MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); >+MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); >+MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); > MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); > > #define AMDGPU_RESUME_MS 2000 > >@@ -98,7 +102,11 @@ > "VEGA12", > "VEGA20", > "RAVEN", >+ "ARCTURUS", >+ "RENOIR", > "NAVI10", >+ "NAVI14", >+ "NAVI12", > "LAST", > }; > >@@ -413,6 +421,40 @@ > } > > /** >+ * amdgpu_invalid_rreg64 - dummy 64 bit reg read function >+ * >+ * @adev: amdgpu device pointer >+ * @reg: offset of register >+ * >+ * Dummy register read function. Used for register blocks >+ * that certain asics don't have (all asics). >+ * Returns the value in the register. >+ */ >+static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) >+{ >+ DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); >+ BUG(); >+ return 0; >+} >+ >+/** >+ * amdgpu_invalid_wreg64 - dummy reg write function >+ * >+ * @adev: amdgpu device pointer >+ * @reg: offset of register >+ * @v: value to write to the register >+ * >+ * Dummy register read function. Used for register blocks >+ * that certain asics don't have (all asics). >+ */ >+static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) >+{ >+ DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", >+ reg, v); >+ BUG(); >+} >+ >+/** > * amdgpu_block_invalid_rreg - dummy reg read function > * > * @adev: amdgpu device pointer >@@ -1384,9 +1426,21 @@ > else > chip_name = "raven"; > break; >+ case CHIP_ARCTURUS: >+ chip_name = "arcturus"; >+ break; >+ case CHIP_RENOIR: >+ chip_name = "renoir"; >+ break; > case CHIP_NAVI10: > chip_name = "navi10"; > break; >+ case CHIP_NAVI14: >+ chip_name = "navi14"; >+ break; >+ case CHIP_NAVI12: >+ chip_name = "navi12"; >+ break; > } > > snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); >@@ -1529,7 +1583,10 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >- if (adev->asic_type == CHIP_RAVEN) >+ case CHIP_ARCTURUS: >+ case CHIP_RENOIR: >+ if (adev->asic_type == CHIP_RAVEN || >+ adev->asic_type == CHIP_RENOIR) > adev->family = AMDGPU_FAMILY_RV; > else > adev->family = AMDGPU_FAMILY_AI; >@@ -1539,6 +1596,8 @@ > return r; > break; > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > adev->family = AMDGPU_FAMILY_NV; > > r = nv_set_ip_blocks(adev); >@@ -1560,9 +1619,6 @@ > r = amdgpu_virt_request_full_gpu(adev, true); > if (r) > return -EAGAIN; >- >- /* query the reg access mode at the very beginning */ >- amdgpu_virt_init_reg_access_mode(adev); > } > > adev->pm.pp_feature = amdgpu_pp_feature_mask; >@@ -1665,28 +1721,34 @@ > > if (adev->asic_type >= CHIP_VEGA10) { > for (i = 0; i < adev->num_ip_blocks; i++) { >- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { >- if (adev->in_gpu_reset || adev->in_suspend) { >- if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) >- break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */ >- r = adev->ip_blocks[i].version->funcs->resume(adev); >- if (r) { >- DRM_ERROR("resume of IP block <%s> failed %d\n", >+ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) >+ continue; >+ >+ /* no need to do the fw loading again if already done*/ >+ if (adev->ip_blocks[i].status.hw == true) >+ break; >+ >+ if (adev->in_gpu_reset || adev->in_suspend) { >+ r = adev->ip_blocks[i].version->funcs->resume(adev); >+ if (r) { >+ DRM_ERROR("resume of IP block <%s> failed %d\n", > adev->ip_blocks[i].version->funcs->name, r); >- return r; >- } >- } else { >- r = adev->ip_blocks[i].version->funcs->hw_init(adev); >- if (r) { >- DRM_ERROR("hw_init of IP block <%s> failed %d\n", >- adev->ip_blocks[i].version->funcs->name, r); >- return r; >- } >+ return r; >+ } >+ } else { >+ r = adev->ip_blocks[i].version->funcs->hw_init(adev); >+ if (r) { >+ DRM_ERROR("hw_init of IP block <%s> failed %d\n", >+ adev->ip_blocks[i].version->funcs->name, r); >+ return r; > } >- adev->ip_blocks[i].status.hw = true; > } >+ >+ adev->ip_blocks[i].status.hw = true; >+ break; > } > } >+ > r = amdgpu_pm_load_smu_firmware(adev, &smu_version); > > return r; >@@ -2128,7 +2190,9 @@ > if (r) { > DRM_ERROR("suspend of IP block <%s> failed %d\n", > adev->ip_blocks[i].version->funcs->name, r); >+ return r; > } >+ adev->ip_blocks[i].status.hw = false; > } > } > >@@ -2163,6 +2227,25 @@ > DRM_ERROR("suspend of IP block <%s> failed %d\n", > adev->ip_blocks[i].version->funcs->name, r); > } >+ adev->ip_blocks[i].status.hw = false; >+ /* handle putting the SMC in the appropriate state */ >+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { >+ if (is_support_sw_smu(adev)) { >+ /* todo */ >+ } else if (adev->powerplay.pp_funcs && >+ adev->powerplay.pp_funcs->set_mp1_state) { >+ r = adev->powerplay.pp_funcs->set_mp1_state( >+ adev->powerplay.pp_handle, >+ adev->mp1_state); >+ if (r) { >+ DRM_ERROR("SMC failed to set mp1 state %d, %d\n", >+ adev->mp1_state, r); >+ return r; >+ } >+ } >+ } >+ >+ adev->ip_blocks[i].status.hw = false; > } > > return 0; >@@ -2215,6 +2298,7 @@ > for (j = 0; j < adev->num_ip_blocks; j++) { > block = &adev->ip_blocks[j]; > >+ block->status.hw = false; > if (block->version->type != ip_order[i] || > !block->status.valid) > continue; >@@ -2223,6 +2307,7 @@ > DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); > if (r) > return r; >+ block->status.hw = true; > } > } > >@@ -2250,13 +2335,15 @@ > block = &adev->ip_blocks[j]; > > if (block->version->type != ip_order[i] || >- !block->status.valid) >+ !block->status.valid || >+ block->status.hw) > continue; > > r = block->version->funcs->hw_init(adev); > DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); > if (r) > return r; >+ block->status.hw = true; > } > } > >@@ -2280,17 +2367,19 @@ > int i, r; > > for (i = 0; i < adev->num_ip_blocks; i++) { >- if (!adev->ip_blocks[i].status.valid) >+ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) > continue; > if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || > adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || > adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { >+ > r = adev->ip_blocks[i].version->funcs->resume(adev); > if (r) { > DRM_ERROR("resume of IP block <%s> failed %d\n", > adev->ip_blocks[i].version->funcs->name, r); > return r; > } >+ adev->ip_blocks[i].status.hw = true; > } > } > >@@ -2315,7 +2404,7 @@ > int i, r; > > for (i = 0; i < adev->num_ip_blocks; i++) { >- if (!adev->ip_blocks[i].status.valid) >+ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) > continue; > if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || > adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || >@@ -2328,6 +2417,7 @@ > adev->ip_blocks[i].version->funcs->name, r); > return r; > } >+ adev->ip_blocks[i].status.hw = true; > } > > return 0; >@@ -2426,6 +2516,11 @@ > #endif > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: >+#endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ case CHIP_RENOIR: > #endif > return amdgpu_dc != 0; > #endif >@@ -2509,6 +2604,8 @@ > adev->pcie_wreg = &amdgpu_invalid_wreg; > adev->pciep_rreg = &amdgpu_invalid_rreg; > adev->pciep_wreg = &amdgpu_invalid_wreg; >+ adev->pcie_rreg64 = &amdgpu_invalid_rreg64; >+ adev->pcie_wreg64 = &amdgpu_invalid_wreg64; > adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; > adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; > adev->didt_rreg = &amdgpu_invalid_rreg; >@@ -3389,7 +3486,7 @@ > amdgpu_virt_init_data_exchange(adev); > amdgpu_virt_release_full_gpu(adev, true); > if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { >- atomic_inc(&adev->vram_lost_counter); >+ amdgpu_inc_vram_lost(adev); > r = amdgpu_device_recover_vram(adev); > } > >@@ -3431,6 +3528,7 @@ > case CHIP_VEGA20: > case CHIP_VEGA10: > case CHIP_VEGA12: >+ case CHIP_RAVEN: > break; > default: > goto disabled; >@@ -3554,7 +3652,7 @@ > vram_lost = amdgpu_device_check_vram_lost(tmp_adev); > if (vram_lost) { > DRM_INFO("VRAM is lost due to GPU reset!\n"); >- atomic_inc(&tmp_adev->vram_lost_counter); >+ amdgpu_inc_vram_lost(tmp_adev); > } > > r = amdgpu_gtt_mgr_recover( >@@ -3627,6 +3725,17 @@ > > atomic_inc(&adev->gpu_reset_counter); > adev->in_gpu_reset = 1; >+ switch (amdgpu_asic_reset_method(adev)) { >+ case AMD_RESET_METHOD_MODE1: >+ adev->mp1_state = PP_MP1_STATE_SHUTDOWN; >+ break; >+ case AMD_RESET_METHOD_MODE2: >+ adev->mp1_state = PP_MP1_STATE_RESET; >+ break; >+ default: >+ adev->mp1_state = PP_MP1_STATE_NONE; >+ break; >+ } > /* Block kfd: SRIOV would do it separately */ > if (!amdgpu_sriov_vf(adev)) > amdgpu_amdkfd_pre_reset(adev); >@@ -3640,6 +3749,7 @@ > if (!amdgpu_sriov_vf(adev)) > amdgpu_amdkfd_post_reset(adev); > amdgpu_vf_error_trans_all(adev); >+ adev->mp1_state = PP_MP1_STATE_NONE; > adev->in_gpu_reset = 0; > mutex_unlock(&adev->lock_reset); > } >@@ -3684,14 +3794,14 @@ > > if (hive && !mutex_trylock(&hive->reset_lock)) { > DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", >- job->base.id, hive->hive_id); >+ job ? job->base.id : -1, hive->hive_id); > return 0; > } > > /* Start with adev pre asic reset first for soft reset check.*/ > if (!amdgpu_device_lock_adev(adev, !hive)) { > DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress", >- job->base.id); >+ job ? job->base.id : -1); > return 0; > } > >@@ -3732,7 +3842,7 @@ > if (!ring || !ring->sched.thread) > continue; > >- drm_sched_stop(&ring->sched, &job->base); >+ drm_sched_stop(&ring->sched, job ? &job->base : NULL); > } > } > >@@ -3757,9 +3867,7 @@ > > > /* Guilty job will be freed after this*/ >- r = amdgpu_device_pre_asic_reset(adev, >- job, >- &need_full_reset); >+ r = amdgpu_device_pre_asic_reset(adev, job, &need_full_reset); > if (r) { > /*TODO Should we stop ?*/ > DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ", >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 2019-08-31 15:01:11.841736167 -0500 >@@ -191,7 +191,8 @@ > } > > if (!adev->enable_virtual_display) { >- r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev)); >+ r = amdgpu_bo_pin(new_abo, >+ amdgpu_display_supported_domains(adev, new_abo->flags)); > if (unlikely(r != 0)) { > DRM_ERROR("failed to pin new abo buffer before flip\n"); > goto unreserve; >@@ -204,7 +205,7 @@ > goto unpin; > } > >- r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl, >+ r = reservation_object_get_fences_rcu(new_abo->tbo.base.resv, &work->excl, > &work->shared_count, > &work->shared); > if (unlikely(r != 0)) { >@@ -495,13 +496,25 @@ > .create_handle = drm_gem_fb_create_handle, > }; > >-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev) >+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, >+ uint64_t bo_flags) > { > uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; > > #if defined(CONFIG_DRM_AMD_DC) >- if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && >- adev->flags & AMD_IS_APU && >+ /* >+ * if amdgpu_bo_support_uswc returns false it means that USWC mappings >+ * is not supported for this board. But this mapping is required >+ * to avoid hang caused by placement of scanout BO in GTT on certain >+ * APUs. So force the BO placement to VRAM in case this architecture >+ * will not allow USWC mappings. >+ * Also, don't allow GTT domain if the BO doens't have USWC falg set. >+ */ >+ if (adev->asic_type >= CHIP_CARRIZO && >+ adev->asic_type <= CHIP_RAVEN && >+ (adev->flags & AMD_IS_APU) && >+ (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && >+ amdgpu_bo_support_uswc(bo_flags) && > amdgpu_device_asic_has_dc_support(adev->asic_type)) > domain |= AMDGPU_GEM_DOMAIN_GTT; > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h 2019-08-31 15:01:11.841736167 -0500 >@@ -38,7 +38,8 @@ > int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data, > struct drm_file *filp); > void amdgpu_display_update_priority(struct amdgpu_device *adev); >-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev); >+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, >+ uint64_t bo_flags); > struct drm_framebuffer * > amdgpu_display_user_framebuffer_create(struct drm_device *dev, > struct drm_file *file_priv, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 2019-08-31 15:01:11.841736167 -0500 >@@ -216,7 +216,7 @@ > * fences on the reservation object into a single exclusive > * fence. > */ >- r = __reservation_object_make_exclusive(bo->tbo.resv); >+ r = __reservation_object_make_exclusive(bo->tbo.base.resv); > if (r) > goto error_unreserve; > } >@@ -268,20 +268,6 @@ > } > > /** >- * amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation >- * @obj: GEM BO >- * >- * Returns: >- * The BO's reservation object. >- */ >-struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj) >-{ >- struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); >- >- return bo->tbo.resv; >-} >- >-/** > * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation > * @dma_buf: Shared DMA buffer > * @direction: Direction of DMA transfer >@@ -299,7 +285,7 @@ > struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv); > struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); > struct ttm_operation_ctx ctx = { true, false }; >- u32 domain = amdgpu_display_supported_domains(adev); >+ u32 domain = amdgpu_display_supported_domains(adev, bo->flags); > int ret; > bool reads = (direction == DMA_BIDIRECTIONAL || > direction == DMA_FROM_DEVICE); >@@ -339,14 +325,12 @@ > * @gobj: GEM BO > * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR. > * >- * The main work is done by the &drm_gem_prime_export helper, which in turn >- * uses &amdgpu_gem_prime_res_obj. >+ * The main work is done by the &drm_gem_prime_export helper. > * > * Returns: > * Shared DMA buffer representing the GEM BO from the given device. > */ >-struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, >- struct drm_gem_object *gobj, >+struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, > int flags) > { > struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); >@@ -356,9 +340,9 @@ > bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) > return ERR_PTR(-EPERM); > >- buf = drm_gem_prime_export(dev, gobj, flags); >+ buf = drm_gem_prime_export(gobj, flags); > if (!IS_ERR(buf)) { >- buf->file->f_mapping = dev->anon_inode->i_mapping; >+ buf->file->f_mapping = gobj->dev->anon_inode->i_mapping; > buf->ops = &amdgpu_dmabuf_ops; > } > >@@ -396,7 +380,7 @@ > bp.flags = 0; > bp.type = ttm_bo_type_sg; > bp.resv = resv; >- ww_mutex_lock(&resv->lock, NULL); >+ reservation_object_lock(resv, NULL); > ret = amdgpu_bo_create(adev, &bp, &bo); > if (ret) > goto error; >@@ -408,11 +392,11 @@ > if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) > bo->prime_shared_count = 1; > >- ww_mutex_unlock(&resv->lock); >- return &bo->gem_base; >+ reservation_object_unlock(resv); >+ return &bo->tbo.base; > > error: >- ww_mutex_unlock(&resv->lock); >+ reservation_object_unlock(resv); > return ERR_PTR(ret); > } > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h 2019-08-31 15:01:11.841736167 -0500 >@@ -30,12 +30,10 @@ > amdgpu_gem_prime_import_sg_table(struct drm_device *dev, > struct dma_buf_attachment *attach, > struct sg_table *sg); >-struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, >- struct drm_gem_object *gobj, >+struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, > int flags); > struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, > struct dma_buf *dma_buf); >-struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); > void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); > void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); > int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h 2019-08-31 15:01:11.841736167 -0500 >@@ -130,13 +130,18 @@ > AMDGPU_VEGA20_DOORBELL_IH = 0x178, > /* MMSCH: 392~407 > * overlap the doorbell assignment with VCN as they are mutually exclusive >- * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD >+ * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD > */ >- AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ >+ AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ > AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, > AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, > AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, > >+ AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ >+ AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, >+ AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, >+ AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, >+ > AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, > AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, > AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 2019-08-31 15:01:11.841736167 -0500 >@@ -79,9 +79,10 @@ > * - 3.31.0 - Add support for per-flip tiling attribute changes with DC > * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. > * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. >+ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches > */ > #define KMS_DRIVER_MAJOR 3 >-#define KMS_DRIVER_MINOR 33 >+#define KMS_DRIVER_MINOR 34 > #define KMS_DRIVER_PATCHLEVEL 0 > > #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256 >@@ -142,7 +143,7 @@ > int amdgpu_mcbp = 0; > int amdgpu_discovery = -1; > int amdgpu_mes = 0; >-int amdgpu_noretry; >+int amdgpu_noretry = 1; > > struct amdgpu_mgpu_info mgpu_info = { > .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), >@@ -610,7 +611,7 @@ > module_param_named(mes, amdgpu_mes, int, 0444); > > MODULE_PARM_DESC(noretry, >- "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)"); >+ "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))"); > module_param_named(noretry, amdgpu_noretry, int, 0644); > > #ifdef CONFIG_HSA_AMD >@@ -996,6 +997,11 @@ > /* Raven */ > {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, > {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, >+ /* Arcturus */ >+ {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, >+ {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, >+ {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, >+ {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, > /* Navi10 */ > {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, > {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, >@@ -1004,6 +1010,11 @@ > {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, > {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, > {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, >+ /* Navi14 */ >+ {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, >+ >+ /* Renoir */ >+ {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT}, > > {0, 0, 0} > }; >@@ -1092,21 +1103,21 @@ > * unfortunately we can't detect certain > * hypervisors so just do this all the time. > */ >+ adev->mp1_state = PP_MP1_STATE_UNLOAD; > amdgpu_device_ip_suspend(adev); >+ adev->mp1_state = PP_MP1_STATE_NONE; > } > > static int amdgpu_pmops_suspend(struct device *dev) > { >- struct pci_dev *pdev = to_pci_dev(dev); >+ struct drm_device *drm_dev = dev_get_drvdata(dev); > >- struct drm_device *drm_dev = pci_get_drvdata(pdev); > return amdgpu_device_suspend(drm_dev, true, true); > } > > static int amdgpu_pmops_resume(struct device *dev) > { >- struct pci_dev *pdev = to_pci_dev(dev); >- struct drm_device *drm_dev = pci_get_drvdata(pdev); >+ struct drm_device *drm_dev = dev_get_drvdata(dev); > > /* GPU comes up enabled by the bios on resume */ > if (amdgpu_device_is_px(drm_dev)) { >@@ -1120,33 +1131,29 @@ > > static int amdgpu_pmops_freeze(struct device *dev) > { >- struct pci_dev *pdev = to_pci_dev(dev); >+ struct drm_device *drm_dev = dev_get_drvdata(dev); > >- struct drm_device *drm_dev = pci_get_drvdata(pdev); > return amdgpu_device_suspend(drm_dev, false, true); > } > > static int amdgpu_pmops_thaw(struct device *dev) > { >- struct pci_dev *pdev = to_pci_dev(dev); >+ struct drm_device *drm_dev = dev_get_drvdata(dev); > >- struct drm_device *drm_dev = pci_get_drvdata(pdev); > return amdgpu_device_resume(drm_dev, false, true); > } > > static int amdgpu_pmops_poweroff(struct device *dev) > { >- struct pci_dev *pdev = to_pci_dev(dev); >+ struct drm_device *drm_dev = dev_get_drvdata(dev); > >- struct drm_device *drm_dev = pci_get_drvdata(pdev); > return amdgpu_device_suspend(drm_dev, true, true); > } > > static int amdgpu_pmops_restore(struct device *dev) > { >- struct pci_dev *pdev = to_pci_dev(dev); >+ struct drm_device *drm_dev = dev_get_drvdata(dev); > >- struct drm_device *drm_dev = pci_get_drvdata(pdev); > return amdgpu_device_resume(drm_dev, false, true); > } > >@@ -1205,8 +1212,7 @@ > > static int amdgpu_pmops_runtime_idle(struct device *dev) > { >- struct pci_dev *pdev = to_pci_dev(dev); >- struct drm_device *drm_dev = pci_get_drvdata(pdev); >+ struct drm_device *drm_dev = dev_get_drvdata(dev); > struct drm_crtc *crtc; > > if (!amdgpu_device_is_px(drm_dev)) { >@@ -1373,7 +1379,7 @@ > .driver_features = > DRIVER_USE_AGP | DRIVER_ATOMIC | > DRIVER_GEM | >- DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, >+ DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, > .load = amdgpu_driver_load_kms, > .open = amdgpu_driver_open_kms, > .postclose = amdgpu_driver_postclose_kms, >@@ -1397,7 +1403,6 @@ > .prime_fd_to_handle = drm_gem_prime_fd_to_handle, > .gem_prime_export = amdgpu_gem_prime_export, > .gem_prime_import = amdgpu_gem_prime_import, >- .gem_prime_res_obj = amdgpu_gem_prime_res_obj, > .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, > .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, > .gem_prime_vmap = amdgpu_gem_prime_vmap, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 2019-08-31 15:01:11.841736167 -0500 >@@ -131,6 +131,10 @@ > int aligned_size, size; > int height = mode_cmd->height; > u32 cpp; >+ u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | >+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | >+ AMDGPU_GEM_CREATE_VRAM_CLEARED | >+ AMDGPU_GEM_CREATE_CPU_GTT_USWC; > > info = drm_get_format_info(adev->ddev, mode_cmd); > cpp = info->cpp[0]; >@@ -138,15 +142,11 @@ > /* need to align pitch with crtc limits */ > mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, > fb_tiled); >- domain = amdgpu_display_supported_domains(adev); >- >+ domain = amdgpu_display_supported_domains(adev, flags); > height = ALIGN(mode_cmd->height, 8); > size = mode_cmd->pitches[0] * height; > aligned_size = ALIGN(size, PAGE_SIZE); >- ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, >- AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | >- AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | >- AMDGPU_GEM_CREATE_VRAM_CLEARED, >+ ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, > ttm_bo_type_kernel, NULL, &gobj); > if (ret) { > pr_err("failed to allocate framebuffer (%d)\n", aligned_size); >@@ -168,7 +168,6 @@ > dev_err(adev->dev, "FB failed to set tiling flags\n"); > } > >- > ret = amdgpu_bo_pin(abo, domain); > if (ret) { > amdgpu_bo_unreserve(abo); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 2019-08-31 15:01:11.841736167 -0500 >@@ -251,7 +251,9 @@ > } > mb(); > amdgpu_asic_flush_hdp(adev, NULL); >- amdgpu_gmc_flush_gpu_tlb(adev, 0, 0); >+ for (i = 0; i < adev->num_vmhubs; i++) >+ amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); >+ > return 0; > } > >@@ -310,9 +312,9 @@ > uint64_t flags) > { > #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS >- unsigned i,t,p; >+ unsigned t,p; > #endif >- int r; >+ int r, i; > > if (!adev->gart.ready) { > WARN(1, "trying to bind memory to uninitialized GART !\n"); >@@ -336,7 +338,8 @@ > > mb(); > amdgpu_asic_flush_hdp(adev, NULL); >- amdgpu_gmc_flush_gpu_tlb(adev, 0, 0); >+ for (i = 0; i < adev->num_vmhubs; i++) >+ amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > return 0; > } > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 2019-08-31 15:01:11.841736167 -0500 >@@ -85,7 +85,7 @@ > } > return r; > } >- *obj = &bo->gem_base; >+ *obj = &bo->tbo.base; > > return 0; > } >@@ -134,7 +134,7 @@ > return -EPERM; > > if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && >- abo->tbo.resv != vm->root.base.bo->tbo.resv) >+ abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) > return -EPERM; > > r = amdgpu_bo_reserve(abo, false); >@@ -252,7 +252,7 @@ > if (r) > return r; > >- resv = vm->root.base.bo->tbo.resv; >+ resv = vm->root.base.bo->tbo.base.resv; > } > > r = amdgpu_gem_object_create(adev, size, args->in.alignment, >@@ -433,7 +433,7 @@ > return -ENOENT; > } > robj = gem_to_amdgpu_bo(gobj); >- ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, >+ ret = reservation_object_wait_timeout_rcu(robj->tbo.base.resv, true, true, > timeout); > > /* ret == 0 means not signaled, >@@ -689,7 +689,7 @@ > struct drm_amdgpu_gem_create_in info; > void __user *out = u64_to_user_ptr(args->value); > >- info.bo_size = robj->gem_base.size; >+ info.bo_size = robj->tbo.base.size; > info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; > info.domains = robj->preferred_domains; > info.domain_flags = robj->flags; >@@ -747,7 +747,8 @@ > struct amdgpu_device *adev = dev->dev_private; > struct drm_gem_object *gobj; > uint32_t handle; >- u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; >+ u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | >+ AMDGPU_GEM_CREATE_CPU_GTT_USWC; > u32 domain; > int r; > >@@ -764,7 +765,7 @@ > args->size = (u64)args->pitch * args->height; > args->size = ALIGN(args->size, PAGE_SIZE); > domain = amdgpu_bo_get_preferred_pin_domain(adev, >- amdgpu_display_supported_domains(adev)); >+ amdgpu_display_supported_domains(adev, flags)); > r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, > ttm_bo_type_device, NULL, &gobj); > if (r) >@@ -819,8 +820,8 @@ > if (pin_count) > seq_printf(m, " pin count %d", pin_count); > >- dma_buf = READ_ONCE(bo->gem_base.dma_buf); >- attachment = READ_ONCE(bo->gem_base.import_attach); >+ dma_buf = READ_ONCE(bo->tbo.base.dma_buf); >+ attachment = READ_ONCE(bo->tbo.base.import_attach); > > if (attachment) > seq_printf(m, " imported from %p", dma_buf); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h 2019-08-31 15:01:11.841736167 -0500 >@@ -31,7 +31,7 @@ > */ > > #define AMDGPU_GEM_DOMAIN_MAX 0x3 >-#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) >+#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base) > > void amdgpu_gem_object_free(struct drm_gem_object *obj); > int amdgpu_gem_object_open(struct drm_gem_object *obj, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 2019-08-31 15:01:11.842736167 -0500 >@@ -389,7 +389,7 @@ > dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); > } > >- if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) { >+ if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { > /* create MQD for each KGQ */ > for (i = 0; i < adev->gfx.num_gfx_rings; i++) { > ring = &adev->gfx.gfx_ring[i]; >@@ -437,7 +437,7 @@ > struct amdgpu_ring *ring = NULL; > int i; > >- if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) { >+ if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { > for (i = 0; i < adev->gfx.num_gfx_rings; i++) { > ring = &adev->gfx.gfx_ring[i]; > kfree(adev->gfx.me.mqd_backup[i]); >@@ -456,7 +456,7 @@ > } > > ring = &adev->gfx.kiq.ring; >- if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) >+ if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) > kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]); > kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); > amdgpu_bo_free_kernel(&ring->mqd_obj, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 2019-08-31 15:01:11.842736167 -0500 >@@ -196,6 +196,8 @@ > uint32_t *dst); > void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, > u32 queue, u32 vmid); >+ int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if); >+ int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status); > }; > > struct amdgpu_ngg_buf { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 2019-08-31 15:01:11.842736167 -0500 >@@ -220,6 +220,14 @@ > const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); > u64 size_af, size_bf; > >+ if (amdgpu_sriov_vf(adev)) { >+ mc->agp_start = 0xffffffff; >+ mc->agp_end = 0x0; >+ mc->agp_size = 0; >+ >+ return; >+ } >+ > if (mc->fb_start > mc->gart_start) { > size_bf = (mc->fb_start & sixteen_gb_mask) - > ALIGN(mc->gart_end + 1, sixteen_gb); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 2019-08-31 15:01:11.842736167 -0500 >@@ -89,8 +89,8 @@ > */ > struct amdgpu_gmc_funcs { > /* flush the vm tlb via mmio */ >- void (*flush_gpu_tlb)(struct amdgpu_device *adev, >- uint32_t vmid, uint32_t flush_type); >+ void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, >+ uint32_t vmhub, uint32_t flush_type); > /* flush the vm tlb via ring */ > uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, > uint64_t pd_addr); >@@ -177,10 +177,11 @@ > > struct amdgpu_xgmi xgmi; > struct amdgpu_irq_src ecc_irq; >- struct ras_common_if *ras_if; >+ struct ras_common_if *umc_ras_if; >+ struct ras_common_if *mmhub_ras_if; > }; > >-#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type)) >+#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) > #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) > #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) > #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu.h 2019-08-31 15:01:11.839736167 -0500 >@@ -86,6 +86,8 @@ > #include "amdgpu_smu.h" > #include "amdgpu_discovery.h" > #include "amdgpu_mes.h" >+#include "amdgpu_umc.h" >+#include "amdgpu_mmhub.h" > > #define MAX_GPU_INSTANCE 16 > >@@ -532,6 +534,14 @@ > bool grbm_indexed; > }; > >+enum amd_reset_method { >+ AMD_RESET_METHOD_LEGACY = 0, >+ AMD_RESET_METHOD_MODE0, >+ AMD_RESET_METHOD_MODE1, >+ AMD_RESET_METHOD_MODE2, >+ AMD_RESET_METHOD_BACO >+}; >+ > /* > * ASIC specific functions. > */ >@@ -543,6 +553,7 @@ > u32 sh_num, u32 reg_offset, u32 *value); > void (*set_vga_state)(struct amdgpu_device *adev, bool state); > int (*reset)(struct amdgpu_device *adev); >+ enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); > /* get the reference clock */ > u32 (*get_xclk)(struct amdgpu_device *adev); > /* MM block clocks */ >@@ -627,6 +638,9 @@ > typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); > typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); > >+typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); >+typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); >+ > typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); > typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); > >@@ -648,6 +662,12 @@ > u32 ref_and_mask_cp9; > u32 ref_and_mask_sdma0; > u32 ref_and_mask_sdma1; >+ u32 ref_and_mask_sdma2; >+ u32 ref_and_mask_sdma3; >+ u32 ref_and_mask_sdma4; >+ u32 ref_and_mask_sdma5; >+ u32 ref_and_mask_sdma6; >+ u32 ref_and_mask_sdma7; > }; > > struct amdgpu_mmio_remap { >@@ -668,7 +688,7 @@ > void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, > bool use_doorbell, int doorbell_index, int doorbell_size); > void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell, >- int doorbell_index); >+ int doorbell_index, int instance); > void (*enable_doorbell_aperture)(struct amdgpu_device *adev, > bool enable); > void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, >@@ -705,6 +725,9 @@ > int is_disable); > void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, > uint64_t *count); >+ uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val); >+ void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val, >+ uint32_t ficadl_val, uint32_t ficadh_val); > }; > /* Define the HW IP blocks will be used in driver , add more if necessary */ > enum amd_hw_ip_block_type { >@@ -712,6 +735,12 @@ > HDP_HWIP, > SDMA0_HWIP, > SDMA1_HWIP, >+ SDMA2_HWIP, >+ SDMA3_HWIP, >+ SDMA4_HWIP, >+ SDMA5_HWIP, >+ SDMA6_HWIP, >+ SDMA7_HWIP, > MMHUB_HWIP, > ATHUB_HWIP, > NBIO_HWIP, >@@ -728,10 +757,12 @@ > NBIF_HWIP, > THM_HWIP, > CLK_HWIP, >+ UMC_HWIP, >+ RSMU_HWIP, > MAX_HWIP > }; > >-#define HWIP_MAX_INSTANCE 6 >+#define HWIP_MAX_INSTANCE 8 > > struct amd_powerplay { > void *pp_handle; >@@ -758,7 +789,6 @@ > int usec_timeout; > const struct amdgpu_asic_funcs *asic_funcs; > bool shutdown; >- bool need_dma32; > bool need_swiotlb; > bool accel_working; > struct notifier_block acpi_nb; >@@ -803,6 +833,8 @@ > amdgpu_wreg_t pcie_wreg; > amdgpu_rreg_t pciep_rreg; > amdgpu_wreg_t pciep_wreg; >+ amdgpu_rreg64_t pcie_rreg64; >+ amdgpu_wreg64_t pcie_wreg64; > /* protects concurrent UVD register access */ > spinlock_t uvd_ctx_idx_lock; > amdgpu_rreg_t uvd_ctx_rreg; >@@ -836,6 +868,7 @@ > dma_addr_t dummy_page_addr; > struct amdgpu_vm_manager vm_manager; > struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; >+ unsigned num_vmhubs; > > /* memory management */ > struct amdgpu_mman mman; >@@ -915,6 +948,9 @@ > /* KFD */ > struct amdgpu_kfd_dev kfd; > >+ /* UMC */ >+ struct amdgpu_umc umc; >+ > /* display related functionality */ > struct amdgpu_display_manager dm; > >@@ -940,6 +976,7 @@ > > const struct amdgpu_nbio_funcs *nbio_funcs; > const struct amdgpu_df_funcs *df_funcs; >+ const struct amdgpu_mmhub_funcs *mmhub_funcs; > > /* delayed work_func for deferring clockgating during resume */ > struct delayed_work delayed_init_work; >@@ -965,6 +1002,7 @@ > /* record last mm index being written through WREG32*/ > unsigned long last_mm_index; > bool in_gpu_reset; >+ enum pp_mp1_state mp1_state; > struct mutex lock_reset; > struct amdgpu_doorbell_index doorbell_index; > >@@ -1033,6 +1071,8 @@ > #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) > #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) > #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) >+#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) >+#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) > #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) > #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) > #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) >@@ -1093,6 +1133,7 @@ > */ > #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) > #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) >+#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) > #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) > #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) > #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) >@@ -1110,6 +1151,7 @@ > #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) > #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) > #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) >+#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); > > /* Common functions */ > bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c 2019-08-31 15:01:11.842736167 -0500 >@@ -368,7 +368,8 @@ > * are broken on Navi10 and Navi14. > */ > if (needs_flush && (adev->asic_type < CHIP_VEGA10 || >- adev->asic_type == CHIP_NAVI10)) >+ adev->asic_type == CHIP_NAVI10 || >+ adev->asic_type == CHIP_NAVI14)) > continue; > > /* Good, we can use this VMID. Remember this submission as >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 2019-08-31 15:01:11.842736167 -0500 >@@ -408,23 +408,38 @@ > break; > case AMDGPU_HW_IP_VCN_DEC: > type = AMD_IP_BLOCK_TYPE_VCN; >- if (adev->vcn.ring_dec.sched.ready) >- ++num_rings; >+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) { >+ if (adev->uvd.harvest_config & (1 << i)) >+ continue; >+ >+ if (adev->vcn.inst[i].ring_dec.sched.ready) >+ ++num_rings; >+ } > ib_start_alignment = 16; > ib_size_alignment = 16; > break; > case AMDGPU_HW_IP_VCN_ENC: > type = AMD_IP_BLOCK_TYPE_VCN; >- for (i = 0; i < adev->vcn.num_enc_rings; i++) >- if (adev->vcn.ring_enc[i].sched.ready) >- ++num_rings; >+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) { >+ if (adev->uvd.harvest_config & (1 << i)) >+ continue; >+ >+ for (j = 0; j < adev->vcn.num_enc_rings; j++) >+ if (adev->vcn.inst[i].ring_enc[j].sched.ready) >+ ++num_rings; >+ } > ib_start_alignment = 64; > ib_size_alignment = 1; > break; > case AMDGPU_HW_IP_VCN_JPEG: > type = AMD_IP_BLOCK_TYPE_VCN; >- if (adev->vcn.ring_jpeg.sched.ready) >- ++num_rings; >+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) { >+ if (adev->uvd.harvest_config & (1 << i)) >+ continue; >+ >+ if (adev->vcn.inst[i].ring_jpeg.sched.ready) >+ ++num_rings; >+ } > ib_start_alignment = 16; > ib_size_alignment = 16; > break; >@@ -1088,7 +1103,7 @@ > amdgpu_vm_fini(adev, &fpriv->vm); > > if (pasid) >- amdgpu_pasid_free_delayed(pd->tbo.resv, pasid); >+ amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); > amdgpu_bo_unref(&pd); > > idr_for_each_entry(&fpriv->bo_list_handles, list, handle) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h 2019-08-31 15:01:11.842736167 -0500 >@@ -0,0 +1,31 @@ >+/* >+ * Copyright (C) 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included >+ * in all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN >+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN >+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. >+ */ >+#ifndef __AMDGPU_MMHUB_H__ >+#define __AMDGPU_MMHUB_H__ >+ >+struct amdgpu_mmhub_funcs { >+ void (*ras_init)(struct amdgpu_device *adev); >+ void (*query_ras_error_count)(struct amdgpu_device *adev, >+ void *ras_error_status); >+}; >+ >+#endif >+ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 2019-08-31 15:01:11.842736167 -0500 >@@ -179,7 +179,7 @@ > if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end)) > continue; > >- r = reservation_object_wait_timeout_rcu(bo->tbo.resv, >+ r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv, > true, false, MAX_SCHEDULE_TIMEOUT); > if (r <= 0) > DRM_ERROR("(%ld) failed to wait for user bo\n", r); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 2019-08-31 15:01:11.842736167 -0500 >@@ -80,14 +80,11 @@ > if (bo->pin_count > 0) > amdgpu_bo_subtract_pin_size(bo); > >- if (bo->kfd_bo) >- amdgpu_amdkfd_unreserve_memory_limit(bo); >- > amdgpu_bo_kunmap(bo); > >- if (bo->gem_base.import_attach) >- drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); >- drm_gem_object_release(&bo->gem_base); >+ if (bo->tbo.base.import_attach) >+ drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); >+ drm_gem_object_release(&bo->tbo.base); > /* in case amdgpu_device_recover_vram got NULL of bo->parent */ > if (!list_empty(&bo->shadow_list)) { > mutex_lock(&adev->shadow_list_lock); >@@ -249,8 +246,9 @@ > bp.size = size; > bp.byte_align = align; > bp.domain = domain; >- bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | >- AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; >+ bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED >+ : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; >+ bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; > bp.type = ttm_bo_type_kernel; > bp.resv = NULL; > >@@ -413,6 +411,40 @@ > return false; > } > >+bool amdgpu_bo_support_uswc(u64 bo_flags) >+{ >+ >+#ifdef CONFIG_X86_32 >+ /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit >+ * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 >+ */ >+ return false; >+#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) >+ /* Don't try to enable write-combining when it can't work, or things >+ * may be slow >+ * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 >+ */ >+ >+#ifndef CONFIG_COMPILE_TEST >+#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ >+ thanks to write-combining >+#endif >+ >+ if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) >+ DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " >+ "better performance thanks to write-combining\n"); >+ return false; >+#else >+ /* For architectures that don't support WC memory, >+ * mask out the WC flag from the BO >+ */ >+ if (!drm_arch_can_wc_memory()) >+ return false; >+ >+ return true; >+#endif >+} >+ > static int amdgpu_bo_do_create(struct amdgpu_device *adev, > struct amdgpu_bo_param *bp, > struct amdgpu_bo **bo_ptr) >@@ -454,7 +486,7 @@ > bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); > if (bo == NULL) > return -ENOMEM; >- drm_gem_private_object_init(adev->ddev, &bo->gem_base, size); >+ drm_gem_private_object_init(adev->ddev, &bo->tbo.base, size); > INIT_LIST_HEAD(&bo->shadow_list); > bo->vm_bo = NULL; > bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : >@@ -466,33 +498,8 @@ > > bo->flags = bp->flags; > >-#ifdef CONFIG_X86_32 >- /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit >- * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 >- */ >- bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; >-#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) >- /* Don't try to enable write-combining when it can't work, or things >- * may be slow >- * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 >- */ >- >-#ifndef CONFIG_COMPILE_TEST >-#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ >- thanks to write-combining >-#endif >- >- if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) >- DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " >- "better performance thanks to write-combining\n"); >- bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; >-#else >- /* For architectures that don't support WC memory, >- * mask out the WC flag from the BO >- */ >- if (!drm_arch_can_wc_memory()) >+ if (!amdgpu_bo_support_uswc(bo->flags)) > bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; >-#endif > > bo->tbo.bdev = &adev->mman.bdev; > if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | >@@ -521,7 +528,7 @@ > bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { > struct dma_fence *fence; > >- r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); >+ r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); > if (unlikely(r)) > goto fail_unreserve; > >@@ -544,7 +551,7 @@ > > fail_unreserve: > if (!bp->resv) >- ww_mutex_unlock(&bo->tbo.resv->lock); >+ reservation_object_unlock(bo->tbo.base.resv); > amdgpu_bo_unref(&bo); > return r; > } >@@ -565,7 +572,7 @@ > bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | > AMDGPU_GEM_CREATE_SHADOW; > bp.type = ttm_bo_type_kernel; >- bp.resv = bo->tbo.resv; >+ bp.resv = bo->tbo.base.resv; > > r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); > if (!r) { >@@ -606,13 +613,13 @@ > > if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { > if (!bp->resv) >- WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv, >+ WARN_ON(reservation_object_lock((*bo_ptr)->tbo.base.resv, > NULL)); > > r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); > > if (!bp->resv) >- reservation_object_unlock((*bo_ptr)->tbo.resv); >+ reservation_object_unlock((*bo_ptr)->tbo.base.resv); > > if (r) > amdgpu_bo_unref(bo_ptr); >@@ -709,7 +716,7 @@ > return 0; > } > >- r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, >+ r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv, false, false, > MAX_SCHEDULE_TIMEOUT); > if (r < 0) > return r; >@@ -1087,7 +1094,7 @@ > */ > void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) > { >- lockdep_assert_held(&bo->tbo.resv->lock.base); >+ reservation_object_assert_held(bo->tbo.base.resv); > > if (tiling_flags) > *tiling_flags = bo->tiling_flags; >@@ -1212,6 +1219,42 @@ > } > > /** >+ * amdgpu_bo_move_notify - notification about a BO being released >+ * @bo: pointer to a buffer object >+ * >+ * Wipes VRAM buffers whose contents should not be leaked before the >+ * memory is released. >+ */ >+void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) >+{ >+ struct dma_fence *fence = NULL; >+ struct amdgpu_bo *abo; >+ int r; >+ >+ if (!amdgpu_bo_is_amdgpu_bo(bo)) >+ return; >+ >+ abo = ttm_to_amdgpu_bo(bo); >+ >+ if (abo->kfd_bo) >+ amdgpu_amdkfd_unreserve_memory_limit(abo); >+ >+ if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || >+ !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) >+ return; >+ >+ reservation_object_lock(bo->base.resv, NULL); >+ >+ r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); >+ if (!WARN_ON(r)) { >+ amdgpu_bo_fence(abo, fence, false); >+ dma_fence_put(fence); >+ } >+ >+ reservation_object_unlock(bo->base.resv); >+} >+ >+/** > * amdgpu_bo_fault_reserve_notify - notification about a memory fault > * @bo: pointer to a buffer object > * >@@ -1283,7 +1326,7 @@ > void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, > bool shared) > { >- struct reservation_object *resv = bo->tbo.resv; >+ struct reservation_object *resv = bo->tbo.base.resv; > > if (shared) > reservation_object_add_shared_fence(resv, fence); >@@ -1308,7 +1351,7 @@ > int r; > > amdgpu_sync_create(&sync); >- amdgpu_sync_resv(adev, &sync, bo->tbo.resv, owner, false); >+ amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, owner, false); > r = amdgpu_sync_wait(&sync, intr); > amdgpu_sync_free(&sync); > >@@ -1328,7 +1371,7 @@ > u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) > { > WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); >- WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && >+ WARN_ON_ONCE(!reservation_object_is_locked(bo->tbo.base.resv) && > !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel); > WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); > WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 2019-08-31 15:01:11.842736167 -0500 >@@ -94,7 +94,6 @@ > /* per VM structure for page tables and with virtual addresses */ > struct amdgpu_vm_bo_base *vm_bo; > /* Constant after initialization */ >- struct drm_gem_object gem_base; > struct amdgpu_bo *parent; > struct amdgpu_bo *shadow; > >@@ -192,7 +191,7 @@ > */ > static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) > { >- return drm_vma_node_offset_addr(&bo->tbo.vma_node); >+ return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); > } > > /** >@@ -265,6 +264,7 @@ > void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, > bool evict, > struct ttm_mem_reg *new_mem); >+void amdgpu_bo_release_notify(struct ttm_buffer_object *bo); > int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); > void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, > bool shared); >@@ -308,5 +308,7 @@ > struct seq_file *m); > #endif > >+bool amdgpu_bo_support_uswc(u64 bo_flags); >+ > > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 2019-08-31 15:01:11.843736167 -0500 >@@ -325,13 +325,6 @@ > (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) > return -EINVAL; > >- if (!amdgpu_sriov_vf(adev)) { >- if (is_support_sw_smu(adev)) >- current_level = smu_get_performance_level(&adev->smu); >- else if (adev->powerplay.pp_funcs->get_performance_level) >- current_level = amdgpu_dpm_get_performance_level(adev); >- } >- > if (strncmp("low", buf, strlen("low")) == 0) { > level = AMD_DPM_FORCED_LEVEL_LOW; > } else if (strncmp("high", buf, strlen("high")) == 0) { >@@ -355,17 +348,23 @@ > goto fail; > } > >- if (amdgpu_sriov_vf(adev)) { >- if (amdgim_is_hwperf(adev) && >- adev->virt.ops->force_dpm_level) { >- mutex_lock(&adev->pm.mutex); >- adev->virt.ops->force_dpm_level(adev, level); >- mutex_unlock(&adev->pm.mutex); >- return count; >- } else { >- return -EINVAL; >+ /* handle sriov case here */ >+ if (amdgpu_sriov_vf(adev)) { >+ if (amdgim_is_hwperf(adev) && >+ adev->virt.ops->force_dpm_level) { >+ mutex_lock(&adev->pm.mutex); >+ adev->virt.ops->force_dpm_level(adev, level); >+ mutex_unlock(&adev->pm.mutex); >+ return count; >+ } else { >+ return -EINVAL; > } >- } >+ } >+ >+ if (is_support_sw_smu(adev)) >+ current_level = smu_get_performance_level(&adev->smu); >+ else if (adev->powerplay.pp_funcs->get_performance_level) >+ current_level = amdgpu_dpm_get_performance_level(adev); > > if (current_level == level) > return count; >@@ -746,10 +745,10 @@ > } > > /** >- * DOC: ppfeatures >+ * DOC: pp_features > * > * The amdgpu driver provides a sysfs API for adjusting what powerplay >- * features to be enabled. The file ppfeatures is used for this. And >+ * features to be enabled. The file pp_features is used for this. And > * this is only available for Vega10 and later dGPUs. > * > * Reading back the file will show you the followings: >@@ -761,7 +760,7 @@ > * the corresponding bit from original ppfeature masks and input the > * new ppfeature masks. > */ >-static ssize_t amdgpu_set_ppfeature_status(struct device *dev, >+static ssize_t amdgpu_set_pp_feature_status(struct device *dev, > struct device_attribute *attr, > const char *buf, > size_t count) >@@ -778,7 +777,7 @@ > pr_debug("featuremask = 0x%llx\n", featuremask); > > if (is_support_sw_smu(adev)) { >- ret = smu_set_ppfeature_status(&adev->smu, featuremask); >+ ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask); > if (ret) > return -EINVAL; > } else if (adev->powerplay.pp_funcs->set_ppfeature_status) { >@@ -790,7 +789,7 @@ > return count; > } > >-static ssize_t amdgpu_get_ppfeature_status(struct device *dev, >+static ssize_t amdgpu_get_pp_feature_status(struct device *dev, > struct device_attribute *attr, > char *buf) > { >@@ -798,7 +797,7 @@ > struct amdgpu_device *adev = ddev->dev_private; > > if (is_support_sw_smu(adev)) { >- return smu_get_ppfeature_status(&adev->smu, buf); >+ return smu_sys_get_pp_feature_mask(&adev->smu, buf); > } else if (adev->powerplay.pp_funcs->get_ppfeature_status) > return amdgpu_dpm_get_ppfeature_status(adev, buf); > >@@ -1458,9 +1457,9 @@ > static DEVICE_ATTR(mem_busy_percent, S_IRUGO, > amdgpu_get_memory_busy_percent, NULL); > static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL); >-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR, >- amdgpu_get_ppfeature_status, >- amdgpu_set_ppfeature_status); >+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR, >+ amdgpu_get_pp_feature_status, >+ amdgpu_set_pp_feature_status); > static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL); > > static ssize_t amdgpu_hwmon_show_temp(struct device *dev, >@@ -1625,20 +1624,16 @@ > (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON)) > return -EINVAL; > >- if (is_support_sw_smu(adev)) { >- err = kstrtoint(buf, 10, &value); >- if (err) >- return err; >+ err = kstrtoint(buf, 10, &value); >+ if (err) >+ return err; > >+ if (is_support_sw_smu(adev)) { > smu_set_fan_control_mode(&adev->smu, value); > } else { > if (!adev->powerplay.pp_funcs->set_fan_control_mode) > return -EINVAL; > >- err = kstrtoint(buf, 10, &value); >- if (err) >- return err; >- > amdgpu_dpm_set_fan_control_mode(adev, value); > } > >@@ -2058,16 +2053,18 @@ > return err; > > value = value / 1000000; /* convert to Watt */ >+ > if (is_support_sw_smu(adev)) { >- adev->smu.funcs->set_power_limit(&adev->smu, value); >+ err = smu_set_power_limit(&adev->smu, value); > } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) { > err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value); >- if (err) >- return err; > } else { >- return -EINVAL; >+ err = -EINVAL; > } > >+ if (err) >+ return err; >+ > return count; > } > >@@ -2352,7 +2349,9 @@ > effective_mode &= ~S_IWUSR; > } > >- if ((adev->flags & AMD_IS_APU) && >+ if (((adev->flags & AMD_IS_APU) || >+ adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ >+ adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */ > (attr == &sensor_dev_attr_power1_average.dev_attr.attr || > attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || > attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr|| >@@ -2376,6 +2375,12 @@ > return 0; > } > >+ if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ >+ adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */ >+ (attr == &sensor_dev_attr_in0_input.dev_attr.attr || >+ attr == &sensor_dev_attr_in0_label.dev_attr.attr)) >+ return 0; >+ > /* only APUs have vddnb */ > if (!(adev->flags & AMD_IS_APU) && > (attr == &sensor_dev_attr_in1_input.dev_attr.attr || >@@ -2831,10 +2836,12 @@ > DRM_ERROR("failed to create device file pp_dpm_socclk\n"); > return ret; > } >- ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk); >- if (ret) { >- DRM_ERROR("failed to create device file pp_dpm_dcefclk\n"); >- return ret; >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk); >+ if (ret) { >+ DRM_ERROR("failed to create device file pp_dpm_dcefclk\n"); >+ return ret; >+ } > } > } > if (adev->asic_type >= CHIP_VEGA20) { >@@ -2844,10 +2851,12 @@ > return ret; > } > } >- ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie); >- if (ret) { >- DRM_ERROR("failed to create device file pp_dpm_pcie\n"); >- return ret; >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie); >+ if (ret) { >+ DRM_ERROR("failed to create device file pp_dpm_pcie\n"); >+ return ret; >+ } > } > ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od); > if (ret) { >@@ -2917,10 +2926,10 @@ > if ((adev->asic_type >= CHIP_VEGA10) && > !(adev->flags & AMD_IS_APU)) { > ret = device_create_file(adev->dev, >- &dev_attr_ppfeatures); >+ &dev_attr_pp_features); > if (ret) { > DRM_ERROR("failed to create device file " >- "ppfeatures\n"); >+ "pp_features\n"); > return ret; > } > } >@@ -2951,9 +2960,11 @@ > device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk); > if (adev->asic_type >= CHIP_VEGA10) { > device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk); >- device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk); >+ if (adev->asic_type != CHIP_ARCTURUS) >+ device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk); > } >- device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie); >+ if (adev->asic_type != CHIP_ARCTURUS) >+ device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie); > if (adev->asic_type >= CHIP_VEGA20) > device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk); > device_remove_file(adev->dev, &dev_attr_pp_sclk_od); >@@ -2974,7 +2985,7 @@ > device_remove_file(adev->dev, &dev_attr_unique_id); > if ((adev->asic_type >= CHIP_VEGA10) && > !(adev->flags & AMD_IS_APU)) >- device_remove_file(adev->dev, &dev_attr_ppfeatures); >+ device_remove_file(adev->dev, &dev_attr_pp_features); > } > > void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 2019-08-31 15:01:11.843736167 -0500 >@@ -32,6 +32,7 @@ > #include "psp_v3_1.h" > #include "psp_v10_0.h" > #include "psp_v11_0.h" >+#include "psp_v12_0.h" > > static void psp_set_funcs(struct amdgpu_device *adev); > >@@ -53,13 +54,19 @@ > psp->autoload_supported = false; > break; > case CHIP_VEGA20: >+ case CHIP_ARCTURUS: > psp_v11_0_set_psp_funcs(psp); > psp->autoload_supported = false; > break; > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > psp_v11_0_set_psp_funcs(psp); > psp->autoload_supported = true; > break; >+ case CHIP_RENOIR: >+ psp_v12_0_set_psp_funcs(psp); >+ break; > default: > return -EINVAL; > } >@@ -137,8 +144,7 @@ > memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); > > index = atomic_inc_return(&psp->fence_value); >- ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, >- fence_mc_addr, index); >+ ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); > if (ret) { > atomic_dec(&psp->fence_value); > mutex_unlock(&psp->mutex); >@@ -162,8 +168,8 @@ > if (ucode) > DRM_WARN("failed to load ucode id (%d) ", > ucode->ucode_id); >- DRM_WARN("psp command failed and response status is (%d)\n", >- psp->cmd_buf_mem->resp.status); >+ DRM_WARN("psp command failed and response status is (0x%X)\n", >+ psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK); > if (!timeout) { > mutex_unlock(&psp->mutex); > return -EINVAL; >@@ -233,6 +239,8 @@ > { > int ret; > int tmr_size; >+ void *tmr_buf; >+ void **pptr; > > /* > * According to HW engineer, they prefer the TMR address be "naturally >@@ -255,9 +263,10 @@ > } > } > >+ pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; > ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, > AMDGPU_GEM_DOMAIN_VRAM, >- &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); >+ &psp->tmr_bo, &psp->tmr_mc_addr, pptr); > > return ret; > } >@@ -831,7 +840,6 @@ > "XGMI: Failed to initialize XGMI session\n"); > } > >- > if (psp->adev->psp.ta_fw) { > ret = psp_ras_initialize(psp); > if (ret) >@@ -852,6 +860,24 @@ > case AMDGPU_UCODE_ID_SDMA1: > *type = GFX_FW_TYPE_SDMA1; > break; >+ case AMDGPU_UCODE_ID_SDMA2: >+ *type = GFX_FW_TYPE_SDMA2; >+ break; >+ case AMDGPU_UCODE_ID_SDMA3: >+ *type = GFX_FW_TYPE_SDMA3; >+ break; >+ case AMDGPU_UCODE_ID_SDMA4: >+ *type = GFX_FW_TYPE_SDMA4; >+ break; >+ case AMDGPU_UCODE_ID_SDMA5: >+ *type = GFX_FW_TYPE_SDMA5; >+ break; >+ case AMDGPU_UCODE_ID_SDMA6: >+ *type = GFX_FW_TYPE_SDMA6; >+ break; >+ case AMDGPU_UCODE_ID_SDMA7: >+ *type = GFX_FW_TYPE_SDMA7; >+ break; > case AMDGPU_UCODE_ID_CP_CE: > *type = GFX_FW_TYPE_CP_CE; > break; >@@ -920,6 +946,60 @@ > return 0; > } > >+static void psp_print_fw_hdr(struct psp_context *psp, >+ struct amdgpu_firmware_info *ucode) >+{ >+ struct amdgpu_device *adev = psp->adev; >+ const struct sdma_firmware_header_v1_0 *sdma_hdr = >+ (const struct sdma_firmware_header_v1_0 *) >+ adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; >+ const struct gfx_firmware_header_v1_0 *ce_hdr = >+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; >+ const struct gfx_firmware_header_v1_0 *pfp_hdr = >+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; >+ const struct gfx_firmware_header_v1_0 *me_hdr = >+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; >+ const struct gfx_firmware_header_v1_0 *mec_hdr = >+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; >+ const struct rlc_firmware_header_v2_0 *rlc_hdr = >+ (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; >+ const struct smc_firmware_header_v1_0 *smc_hdr = >+ (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data; >+ >+ switch (ucode->ucode_id) { >+ case AMDGPU_UCODE_ID_SDMA0: >+ case AMDGPU_UCODE_ID_SDMA1: >+ case AMDGPU_UCODE_ID_SDMA2: >+ case AMDGPU_UCODE_ID_SDMA3: >+ case AMDGPU_UCODE_ID_SDMA4: >+ case AMDGPU_UCODE_ID_SDMA5: >+ case AMDGPU_UCODE_ID_SDMA6: >+ case AMDGPU_UCODE_ID_SDMA7: >+ amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header); >+ break; >+ case AMDGPU_UCODE_ID_CP_CE: >+ amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); >+ break; >+ case AMDGPU_UCODE_ID_CP_PFP: >+ amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); >+ break; >+ case AMDGPU_UCODE_ID_CP_ME: >+ amdgpu_ucode_print_gfx_hdr(&me_hdr->header); >+ break; >+ case AMDGPU_UCODE_ID_CP_MEC1: >+ amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); >+ break; >+ case AMDGPU_UCODE_ID_RLC_G: >+ amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header); >+ break; >+ case AMDGPU_UCODE_ID_SMC: >+ amdgpu_ucode_print_smc_hdr(&smc_hdr->header); >+ break; >+ default: >+ break; >+ } >+} >+ > static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, > struct psp_gfx_cmd_resp *cmd) > { >@@ -980,17 +1060,31 @@ > if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && > (psp_smu_reload_quirk(psp) || psp->autoload_supported)) > continue; >+ > if (amdgpu_sriov_vf(adev) && > (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 > || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 >+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 >+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 >+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 >+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 >+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 >+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 > || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) > /*skip ucode loading in SRIOV VF */ > continue; >+ > if (psp->autoload_supported && > (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || > ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) > /* skip mec JT when autoload is enabled */ > continue; >+ /* Renoir only needs to load mec jump table one time */ >+ if (adev->asic_type == CHIP_RENOIR && >+ ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) >+ continue; >+ >+ psp_print_fw_hdr(psp, ucode); > > ret = psp_execute_np_fw_load(psp, ucode); > if (ret) >@@ -1115,6 +1209,8 @@ > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > struct psp_context *psp = &adev->psp; >+ void *tmr_buf; >+ void **pptr; > > if (adev->gmc.xgmi.num_physical_nodes > 1 && > psp->xgmi_context.initialized == 1) >@@ -1125,7 +1221,8 @@ > > psp_ring_destroy(psp, PSP_RING_TYPE__KM); > >- amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); >+ pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; >+ amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); > amdgpu_bo_free_kernel(&psp->fw_pri_bo, > &psp->fw_pri_mc_addr, &psp->fw_pri_buf); > amdgpu_bo_free_kernel(&psp->fence_buf_bo, >@@ -1328,4 +1425,13 @@ > .minor = 0, > .rev = 0, > .funcs = &psp_ip_funcs, >+}; >+ >+const struct amdgpu_ip_block_version psp_v12_0_ip_block = >+{ >+ .type = AMD_IP_BLOCK_TYPE_PSP, >+ .major = 12, >+ .minor = 0, >+ .rev = 0, >+ .funcs = &psp_ip_funcs, > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 2019-08-31 15:01:11.843736167 -0500 >@@ -90,7 +90,6 @@ > int (*ring_destroy)(struct psp_context *psp, > enum psp_ring_type ring_type); > int (*cmd_submit)(struct psp_context *psp, >- struct amdgpu_firmware_info *ucode, > uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, > int index); > bool (*compare_sram_data)(struct psp_context *psp, >@@ -172,7 +171,6 @@ > /* tmr buffer */ > struct amdgpu_bo *tmr_bo; > uint64_t tmr_mc_addr; >- void *tmr_buf; > > /* asd firmware and buffer */ > const struct firmware *asd_fw; >@@ -223,8 +221,8 @@ > #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) > #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) > #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) >-#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ >- (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) >+#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \ >+ (psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index)) > #define psp_compare_sram_data(psp, ucode, type) \ > (psp)->funcs->compare_sram_data((psp), (ucode), (type)) > #define psp_init_microcode(psp) \ >@@ -270,6 +268,7 @@ > uint32_t field_val, uint32_t mask, bool check_changed); > > extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; >+extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; > > int psp_gpu_reset(struct amdgpu_device *adev); > int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 2019-08-31 15:01:11.843736167 -0500 >@@ -30,74 +30,6 @@ > #include "amdgpu_ras.h" > #include "amdgpu_atomfirmware.h" > >-struct ras_ih_data { >- /* interrupt bottom half */ >- struct work_struct ih_work; >- int inuse; >- /* IP callback */ >- ras_ih_cb cb; >- /* full of entries */ >- unsigned char *ring; >- unsigned int ring_size; >- unsigned int element_size; >- unsigned int aligned_element_size; >- unsigned int rptr; >- unsigned int wptr; >-}; >- >-struct ras_fs_data { >- char sysfs_name[32]; >- char debugfs_name[32]; >-}; >- >-struct ras_err_data { >- unsigned long ue_count; >- unsigned long ce_count; >-}; >- >-struct ras_err_handler_data { >- /* point to bad pages array */ >- struct { >- unsigned long bp; >- struct amdgpu_bo *bo; >- } *bps; >- /* the count of entries */ >- int count; >- /* the space can place new entries */ >- int space_left; >- /* last reserved entry's index + 1 */ >- int last_reserved; >-}; >- >-struct ras_manager { >- struct ras_common_if head; >- /* reference count */ >- int use; >- /* ras block link */ >- struct list_head node; >- /* the device */ >- struct amdgpu_device *adev; >- /* debugfs */ >- struct dentry *ent; >- /* sysfs */ >- struct device_attribute sysfs_attr; >- int attr_inuse; >- >- /* fs node name */ >- struct ras_fs_data fs_data; >- >- /* IH data */ >- struct ras_ih_data ih_data; >- >- struct ras_err_data err_data; >-}; >- >-struct ras_badpage { >- unsigned int bp; >- unsigned int size; >- unsigned int flags; >-}; >- > const char *ras_error_string[] = { > "none", > "parity", >@@ -130,6 +62,9 @@ > #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2 > #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) > >+/* inject address is 52 bits */ >+#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) >+ > static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev, > uint64_t offset, uint64_t size, > struct amdgpu_bo **bo_ptr); >@@ -196,6 +131,7 @@ > char err[9] = "ue"; > int op = -1; > int block_id; >+ uint32_t sub_block; > u64 address, value; > > if (*pos) >@@ -223,17 +159,23 @@ > return -EINVAL; > > data->head.block = block_id; >- data->head.type = memcmp("ue", err, 2) == 0 ? >- AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE : >- AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; >+ /* only ue and ce errors are supported */ >+ if (!memcmp("ue", err, 2)) >+ data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; >+ else if (!memcmp("ce", err, 2)) >+ data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; >+ else >+ return -EINVAL; >+ > data->op = op; > > if (op == 2) { >- if (sscanf(str, "%*s %*s %*s %llu %llu", >- &address, &value) != 2) >- if (sscanf(str, "%*s %*s %*s 0x%llx 0x%llx", >- &address, &value) != 2) >+ if (sscanf(str, "%*s %*s %*s %u %llu %llu", >+ &sub_block, &address, &value) != 3) >+ if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", >+ &sub_block, &address, &value) != 3) > return -EINVAL; >+ data->head.sub_block_index = sub_block; > data->inject.address = address; > data->inject.value = value; > } >@@ -278,7 +220,7 @@ > * write the struct to the control node. > * > * bash: >- * echo op block [error [address value]] > .../ras/ras_ctrl >+ * echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl > * op: disable, enable, inject > * disable: only block is needed > * enable: block and error are needed >@@ -288,10 +230,11 @@ > * error: ue, ce > * ue: multi_uncorrectable > * ce: single_correctable >+ * sub_block: sub block index, pass 0 if there is no sub block > * > * here are some examples for bash commands, >- * echo inject umc ue 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl >- * echo inject umc ce 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl >+ * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl >+ * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl > * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl > * > * How to check the result? >@@ -310,7 +253,6 @@ > { > struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; > struct ras_debug_if data; >- struct amdgpu_bo *bo; > int ret = 0; > > ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); >@@ -328,17 +270,14 @@ > ret = amdgpu_ras_feature_enable(adev, &data.head, 1); > break; > case 2: >- ret = amdgpu_ras_reserve_vram(adev, >- data.inject.address, PAGE_SIZE, &bo); >- if (ret) { >- /* address was offset, now it is absolute.*/ >- data.inject.address += adev->gmc.vram_start; >- if (data.inject.address > adev->gmc.vram_end) >- break; >- } else >- data.inject.address = amdgpu_bo_gpu_offset(bo); >+ if ((data.inject.address >= adev->gmc.mc_vram_size) || >+ (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { >+ ret = -EINVAL; >+ break; >+ } >+ >+ /* data.inject.address is offset instead of absolute gpu address */ > ret = amdgpu_ras_error_inject(adev, &data.inject); >- amdgpu_ras_release_vram(adev, &bo); > break; > default: > ret = -EINVAL; >@@ -656,14 +595,46 @@ > struct ras_query_if *info) > { > struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); >+ struct ras_err_data err_data = {0, 0, 0, NULL}; > > if (!obj) > return -EINVAL; >- /* TODO might read the register to read the count */ >+ >+ switch (info->head.block) { >+ case AMDGPU_RAS_BLOCK__UMC: >+ if (adev->umc.funcs->query_ras_error_count) >+ adev->umc.funcs->query_ras_error_count(adev, &err_data); >+ /* umc query_ras_error_address is also responsible for clearing >+ * error status >+ */ >+ if (adev->umc.funcs->query_ras_error_address) >+ adev->umc.funcs->query_ras_error_address(adev, &err_data); >+ break; >+ case AMDGPU_RAS_BLOCK__GFX: >+ if (adev->gfx.funcs->query_ras_error_count) >+ adev->gfx.funcs->query_ras_error_count(adev, &err_data); >+ break; >+ case AMDGPU_RAS_BLOCK__MMHUB: >+ if (adev->mmhub_funcs->query_ras_error_count) >+ adev->mmhub_funcs->query_ras_error_count(adev, &err_data); >+ break; >+ default: >+ break; >+ } >+ >+ obj->err_data.ue_count += err_data.ue_count; >+ obj->err_data.ce_count += err_data.ce_count; > > info->ue_count = obj->err_data.ue_count; > info->ce_count = obj->err_data.ce_count; > >+ if (err_data.ce_count) >+ dev_info(adev->dev, "%ld correctable errors detected in %s block\n", >+ obj->err_data.ce_count, ras_block_str(info->head.block)); >+ if (err_data.ue_count) >+ dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n", >+ obj->err_data.ue_count, ras_block_str(info->head.block)); >+ > return 0; > } > >@@ -684,13 +655,23 @@ > if (!obj) > return -EINVAL; > >- if (block_info.block_id != TA_RAS_BLOCK__UMC) { >+ switch (info->head.block) { >+ case AMDGPU_RAS_BLOCK__GFX: >+ if (adev->gfx.funcs->ras_error_inject) >+ ret = adev->gfx.funcs->ras_error_inject(adev, info); >+ else >+ ret = -EINVAL; >+ break; >+ case AMDGPU_RAS_BLOCK__UMC: >+ case AMDGPU_RAS_BLOCK__MMHUB: >+ ret = psp_ras_trigger_error(&adev->psp, &block_info); >+ break; >+ default: > DRM_INFO("%s error injection is not supported yet\n", > ras_block_str(info->head.block)); >- return -EINVAL; >+ ret = -EINVAL; > } > >- ret = psp_ras_trigger_error(&adev->psp, &block_info); > if (ret) > DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n", > ras_block_str(info->head.block), >@@ -707,7 +688,7 @@ > } > > /* get the total error counts on all IPs */ >-int amdgpu_ras_query_error_count(struct amdgpu_device *adev, >+unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, > bool is_ce) > { > struct amdgpu_ras *con = amdgpu_ras_get_context(adev); >@@ -715,7 +696,7 @@ > struct ras_err_data data = {0, 0}; > > if (!con) >- return -EINVAL; >+ return 0; > > list_for_each_entry(obj, &con->head, node) { > struct ras_query_if info = { >@@ -723,7 +704,7 @@ > }; > > if (amdgpu_ras_error_query(adev, &info)) >- return -EINVAL; >+ return 0; > > data.ce_count += info.ce_count; > data.ue_count += info.ue_count; >@@ -812,32 +793,8 @@ > { > struct amdgpu_ras *con = > container_of(attr, struct amdgpu_ras, features_attr); >- struct drm_device *ddev = dev_get_drvdata(dev); >- struct amdgpu_device *adev = ddev->dev_private; >- struct ras_common_if head; >- int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; >- int i; >- ssize_t s; >- struct ras_manager *obj; >- >- s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); > >- for (i = 0; i < ras_block_count; i++) { >- head.block = i; >- >- if (amdgpu_ras_is_feature_enabled(adev, &head)) { >- obj = amdgpu_ras_find_obj(adev, &head); >- s += scnprintf(&buf[s], PAGE_SIZE - s, >- "%s: %s\n", >- ras_block_str(i), >- ras_err_str(obj->head.type)); >- } else >- s += scnprintf(&buf[s], PAGE_SIZE - s, >- "%s: disabled\n", >- ras_block_str(i)); >- } >- >- return s; >+ return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); > } > > static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev) >@@ -1054,6 +1011,7 @@ > struct ras_ih_data *data = &obj->ih_data; > struct amdgpu_iv_entry entry; > int ret; >+ struct ras_err_data err_data = {0, 0, 0, NULL}; > > while (data->rptr != data->wptr) { > rmb(); >@@ -1068,19 +1026,19 @@ > * from the callback to udpate the error type/count, etc > */ > if (data->cb) { >- ret = data->cb(obj->adev, &entry); >+ ret = data->cb(obj->adev, &err_data, &entry); > /* ue will trigger an interrupt, and in that case > * we need do a reset to recovery the whole system. > * But leave IP do that recovery, here we just dispatch > * the error. > */ >- if (ret == AMDGPU_RAS_UE) { >- obj->err_data.ue_count++; >+ if (ret == AMDGPU_RAS_SUCCESS) { >+ /* these counts could be left as 0 if >+ * some blocks do not count error number >+ */ >+ obj->err_data.ue_count += err_data.ue_count; >+ obj->err_data.ce_count += err_data.ce_count; > } >- /* Might need get ce count by register, but not all IP >- * saves ce count, some IP just use one bit or two bits >- * to indicate ce happened. >- */ > } > } > } >@@ -1577,6 +1535,10 @@ > if (amdgpu_ras_fs_init(adev)) > goto fs_out; > >+ /* ras init for each ras block */ >+ if (adev->umc.funcs->ras_init) >+ adev->umc.funcs->ras_init(adev); >+ > DRM_INFO("RAS INFO: ras initialized successfully, " > "hardware ability[%x] ras_mask[%x]\n", > con->hw_supported, con->supported); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 2019-08-31 15:01:11.843736167 -0500 >@@ -0,0 +1,493 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+ >+#include "amdgpu_ras_eeprom.h" >+#include "amdgpu.h" >+#include "amdgpu_ras.h" >+#include <linux/bits.h> >+#include "smu_v11_0_i2c.h" >+ >+#define EEPROM_I2C_TARGET_ADDR 0xA0 >+ >+/* >+ * The 2 macros bellow represent the actual size in bytes that >+ * those entities occupy in the EEPROM memory. >+ * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which >+ * uses uint64 to store 6b fields such as retired_page. >+ */ >+#define EEPROM_TABLE_HEADER_SIZE 20 >+#define EEPROM_TABLE_RECORD_SIZE 24 >+ >+#define EEPROM_ADDRESS_SIZE 0x2 >+ >+/* Table hdr is 'AMDR' */ >+#define EEPROM_TABLE_HDR_VAL 0x414d4452 >+#define EEPROM_TABLE_VER 0x00010000 >+ >+/* Assume 2 Mbit size */ >+#define EEPROM_SIZE_BYTES 256000 >+#define EEPROM_PAGE__SIZE_BYTES 256 >+#define EEPROM_HDR_START 0 >+#define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE) >+#define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE) >+#define EEPROM_ADDR_MSB_MASK GENMASK(17, 8) >+ >+#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev >+ >+static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr, >+ unsigned char *buff) >+{ >+ uint32_t *pp = (uint32_t *) buff; >+ >+ pp[0] = cpu_to_le32(hdr->header); >+ pp[1] = cpu_to_le32(hdr->version); >+ pp[2] = cpu_to_le32(hdr->first_rec_offset); >+ pp[3] = cpu_to_le32(hdr->tbl_size); >+ pp[4] = cpu_to_le32(hdr->checksum); >+} >+ >+static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr, >+ unsigned char *buff) >+{ >+ uint32_t *pp = (uint32_t *)buff; >+ >+ hdr->header = le32_to_cpu(pp[0]); >+ hdr->version = le32_to_cpu(pp[1]); >+ hdr->first_rec_offset = le32_to_cpu(pp[2]); >+ hdr->tbl_size = le32_to_cpu(pp[3]); >+ hdr->checksum = le32_to_cpu(pp[4]); >+} >+ >+static int __update_table_header(struct amdgpu_ras_eeprom_control *control, >+ unsigned char *buff) >+{ >+ int ret = 0; >+ struct i2c_msg msg = { >+ .addr = EEPROM_I2C_TARGET_ADDR, >+ .flags = 0, >+ .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, >+ .buf = buff, >+ }; >+ >+ >+ *(uint16_t *)buff = EEPROM_HDR_START; >+ __encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE); >+ >+ ret = i2c_transfer(&control->eeprom_accessor, &msg, 1); >+ if (ret < 1) >+ DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret); >+ >+ return ret; >+} >+ >+static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control); >+ >+int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) >+{ >+ int ret = 0; >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 }; >+ struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; >+ struct i2c_msg msg = { >+ .addr = EEPROM_I2C_TARGET_ADDR, >+ .flags = I2C_M_RD, >+ .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, >+ .buf = buff, >+ }; >+ >+ mutex_init(&control->tbl_mutex); >+ >+ switch (adev->asic_type) { >+ case CHIP_VEGA20: >+ ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor); >+ break; >+ >+ default: >+ return 0; >+ } >+ >+ if (ret) { >+ DRM_ERROR("Failed to init I2C controller, ret:%d", ret); >+ return ret; >+ } >+ >+ /* Read/Create table header from EEPROM address 0 */ >+ ret = i2c_transfer(&control->eeprom_accessor, &msg, 1); >+ if (ret < 1) { >+ DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret); >+ return ret; >+ } >+ >+ __decode_table_header_from_buff(hdr, &buff[2]); >+ >+ if (hdr->header == EEPROM_TABLE_HDR_VAL) { >+ control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) / >+ EEPROM_TABLE_RECORD_SIZE; >+ DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", >+ control->num_recs); >+ >+ } else { >+ DRM_INFO("Creating new EEPROM table"); >+ >+ hdr->header = EEPROM_TABLE_HDR_VAL; >+ hdr->version = EEPROM_TABLE_VER; >+ hdr->first_rec_offset = EEPROM_RECORD_START; >+ hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE; >+ >+ adev->psp.ras.ras->eeprom_control.tbl_byte_sum = >+ __calc_hdr_byte_sum(&adev->psp.ras.ras->eeprom_control); >+ ret = __update_table_header(control, buff); >+ } >+ >+ /* Start inserting records from here */ >+ adev->psp.ras.ras->eeprom_control.next_addr = EEPROM_RECORD_START; >+ >+ return ret == 1 ? 0 : -EIO; >+} >+ >+void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ >+ switch (adev->asic_type) { >+ case CHIP_VEGA20: >+ smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor); >+ break; >+ >+ default: >+ return; >+ } >+} >+ >+static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control, >+ struct eeprom_table_record *record, >+ unsigned char *buff) >+{ >+ __le64 tmp = 0; >+ int i = 0; >+ >+ /* Next are all record fields according to EEPROM page spec in LE foramt */ >+ buff[i++] = record->err_type; >+ >+ buff[i++] = record->bank; >+ >+ tmp = cpu_to_le64(record->ts); >+ memcpy(buff + i, &tmp, 8); >+ i += 8; >+ >+ tmp = cpu_to_le64((record->offset & 0xffffffffffff)); >+ memcpy(buff + i, &tmp, 6); >+ i += 6; >+ >+ buff[i++] = record->mem_channel; >+ buff[i++] = record->mcumc_id; >+ >+ tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); >+ memcpy(buff + i, &tmp, 6); >+} >+ >+static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control, >+ struct eeprom_table_record *record, >+ unsigned char *buff) >+{ >+ __le64 tmp = 0; >+ int i = 0; >+ >+ /* Next are all record fields according to EEPROM page spec in LE foramt */ >+ record->err_type = buff[i++]; >+ >+ record->bank = buff[i++]; >+ >+ memcpy(&tmp, buff + i, 8); >+ record->ts = le64_to_cpu(tmp); >+ i += 8; >+ >+ memcpy(&tmp, buff + i, 6); >+ record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); >+ i += 6; >+ >+ buff[i++] = record->mem_channel; >+ buff[i++] = record->mcumc_id; >+ >+ memcpy(&tmp, buff + i, 6); >+ record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); >+} >+ >+/* >+ * When reaching end of EEPROM memory jump back to 0 record address >+ * When next record access will go beyond EEPROM page boundary modify bits A17/A8 >+ * in I2C selector to go to next page >+ */ >+static uint32_t __correct_eeprom_dest_address(uint32_t curr_address) >+{ >+ uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE; >+ >+ /* When all EEPROM memory used jump back to 0 address */ >+ if (next_address > EEPROM_SIZE_BYTES) { >+ DRM_INFO("Reached end of EEPROM memory, jumping to 0 " >+ "and overriding old record"); >+ return EEPROM_RECORD_START; >+ } >+ >+ /* >+ * To check if we overflow page boundary compare next address with >+ * current and see if bits 17/8 of the EEPROM address will change >+ * If they do start from the next 256b page >+ * >+ * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2 >+ */ >+ if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) { >+ DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx", >+ (next_address & EEPROM_ADDR_MSB_MASK)); >+ >+ return (next_address & EEPROM_ADDR_MSB_MASK); >+ } >+ >+ return curr_address; >+} >+ >+ >+static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control) >+{ >+ int i; >+ uint32_t tbl_sum = 0; >+ >+ /* Header checksum, skip checksum field in the calculation */ >+ for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++) >+ tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i); >+ >+ return tbl_sum; >+} >+ >+static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records, >+ int num) >+{ >+ int i, j; >+ uint32_t tbl_sum = 0; >+ >+ /* Records checksum */ >+ for (i = 0; i < num; i++) { >+ struct eeprom_table_record *record = &records[i]; >+ >+ for (j = 0; j < sizeof(*record); j++) { >+ tbl_sum += *(((unsigned char *)record) + j); >+ } >+ } >+ >+ return tbl_sum; >+} >+ >+static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control, >+ struct eeprom_table_record *records, int num) >+{ >+ return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num); >+} >+ >+/* Checksum = 256 -((sum of all table entries) mod 256) */ >+static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control, >+ struct eeprom_table_record *records, int num, >+ uint32_t old_hdr_byte_sum) >+{ >+ /* >+ * This will update the table sum with new records. >+ * >+ * TODO: What happens when the EEPROM table is to be wrapped around >+ * and old records from start will get overridden. >+ */ >+ >+ /* need to recalculate updated header byte sum */ >+ control->tbl_byte_sum -= old_hdr_byte_sum; >+ control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num); >+ >+ control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256); >+} >+ >+/* table sum mod 256 + checksum must equals 256 */ >+static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control, >+ struct eeprom_table_record *records, int num) >+{ >+ control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num); >+ >+ if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) { >+ DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum); >+ return false; >+ } >+ >+ return true; >+} >+ >+int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control, >+ struct eeprom_table_record *records, >+ bool write, >+ int num) >+{ >+ int i, ret = 0; >+ struct i2c_msg *msgs; >+ unsigned char *buffs; >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ >+ if (adev->asic_type != CHIP_VEGA20) >+ return 0; >+ >+ buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE, >+ GFP_KERNEL); >+ if (!buffs) >+ return -ENOMEM; >+ >+ mutex_lock(&control->tbl_mutex); >+ >+ msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL); >+ if (!msgs) { >+ ret = -ENOMEM; >+ goto free_buff; >+ } >+ >+ /* In case of overflow just start from beginning to not lose newest records */ >+ if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES)) >+ control->next_addr = EEPROM_RECORD_START; >+ >+ >+ /* >+ * TODO Currently makes EEPROM writes for each record, this creates >+ * internal fragmentation. Optimized the code to do full page write of >+ * 256b >+ */ >+ for (i = 0; i < num; i++) { >+ unsigned char *buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)]; >+ struct eeprom_table_record *record = &records[i]; >+ struct i2c_msg *msg = &msgs[i]; >+ >+ control->next_addr = __correct_eeprom_dest_address(control->next_addr); >+ >+ /* >+ * Update bits 16,17 of EEPROM address in I2C address by setting them >+ * to bits 1,2 of Device address byte >+ */ >+ msg->addr = EEPROM_I2C_TARGET_ADDR | >+ ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15); >+ msg->flags = write ? 0 : I2C_M_RD; >+ msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE; >+ msg->buf = buff; >+ >+ /* Insert the EEPROM dest addess, bits 0-15 */ >+ buff[0] = ((control->next_addr >> 8) & 0xff); >+ buff[1] = (control->next_addr & 0xff); >+ >+ /* EEPROM table content is stored in LE format */ >+ if (write) >+ __encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE); >+ >+ /* >+ * The destination EEPROM address might need to be corrected to account >+ * for page or entire memory wrapping >+ */ >+ control->next_addr += EEPROM_TABLE_RECORD_SIZE; >+ } >+ >+ ret = i2c_transfer(&control->eeprom_accessor, msgs, num); >+ if (ret < 1) { >+ DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret); >+ >+ /* TODO Restore prev next EEPROM address ? */ >+ goto free_msgs; >+ } >+ >+ >+ if (!write) { >+ for (i = 0; i < num; i++) { >+ unsigned char *buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)]; >+ struct eeprom_table_record *record = &records[i]; >+ >+ __decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE); >+ } >+ } >+ >+ if (write) { >+ uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control); >+ >+ /* >+ * Update table header with size and CRC and account for table >+ * wrap around where the assumption is that we treat it as empty >+ * table >+ * >+ * TODO - Check the assumption is correct >+ */ >+ control->num_recs += num; >+ control->num_recs %= EEPROM_MAX_RECORD_NUM; >+ control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num; >+ if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES) >+ control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE + >+ control->num_recs * EEPROM_TABLE_RECORD_SIZE; >+ >+ __update_tbl_checksum(control, records, num, old_hdr_byte_sum); >+ >+ __update_table_header(control, buffs); >+ } else if (!__validate_tbl_checksum(control, records, num)) { >+ DRM_WARN("EEPROM Table checksum mismatch!"); >+ /* TODO Uncomment when EEPROM read/write is relliable */ >+ /* ret = -EIO; */ >+ } >+ >+free_msgs: >+ kfree(msgs); >+ >+free_buff: >+ kfree(buffs); >+ >+ mutex_unlock(&control->tbl_mutex); >+ >+ return ret == num ? 0 : -EIO; >+} >+ >+/* Used for testing if bugs encountered */ >+#if 0 >+void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control) >+{ >+ int i; >+ struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL); >+ >+ if (!recs) >+ return; >+ >+ for (i = 0; i < 1 ; i++) { >+ recs[i].address = 0xdeadbeef; >+ recs[i].retired_page = i; >+ } >+ >+ if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) { >+ >+ memset(recs, 0, sizeof(*recs) * 1); >+ >+ control->next_addr = EEPROM_RECORD_START; >+ >+ if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) { >+ for (i = 0; i < 1; i++) >+ DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu", >+ recs[i].address, recs[i].retired_page); >+ } else >+ DRM_ERROR("Failed in reading from table"); >+ >+ } else >+ DRM_ERROR("Failed in writing to table"); >+} >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h 2019-08-31 15:01:11.843736167 -0500 >@@ -0,0 +1,90 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+ >+#ifndef _AMDGPU_RAS_EEPROM_H >+#define _AMDGPU_RAS_EEPROM_H >+ >+#include <linux/i2c.h> >+ >+struct amdgpu_device; >+ >+enum amdgpu_ras_eeprom_err_type{ >+ AMDGPU_RAS_EEPROM_ERR_PLACE_HOLDER, >+ AMDGPU_RAS_EEPROM_ERR_RECOVERABLE, >+ AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE >+}; >+ >+struct amdgpu_ras_eeprom_table_header { >+ uint32_t header; >+ uint32_t version; >+ uint32_t first_rec_offset; >+ uint32_t tbl_size; >+ uint32_t checksum; >+}__attribute__((__packed__)); >+ >+struct amdgpu_ras_eeprom_control { >+ struct amdgpu_ras_eeprom_table_header tbl_hdr; >+ struct i2c_adapter eeprom_accessor; >+ uint32_t next_addr; >+ unsigned int num_recs; >+ struct mutex tbl_mutex; >+ bool bus_locked; >+ uint32_t tbl_byte_sum; >+}; >+ >+/* >+ * Represents single table record. Packed to be easily serialized into byte >+ * stream. >+ */ >+struct eeprom_table_record { >+ >+ union { >+ uint64_t address; >+ uint64_t offset; >+ }; >+ >+ uint64_t retired_page; >+ uint64_t ts; >+ >+ enum amdgpu_ras_eeprom_err_type err_type; >+ >+ union { >+ unsigned char bank; >+ unsigned char cu; >+ }; >+ >+ unsigned char mem_channel; >+ unsigned char mcumc_id; >+}__attribute__((__packed__)); >+ >+int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control); >+void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control); >+ >+int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control, >+ struct eeprom_table_record *records, >+ bool write, >+ int num); >+ >+void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control); >+ >+#endif // _AMDGPU_RAS_EEPROM_H >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 2019-08-31 15:01:11.843736167 -0500 >@@ -29,6 +29,7 @@ > #include "amdgpu.h" > #include "amdgpu_psp.h" > #include "ta_ras_if.h" >+#include "amdgpu_ras_eeprom.h" > > enum amdgpu_ras_block { > AMDGPU_RAS_BLOCK__UMC = 0, >@@ -52,6 +53,236 @@ > #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST > #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) > >+enum amdgpu_ras_gfx_subblock { >+ /* CPC */ >+ AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, >+ AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = >+ AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, >+ AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, >+ AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, >+ AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, >+ AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, >+ AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, >+ AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, >+ AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = >+ AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, >+ /* CPF */ >+ AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = >+ AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, >+ AMDGPU_RAS_BLOCK__GFX_CPF_TAG, >+ AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, >+ /* CPG */ >+ AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = >+ AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, >+ AMDGPU_RAS_BLOCK__GFX_CPG_TAG, >+ AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, >+ /* GDS */ >+ AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, >+ AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, >+ AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, >+ AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, >+ AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = >+ AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, >+ /* SPI */ >+ AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, >+ /* SQ */ >+ AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, >+ AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, >+ AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, >+ AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, >+ /* SQC (3 ranges) */ >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, >+ /* SQC range 0 */ >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, >+ /* SQC range 1 */ >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, >+ /* SQC range 2 */ >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = >+ AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = >+ AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, >+ /* TA */ >+ AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = >+ AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, >+ AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, >+ AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, >+ AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, >+ AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, >+ /* TCA */ >+ AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = >+ AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = >+ AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, >+ /* TCC (5 sub-ranges) */ >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, >+ /* TCC range 0 */ >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, >+ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, >+ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, >+ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, >+ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, >+ AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, >+ AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = >+ AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, >+ /* TCC range 1 */ >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = >+ AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, >+ /* TCC range 2 */ >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, >+ AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, >+ AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, >+ AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, >+ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = >+ AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, >+ /* TCC range 3 */ >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = >+ AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, >+ /* TCC range 4 */ >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, >+ AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = >+ AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = >+ AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, >+ /* TCI */ >+ AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, >+ /* TCP */ >+ AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = >+ AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, >+ AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, >+ AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, >+ AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, >+ AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = >+ AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, >+ /* TD */ >+ AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = >+ AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, >+ AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, >+ AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, >+ /* EA (3 sub-ranges) */ >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, >+ /* EA range 0 */ >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, >+ AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, >+ AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = >+ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, >+ /* EA range 1 */ >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, >+ AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, >+ AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = >+ AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, >+ /* EA range 2 */ >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, >+ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, >+ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = >+ AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = >+ AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, >+ /* UTC VM L2 bank */ >+ AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, >+ /* UTC VM walker */ >+ AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, >+ /* UTC ATC L2 2MB cache */ >+ AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, >+ /* UTC ATC L2 4KB cache */ >+ AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, >+ AMDGPU_RAS_BLOCK__GFX_MAX >+}; >+ > enum amdgpu_ras_error_type { > AMDGPU_RAS_ERROR__NONE = 0, > AMDGPU_RAS_ERROR__PARITY = 1, >@@ -76,9 +307,6 @@ > char name[32]; > }; > >-typedef int (*ras_ih_cb)(struct amdgpu_device *adev, >- struct amdgpu_iv_entry *entry); >- > struct amdgpu_ras { > /* ras infrastructure */ > /* for ras itself. */ >@@ -106,10 +334,85 @@ > struct mutex recovery_lock; > > uint32_t flags; >+ >+ struct amdgpu_ras_eeprom_control eeprom_control; > }; > >-/* interfaces for IP */ >+struct ras_fs_data { >+ char sysfs_name[32]; >+ char debugfs_name[32]; >+}; >+ >+struct ras_err_data { >+ unsigned long ue_count; >+ unsigned long ce_count; >+ unsigned long err_addr_cnt; >+ uint64_t *err_addr; >+}; > >+struct ras_err_handler_data { >+ /* point to bad pages array */ >+ struct { >+ unsigned long bp; >+ struct amdgpu_bo *bo; >+ } *bps; >+ /* the count of entries */ >+ int count; >+ /* the space can place new entries */ >+ int space_left; >+ /* last reserved entry's index + 1 */ >+ int last_reserved; >+}; >+ >+typedef int (*ras_ih_cb)(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, >+ struct amdgpu_iv_entry *entry); >+ >+struct ras_ih_data { >+ /* interrupt bottom half */ >+ struct work_struct ih_work; >+ int inuse; >+ /* IP callback */ >+ ras_ih_cb cb; >+ /* full of entries */ >+ unsigned char *ring; >+ unsigned int ring_size; >+ unsigned int element_size; >+ unsigned int aligned_element_size; >+ unsigned int rptr; >+ unsigned int wptr; >+}; >+ >+struct ras_manager { >+ struct ras_common_if head; >+ /* reference count */ >+ int use; >+ /* ras block link */ >+ struct list_head node; >+ /* the device */ >+ struct amdgpu_device *adev; >+ /* debugfs */ >+ struct dentry *ent; >+ /* sysfs */ >+ struct device_attribute sysfs_attr; >+ int attr_inuse; >+ >+ /* fs node name */ >+ struct ras_fs_data fs_data; >+ >+ /* IH data */ >+ struct ras_ih_data ih_data; >+ >+ struct ras_err_data err_data; >+}; >+ >+struct ras_badpage { >+ unsigned int bp; >+ unsigned int size; >+ unsigned int flags; >+}; >+ >+/* interfaces for IP */ > struct ras_fs_if { > struct ras_common_if head; > char sysfs_name[32]; >@@ -184,7 +487,7 @@ > void amdgpu_ras_resume(struct amdgpu_device *adev); > void amdgpu_ras_suspend(struct amdgpu_device *adev); > >-int amdgpu_ras_query_error_count(struct amdgpu_device *adev, >+unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, > bool is_ce); > > /* error handling functions */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 2019-08-31 15:01:11.843736167 -0500 >@@ -29,7 +29,7 @@ > #include <drm/drm_print.h> > > /* max number of rings */ >-#define AMDGPU_MAX_RINGS 24 >+#define AMDGPU_MAX_RINGS 28 > #define AMDGPU_MAX_GFX_RINGS 2 > #define AMDGPU_MAX_COMPUTE_RINGS 8 > #define AMDGPU_MAX_VCE_RINGS 3 >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 2019-08-31 15:01:11.843736167 -0500 >@@ -25,11 +25,17 @@ > #define __AMDGPU_SDMA_H__ > > /* max number of IP instances */ >-#define AMDGPU_MAX_SDMA_INSTANCES 2 >+#define AMDGPU_MAX_SDMA_INSTANCES 8 > > enum amdgpu_sdma_irq { > AMDGPU_SDMA_IRQ_INSTANCE0 = 0, > AMDGPU_SDMA_IRQ_INSTANCE1, >+ AMDGPU_SDMA_IRQ_INSTANCE2, >+ AMDGPU_SDMA_IRQ_INSTANCE3, >+ AMDGPU_SDMA_IRQ_INSTANCE4, >+ AMDGPU_SDMA_IRQ_INSTANCE5, >+ AMDGPU_SDMA_IRQ_INSTANCE6, >+ AMDGPU_SDMA_IRQ_INSTANCE7, > AMDGPU_SDMA_IRQ_LAST > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 2019-08-31 15:01:11.844736167 -0500 >@@ -227,7 +227,7 @@ > > if (amdgpu_ttm_tt_get_usermm(bo->ttm)) > return -EPERM; >- return drm_vma_node_verify_access(&abo->gem_base.vma_node, >+ return drm_vma_node_verify_access(&abo->tbo.base.vma_node, > filp->private_data); > } > >@@ -440,10 +440,26 @@ > > r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, > new_mem->num_pages << PAGE_SHIFT, >- bo->resv, &fence); >+ bo->base.resv, &fence); > if (r) > goto error; > >+ /* clear the space being freed */ >+ if (old_mem->mem_type == TTM_PL_VRAM && >+ (ttm_to_amdgpu_bo(bo)->flags & >+ AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { >+ struct dma_fence *wipe_fence = NULL; >+ >+ r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, >+ NULL, &wipe_fence); >+ if (r) { >+ goto error; >+ } else if (wipe_fence) { >+ dma_fence_put(fence); >+ fence = wipe_fence; >+ } >+ } >+ > /* Always block for VM page tables before committing the new location */ > if (bo->type == ttm_bo_type_kernel) > r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem); >@@ -1478,18 +1494,18 @@ > * cleanly handle page faults. > */ > if (bo->type == ttm_bo_type_kernel && >- !reservation_object_test_signaled_rcu(bo->resv, true)) >+ !reservation_object_test_signaled_rcu(bo->base.resv, true)) > return false; > > /* If bo is a KFD BO, check if the bo belongs to the current process. > * If true, then return false as any KFD process needs all its BOs to > * be resident to run successfully > */ >- flist = reservation_object_get_list(bo->resv); >+ flist = reservation_object_get_list(bo->base.resv); > if (flist) { > for (i = 0; i < flist->shared_count; ++i) { > f = rcu_dereference_protected(flist->shared[i], >- reservation_object_held(bo->resv)); >+ reservation_object_held(bo->base.resv)); > if (amdkfd_fence_check_mm(f, current->mm)) > return false; > } >@@ -1599,6 +1615,7 @@ > .move = &amdgpu_bo_move, > .verify_access = &amdgpu_verify_access, > .move_notify = &amdgpu_bo_move_notify, >+ .release_notify = &amdgpu_bo_release_notify, > .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, > .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, > .io_mem_free = &amdgpu_ttm_io_mem_free, >@@ -1721,6 +1738,7 @@ > uint64_t gtt_size; > int r; > u64 vis_vram_limit; >+ void *stolen_vga_buf; > > mutex_init(&adev->mman.gtt_window_lock); > >@@ -1728,7 +1746,7 @@ > r = ttm_bo_device_init(&adev->mman.bdev, > &amdgpu_bo_driver, > adev->ddev->anon_inode->i_mapping, >- adev->need_dma32); >+ dma_addressing_limited(adev->dev)); > if (r) { > DRM_ERROR("failed initializing buffer object driver(%d).\n", r); > return r; >@@ -1775,7 +1793,7 @@ > r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE, > AMDGPU_GEM_DOMAIN_VRAM, > &adev->stolen_vga_memory, >- NULL, NULL); >+ NULL, &stolen_vga_buf); > if (r) > return r; > DRM_INFO("amdgpu: %uM of VRAM memory ready\n", >@@ -1839,8 +1857,9 @@ > */ > void amdgpu_ttm_late_init(struct amdgpu_device *adev) > { >+ void *stolen_vga_buf; > /* return the VGA stolen memory (if any) back to VRAM */ >- amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); >+ amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); > } > > /** >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 2019-08-31 15:01:11.844736167 -0500 >@@ -38,6 +38,8 @@ > #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 > #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 > >+#define AMDGPU_POISON 0xd0bed0be >+ > struct amdgpu_mman { > struct ttm_bo_device bdev; > bool mem_global_referenced; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 2019-08-31 15:01:11.844736167 -0500 >@@ -83,8 +83,8 @@ > const struct smc_firmware_header_v2_0 *v2_hdr = > container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0); > >- DRM_INFO("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes)); >- DRM_INFO("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes)); >+ DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes)); >+ DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes)); > } else { > DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); > } >@@ -269,6 +269,16 @@ > DRM_DEBUG("kdb_size_bytes: %u\n", > le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes)); > } >+ if (version_minor == 2) { >+ const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = >+ container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); >+ DRM_DEBUG("kdb_header_version: %u\n", >+ le32_to_cpu(psp_hdr_v1_2->kdb_header_version)); >+ DRM_DEBUG("kdb_offset_bytes: %u\n", >+ le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes)); >+ DRM_DEBUG("kdb_size_bytes: %u\n", >+ le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes)); >+ } > } else { > DRM_ERROR("Unknown PSP ucode version: %u.%u\n", > version_major, version_minor); >@@ -350,11 +360,17 @@ > case CHIP_RAVEN: > case CHIP_VEGA12: > case CHIP_VEGA20: >+ case CHIP_RENOIR: > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > if (!load_type) > return AMDGPU_FW_LOAD_DIRECT; > else > return AMDGPU_FW_LOAD_PSP; >+ case CHIP_ARCTURUS: >+ return AMDGPU_FW_LOAD_DIRECT; >+ > default: > DRM_ERROR("Unknown firmware load type\n"); > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h 2019-08-31 15:01:11.844736167 -0500 >@@ -90,6 +90,15 @@ > uint32_t kdb_size_bytes; > }; > >+/* version_major=1, version_minor=2 */ >+struct psp_firmware_header_v1_2 { >+ struct psp_firmware_header_v1_0 v1_0; >+ uint32_t reserve[3]; >+ uint32_t kdb_header_version; >+ uint32_t kdb_offset_bytes; >+ uint32_t kdb_size_bytes; >+}; >+ > /* version_major=1, version_minor=0 */ > struct ta_firmware_header_v1_0 { > struct common_firmware_header header; >@@ -262,6 +271,12 @@ > enum AMDGPU_UCODE_ID { > AMDGPU_UCODE_ID_SDMA0 = 0, > AMDGPU_UCODE_ID_SDMA1, >+ AMDGPU_UCODE_ID_SDMA2, >+ AMDGPU_UCODE_ID_SDMA3, >+ AMDGPU_UCODE_ID_SDMA4, >+ AMDGPU_UCODE_ID_SDMA5, >+ AMDGPU_UCODE_ID_SDMA6, >+ AMDGPU_UCODE_ID_SDMA7, > AMDGPU_UCODE_ID_CP_CE, > AMDGPU_UCODE_ID_CP_PFP, > AMDGPU_UCODE_ID_CP_ME, >@@ -281,6 +296,7 @@ > AMDGPU_UCODE_ID_UVD1, > AMDGPU_UCODE_ID_VCE, > AMDGPU_UCODE_ID_VCN, >+ AMDGPU_UCODE_ID_VCN1, > AMDGPU_UCODE_ID_DMCU_ERAM, > AMDGPU_UCODE_ID_DMCU_INTV, > AMDGPU_UCODE_ID_VCN0_RAM, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 2019-08-31 15:01:11.844736167 -0500 >@@ -0,0 +1,82 @@ >+/* >+ * Copyright (C) 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included >+ * in all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN >+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN >+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. >+ */ >+#ifndef __AMDGPU_UMC_H__ >+#define __AMDGPU_UMC_H__ >+ >+/* implement 64 bits REG operations via 32 bits interface */ >+#define RREG64_UMC(reg) (RREG32(reg) | \ >+ ((uint64_t)RREG32((reg) + 1) << 32)) >+#define WREG64_UMC(reg, v) \ >+ do { \ >+ WREG32((reg), lower_32_bits(v)); \ >+ WREG32((reg) + 1, upper_32_bits(v)); \ >+ } while (0) >+ >+/* >+ * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data, >+ * uint32_t umc_reg_offset, uint32_t channel_index) >+ */ >+#define amdgpu_umc_for_each_channel(func) \ >+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; \ >+ uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \ >+ for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) { \ >+ /* enable the index mode to query eror count per channel */ \ >+ adev->umc.funcs->enable_umc_index_mode(adev, umc_inst); \ >+ for (channel_inst = 0; \ >+ channel_inst < adev->umc.channel_inst_num; \ >+ channel_inst++) { \ >+ /* calc the register offset according to channel instance */ \ >+ umc_reg_offset = adev->umc.channel_offs * channel_inst; \ >+ /* get channel index of interleaved memory */ \ >+ channel_index = adev->umc.channel_idx_tbl[ \ >+ umc_inst * adev->umc.channel_inst_num + channel_inst]; \ >+ (func)(adev, err_data, umc_reg_offset, channel_index); \ >+ } \ >+ } \ >+ adev->umc.funcs->disable_umc_index_mode(adev); >+ >+struct amdgpu_umc_funcs { >+ void (*ras_init)(struct amdgpu_device *adev); >+ void (*query_ras_error_count)(struct amdgpu_device *adev, >+ void *ras_error_status); >+ void (*query_ras_error_address)(struct amdgpu_device *adev, >+ void *ras_error_status); >+ void (*enable_umc_index_mode)(struct amdgpu_device *adev, >+ uint32_t umc_instance); >+ void (*disable_umc_index_mode)(struct amdgpu_device *adev); >+}; >+ >+struct amdgpu_umc { >+ /* max error count in one ras query call */ >+ uint32_t max_ras_err_cnt_per_query; >+ /* number of umc channel instance with memory map register access */ >+ uint32_t channel_inst_num; >+ /* number of umc instance with memory map register access */ >+ uint32_t umc_inst_num; >+ /* UMC regiser per channel offset */ >+ uint32_t channel_offs; >+ /* channel index table of interleaved memory */ >+ const uint32_t *channel_idx_tbl; >+ >+ const struct amdgpu_umc_funcs *funcs; >+}; >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 2019-08-31 15:01:11.844736167 -0500 >@@ -1073,7 +1073,7 @@ > ib->length_dw = 16; > > if (direct) { >- r = reservation_object_wait_timeout_rcu(bo->tbo.resv, >+ r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv, > true, false, > msecs_to_jiffies(10)); > if (r == 0) >@@ -1085,7 +1085,7 @@ > if (r) > goto err_free; > } else { >- r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, >+ r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, > AMDGPU_FENCE_OWNER_UNDEFINED, false); > if (r) > goto err_free; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 2019-08-31 15:01:11.844736167 -0500 >@@ -46,12 +46,20 @@ > #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" > #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" > #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" >+#define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" >+#define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" > #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" >+#define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" >+#define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" > > MODULE_FIRMWARE(FIRMWARE_RAVEN); > MODULE_FIRMWARE(FIRMWARE_PICASSO); > MODULE_FIRMWARE(FIRMWARE_RAVEN2); >+MODULE_FIRMWARE(FIRMWARE_ARCTURUS); >+MODULE_FIRMWARE(FIRMWARE_RENOIR); > MODULE_FIRMWARE(FIRMWARE_NAVI10); >+MODULE_FIRMWARE(FIRMWARE_NAVI14); >+MODULE_FIRMWARE(FIRMWARE_NAVI12); > > static void amdgpu_vcn_idle_work_handler(struct work_struct *work); > >@@ -61,7 +69,7 @@ > const char *fw_name; > const struct common_firmware_header *hdr; > unsigned char fw_check; >- int r; >+ int i, r; > > INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); > >@@ -74,12 +82,33 @@ > else > fw_name = FIRMWARE_RAVEN; > break; >+ case CHIP_ARCTURUS: >+ fw_name = FIRMWARE_ARCTURUS; >+ break; >+ case CHIP_RENOIR: >+ fw_name = FIRMWARE_RENOIR; >+ if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && >+ (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) >+ adev->vcn.indirect_sram = true; >+ break; > case CHIP_NAVI10: > fw_name = FIRMWARE_NAVI10; > if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && > (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) > adev->vcn.indirect_sram = true; > break; >+ case CHIP_NAVI14: >+ fw_name = FIRMWARE_NAVI14; >+ if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && >+ (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) >+ adev->vcn.indirect_sram = true; >+ break; >+ case CHIP_NAVI12: >+ fw_name = FIRMWARE_NAVI12; >+ if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && >+ (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) >+ adev->vcn.indirect_sram = true; >+ break; > default: > return -EINVAL; > } >@@ -133,12 +162,18 @@ > bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; > if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) > bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); >- r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, >- AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo, >- &adev->vcn.gpu_addr, &adev->vcn.cpu_addr); >- if (r) { >- dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); >- return r; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ >+ r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, >+ AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, >+ &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); >+ if (r) { >+ dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); >+ return r; >+ } > } > > if (adev->vcn.indirect_sram) { >@@ -156,26 +191,30 @@ > > int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) > { >- int i; >- >- kvfree(adev->vcn.saved_bo); >+ int i, j; > > if (adev->vcn.indirect_sram) { > amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo, >- &adev->vcn.dpg_sram_gpu_addr, >- (void **)&adev->vcn.dpg_sram_cpu_addr); >+ &adev->vcn.dpg_sram_gpu_addr, >+ (void **)&adev->vcn.dpg_sram_cpu_addr); > } > >- amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo, >- &adev->vcn.gpu_addr, >- (void **)&adev->vcn.cpu_addr); >+ for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ kvfree(adev->vcn.inst[j].saved_bo); > >- amdgpu_ring_fini(&adev->vcn.ring_dec); >+ amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, >+ &adev->vcn.inst[j].gpu_addr, >+ (void **)&adev->vcn.inst[j].cpu_addr); > >- for (i = 0; i < adev->vcn.num_enc_rings; ++i) >- amdgpu_ring_fini(&adev->vcn.ring_enc[i]); >+ amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); > >- amdgpu_ring_fini(&adev->vcn.ring_jpeg); >+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) >+ amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); >+ >+ amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg); >+ } > > release_firmware(adev->vcn.fw); > >@@ -186,21 +225,25 @@ > { > unsigned size; > void *ptr; >+ int i; > > cancel_delayed_work_sync(&adev->vcn.idle_work); > >- if (adev->vcn.vcpu_bo == NULL) >- return 0; >- >- size = amdgpu_bo_size(adev->vcn.vcpu_bo); >- ptr = adev->vcn.cpu_addr; >- >- adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL); >- if (!adev->vcn.saved_bo) >- return -ENOMEM; >- >- memcpy_fromio(adev->vcn.saved_bo, ptr, size); >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ if (adev->vcn.inst[i].vcpu_bo == NULL) >+ return 0; >+ >+ size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); >+ ptr = adev->vcn.inst[i].cpu_addr; >+ >+ adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); >+ if (!adev->vcn.inst[i].saved_bo) >+ return -ENOMEM; > >+ memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); >+ } > return 0; > } > >@@ -208,32 +251,36 @@ > { > unsigned size; > void *ptr; >+ int i; > >- if (adev->vcn.vcpu_bo == NULL) >- return -EINVAL; >- >- size = amdgpu_bo_size(adev->vcn.vcpu_bo); >- ptr = adev->vcn.cpu_addr; >- >- if (adev->vcn.saved_bo != NULL) { >- memcpy_toio(ptr, adev->vcn.saved_bo, size); >- kvfree(adev->vcn.saved_bo); >- adev->vcn.saved_bo = NULL; >- } else { >- const struct common_firmware_header *hdr; >- unsigned offset; >- >- hdr = (const struct common_firmware_header *)adev->vcn.fw->data; >- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { >- offset = le32_to_cpu(hdr->ucode_array_offset_bytes); >- memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset, >- le32_to_cpu(hdr->ucode_size_bytes)); >- size -= le32_to_cpu(hdr->ucode_size_bytes); >- ptr += le32_to_cpu(hdr->ucode_size_bytes); >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ if (adev->vcn.inst[i].vcpu_bo == NULL) >+ return -EINVAL; >+ >+ size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); >+ ptr = adev->vcn.inst[i].cpu_addr; >+ >+ if (adev->vcn.inst[i].saved_bo != NULL) { >+ memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); >+ kvfree(adev->vcn.inst[i].saved_bo); >+ adev->vcn.inst[i].saved_bo = NULL; >+ } else { >+ const struct common_firmware_header *hdr; >+ unsigned offset; >+ >+ hdr = (const struct common_firmware_header *)adev->vcn.fw->data; >+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { >+ offset = le32_to_cpu(hdr->ucode_array_offset_bytes); >+ memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, >+ le32_to_cpu(hdr->ucode_size_bytes)); >+ size -= le32_to_cpu(hdr->ucode_size_bytes); >+ ptr += le32_to_cpu(hdr->ucode_size_bytes); >+ } >+ memset_io(ptr, 0, size); > } >- memset_io(ptr, 0, size); > } >- > return 0; > } > >@@ -241,35 +288,40 @@ > { > struct amdgpu_device *adev = > container_of(work, struct amdgpu_device, vcn.idle_work.work); >- unsigned int fences = 0; >- unsigned int i; >+ unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; >+ unsigned int i, j; > >- for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >- fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]); >- } >+ for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >+ fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); >+ } > >- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { >- struct dpg_pause_state new_state; >+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { >+ struct dpg_pause_state new_state; > >- if (fences) >- new_state.fw_based = VCN_DPG_STATE__PAUSE; >- else >- new_state.fw_based = VCN_DPG_STATE__UNPAUSE; >+ if (fence[j]) >+ new_state.fw_based = VCN_DPG_STATE__PAUSE; >+ else >+ new_state.fw_based = VCN_DPG_STATE__UNPAUSE; >+ >+ if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg)) >+ new_state.jpeg = VCN_DPG_STATE__PAUSE; >+ else >+ new_state.jpeg = VCN_DPG_STATE__UNPAUSE; > >- if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg)) >- new_state.jpeg = VCN_DPG_STATE__PAUSE; >- else >- new_state.jpeg = VCN_DPG_STATE__UNPAUSE; >+ adev->vcn.pause_dpg_mode(adev, &new_state); >+ } > >- adev->vcn.pause_dpg_mode(adev, &new_state); >+ fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg); >+ fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); >+ fences += fence[j]; > } > >- fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg); >- fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec); >- > if (fences == 0) { > amdgpu_gfx_off_ctrl(adev, true); >- if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled) >+ if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled) > amdgpu_dpm_enable_uvd(adev, false); > else > amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, >@@ -286,7 +338,7 @@ > > if (set_clocks) { > amdgpu_gfx_off_ctrl(adev, false); >- if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled) >+ if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled) > amdgpu_dpm_enable_uvd(adev, true); > else > amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, >@@ -299,14 +351,14 @@ > unsigned int i; > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >- fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]); >+ fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); > } > if (fences) > new_state.fw_based = VCN_DPG_STATE__PAUSE; > else > new_state.fw_based = VCN_DPG_STATE__UNPAUSE; > >- if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg)) >+ if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg)) > new_state.jpeg = VCN_DPG_STATE__PAUSE; > else > new_state.jpeg = VCN_DPG_STATE__UNPAUSE; >@@ -332,7 +384,7 @@ > unsigned i; > int r; > >- WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD); >+ WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); > r = amdgpu_ring_alloc(ring, 3); > if (r) > return r; >@@ -340,7 +392,7 @@ > amdgpu_ring_write(ring, 0xDEADBEEF); > amdgpu_ring_commit(ring); > for (i = 0; i < adev->usec_timeout; i++) { >- tmp = RREG32(adev->vcn.external.scratch9); >+ tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); > if (tmp == 0xDEADBEEF) > break; > udelay(1); >@@ -651,7 +703,7 @@ > unsigned i; > int r; > >- WREG32(adev->vcn.external.jpeg_pitch, 0xCAFEDEAD); >+ WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD); > r = amdgpu_ring_alloc(ring, 3); > if (r) > return r; >@@ -661,7 +713,7 @@ > amdgpu_ring_commit(ring); > > for (i = 0; i < adev->usec_timeout; i++) { >- tmp = RREG32(adev->vcn.external.jpeg_pitch); >+ tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); > if (tmp == 0xDEADBEEF) > break; > udelay(1); >@@ -735,7 +787,7 @@ > } > > for (i = 0; i < adev->usec_timeout; i++) { >- tmp = RREG32(adev->vcn.external.jpeg_pitch); >+ tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); > if (tmp == 0xDEADBEEF) > break; > udelay(1); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 2019-08-31 15:09:42.578781293 -0500 >@@ -30,6 +30,11 @@ > #define AMDGPU_VCN_FIRMWARE_OFFSET 256 > #define AMDGPU_VCN_MAX_ENC_RINGS 3 > >+#define AMDGPU_MAX_VCN_INSTANCES 2 >+ >+#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0) >+#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1) >+ > #define VCN_DEC_KMD_CMD 0x80000000 > #define VCN_DEC_CMD_FENCE 0x00000000 > #define VCN_DEC_CMD_TRAP 0x00000001 >@@ -146,34 +151,49 @@ > unsigned data1; > unsigned cmd; > unsigned nop; >+ unsigned context_id; >+ unsigned ib_vmid; >+ unsigned ib_bar_low; >+ unsigned ib_bar_high; >+ unsigned ib_size; >+ unsigned gp_scratch8; > unsigned scratch9; > unsigned jpeg_pitch; > }; > >-struct amdgpu_vcn { >+struct amdgpu_vcn_inst { > struct amdgpu_bo *vcpu_bo; > void *cpu_addr; > uint64_t gpu_addr; >- unsigned fw_version; > void *saved_bo; >- struct delayed_work idle_work; >- const struct firmware *fw; /* VCN firmware */ > struct amdgpu_ring ring_dec; > struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; > struct amdgpu_ring ring_jpeg; > struct amdgpu_irq_src irq; >+ struct amdgpu_vcn_reg external; >+}; >+ >+struct amdgpu_vcn { >+ unsigned fw_version; >+ struct delayed_work idle_work; >+ const struct firmware *fw; /* VCN firmware */ > unsigned num_enc_rings; > enum amd_powergating_state cur_state; > struct dpg_pause_state pause_state; >- struct amdgpu_vcn_reg internal, external; >- int (*pause_dpg_mode)(struct amdgpu_device *adev, >- struct dpg_pause_state *new_state); > > bool indirect_sram; > struct amdgpu_bo *dpg_sram_bo; > void *dpg_sram_cpu_addr; > uint64_t dpg_sram_gpu_addr; > uint32_t *dpg_sram_curr_addr; >+ >+ uint8_t num_vcn_inst; >+ struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES]; >+ struct amdgpu_vcn_reg internal; >+ >+ unsigned harvest_config; >+ int (*pause_dpg_mode)(struct amdgpu_device *adev, >+ struct dpg_pause_state *new_state); > }; > > int amdgpu_vcn_sw_init(struct amdgpu_device *adev); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 2019-08-31 15:01:11.844736167 -0500 >@@ -430,48 +430,3 @@ > > return clk; > } >- >-void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev) >-{ >- struct amdgpu_virt *virt = &adev->virt; >- >- if (virt->ops && virt->ops->init_reg_access_mode) >- virt->ops->init_reg_access_mode(adev); >-} >- >-bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev) >-{ >- bool ret = false; >- struct amdgpu_virt *virt = &adev->virt; >- >- if (amdgpu_sriov_vf(adev) >- && (virt->reg_access_mode & AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH)) >- ret = true; >- >- return ret; >-} >- >-bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev) >-{ >- bool ret = false; >- struct amdgpu_virt *virt = &adev->virt; >- >- if (amdgpu_sriov_vf(adev) >- && (virt->reg_access_mode & AMDGPU_VIRT_REG_ACCESS_RLC) >- && !(amdgpu_sriov_runtime(adev))) >- ret = true; >- >- return ret; >-} >- >-bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev) >-{ >- bool ret = false; >- struct amdgpu_virt *virt = &adev->virt; >- >- if (amdgpu_sriov_vf(adev) >- && (virt->reg_access_mode & AMDGPU_VIRT_REG_SKIP_SEETING)) >- ret = true; >- >- return ret; >-} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 2019-08-31 15:01:11.844736167 -0500 >@@ -48,12 +48,6 @@ > uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; > }; > >-/* According to the fw feature, some new reg access modes are supported */ >-#define AMDGPU_VIRT_REG_ACCESS_LEGACY (1 << 0) /* directly mmio */ >-#define AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH (1 << 1) /* by PSP */ >-#define AMDGPU_VIRT_REG_ACCESS_RLC (1 << 2) /* by RLC */ >-#define AMDGPU_VIRT_REG_SKIP_SEETING (1 << 3) /* Skip setting reg */ >- > /** > * struct amdgpu_virt_ops - amdgpu device virt operations > */ >@@ -65,7 +59,6 @@ > void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); > int (*get_pp_clk)(struct amdgpu_device *adev, u32 type, char *buf); > int (*force_dpm_level)(struct amdgpu_device *adev, u32 level); >- void (*init_reg_access_mode)(struct amdgpu_device *adev); > }; > > /* >@@ -315,10 +308,4 @@ > void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); > uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest); > uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest); >- >-void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev); >-bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev); >-bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev); >-bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev); >- > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 2019-08-31 15:01:11.845736167 -0500 >@@ -302,7 +302,7 @@ > base->next = bo->vm_bo; > bo->vm_bo = base; > >- if (bo->tbo.resv != vm->root.base.bo->tbo.resv) >+ if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) > return; > > vm->bulk_moveable = false; >@@ -583,7 +583,7 @@ > for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) { > struct amdgpu_vm *vm = bo_base->vm; > >- if (abo->tbo.resv == vm->root.base.bo->tbo.resv) >+ if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) > vm->bulk_moveable = false; > } > >@@ -834,7 +834,7 @@ > bp->flags |= AMDGPU_GEM_CREATE_SHADOW; > bp->type = ttm_bo_type_kernel; > if (vm->root.base.bo) >- bp->resv = vm->root.base.bo->tbo.resv; >+ bp->resv = vm->root.base.bo->tbo.base.resv; > } > > /** >@@ -1574,7 +1574,7 @@ > flags &= ~AMDGPU_PTE_EXECUTABLE; > flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; > >- if (adev->asic_type == CHIP_NAVI10) { >+ if (adev->asic_type >= CHIP_NAVI10) { > flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; > flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); > } else { >@@ -1702,7 +1702,7 @@ > ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm); > pages_addr = ttm->dma_address; > } >- exclusive = reservation_object_get_excl(bo->tbo.resv); >+ exclusive = reservation_object_get_excl(bo->tbo.base.resv); > } > > if (bo) { >@@ -1712,7 +1712,7 @@ > flags = 0x0; > } > >- if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) >+ if (clear || (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)) > last_update = &vm->last_update; > else > last_update = &bo_va->last_pt_update; >@@ -1743,7 +1743,7 @@ > * the evicted list so that it gets validated again on the > * next command submission. > */ >- if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { >+ if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { > uint32_t mem_type = bo->tbo.mem.mem_type; > > if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type))) >@@ -1879,7 +1879,7 @@ > */ > static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) > { >- struct reservation_object *resv = vm->root.base.bo->tbo.resv; >+ struct reservation_object *resv = vm->root.base.bo->tbo.base.resv; > struct dma_fence *excl, **shared; > unsigned i, shared_count; > int r; >@@ -1993,7 +1993,7 @@ > while (!list_empty(&vm->invalidated)) { > bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, > base.vm_status); >- resv = bo_va->base.bo->tbo.resv; >+ resv = bo_va->base.bo->tbo.base.resv; > spin_unlock(&vm->invalidated_lock); > > /* Try to reserve the BO to avoid clearing its ptes */ >@@ -2084,7 +2084,7 @@ > if (mapping->flags & AMDGPU_PTE_PRT) > amdgpu_vm_prt_get(adev); > >- if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv && >+ if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv && > !bo_va->base.moved) { > list_move(&bo_va->base.vm_status, &vm->moved); > } >@@ -2416,7 +2416,8 @@ > struct amdgpu_bo *bo; > > bo = mapping->bo_va->base.bo; >- if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket) >+ if (reservation_object_locking_ctx(bo->tbo.base.resv) != >+ ticket) > continue; > } > >@@ -2443,7 +2444,7 @@ > struct amdgpu_vm_bo_base **base; > > if (bo) { >- if (bo->tbo.resv == vm->root.base.bo->tbo.resv) >+ if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) > vm->bulk_moveable = false; > > for (base = &bo_va->base.bo->vm_bo; *base; >@@ -2507,7 +2508,7 @@ > for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { > struct amdgpu_vm *vm = bo_base->vm; > >- if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { >+ if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { > amdgpu_vm_bo_evicted(bo_base); > continue; > } >@@ -2518,7 +2519,7 @@ > > if (bo->tbo.type == ttm_bo_type_kernel) > amdgpu_vm_bo_relocated(bo_base); >- else if (bo->tbo.resv == vm->root.base.bo->tbo.resv) >+ else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) > amdgpu_vm_bo_moved(bo_base); > else > amdgpu_vm_bo_invalidated(bo_base); >@@ -2648,7 +2649,7 @@ > */ > long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) > { >- return reservation_object_wait_timeout_rcu(vm->root.base.bo->tbo.resv, >+ return reservation_object_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv, > true, true, timeout); > } > >@@ -2723,7 +2724,7 @@ > if (r) > goto error_free_root; > >- r = reservation_object_reserve_shared(root->tbo.resv, 1); >+ r = reservation_object_reserve_shared(root->tbo.base.resv, 1); > if (r) > goto error_unreserve; > >@@ -2862,6 +2863,13 @@ > WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)), > "CPU update of VM recommended only for large BAR system\n"); > >+ if (vm->use_cpu_for_update) >+ vm->update_funcs = &amdgpu_vm_cpu_funcs; >+ else >+ vm->update_funcs = &amdgpu_vm_sdma_funcs; >+ dma_fence_put(vm->last_update); >+ vm->last_update = NULL; >+ > if (vm->pasid) { > unsigned long flags; > >@@ -3060,12 +3068,12 @@ > switch (args->in.op) { > case AMDGPU_VM_OP_RESERVE_VMID: > /* current, we only have requirement to reserve vmid from gfxhub */ >- r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); >+ r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0); > if (r) > return r; > break; > case AMDGPU_VM_OP_UNRESERVE_VMID: >- amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); >+ amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0); > break; > default: > return -EINVAL; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 2019-08-31 15:01:11.845736167 -0500 >@@ -90,7 +90,7 @@ > | AMDGPU_PTE_WRITEABLE \ > | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) > >-/* NAVI10 only */ >+/* gfx10 */ > #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) > #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) > >@@ -100,9 +100,10 @@ > #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 > > /* max number of VMHUB */ >-#define AMDGPU_MAX_VMHUBS 2 >-#define AMDGPU_GFXHUB 0 >-#define AMDGPU_MMHUB 1 >+#define AMDGPU_MAX_VMHUBS 3 >+#define AMDGPU_GFXHUB_0 0 >+#define AMDGPU_MMHUB_0 1 >+#define AMDGPU_MMHUB_1 2 > > /* hardcode that limit for now */ > #define AMDGPU_VA_RESERVED_SIZE (1ULL << 20) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 2019-08-31 15:01:11.845736167 -0500 >@@ -72,7 +72,7 @@ > if (r) > return r; > >- r = amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.resv, >+ r = amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.base.resv, > owner, false); > if (r) > return r; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 2019-08-31 15:01:11.845736167 -0500 >@@ -25,7 +25,7 @@ > #include "amdgpu.h" > #include "amdgpu_xgmi.h" > #include "amdgpu_smu.h" >- >+#include "df/df_3_6_offset.h" > > static DEFINE_MUTEX(xgmi_mutex); > >@@ -131,9 +131,37 @@ > > } > >+#define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) >+static ssize_t amdgpu_xgmi_show_error(struct device *dev, >+ struct device_attribute *attr, >+ char *buf) >+{ >+ struct drm_device *ddev = dev_get_drvdata(dev); >+ struct amdgpu_device *adev = ddev->dev_private; >+ uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; >+ uint64_t fica_out; >+ unsigned int error_count = 0; >+ >+ ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); >+ ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); > >-static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); >+ fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_ctl_in); >+ if (fica_out != 0x1f) >+ pr_err("xGMI error counters not enabled!\n"); >+ >+ fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_status_in); >+ >+ if ((fica_out & 0xffff) == 2) >+ error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); > >+ adev->df_funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); >+ >+ return snprintf(buf, PAGE_SIZE, "%d\n", error_count); >+} >+ >+ >+static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); >+static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); > > static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, > struct amdgpu_hive_info *hive) >@@ -148,6 +176,12 @@ > return ret; > } > >+ /* Create xgmi error file */ >+ ret = device_create_file(adev->dev, &dev_attr_xgmi_error); >+ if (ret) >+ pr_err("failed to create xgmi_error\n"); >+ >+ > /* Create sysfs link to hive info folder on the first device */ > if (adev != hive->adev) { > ret = sysfs_create_link(&adev->dev->kobj, hive->kobj, >@@ -248,7 +282,7 @@ > > dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate); > >- if (is_support_sw_smu(adev)) >+ if (is_support_sw_smu_xgmi(adev)) > ret = smu_set_xgmi_pstate(&adev->smu, pstate); > if (ret) > dev_err(adev->dev, >@@ -296,23 +330,28 @@ > struct amdgpu_xgmi *entry; > struct amdgpu_device *tmp_adev = NULL; > >- int count = 0, ret = -EINVAL; >+ int count = 0, ret = 0; > > if (!adev->gmc.xgmi.supported) > return 0; > >- ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); >- if (ret) { >- dev_err(adev->dev, >- "XGMI: Failed to get node id\n"); >- return ret; >- } >+ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { >+ ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); >+ if (ret) { >+ dev_err(adev->dev, >+ "XGMI: Failed to get hive id\n"); >+ return ret; >+ } > >- ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); >- if (ret) { >- dev_err(adev->dev, >- "XGMI: Failed to get hive id\n"); >- return ret; >+ ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); >+ if (ret) { >+ dev_err(adev->dev, >+ "XGMI: Failed to get node id\n"); >+ return ret; >+ } >+ } else { >+ adev->gmc.xgmi.hive_id = 16; >+ adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; > } > > hive = amdgpu_get_xgmi_hive(adev, 1); >@@ -332,29 +371,32 @@ > top_info->num_nodes = count; > hive->number_devices = count; > >- list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { >- /* update node list for other device in the hive */ >- if (tmp_adev != adev) { >- top_info = &tmp_adev->psp.xgmi_context.top_info; >- top_info->nodes[count - 1].node_id = adev->gmc.xgmi.node_id; >- top_info->num_nodes = count; >+ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { >+ list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { >+ /* update node list for other device in the hive */ >+ if (tmp_adev != adev) { >+ top_info = &tmp_adev->psp.xgmi_context.top_info; >+ top_info->nodes[count - 1].node_id = >+ adev->gmc.xgmi.node_id; >+ top_info->num_nodes = count; >+ } >+ ret = amdgpu_xgmi_update_topology(hive, tmp_adev); >+ if (ret) >+ goto exit; > } >- ret = amdgpu_xgmi_update_topology(hive, tmp_adev); >- if (ret) >- goto exit; >- } > >- /* get latest topology info for each device from psp */ >- list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { >- ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, >- &tmp_adev->psp.xgmi_context.top_info); >- if (ret) { >- dev_err(tmp_adev->dev, >- "XGMI: Get topology failure on device %llx, hive %llx, ret %d", >- tmp_adev->gmc.xgmi.node_id, >- tmp_adev->gmc.xgmi.hive_id, ret); >- /* To do : continue with some node failed or disable the whole hive */ >- goto exit; >+ /* get latest topology info for each device from psp */ >+ list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { >+ ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, >+ &tmp_adev->psp.xgmi_context.top_info); >+ if (ret) { >+ dev_err(tmp_adev->dev, >+ "XGMI: Get topology failure on device %llx, hive %llx, ret %d", >+ tmp_adev->gmc.xgmi.node_id, >+ tmp_adev->gmc.xgmi.hive_id, ret); >+ /* To do : continue with some node failed or disable the whole hive */ >+ goto exit; >+ } > } > } > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 2019-08-31 15:01:11.845736167 -0500 >@@ -0,0 +1,59 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#include "amdgpu.h" >+#include "soc15.h" >+ >+#include "soc15_common.h" >+#include "soc15_hw_ip.h" >+#include "arct_ip_offset.h" >+ >+int arct_reg_base_init(struct amdgpu_device *adev) >+{ >+ /* HW has more IP blocks, only initialized the block needed by our driver */ >+ uint32_t i; >+ for (i = 0 ; i < MAX_INSTANCE ; ++i) { >+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); >+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); >+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); >+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); >+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); >+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); >+ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); >+ adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); >+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); >+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); >+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); >+ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); >+ adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i])); >+ adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i])); >+ adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i])); >+ adev->reg_offset[SDMA5_HWIP][i] = (uint32_t *)(&(SDMA5_BASE.instance[i])); >+ adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i])); >+ adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i])); >+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); >+ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); >+ } >+ return 0; >+} >+ >+ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c 2019-08-31 15:01:11.845736167 -0500 >@@ -0,0 +1,103 @@ >+/* >+ * Copyright 2016 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#include "amdgpu.h" >+#include "athub_v1_0.h" >+ >+#include "athub/athub_1_0_offset.h" >+#include "athub/athub_1_0_sh_mask.h" >+#include "vega10_enum.h" >+ >+#include "soc15_common.h" >+ >+static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, >+ bool enable) >+{ >+ uint32_t def, data; >+ >+ def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); >+ >+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) >+ data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; >+ else >+ data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; >+ >+ if (def != data) >+ WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); >+} >+ >+static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, >+ bool enable) >+{ >+ uint32_t def, data; >+ >+ def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); >+ >+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && >+ (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) >+ data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; >+ else >+ data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; >+ >+ if(def != data) >+ WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); >+} >+ >+int athub_v1_0_set_clockgating(struct amdgpu_device *adev, >+ enum amd_clockgating_state state) >+{ >+ if (amdgpu_sriov_vf(adev)) >+ return 0; >+ >+ switch (adev->asic_type) { >+ case CHIP_VEGA10: >+ case CHIP_VEGA12: >+ case CHIP_VEGA20: >+ case CHIP_RAVEN: >+ athub_update_medium_grain_clock_gating(adev, >+ state == AMD_CG_STATE_GATE ? true : false); >+ athub_update_medium_grain_light_sleep(adev, >+ state == AMD_CG_STATE_GATE ? true : false); >+ break; >+ default: >+ break; >+ } >+ >+ return 0; >+} >+ >+void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) >+{ >+ int data; >+ >+ if (amdgpu_sriov_vf(adev)) >+ *flags = 0; >+ >+ /* AMD_CG_SUPPORT_ATHUB_MGCG */ >+ data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); >+ if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) >+ *flags |= AMD_CG_SUPPORT_ATHUB_MGCG; >+ >+ /* AMD_CG_SUPPORT_ATHUB_LS */ >+ if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK) >+ *flags |= AMD_CG_SUPPORT_ATHUB_LS; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h 2019-08-31 15:01:11.845736167 -0500 >@@ -0,0 +1,30 @@ >+/* >+ * Copyright 2016 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#ifndef __ATHUB_V1_0_H__ >+#define __ATHUB_V1_0_H__ >+ >+int athub_v1_0_set_clockgating(struct amdgpu_device *adev, >+ enum amd_clockgating_state state); >+void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c 2019-08-31 15:01:11.845736167 -0500 >@@ -74,6 +74,8 @@ > > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > athub_v2_0_update_medium_grain_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > athub_v2_0_update_medium_grain_light_sleep(adev, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/cik.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/cik.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/cik.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/cik.c 2019-08-31 15:01:11.845736167 -0500 >@@ -1291,6 +1291,12 @@ > return r; > } > >+static enum amd_reset_method >+cik_asic_reset_method(struct amdgpu_device *adev) >+{ >+ return AMD_RESET_METHOD_LEGACY; >+} >+ > static u32 cik_get_config_memsize(struct amdgpu_device *adev) > { > return RREG32(mmCONFIG_MEMSIZE); >@@ -1823,6 +1829,7 @@ > .read_bios_from_rom = &cik_read_bios_from_rom, > .read_register = &cik_read_register, > .reset = &cik_asic_reset, >+ .reset_method = &cik_asic_reset_method, > .set_vga_state = &cik_vga_set_state, > .get_xclk = &cik_get_xclk, > .set_uvd_clocks = &cik_set_uvd_clocks, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 2019-08-31 15:01:11.846736167 -0500 >@@ -236,6 +236,7 @@ > int crtc_id, u64 crtc_base, bool async) > { > struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; >+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; > u32 tmp; > > /* flip at hsync for async, default is vsync */ >@@ -243,6 +244,9 @@ > tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, > GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); > WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); >+ /* update pitch */ >+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, >+ fb->pitches[0] / fb->format->cpp[0]); > /* update the primary scanout address */ > WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, > upper_32_bits(crtc_base)); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 2019-08-31 15:01:11.846736167 -0500 >@@ -254,6 +254,7 @@ > int crtc_id, u64 crtc_base, bool async) > { > struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; >+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; > u32 tmp; > > /* flip immediate for async, default is vsync */ >@@ -261,6 +262,9 @@ > tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, > GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); > WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); >+ /* update pitch */ >+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, >+ fb->pitches[0] / fb->format->cpp[0]); > /* update the scanout addresses */ > WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, > upper_32_bits(crtc_base)); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 2019-08-31 15:01:11.846736167 -0500 >@@ -191,10 +191,14 @@ > int crtc_id, u64 crtc_base, bool async) > { > struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; >+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; > > /* flip at hsync for async, default is vsync */ > WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? > GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); >+ /* update pitch */ >+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, >+ fb->pitches[0] / fb->format->cpp[0]); > /* update the scanout addresses */ > WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, > upper_32_bits(crtc_base)); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 2019-08-31 15:01:11.846736167 -0500 >@@ -184,10 +184,14 @@ > int crtc_id, u64 crtc_base, bool async) > { > struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; >+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; > > /* flip at hsync for async, default is vsync */ > WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? > GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); >+ /* update pitch */ >+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, >+ fb->pitches[0] / fb->format->cpp[0]); > /* update the primary scanout addresses */ > WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, > upper_32_bits(crtc_base)); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_virtual.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_virtual.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 2019-08-31 15:01:11.846736167 -0500 >@@ -454,13 +454,8 @@ > #endif > /* no DCE */ > break; >- case CHIP_VEGA10: >- case CHIP_VEGA12: >- case CHIP_VEGA20: >- case CHIP_NAVI10: >- break; > default: >- DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type); >+ break; > } > return 0; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/df_v3_6.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/df_v3_6.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/df_v3_6.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/df_v3_6.c 2019-08-31 15:01:11.846736167 -0500 >@@ -93,6 +93,96 @@ > NULL > }; > >+static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, >+ uint32_t ficaa_val) >+{ >+ unsigned long flags, address, data; >+ uint32_t ficadl_val, ficadh_val; >+ >+ address = adev->nbio_funcs->get_pcie_index_offset(adev); >+ data = adev->nbio_funcs->get_pcie_data_offset(adev); >+ >+ spin_lock_irqsave(&adev->pcie_idx_lock, flags); >+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); >+ WREG32(data, ficaa_val); >+ >+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3); >+ ficadl_val = RREG32(data); >+ >+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); >+ ficadh_val = RREG32(data); >+ >+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); >+ >+ return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val); >+} >+ >+static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, >+ uint32_t ficadl_val, uint32_t ficadh_val) >+{ >+ unsigned long flags, address, data; >+ >+ address = adev->nbio_funcs->get_pcie_index_offset(adev); >+ data = adev->nbio_funcs->get_pcie_data_offset(adev); >+ >+ spin_lock_irqsave(&adev->pcie_idx_lock, flags); >+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); >+ WREG32(data, ficaa_val); >+ >+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3); >+ WREG32(data, ficadl_val); >+ >+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); >+ WREG32(data, ficadh_val); >+ >+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); >+} >+ >+/* >+ * df_v3_6_perfmon_rreg - read perfmon lo and hi >+ * >+ * required to be atomic. no mmio method provided so subsequent reads for lo >+ * and hi require to preserve df finite state machine >+ */ >+static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev, >+ uint32_t lo_addr, uint32_t *lo_val, >+ uint32_t hi_addr, uint32_t *hi_val) >+{ >+ unsigned long flags, address, data; >+ >+ address = adev->nbio_funcs->get_pcie_index_offset(adev); >+ data = adev->nbio_funcs->get_pcie_data_offset(adev); >+ >+ spin_lock_irqsave(&adev->pcie_idx_lock, flags); >+ WREG32(address, lo_addr); >+ *lo_val = RREG32(data); >+ WREG32(address, hi_addr); >+ *hi_val = RREG32(data); >+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); >+} >+ >+/* >+ * df_v3_6_perfmon_wreg - write to perfmon lo and hi >+ * >+ * required to be atomic. no mmio method provided so subsequent reads after >+ * data writes cannot occur to preserve data fabrics finite state machine. >+ */ >+static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr, >+ uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val) >+{ >+ unsigned long flags, address, data; >+ >+ address = adev->nbio_funcs->get_pcie_index_offset(adev); >+ data = adev->nbio_funcs->get_pcie_data_offset(adev); >+ >+ spin_lock_irqsave(&adev->pcie_idx_lock, flags); >+ WREG32(address, lo_addr); >+ WREG32(data, lo_val); >+ WREG32(address, hi_addr); >+ WREG32(data, hi_val); >+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); >+} >+ > /* get the number of df counters available */ > static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev, > struct device_attribute *attr, >@@ -268,6 +358,10 @@ > uint32_t *lo_val, > uint32_t *hi_val) > { >+ >+ uint32_t eventsel, instance, unitmask; >+ uint32_t instance_10, instance_5432, instance_76; >+ > df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr); > > if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) { >@@ -276,40 +370,33 @@ > return -ENXIO; > } > >- if (lo_val && hi_val) { >- uint32_t eventsel, instance, unitmask; >- uint32_t instance_10, instance_5432, instance_76; >- >- eventsel = DF_V3_6_GET_EVENT(config) & 0x3f; >- unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf; >- instance = DF_V3_6_GET_INSTANCE(config); >- >- instance_10 = instance & 0x3; >- instance_5432 = (instance >> 2) & 0xf; >- instance_76 = (instance >> 6) & 0x3; >+ eventsel = DF_V3_6_GET_EVENT(config) & 0x3f; >+ unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf; >+ instance = DF_V3_6_GET_INSTANCE(config); >+ >+ instance_10 = instance & 0x3; >+ instance_5432 = (instance >> 2) & 0xf; >+ instance_76 = (instance >> 6) & 0x3; > >- *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel; >- *hi_val = (instance_76 << 29) | instance_5432; >- } >+ *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22); >+ *hi_val = (instance_76 << 29) | instance_5432; >+ >+ DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x", >+ config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val); > > return 0; > } > >-/* assign df performance counters for read */ >-static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev, >- uint64_t config, >- int *is_assigned) >+/* add df performance counters for read */ >+static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev, >+ uint64_t config) > { > int i, target_cntr; > >- *is_assigned = 0; >- > target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); > >- if (target_cntr >= 0) { >- *is_assigned = 1; >+ if (target_cntr >= 0) > return 0; >- } > > for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) { > if (adev->df_perfmon_config_assign_mask[i] == 0U) { >@@ -344,45 +431,13 @@ > if ((lo_base_addr == 0) || (hi_base_addr == 0)) > return; > >- WREG32_PCIE(lo_base_addr, 0UL); >- WREG32_PCIE(hi_base_addr, 0UL); >-} >- >- >-static int df_v3_6_add_perfmon_cntr(struct amdgpu_device *adev, >- uint64_t config) >-{ >- uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; >- int ret, is_assigned; >- >- ret = df_v3_6_pmc_assign_cntr(adev, config, &is_assigned); >- >- if (ret || is_assigned) >- return ret; >- >- ret = df_v3_6_pmc_get_ctrl_settings(adev, >- config, >- &lo_base_addr, >- &hi_base_addr, >- &lo_val, >- &hi_val); >- >- if (ret) >- return ret; >- >- DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x", >- config, lo_base_addr, hi_base_addr, lo_val, hi_val); >- >- WREG32_PCIE(lo_base_addr, lo_val); >- WREG32_PCIE(hi_base_addr, hi_val); >- >- return ret; >+ df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0); > } > > static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config, > int is_enable) > { >- uint32_t lo_base_addr, hi_base_addr, lo_val; >+ uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; > int ret = 0; > > switch (adev->asic_type) { >@@ -391,24 +446,20 @@ > df_v3_6_reset_perfmon_cntr(adev, config); > > if (is_enable) { >- ret = df_v3_6_add_perfmon_cntr(adev, config); >+ ret = df_v3_6_pmc_add_cntr(adev, config); > } else { > ret = df_v3_6_pmc_get_ctrl_settings(adev, > config, > &lo_base_addr, > &hi_base_addr, >- NULL, >- NULL); >+ &lo_val, >+ &hi_val); > > if (ret) > return ret; > >- lo_val = RREG32_PCIE(lo_base_addr); >- >- DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x", >- config, lo_base_addr, hi_base_addr, lo_val); >- >- WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22)); >+ df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val, >+ hi_base_addr, hi_val); > } > > break; >@@ -422,7 +473,7 @@ > static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config, > int is_disable) > { >- uint32_t lo_base_addr, hi_base_addr, lo_val; >+ uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; > int ret = 0; > > switch (adev->asic_type) { >@@ -431,18 +482,13 @@ > config, > &lo_base_addr, > &hi_base_addr, >- NULL, >- NULL); >+ &lo_val, >+ &hi_val); > > if (ret) > return ret; > >- lo_val = RREG32_PCIE(lo_base_addr); >- >- DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x", >- config, lo_base_addr, hi_base_addr, lo_val); >- >- WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22)); >+ df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0); > > if (is_disable) > df_v3_6_pmc_release_cntr(adev, config); >@@ -471,8 +517,8 @@ > if ((lo_base_addr == 0) || (hi_base_addr == 0)) > return; > >- lo_val = RREG32_PCIE(lo_base_addr); >- hi_val = RREG32_PCIE(hi_base_addr); >+ df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val, >+ hi_base_addr, &hi_val); > > *count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL); > >@@ -480,7 +526,7 @@ > *count = 0; > > DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x", >- config, lo_base_addr, hi_base_addr, lo_val, hi_val); >+ config, lo_base_addr, hi_base_addr, lo_val, hi_val); > > break; > >@@ -499,5 +545,7 @@ > .get_clockgating_state = df_v3_6_get_clockgating_state, > .pmc_start = df_v3_6_pmc_start, > .pmc_stop = df_v3_6_pmc_stop, >- .pmc_get_count = df_v3_6_pmc_get_count >+ .pmc_get_count = df_v3_6_pmc_get_count, >+ .get_fica = df_v3_6_get_fica, >+ .set_fica = df_v3_6_set_fica > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 2019-08-31 15:01:11.847736167 -0500 >@@ -357,7 +357,7 @@ > > void gfxhub_v1_0_init(struct amdgpu_device *adev) > { >- struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; >+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; > > hub->ctx0_ptb_addr_lo32 = > SOC15_REG_OFFSET(GC, 0, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 2019-08-31 15:01:11.847736167 -0500 >@@ -140,7 +140,7 @@ > /* XXX for emulation, Refer to closed source code.*/ > tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, > L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); >- tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); >+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); > tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); > tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); > WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); >@@ -333,7 +333,7 @@ > > void gfxhub_v2_0_init(struct amdgpu_device *adev) > { >- struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; >+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; > > hub->ctx0_ptb_addr_lo32 = > SOC15_REG_OFFSET(GC, 0, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 2019-08-31 15:01:12.277736205 -0500 >@@ -20,8 +20,12 @@ > * OTHER DEALINGS IN THE SOFTWARE. > * > */ >+ >+#include <linux/delay.h> >+#include <linux/kernel.h> > #include <linux/firmware.h> >-#include <drm/drmP.h> >+#include <linux/module.h> >+#include <linux/pci.h> > #include "amdgpu.h" > #include "amdgpu_gfx.h" > #include "amdgpu_psp.h" >@@ -56,6 +60,9 @@ > #define F32_CE_PROGRAM_RAM_SIZE 65536 > #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L > >+#define mmCGTT_GS_NGG_CLK_CTRL 0x5087 >+#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 >+ > MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); > MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); > MODULE_FIRMWARE("amdgpu/navi10_me.bin"); >@@ -63,6 +70,20 @@ > MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); > MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); > >+MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_me.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); >+ >+MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_me.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); >+ > static const struct soc15_reg_golden golden_settings_gc_10_1[] = > { > SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), >@@ -109,6 +130,99 @@ > /* Pending on emulation bring up */ > }; > >+static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = >+{ >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000), >+}; >+ >+static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = >+{ >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) >+}; >+ >+static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = >+{ >+ /* Pending on emulation bring up */ >+}; >+ >+static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = >+{ >+ /* Pending on emulation bring up */ >+}; >+ > #define DEFAULT_SH_MEM_CONFIG \ > ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ > (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ >@@ -250,6 +364,22 @@ > golden_settings_gc_10_0_nv10, > (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); > break; >+ case CHIP_NAVI14: >+ soc15_program_register_sequence(adev, >+ golden_settings_gc_10_1_1, >+ (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); >+ soc15_program_register_sequence(adev, >+ golden_settings_gc_10_1_nv14, >+ (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); >+ break; >+ case CHIP_NAVI12: >+ soc15_program_register_sequence(adev, >+ golden_settings_gc_10_1_2, >+ (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); >+ soc15_program_register_sequence(adev, >+ golden_settings_gc_10_1_2_nv12, >+ (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); >+ break; > default: > break; > } >@@ -331,7 +461,7 @@ > if (amdgpu_emu_mode == 1) > msleep(1); > else >- DRM_UDELAY(1); >+ udelay(1); > } > if (i < adev->usec_timeout) { > if (amdgpu_emu_mode == 1) >@@ -481,6 +611,12 @@ > case CHIP_NAVI10: > chip_name = "navi10"; > break; >+ case CHIP_NAVI14: >+ chip_name = "navi14"; >+ break; >+ case CHIP_NAVI12: >+ chip_name = "navi12"; >+ break; > default: > BUG(); > } >@@ -1026,6 +1162,8 @@ > > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > adev->gfx.config.max_hw_contexts = 8; > adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; > adev->gfx.config.sc_prim_fifo_size_backend = 0x100; >@@ -1133,6 +1271,8 @@ > > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > adev->gfx.me.num_me = 1; > adev->gfx.me.num_pipe_per_me = 2; > adev->gfx.me.num_queue_per_pipe = 1; >@@ -1452,6 +1592,25 @@ > } > } > >+static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) >+{ >+ int vmid; >+ >+ /* >+ * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA >+ * access. Compute VMIDs should be enabled by FW for target VMIDs, >+ * the driver can enable them for graphics. VMID0 should maintain >+ * access so that HWS firmware can save/restore entries. >+ */ >+ for (vmid = 1; vmid < 16; vmid++) { >+ WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); >+ WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); >+ WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); >+ WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); >+ } >+} >+ >+ > static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) > { > int i, j, k; >@@ -1461,7 +1620,8 @@ > u32 utcl_invreq_disable = 0; > /* > * GCRD_TARGETS_DISABLE field contains >- * for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0] >+ * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] >+ * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] > */ > u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( > 2 * max_wgp_per_sh + /* TCP */ >@@ -1469,7 +1629,8 @@ > 4); /* GL1C */ > /* > * UTCL1_UTCL0_INVREQ_DISABLE field contains >- * for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] >+ * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] >+ * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] > */ > u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( > 2 * max_wgp_per_sh + /* TCP */ >@@ -1477,7 +1638,9 @@ > 4 + /* RMI */ > 1); /* SQG */ > >- if (adev->asic_type == CHIP_NAVI10) { >+ if (adev->asic_type == CHIP_NAVI10 || >+ adev->asic_type == CHIP_NAVI14 || >+ adev->asic_type == CHIP_NAVI12) { > mutex_lock(&adev->grbm_idx_mutex); > for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { > for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { >@@ -1535,7 +1698,7 @@ > /* XXX SH_MEM regs */ > /* where to put LDS, scratch, GPUVM in FSA64 space */ > mutex_lock(&adev->srbm_mutex); >- for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { >+ for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { > nv_grbm_select(adev, 0, 0, 0, i); > /* CP and shaders */ > WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); >@@ -1552,6 +1715,7 @@ > mutex_unlock(&adev->srbm_mutex); > > gfx_v10_0_init_compute_vmid(adev); >+ gfx_v10_0_init_gds_vmid(adev); > > } > >@@ -1584,9 +1748,12 @@ > > static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > { >+ int i; >+ > gfx_v10_0_init_csb(adev); > >- amdgpu_gmc_flush_gpu_tlb(adev, 0, 0); >+ for (i = 0; i < adev->num_vmhubs; i++) >+ amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > return; >@@ -1624,9 +1791,9 @@ > * hence no handshake between SMU & RLC > * GFXOFF will be disabled > */ >- rlc_pg_cntl |= 0x80000; >+ rlc_pg_cntl |= 0x800000; > } else >- rlc_pg_cntl &= ~0x80000; >+ rlc_pg_cntl &= ~0x800000; > WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); > } > >@@ -3614,20 +3781,12 @@ > > static int gfx_v10_0_suspend(void *handle) > { >- struct amdgpu_device *adev = (struct amdgpu_device *)handle; >- >- adev->in_suspend = true; >- return gfx_v10_0_hw_fini(adev); >+ return gfx_v10_0_hw_fini(handle); > } > > static int gfx_v10_0_resume(void *handle) > { >- struct amdgpu_device *adev = (struct amdgpu_device *)handle; >- int r; >- >- r = gfx_v10_0_hw_init(adev); >- adev->in_suspend = false; >- return r; >+ return gfx_v10_0_hw_init(handle); > } > > static bool gfx_v10_0_is_idle(void *handle) >@@ -4037,6 +4196,7 @@ > bool enable = (state == AMD_PG_STATE_GATE) ? true : false; > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: > if (!enable) { > amdgpu_gfx_off_ctrl(adev, false); > cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); >@@ -4056,6 +4216,8 @@ > > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > gfx_v10_0_update_gfx_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > break; >@@ -4453,7 +4615,7 @@ > if (ring->trail_seq == > le32_to_cpu(*(ring->trail_fence_cpu_addr))) > break; >- DRM_UDELAY(1); >+ udelay(1); > } > > if (i >= adev->usec_timeout) { >@@ -4927,7 +5089,7 @@ > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_GFXHUB, >+ .vmhub = AMDGPU_GFXHUB_0, > .get_rptr = gfx_v10_0_ring_get_rptr_gfx, > .get_wptr = gfx_v10_0_ring_get_wptr_gfx, > .set_wptr = gfx_v10_0_ring_set_wptr_gfx, >@@ -4978,7 +5140,7 @@ > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_GFXHUB, >+ .vmhub = AMDGPU_GFXHUB_0, > .get_rptr = gfx_v10_0_ring_get_rptr_compute, > .get_wptr = gfx_v10_0_ring_get_wptr_compute, > .set_wptr = gfx_v10_0_ring_set_wptr_compute, >@@ -5011,7 +5173,7 @@ > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_GFXHUB, >+ .vmhub = AMDGPU_GFXHUB_0, > .get_rptr = gfx_v10_0_ring_get_rptr_compute, > .get_wptr = gfx_v10_0_ring_get_wptr_compute, > .set_wptr = gfx_v10_0_ring_set_wptr_compute, >@@ -5088,6 +5250,8 @@ > { > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; > break; > default: >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 2019-08-31 15:01:11.847736167 -0500 >@@ -1890,6 +1890,24 @@ > } > } > >+static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev) >+{ >+ int vmid; >+ >+ /* >+ * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA >+ * access. Compute VMIDs should be enabled by FW for target VMIDs, >+ * the driver can enable them for graphics. VMID0 should maintain >+ * access so that HWS firmware can save/restore entries. >+ */ >+ for (vmid = 1; vmid < 16; vmid++) { >+ WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); >+ WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); >+ WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); >+ WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); >+ } >+} >+ > static void gfx_v7_0_config_init(struct amdgpu_device *adev) > { > adev->gfx.config.double_offchip_lds_buf = 1; >@@ -1968,6 +1986,7 @@ > mutex_unlock(&adev->srbm_mutex); > > gfx_v7_0_init_compute_vmid(adev); >+ gfx_v7_0_init_gds_vmid(adev); > > WREG32(mmSX_DEBUG_1, 0x20); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 2019-08-31 15:01:12.274736205 -0500 >@@ -3750,6 +3750,24 @@ > } > } > >+static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev) >+{ >+ int vmid; >+ >+ /* >+ * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA >+ * access. Compute VMIDs should be enabled by FW for target VMIDs, >+ * the driver can enable them for graphics. VMID0 should maintain >+ * access so that HWS firmware can save/restore entries. >+ */ >+ for (vmid = 1; vmid < 16; vmid++) { >+ WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); >+ WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); >+ WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); >+ WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); >+ } >+} >+ > static void gfx_v8_0_config_init(struct amdgpu_device *adev) > { > switch (adev->asic_type) { >@@ -3816,6 +3834,7 @@ > mutex_unlock(&adev->srbm_mutex); > > gfx_v8_0_init_compute_vmid(adev); >+ gfx_v8_0_init_gds_vmid(adev); > > mutex_lock(&adev->grbm_idx_mutex); > /* >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 2019-08-31 15:09:16.619778999 -0500 >@@ -36,10 +36,10 @@ > > #include "gc/gc_9_0_offset.h" > #include "gc/gc_9_0_sh_mask.h" >+ > #include "vega10_enum.h" > #include "hdp/hdp_4_0_offset.h" > >-#include "soc15.h" > #include "soc15_common.h" > #include "clearstate_gfx9.h" > #include "v9_structs.h" >@@ -60,6 +60,9 @@ > #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L > #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L > >+#define mmGCEA_PROBE_MAP 0x070c >+#define mmGCEA_PROBE_MAP_BASE_IDX 0 >+ > MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); > MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); > MODULE_FIRMWARE("amdgpu/vega10_me.bin"); >@@ -104,6 +107,397 @@ > MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); > MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); > >+MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); >+MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin"); >+MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); >+ >+MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); >+MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); >+MODULE_FIRMWARE("amdgpu/renoir_me.bin"); >+MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); >+MODULE_FIRMWARE("amdgpu/renoir_mec2.bin"); >+MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); >+ >+#define mmTCP_CHAN_STEER_0_ARCT 0x0b03 >+#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 >+#define mmTCP_CHAN_STEER_1_ARCT 0x0b04 >+#define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 >+#define mmTCP_CHAN_STEER_2_ARCT 0x0b09 >+#define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 >+#define mmTCP_CHAN_STEER_3_ARCT 0x0b0a >+#define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 >+#define mmTCP_CHAN_STEER_4_ARCT 0x0b0b >+#define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 >+#define mmTCP_CHAN_STEER_5_ARCT 0x0b0c >+#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 >+ >+enum ta_ras_gfx_subblock { >+ /*CPC*/ >+ TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, >+ TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, >+ TA_RAS_BLOCK__GFX_CPC_UCODE, >+ TA_RAS_BLOCK__GFX_DC_STATE_ME1, >+ TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, >+ TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, >+ TA_RAS_BLOCK__GFX_DC_STATE_ME2, >+ TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, >+ TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, >+ TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, >+ /* CPF*/ >+ TA_RAS_BLOCK__GFX_CPF_INDEX_START, >+ TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, >+ TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, >+ TA_RAS_BLOCK__GFX_CPF_TAG, >+ TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, >+ /* CPG*/ >+ TA_RAS_BLOCK__GFX_CPG_INDEX_START, >+ TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, >+ TA_RAS_BLOCK__GFX_CPG_DMA_TAG, >+ TA_RAS_BLOCK__GFX_CPG_TAG, >+ TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, >+ /* GDS*/ >+ TA_RAS_BLOCK__GFX_GDS_INDEX_START, >+ TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, >+ TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, >+ TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, >+ TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, >+ TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, >+ TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, >+ /* SPI*/ >+ TA_RAS_BLOCK__GFX_SPI_SR_MEM, >+ /* SQ*/ >+ TA_RAS_BLOCK__GFX_SQ_INDEX_START, >+ TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, >+ TA_RAS_BLOCK__GFX_SQ_LDS_D, >+ TA_RAS_BLOCK__GFX_SQ_LDS_I, >+ TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ >+ TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, >+ /* SQC (3 ranges)*/ >+ TA_RAS_BLOCK__GFX_SQC_INDEX_START, >+ /* SQC range 0*/ >+ TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, >+ TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = >+ TA_RAS_BLOCK__GFX_SQC_INDEX0_START, >+ TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, >+ TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, >+ TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, >+ TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, >+ TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, >+ TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, >+ TA_RAS_BLOCK__GFX_SQC_INDEX0_END = >+ TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, >+ /* SQC range 1*/ >+ TA_RAS_BLOCK__GFX_SQC_INDEX1_START, >+ TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = >+ TA_RAS_BLOCK__GFX_SQC_INDEX1_START, >+ TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, >+ TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, >+ TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, >+ TA_RAS_BLOCK__GFX_SQC_INDEX1_END = >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, >+ /* SQC range 2*/ >+ TA_RAS_BLOCK__GFX_SQC_INDEX2_START, >+ TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = >+ TA_RAS_BLOCK__GFX_SQC_INDEX2_START, >+ TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, >+ TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, >+ TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, >+ TA_RAS_BLOCK__GFX_SQC_INDEX2_END = >+ TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, >+ TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, >+ /* TA*/ >+ TA_RAS_BLOCK__GFX_TA_INDEX_START, >+ TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, >+ TA_RAS_BLOCK__GFX_TA_FS_AFIFO, >+ TA_RAS_BLOCK__GFX_TA_FL_LFIFO, >+ TA_RAS_BLOCK__GFX_TA_FX_LFIFO, >+ TA_RAS_BLOCK__GFX_TA_FS_CFIFO, >+ TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, >+ /* TCA*/ >+ TA_RAS_BLOCK__GFX_TCA_INDEX_START, >+ TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, >+ TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, >+ TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, >+ /* TCC (5 sub-ranges)*/ >+ TA_RAS_BLOCK__GFX_TCC_INDEX_START, >+ /* TCC range 0*/ >+ TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, >+ TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, >+ TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, >+ TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, >+ TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, >+ TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, >+ TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, >+ TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, >+ TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, >+ TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, >+ /* TCC range 1*/ >+ TA_RAS_BLOCK__GFX_TCC_INDEX1_START, >+ TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, >+ TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, >+ TA_RAS_BLOCK__GFX_TCC_INDEX1_END = >+ TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, >+ /* TCC range 2*/ >+ TA_RAS_BLOCK__GFX_TCC_INDEX2_START, >+ TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, >+ TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, >+ TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, >+ TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, >+ TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, >+ TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, >+ TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, >+ TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, >+ TA_RAS_BLOCK__GFX_TCC_INDEX2_END = >+ TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, >+ /* TCC range 3*/ >+ TA_RAS_BLOCK__GFX_TCC_INDEX3_START, >+ TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, >+ TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, >+ TA_RAS_BLOCK__GFX_TCC_INDEX3_END = >+ TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, >+ /* TCC range 4*/ >+ TA_RAS_BLOCK__GFX_TCC_INDEX4_START, >+ TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = >+ TA_RAS_BLOCK__GFX_TCC_INDEX4_START, >+ TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, >+ TA_RAS_BLOCK__GFX_TCC_INDEX4_END = >+ TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, >+ TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, >+ /* TCI*/ >+ TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, >+ /* TCP*/ >+ TA_RAS_BLOCK__GFX_TCP_INDEX_START, >+ TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, >+ TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, >+ TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, >+ TA_RAS_BLOCK__GFX_TCP_VM_FIFO, >+ TA_RAS_BLOCK__GFX_TCP_DB_RAM, >+ TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, >+ TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, >+ TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, >+ /* TD*/ >+ TA_RAS_BLOCK__GFX_TD_INDEX_START, >+ TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, >+ TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, >+ TA_RAS_BLOCK__GFX_TD_CS_FIFO, >+ TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, >+ /* EA (3 sub-ranges)*/ >+ TA_RAS_BLOCK__GFX_EA_INDEX_START, >+ /* EA range 0*/ >+ TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, >+ TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, >+ TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, >+ TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, >+ TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, >+ TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, >+ TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, >+ TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, >+ TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, >+ TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, >+ /* EA range 1*/ >+ TA_RAS_BLOCK__GFX_EA_INDEX1_START, >+ TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, >+ TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, >+ TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, >+ TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, >+ TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, >+ TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, >+ TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, >+ TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, >+ /* EA range 2*/ >+ TA_RAS_BLOCK__GFX_EA_INDEX2_START, >+ TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, >+ TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, >+ TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, >+ TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, >+ TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, >+ TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, >+ /* UTC VM L2 bank*/ >+ TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, >+ /* UTC VM walker*/ >+ TA_RAS_BLOCK__UTC_VML2_WALKER, >+ /* UTC ATC L2 2MB cache*/ >+ TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, >+ /* UTC ATC L2 4KB cache*/ >+ TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, >+ TA_RAS_BLOCK__GFX_MAX >+}; >+ >+struct ras_gfx_subblock { >+ unsigned char *name; >+ int ta_subblock; >+ int hw_supported_error_type; >+ int sw_supported_error_type; >+}; >+ >+#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ >+ [AMDGPU_RAS_BLOCK__##subblock] = { \ >+ #subblock, \ >+ TA_RAS_BLOCK__##subblock, \ >+ ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ >+ (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ >+ } >+ >+static const struct ras_gfx_subblock ras_gfx_subblocks[] = { >+ AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, >+ 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, >+ 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, >+ 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, >+ 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, >+ 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, >+ 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, >+ 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, >+ 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, >+ 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, >+ 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, >+ 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, >+ 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, >+ 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), >+ AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), >+}; >+ > static const struct soc15_reg_golden golden_settings_gc_9_0[] = > { > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), >@@ -227,6 +621,22 @@ > SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), > }; > >+static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = >+{ >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), >+}; >+ > static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = > { > SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), >@@ -271,6 +681,18 @@ > SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) > }; > >+static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = >+{ >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), >+}; >+ > static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = > { > mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, >@@ -310,19 +732,21 @@ > static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); > static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); > static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); >+static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, >+ void *ras_error_status); >+static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, >+ void *inject_if); > > static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) > { > switch (adev->asic_type) { > case CHIP_VEGA10: >- if (!amdgpu_virt_support_skip_setting(adev)) { >- soc15_program_register_sequence(adev, >- golden_settings_gc_9_0, >- ARRAY_SIZE(golden_settings_gc_9_0)); >- soc15_program_register_sequence(adev, >- golden_settings_gc_9_0_vg10, >- ARRAY_SIZE(golden_settings_gc_9_0_vg10)); >- } >+ soc15_program_register_sequence(adev, >+ golden_settings_gc_9_0, >+ ARRAY_SIZE(golden_settings_gc_9_0)); >+ soc15_program_register_sequence(adev, >+ golden_settings_gc_9_0_vg10, >+ ARRAY_SIZE(golden_settings_gc_9_0_vg10)); > break; > case CHIP_VEGA12: > soc15_program_register_sequence(adev, >@@ -340,6 +764,11 @@ > golden_settings_gc_9_0_vg20, > ARRAY_SIZE(golden_settings_gc_9_0_vg20)); > break; >+ case CHIP_ARCTURUS: >+ soc15_program_register_sequence(adev, >+ golden_settings_gc_9_4_1_arct, >+ ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); >+ break; > case CHIP_RAVEN: > soc15_program_register_sequence(adev, golden_settings_gc_9_1, > ARRAY_SIZE(golden_settings_gc_9_1)); >@@ -352,12 +781,18 @@ > golden_settings_gc_9_1_rv1, > ARRAY_SIZE(golden_settings_gc_9_1_rv1)); > break; >+ case CHIP_RENOIR: >+ soc15_program_register_sequence(adev, >+ golden_settings_gc_9_1_rn, >+ ARRAY_SIZE(golden_settings_gc_9_1_rn)); >+ return; /* for renoir, don't need common goldensetting */ > default: > break; > } > >- soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, >- (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); >+ if (adev->asic_type != CHIP_ARCTURUS) >+ soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, >+ (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); > } > > static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) >@@ -596,14 +1031,14 @@ > case CHIP_VEGA20: > break; > case CHIP_RAVEN: >- if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) >- break; >- if ((adev->gfx.rlc_fw_version != 106 && >- adev->gfx.rlc_fw_version < 531) || >- (adev->gfx.rlc_fw_version == 53815) || >- (adev->gfx.rlc_feature_version < 1) || >- !adev->gfx.rlc.is_rlc_v2_1) >+ if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) >+ &&((adev->gfx.rlc_fw_version != 106 && >+ adev->gfx.rlc_fw_version < 531) || >+ (adev->gfx.rlc_fw_version == 53815) || >+ (adev->gfx.rlc_feature_version < 1) || >+ !adev->gfx.rlc.is_rlc_v2_1)) > adev->pm.pp_feature &= ~PP_GFXOFF_MASK; >+ > if (adev->pm.pp_feature & PP_GFXOFF_MASK) > adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | > AMD_PG_SUPPORT_CP | >@@ -614,44 +1049,14 @@ > } > } > >-static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) >+static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, >+ const char *chip_name) > { >- const char *chip_name; > char fw_name[30]; > int err; > struct amdgpu_firmware_info *info = NULL; > const struct common_firmware_header *header = NULL; > const struct gfx_firmware_header_v1_0 *cp_hdr; >- const struct rlc_firmware_header_v2_0 *rlc_hdr; >- unsigned int *tmp = NULL; >- unsigned int i = 0; >- uint16_t version_major; >- uint16_t version_minor; >- uint32_t smu_version; >- >- DRM_DEBUG("\n"); >- >- switch (adev->asic_type) { >- case CHIP_VEGA10: >- chip_name = "vega10"; >- break; >- case CHIP_VEGA12: >- chip_name = "vega12"; >- break; >- case CHIP_VEGA20: >- chip_name = "vega20"; >- break; >- case CHIP_RAVEN: >- if (adev->rev_id >= 8) >- chip_name = "raven2"; >- else if (adev->pdev->device == 0x15d8) >- chip_name = "picasso"; >- else >- chip_name = "raven"; >- break; >- default: >- BUG(); >- } > > snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); > err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); >@@ -686,6 +1091,58 @@ > adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); > adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); > >+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { >+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; >+ info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; >+ info->fw = adev->gfx.pfp_fw; >+ header = (const struct common_firmware_header *)info->fw->data; >+ adev->firmware.fw_size += >+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); >+ >+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; >+ info->ucode_id = AMDGPU_UCODE_ID_CP_ME; >+ info->fw = adev->gfx.me_fw; >+ header = (const struct common_firmware_header *)info->fw->data; >+ adev->firmware.fw_size += >+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); >+ >+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; >+ info->ucode_id = AMDGPU_UCODE_ID_CP_CE; >+ info->fw = adev->gfx.ce_fw; >+ header = (const struct common_firmware_header *)info->fw->data; >+ adev->firmware.fw_size += >+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); >+ } >+ >+out: >+ if (err) { >+ dev_err(adev->dev, >+ "gfx9: Failed to load firmware \"%s\"\n", >+ fw_name); >+ release_firmware(adev->gfx.pfp_fw); >+ adev->gfx.pfp_fw = NULL; >+ release_firmware(adev->gfx.me_fw); >+ adev->gfx.me_fw = NULL; >+ release_firmware(adev->gfx.ce_fw); >+ adev->gfx.ce_fw = NULL; >+ } >+ return err; >+} >+ >+static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, >+ const char *chip_name) >+{ >+ char fw_name[30]; >+ int err; >+ struct amdgpu_firmware_info *info = NULL; >+ const struct common_firmware_header *header = NULL; >+ const struct rlc_firmware_header_v2_0 *rlc_hdr; >+ unsigned int *tmp = NULL; >+ unsigned int i = 0; >+ uint16_t version_major; >+ uint16_t version_minor; >+ uint32_t smu_version; >+ > /* > * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin > * instead of picasso_rlc.bin. >@@ -760,57 +1217,7 @@ > if (adev->gfx.rlc.is_rlc_v2_1) > gfx_v9_0_init_rlc_ext_microcode(adev); > >- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); >- err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); >- if (err) >- goto out; >- err = amdgpu_ucode_validate(adev->gfx.mec_fw); >- if (err) >- goto out; >- cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; >- adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); >- adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); >- >- >- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); >- err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); >- if (!err) { >- err = amdgpu_ucode_validate(adev->gfx.mec2_fw); >- if (err) >- goto out; >- cp_hdr = (const struct gfx_firmware_header_v1_0 *) >- adev->gfx.mec2_fw->data; >- adev->gfx.mec2_fw_version = >- le32_to_cpu(cp_hdr->header.ucode_version); >- adev->gfx.mec2_feature_version = >- le32_to_cpu(cp_hdr->ucode_feature_version); >- } else { >- err = 0; >- adev->gfx.mec2_fw = NULL; >- } >- > if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { >- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; >- info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; >- info->fw = adev->gfx.pfp_fw; >- header = (const struct common_firmware_header *)info->fw->data; >- adev->firmware.fw_size += >- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); >- >- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; >- info->ucode_id = AMDGPU_UCODE_ID_CP_ME; >- info->fw = adev->gfx.me_fw; >- header = (const struct common_firmware_header *)info->fw->data; >- adev->firmware.fw_size += >- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); >- >- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; >- info->ucode_id = AMDGPU_UCODE_ID_CP_CE; >- info->fw = adev->gfx.ce_fw; >- header = (const struct common_firmware_header *)info->fw->data; >- adev->firmware.fw_size += >- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); >- > info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; > info->ucode_id = AMDGPU_UCODE_ID_RLC_G; > info->fw = adev->gfx.rlc_fw; >@@ -840,7 +1247,58 @@ > adev->firmware.fw_size += > ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); > } >+ } > >+out: >+ if (err) { >+ dev_err(adev->dev, >+ "gfx9: Failed to load firmware \"%s\"\n", >+ fw_name); >+ release_firmware(adev->gfx.rlc_fw); >+ adev->gfx.rlc_fw = NULL; >+ } >+ return err; >+} >+ >+static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, >+ const char *chip_name) >+{ >+ char fw_name[30]; >+ int err; >+ struct amdgpu_firmware_info *info = NULL; >+ const struct common_firmware_header *header = NULL; >+ const struct gfx_firmware_header_v1_0 *cp_hdr; >+ >+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); >+ err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); >+ if (err) >+ goto out; >+ err = amdgpu_ucode_validate(adev->gfx.mec_fw); >+ if (err) >+ goto out; >+ cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; >+ adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); >+ adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); >+ >+ >+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); >+ err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); >+ if (!err) { >+ err = amdgpu_ucode_validate(adev->gfx.mec2_fw); >+ if (err) >+ goto out; >+ cp_hdr = (const struct gfx_firmware_header_v1_0 *) >+ adev->gfx.mec2_fw->data; >+ adev->gfx.mec2_fw_version = >+ le32_to_cpu(cp_hdr->header.ucode_version); >+ adev->gfx.mec2_feature_version = >+ le32_to_cpu(cp_hdr->ucode_feature_version); >+ } else { >+ err = 0; >+ adev->gfx.mec2_fw = NULL; >+ } >+ >+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { > info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; > info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; > info->fw = adev->gfx.mec_fw; >@@ -863,13 +1321,18 @@ > cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; > adev->firmware.fw_size += > ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); >- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; >- info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; >- info->fw = adev->gfx.mec2_fw; >- adev->firmware.fw_size += >- ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); >- } > >+ /* TODO: Determine if MEC2 JT FW loading can be removed >+ for all GFX V9 asic and above */ >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; >+ info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; >+ info->fw = adev->gfx.mec2_fw; >+ adev->firmware.fw_size += >+ ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, >+ PAGE_SIZE); >+ } >+ } > } > > out: >@@ -879,14 +1342,6 @@ > dev_err(adev->dev, > "gfx9: Failed to load firmware \"%s\"\n", > fw_name); >- release_firmware(adev->gfx.pfp_fw); >- adev->gfx.pfp_fw = NULL; >- release_firmware(adev->gfx.me_fw); >- adev->gfx.me_fw = NULL; >- release_firmware(adev->gfx.ce_fw); >- adev->gfx.ce_fw = NULL; >- release_firmware(adev->gfx.rlc_fw); >- adev->gfx.rlc_fw = NULL; > release_firmware(adev->gfx.mec_fw); > adev->gfx.mec_fw = NULL; > release_firmware(adev->gfx.mec2_fw); >@@ -895,6 +1350,59 @@ > return err; > } > >+static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) >+{ >+ const char *chip_name; >+ int r; >+ >+ DRM_DEBUG("\n"); >+ >+ switch (adev->asic_type) { >+ case CHIP_VEGA10: >+ chip_name = "vega10"; >+ break; >+ case CHIP_VEGA12: >+ chip_name = "vega12"; >+ break; >+ case CHIP_VEGA20: >+ chip_name = "vega20"; >+ break; >+ case CHIP_RAVEN: >+ if (adev->rev_id >= 8) >+ chip_name = "raven2"; >+ else if (adev->pdev->device == 0x15d8) >+ chip_name = "picasso"; >+ else >+ chip_name = "raven"; >+ break; >+ case CHIP_ARCTURUS: >+ chip_name = "arcturus"; >+ break; >+ case CHIP_RENOIR: >+ chip_name = "renoir"; >+ break; >+ default: >+ BUG(); >+ } >+ >+ /* No CPG in Arcturus */ >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); >+ if (r) >+ return r; >+ } >+ >+ r = gfx_v9_0_init_rlc_microcode(adev, chip_name); >+ if (r) >+ return r; >+ >+ r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); >+ if (r) >+ return r; >+ >+ return r; >+} >+ > static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) > { > u32 count = 0; >@@ -1132,7 +1640,7 @@ > return r; > } > >- if (adev->asic_type == CHIP_RAVEN) { >+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) { > /* TODO: double check the cp_table_size for RV */ > adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ > r = amdgpu_gfx_rlc_init_cpt(adev); >@@ -1142,6 +1650,7 @@ > > switch (adev->asic_type) { > case CHIP_RAVEN: >+ case CHIP_RENOIR: > gfx_v9_0_init_lbpw(adev); > break; > case CHIP_VEGA20: >@@ -1328,7 +1837,9 @@ > .read_wave_data = &gfx_v9_0_read_wave_data, > .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, > .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, >- .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q >+ .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, >+ .ras_error_inject = &gfx_v9_0_ras_error_inject, >+ .query_ras_error_count = &gfx_v9_0_query_ras_error_count > }; > > static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) >@@ -1381,6 +1892,26 @@ > else > gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; > break; >+ case CHIP_ARCTURUS: >+ adev->gfx.config.max_hw_contexts = 8; >+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; >+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100; >+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; >+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; >+ gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); >+ gb_addr_config &= ~0xf3e777ff; >+ gb_addr_config |= 0x22014042; >+ break; >+ case CHIP_RENOIR: >+ adev->gfx.config.max_hw_contexts = 8; >+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; >+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100; >+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; >+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; >+ gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); >+ gb_addr_config &= ~0xf3e777ff; >+ gb_addr_config |= 0x22010042; >+ break; > default: > BUG(); > break; >@@ -1657,6 +2188,8 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: >+ case CHIP_RENOIR: > adev->gfx.mec.num_mec = 2; > break; > default: >@@ -1814,7 +2347,7 @@ > gfx_v9_0_mec_fini(adev); > gfx_v9_0_ngg_fini(adev); > amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); >- if (adev->asic_type == CHIP_RAVEN) { >+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) { > amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, > &adev->gfx.rlc.cp_table_gpu_addr, > (void **)&adev->gfx.rlc.cp_table_ptr); >@@ -1933,6 +2466,24 @@ > } > } > >+static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) >+{ >+ int vmid; >+ >+ /* >+ * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA >+ * access. Compute VMIDs should be enabled by FW for target VMIDs, >+ * the driver can enable them for graphics. VMID0 should maintain >+ * access so that HWS firmware can save/restore entries. >+ */ >+ for (vmid = 1; vmid < 16; vmid++) { >+ WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); >+ WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); >+ WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); >+ WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); >+ } >+} >+ > static void gfx_v9_0_constants_init(struct amdgpu_device *adev) > { > u32 tmp; >@@ -1949,7 +2500,7 @@ > /* XXX SH_MEM regs */ > /* where to put LDS, scratch, GPUVM in FSA64 space */ > mutex_lock(&adev->srbm_mutex); >- for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { >+ for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { > soc15_grbm_select(adev, 0, 0, 0, i); > /* CP and shaders */ > if (i == 0) { >@@ -1977,6 +2528,7 @@ > mutex_unlock(&adev->srbm_mutex); > > gfx_v9_0_init_compute_vmid(adev); >+ gfx_v9_0_init_gds_vmid(adev); > } > > static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) >@@ -2474,6 +3026,7 @@ > > switch (adev->asic_type) { > case CHIP_RAVEN: >+ case CHIP_RENOIR: > if (amdgpu_lbpw == 0) > gfx_v9_0_enable_lbpw(adev, false); > else >@@ -2853,6 +3406,10 @@ > mqd->compute_static_thread_mgmt_se1 = 0xffffffff; > mqd->compute_static_thread_mgmt_se2 = 0xffffffff; > mqd->compute_static_thread_mgmt_se3 = 0xffffffff; >+ mqd->compute_static_thread_mgmt_se4 = 0xffffffff; >+ mqd->compute_static_thread_mgmt_se5 = 0xffffffff; >+ mqd->compute_static_thread_mgmt_se6 = 0xffffffff; >+ mqd->compute_static_thread_mgmt_se7 = 0xffffffff; > mqd->compute_misc_reserved = 0x00000003; > > mqd->dynamic_cu_mask_addr_lo = >@@ -3256,10 +3813,12 @@ > gfx_v9_0_enable_gui_idle_interrupt(adev, false); > > if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { >- /* legacy firmware loading */ >- r = gfx_v9_0_cp_gfx_load_microcode(adev); >- if (r) >- return r; >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ /* legacy firmware loading */ >+ r = gfx_v9_0_cp_gfx_load_microcode(adev); >+ if (r) >+ return r; >+ } > > r = gfx_v9_0_cp_compute_load_microcode(adev); > if (r) >@@ -3270,18 +3829,22 @@ > if (r) > return r; > >- r = gfx_v9_0_cp_gfx_resume(adev); >- if (r) >- return r; >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ r = gfx_v9_0_cp_gfx_resume(adev); >+ if (r) >+ return r; >+ } > > r = gfx_v9_0_kcq_resume(adev); > if (r) > return r; > >- ring = &adev->gfx.gfx_ring[0]; >- r = amdgpu_ring_test_helper(ring); >- if (r) >- return r; >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ ring = &adev->gfx.gfx_ring[0]; >+ r = amdgpu_ring_test_helper(ring); >+ if (r) >+ return r; >+ } > > for (i = 0; i < adev->gfx.num_compute_rings; i++) { > ring = &adev->gfx.compute_ring[i]; >@@ -3295,7 +3858,8 @@ > > static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) > { >- gfx_v9_0_cp_gfx_enable(adev, enable); >+ if (adev->asic_type != CHIP_ARCTURUS) >+ gfx_v9_0_cp_gfx_enable(adev, enable); > gfx_v9_0_cp_compute_enable(adev, enable); > } > >@@ -3304,7 +3868,8 @@ > int r; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >- gfx_v9_0_init_golden_registers(adev); >+ if (!amdgpu_sriov_vf(adev)) >+ gfx_v9_0_init_golden_registers(adev); > > gfx_v9_0_constants_init(adev); > >@@ -3320,9 +3885,11 @@ > if (r) > return r; > >- r = gfx_v9_0_ngg_en(adev); >- if (r) >- return r; >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ r = gfx_v9_0_ngg_en(adev); >+ if (r) >+ return r; >+ } > > return r; > } >@@ -3470,8 +4037,9 @@ > /* stop the rlc */ > adev->gfx.rlc.funcs->stop(adev); > >- /* Disable GFX parsing/prefetching */ >- gfx_v9_0_cp_gfx_enable(adev, false); >+ if (adev->asic_type != CHIP_ARCTURUS) >+ /* Disable GFX parsing/prefetching */ >+ gfx_v9_0_cp_gfx_enable(adev, false); > > /* Disable MEC parsing/prefetching */ > gfx_v9_0_cp_compute_enable(adev, false); >@@ -3814,7 +4382,10 @@ > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >- adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; >+ if (adev->asic_type == CHIP_ARCTURUS) >+ adev->gfx.num_gfx_rings = 0; >+ else >+ adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; > adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; > gfx_v9_0_set_ring_funcs(adev); > gfx_v9_0_set_irq_funcs(adev); >@@ -3825,6 +4396,7 @@ > } > > static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, > struct amdgpu_iv_entry *entry); > > static int gfx_v9_0_ecc_late_init(void *handle) >@@ -3990,6 +4562,9 @@ > { > amdgpu_gfx_rlc_enter_safe_mode(adev); > >+ if (is_support_sw_smu(adev) && !enable) >+ smu_set_gfx_cgpg(&adev->smu, enable); >+ > if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { > gfx_v9_0_enable_gfx_cg_power_gating(adev, true); > if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) >@@ -4101,6 +4676,9 @@ > { > uint32_t data, def; > >+ if (adev->asic_type == CHIP_ARCTURUS) >+ return; >+ > amdgpu_gfx_rlc_enter_safe_mode(adev); > > /* Enable 3D CGCG/CGLS */ >@@ -4166,8 +4744,12 @@ > /* enable cgcg FSM(0x0000363F) */ > def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); > >- data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | >- RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; >+ if (adev->asic_type == CHIP_ARCTURUS) >+ data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | >+ RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; >+ else >+ data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | >+ RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; > if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) > data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | > RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; >@@ -4239,6 +4821,7 @@ > > switch (adev->asic_type) { > case CHIP_RAVEN: >+ case CHIP_RENOIR: > if (!enable) { > amdgpu_gfx_off_ctrl(adev, false); > cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); >@@ -4257,6 +4840,8 @@ > gfx_v9_0_enable_cp_power_gating(adev, false); > > /* update gfx cgpg state */ >+ if (is_support_sw_smu(adev) && enable) >+ smu_set_gfx_cgpg(&adev->smu, enable); > gfx_v9_0_update_gfx_cg_power_gating(adev, enable); > > /* update mgcg state */ >@@ -4293,6 +4878,8 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: >+ case CHIP_RENOIR: > gfx_v9_0_update_gfx_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > break; >@@ -4334,14 +4921,16 @@ > if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) > *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; > >- /* AMD_CG_SUPPORT_GFX_3D_CGCG */ >- data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); >- if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) >- *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; >- >- /* AMD_CG_SUPPORT_GFX_3D_CGLS */ >- if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) >- *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; >+ if (adev->asic_type != CHIP_ARCTURUS) { >+ /* AMD_CG_SUPPORT_GFX_3D_CGCG */ >+ data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); >+ if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) >+ *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; >+ >+ /* AMD_CG_SUPPORT_GFX_3D_CGLS */ >+ if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) >+ *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; >+ } > } > > static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) >@@ -5137,12 +5726,423 @@ > } > > static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, > struct amdgpu_iv_entry *entry) > { > /* TODO ue will trigger an interrupt. */ > kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); >+ if (adev->gfx.funcs->query_ras_error_count) >+ adev->gfx.funcs->query_ras_error_count(adev, err_data); > amdgpu_ras_reset_gpu(adev, 0); >- return AMDGPU_RAS_UE; >+ return AMDGPU_RAS_SUCCESS; >+} >+ >+static const struct { >+ const char *name; >+ uint32_t ip; >+ uint32_t inst; >+ uint32_t seg; >+ uint32_t reg_offset; >+ uint32_t per_se_instance; >+ int32_t num_instance; >+ uint32_t sec_count_mask; >+ uint32_t ded_count_mask; >+} gfx_ras_edc_regs[] = { >+ { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, >+ REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT), >+ REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) }, >+ { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, >+ REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT), >+ REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) }, >+ { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, >+ REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 }, >+ { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, >+ REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 }, >+ { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, >+ REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT), >+ REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) }, >+ { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, >+ REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 }, >+ { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, >+ REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), >+ REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_DED_COUNT) }, >+ { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, >+ REG_FIELD_MASK(CPG_EDC_TAG_CNT, SEC_COUNT), >+ REG_FIELD_MASK(CPG_EDC_TAG_CNT, DED_COUNT) }, >+ { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, >+ REG_FIELD_MASK(DC_EDC_CSINVOC_CNT, COUNT_ME1), 0 }, >+ { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, >+ REG_FIELD_MASK(DC_EDC_RESTORE_CNT, COUNT_ME1), 0 }, >+ { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, >+ REG_FIELD_MASK(DC_EDC_STATE_CNT, COUNT_ME1), 0 }, >+ { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, >+ REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_SEC), >+ REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_DED) }, >+ { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, >+ REG_FIELD_MASK(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 0 }, >+ { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), >+ 0, 1, REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), >+ REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) }, >+ { "GDS_OA_PHY_PHY_CMD_RAM_MEM", >+ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, >+ REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), >+ REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) }, >+ { "GDS_OA_PHY_PHY_DATA_RAM_MEM", >+ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, >+ REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 0 }, >+ { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", >+ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, >+ REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), >+ REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) }, >+ { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", >+ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, >+ REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), >+ REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) }, >+ { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", >+ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, >+ REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), >+ REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) }, >+ { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", >+ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, >+ REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), >+ REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) }, >+ { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 1, 1, >+ REG_FIELD_MASK(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 0 }, >+ { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), >+ REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) }, >+ { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 0 }, >+ { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 0 }, >+ { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 0 }, >+ { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 0 }, >+ { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2, >+ REG_FIELD_MASK(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 0 }, >+ { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2, >+ REG_FIELD_MASK(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 0 }, >+ { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), >+ REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) }, >+ { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), >+ REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) }, >+ { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), >+ REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) }, >+ { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), >+ REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) }, >+ { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), >+ REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) }, >+ { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 0 }, >+ { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 0 }, >+ { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 0 }, >+ { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 0 }, >+ { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 0 }, >+ { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 0 }, >+ { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 0 }, >+ { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16, >+ REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 0 }, >+ { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, >+ 16, REG_FIELD_MASK(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 0 }, >+ { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), >+ 0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), >+ 0 }, >+ { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, >+ 16, REG_FIELD_MASK(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 0 }, >+ { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), >+ 0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), >+ 0 }, >+ { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, >+ 16, REG_FIELD_MASK(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 0 }, >+ { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 72, >+ REG_FIELD_MASK(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 0 }, >+ { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) }, >+ { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) }, >+ { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 0 }, >+ { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 0 }, >+ { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0 }, >+ { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) }, >+ { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), >+ REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) }, >+ { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), >+ REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) }, >+ { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), >+ REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) }, >+ { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(TD_EDC_CNT, CS_FIFO_SED_COUNT), 0 }, >+ { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_SEC_COUNT), >+ REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_DED_COUNT) }, >+ { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_SEC_COUNT), >+ REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_DED_COUNT) }, >+ { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(SQ_EDC_CNT, SGPR_SEC_COUNT), >+ REG_FIELD_MASK(SQ_EDC_CNT, SGPR_DED_COUNT) }, >+ { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_SEC_COUNT), >+ REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_DED_COUNT) }, >+ { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_SEC_COUNT), >+ REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_DED_COUNT) }, >+ { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_SEC_COUNT), >+ REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_DED_COUNT) }, >+ { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, >+ REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_SEC_COUNT), >+ REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_DED_COUNT) }, >+ { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), >+ 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) }, >+ { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) }, >+ { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), >+ 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) }, >+ { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) }, >+ { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), >+ 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) }, >+ { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) }, >+ { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) }, >+ { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) }, >+ { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) }, >+ { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) }, >+ { "SQC_INST_BANKA_UTCL1_MISS_FIFO", >+ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, >+ REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), >+ 0 }, >+ { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 0 }, >+ { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 0 }, >+ { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 0 }, >+ { "SQC_DATA_BANKA_DIRTY_BIT_RAM", >+ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, >+ REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 0 }, >+ { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, >+ REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) }, >+ { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) }, >+ { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) }, >+ { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) }, >+ { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), >+ REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) }, >+ { "SQC_INST_BANKB_UTCL1_MISS_FIFO", >+ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6, >+ REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), >+ 0 }, >+ { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 0 }, >+ { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 0 }, >+ { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, >+ 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 0 }, >+ { "SQC_DATA_BANKB_DIRTY_BIT_RAM", >+ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6, >+ REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 0 }, >+ { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), >+ REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) }, >+ { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), >+ REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) }, >+ { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), >+ REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) }, >+ { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), >+ REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) }, >+ { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), >+ REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) }, >+ { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0 }, >+ { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0 }, >+ { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0 }, >+ { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0 }, >+ { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0 }, >+ { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), >+ REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) }, >+ { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), >+ REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) }, >+ { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), >+ REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) }, >+ { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0 }, >+ { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0 }, >+ { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 0 }, >+ { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 0 }, >+ { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 0 }, >+ { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, >+ REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 0 }, >+}; >+ >+static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, >+ void *inject_if) >+{ >+ struct ras_inject_if *info = (struct ras_inject_if *)inject_if; >+ int ret; >+ struct ta_ras_trigger_error_input block_info = { 0 }; >+ >+ if (adev->asic_type != CHIP_VEGA20) >+ return -EINVAL; >+ >+ if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) >+ return -EINVAL; >+ >+ if (!ras_gfx_subblocks[info->head.sub_block_index].name) >+ return -EPERM; >+ >+ if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & >+ info->head.type)) { >+ DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", >+ ras_gfx_subblocks[info->head.sub_block_index].name, >+ info->head.type); >+ return -EPERM; >+ } >+ >+ if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & >+ info->head.type)) { >+ DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", >+ ras_gfx_subblocks[info->head.sub_block_index].name, >+ info->head.type); >+ return -EPERM; >+ } >+ >+ block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); >+ block_info.sub_block_index = >+ ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; >+ block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); >+ block_info.address = info->address; >+ block_info.value = info->value; >+ >+ mutex_lock(&adev->grbm_idx_mutex); >+ ret = psp_ras_trigger_error(&adev->psp, &block_info); >+ mutex_unlock(&adev->grbm_idx_mutex); >+ >+ return ret; >+} >+ >+static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, >+ void *ras_error_status) >+{ >+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; >+ uint32_t sec_count, ded_count; >+ uint32_t i; >+ uint32_t reg_value; >+ uint32_t se_id, instance_id; >+ >+ if (adev->asic_type != CHIP_VEGA20) >+ return -EINVAL; >+ >+ err_data->ue_count = 0; >+ err_data->ce_count = 0; >+ >+ mutex_lock(&adev->grbm_idx_mutex); >+ for (se_id = 0; se_id < adev->gfx.config.max_shader_engines; se_id++) { >+ for (instance_id = 0; instance_id < 256; instance_id++) { >+ for (i = 0; >+ i < sizeof(gfx_ras_edc_regs) / sizeof(gfx_ras_edc_regs[0]); >+ i++) { >+ if (se_id != 0 && >+ !gfx_ras_edc_regs[i].per_se_instance) >+ continue; >+ if (instance_id >= gfx_ras_edc_regs[i].num_instance) >+ continue; >+ >+ gfx_v9_0_select_se_sh(adev, se_id, 0, >+ instance_id); >+ >+ reg_value = RREG32( >+ adev->reg_offset[gfx_ras_edc_regs[i].ip] >+ [gfx_ras_edc_regs[i].inst] >+ [gfx_ras_edc_regs[i].seg] + >+ gfx_ras_edc_regs[i].reg_offset); >+ sec_count = reg_value & >+ gfx_ras_edc_regs[i].sec_count_mask; >+ ded_count = reg_value & >+ gfx_ras_edc_regs[i].ded_count_mask; >+ if (sec_count) { >+ DRM_INFO( >+ "Instance[%d][%d]: SubBlock %s, SEC %d\n", >+ se_id, instance_id, >+ gfx_ras_edc_regs[i].name, >+ sec_count); >+ err_data->ce_count++; >+ } >+ >+ if (ded_count) { >+ DRM_INFO( >+ "Instance[%d][%d]: SubBlock %s, DED %d\n", >+ se_id, instance_id, >+ gfx_ras_edc_regs[i].name, >+ ded_count); >+ err_data->ue_count++; >+ } >+ } >+ } >+ } >+ gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); >+ mutex_unlock(&adev->grbm_idx_mutex); >+ >+ return 0; > } > > static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev, >@@ -5187,7 +6187,7 @@ > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_GFXHUB, >+ .vmhub = AMDGPU_GFXHUB_0, > .get_rptr = gfx_v9_0_ring_get_rptr_gfx, > .get_wptr = gfx_v9_0_ring_get_wptr_gfx, > .set_wptr = gfx_v9_0_ring_set_wptr_gfx, >@@ -5238,7 +6238,7 @@ > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_GFXHUB, >+ .vmhub = AMDGPU_GFXHUB_0, > .get_rptr = gfx_v9_0_ring_get_rptr_compute, > .get_wptr = gfx_v9_0_ring_get_wptr_compute, > .set_wptr = gfx_v9_0_ring_set_wptr_compute, >@@ -5273,7 +6273,7 @@ > .align_mask = 0xff, > .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_GFXHUB, >+ .vmhub = AMDGPU_GFXHUB_0, > .get_rptr = gfx_v9_0_ring_get_rptr_compute, > .get_wptr = gfx_v9_0_ring_get_wptr_compute, > .set_wptr = gfx_v9_0_ring_set_wptr_compute, >@@ -5353,6 +6353,8 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: >+ case CHIP_RENOIR: > adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; > break; > default: >@@ -5370,6 +6372,7 @@ > adev->gds.gds_size = 0x10000; > break; > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: > adev->gds.gds_size = 0x1000; > break; > default: >@@ -5391,6 +6394,9 @@ > else > adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ > break; >+ case CHIP_ARCTURUS: >+ adev->gds.gds_compute_max_wave_id = 0xfff; >+ break; > default: > /* this really depends on the chip */ > adev->gds.gds_compute_max_wave_id = 0x7ff; >@@ -5435,12 +6441,21 @@ > { > int i, j, k, counter, active_cu_number = 0; > u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; >- unsigned disable_masks[4 * 2]; >+ unsigned disable_masks[4 * 4]; > > if (!adev || !cu_info) > return -EINVAL; > >- amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); >+ /* >+ * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs >+ */ >+ if (adev->gfx.config.max_shader_engines * >+ adev->gfx.config.max_sh_per_se > 16) >+ return -EINVAL; >+ >+ amdgpu_gfx_parse_disable_cu(disable_masks, >+ adev->gfx.config.max_shader_engines, >+ adev->gfx.config.max_sh_per_se); > > mutex_lock(&adev->grbm_idx_mutex); > for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { >@@ -5449,11 +6464,23 @@ > ao_bitmap = 0; > counter = 0; > gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); >- if (i < 4 && j < 2) >- gfx_v9_0_set_user_cu_inactive_bitmap( >- adev, disable_masks[i * 2 + j]); >+ gfx_v9_0_set_user_cu_inactive_bitmap( >+ adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); > bitmap = gfx_v9_0_get_cu_active_bitmap(adev); >- cu_info->bitmap[i][j] = bitmap; >+ >+ /* >+ * The bitmap(and ao_cu_bitmap) in cu_info structure is >+ * 4x4 size array, and it's usually suitable for Vega >+ * ASICs which has 4*2 SE/SH layout. >+ * But for Arcturus, SE/SH layout is changed to 8*1. >+ * To mostly reduce the impact, we make it compatible >+ * with current bitmap array as below: >+ * SE4,SH0 --> bitmap[0][1] >+ * SE5,SH0 --> bitmap[1][1] >+ * SE6,SH0 --> bitmap[2][1] >+ * SE7,SH0 --> bitmap[3][1] >+ */ >+ cu_info->bitmap[i % 4][j + i / 4] = bitmap; > > for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { > if (bitmap & mask) { >@@ -5466,7 +6493,7 @@ > active_cu_number += counter; > if (i < 2 && j < 2) > ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); >- cu_info->ao_cu_bitmap[i][j] = ao_bitmap; >+ cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; > } > } > gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 2019-08-31 15:01:11.848736167 -0500 >@@ -62,7 +62,7 @@ > struct amdgpu_vmhub *hub; > u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i; > >- bits[AMDGPU_GFXHUB] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | >+ bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | > GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | > GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | > GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | >@@ -70,7 +70,7 @@ > GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | > GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; > >- bits[AMDGPU_MMHUB] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | >+ bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | > MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | > MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | > MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | >@@ -81,39 +81,39 @@ > switch (state) { > case AMDGPU_IRQ_STATE_DISABLE: > /* MM HUB */ >- hub = &adev->vmhub[AMDGPU_MMHUB]; >+ hub = &adev->vmhub[AMDGPU_MMHUB_0]; > for (i = 0; i < 16; i++) { > reg = hub->vm_context0_cntl + i; > tmp = RREG32(reg); >- tmp &= ~bits[AMDGPU_MMHUB]; >+ tmp &= ~bits[AMDGPU_MMHUB_0]; > WREG32(reg, tmp); > } > > /* GFX HUB */ >- hub = &adev->vmhub[AMDGPU_GFXHUB]; >+ hub = &adev->vmhub[AMDGPU_GFXHUB_0]; > for (i = 0; i < 16; i++) { > reg = hub->vm_context0_cntl + i; > tmp = RREG32(reg); >- tmp &= ~bits[AMDGPU_GFXHUB]; >+ tmp &= ~bits[AMDGPU_GFXHUB_0]; > WREG32(reg, tmp); > } > break; > case AMDGPU_IRQ_STATE_ENABLE: > /* MM HUB */ >- hub = &adev->vmhub[AMDGPU_MMHUB]; >+ hub = &adev->vmhub[AMDGPU_MMHUB_0]; > for (i = 0; i < 16; i++) { > reg = hub->vm_context0_cntl + i; > tmp = RREG32(reg); >- tmp |= bits[AMDGPU_MMHUB]; >+ tmp |= bits[AMDGPU_MMHUB_0]; > WREG32(reg, tmp); > } > > /* GFX HUB */ >- hub = &adev->vmhub[AMDGPU_GFXHUB]; >+ hub = &adev->vmhub[AMDGPU_GFXHUB_0]; > for (i = 0; i < 16; i++) { > reg = hub->vm_context0_cntl + i; > tmp = RREG32(reg); >- tmp |= bits[AMDGPU_GFXHUB]; >+ tmp |= bits[AMDGPU_GFXHUB_0]; > WREG32(reg, tmp); > } > break; >@@ -136,22 +136,53 @@ > addr |= ((u64)entry->src_data[1] & 0xf) << 44; > > if (!amdgpu_sriov_vf(adev)) { >+ /* >+ * Issue a dummy read to wait for the status register to >+ * be updated to avoid reading an incorrect value due to >+ * the new fast GRBM interface. >+ */ >+ if (entry->vmid_src == AMDGPU_GFXHUB_0) >+ RREG32(hub->vm_l2_pro_fault_status); >+ > status = RREG32(hub->vm_l2_pro_fault_status); > WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); > } > > if (printk_ratelimit()) { >+ struct amdgpu_task_info task_info; >+ >+ memset(&task_info, 0, sizeof(struct amdgpu_task_info)); >+ amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); >+ > dev_err(adev->dev, >- "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", >+ "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " >+ "for process %s pid %d thread %s pid %d)\n", > entry->vmid_src ? "mmhub" : "gfxhub", > entry->src_id, entry->ring_id, entry->vmid, >- entry->pasid); >- dev_err(adev->dev, " at page 0x%016llx from %d\n", >+ entry->pasid, task_info.process_name, task_info.tgid, >+ task_info.task_name, task_info.pid); >+ dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", > addr, entry->client_id); >- if (!amdgpu_sriov_vf(adev)) >+ if (!amdgpu_sriov_vf(adev)) { > dev_err(adev->dev, >- "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", >+ "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", > status); >+ dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", >+ REG_GET_FIELD(status, >+ GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); >+ dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", >+ REG_GET_FIELD(status, >+ GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); >+ dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", >+ REG_GET_FIELD(status, >+ GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); >+ dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", >+ REG_GET_FIELD(status, >+ GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); >+ dev_err(adev->dev, "\t RW: 0x%lx\n", >+ REG_GET_FIELD(status, >+ GCVM_L2_PROTECTION_FAULT_STATUS, RW)); >+ } > } > > return 0; >@@ -206,6 +237,13 @@ > > WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); > >+ /* >+ * Issue a dummy read to wait for the ACK register to be cleared >+ * to avoid a false ACK due to the new fast GRBM interface. >+ */ >+ if (vmhub == AMDGPU_GFXHUB_0) >+ RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); >+ > /* Wait for ACK with a delay.*/ > for (i = 0; i < adev->usec_timeout; i++) { > tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); >@@ -230,8 +268,8 @@ > * > * Flush the TLB for the requested page table. > */ >-static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, >- uint32_t vmid, uint32_t flush_type) >+static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, >+ uint32_t vmhub, uint32_t flush_type) > { > struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; > struct dma_fence *fence; >@@ -244,11 +282,18 @@ > > mutex_lock(&adev->mman.gtt_window_lock); > >- gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0); >+ if (vmhub == AMDGPU_MMHUB_0) { >+ gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); >+ mutex_unlock(&adev->mman.gtt_window_lock); >+ return; >+ } >+ >+ BUG_ON(vmhub != AMDGPU_GFXHUB_0); >+ > if (!adev->mman.buffer_funcs_enabled || > !adev->ib_pool_ready || > adev->in_gpu_reset) { >- gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0); >+ gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); > mutex_unlock(&adev->mman.gtt_window_lock); > return; > } >@@ -313,7 +358,7 @@ > struct amdgpu_device *adev = ring->adev; > uint32_t reg; > >- if (ring->funcs->vmhub == AMDGPU_GFXHUB) >+ if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) > reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; > else > reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; >@@ -524,6 +569,8 @@ > if (amdgpu_gart_size == -1) { > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > default: > adev->gmc.gart_size = 512ULL << 20; > break; >@@ -590,7 +637,6 @@ > static int gmc_v10_0_sw_init(void *handle) > { > int r; >- int dma_bits; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > gfxhub_v2_0_init(adev); >@@ -601,9 +647,12 @@ > adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: >+ adev->num_vmhubs = 2; > /* > * To fulfill 4-level page support, >- * vm size is 256TB (48bit), maximum size of Navi10, >+ * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, > * block size 512 (9bit) > */ > amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); >@@ -637,26 +686,10 @@ > else > adev->gmc.stolen_size = 9 * 1024 *1024; > >- /* >- * Set DMA mask + need_dma32 flags. >- * PCIE - can handle 44-bits. >- * IGP - can handle 44-bits >- * PCI - dma32 for legacy pci gart, 44 bits on navi10 >- */ >- adev->need_dma32 = false; >- dma_bits = adev->need_dma32 ? 32 : 44; >- >- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); > if (r) { >- adev->need_dma32 = true; >- dma_bits = 32; > printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); >- } >- >- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >- if (r) { >- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); >- printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); >+ return r; > } > > r = gmc_v10_0_mc_init(adev); >@@ -680,8 +713,8 @@ > * amdgpu graphics/compute will use VMIDs 1-7 > * amdkfd will use VMIDs 8-15 > */ >- adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; >- adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; >+ adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; >+ adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; > > amdgpu_vm_manager_init(adev); > >@@ -717,6 +750,8 @@ > { > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > break; > default: > break; >@@ -766,7 +801,8 @@ > > gfxhub_v2_0_set_fault_enable_default(adev, value); > mmhub_v2_0_set_fault_enable_default(adev, value); >- gmc_v10_0_flush_gpu_tlb(adev, 0, 0); >+ gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); >+ gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); > > DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", > (unsigned)(adev->gmc.gart_size >> 20), >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 2019-08-31 15:01:11.848736167 -0500 >@@ -362,8 +362,8 @@ > return 0; > } > >-static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, >- uint32_t vmid, uint32_t flush_type) >+static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, >+ uint32_t vmhub, uint32_t flush_type) > { > WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); > } >@@ -571,7 +571,7 @@ > else > gmc_v6_0_set_fault_enable_default(adev, true); > >- gmc_v6_0_flush_gpu_tlb(adev, 0, 0); >+ gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0); > dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", > (unsigned)(adev->gmc.gart_size >> 20), > (unsigned long long)table_addr); >@@ -839,9 +839,10 @@ > static int gmc_v6_0_sw_init(void *handle) > { > int r; >- int dma_bits; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >+ adev->num_vmhubs = 1; >+ > if (adev->flags & AMD_IS_APU) { > adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; > } else { >@@ -862,20 +863,12 @@ > > adev->gmc.mc_mask = 0xffffffffffULL; > >- adev->need_dma32 = false; >- dma_bits = adev->need_dma32 ? 32 : 40; >- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); > if (r) { >- adev->need_dma32 = true; >- dma_bits = 32; > dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); >+ return r; > } >- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >- if (r) { >- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); >- dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n"); >- } >- adev->need_swiotlb = drm_need_swiotlb(dma_bits); >+ adev->need_swiotlb = drm_need_swiotlb(44); > > r = gmc_v6_0_init_microcode(adev); > if (r) { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 2019-08-31 15:01:11.848736167 -0500 >@@ -433,8 +433,8 @@ > * > * Flush the TLB for the requested page table (CIK). > */ >-static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, >- uint32_t vmid, uint32_t flush_type) >+static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, >+ uint32_t vmhub, uint32_t flush_type) > { > /* bits 0-15 are the VM contexts0-15 */ > WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); >@@ -677,7 +677,7 @@ > WREG32(mmCHUB_CONTROL, tmp); > } > >- gmc_v7_0_flush_gpu_tlb(adev, 0, 0); >+ gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0); > DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", > (unsigned)(adev->gmc.gart_size >> 20), > (unsigned long long)table_addr); >@@ -959,9 +959,10 @@ > static int gmc_v7_0_sw_init(void *handle) > { > int r; >- int dma_bits; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >+ adev->num_vmhubs = 1; >+ > if (adev->flags & AMD_IS_APU) { > adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; > } else { >@@ -990,25 +991,12 @@ > */ > adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ > >- /* set DMA mask + need_dma32 flags. >- * PCIE - can handle 40-bits. >- * IGP - can handle 40-bits >- * PCI - dma32 for legacy pci gart, 40 bits on newer asics >- */ >- adev->need_dma32 = false; >- dma_bits = adev->need_dma32 ? 32 : 40; >- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); > if (r) { >- adev->need_dma32 = true; >- dma_bits = 32; > pr_warn("amdgpu: No suitable DMA available\n"); >+ return r; > } >- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >- if (r) { >- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); >- pr_warn("amdgpu: No coherent DMA available\n"); >- } >- adev->need_swiotlb = drm_need_swiotlb(dma_bits); >+ adev->need_swiotlb = drm_need_swiotlb(40); > > r = gmc_v7_0_init_microcode(adev); > if (r) { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 2019-08-31 15:01:11.848736167 -0500 >@@ -635,8 +635,8 @@ > * > * Flush the TLB for the requested page table (VI). > */ >-static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, >- uint32_t vmid, uint32_t flush_type) >+static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, >+ uint32_t vmhub, uint32_t flush_type) > { > /* bits 0-15 are the VM contexts0-15 */ > WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); >@@ -921,7 +921,7 @@ > else > gmc_v8_0_set_fault_enable_default(adev, true); > >- gmc_v8_0_flush_gpu_tlb(adev, 0, 0); >+ gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); > DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", > (unsigned)(adev->gmc.gart_size >> 20), > (unsigned long long)table_addr); >@@ -1079,9 +1079,10 @@ > static int gmc_v8_0_sw_init(void *handle) > { > int r; >- int dma_bits; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >+ adev->num_vmhubs = 1; >+ > if (adev->flags & AMD_IS_APU) { > adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; > } else { >@@ -1116,25 +1117,12 @@ > */ > adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ > >- /* set DMA mask + need_dma32 flags. >- * PCIE - can handle 40-bits. >- * IGP - can handle 40-bits >- * PCI - dma32 for legacy pci gart, 40 bits on newer asics >- */ >- adev->need_dma32 = false; >- dma_bits = adev->need_dma32 ? 32 : 40; >- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); > if (r) { >- adev->need_dma32 = true; >- dma_bits = 32; > pr_warn("amdgpu: No suitable DMA available\n"); >+ return r; > } >- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >- if (r) { >- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); >- pr_warn("amdgpu: No coherent DMA available\n"); >- } >- adev->need_swiotlb = drm_need_swiotlb(dma_bits); >+ adev->need_swiotlb = drm_need_swiotlb(40); > > r = gmc_v8_0_init_microcode(adev); > if (r) { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 2019-08-31 15:01:11.848736167 -0500 >@@ -47,7 +47,10 @@ > > #include "gfxhub_v1_0.h" > #include "mmhub_v1_0.h" >+#include "athub_v1_0.h" > #include "gfxhub_v1_1.h" >+#include "mmhub_v9_4.h" >+#include "umc_v6_1.h" > > #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" > >@@ -241,18 +244,30 @@ > } > > static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, > struct amdgpu_iv_entry *entry) > { > kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); >- amdgpu_ras_reset_gpu(adev, 0); >- return AMDGPU_RAS_UE; >+ if (adev->umc.funcs->query_ras_error_count) >+ adev->umc.funcs->query_ras_error_count(adev, err_data); >+ /* umc query_ras_error_address is also responsible for clearing >+ * error status >+ */ >+ if (adev->umc.funcs->query_ras_error_address) >+ adev->umc.funcs->query_ras_error_address(adev, err_data); >+ >+ /* only uncorrectable error needs gpu reset */ >+ if (err_data->ue_count) >+ amdgpu_ras_reset_gpu(adev, 0); >+ >+ return AMDGPU_RAS_SUCCESS; > } > > static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, > struct amdgpu_irq_src *source, > struct amdgpu_iv_entry *entry) > { >- struct ras_common_if *ras_if = adev->gmc.ras_if; >+ struct ras_common_if *ras_if = adev->gmc.umc_ras_if; > struct ras_dispatch_if ih_data = { > .entry = entry, > }; >@@ -284,7 +299,7 @@ > > switch (state) { > case AMDGPU_IRQ_STATE_DISABLE: >- for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { >+ for (j = 0; j < adev->num_vmhubs; j++) { > hub = &adev->vmhub[j]; > for (i = 0; i < 16; i++) { > reg = hub->vm_context0_cntl + i; >@@ -295,7 +310,7 @@ > } > break; > case AMDGPU_IRQ_STATE_ENABLE: >- for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { >+ for (j = 0; j < adev->num_vmhubs; j++) { > hub = &adev->vmhub[j]; > for (i = 0; i < 16; i++) { > reg = hub->vm_context0_cntl + i; >@@ -315,10 +330,11 @@ > struct amdgpu_irq_src *source, > struct amdgpu_iv_entry *entry) > { >- struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; >+ struct amdgpu_vmhub *hub; > bool retry_fault = !!(entry->src_data[1] & 0x80); > uint32_t status = 0; > u64 addr; >+ char hub_name[10]; > > addr = (u64)entry->src_data[0] << 12; > addr |= ((u64)entry->src_data[1] & 0xf) << 44; >@@ -327,8 +343,27 @@ > entry->timestamp)) > return 1; /* This also prevents sending it to KFD */ > >+ if (entry->client_id == SOC15_IH_CLIENTID_VMC) { >+ snprintf(hub_name, sizeof(hub_name), "mmhub0"); >+ hub = &adev->vmhub[AMDGPU_MMHUB_0]; >+ } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { >+ snprintf(hub_name, sizeof(hub_name), "mmhub1"); >+ hub = &adev->vmhub[AMDGPU_MMHUB_1]; >+ } else { >+ snprintf(hub_name, sizeof(hub_name), "gfxhub0"); >+ hub = &adev->vmhub[AMDGPU_GFXHUB_0]; >+ } >+ > /* If it's the first fault for this address, process it normally */ > if (!amdgpu_sriov_vf(adev)) { >+ /* >+ * Issue a dummy read to wait for the status register to >+ * be updated to avoid reading an incorrect value due to >+ * the new fast GRBM interface. >+ */ >+ if (entry->vmid_src == AMDGPU_GFXHUB_0) >+ RREG32(hub->vm_l2_pro_fault_status); >+ > status = RREG32(hub->vm_l2_pro_fault_status); > WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); > } >@@ -342,17 +377,33 @@ > dev_err(adev->dev, > "[%s] %s page fault (src_id:%u ring:%u vmid:%u " > "pasid:%u, for process %s pid %d thread %s pid %d)\n", >- entry->vmid_src ? "mmhub" : "gfxhub", >- retry_fault ? "retry" : "no-retry", >+ hub_name, retry_fault ? "retry" : "no-retry", > entry->src_id, entry->ring_id, entry->vmid, > entry->pasid, task_info.process_name, task_info.tgid, > task_info.task_name, task_info.pid); >- dev_err(adev->dev, " in page starting at address 0x%016llx from %d\n", >+ dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", > addr, entry->client_id); >- if (!amdgpu_sriov_vf(adev)) >+ if (!amdgpu_sriov_vf(adev)) { > dev_err(adev->dev, > "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", > status); >+ dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", >+ REG_GET_FIELD(status, >+ VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); >+ dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", >+ REG_GET_FIELD(status, >+ VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); >+ dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", >+ REG_GET_FIELD(status, >+ VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); >+ dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", >+ REG_GET_FIELD(status, >+ VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); >+ dev_err(adev->dev, "\t RW: 0x%lx\n", >+ REG_GET_FIELD(status, >+ VM_L2_PROTECTION_FAULT_STATUS, RW)); >+ >+ } > } > > return 0; >@@ -413,44 +464,53 @@ > * > * Flush the TLB for the requested page table using certain type. > */ >-static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, >- uint32_t vmid, uint32_t flush_type) >+static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, >+ uint32_t vmhub, uint32_t flush_type) > { > const unsigned eng = 17; >- unsigned i, j; >+ u32 j, tmp; >+ struct amdgpu_vmhub *hub; > >- for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { >- struct amdgpu_vmhub *hub = &adev->vmhub[i]; >- u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); >+ BUG_ON(vmhub >= adev->num_vmhubs); > >- /* This is necessary for a HW workaround under SRIOV as well >- * as GFXOFF under bare metal >- */ >- if (adev->gfx.kiq.ring.sched.ready && >- (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && >- !adev->in_gpu_reset) { >- uint32_t req = hub->vm_inv_eng0_req + eng; >- uint32_t ack = hub->vm_inv_eng0_ack + eng; >- >- amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, >- 1 << vmid); >- continue; >- } >+ hub = &adev->vmhub[vmhub]; >+ tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); > >- spin_lock(&adev->gmc.invalidate_lock); >- WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); >- for (j = 0; j < adev->usec_timeout; j++) { >- tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); >- if (tmp & (1 << vmid)) >- break; >- udelay(1); >- } >- spin_unlock(&adev->gmc.invalidate_lock); >- if (j < adev->usec_timeout) >- continue; >+ /* This is necessary for a HW workaround under SRIOV as well >+ * as GFXOFF under bare metal >+ */ >+ if (adev->gfx.kiq.ring.sched.ready && >+ (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && >+ !adev->in_gpu_reset) { >+ uint32_t req = hub->vm_inv_eng0_req + eng; >+ uint32_t ack = hub->vm_inv_eng0_ack + eng; > >- DRM_ERROR("Timeout waiting for VM flush ACK!\n"); >+ amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, >+ 1 << vmid); >+ return; > } >+ >+ spin_lock(&adev->gmc.invalidate_lock); >+ WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); >+ >+ /* >+ * Issue a dummy read to wait for the ACK register to be cleared >+ * to avoid a false ACK due to the new fast GRBM interface. >+ */ >+ if (vmhub == AMDGPU_GFXHUB_0) >+ RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); >+ >+ for (j = 0; j < adev->usec_timeout; j++) { >+ tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); >+ if (tmp & (1 << vmid)) >+ break; >+ udelay(1); >+ } >+ spin_unlock(&adev->gmc.invalidate_lock); >+ if (j < adev->usec_timeout) >+ return; >+ >+ DRM_ERROR("Timeout waiting for VM flush ACK!\n"); > } > > static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, >@@ -480,7 +540,11 @@ > struct amdgpu_device *adev = ring->adev; > uint32_t reg; > >- if (ring->funcs->vmhub == AMDGPU_GFXHUB) >+ /* Do nothing because there's no lut register for mmhub1. */ >+ if (ring->funcs->vmhub == AMDGPU_MMHUB_1) >+ return; >+ >+ if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) > reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; > else > reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; >@@ -597,12 +661,41 @@ > adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; > } > >+static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) >+{ >+ switch (adev->asic_type) { >+ case CHIP_VEGA20: >+ adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; >+ adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; >+ adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; >+ adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; >+ adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; >+ adev->umc.funcs = &umc_v6_1_funcs; >+ break; >+ default: >+ break; >+ } >+} >+ >+static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) >+{ >+ switch (adev->asic_type) { >+ case CHIP_VEGA20: >+ adev->mmhub_funcs = &mmhub_v1_0_funcs; >+ break; >+ default: >+ break; >+ } >+} >+ > static int gmc_v9_0_early_init(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > gmc_v9_0_set_gmc_funcs(adev); > gmc_v9_0_set_irq_funcs(adev); >+ gmc_v9_0_set_umc_funcs(adev); >+ gmc_v9_0_set_mmhub_funcs(adev); > > adev->gmc.shared_aperture_start = 0x2000000000000000ULL; > adev->gmc.shared_aperture_end = >@@ -629,6 +722,8 @@ > switch (adev->asic_type) { > case CHIP_VEGA10: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: >+ case CHIP_RENOIR: > return true; > case CHIP_VEGA12: > case CHIP_VEGA20: >@@ -641,7 +736,8 @@ > { > struct amdgpu_ring *ring; > unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = >- {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP}; >+ {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, >+ GFXHUB_FREE_VM_INV_ENGS_BITMAP}; > unsigned i; > unsigned vmhub, inv_eng; > >@@ -666,29 +762,28 @@ > return 0; > } > >-static int gmc_v9_0_ecc_late_init(void *handle) >+static int gmc_v9_0_ecc_ras_block_late_init(void *handle, >+ struct ras_fs_if *fs_info, struct ras_common_if *ras_block) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; >- struct ras_common_if **ras_if = &adev->gmc.ras_if; >+ struct ras_common_if **ras_if = NULL; > struct ras_ih_if ih_info = { > .cb = gmc_v9_0_process_ras_data_cb, > }; >- struct ras_fs_if fs_info = { >- .sysfs_name = "umc_err_count", >- .debugfs_name = "umc_err_inject", >- }; >- struct ras_common_if ras_block = { >- .block = AMDGPU_RAS_BLOCK__UMC, >- .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, >- .sub_block_index = 0, >- .name = "umc", >- }; > int r; > >- if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { >- amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); >+ if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) >+ ras_if = &adev->gmc.umc_ras_if; >+ else if (ras_block->block == AMDGPU_RAS_BLOCK__MMHUB) >+ ras_if = &adev->gmc.mmhub_ras_if; >+ else >+ BUG(); >+ >+ if (!amdgpu_ras_is_supported(adev, ras_block->block)) { >+ amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); > return 0; > } >+ > /* handle resume path. */ > if (*ras_if) { > /* resend ras TA enable cmd during resume. >@@ -700,7 +795,7 @@ > if (r == -EAGAIN) { > /* request a gpu reset. will run again. */ > amdgpu_ras_request_reset_on_boot(adev, >- AMDGPU_RAS_BLOCK__UMC); >+ ras_block->block); > return 0; > } > /* fail to enable ras, cleanup all. */ >@@ -714,41 +809,46 @@ > if (!*ras_if) > return -ENOMEM; > >- **ras_if = ras_block; >+ **ras_if = *ras_block; > > r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); > if (r) { > if (r == -EAGAIN) { > amdgpu_ras_request_reset_on_boot(adev, >- AMDGPU_RAS_BLOCK__UMC); >+ ras_block->block); > r = 0; > } > goto feature; > } > > ih_info.head = **ras_if; >- fs_info.head = **ras_if; >+ fs_info->head = **ras_if; > >- r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); >- if (r) >- goto interrupt; >+ if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) { >+ r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); >+ if (r) >+ goto interrupt; >+ } > >- amdgpu_ras_debugfs_create(adev, &fs_info); >+ amdgpu_ras_debugfs_create(adev, fs_info); > >- r = amdgpu_ras_sysfs_create(adev, &fs_info); >+ r = amdgpu_ras_sysfs_create(adev, fs_info); > if (r) > goto sysfs; > resume: >- r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); >- if (r) >- goto irq; >+ if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) { >+ r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); >+ if (r) >+ goto irq; >+ } > > return 0; > irq: > amdgpu_ras_sysfs_remove(adev, *ras_if); > sysfs: > amdgpu_ras_debugfs_remove(adev, *ras_if); >- amdgpu_ras_interrupt_remove_handler(adev, &ih_info); >+ if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) >+ amdgpu_ras_interrupt_remove_handler(adev, &ih_info); > interrupt: > amdgpu_ras_feature_enable(adev, *ras_if, 0); > feature: >@@ -757,6 +857,40 @@ > return r; > } > >+static int gmc_v9_0_ecc_late_init(void *handle) >+{ >+ int r; >+ >+ struct ras_fs_if umc_fs_info = { >+ .sysfs_name = "umc_err_count", >+ .debugfs_name = "umc_err_inject", >+ }; >+ struct ras_common_if umc_ras_block = { >+ .block = AMDGPU_RAS_BLOCK__UMC, >+ .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, >+ .sub_block_index = 0, >+ .name = "umc", >+ }; >+ struct ras_fs_if mmhub_fs_info = { >+ .sysfs_name = "mmhub_err_count", >+ .debugfs_name = "mmhub_err_inject", >+ }; >+ struct ras_common_if mmhub_ras_block = { >+ .block = AMDGPU_RAS_BLOCK__MMHUB, >+ .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, >+ .sub_block_index = 0, >+ .name = "mmhub", >+ }; >+ >+ r = gmc_v9_0_ecc_ras_block_late_init(handle, >+ &umc_fs_info, &umc_ras_block); >+ if (r) >+ return r; >+ >+ r = gmc_v9_0_ecc_ras_block_late_init(handle, >+ &mmhub_fs_info, &mmhub_ras_block); >+ return r; >+} > > static int gmc_v9_0_late_init(void *handle) > { >@@ -806,14 +940,17 @@ > struct amdgpu_gmc *mc) > { > u64 base = 0; >- if (!amdgpu_sriov_vf(adev)) >+ >+ if (adev->asic_type == CHIP_ARCTURUS) >+ base = mmhub_v9_4_get_fb_location(adev); >+ else if (!amdgpu_sriov_vf(adev)) > base = mmhub_v1_0_get_fb_location(adev); >+ > /* add the xgmi offset of the physical node */ > base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; > amdgpu_gmc_vram_location(adev, mc, base); > amdgpu_gmc_gart_location(adev, mc); >- if (!amdgpu_sriov_vf(adev)) >- amdgpu_gmc_agp_location(adev, mc); >+ amdgpu_gmc_agp_location(adev, mc); > /* base offset of vram pages */ > adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); > >@@ -887,10 +1024,12 @@ > case CHIP_VEGA10: /* all engines support GPUVM */ > case CHIP_VEGA12: /* all engines support GPUVM */ > case CHIP_VEGA20: >+ case CHIP_ARCTURUS: > default: > adev->gmc.gart_size = 512ULL << 20; > break; > case CHIP_RAVEN: /* DCE SG support */ >+ case CHIP_RENOIR: > adev->gmc.gart_size = 1024ULL << 20; > break; > } >@@ -923,7 +1062,7 @@ > > static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) > { >- u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); >+ u32 d1vga_control; > unsigned size; > > /* >@@ -933,6 +1072,7 @@ > if (gmc_v9_0_keep_stolen_memory(adev)) > return 9 * 1024 * 1024; > >+ d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); > if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { > size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ > } else { >@@ -940,6 +1080,7 @@ > > switch (adev->asic_type) { > case CHIP_RAVEN: >+ case CHIP_RENOIR: > viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); > size = (REG_GET_FIELD(viewport, > HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * >@@ -968,17 +1109,21 @@ > static int gmc_v9_0_sw_init(void *handle) > { > int r; >- int dma_bits; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > gfxhub_v1_0_init(adev); >- mmhub_v1_0_init(adev); >+ if (adev->asic_type == CHIP_ARCTURUS) >+ mmhub_v9_4_init(adev); >+ else >+ mmhub_v1_0_init(adev); > > spin_lock_init(&adev->gmc.invalidate_lock); > > adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); > switch (adev->asic_type) { > case CHIP_RAVEN: >+ adev->num_vmhubs = 2; >+ > if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { > amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); > } else { >@@ -991,6 +1136,10 @@ > case CHIP_VEGA10: > case CHIP_VEGA12: > case CHIP_VEGA20: >+ case CHIP_RENOIR: >+ adev->num_vmhubs = 2; >+ >+ > /* > * To fulfill 4-level page support, > * vm size is 256TB (48bit), maximum size of Vega10, >@@ -1002,6 +1151,12 @@ > else > amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); > break; >+ case CHIP_ARCTURUS: >+ adev->num_vmhubs = 3; >+ >+ /* Keep the vm size same with Vega20 */ >+ amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); >+ break; > default: > break; > } >@@ -1012,6 +1167,13 @@ > if (r) > return r; > >+ if (adev->asic_type == CHIP_ARCTURUS) { >+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, >+ &adev->gmc.vm_fault); >+ if (r) >+ return r; >+ } >+ > r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, > &adev->gmc.vm_fault); > >@@ -1030,25 +1192,12 @@ > */ > adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ > >- /* set DMA mask + need_dma32 flags. >- * PCIE - can handle 44-bits. >- * IGP - can handle 44-bits >- * PCI - dma32 for legacy pci gart, 44 bits on vega10 >- */ >- adev->need_dma32 = false; >- dma_bits = adev->need_dma32 ? 32 : 44; >- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); > if (r) { >- adev->need_dma32 = true; >- dma_bits = 32; > printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); >+ return r; > } >- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); >- if (r) { >- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); >- printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); >- } >- adev->need_swiotlb = drm_need_swiotlb(dma_bits); >+ adev->need_swiotlb = drm_need_swiotlb(44); > > if (adev->gmc.xgmi.supported) { > r = gfxhub_v1_1_get_xgmi_info(adev); >@@ -1077,8 +1226,9 @@ > * amdgpu graphics/compute will use VMIDs 1-7 > * amdkfd will use VMIDs 8-15 > */ >- adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; >- adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; >+ adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; >+ adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; >+ adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; > > amdgpu_vm_manager_init(adev); > >@@ -1088,28 +1238,40 @@ > static int gmc_v9_0_sw_fini(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ void *stolen_vga_buf; > > if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && >- adev->gmc.ras_if) { >- struct ras_common_if *ras_if = adev->gmc.ras_if; >+ adev->gmc.umc_ras_if) { >+ struct ras_common_if *ras_if = adev->gmc.umc_ras_if; > struct ras_ih_if ih_info = { > .head = *ras_if, > }; > >- /*remove fs first*/ >+ /* remove fs first */ > amdgpu_ras_debugfs_remove(adev, ras_if); > amdgpu_ras_sysfs_remove(adev, ras_if); >- /*remove the IH*/ >+ /* remove the IH */ > amdgpu_ras_interrupt_remove_handler(adev, &ih_info); > amdgpu_ras_feature_enable(adev, ras_if, 0); > kfree(ras_if); > } > >+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) && >+ adev->gmc.mmhub_ras_if) { >+ struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if; >+ >+ /* remove fs and disable ras feature */ >+ amdgpu_ras_debugfs_remove(adev, ras_if); >+ amdgpu_ras_sysfs_remove(adev, ras_if); >+ amdgpu_ras_feature_enable(adev, ras_if, 0); >+ kfree(ras_if); >+ } >+ > amdgpu_gem_force_release(adev); > amdgpu_vm_manager_fini(adev); > > if (gmc_v9_0_keep_stolen_memory(adev)) >- amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); >+ amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); > > amdgpu_gart_table_vram_free(adev); > amdgpu_bo_fini(adev); >@@ -1123,7 +1285,7 @@ > > switch (adev->asic_type) { > case CHIP_VEGA10: >- if (amdgpu_virt_support_skip_setting(adev)) >+ if (amdgpu_sriov_vf(adev)) > break; > /* fall through */ > case CHIP_VEGA20: >@@ -1137,6 +1299,7 @@ > case CHIP_VEGA12: > break; > case CHIP_RAVEN: >+ /* TODO for renoir */ > soc15_program_register_sequence(adev, > golden_settings_athub_1_0_0, > ARRAY_SIZE(golden_settings_athub_1_0_0)); >@@ -1153,7 +1316,7 @@ > */ > static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) > { >- int r; >+ int r, i; > bool value; > u32 tmp; > >@@ -1171,6 +1334,7 @@ > > switch (adev->asic_type) { > case CHIP_RAVEN: >+ /* TODO for renoir */ > mmhub_v1_0_update_power_gating(adev, true); > break; > default: >@@ -1181,7 +1345,10 @@ > if (r) > return r; > >- r = mmhub_v1_0_gart_enable(adev); >+ if (adev->asic_type == CHIP_ARCTURUS) >+ r = mmhub_v9_4_gart_enable(adev); >+ else >+ r = mmhub_v1_0_gart_enable(adev); > if (r) > return r; > >@@ -1202,8 +1369,13 @@ > value = true; > > gfxhub_v1_0_set_fault_enable_default(adev, value); >- mmhub_v1_0_set_fault_enable_default(adev, value); >- gmc_v9_0_flush_gpu_tlb(adev, 0, 0); >+ if (adev->asic_type == CHIP_ARCTURUS) >+ mmhub_v9_4_set_fault_enable_default(adev, value); >+ else >+ mmhub_v1_0_set_fault_enable_default(adev, value); >+ >+ for (i = 0; i < adev->num_vmhubs; ++i) >+ gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); > > DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", > (unsigned)(adev->gmc.gart_size >> 20), >@@ -1243,7 +1415,10 @@ > static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) > { > gfxhub_v1_0_gart_disable(adev); >- mmhub_v1_0_gart_disable(adev); >+ if (adev->asic_type == CHIP_ARCTURUS) >+ mmhub_v9_4_gart_disable(adev); >+ else >+ mmhub_v1_0_gart_disable(adev); > amdgpu_gart_table_vram_unpin(adev); > } > >@@ -1308,14 +1483,26 @@ > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >- return mmhub_v1_0_set_clockgating(adev, state); >+ if (adev->asic_type == CHIP_ARCTURUS) >+ mmhub_v9_4_set_clockgating(adev, state); >+ else >+ mmhub_v1_0_set_clockgating(adev, state); >+ >+ athub_v1_0_set_clockgating(adev, state); >+ >+ return 0; > } > > static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >- mmhub_v1_0_get_clockgating(adev, flags); >+ if (adev->asic_type == CHIP_ARCTURUS) >+ mmhub_v9_4_get_clockgating(adev, flags); >+ else >+ mmhub_v1_0_get_clockgating(adev, flags); >+ >+ athub_v1_0_get_clockgating(adev, flags); > } > > static int gmc_v9_0_set_powergating_state(void *handle, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h 2019-08-31 15:01:11.848736167 -0500 >@@ -37,4 +37,11 @@ > extern const struct amd_ip_funcs gmc_v9_0_ip_funcs; > extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block; > >+/* amdgpu_amdkfd*.c */ >+void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, >+ uint64_t value); >+void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, >+ uint64_t value); >+void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid, >+ uint32_t vmid, uint64_t value); > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/Makefile 2019-08-31 15:01:11.838736166 -0500 >@@ -54,7 +54,7 @@ > amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \ > amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \ > amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \ >- amdgpu_vm_sdma.o amdgpu_discovery.o >+ amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o > > amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o > >@@ -66,7 +66,8 @@ > > amdgpu-y += \ > vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ >- vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o >+ vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \ >+ arct_reg_init.o navi12_reg_init.o > > # add DF block > amdgpu-y += \ >@@ -77,9 +78,13 @@ > amdgpu-y += \ > gmc_v7_0.o \ > gmc_v8_0.o \ >- gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \ >+ gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \ > gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o > >+# add UMC block >+amdgpu-y += \ >+ umc_v6_1.o >+ > # add IH block > amdgpu-y += \ > amdgpu_irq.o \ >@@ -95,7 +100,8 @@ > amdgpu_psp.o \ > psp_v3_1.o \ > psp_v10_0.o \ >- psp_v11_0.o >+ psp_v11_0.o \ >+ psp_v12_0.o > > # add SMC block > amdgpu-y += \ >@@ -144,10 +150,12 @@ > amdgpu-y += \ > amdgpu_vcn.o \ > vcn_v1_0.o \ >- vcn_v2_0.o >+ vcn_v2_0.o \ >+ vcn_v2_5.o > > # add ATHUB block > amdgpu-y += \ >+ athub_v1_0.o \ > athub_v2_0.o > > # add amdkfd interfaces >@@ -162,6 +170,7 @@ > amdgpu_amdkfd_gpuvm.o \ > amdgpu_amdkfd_gfx_v8.o \ > amdgpu_amdkfd_gfx_v9.o \ >+ amdgpu_amdkfd_arcturus.o \ > amdgpu_amdkfd_gfx_v10.o > > ifneq ($(CONFIG_DRM_AMDGPU_CIK),) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 2019-08-31 15:01:11.848736167 -0500 >@@ -21,13 +21,13 @@ > * > */ > #include "amdgpu.h" >+#include "amdgpu_ras.h" > #include "mmhub_v1_0.h" > > #include "mmhub/mmhub_1_0_offset.h" > #include "mmhub/mmhub_1_0_sh_mask.h" > #include "mmhub/mmhub_1_0_default.h" >-#include "athub/athub_1_0_offset.h" >-#include "athub/athub_1_0_sh_mask.h" >+#include "mmhub/mmhub_9_4_0_offset.h" > #include "vega10_enum.h" > > #include "soc15_common.h" >@@ -35,6 +35,9 @@ > #define mmDAGB0_CNTL_MISC2_RV 0x008f > #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 > >+#define EA_EDC_CNT_MASK 0x3 >+#define EA_EDC_CNT_SHIFT 0x2 >+ > u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) > { > u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); >@@ -111,7 +114,7 @@ > WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, > max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); > >- if (amdgpu_virt_support_skip_setting(adev)) >+ if (amdgpu_sriov_vf(adev)) > return; > > /* Set default page address. */ >@@ -159,7 +162,7 @@ > { > uint32_t tmp; > >- if (amdgpu_virt_support_skip_setting(adev)) >+ if (amdgpu_sriov_vf(adev)) > return; > > /* Setup L2 cache */ >@@ -208,7 +211,7 @@ > > static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) > { >- if (amdgpu_virt_support_skip_setting(adev)) >+ if (amdgpu_sriov_vf(adev)) > return; > > WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, >@@ -348,7 +351,7 @@ > 0); > WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); > >- if (!amdgpu_virt_support_skip_setting(adev)) { >+ if (!amdgpu_sriov_vf(adev)) { > /* Setup L2 cache */ > tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); >@@ -367,7 +370,7 @@ > { > u32 tmp; > >- if (amdgpu_virt_support_skip_setting(adev)) >+ if (amdgpu_sriov_vf(adev)) > return; > > tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); >@@ -407,7 +410,7 @@ > > void mmhub_v1_0_init(struct amdgpu_device *adev) > { >- struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; >+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; > > hub->ctx0_ptb_addr_lo32 = > SOC15_REG_OFFSET(MMHUB, 0, >@@ -491,22 +494,6 @@ > WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); > } > >-static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, >- bool enable) >-{ >- uint32_t def, data; >- >- def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); >- >- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) >- data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; >- else >- data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; >- >- if (def != data) >- WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); >-} >- > static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, > bool enable) > { >@@ -523,23 +510,6 @@ > WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); > } > >-static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, >- bool enable) >-{ >- uint32_t def, data; >- >- def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); >- >- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && >- (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) >- data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; >- else >- data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; >- >- if(def != data) >- WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); >-} >- > int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, > enum amd_clockgating_state state) > { >@@ -551,14 +521,11 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_RENOIR: > mmhub_v1_0_update_medium_grain_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); >- athub_update_medium_grain_clock_gating(adev, >- state == AMD_CG_STATE_GATE ? true : false); > mmhub_v1_0_update_medium_grain_light_sleep(adev, > state == AMD_CG_STATE_GATE ? true : false); >- athub_update_medium_grain_light_sleep(adev, >- state == AMD_CG_STATE_GATE ? true : false); > break; > default: > break; >@@ -569,18 +536,85 @@ > > void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) > { >- int data; >+ int data, data1; > > if (amdgpu_sriov_vf(adev)) > *flags = 0; > >+ data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); >+ >+ data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); >+ > /* AMD_CG_SUPPORT_MC_MGCG */ >- data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); >- if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) >+ if ((data & ATC_L2_MISC_CG__ENABLE_MASK) && >+ !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) > *flags |= AMD_CG_SUPPORT_MC_MGCG; > > /* AMD_CG_SUPPORT_MC_LS */ >- data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); > if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) > *flags |= AMD_CG_SUPPORT_MC_LS; > } >+ >+static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev, >+ void *ras_error_status) >+{ >+ int i; >+ uint32_t ea0_edc_cnt, ea0_edc_cnt2; >+ uint32_t ea1_edc_cnt, ea1_edc_cnt2; >+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; >+ >+ /* EDC CNT will be cleared automatically after read */ >+ ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20); >+ ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20); >+ ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20); >+ ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20); >+ >+ /* error count of each error type is recorded by 2 bits, >+ * ce and ue count in EDC_CNT >+ */ >+ for (i = 0; i < 5; i++) { >+ err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); >+ err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); >+ ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; >+ ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; >+ err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); >+ err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); >+ ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; >+ ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; >+ } >+ /* successive ue count in EDC_CNT */ >+ for (i = 0; i < 5; i++) { >+ err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); >+ err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); >+ ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; >+ ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; >+ } >+ >+ /* ce and ue count in EDC_CNT2 */ >+ for (i = 0; i < 3; i++) { >+ err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); >+ err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); >+ ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; >+ ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; >+ err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); >+ err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); >+ ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; >+ ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; >+ } >+ /* successive ue count in EDC_CNT2 */ >+ for (i = 0; i < 6; i++) { >+ err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); >+ err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); >+ ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; >+ ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; >+ } >+} >+ >+const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = { >+ .query_ras_error_count = mmhub_v1_0_query_ras_error_count, >+}; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h 2019-08-31 15:01:11.849736167 -0500 >@@ -23,6 +23,8 @@ > #ifndef __MMHUB_V1_0_H__ > #define __MMHUB_V1_0_H__ > >+extern const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs; >+ > u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev); > int mmhub_v1_0_gart_enable(struct amdgpu_device *adev); > void mmhub_v1_0_gart_disable(struct amdgpu_device *adev); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 2019-08-31 15:01:11.849736167 -0500 >@@ -126,7 +126,7 @@ > /* XXX for emulation, Refer to closed source code.*/ > tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, > 0); >- tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); >+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); > tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); > tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); > WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); >@@ -324,7 +324,7 @@ > > void mmhub_v2_0_init(struct amdgpu_device *adev) > { >- struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; >+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; > > hub->ctx0_ptb_addr_lo32 = > SOC15_REG_OFFSET(MMHUB, 0, >@@ -406,6 +406,8 @@ > > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > mmhub_v2_0_update_medium_grain_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > mmhub_v2_0_update_medium_grain_light_sleep(adev, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 2019-08-31 15:01:11.849736167 -0500 >@@ -0,0 +1,642 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#include "amdgpu.h" >+#include "mmhub_v9_4.h" >+ >+#include "mmhub/mmhub_9_4_1_offset.h" >+#include "mmhub/mmhub_9_4_1_sh_mask.h" >+#include "mmhub/mmhub_9_4_1_default.h" >+#include "athub/athub_1_0_offset.h" >+#include "athub/athub_1_0_sh_mask.h" >+#include "vega10_enum.h" >+ >+#include "soc15_common.h" >+ >+#define MMHUB_NUM_INSTANCES 2 >+#define MMHUB_INSTANCE_REGISTER_OFFSET 0x3000 >+ >+u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev) >+{ >+ /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */ >+ u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE); >+ u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP); >+ >+ base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; >+ base <<= 24; >+ >+ top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; >+ top <<= 24; >+ >+ adev->gmc.fb_start = base; >+ adev->gmc.fb_end = top; >+ >+ return base; >+} >+ >+void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid, >+ uint32_t vmid, uint64_t value) >+{ >+ /* two registers distance between mmVML2VC0_VM_CONTEXT0_* to >+ * mmVML2VC0_VM_CONTEXT1_* >+ */ >+ int dist = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 >+ - mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; >+ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, >+ dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ lower_32_bits(value)); >+ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, >+ dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ upper_32_bits(value)); >+ >+} >+ >+static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev, >+ int hubid) >+{ >+ uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); >+ >+ mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base); >+ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ (u32)(adev->gmc.gart_start >> 12)); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ (u32)(adev->gmc.gart_start >> 44)); >+ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ (u32)(adev->gmc.gart_end >> 12)); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ (u32)(adev->gmc.gart_end >> 44)); >+} >+ >+static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev, >+ int hubid) >+{ >+ uint64_t value; >+ uint32_t tmp; >+ >+ /* Program the AGP BAR */ >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ adev->gmc.agp_end >> 24); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ adev->gmc.agp_start >> 24); >+ >+ /* Program the system aperture low logical page number. */ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); >+ >+ /* Set default page address. */ >+ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + >+ adev->vm_manager.vram_base_offset; >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ (u32)(value >> 12)); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ (u32)(value >> 44)); >+ >+ /* Program "protection fault". */ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ (u32)(adev->dummy_page_addr >> 12)); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, >+ (u32)((u64)adev->dummy_page_addr >> 44)); >+ >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, >+ ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+} >+ >+static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid) >+{ >+ uint32_t tmp; >+ >+ /* Setup TLB control */ >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET); >+ >+ tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ ENABLE_L1_TLB, 1); >+ tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ SYSTEM_ACCESS_MODE, 3); >+ tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ ENABLE_ADVANCED_DRIVER_MODEL, 1); >+ tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); >+ tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ ECO_BITS, 0); >+ tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ MTYPE, MTYPE_UC);/* XXX for emulation. */ >+ tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ ATC_EN, 1); >+ >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+} >+ >+static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid) >+{ >+ uint32_t tmp; >+ >+ /* Setup L2 cache */ >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, >+ ENABLE_L2_CACHE, 1); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, >+ ENABLE_L2_FRAGMENT_PROCESSING, 1); >+ /* XXX for emulation, Refer to closed source code.*/ >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, >+ L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, >+ PDE_FAULT_CLASSIFICATION, 0); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, >+ CONTEXT1_IDENTITY_ACCESS_MODE, 1); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, >+ IDENTITY_MODE_FRAGMENT_SIZE, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+ >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2, >+ INVALIDATE_ALL_L1_TLBS, 1); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2, >+ INVALIDATE_L2_CACHE, 1); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+ >+ tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT; >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+ >+ tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT; >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4, >+ VMC_TAP_PDE_REQUEST_PHYSICAL, 0); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4, >+ VMC_TAP_PTE_REQUEST_PHYSICAL, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+} >+ >+static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev, >+ int hubid) >+{ >+ uint32_t tmp; >+ >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+} >+ >+static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev, >+ int hubid) >+{ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F); >+ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); >+ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); >+} >+ >+static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid) >+{ >+ uint32_t tmp; >+ int i; >+ >+ for (i = 0; i <= 14; i++) { >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ ENABLE_CONTEXT, 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ PAGE_TABLE_DEPTH, >+ adev->vm_manager.num_level); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, >+ 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ PAGE_TABLE_BLOCK_SIZE, >+ adev->vm_manager.block_size - 9); >+ /* Send no-retry XNACK on fault to suppress VM fault storm. */ >+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, >+ RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i, >+ tmp); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, >+ lower_32_bits(adev->vm_manager.max_pfn - 1)); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, >+ upper_32_bits(adev->vm_manager.max_pfn - 1)); >+ } >+} >+ >+static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev, >+ int hubid) >+{ >+ unsigned i; >+ >+ for (i = 0; i < 18; ++i) { >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i, >+ 0xffffffff); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32, >+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i, >+ 0x1f); >+ } >+} >+ >+int mmhub_v9_4_gart_enable(struct amdgpu_device *adev) >+{ >+ int i; >+ >+ for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { >+ if (amdgpu_sriov_vf(adev)) { >+ /* >+ * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase >+ * they are VF copy registers so vbios post doesn't >+ * program them, for SRIOV driver need to program them >+ */ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET, >+ adev->gmc.vram_start >> 24); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET, >+ adev->gmc.vram_end >> 24); >+ } >+ >+ /* GART Enable. */ >+ mmhub_v9_4_init_gart_aperture_regs(adev, i); >+ mmhub_v9_4_init_system_aperture_regs(adev, i); >+ mmhub_v9_4_init_tlb_regs(adev, i); >+ mmhub_v9_4_init_cache_regs(adev, i); >+ >+ mmhub_v9_4_enable_system_domain(adev, i); >+ mmhub_v9_4_disable_identity_aperture(adev, i); >+ mmhub_v9_4_setup_vmid_config(adev, i); >+ mmhub_v9_4_program_invalidation(adev, i); >+ } >+ >+ return 0; >+} >+ >+void mmhub_v9_4_gart_disable(struct amdgpu_device *adev) >+{ >+ u32 tmp; >+ u32 i, j; >+ >+ for (j = 0; j < MMHUB_NUM_INSTANCES; j++) { >+ /* Disable all tables */ >+ for (i = 0; i < 16; i++) >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_CNTL, >+ j * MMHUB_INSTANCE_REGISTER_OFFSET + >+ i, 0); >+ >+ /* Setup TLB control */ >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ j * MMHUB_INSTANCE_REGISTER_OFFSET); >+ tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ ENABLE_L1_TLB, 0); >+ tmp = REG_SET_FIELD(tmp, >+ VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ ENABLE_ADVANCED_DRIVER_MODEL, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, >+ j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+ >+ /* Setup L2 cache */ >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, >+ j * MMHUB_INSTANCE_REGISTER_OFFSET); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, >+ ENABLE_L2_CACHE, 0); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, >+ j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, >+ j * MMHUB_INSTANCE_REGISTER_OFFSET, 0); >+ } >+} >+ >+/** >+ * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling >+ * >+ * @adev: amdgpu_device pointer >+ * @value: true redirects VM faults to the default page >+ */ >+void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value) >+{ >+ u32 tmp; >+ int i; >+ >+ for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { >+ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, >+ VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ NACK_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ READ_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, >+ value); >+ if (!value) { >+ tmp = REG_SET_FIELD(tmp, >+ VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ CRASH_ON_NO_RETRY_FAULT, 1); >+ tmp = REG_SET_FIELD(tmp, >+ VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ CRASH_ON_RETRY_FAULT, 1); >+ } >+ >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); >+ } >+} >+ >+void mmhub_v9_4_init(struct amdgpu_device *adev) >+{ >+ struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] = >+ {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]}; >+ int i; >+ >+ for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { >+ hub[i]->ctx0_ptb_addr_lo32 = >+ SOC15_REG_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + >+ i * MMHUB_INSTANCE_REGISTER_OFFSET; >+ hub[i]->ctx0_ptb_addr_hi32 = >+ SOC15_REG_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + >+ i * MMHUB_INSTANCE_REGISTER_OFFSET; >+ hub[i]->vm_inv_eng0_req = >+ SOC15_REG_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_INVALIDATE_ENG0_REQ) + >+ i * MMHUB_INSTANCE_REGISTER_OFFSET; >+ hub[i]->vm_inv_eng0_ack = >+ SOC15_REG_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_INVALIDATE_ENG0_ACK) + >+ i * MMHUB_INSTANCE_REGISTER_OFFSET; >+ hub[i]->vm_context0_cntl = >+ SOC15_REG_OFFSET(MMHUB, 0, >+ mmVML2VC0_VM_CONTEXT0_CNTL) + >+ i * MMHUB_INSTANCE_REGISTER_OFFSET; >+ hub[i]->vm_l2_pro_fault_status = >+ SOC15_REG_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) + >+ i * MMHUB_INSTANCE_REGISTER_OFFSET; >+ hub[i]->vm_l2_pro_fault_cntl = >+ SOC15_REG_OFFSET(MMHUB, 0, >+ mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) + >+ i * MMHUB_INSTANCE_REGISTER_OFFSET; >+ } >+} >+ >+static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, >+ bool enable) >+{ >+ uint32_t def, data, def1, data1; >+ int i, j; >+ int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2; >+ >+ for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { >+ def = data = RREG32_SOC15_OFFSET(MMHUB, 0, >+ mmATCL2_0_ATC_L2_MISC_CG, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET); >+ >+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) >+ data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK; >+ else >+ data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK; >+ >+ if (def != data) >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET, data); >+ >+ for (j = 0; j < 5; j++) { >+ def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0, >+ mmDAGB0_CNTL_MISC2, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET + >+ j * dist); >+ if (enable && >+ (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { >+ data1 &= >+ ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); >+ } else { >+ data1 |= >+ (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); >+ } >+ >+ if (def1 != data1) >+ WREG32_SOC15_OFFSET(MMHUB, 0, >+ mmDAGB0_CNTL_MISC2, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET + >+ j * dist, data1); >+ >+ if (i == 1 && j == 3) >+ break; >+ } >+ } >+} >+ >+static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, >+ bool enable) >+{ >+ uint32_t def, data; >+ int i; >+ >+ for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { >+ def = data = RREG32_SOC15_OFFSET(MMHUB, 0, >+ mmATCL2_0_ATC_L2_MISC_CG, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET); >+ >+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) >+ data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; >+ else >+ data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; >+ >+ if (def != data) >+ WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG, >+ i * MMHUB_INSTANCE_REGISTER_OFFSET, data); >+ } >+} >+ >+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev, >+ enum amd_clockgating_state state) >+{ >+ if (amdgpu_sriov_vf(adev)) >+ return 0; >+ >+ switch (adev->asic_type) { >+ case CHIP_ARCTURUS: >+ mmhub_v9_4_update_medium_grain_clock_gating(adev, >+ state == AMD_CG_STATE_GATE ? true : false); >+ mmhub_v9_4_update_medium_grain_light_sleep(adev, >+ state == AMD_CG_STATE_GATE ? true : false); >+ break; >+ default: >+ break; >+ } >+ >+ return 0; >+} >+ >+void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags) >+{ >+ int data, data1; >+ >+ if (amdgpu_sriov_vf(adev)) >+ *flags = 0; >+ >+ /* AMD_CG_SUPPORT_MC_MGCG */ >+ data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); >+ >+ data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); >+ >+ if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) && >+ !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | >+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) >+ *flags |= AMD_CG_SUPPORT_MC_MGCG; >+ >+ /* AMD_CG_SUPPORT_MC_LS */ >+ if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) >+ *flags |= AMD_CG_SUPPORT_MC_LS; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h 2019-08-31 15:01:11.849736167 -0500 >@@ -0,0 +1,36 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#ifndef __MMHUB_V9_4_H__ >+#define __MMHUB_V9_4_H__ >+ >+u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev); >+int mmhub_v9_4_gart_enable(struct amdgpu_device *adev); >+void mmhub_v9_4_gart_disable(struct amdgpu_device *adev); >+void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, >+ bool value); >+void mmhub_v9_4_init(struct amdgpu_device *adev); >+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev, >+ enum amd_clockgating_state state); >+void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 2019-08-31 15:01:11.849736167 -0500 >@@ -449,20 +449,6 @@ > amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); > } > >-static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev) >-{ >- adev->virt.reg_access_mode = AMDGPU_VIRT_REG_ACCESS_LEGACY; >- >- /* Enable L1 security reg access mode by defaul, as non-security VF >- * will no longer be supported. >- */ >- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC; >- >- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH; >- >- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING; >-} >- > const struct amdgpu_virt_ops xgpu_ai_virt_ops = { > .req_full_gpu = xgpu_ai_request_full_gpu_access, > .rel_full_gpu = xgpu_ai_release_full_gpu_access, >@@ -471,5 +457,4 @@ > .trans_msg = xgpu_ai_mailbox_trans_msg, > .get_pp_clk = xgpu_ai_get_pp_clk, > .force_dpm_level = xgpu_ai_force_dpm_level, >- .init_reg_access_mode = xgpu_ai_init_reg_access_mode, > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi10_ih.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi10_ih.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 2019-08-31 15:01:11.849736167 -0500 >@@ -21,7 +21,8 @@ > * > */ > >-#include <drm/drmP.h> >+#include <linux/pci.h> >+ > #include "amdgpu.h" > #include "amdgpu_ih.h" > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 2019-08-31 15:01:11.849736167 -0500 >@@ -29,20 +29,8 @@ > > int navi10_reg_base_init(struct amdgpu_device *adev) > { >- int r, i; >+ int i; > >- if (amdgpu_discovery) { >- r = amdgpu_discovery_reg_base_init(adev); >- if (r) { >- DRM_WARN("failed to init reg base from ip discovery table, " >- "fallback to legacy init method\n"); >- goto legacy_init; >- } >- >- return 0; >- } >- >-legacy_init: > for (i = 0 ; i < MAX_INSTANCE ; ++i) { > adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); > adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 2019-08-31 15:01:11.849736167 -0500 >@@ -0,0 +1,53 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#include "amdgpu.h" >+#include "nv.h" >+ >+#include "soc15_common.h" >+#include "soc15_hw_ip.h" >+#include "navi12_ip_offset.h" >+ >+int navi12_reg_base_init(struct amdgpu_device *adev) >+{ >+ /* HW has more IP blocks, only initialized the blocks needed by driver */ >+ uint32_t i; >+ for (i = 0 ; i < MAX_INSTANCE ; ++i) { >+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); >+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); >+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); >+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); >+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); >+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); >+ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); >+ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); >+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); >+ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); >+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); >+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); >+ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); >+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); >+ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); >+ adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); >+ } >+ return 0; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 2019-08-31 15:01:11.849736167 -0500 >@@ -0,0 +1,54 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#include "amdgpu.h" >+#include "nv.h" >+ >+#include "soc15_common.h" >+#include "soc15_hw_ip.h" >+#include "navi14_ip_offset.h" >+ >+int navi14_reg_base_init(struct amdgpu_device *adev) >+{ >+ int i; >+ >+ for (i = 0 ; i < MAX_INSTANCE ; ++i) { >+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); >+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); >+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); >+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); >+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); >+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); >+ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); >+ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); >+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); >+ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); >+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); >+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); >+ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); >+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); >+ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); >+ adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); >+ } >+ >+ return 0; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 2019-08-31 15:01:11.849736167 -0500 >@@ -92,7 +92,7 @@ > } > > static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, >- int doorbell_index) >+ int doorbell_index, int instance) > { > u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 2019-08-31 15:01:11.849736167 -0500 >@@ -91,6 +91,26 @@ > WREG32(reg, doorbell_range); > } > >+static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, >+ int doorbell_index, int instance) >+{ >+ u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); >+ >+ u32 doorbell_range = RREG32(reg); >+ >+ if (use_doorbell) { >+ doorbell_range = REG_SET_FIELD(doorbell_range, >+ BIF_MMSCH0_DOORBELL_RANGE, OFFSET, >+ doorbell_index); >+ doorbell_range = REG_SET_FIELD(doorbell_range, >+ BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); >+ } else >+ doorbell_range = REG_SET_FIELD(doorbell_range, >+ BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); >+ >+ WREG32(reg, doorbell_range); >+} >+ > static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, > bool enable) > { >@@ -282,6 +302,7 @@ > .hdp_flush = nbio_v7_0_hdp_flush, > .get_memsize = nbio_v7_0_get_memsize, > .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range, >+ .vcn_doorbell_range = nbio_v7_0_vcn_doorbell_range, > .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture, > .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture, > .ih_doorbell_range = nbio_v7_0_ih_doorbell_range, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 2019-08-31 15:01:11.849736167 -0500 >@@ -31,6 +31,25 @@ > > #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c > >+/* >+ * These are nbio v7_4_1 registers mask. Temporarily define these here since >+ * nbio v7_4_1 header is incomplete. >+ */ >+#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L >+#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L >+#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L >+#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L >+#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L >+#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L >+ >+#define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc >+#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 >+//BIF_MMSCH1_DOORBELL_RANGE >+#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 >+#define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 >+#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL >+#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L >+ > static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) > { > WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, >@@ -75,10 +94,24 @@ > static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, > bool use_doorbell, int doorbell_index, int doorbell_size) > { >- u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : >- SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); >+ u32 reg, doorbell_range; >+ >+ if (instance < 2) >+ reg = instance + >+ SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); >+ else >+ /* >+ * These registers address of SDMA2~7 is not consecutive >+ * from SDMA0~1. Need plus 4 dwords offset. >+ * >+ * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 >+ * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 >+ * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 >+ */ >+ reg = instance + 0x4 + >+ SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); > >- u32 doorbell_range = RREG32(reg); >+ doorbell_range = RREG32(reg); > > if (use_doorbell) { > doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); >@@ -89,6 +122,32 @@ > WREG32(reg, doorbell_range); > } > >+static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, >+ int doorbell_index, int instance) >+{ >+ u32 reg; >+ u32 doorbell_range; >+ >+ if (instance) >+ reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); >+ else >+ reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); >+ >+ doorbell_range = RREG32(reg); >+ >+ if (use_doorbell) { >+ doorbell_range = REG_SET_FIELD(doorbell_range, >+ BIF_MMSCH0_DOORBELL_RANGE, OFFSET, >+ doorbell_index); >+ doorbell_range = REG_SET_FIELD(doorbell_range, >+ BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); >+ } else >+ doorbell_range = REG_SET_FIELD(doorbell_range, >+ BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); >+ >+ WREG32(reg, doorbell_range); >+} >+ > static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, > bool enable) > { >@@ -220,6 +279,12 @@ > .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, > .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, > .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, >+ .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, >+ .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, >+ .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, >+ .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, >+ .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, >+ .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, > }; > > static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev) >@@ -261,6 +326,7 @@ > .hdp_flush = nbio_v7_4_hdp_flush, > .get_memsize = nbio_v7_4_get_memsize, > .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, >+ .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, > .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, > .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, > .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nv.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nv.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nv.c 2019-08-31 15:01:12.265736204 -0500 >@@ -23,7 +23,8 @@ > #include <linux/firmware.h> > #include <linux/slab.h> > #include <linux/module.h> >-#include <drm/drmP.h> >+#include <linux/pci.h> >+ > #include "amdgpu.h" > #include "amdgpu_atombios.h" > #include "amdgpu_ih.h" >@@ -289,6 +290,18 @@ > > return ret; > } >+ >+static enum amd_reset_method >+nv_asic_reset_method(struct amdgpu_device *adev) >+{ >+ struct smu_context *smu = &adev->smu; >+ >+ if (smu_baco_is_support(smu)) >+ return AMD_RESET_METHOD_BACO; >+ else >+ return AMD_RESET_METHOD_MODE1; >+} >+ > static int nv_asic_reset(struct amdgpu_device *adev) > { > >@@ -303,10 +316,13 @@ > int ret = 0; > struct smu_context *smu = &adev->smu; > >- if (smu_baco_is_support(smu)) >+ if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { >+ amdgpu_inc_vram_lost(adev); > ret = smu_baco_reset(smu); >- else >+ } else { >+ amdgpu_inc_vram_lost(adev); > ret = nv_asic_mode1_reset(adev); >+ } > > return ret; > } >@@ -363,23 +379,55 @@ > .funcs = &nv_common_ip_funcs, > }; > >-int nv_set_ip_blocks(struct amdgpu_device *adev) >+static int nv_reg_base_init(struct amdgpu_device *adev) > { >- /* Set IP register base before any HW register access */ >+ int r; >+ >+ if (amdgpu_discovery) { >+ r = amdgpu_discovery_reg_base_init(adev); >+ if (r) { >+ DRM_WARN("failed to init reg base from ip discovery table, " >+ "fallback to legacy init method\n"); >+ goto legacy_init; >+ } >+ >+ return 0; >+ } >+ >+legacy_init: > switch (adev->asic_type) { > case CHIP_NAVI10: > navi10_reg_base_init(adev); > break; >+ case CHIP_NAVI14: >+ navi14_reg_base_init(adev); >+ break; >+ case CHIP_NAVI12: >+ navi12_reg_base_init(adev); >+ break; > default: > return -EINVAL; > } > >+ return 0; >+} >+ >+int nv_set_ip_blocks(struct amdgpu_device *adev) >+{ >+ int r; >+ >+ /* Set IP register base before any HW register access */ >+ r = nv_reg_base_init(adev); >+ if (r) >+ return r; >+ > adev->nbio_funcs = &nbio_v2_3_funcs; > > adev->nbio_funcs->detect_hw_virt(adev); > > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: > amdgpu_device_ip_block_add(adev, &nv_common_ip_block); > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); > amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); >@@ -402,6 +450,27 @@ > if (adev->enable_mes) > amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); > break; >+ case CHIP_NAVI12: >+ amdgpu_device_ip_block_add(adev, &nv_common_ip_block); >+ amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); >+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); >+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && >+ is_support_sw_smu(adev)) >+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); >+ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) >+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); >+#if defined(CONFIG_DRM_AMD_DC) >+ else if (amdgpu_device_has_dc_support(adev)) >+ amdgpu_device_ip_block_add(adev, &dm_ip_block); >+#endif >+ amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); >+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && >+ is_support_sw_smu(adev)) >+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); >+ break; > default: > return -EINVAL; > } >@@ -496,6 +565,7 @@ > .read_bios_from_rom = &nv_read_bios_from_rom, > .read_register = &nv_read_register, > .reset = &nv_asic_reset, >+ .reset_method = &nv_asic_reset_method, > .set_vga_state = &nv_vga_set_state, > .get_xclk = &nv_get_xclk, > .set_uvd_clocks = &nv_set_uvd_clocks, >@@ -511,7 +581,6 @@ > > static int nv_common_early_init(void *handle) > { >- bool psp_enabled = false; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > adev->smc_rreg = NULL; >@@ -528,10 +597,6 @@ > > adev->asic_funcs = &nv_asic_funcs; > >- if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && >- (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) >- psp_enabled = true; >- > adev->rev_id = nv_get_rev_id(adev); > adev->external_rev_id = 0xff; > switch (adev->asic_type) { >@@ -555,6 +620,46 @@ > AMD_PG_SUPPORT_ATHUB; > adev->external_rev_id = adev->rev_id + 0x1; > break; >+ case CHIP_NAVI14: >+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | >+ AMD_CG_SUPPORT_GFX_CGCG | >+ AMD_CG_SUPPORT_IH_CG | >+ AMD_CG_SUPPORT_HDP_MGCG | >+ AMD_CG_SUPPORT_HDP_LS | >+ AMD_CG_SUPPORT_SDMA_MGCG | >+ AMD_CG_SUPPORT_SDMA_LS | >+ AMD_CG_SUPPORT_MC_MGCG | >+ AMD_CG_SUPPORT_MC_LS | >+ AMD_CG_SUPPORT_ATHUB_MGCG | >+ AMD_CG_SUPPORT_ATHUB_LS | >+ AMD_CG_SUPPORT_VCN_MGCG | >+ AMD_CG_SUPPORT_BIF_MGCG | >+ AMD_CG_SUPPORT_BIF_LS; >+ adev->pg_flags = AMD_PG_SUPPORT_VCN | >+ AMD_PG_SUPPORT_VCN_DPG; >+ adev->external_rev_id = adev->rev_id + 20; >+ break; >+ case CHIP_NAVI12: >+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | >+ AMD_CG_SUPPORT_GFX_MGLS | >+ AMD_CG_SUPPORT_GFX_CGCG | >+ AMD_CG_SUPPORT_GFX_CP_LS | >+ AMD_CG_SUPPORT_GFX_RLC_LS | >+ AMD_CG_SUPPORT_IH_CG | >+ AMD_CG_SUPPORT_HDP_MGCG | >+ AMD_CG_SUPPORT_HDP_LS | >+ AMD_CG_SUPPORT_SDMA_MGCG | >+ AMD_CG_SUPPORT_SDMA_LS | >+ AMD_CG_SUPPORT_MC_MGCG | >+ AMD_CG_SUPPORT_MC_LS | >+ AMD_CG_SUPPORT_ATHUB_MGCG | >+ AMD_CG_SUPPORT_ATHUB_LS | >+ AMD_CG_SUPPORT_VCN_MGCG; >+ adev->pg_flags = AMD_PG_SUPPORT_VCN | >+ AMD_PG_SUPPORT_VCN_DPG | >+ AMD_PG_SUPPORT_ATHUB; >+ adev->external_rev_id = adev->rev_id + 0xa; >+ break; > default: > /* FIXME: not supported yet */ > return -EINVAL; >@@ -747,6 +852,8 @@ > > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > adev->nbio_funcs->update_medium_grain_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > adev->nbio_funcs->update_medium_grain_light_sleep(adev, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nv.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nv.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nv.h 2019-08-31 15:01:11.849736167 -0500 >@@ -30,4 +30,6 @@ > u32 me, u32 pipe, u32 queue, u32 vmid); > int nv_set_ip_blocks(struct amdgpu_device *adev); > int navi10_reg_base_init(struct amdgpu_device *adev); >+int navi14_reg_base_init(struct amdgpu_device *adev); >+int navi12_reg_base_init(struct amdgpu_device *adev); > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h 2019-08-31 15:01:11.849736167 -0500 >@@ -233,8 +233,15 @@ > GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */ > GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */ > GFX_FW_TYPE_RLX6_DRAM_BOOT = 48, /* RLX6 DRAM BOOT NV */ >- GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV */ >- GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV */ >+ GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */ >+ GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */ >+ GFX_FW_TYPE_DMUB = 51, /* DMUB RN */ >+ GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */ >+ GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */ >+ GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */ >+ GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */ >+ GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */ >+ GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */ > GFX_FW_TYPE_MAX > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 2019-08-31 15:01:11.850736167 -0500 >@@ -190,7 +190,6 @@ > } > > static int psp_v10_0_cmd_submit(struct psp_context *psp, >- struct amdgpu_firmware_info *ucode, > uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, > int index) > { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 2019-08-31 15:01:11.850736167 -0500 >@@ -43,6 +43,12 @@ > MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); > MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); > MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); >+MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); >+MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); > > /* address block */ > #define smnMP1_FIRMWARE_FLAGS 0x3010024 >@@ -60,6 +66,7 @@ > int err = 0; > const struct psp_firmware_header_v1_0 *sos_hdr; > const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; >+ const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; > const struct psp_firmware_header_v1_0 *asd_hdr; > const struct ta_firmware_header_v1_0 *ta_hdr; > >@@ -72,6 +79,15 @@ > case CHIP_NAVI10: > chip_name = "navi10"; > break; >+ case CHIP_NAVI14: >+ chip_name = "navi14"; >+ break; >+ case CHIP_NAVI12: >+ chip_name = "navi12"; >+ break; >+ case CHIP_ARCTURUS: >+ chip_name = "arcturus"; >+ break; > default: > BUG(); > } >@@ -107,6 +123,12 @@ > adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + > le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); > } >+ if (sos_hdr->header.header_version_minor == 2) { >+ sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; >+ adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); >+ adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + >+ le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); >+ } > break; > default: > dev_err(adev->dev, >@@ -158,6 +180,9 @@ > } > break; > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: >+ case CHIP_ARCTURUS: > break; > default: > BUG(); >@@ -473,7 +498,6 @@ > } > > static int psp_v11_0_cmd_submit(struct psp_context *psp, >- struct amdgpu_firmware_info *ucode, > uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, > int index) > { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 2019-08-31 15:01:11.850736167 -0500 >@@ -0,0 +1,565 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ */ >+ >+#include <linux/firmware.h> >+#include <linux/module.h> >+#include "amdgpu.h" >+#include "amdgpu_psp.h" >+#include "amdgpu_ucode.h" >+#include "soc15_common.h" >+#include "psp_v12_0.h" >+ >+#include "mp/mp_12_0_0_offset.h" >+#include "mp/mp_12_0_0_sh_mask.h" >+#include "gc/gc_9_0_offset.h" >+#include "sdma0/sdma0_4_0_offset.h" >+#include "nbio/nbio_7_4_offset.h" >+ >+#include "oss/osssys_4_0_offset.h" >+#include "oss/osssys_4_0_sh_mask.h" >+ >+MODULE_FIRMWARE("amdgpu/renoir_asd.bin"); >+/* address block */ >+#define smnMP1_FIRMWARE_FLAGS 0x3010024 >+ >+static int psp_v12_0_init_microcode(struct psp_context *psp) >+{ >+ struct amdgpu_device *adev = psp->adev; >+ const char *chip_name; >+ char fw_name[30]; >+ int err = 0; >+ const struct psp_firmware_header_v1_0 *asd_hdr; >+ >+ DRM_DEBUG("\n"); >+ >+ switch (adev->asic_type) { >+ case CHIP_RENOIR: >+ chip_name = "renoir"; >+ break; >+ default: >+ BUG(); >+ } >+ >+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); >+ err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); >+ if (err) >+ goto out1; >+ >+ err = amdgpu_ucode_validate(adev->psp.asd_fw); >+ if (err) >+ goto out1; >+ >+ asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; >+ adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); >+ adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); >+ adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); >+ adev->psp.asd_start_addr = (uint8_t *)asd_hdr + >+ le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); >+ >+ return 0; >+ >+out1: >+ release_firmware(adev->psp.asd_fw); >+ adev->psp.asd_fw = NULL; >+ >+ return err; >+} >+ >+static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) >+{ >+ int ret; >+ uint32_t psp_gfxdrv_command_reg = 0; >+ struct amdgpu_device *adev = psp->adev; >+ uint32_t sol_reg; >+ >+ /* Check sOS sign of life register to confirm sys driver and sOS >+ * are already been loaded. >+ */ >+ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); >+ if (sol_reg) { >+ psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); >+ printk("sos fw version = 0x%x.\n", psp->sos_fw_version); >+ return 0; >+ } >+ >+ /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ >+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), >+ 0x80000000, 0x80000000, false); >+ if (ret) >+ return ret; >+ >+ memset(psp->fw_pri_buf, 0, PSP_1_MEG); >+ >+ /* Copy PSP System Driver binary to memory */ >+ memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); >+ >+ /* Provide the sys driver to bootloader */ >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, >+ (uint32_t)(psp->fw_pri_mc_addr >> 20)); >+ psp_gfxdrv_command_reg = 1 << 16; >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, >+ psp_gfxdrv_command_reg); >+ >+ /* there might be handshake issue with hardware which needs delay */ >+ mdelay(20); >+ >+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), >+ 0x80000000, 0x80000000, false); >+ >+ return ret; >+} >+ >+static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) >+{ >+ int ret; >+ unsigned int psp_gfxdrv_command_reg = 0; >+ struct amdgpu_device *adev = psp->adev; >+ uint32_t sol_reg; >+ >+ /* Check sOS sign of life register to confirm sys driver and sOS >+ * are already been loaded. >+ */ >+ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); >+ if (sol_reg) >+ return 0; >+ >+ /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ >+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), >+ 0x80000000, 0x80000000, false); >+ if (ret) >+ return ret; >+ >+ memset(psp->fw_pri_buf, 0, PSP_1_MEG); >+ >+ /* Copy Secure OS binary to PSP memory */ >+ memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); >+ >+ /* Provide the PSP secure OS to bootloader */ >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, >+ (uint32_t)(psp->fw_pri_mc_addr >> 20)); >+ psp_gfxdrv_command_reg = 2 << 16; >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, >+ psp_gfxdrv_command_reg); >+ >+ /* there might be handshake issue with hardware which needs delay */ >+ mdelay(20); >+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), >+ RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), >+ 0, true); >+ >+ return ret; >+} >+ >+static void psp_v12_0_reroute_ih(struct psp_context *psp) >+{ >+ struct amdgpu_device *adev = psp->adev; >+ uint32_t tmp; >+ >+ /* Change IH ring for VMC */ >+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); >+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); >+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); >+ >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); >+ >+ mdelay(20); >+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), >+ 0x80000000, 0x8000FFFF, false); >+ >+ /* Change IH ring for UMC */ >+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); >+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); >+ >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); >+ >+ mdelay(20); >+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), >+ 0x80000000, 0x8000FFFF, false); >+} >+ >+static int psp_v12_0_ring_init(struct psp_context *psp, >+ enum psp_ring_type ring_type) >+{ >+ int ret = 0; >+ struct psp_ring *ring; >+ struct amdgpu_device *adev = psp->adev; >+ >+ psp_v12_0_reroute_ih(psp); >+ >+ ring = &psp->km_ring; >+ >+ ring->ring_type = ring_type; >+ >+ /* allocate 4k Page of Local Frame Buffer memory for ring */ >+ ring->ring_size = 0x1000; >+ ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, >+ AMDGPU_GEM_DOMAIN_VRAM, >+ &adev->firmware.rbuf, >+ &ring->ring_mem_mc_addr, >+ (void **)&ring->ring_mem); >+ if (ret) { >+ ring->ring_size = 0; >+ return ret; >+ } >+ >+ return 0; >+} >+ >+static bool psp_v12_0_support_vmr_ring(struct psp_context *psp) >+{ >+ if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) >+ return true; >+ return false; >+} >+ >+static int psp_v12_0_ring_create(struct psp_context *psp, >+ enum psp_ring_type ring_type) >+{ >+ int ret = 0; >+ unsigned int psp_ring_reg = 0; >+ struct psp_ring *ring = &psp->km_ring; >+ struct amdgpu_device *adev = psp->adev; >+ >+ if (psp_v12_0_support_vmr_ring(psp)) { >+ /* Write low address of the ring to C2PMSG_102 */ >+ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); >+ /* Write high address of the ring to C2PMSG_103 */ >+ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); >+ >+ /* Write the ring initialization command to C2PMSG_101 */ >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, >+ GFX_CTRL_CMD_ID_INIT_GPCOM_RING); >+ >+ /* there might be handshake issue with hardware which needs delay */ >+ mdelay(20); >+ >+ /* Wait for response flag (bit 31) in C2PMSG_101 */ >+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), >+ 0x80000000, 0x8000FFFF, false); >+ >+ } else { >+ /* Write low address of the ring to C2PMSG_69 */ >+ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); >+ /* Write high address of the ring to C2PMSG_70 */ >+ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); >+ /* Write size of ring to C2PMSG_71 */ >+ psp_ring_reg = ring->ring_size; >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); >+ /* Write the ring initialization command to C2PMSG_64 */ >+ psp_ring_reg = ring_type; >+ psp_ring_reg = psp_ring_reg << 16; >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); >+ >+ /* there might be handshake issue with hardware which needs delay */ >+ mdelay(20); >+ >+ /* Wait for response flag (bit 31) in C2PMSG_64 */ >+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), >+ 0x80000000, 0x8000FFFF, false); >+ } >+ >+ return ret; >+} >+ >+static int psp_v12_0_ring_stop(struct psp_context *psp, >+ enum psp_ring_type ring_type) >+{ >+ int ret = 0; >+ struct amdgpu_device *adev = psp->adev; >+ >+ /* Write the ring destroy command*/ >+ if (psp_v12_0_support_vmr_ring(psp)) >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, >+ GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); >+ else >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, >+ GFX_CTRL_CMD_ID_DESTROY_RINGS); >+ >+ /* there might be handshake issue with hardware which needs delay */ >+ mdelay(20); >+ >+ /* Wait for response flag (bit 31) */ >+ if (psp_v12_0_support_vmr_ring(psp)) >+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), >+ 0x80000000, 0x80000000, false); >+ else >+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), >+ 0x80000000, 0x80000000, false); >+ >+ return ret; >+} >+ >+static int psp_v12_0_ring_destroy(struct psp_context *psp, >+ enum psp_ring_type ring_type) >+{ >+ int ret = 0; >+ struct psp_ring *ring = &psp->km_ring; >+ struct amdgpu_device *adev = psp->adev; >+ >+ ret = psp_v12_0_ring_stop(psp, ring_type); >+ if (ret) >+ DRM_ERROR("Fail to stop psp ring\n"); >+ >+ amdgpu_bo_free_kernel(&adev->firmware.rbuf, >+ &ring->ring_mem_mc_addr, >+ (void **)&ring->ring_mem); >+ >+ return ret; >+} >+ >+static int psp_v12_0_cmd_submit(struct psp_context *psp, >+ uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, >+ int index) >+{ >+ unsigned int psp_write_ptr_reg = 0; >+ struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; >+ struct psp_ring *ring = &psp->km_ring; >+ struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; >+ struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + >+ ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; >+ struct amdgpu_device *adev = psp->adev; >+ uint32_t ring_size_dw = ring->ring_size / 4; >+ uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; >+ >+ /* KM (GPCOM) prepare write pointer */ >+ if (psp_v12_0_support_vmr_ring(psp)) >+ psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); >+ else >+ psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); >+ >+ /* Update KM RB frame pointer to new frame */ >+ /* write_frame ptr increments by size of rb_frame in bytes */ >+ /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ >+ if ((psp_write_ptr_reg % ring_size_dw) == 0) >+ write_frame = ring_buffer_start; >+ else >+ write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); >+ /* Check invalid write_frame ptr address */ >+ if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { >+ DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", >+ ring_buffer_start, ring_buffer_end, write_frame); >+ DRM_ERROR("write_frame is pointing to address out of bounds\n"); >+ return -EINVAL; >+ } >+ >+ /* Initialize KM RB frame */ >+ memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); >+ >+ /* Update KM RB frame */ >+ write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); >+ write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); >+ write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); >+ write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); >+ write_frame->fence_value = index; >+ >+ /* Update the write Pointer in DWORDs */ >+ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; >+ if (psp_v12_0_support_vmr_ring(psp)) { >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); >+ } else >+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); >+ >+ return 0; >+} >+ >+static int >+psp_v12_0_sram_map(struct amdgpu_device *adev, >+ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, >+ unsigned int *sram_data_reg_offset, >+ enum AMDGPU_UCODE_ID ucode_id) >+{ >+ int ret = 0; >+ >+ switch (ucode_id) { >+/* TODO: needs to confirm */ >+#if 0 >+ case AMDGPU_UCODE_ID_SMC: >+ *sram_offset = 0; >+ *sram_addr_reg_offset = 0; >+ *sram_data_reg_offset = 0; >+ break; >+#endif >+ >+ case AMDGPU_UCODE_ID_CP_CE: >+ *sram_offset = 0x0; >+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); >+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); >+ break; >+ >+ case AMDGPU_UCODE_ID_CP_PFP: >+ *sram_offset = 0x0; >+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); >+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); >+ break; >+ >+ case AMDGPU_UCODE_ID_CP_ME: >+ *sram_offset = 0x0; >+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); >+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); >+ break; >+ >+ case AMDGPU_UCODE_ID_CP_MEC1: >+ *sram_offset = 0x10000; >+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); >+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); >+ break; >+ >+ case AMDGPU_UCODE_ID_CP_MEC2: >+ *sram_offset = 0x10000; >+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); >+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); >+ break; >+ >+ case AMDGPU_UCODE_ID_RLC_G: >+ *sram_offset = 0x2000; >+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); >+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); >+ break; >+ >+ case AMDGPU_UCODE_ID_SDMA0: >+ *sram_offset = 0x0; >+ *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); >+ *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); >+ break; >+ >+/* TODO: needs to confirm */ >+#if 0 >+ case AMDGPU_UCODE_ID_SDMA1: >+ *sram_offset = ; >+ *sram_addr_reg_offset = ; >+ break; >+ >+ case AMDGPU_UCODE_ID_UVD: >+ *sram_offset = ; >+ *sram_addr_reg_offset = ; >+ break; >+ >+ case AMDGPU_UCODE_ID_VCE: >+ *sram_offset = ; >+ *sram_addr_reg_offset = ; >+ break; >+#endif >+ >+ case AMDGPU_UCODE_ID_MAXIMUM: >+ default: >+ ret = -EINVAL; >+ break; >+ } >+ >+ return ret; >+} >+ >+static bool psp_v12_0_compare_sram_data(struct psp_context *psp, >+ struct amdgpu_firmware_info *ucode, >+ enum AMDGPU_UCODE_ID ucode_type) >+{ >+ int err = 0; >+ unsigned int fw_sram_reg_val = 0; >+ unsigned int fw_sram_addr_reg_offset = 0; >+ unsigned int fw_sram_data_reg_offset = 0; >+ unsigned int ucode_size; >+ uint32_t *ucode_mem = NULL; >+ struct amdgpu_device *adev = psp->adev; >+ >+ err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, >+ &fw_sram_data_reg_offset, ucode_type); >+ if (err) >+ return false; >+ >+ WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); >+ >+ ucode_size = ucode->ucode_size; >+ ucode_mem = (uint32_t *)ucode->kaddr; >+ while (ucode_size) { >+ fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); >+ >+ if (*ucode_mem != fw_sram_reg_val) >+ return false; >+ >+ ucode_mem++; >+ /* 4 bytes */ >+ ucode_size -= 4; >+ } >+ >+ return true; >+} >+ >+static int psp_v12_0_mode1_reset(struct psp_context *psp) >+{ >+ int ret; >+ uint32_t offset; >+ struct amdgpu_device *adev = psp->adev; >+ >+ offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); >+ >+ ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); >+ >+ if (ret) { >+ DRM_INFO("psp is not working correctly before mode1 reset!\n"); >+ return -EINVAL; >+ } >+ >+ /*send the mode 1 reset command*/ >+ WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); >+ >+ msleep(500); >+ >+ offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); >+ >+ ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); >+ >+ if (ret) { >+ DRM_INFO("psp mode 1 reset failed!\n"); >+ return -EINVAL; >+ } >+ >+ DRM_INFO("psp mode1 reset succeed \n"); >+ >+ return 0; >+} >+ >+static const struct psp_funcs psp_v12_0_funcs = { >+ .init_microcode = psp_v12_0_init_microcode, >+ .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv, >+ .bootloader_load_sos = psp_v12_0_bootloader_load_sos, >+ .ring_init = psp_v12_0_ring_init, >+ .ring_create = psp_v12_0_ring_create, >+ .ring_stop = psp_v12_0_ring_stop, >+ .ring_destroy = psp_v12_0_ring_destroy, >+ .cmd_submit = psp_v12_0_cmd_submit, >+ .compare_sram_data = psp_v12_0_compare_sram_data, >+ .mode1_reset = psp_v12_0_mode1_reset, >+}; >+ >+void psp_v12_0_set_psp_funcs(struct psp_context *psp) >+{ >+ psp->funcs = &psp_v12_0_funcs; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h 2019-08-31 15:01:12.265736204 -0500 >@@ -0,0 +1,30 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#ifndef __PSP_V12_0_H__ >+#define __PSP_V12_0_H__ >+ >+#include "amdgpu_psp.h" >+ >+void psp_v12_0_set_psp_funcs(struct psp_context *psp); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 2019-08-31 15:01:11.850736167 -0500 >@@ -411,7 +411,6 @@ > } > > static int psp_v3_1_cmd_submit(struct psp_context *psp, >- struct amdgpu_firmware_info *ucode, > uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, > int index) > { >@@ -636,7 +635,7 @@ > > static bool psp_v3_1_support_vmr_ring(struct psp_context *psp) > { >- if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version >= 0x80455) >+ if (amdgpu_sriov_vf(psp->adev)) > return true; > > return false; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 2019-08-31 15:01:11.850736167 -0500 >@@ -34,6 +34,18 @@ > #include "sdma0/sdma0_4_2_sh_mask.h" > #include "sdma1/sdma1_4_2_offset.h" > #include "sdma1/sdma1_4_2_sh_mask.h" >+#include "sdma2/sdma2_4_2_2_offset.h" >+#include "sdma2/sdma2_4_2_2_sh_mask.h" >+#include "sdma3/sdma3_4_2_2_offset.h" >+#include "sdma3/sdma3_4_2_2_sh_mask.h" >+#include "sdma4/sdma4_4_2_2_offset.h" >+#include "sdma4/sdma4_4_2_2_sh_mask.h" >+#include "sdma5/sdma5_4_2_2_offset.h" >+#include "sdma5/sdma5_4_2_2_sh_mask.h" >+#include "sdma6/sdma6_4_2_2_offset.h" >+#include "sdma6/sdma6_4_2_2_sh_mask.h" >+#include "sdma7/sdma7_4_2_2_offset.h" >+#include "sdma7/sdma7_4_2_2_sh_mask.h" > #include "hdp/hdp_4_0_offset.h" > #include "sdma0/sdma0_4_1_default.h" > >@@ -55,6 +67,8 @@ > MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); > MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); > MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); >+MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); >+MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); > > #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L > #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L >@@ -202,25 +216,132 @@ > SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) > }; > >+static const struct soc15_reg_golden golden_settings_sdma_arct[] = >+{ >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), >+ SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002) >+}; >+ >+static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), >+}; >+ > static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, > u32 instance, u32 offset) > { >- return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : >- (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); >+ switch (instance) { >+ case 0: >+ return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); >+ case 1: >+ return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); >+ case 2: >+ return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); >+ case 3: >+ return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); >+ case 4: >+ return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); >+ case 5: >+ return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); >+ case 6: >+ return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); >+ case 7: >+ return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); >+ default: >+ break; >+ } >+ return 0; >+} >+ >+static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) >+{ >+ switch (seq_num) { >+ case 0: >+ return SOC15_IH_CLIENTID_SDMA0; >+ case 1: >+ return SOC15_IH_CLIENTID_SDMA1; >+ case 2: >+ return SOC15_IH_CLIENTID_SDMA2; >+ case 3: >+ return SOC15_IH_CLIENTID_SDMA3; >+ case 4: >+ return SOC15_IH_CLIENTID_SDMA4; >+ case 5: >+ return SOC15_IH_CLIENTID_SDMA5; >+ case 6: >+ return SOC15_IH_CLIENTID_SDMA6; >+ case 7: >+ return SOC15_IH_CLIENTID_SDMA7; >+ default: >+ break; >+ } >+ return -EINVAL; >+} >+ >+static int sdma_v4_0_irq_id_to_seq(unsigned client_id) >+{ >+ switch (client_id) { >+ case SOC15_IH_CLIENTID_SDMA0: >+ return 0; >+ case SOC15_IH_CLIENTID_SDMA1: >+ return 1; >+ case SOC15_IH_CLIENTID_SDMA2: >+ return 2; >+ case SOC15_IH_CLIENTID_SDMA3: >+ return 3; >+ case SOC15_IH_CLIENTID_SDMA4: >+ return 4; >+ case SOC15_IH_CLIENTID_SDMA5: >+ return 5; >+ case SOC15_IH_CLIENTID_SDMA6: >+ return 6; >+ case SOC15_IH_CLIENTID_SDMA7: >+ return 7; >+ default: >+ break; >+ } >+ return -EINVAL; > } > > static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) > { > switch (adev->asic_type) { > case CHIP_VEGA10: >- if (!amdgpu_virt_support_skip_setting(adev)) { >- soc15_program_register_sequence(adev, >- golden_settings_sdma_4, >- ARRAY_SIZE(golden_settings_sdma_4)); >- soc15_program_register_sequence(adev, >- golden_settings_sdma_vg10, >- ARRAY_SIZE(golden_settings_sdma_vg10)); >- } >+ soc15_program_register_sequence(adev, >+ golden_settings_sdma_4, >+ ARRAY_SIZE(golden_settings_sdma_4)); >+ soc15_program_register_sequence(adev, >+ golden_settings_sdma_vg10, >+ ARRAY_SIZE(golden_settings_sdma_vg10)); > break; > case CHIP_VEGA12: > soc15_program_register_sequence(adev, >@@ -241,6 +362,11 @@ > golden_settings_sdma1_4_2, > ARRAY_SIZE(golden_settings_sdma1_4_2)); > break; >+ case CHIP_ARCTURUS: >+ soc15_program_register_sequence(adev, >+ golden_settings_sdma_arct, >+ ARRAY_SIZE(golden_settings_sdma_arct)); >+ break; > case CHIP_RAVEN: > soc15_program_register_sequence(adev, > golden_settings_sdma_4_1, >@@ -254,11 +380,53 @@ > golden_settings_sdma_rv1, > ARRAY_SIZE(golden_settings_sdma_rv1)); > break; >+ case CHIP_RENOIR: >+ soc15_program_register_sequence(adev, >+ golden_settings_sdma_4_3, >+ ARRAY_SIZE(golden_settings_sdma_4_3)); >+ break; > default: > break; > } > } > >+static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) >+{ >+ int err = 0; >+ const struct sdma_firmware_header_v1_0 *hdr; >+ >+ err = amdgpu_ucode_validate(sdma_inst->fw); >+ if (err) >+ return err; >+ >+ hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; >+ sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); >+ sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); >+ >+ if (sdma_inst->feature_version >= 20) >+ sdma_inst->burst_nop = true; >+ >+ return 0; >+} >+ >+static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) >+{ >+ int i; >+ >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ if (adev->sdma.instance[i].fw != NULL) >+ release_firmware(adev->sdma.instance[i].fw); >+ >+ /* arcturus shares the same FW memory across >+ all SDMA isntances */ >+ if (adev->asic_type == CHIP_ARCTURUS) >+ break; >+ } >+ >+ memset((void*)adev->sdma.instance, 0, >+ sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); >+} >+ > /** > * sdma_v4_0_init_microcode - load ucode images from disk > * >@@ -278,7 +446,6 @@ > int err = 0, i; > struct amdgpu_firmware_info *info = NULL; > const struct common_firmware_header *header = NULL; >- const struct sdma_firmware_header_v1_0 *hdr; > > DRM_DEBUG("\n"); > >@@ -300,30 +467,52 @@ > else > chip_name = "raven"; > break; >+ case CHIP_ARCTURUS: >+ chip_name = "arcturus"; >+ break; >+ case CHIP_RENOIR: >+ chip_name = "renoir"; >+ break; > default: > BUG(); > } > >- for (i = 0; i < adev->sdma.num_instances; i++) { >- if (i == 0) >- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); >- else >- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); >- err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); >- if (err) >- goto out; >- err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); >- if (err) >- goto out; >- hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; >- adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); >- adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); >- if (adev->sdma.instance[i].feature_version >= 20) >- adev->sdma.instance[i].burst_nop = true; >- DRM_DEBUG("psp_load == '%s'\n", >- adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); >+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); >+ >+ err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); >+ if (err) >+ goto out; >+ >+ err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); >+ if (err) >+ goto out; >+ >+ for (i = 1; i < adev->sdma.num_instances; i++) { >+ if (adev->asic_type == CHIP_ARCTURUS) { >+ /* Acturus will leverage the same FW memory >+ for every SDMA instance */ >+ memcpy((void*)&adev->sdma.instance[i], >+ (void*)&adev->sdma.instance[0], >+ sizeof(struct amdgpu_sdma_instance)); >+ } >+ else { >+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); >+ >+ err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); >+ if (err) >+ goto out; >+ >+ err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); >+ if (err) >+ goto out; >+ } >+ } > >- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { >+ DRM_DEBUG("psp_load == '%s'\n", >+ adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); >+ >+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { >+ for (i = 0; i < adev->sdma.num_instances; i++) { > info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; > info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; > info->fw = adev->sdma.instance[i].fw; >@@ -332,13 +521,11 @@ > ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); > } > } >+ > out: > if (err) { > DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); >- for (i = 0; i < adev->sdma.num_instances; i++) { >- release_firmware(adev->sdma.instance[i].fw); >- adev->sdma.instance[i].fw = NULL; >- } >+ sdma_v4_0_destroy_inst_ctx(adev); > } > return err; > } >@@ -561,10 +748,7 @@ > u32 ref_and_mask = 0; > const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; > >- if (ring->me == 0) >- ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; >- else >- ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; >+ ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; > > sdma_v4_0_wait_reg_mem(ring, 0, 1, > adev->nbio_funcs->get_hdp_flush_done_offset(adev), >@@ -620,26 +804,27 @@ > */ > static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) > { >- struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; >- struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; >+ struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; > u32 rb_cntl, ib_cntl; >- int i; >+ int i, unset = 0; >+ >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ sdma[i] = &adev->sdma.instance[i].ring; > >- if ((adev->mman.buffer_funcs_ring == sdma0) || >- (adev->mman.buffer_funcs_ring == sdma1)) >+ if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { > amdgpu_ttm_set_buffer_funcs_status(adev, false); >+ unset = 1; >+ } > >- for (i = 0; i < adev->sdma.num_instances; i++) { > rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); > rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); > WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); > ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); > ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); > WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); >- } > >- sdma0->sched.ready = false; >- sdma1->sched.ready = false; >+ sdma[i]->sched.ready = false; >+ } > } > > /** >@@ -663,16 +848,20 @@ > */ > static void sdma_v4_0_page_stop(struct amdgpu_device *adev) > { >- struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page; >- struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page; >+ struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; > u32 rb_cntl, ib_cntl; > int i; >- >- if ((adev->mman.buffer_funcs_ring == sdma0) || >- (adev->mman.buffer_funcs_ring == sdma1)) >- amdgpu_ttm_set_buffer_funcs_status(adev, false); >+ bool unset = false; > > for (i = 0; i < adev->sdma.num_instances; i++) { >+ sdma[i] = &adev->sdma.instance[i].page; >+ >+ if ((adev->mman.buffer_funcs_ring == sdma[i]) && >+ (unset == false)) { >+ amdgpu_ttm_set_buffer_funcs_status(adev, false); >+ unset = true; >+ } >+ > rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); > rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, > RB_ENABLE, 0); >@@ -681,10 +870,9 @@ > ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, > IB_ENABLE, 0); > WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); >- } > >- sdma0->sched.ready = false; >- sdma1->sched.ready = false; >+ sdma[i]->sched.ready = false; >+ } > } > > /** >@@ -1018,6 +1206,7 @@ > > switch (adev->asic_type) { > case CHIP_RAVEN: >+ case CHIP_RENOIR: > sdma_v4_1_init_power_gating(adev); > sdma_v4_1_update_power_gating(adev, true); > break; >@@ -1473,8 +1662,10 @@ > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > int r; > >- if (adev->asic_type == CHIP_RAVEN) >+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) > adev->sdma.num_instances = 1; >+ else if (adev->asic_type == CHIP_ARCTURUS) >+ adev->sdma.num_instances = 8; > else > adev->sdma.num_instances = 2; > >@@ -1499,6 +1690,7 @@ > } > > static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, > struct amdgpu_iv_entry *entry); > > static int sdma_v4_0_late_init(void *handle) >@@ -1518,7 +1710,7 @@ > .sub_block_index = 0, > .name = "sdma", > }; >- int r; >+ int r, i; > > if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { > amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); >@@ -1575,14 +1767,11 @@ > if (r) > goto sysfs; > resume: >- r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0); >- if (r) >- goto irq; >- >- r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1); >- if (r) { >- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0); >- goto irq; >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, >+ AMDGPU_SDMA_IRQ_INSTANCE0 + i); >+ if (r) >+ goto irq; > } > > return 0; >@@ -1606,28 +1795,22 @@ > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > /* SDMA trap event */ >- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP, >- &adev->sdma.trap_irq); >- if (r) >- return r; >- >- /* SDMA trap event */ >- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP, >- &adev->sdma.trap_irq); >- if (r) >- return r; >- >- /* SDMA SRAM ECC event */ >- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_SRAM_ECC, >- &adev->sdma.ecc_irq); >- if (r) >- return r; >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), >+ SDMA0_4_0__SRCID__SDMA_TRAP, >+ &adev->sdma.trap_irq); >+ if (r) >+ return r; >+ } > > /* SDMA SRAM ECC event */ >- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_SRAM_ECC, >- &adev->sdma.ecc_irq); >- if (r) >- return r; >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), >+ SDMA0_4_0__SRCID__SDMA_SRAM_ECC, >+ &adev->sdma.ecc_irq); >+ if (r) >+ return r; >+ } > > for (i = 0; i < adev->sdma.num_instances; i++) { > ring = &adev->sdma.instance[i].ring; >@@ -1641,11 +1824,8 @@ > ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; > > sprintf(ring->name, "sdma%d", i); >- r = amdgpu_ring_init(adev, ring, 1024, >- &adev->sdma.trap_irq, >- (i == 0) ? >- AMDGPU_SDMA_IRQ_INSTANCE0 : >- AMDGPU_SDMA_IRQ_INSTANCE1); >+ r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, >+ AMDGPU_SDMA_IRQ_INSTANCE0 + i); > if (r) > return r; > >@@ -1663,9 +1843,7 @@ > sprintf(ring->name, "page%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > &adev->sdma.trap_irq, >- (i == 0) ? >- AMDGPU_SDMA_IRQ_INSTANCE0 : >- AMDGPU_SDMA_IRQ_INSTANCE1); >+ AMDGPU_SDMA_IRQ_INSTANCE0 + i); > if (r) > return r; > } >@@ -1701,10 +1879,7 @@ > amdgpu_ring_fini(&adev->sdma.instance[i].page); > } > >- for (i = 0; i < adev->sdma.num_instances; i++) { >- release_firmware(adev->sdma.instance[i].fw); >- adev->sdma.instance[i].fw = NULL; >- } >+ sdma_v4_0_destroy_inst_ctx(adev); > > return 0; > } >@@ -1718,7 +1893,8 @@ > adev->powerplay.pp_funcs->set_powergating_by_smu) > amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); > >- sdma_v4_0_init_golden_registers(adev); >+ if (!amdgpu_sriov_vf(adev)) >+ sdma_v4_0_init_golden_registers(adev); > > r = sdma_v4_0_start(adev); > >@@ -1728,12 +1904,15 @@ > static int sdma_v4_0_hw_fini(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ int i; > > if (amdgpu_sriov_vf(adev)) > return 0; > >- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0); >- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1); >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ amdgpu_irq_put(adev, &adev->sdma.ecc_irq, >+ AMDGPU_SDMA_IRQ_INSTANCE0 + i); >+ } > > sdma_v4_0_ctx_switch_enable(adev, false); > sdma_v4_0_enable(adev, false); >@@ -1776,15 +1955,17 @@ > > static int sdma_v4_0_wait_for_idle(void *handle) > { >- unsigned i; >- u32 sdma0, sdma1; >+ unsigned i, j; >+ u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > for (i = 0; i < adev->usec_timeout; i++) { >- sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG); >- sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG); >- >- if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) >+ for (j = 0; j < adev->sdma.num_instances; j++) { >+ sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); >+ if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) >+ break; >+ } >+ if (j == adev->sdma.num_instances) > return 0; > udelay(1); > } >@@ -1820,17 +2001,7 @@ > uint32_t instance; > > DRM_DEBUG("IH: SDMA trap\n"); >- switch (entry->client_id) { >- case SOC15_IH_CLIENTID_SDMA0: >- instance = 0; >- break; >- case SOC15_IH_CLIENTID_SDMA1: >- instance = 1; >- break; >- default: >- return 0; >- } >- >+ instance = sdma_v4_0_irq_id_to_seq(entry->client_id); > switch (entry->ring_id) { > case 0: > amdgpu_fence_process(&adev->sdma.instance[instance].ring); >@@ -1851,20 +2022,15 @@ > } > > static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, > struct amdgpu_iv_entry *entry) > { >- uint32_t instance, err_source; >+ uint32_t err_source; >+ int instance; > >- switch (entry->client_id) { >- case SOC15_IH_CLIENTID_SDMA0: >- instance = 0; >- break; >- case SOC15_IH_CLIENTID_SDMA1: >- instance = 1; >- break; >- default: >+ instance = sdma_v4_0_irq_id_to_seq(entry->client_id); >+ if (instance < 0) > return 0; >- } > > switch (entry->src_id) { > case SDMA0_4_0__SRCID__SDMA_SRAM_ECC: >@@ -1881,7 +2047,7 @@ > > amdgpu_ras_reset_gpu(adev, 0); > >- return AMDGPU_RAS_UE; >+ return AMDGPU_RAS_SUCCESS; > } > > static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev, >@@ -1910,16 +2076,9 @@ > > DRM_ERROR("Illegal instruction in SDMA command stream\n"); > >- switch (entry->client_id) { >- case SOC15_IH_CLIENTID_SDMA0: >- instance = 0; >- break; >- case SOC15_IH_CLIENTID_SDMA1: >- instance = 1; >- break; >- default: >+ instance = sdma_v4_0_irq_id_to_seq(entry->client_id); >+ if (instance < 0) > return 0; >- } > > switch (entry->ring_id) { > case 0: >@@ -1936,14 +2095,10 @@ > { > u32 sdma_edc_config; > >- u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? >- sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_EDC_CONFIG) : >- sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_EDC_CONFIG); >- >- sdma_edc_config = RREG32(reg_offset); >+ sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); > sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, > state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); >- WREG32(reg_offset, sdma_edc_config); >+ WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); > > return 0; > } >@@ -1953,61 +2108,35 @@ > bool enable) > { > uint32_t data, def; >+ int i; > > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { >- /* enable sdma0 clock gating */ >- def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); >- data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); >- if (def != data) >- WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); >- >- if (adev->sdma.num_instances > 1) { >- def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); >- data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); >+ data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); > if (def != data) >- WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); >+ WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); > } > } else { >- /* disable sdma0 clock gating */ >- def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); >- data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | >- SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); >- >- if (def != data) >- WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); >- >- if (adev->sdma.num_instances > 1) { >- def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); >- data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | >- SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); >+ data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | >+ SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); > if (def != data) >- WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); >+ WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); > } > } > } >@@ -2018,34 +2147,23 @@ > bool enable) > { > uint32_t data, def; >+ int i; > > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { >- /* 1-not override: enable sdma0 mem light sleep */ >- def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); >- data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; >- if (def != data) >- WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); >- >- /* 1-not override: enable sdma1 mem light sleep */ >- if (adev->sdma.num_instances > 1) { >- def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); >- data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ /* 1-not override: enable sdma mem light sleep */ >+ def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); >+ data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; > if (def != data) >- WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); >+ WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); > } > } else { >- /* 0-override:disable sdma0 mem light sleep */ >- def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); >- data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; >- if (def != data) >- WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); >- >- /* 0-override:disable sdma1 mem light sleep */ >- if (adev->sdma.num_instances > 1) { >- def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); >- data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ /* 0-override:disable sdma mem light sleep */ >+ def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); >+ data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; > if (def != data) >- WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); >+ WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); > } > } > } >@@ -2063,6 +2181,8 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: >+ case CHIP_RENOIR: > sdma_v4_0_update_medium_grain_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > sdma_v4_0_update_medium_grain_light_sleep(adev, >@@ -2133,7 +2253,43 @@ > .align_mask = 0xf, > .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, >+ .get_rptr = sdma_v4_0_ring_get_rptr, >+ .get_wptr = sdma_v4_0_ring_get_wptr, >+ .set_wptr = sdma_v4_0_ring_set_wptr, >+ .emit_frame_size = >+ 6 + /* sdma_v4_0_ring_emit_hdp_flush */ >+ 3 + /* hdp invalidate */ >+ 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ >+ /* sdma_v4_0_ring_emit_vm_flush */ >+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + >+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + >+ 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ >+ .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ >+ .emit_ib = sdma_v4_0_ring_emit_ib, >+ .emit_fence = sdma_v4_0_ring_emit_fence, >+ .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, >+ .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, >+ .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, >+ .test_ring = sdma_v4_0_ring_test_ring, >+ .test_ib = sdma_v4_0_ring_test_ib, >+ .insert_nop = sdma_v4_0_ring_insert_nop, >+ .pad_ib = sdma_v4_0_ring_pad_ib, >+ .emit_wreg = sdma_v4_0_ring_emit_wreg, >+ .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, >+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, >+}; >+ >+/* >+ * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). >+ * So create a individual constant ring_funcs for those instances. >+ */ >+static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { >+ .type = AMDGPU_RING_TYPE_SDMA, >+ .align_mask = 0xf, >+ .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), >+ .support_64bit_ptrs = true, >+ .vmhub = AMDGPU_MMHUB_1, > .get_rptr = sdma_v4_0_ring_get_rptr, > .get_wptr = sdma_v4_0_ring_get_wptr, > .set_wptr = sdma_v4_0_ring_set_wptr, >@@ -2165,7 +2321,39 @@ > .align_mask = 0xf, > .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, >+ .get_rptr = sdma_v4_0_ring_get_rptr, >+ .get_wptr = sdma_v4_0_page_ring_get_wptr, >+ .set_wptr = sdma_v4_0_page_ring_set_wptr, >+ .emit_frame_size = >+ 6 + /* sdma_v4_0_ring_emit_hdp_flush */ >+ 3 + /* hdp invalidate */ >+ 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ >+ /* sdma_v4_0_ring_emit_vm_flush */ >+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + >+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + >+ 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ >+ .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ >+ .emit_ib = sdma_v4_0_ring_emit_ib, >+ .emit_fence = sdma_v4_0_ring_emit_fence, >+ .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, >+ .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, >+ .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, >+ .test_ring = sdma_v4_0_ring_test_ring, >+ .test_ib = sdma_v4_0_ring_test_ib, >+ .insert_nop = sdma_v4_0_ring_insert_nop, >+ .pad_ib = sdma_v4_0_ring_pad_ib, >+ .emit_wreg = sdma_v4_0_ring_emit_wreg, >+ .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, >+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, >+}; >+ >+static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { >+ .type = AMDGPU_RING_TYPE_SDMA, >+ .align_mask = 0xf, >+ .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), >+ .support_64bit_ptrs = true, >+ .vmhub = AMDGPU_MMHUB_1, > .get_rptr = sdma_v4_0_ring_get_rptr, > .get_wptr = sdma_v4_0_page_ring_get_wptr, > .set_wptr = sdma_v4_0_page_ring_set_wptr, >@@ -2197,10 +2385,20 @@ > int i; > > for (i = 0; i < adev->sdma.num_instances; i++) { >- adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; >+ if (adev->asic_type == CHIP_ARCTURUS && i >= 5) >+ adev->sdma.instance[i].ring.funcs = >+ &sdma_v4_0_ring_funcs_2nd_mmhub; >+ else >+ adev->sdma.instance[i].ring.funcs = >+ &sdma_v4_0_ring_funcs; > adev->sdma.instance[i].ring.me = i; > if (adev->sdma.has_page_queue) { >- adev->sdma.instance[i].page.funcs = &sdma_v4_0_page_ring_funcs; >+ if (adev->asic_type == CHIP_ARCTURUS && i >= 5) >+ adev->sdma.instance[i].page.funcs = >+ &sdma_v4_0_page_ring_funcs_2nd_mmhub; >+ else >+ adev->sdma.instance[i].page.funcs = >+ &sdma_v4_0_page_ring_funcs; > adev->sdma.instance[i].page.me = i; > } > } >@@ -2224,10 +2422,23 @@ > > static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) > { >- adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; >+ switch (adev->sdma.num_instances) { >+ case 1: >+ adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; >+ adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; >+ break; >+ case 8: >+ adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; >+ adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; >+ break; >+ case 2: >+ default: >+ adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; >+ adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; >+ break; >+ } > adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; > adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; >- adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; > adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; > } > >@@ -2293,8 +2504,8 @@ > static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) > { > adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; >- if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) >- adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page; >+ if (adev->sdma.has_page_queue) >+ adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; > else > adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; > } >@@ -2313,22 +2524,15 @@ > unsigned i; > > adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; >- if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) { >- for (i = 1; i < adev->sdma.num_instances; i++) { >+ for (i = 0; i < adev->sdma.num_instances; i++) { >+ if (adev->sdma.has_page_queue) > sched = &adev->sdma.instance[i].page.sched; >- adev->vm_manager.vm_pte_rqs[i - 1] = >- &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; >- } >- adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances - 1; >- adev->vm_manager.page_fault = &adev->sdma.instance[0].page; >- } else { >- for (i = 0; i < adev->sdma.num_instances; i++) { >+ else > sched = &adev->sdma.instance[i].ring.sched; >- adev->vm_manager.vm_pte_rqs[i] = >- &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; >- } >- adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; >+ adev->vm_manager.vm_pte_rqs[i] = >+ &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; > } >+ adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; > } > > const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 2019-08-31 15:01:11.850736167 -0500 >@@ -21,8 +21,11 @@ > * > */ > >+#include <linux/delay.h> > #include <linux/firmware.h> >-#include <drm/drmP.h> >+#include <linux/module.h> >+#include <linux/pci.h> >+ > #include "amdgpu.h" > #include "amdgpu_ucode.h" > #include "amdgpu_trace.h" >@@ -42,6 +45,12 @@ > MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); > MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); > >+MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); >+MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); >+ >+MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); >+MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); >+ > #define SDMA1_REG_OFFSET 0x600 > #define SDMA0_HYP_DEC_REG_START 0x5880 > #define SDMA0_HYP_DEC_REG_END 0x5893 >@@ -59,7 +68,7 @@ > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >- SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >@@ -71,7 +80,7 @@ > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >- SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >@@ -80,6 +89,18 @@ > }; > > static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), >+}; >+ >+static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >+}; >+ >+static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), >+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), > }; > > static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) >@@ -111,6 +132,22 @@ > golden_settings_sdma_nv10, > (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); > break; >+ case CHIP_NAVI14: >+ soc15_program_register_sequence(adev, >+ golden_settings_sdma_5, >+ (const u32)ARRAY_SIZE(golden_settings_sdma_5)); >+ soc15_program_register_sequence(adev, >+ golden_settings_sdma_nv14, >+ (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); >+ break; >+ case CHIP_NAVI12: >+ soc15_program_register_sequence(adev, >+ golden_settings_sdma_5, >+ (const u32)ARRAY_SIZE(golden_settings_sdma_5)); >+ soc15_program_register_sequence(adev, >+ golden_settings_sdma_nv12, >+ (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); >+ break; > default: > break; > } >@@ -143,6 +180,12 @@ > case CHIP_NAVI10: > chip_name = "navi10"; > break; >+ case CHIP_NAVI14: >+ chip_name = "navi14"; >+ break; >+ case CHIP_NAVI12: >+ chip_name = "navi12"; >+ break; > default: > BUG(); > } >@@ -861,7 +904,7 @@ > if (amdgpu_emu_mode == 1) > msleep(1); > else >- DRM_UDELAY(1); >+ udelay(1); > } > > if (i < adev->usec_timeout) { >@@ -1316,7 +1359,7 @@ > if (ring->trail_seq == > le32_to_cpu(*(ring->trail_fence_cpu_addr))) > break; >- DRM_UDELAY(1); >+ udelay(1); > } > > if (i >= adev->usec_timeout) { >@@ -1472,6 +1515,8 @@ > > switch (adev->asic_type) { > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: > sdma_v5_0_update_medium_grain_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > sdma_v5_0_update_medium_grain_light_sleep(adev, >@@ -1532,7 +1577,7 @@ > .align_mask = 0xf, > .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > .support_64bit_ptrs = true, >- .vmhub = AMDGPU_GFXHUB, >+ .vmhub = AMDGPU_GFXHUB_0, > .get_rptr = sdma_v5_0_ring_get_rptr, > .get_wptr = sdma_v5_0_ring_get_wptr, > .set_wptr = sdma_v5_0_ring_set_wptr, >@@ -1583,7 +1628,8 @@ > > static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) > { >- adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; >+ adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + >+ adev->sdma.num_instances; > adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; > adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/si.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/si.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/si.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/si.c 2019-08-31 15:01:11.850736167 -0500 >@@ -1186,6 +1186,12 @@ > return 0; > } > >+static enum amd_reset_method >+si_asic_reset_method(struct amdgpu_device *adev) >+{ >+ return AMD_RESET_METHOD_LEGACY; >+} >+ > static u32 si_get_config_memsize(struct amdgpu_device *adev) > { > return RREG32(mmCONFIG_MEMSIZE); >@@ -1394,6 +1400,7 @@ > .read_bios_from_rom = &si_read_bios_from_rom, > .read_register = &si_read_register, > .reset = &si_asic_reset, >+ .reset_method = &si_asic_reset_method, > .set_vga_state = &si_vga_set_state, > .get_xclk = &si_get_xclk, > .set_uvd_clocks = &si_set_uvd_clocks, >@@ -1881,7 +1888,7 @@ > if (orig != data) > si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); > >- if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) { >+ if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) { > orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); > data &= ~PLL_RAMP_UP_TIME_0_MASK; > if (orig != data) >@@ -1930,14 +1937,14 @@ > > orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL); > data &= ~LS2_EXIT_TIME_MASK; >- if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN)) >+ if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) > data |= LS2_EXIT_TIME(5); > if (orig != data) > si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data); > > orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL); > data &= ~LS2_EXIT_TIME_MASK; >- if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN)) >+ if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) > data |= LS2_EXIT_TIME(5); > if (orig != data) > si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 2019-08-31 15:01:11.850736167 -0500 >@@ -0,0 +1,724 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+ >+#include "smuio/smuio_11_0_0_offset.h" >+#include "smuio/smuio_11_0_0_sh_mask.h" >+ >+#include "smu_v11_0_i2c.h" >+#include "amdgpu.h" >+#include "soc15_common.h" >+#include <drm/drm_fixed.h> >+#include <drm/drm_drv.h> >+#include "amdgpu_amdkfd.h" >+#include <linux/i2c.h> >+#include <linux/pci.h> >+#include "amdgpu_ras.h" >+ >+/* error codes */ >+#define I2C_OK 0 >+#define I2C_NAK_7B_ADDR_NOACK 1 >+#define I2C_NAK_TXDATA_NOACK 2 >+#define I2C_TIMEOUT 4 >+#define I2C_SW_TIMEOUT 8 >+#define I2C_ABORT 0x10 >+ >+/* I2C transaction flags */ >+#define I2C_NO_STOP 1 >+#define I2C_RESTART 2 >+ >+#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev >+#define to_eeprom_control(x) container_of(x, struct amdgpu_ras_eeprom_control, eeprom_accessor) >+ >+static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); >+ >+ reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0); >+ WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg); >+} >+ >+ >+static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0); >+} >+ >+static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ /* do */ >+ { >+ RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); >+ >+ } /* while (reg_CKSVII2C_ic_clr_intr == 0) */ >+} >+ >+static void smu_v11_0_i2c_configure(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ uint32_t reg = 0; >+ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1); >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1); >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0); >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0); >+ /* Standard mode */ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2); >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1); >+ >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg); >+} >+ >+static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ >+ /* >+ * Standard mode speed, These values are taken from SMUIO MAS, >+ * but are different from what is given is >+ * Synopsys spec. The values here are based on assumption >+ * that refclock is 100MHz >+ * >+ * Configuration for standard mode; Speed = 100kbps >+ * Scale linearly, for now only support standard speed clock >+ * This will work only with 100M ref clock >+ * >+ * TBD:Change the calculation to take into account ref clock values also. >+ */ >+ >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2); >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120); >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130); >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20); >+} >+ >+static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t address) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ >+ /* Convert fromr 8-bit to 7-bit address */ >+ address >>= 1; >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF)); >+} >+ >+static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ uint32_t ret = I2C_OK; >+ uint32_t reg, reg_c_tx_abrt_source; >+ >+ /*Check if transmission is completed */ >+ unsigned long timeout_counter = jiffies + msecs_to_jiffies(20); >+ >+ do { >+ if (time_after(jiffies, timeout_counter)) { >+ ret |= I2C_SW_TIMEOUT; >+ break; >+ } >+ >+ reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); >+ >+ } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); >+ >+ if (ret != I2C_OK) >+ return ret; >+ >+ /* This only checks if NAK is received and transaction got aborted */ >+ reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); >+ >+ if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { >+ reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); >+ DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source); >+ >+ /* Check for stop due to NACK */ >+ if (REG_GET_FIELD(reg_c_tx_abrt_source, >+ CKSVII2C_IC_TX_ABRT_SOURCE, >+ ABRT_TXDATA_NOACK) == 1) { >+ >+ ret |= I2C_NAK_TXDATA_NOACK; >+ >+ } else if (REG_GET_FIELD(reg_c_tx_abrt_source, >+ CKSVII2C_IC_TX_ABRT_SOURCE, >+ ABRT_7B_ADDR_NOACK) == 1) { >+ >+ ret |= I2C_NAK_7B_ADDR_NOACK; >+ } else { >+ ret |= I2C_ABORT; >+ } >+ >+ smu_v11_0_i2c_clear_status(control); >+ } >+ >+ return ret; >+} >+ >+static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ uint32_t ret = I2C_OK; >+ uint32_t reg_ic_status, reg_c_tx_abrt_source; >+ >+ reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); >+ >+ /* If slave is not present */ >+ if (REG_GET_FIELD(reg_c_tx_abrt_source, >+ CKSVII2C_IC_TX_ABRT_SOURCE, >+ ABRT_7B_ADDR_NOACK) == 1) { >+ ret |= I2C_NAK_7B_ADDR_NOACK; >+ >+ smu_v11_0_i2c_clear_status(control); >+ } else { /* wait till some data is there in RXFIFO */ >+ /* Poll for some byte in RXFIFO */ >+ unsigned long timeout_counter = jiffies + msecs_to_jiffies(20); >+ >+ do { >+ if (time_after(jiffies, timeout_counter)) { >+ ret |= I2C_SW_TIMEOUT; >+ break; >+ } >+ >+ reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); >+ >+ } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); >+ } >+ >+ return ret; >+} >+ >+ >+ >+ >+/** >+ * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device. >+ * >+ * @address: The I2C address of the slave device. >+ * @data: The data to transmit over the bus. >+ * @numbytes: The amount of data to transmit. >+ * @i2c_flag: Flags for transmission >+ * >+ * Returns 0 on success or error. >+ */ >+static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control, >+ uint8_t address, uint8_t *data, >+ uint32_t numbytes, uint32_t i2c_flag) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ uint32_t bytes_sent, reg, ret = 0; >+ unsigned long timeout_counter; >+ >+ bytes_sent = 0; >+ >+ DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ", >+ (uint16_t)address, numbytes); >+ >+ if (drm_debug & DRM_UT_DRIVER) { >+ print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE, >+ 16, 1, data, numbytes, false); >+ } >+ >+ /* Set the I2C slave address */ >+ smu_v11_0_i2c_set_address(control, address); >+ /* Enable I2C */ >+ smu_v11_0_i2c_enable(control, true); >+ >+ /* Clear status bits */ >+ smu_v11_0_i2c_clear_status(control); >+ >+ >+ timeout_counter = jiffies + msecs_to_jiffies(20); >+ >+ while (numbytes > 0) { >+ reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); >+ if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { >+ do { >+ reg = 0; >+ /* >+ * Prepare transaction, no need to set RESTART. I2C engine will send >+ * START as soon as it sees data in TXFIFO >+ */ >+ if (bytes_sent == 0) >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, >+ (i2c_flag & I2C_RESTART) ? 1 : 0); >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]); >+ >+ /* determine if we need to send STOP bit or not */ >+ if (numbytes == 1) >+ /* Final transaction, so send stop unless I2C_NO_STOP */ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, >+ (i2c_flag & I2C_NO_STOP) ? 0 : 1); >+ /* Write */ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0); >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); >+ >+ /* Record that the bytes were transmitted */ >+ bytes_sent++; >+ numbytes--; >+ >+ reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); >+ >+ } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)); >+ } >+ >+ /* >+ * We waited too long for the transmission FIFO to become not-full. >+ * Exit the loop with error. >+ */ >+ if (time_after(jiffies, timeout_counter)) { >+ ret |= I2C_SW_TIMEOUT; >+ goto Err; >+ } >+ } >+ >+ ret = smu_v11_0_i2c_poll_tx_status(control); >+ >+Err: >+ /* Any error, no point in proceeding */ >+ if (ret != I2C_OK) { >+ if (ret & I2C_SW_TIMEOUT) >+ DRM_ERROR("TIMEOUT ERROR !!!"); >+ >+ if (ret & I2C_NAK_7B_ADDR_NOACK) >+ DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!"); >+ >+ >+ if (ret & I2C_NAK_TXDATA_NOACK) >+ DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!"); >+ } >+ >+ return ret; >+} >+ >+ >+/** >+ * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device. >+ * >+ * @address: The I2C address of the slave device. >+ * @numbytes: The amount of data to transmit. >+ * @i2c_flag: Flags for transmission >+ * >+ * Returns 0 on success or error. >+ */ >+static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control, >+ uint8_t address, uint8_t *data, >+ uint32_t numbytes, uint8_t i2c_flag) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ uint32_t bytes_received, ret = I2C_OK; >+ >+ bytes_received = 0; >+ >+ /* Set the I2C slave address */ >+ smu_v11_0_i2c_set_address(control, address); >+ >+ /* Enable I2C */ >+ smu_v11_0_i2c_enable(control, true); >+ >+ while (numbytes > 0) { >+ uint32_t reg = 0; >+ >+ smu_v11_0_i2c_clear_status(control); >+ >+ >+ /* Prepare transaction */ >+ >+ /* Each time we disable I2C, so this is not a restart */ >+ if (bytes_received == 0) >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, >+ (i2c_flag & I2C_RESTART) ? 1 : 0); >+ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0); >+ /* Read */ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1); >+ >+ /* Transmitting last byte */ >+ if (numbytes == 1) >+ /* Final transaction, so send stop if requested */ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, >+ (i2c_flag & I2C_NO_STOP) ? 0 : 1); >+ >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); >+ >+ ret = smu_v11_0_i2c_poll_rx_status(control); >+ >+ /* Any error, no point in proceeding */ >+ if (ret != I2C_OK) { >+ if (ret & I2C_SW_TIMEOUT) >+ DRM_ERROR("TIMEOUT ERROR !!!"); >+ >+ if (ret & I2C_NAK_7B_ADDR_NOACK) >+ DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!"); >+ >+ if (ret & I2C_NAK_TXDATA_NOACK) >+ DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!"); >+ >+ break; >+ } >+ >+ reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); >+ data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); >+ >+ /* Record that the bytes were received */ >+ bytes_received++; >+ numbytes--; >+ } >+ >+ DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :", >+ (uint16_t)address, bytes_received); >+ >+ if (drm_debug & DRM_UT_DRIVER) { >+ print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE, >+ 16, 1, data, bytes_received, false); >+ } >+ >+ return ret; >+} >+ >+static void smu_v11_0_i2c_abort(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ uint32_t reg = 0; >+ >+ /* Enable I2C engine; */ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1); >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); >+ >+ /* Abort previous transaction */ >+ reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1); >+ WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); >+ >+ DRM_DEBUG_DRIVER("I2C_Abort() Done."); >+} >+ >+ >+static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ >+ const uint32_t IDLE_TIMEOUT = 1024; >+ uint32_t timeout_count = 0; >+ uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity; >+ >+ reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); >+ reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); >+ >+ >+ if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && >+ (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) { >+ /* >+ * Nobody is using I2C engine, but engine remains active because >+ * someone missed to send STOP >+ */ >+ smu_v11_0_i2c_abort(control); >+ } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) { >+ /* Nobody is using I2C engine */ >+ return true; >+ } >+ >+ /* Keep reading activity bit until it's cleared */ >+ do { >+ reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY); >+ >+ if (REG_GET_FIELD(reg_ic_clr_activity, >+ CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0) >+ return true; >+ >+ ++timeout_count; >+ >+ } while (timeout_count < IDLE_TIMEOUT); >+ >+ return false; >+} >+ >+static void smu_v11_0_i2c_init(struct i2c_adapter *control) >+{ >+ /* Disable clock gating */ >+ smu_v11_0_i2c_set_clock_gating(control, false); >+ >+ if (!smu_v11_0_i2c_activity_done(control)) >+ DRM_WARN("I2C busy !"); >+ >+ /* Disable I2C */ >+ smu_v11_0_i2c_enable(control, false); >+ >+ /* Configure I2C to operate as master and in standard mode */ >+ smu_v11_0_i2c_configure(control); >+ >+ /* Initialize the clock to 50 kHz default */ >+ smu_v11_0_i2c_set_clock(control); >+ >+} >+ >+static void smu_v11_0_i2c_fini(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ uint32_t reg_ic_enable_status, reg_ic_enable; >+ >+ smu_v11_0_i2c_enable(control, false); >+ >+ /* Double check if disabled, else force abort */ >+ reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); >+ reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); >+ >+ if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && >+ (REG_GET_FIELD(reg_ic_enable_status, >+ CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) { >+ /* >+ * Nobody is using I2C engine, but engine remains active because >+ * someone missed to send STOP >+ */ >+ smu_v11_0_i2c_abort(control); >+ } >+ >+ /* Restore clock gating */ >+ smu_v11_0_i2c_set_clock_gating(control, true); >+ >+} >+ >+static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ >+ /* Send PPSMC_MSG_RequestI2CBus */ >+ if (!adev->powerplay.pp_funcs->smu_i2c_bus_access) >+ goto Fail; >+ >+ >+ if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle, true)) >+ return true; >+ >+Fail: >+ return false; >+} >+ >+static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ >+ /* Send PPSMC_MSG_RequestI2CBus */ >+ if (!adev->powerplay.pp_funcs->smu_i2c_bus_access) >+ goto Fail; >+ >+ /* Send PPSMC_MSG_ReleaseI2CBus */ >+ if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle, >+ false)) >+ return true; >+ >+Fail: >+ return false; >+} >+ >+/***************************** EEPROM I2C GLUE ****************************/ >+ >+static uint32_t smu_v11_0_i2c_eeprom_read_data(struct i2c_adapter *control, >+ uint8_t address, >+ uint8_t *data, >+ uint32_t numbytes) >+{ >+ uint32_t ret = 0; >+ >+ /* First 2 bytes are dummy write to set EEPROM address */ >+ ret = smu_v11_0_i2c_transmit(control, address, data, 2, I2C_NO_STOP); >+ if (ret != I2C_OK) >+ goto Fail; >+ >+ /* Now read data starting with that address */ >+ ret = smu_v11_0_i2c_receive(control, address, data + 2, numbytes - 2, >+ I2C_RESTART); >+ >+Fail: >+ if (ret != I2C_OK) >+ DRM_ERROR("ReadData() - I2C error occurred :%x", ret); >+ >+ return ret; >+} >+ >+static uint32_t smu_v11_0_i2c_eeprom_write_data(struct i2c_adapter *control, >+ uint8_t address, >+ uint8_t *data, >+ uint32_t numbytes) >+{ >+ uint32_t ret; >+ >+ ret = smu_v11_0_i2c_transmit(control, address, data, numbytes, 0); >+ >+ if (ret != I2C_OK) >+ DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret); >+ else >+ /* >+ * According to EEPROM spec there is a MAX of 10 ms required for >+ * EEPROM to flush internal RX buffer after STOP was issued at the >+ * end of write transaction. During this time the EEPROM will not be >+ * responsive to any more commands - so wait a bit more. >+ * >+ * TODO Improve to wait for first ACK for slave address after >+ * internal write cycle done. >+ */ >+ msleep(10); >+ >+ return ret; >+ >+} >+ >+static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) >+{ >+ struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c); >+ >+ if (!smu_v11_0_i2c_bus_lock(i2c)) { >+ DRM_ERROR("Failed to lock the bus from SMU"); >+ return; >+ } >+ >+ control->bus_locked = true; >+} >+ >+static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) >+{ >+ WARN_ONCE(1, "This operation not supposed to run in atomic context!"); >+ return false; >+} >+ >+static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) >+{ >+ struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c); >+ >+ if (!smu_v11_0_i2c_bus_unlock(i2c)) { >+ DRM_ERROR("Failed to unlock the bus from SMU"); >+ return; >+ } >+ >+ control->bus_locked = false; >+} >+ >+static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = { >+ .lock_bus = lock_bus, >+ .trylock_bus = trylock_bus, >+ .unlock_bus = unlock_bus, >+}; >+ >+static int smu_v11_0_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap, >+ struct i2c_msg *msgs, int num) >+{ >+ int i, ret; >+ struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c_adap); >+ >+ if (!control->bus_locked) { >+ DRM_ERROR("I2C bus unlocked, stopping transaction!"); >+ return -EIO; >+ } >+ >+ smu_v11_0_i2c_init(i2c_adap); >+ >+ for (i = 0; i < num; i++) { >+ if (msgs[i].flags & I2C_M_RD) >+ ret = smu_v11_0_i2c_eeprom_read_data(i2c_adap, >+ (uint8_t)msgs[i].addr, >+ msgs[i].buf, msgs[i].len); >+ else >+ ret = smu_v11_0_i2c_eeprom_write_data(i2c_adap, >+ (uint8_t)msgs[i].addr, >+ msgs[i].buf, msgs[i].len); >+ >+ if (ret != I2C_OK) { >+ num = -EIO; >+ break; >+ } >+ } >+ >+ smu_v11_0_i2c_fini(i2c_adap); >+ return num; >+} >+ >+static u32 smu_v11_0_i2c_eeprom_i2c_func(struct i2c_adapter *adap) >+{ >+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; >+} >+ >+ >+static const struct i2c_algorithm smu_v11_0_i2c_eeprom_i2c_algo = { >+ .master_xfer = smu_v11_0_i2c_eeprom_i2c_xfer, >+ .functionality = smu_v11_0_i2c_eeprom_i2c_func, >+}; >+ >+int smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter *control) >+{ >+ struct amdgpu_device *adev = to_amdgpu_device(control); >+ int res; >+ >+ control->owner = THIS_MODULE; >+ control->class = I2C_CLASS_SPD; >+ control->dev.parent = &adev->pdev->dev; >+ control->algo = &smu_v11_0_i2c_eeprom_i2c_algo; >+ snprintf(control->name, sizeof(control->name), "RAS EEPROM"); >+ control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops; >+ >+ res = i2c_add_adapter(control); >+ if (res) >+ DRM_ERROR("Failed to register hw i2c, err: %d\n", res); >+ >+ return res; >+} >+ >+void smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter *control) >+{ >+ i2c_del_adapter(control); >+} >+ >+/* >+ * Keep this for future unit test if bugs arise >+ */ >+#if 0 >+#define I2C_TARGET_ADDR 0xA0 >+ >+bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control) >+{ >+ >+ uint32_t ret = I2C_OK; >+ uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef}; >+ >+ >+ DRM_INFO("Begin"); >+ >+ if (!smu_v11_0_i2c_bus_lock(control)) { >+ DRM_ERROR("Failed to lock the bus!."); >+ return false; >+ } >+ >+ smu_v11_0_i2c_init(control); >+ >+ /* Write 0xde to address 0x0000 on the EEPROM */ >+ ret = smu_v11_0_i2c_eeprom_write_data(control, I2C_TARGET_ADDR, data, 6); >+ >+ ret = smu_v11_0_i2c_eeprom_read_data(control, I2C_TARGET_ADDR, data, 6); >+ >+ smu_v11_0_i2c_fini(control); >+ >+ smu_v11_0_i2c_bus_unlock(control); >+ >+ >+ DRM_INFO("End"); >+ return true; >+} >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h 2019-08-31 15:01:11.851736168 -0500 >@@ -0,0 +1,34 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+ >+#ifndef SMU_V11_I2C_CONTROL_H >+#define SMU_V11_I2C_CONTROL_H >+ >+#include <linux/types.h> >+ >+struct i2c_adapter; >+ >+int smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter *control); >+void smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter *control); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15.c 2019-08-31 15:08:53.346776943 -0500 >@@ -63,6 +63,8 @@ > #include "uvd_v7_0.h" > #include "vce_v4_0.h" > #include "vcn_v1_0.h" >+#include "vcn_v2_0.h" >+#include "vcn_v2_5.h" > #include "dce_virtual.h" > #include "mxgpu_ai.h" > #include "amdgpu_smu.h" >@@ -115,6 +117,49 @@ > spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); > } > >+static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) >+{ >+ unsigned long flags, address, data; >+ u64 r; >+ address = adev->nbio_funcs->get_pcie_index_offset(adev); >+ data = adev->nbio_funcs->get_pcie_data_offset(adev); >+ >+ spin_lock_irqsave(&adev->pcie_idx_lock, flags); >+ /* read low 32 bit */ >+ WREG32(address, reg); >+ (void)RREG32(address); >+ r = RREG32(data); >+ >+ /* read high 32 bit*/ >+ WREG32(address, reg + 4); >+ (void)RREG32(address); >+ r |= ((u64)RREG32(data) << 32); >+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); >+ return r; >+} >+ >+static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) >+{ >+ unsigned long flags, address, data; >+ >+ address = adev->nbio_funcs->get_pcie_index_offset(adev); >+ data = adev->nbio_funcs->get_pcie_data_offset(adev); >+ >+ spin_lock_irqsave(&adev->pcie_idx_lock, flags); >+ /* write low 32 bit */ >+ WREG32(address, reg); >+ (void)RREG32(address); >+ WREG32(data, (u32)(v & 0xffffffffULL)); >+ (void)RREG32(data); >+ >+ /* write high 32 bit */ >+ WREG32(address, reg + 4); >+ (void)RREG32(address); >+ WREG32(data, (u32)(v >> 32)); >+ (void)RREG32(data); >+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); >+} >+ > static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) > { > unsigned long flags, address, data; >@@ -464,12 +509,23 @@ > return 0; > } > >-static int soc15_asic_reset(struct amdgpu_device *adev) >+static int soc15_mode2_reset(struct amdgpu_device *adev) >+{ >+ if (!adev->powerplay.pp_funcs || >+ !adev->powerplay.pp_funcs->asic_reset_mode_2) >+ return -ENOENT; >+ >+ return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle); >+} >+ >+static enum amd_reset_method >+soc15_asic_reset_method(struct amdgpu_device *adev) > { >- int ret; > bool baco_reset; > > switch (adev->asic_type) { >+ case CHIP_RAVEN: >+ return AMD_RESET_METHOD_MODE2; > case CHIP_VEGA10: > case CHIP_VEGA12: > soc15_asic_get_baco_capability(adev, &baco_reset); >@@ -493,11 +549,23 @@ > } > > if (baco_reset) >- ret = soc15_asic_baco_reset(adev); >+ return AMD_RESET_METHOD_BACO; > else >- ret = soc15_asic_mode1_reset(adev); >+ return AMD_RESET_METHOD_MODE1; >+} > >- return ret; >+static int soc15_asic_reset(struct amdgpu_device *adev) >+{ >+ switch (soc15_asic_reset_method(adev)) { >+ case AMD_RESET_METHOD_BACO: >+ amdgpu_inc_vram_lost(adev); >+ return soc15_asic_baco_reset(adev); >+ case AMD_RESET_METHOD_MODE2: >+ return soc15_mode2_reset(adev); >+ default: >+ amdgpu_inc_vram_lost(adev); >+ return soc15_asic_mode1_reset(adev); >+ } > } > > /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, >@@ -581,26 +649,31 @@ > case CHIP_VEGA10: > case CHIP_VEGA12: > case CHIP_RAVEN: >+ case CHIP_RENOIR: > vega10_reg_base_init(adev); > break; > case CHIP_VEGA20: > vega20_reg_base_init(adev); > break; >+ case CHIP_ARCTURUS: >+ arct_reg_base_init(adev); >+ break; > default: > return -EINVAL; > } > >- if (adev->asic_type == CHIP_VEGA20) >+ if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) > adev->gmc.xgmi.supported = true; > > if (adev->flags & AMD_IS_APU) > adev->nbio_funcs = &nbio_v7_0_funcs; >- else if (adev->asic_type == CHIP_VEGA20) >+ else if (adev->asic_type == CHIP_VEGA20 || >+ adev->asic_type == CHIP_ARCTURUS) > adev->nbio_funcs = &nbio_v7_4_funcs; > else > adev->nbio_funcs = &nbio_v6_1_funcs; > >- if (adev->asic_type == CHIP_VEGA20) >+ if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) > adev->df_funcs = &df_v3_6_funcs; > else > adev->df_funcs = &df_v1_7_funcs; >@@ -672,6 +745,37 @@ > #endif > amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); > break; >+ case CHIP_ARCTURUS: >+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); >+ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); >+ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) >+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); >+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); >+ break; >+ case CHIP_RENOIR: >+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); >+ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); >+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) >+ amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); >+ if (is_support_sw_smu(adev)) >+ amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); >+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); >+ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) >+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); >+#if defined(CONFIG_DRM_AMD_DC) >+ else if (amdgpu_device_has_dc_support(adev)) >+ amdgpu_device_ip_block_add(adev, &dm_ip_block); >+#else >+# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." >+#endif >+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); >+ break; > default: > return -EINVAL; > } >@@ -688,7 +792,7 @@ > struct amdgpu_ring *ring) > { > if (!ring || !ring->funcs->emit_wreg) >- WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); >+ WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); > else > amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( > HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); >@@ -714,14 +818,9 @@ > > /* Set the 2 events that we wish to watch, defined above */ > /* Reg 40 is # received msgs */ >+ /* Reg 104 is # of posted requests sent */ > perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); >- /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */ >- if (adev->asic_type == CHIP_VEGA20) >- perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, >- EVENT1_SEL, 108); >- else >- perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, >- EVENT1_SEL, 104); >+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); > > /* Write to enable desired perf counters */ > WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); >@@ -751,6 +850,55 @@ > *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); > } > >+static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, >+ uint64_t *count1) >+{ >+ uint32_t perfctr = 0; >+ uint64_t cnt0_of, cnt1_of; >+ int tmp; >+ >+ /* This reports 0 on APUs, so return to avoid writing/reading registers >+ * that may or may not be different from their GPU counterparts >+ */ >+ if (adev->flags & AMD_IS_APU) >+ return; >+ >+ /* Set the 2 events that we wish to watch, defined above */ >+ /* Reg 40 is # received msgs */ >+ /* Reg 108 is # of posted requests sent on VG20 */ >+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, >+ EVENT0_SEL, 40); >+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, >+ EVENT1_SEL, 108); >+ >+ /* Write to enable desired perf counters */ >+ WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); >+ /* Zero out and enable the perf counters >+ * Write 0x5: >+ * Bit 0 = Start all counters(1) >+ * Bit 2 = Global counter reset enable(1) >+ */ >+ WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); >+ >+ msleep(1000); >+ >+ /* Load the shadow and disable the perf counters >+ * Write 0x2: >+ * Bit 0 = Stop counters(0) >+ * Bit 1 = Load the shadow counters(1) >+ */ >+ WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); >+ >+ /* Read register values to get any >32bit overflow */ >+ tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); >+ cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); >+ cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); >+ >+ /* Get the values and add the overflow */ >+ *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); >+ *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); >+} >+ > static bool soc15_need_reset_on_init(struct amdgpu_device *adev) > { > u32 sol_reg; >@@ -792,6 +940,7 @@ > .read_bios_from_rom = &soc15_read_bios_from_rom, > .read_register = &soc15_read_register, > .reset = &soc15_asic_reset, >+ .reset_method = &soc15_asic_reset_method, > .set_vga_state = &soc15_vga_set_state, > .get_xclk = &soc15_get_xclk, > .set_uvd_clocks = &soc15_set_uvd_clocks, >@@ -821,9 +970,10 @@ > .invalidate_hdp = &soc15_invalidate_hdp, > .need_full_reset = &soc15_need_full_reset, > .init_doorbell_index = &vega20_doorbell_index_init, >- .get_pcie_usage = &soc15_get_pcie_usage, >+ .get_pcie_usage = &vega20_get_pcie_usage, > .need_reset_on_init = &soc15_need_reset_on_init, > .get_pcie_replay_count = &soc15_get_pcie_replay_count, >+ .reset_method = &soc15_asic_reset_method > }; > > static int soc15_common_early_init(void *handle) >@@ -837,6 +987,8 @@ > adev->smc_wreg = NULL; > adev->pcie_rreg = &soc15_pcie_rreg; > adev->pcie_wreg = &soc15_pcie_wreg; >+ adev->pcie_rreg64 = &soc15_pcie_rreg64; >+ adev->pcie_wreg64 = &soc15_pcie_wreg64; > adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; > adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; > adev->didt_rreg = &soc15_didt_rreg; >@@ -993,6 +1145,53 @@ > adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; > } > break; >+ case CHIP_ARCTURUS: >+ adev->asic_funcs = &vega20_asic_funcs; >+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | >+ AMD_CG_SUPPORT_GFX_MGLS | >+ AMD_CG_SUPPORT_GFX_CGCG | >+ AMD_CG_SUPPORT_GFX_CGLS | >+ AMD_CG_SUPPORT_GFX_CP_LS | >+ AMD_CG_SUPPORT_HDP_MGCG | >+ AMD_CG_SUPPORT_HDP_LS | >+ AMD_CG_SUPPORT_SDMA_MGCG | >+ AMD_CG_SUPPORT_SDMA_LS | >+ AMD_CG_SUPPORT_MC_MGCG | >+ AMD_CG_SUPPORT_MC_LS; >+ adev->pg_flags = 0; >+ adev->external_rev_id = adev->rev_id + 0x32; >+ break; >+ case CHIP_RENOIR: >+ adev->asic_funcs = &soc15_asic_funcs; >+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | >+ AMD_CG_SUPPORT_GFX_MGLS | >+ AMD_CG_SUPPORT_GFX_3D_CGCG | >+ AMD_CG_SUPPORT_GFX_3D_CGLS | >+ AMD_CG_SUPPORT_GFX_CGCG | >+ AMD_CG_SUPPORT_GFX_CGLS | >+ AMD_CG_SUPPORT_GFX_CP_LS | >+ AMD_CG_SUPPORT_MC_MGCG | >+ AMD_CG_SUPPORT_MC_LS | >+ AMD_CG_SUPPORT_SDMA_MGCG | >+ AMD_CG_SUPPORT_SDMA_LS | >+ AMD_CG_SUPPORT_BIF_LS | >+ AMD_CG_SUPPORT_HDP_LS | >+ AMD_CG_SUPPORT_ROM_MGCG | >+ AMD_CG_SUPPORT_VCN_MGCG | >+ AMD_CG_SUPPORT_IH_CG | >+ AMD_CG_SUPPORT_ATHUB_LS | >+ AMD_CG_SUPPORT_ATHUB_MGCG | >+ AMD_CG_SUPPORT_DF_MGCG; >+ adev->pg_flags = AMD_PG_SUPPORT_SDMA | >+ AMD_PG_SUPPORT_VCN | >+ AMD_PG_SUPPORT_VCN_DPG; >+ adev->external_rev_id = adev->rev_id + 0x91; >+ >+ if (adev->pm.pp_feature & PP_GFXOFF_MASK) >+ adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | >+ AMD_PG_SUPPORT_CP | >+ AMD_PG_SUPPORT_RLC_SMU_HS; >+ break; > default: > /* FIXME: not supported yet */ > return -EINVAL; >@@ -1038,21 +1237,18 @@ > int i; > struct amdgpu_ring *ring; > >- /* Two reasons to skip >- * 1, Host driver already programmed them >- * 2, To avoid registers program violations in SR-IOV >- */ >- if (!amdgpu_virt_support_skip_setting(adev)) { >+ /* sdma/ih doorbell range are programed by hypervisor */ >+ if (!amdgpu_sriov_vf(adev)) { > for (i = 0; i < adev->sdma.num_instances; i++) { > ring = &adev->sdma.instance[i].ring; > adev->nbio_funcs->sdma_doorbell_range(adev, i, > ring->use_doorbell, ring->doorbell_index, > adev->doorbell_index.sdma_doorbell_range); > } >- } > >- adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, >+ adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, > adev->irq.ih.doorbell_index); >+ } > } > > static int soc15_common_hw_init(void *handle) >@@ -1129,7 +1325,8 @@ > { > uint32_t def, data; > >- if (adev->asic_type == CHIP_VEGA20) { >+ if (adev->asic_type == CHIP_VEGA20 || >+ adev->asic_type == CHIP_ARCTURUS) { > def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); > > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) >@@ -1248,6 +1445,7 @@ > state == AMD_CG_STATE_GATE ? true : false); > break; > case CHIP_RAVEN: >+ case CHIP_RENOIR: > adev->nbio_funcs->update_medium_grain_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > adev->nbio_funcs->update_medium_grain_light_sleep(adev, >@@ -1261,6 +1459,10 @@ > soc15_update_rom_medium_grain_clock_gating(adev, > state == AMD_CG_STATE_GATE ? true : false); > break; >+ case CHIP_ARCTURUS: >+ soc15_update_hdp_light_sleep(adev, >+ state == AMD_CG_STATE_GATE ? true : false); >+ break; > default: > break; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15_common.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15_common.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15_common.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15_common.h 2019-08-31 15:01:11.851736168 -0500 >@@ -69,9 +69,10 @@ > } \ > } while (0) > >+#define AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(a) (amdgpu_sriov_vf((a)) && !amdgpu_sriov_runtime((a))) > #define WREG32_RLC(reg, value) \ > do { \ >- if (amdgpu_virt_support_rlc_prg_reg(adev)) { \ >+ if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) { \ > uint32_t i = 0; \ > uint32_t retries = 50000; \ > uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \ >@@ -96,7 +97,7 @@ > #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ > do { \ > uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ >- if (amdgpu_virt_support_rlc_prg_reg(adev)) { \ >+ if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) { \ > uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \ > uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \ > uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15.h 2019-08-31 15:01:11.851736168 -0500 >@@ -77,6 +77,7 @@ > > int vega10_reg_base_init(struct amdgpu_device *adev); > int vega20_reg_base_init(struct amdgpu_device *adev); >+int arct_reg_base_init(struct amdgpu_device *adev); > > void vega10_doorbell_index_init(struct amdgpu_device *adev); > void vega20_doorbell_index_init(struct amdgpu_device *adev); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 2019-08-31 15:01:11.851736168 -0500 >@@ -0,0 +1,255 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#include "umc_v6_1.h" >+#include "amdgpu_ras.h" >+#include "amdgpu.h" >+ >+#include "rsmu/rsmu_0_0_2_offset.h" >+#include "rsmu/rsmu_0_0_2_sh_mask.h" >+#include "umc/umc_6_1_1_offset.h" >+#include "umc/umc_6_1_1_sh_mask.h" >+ >+#define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10 >+ >+/* >+ * (addr / 256) * 8192, the higher 26 bits in ErrorAddr >+ * is the index of 8KB block >+ */ >+#define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) >+/* channel index is the index of 256B block */ >+#define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) >+/* offset in 256B block */ >+#define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) >+ >+const uint32_t >+ umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = { >+ {2, 18, 11, 27}, {4, 20, 13, 29}, >+ {1, 17, 8, 24}, {7, 23, 14, 30}, >+ {10, 26, 3, 19}, {12, 28, 5, 21}, >+ {9, 25, 0, 16}, {15, 31, 6, 22} >+}; >+ >+static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev, >+ uint32_t umc_instance) >+{ >+ uint32_t rsmu_umc_index; >+ >+ rsmu_umc_index = RREG32_SOC15(RSMU, 0, >+ mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU); >+ rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, >+ RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, >+ RSMU_UMC_INDEX_MODE_EN, 1); >+ rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, >+ RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, >+ RSMU_UMC_INDEX_INSTANCE, umc_instance); >+ rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, >+ RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, >+ RSMU_UMC_INDEX_WREN, 1 << umc_instance); >+ WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, >+ rsmu_umc_index); >+} >+ >+static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev) >+{ >+ WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, >+ RSMU_UMC_INDEX_MODE_EN, 0); >+} >+ >+static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, >+ uint32_t umc_reg_offset, >+ unsigned long *error_count) >+{ >+ uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; >+ uint32_t ecc_err_cnt, ecc_err_cnt_addr; >+ uint64_t mc_umc_status; >+ uint32_t mc_umc_status_addr; >+ >+ ecc_err_cnt_sel_addr = >+ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); >+ ecc_err_cnt_addr = >+ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); >+ mc_umc_status_addr = >+ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); >+ >+ /* select the lower chip and check the error count */ >+ ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset); >+ ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, >+ EccErrCntCsSel, 0); >+ WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); >+ ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); >+ *error_count += >+ (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - >+ UMC_V6_1_CE_CNT_INIT); >+ /* clear the lower chip err count */ >+ WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); >+ >+ /* select the higher chip and check the err counter */ >+ ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, >+ EccErrCntCsSel, 1); >+ WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); >+ ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); >+ *error_count += >+ (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - >+ UMC_V6_1_CE_CNT_INIT); >+ /* clear the higher chip err count */ >+ WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); >+ >+ /* check for SRAM correctable error >+ MCUMC_STATUS is a 64 bit register */ >+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); >+ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && >+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && >+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) >+ *error_count += 1; >+} >+ >+static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev, >+ uint32_t umc_reg_offset, >+ unsigned long *error_count) >+{ >+ uint64_t mc_umc_status; >+ uint32_t mc_umc_status_addr; >+ >+ mc_umc_status_addr = >+ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); >+ >+ /* check the MCUMC_STATUS */ >+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); >+ if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && >+ (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || >+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || >+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || >+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || >+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) >+ *error_count += 1; >+} >+ >+static void umc_v6_1_query_error_count(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, uint32_t umc_reg_offset, >+ uint32_t channel_index) >+{ >+ umc_v6_1_query_correctable_error_count(adev, umc_reg_offset, >+ &(err_data->ce_count)); >+ umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset, >+ &(err_data->ue_count)); >+} >+ >+static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev, >+ void *ras_error_status) >+{ >+ amdgpu_umc_for_each_channel(umc_v6_1_query_error_count); >+} >+ >+static void umc_v6_1_query_error_address(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, >+ uint32_t umc_reg_offset, uint32_t channel_index) >+{ >+ uint32_t lsb, mc_umc_status_addr; >+ uint64_t mc_umc_status, err_addr; >+ >+ mc_umc_status_addr = >+ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); >+ >+ /* skip error address process if -ENOMEM */ >+ if (!err_data->err_addr) { >+ /* clear umc status */ >+ WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL); >+ return; >+ } >+ >+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); >+ >+ /* calculate error address if ue/ce error is detected */ >+ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && >+ (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || >+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { >+ err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4); >+ >+ /* the lowest lsb bits should be ignored */ >+ lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB); >+ err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); >+ err_addr &= ~((0x1ULL << lsb) - 1); >+ >+ /* translate umc channel address to soc pa, 3 parts are included */ >+ err_data->err_addr[err_data->err_addr_cnt] = >+ ADDR_OF_8KB_BLOCK(err_addr) | >+ ADDR_OF_256B_BLOCK(channel_index) | >+ OFFSET_IN_256B_BLOCK(err_addr); >+ >+ err_data->err_addr_cnt++; >+ } >+ >+ /* clear umc status */ >+ WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL); >+} >+ >+static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, >+ void *ras_error_status) >+{ >+ amdgpu_umc_for_each_channel(umc_v6_1_query_error_address); >+} >+ >+static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev, >+ struct ras_err_data *err_data, >+ uint32_t umc_reg_offset, uint32_t channel_index) >+{ >+ uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; >+ uint32_t ecc_err_cnt_addr; >+ >+ ecc_err_cnt_sel_addr = >+ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); >+ ecc_err_cnt_addr = >+ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); >+ >+ /* select the lower chip and check the error count */ >+ ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset); >+ ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, >+ EccErrCntCsSel, 0); >+ /* set ce error interrupt type to APIC based interrupt */ >+ ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, >+ EccErrInt, 0x1); >+ WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); >+ /* set error count to initial value */ >+ WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); >+ >+ /* select the higher chip and check the err counter */ >+ ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, >+ EccErrCntCsSel, 1); >+ WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); >+ WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); >+} >+ >+static void umc_v6_1_ras_init(struct amdgpu_device *adev) >+{ >+ void *ras_error_status = NULL; >+ >+ amdgpu_umc_for_each_channel(umc_v6_1_ras_init_per_channel); >+} >+ >+const struct amdgpu_umc_funcs umc_v6_1_funcs = { >+ .ras_init = umc_v6_1_ras_init, >+ .query_ras_error_count = umc_v6_1_query_ras_error_count, >+ .query_ras_error_address = umc_v6_1_query_ras_error_address, >+ .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode, >+ .disable_umc_index_mode = umc_v6_1_disable_umc_index_mode, >+}; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h 2019-08-31 15:01:11.851736168 -0500 >@@ -0,0 +1,51 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+#ifndef __UMC_V6_1_H__ >+#define __UMC_V6_1_H__ >+ >+#include "soc15_common.h" >+#include "amdgpu.h" >+ >+/* HBM Memory Channel Width */ >+#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH 128 >+/* number of umc channel instance with memory map register access */ >+#define UMC_V6_1_CHANNEL_INSTANCE_NUM 4 >+/* number of umc instance with memory map register access */ >+#define UMC_V6_1_UMC_INSTANCE_NUM 8 >+/* total channel instances in one umc block */ >+#define UMC_V6_1_TOTAL_CHANNEL_NUM (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM) >+/* UMC regiser per channel offset */ >+#define UMC_V6_1_PER_CHANNEL_OFFSET 0x800 >+ >+/* EccErrCnt max value */ >+#define UMC_V6_1_CE_CNT_MAX 0xffff >+/* umc ce interrupt threshold */ >+#define UMC_V6_1_CE_INT_THRESHOLD 0xffff >+/* umc ce count initial value */ >+#define UMC_V6_1_CE_CNT_INIT (UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD) >+ >+extern const struct amdgpu_umc_funcs umc_v6_1_funcs; >+extern const uint32_t >+ umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM]; >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 2019-08-31 15:01:11.851736168 -0500 >@@ -1763,7 +1763,7 @@ > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .get_rptr = uvd_v7_0_ring_get_rptr, > .get_wptr = uvd_v7_0_ring_get_wptr, > .set_wptr = uvd_v7_0_ring_set_wptr, >@@ -1796,7 +1796,7 @@ > .nop = HEVC_ENC_CMD_NO_OP, > .support_64bit_ptrs = false, > .no_user_fence = true, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .get_rptr = uvd_v7_0_enc_ring_get_rptr, > .get_wptr = uvd_v7_0_enc_ring_get_wptr, > .set_wptr = uvd_v7_0_enc_ring_set_wptr, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 2019-08-31 15:01:11.851736168 -0500 >@@ -1070,7 +1070,7 @@ > .nop = VCE_CMD_NO_OP, > .support_64bit_ptrs = false, > .no_user_fence = true, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .get_rptr = vce_v4_0_ring_get_rptr, > .get_wptr = vce_v4_0_ring_get_wptr, > .set_wptr = vce_v4_0_ring_set_wptr, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 2019-08-31 15:01:11.851736168 -0500 >@@ -63,6 +63,7 @@ > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >+ adev->vcn.num_vcn_inst = 1; > adev->vcn.num_enc_rings = 2; > > vcn_v1_0_set_dec_ring_funcs(adev); >@@ -87,20 +88,21 @@ > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > /* VCN DEC TRAP */ >- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq); >+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, >+ VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); > if (r) > return r; > > /* VCN ENC TRAP */ > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { > r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, >- &adev->vcn.irq); >+ &adev->vcn.inst->irq); > if (r) > return r; > } > > /* VCN JPEG TRAP */ >- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq); >+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.inst->irq); > if (r) > return r; > >@@ -122,39 +124,39 @@ > if (r) > return r; > >- ring = &adev->vcn.ring_dec; >+ ring = &adev->vcn.inst->ring_dec; > sprintf(ring->name, "vcn_dec"); >- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); > if (r) > return r; > >- adev->vcn.internal.scratch9 = adev->vcn.external.scratch9 = >+ adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = > SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); >- adev->vcn.internal.data0 = adev->vcn.external.data0 = >+ adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = > SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); >- adev->vcn.internal.data1 = adev->vcn.external.data1 = >+ adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = > SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); >- adev->vcn.internal.cmd = adev->vcn.external.cmd = >+ adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = > SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); >- adev->vcn.internal.nop = adev->vcn.external.nop = >+ adev->vcn.internal.nop = adev->vcn.inst->external.nop = > SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >- ring = &adev->vcn.ring_enc[i]; >+ ring = &adev->vcn.inst->ring_enc[i]; > sprintf(ring->name, "vcn_enc%d", i); >- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); > if (r) > return r; > } > >- ring = &adev->vcn.ring_jpeg; >+ ring = &adev->vcn.inst->ring_jpeg; > sprintf(ring->name, "vcn_jpeg"); >- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); > if (r) > return r; > > adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; >- adev->vcn.internal.jpeg_pitch = adev->vcn.external.jpeg_pitch = >+ adev->vcn.internal.jpeg_pitch = adev->vcn.inst->external.jpeg_pitch = > SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); > > return 0; >@@ -191,7 +193,7 @@ > static int vcn_v1_0_hw_init(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; >- struct amdgpu_ring *ring = &adev->vcn.ring_dec; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; > int i, r; > > r = amdgpu_ring_test_helper(ring); >@@ -199,14 +201,14 @@ > goto done; > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >- ring = &adev->vcn.ring_enc[i]; >+ ring = &adev->vcn.inst->ring_enc[i]; > ring->sched.ready = true; > r = amdgpu_ring_test_helper(ring); > if (r) > goto done; > } > >- ring = &adev->vcn.ring_jpeg; >+ ring = &adev->vcn.inst->ring_jpeg; > r = amdgpu_ring_test_helper(ring); > if (r) > goto done; >@@ -229,7 +231,7 @@ > static int vcn_v1_0_hw_fini(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; >- struct amdgpu_ring *ring = &adev->vcn.ring_dec; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; > > if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || > RREG32_SOC15(VCN, 0, mmUVD_STATUS)) >@@ -304,9 +306,9 @@ > offset = 0; > } else { > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr)); >+ lower_32_bits(adev->vcn.inst->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr)); >+ upper_32_bits(adev->vcn.inst->gpu_addr)); > offset = size; > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, > AMDGPU_UVD_FIRMWARE_OFFSET >> 3); >@@ -316,17 +318,17 @@ > > /* cache window 1: stack */ > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr + offset)); >+ lower_32_bits(adev->vcn.inst->gpu_addr + offset)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr + offset)); >+ upper_32_bits(adev->vcn.inst->gpu_addr + offset)); > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); > > /* cache window 2: context */ > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); >+ lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); >+ upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); > >@@ -374,9 +376,9 @@ > offset = 0; > } else { > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); >+ lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); >+ upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); > offset = size; > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, > AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); >@@ -386,9 +388,9 @@ > > /* cache window 1: stack */ > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); >+ lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); >+ upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, > 0xFFFFFFFF, 0); > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, >@@ -396,10 +398,10 @@ > > /* cache window 2: context */ > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), >+ lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), > 0xFFFFFFFF, 0); > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), >+ upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), > 0xFFFFFFFF, 0); > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); > WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, >@@ -779,7 +781,7 @@ > */ > static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) > { >- struct amdgpu_ring *ring = &adev->vcn.ring_dec; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; > uint32_t rb_bufsz, tmp; > uint32_t lmi_swap_cntl; > int i, j, r; >@@ -932,21 +934,21 @@ > WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, > ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); > >- ring = &adev->vcn.ring_enc[0]; >+ ring = &adev->vcn.inst->ring_enc[0]; > WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); > >- ring = &adev->vcn.ring_enc[1]; >+ ring = &adev->vcn.inst->ring_enc[1]; > WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); > >- ring = &adev->vcn.ring_jpeg; >+ ring = &adev->vcn.inst->ring_jpeg; > WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); > WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | > UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); >@@ -968,7 +970,7 @@ > > static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) > { >- struct amdgpu_ring *ring = &adev->vcn.ring_dec; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; > uint32_t rb_bufsz, tmp; > uint32_t lmi_swap_cntl; > >@@ -1106,7 +1108,7 @@ > ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); > > /* initialize JPEG wptr */ >- ring = &adev->vcn.ring_jpeg; >+ ring = &adev->vcn.inst->ring_jpeg; > ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); > > /* copy patch commands to the jpeg ring */ >@@ -1255,21 +1257,21 @@ > UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); > > /* Restore */ >- ring = &adev->vcn.ring_enc[0]; >+ ring = &adev->vcn.inst->ring_enc[0]; > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); > WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); > >- ring = &adev->vcn.ring_enc[1]; >+ ring = &adev->vcn.inst->ring_enc[1]; > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); > WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); > >- ring = &adev->vcn.ring_dec; >+ ring = &adev->vcn.inst->ring_dec; > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); > SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, >@@ -1315,7 +1317,7 @@ > UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); > > /* Restore */ >- ring = &adev->vcn.ring_jpeg; >+ ring = &adev->vcn.inst->ring_jpeg; > WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); > WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, > UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | >@@ -1329,7 +1331,7 @@ > WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, > UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); > >- ring = &adev->vcn.ring_dec; >+ ring = &adev->vcn.inst->ring_dec; > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); > SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, >@@ -1596,7 +1598,7 @@ > { > struct amdgpu_device *adev = ring->adev; > >- if (ring == &adev->vcn.ring_enc[0]) >+ if (ring == &adev->vcn.inst->ring_enc[0]) > return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); > else > return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); >@@ -1613,7 +1615,7 @@ > { > struct amdgpu_device *adev = ring->adev; > >- if (ring == &adev->vcn.ring_enc[0]) >+ if (ring == &adev->vcn.inst->ring_enc[0]) > return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); > else > return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); >@@ -1630,7 +1632,7 @@ > { > struct amdgpu_device *adev = ring->adev; > >- if (ring == &adev->vcn.ring_enc[0]) >+ if (ring == &adev->vcn.inst->ring_enc[0]) > WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, > lower_32_bits(ring->wptr)); > else >@@ -2114,16 +2116,16 @@ > > switch (entry->src_id) { > case 124: >- amdgpu_fence_process(&adev->vcn.ring_dec); >+ amdgpu_fence_process(&adev->vcn.inst->ring_dec); > break; > case 119: >- amdgpu_fence_process(&adev->vcn.ring_enc[0]); >+ amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); > break; > case 120: >- amdgpu_fence_process(&adev->vcn.ring_enc[1]); >+ amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); > break; > case 126: >- amdgpu_fence_process(&adev->vcn.ring_jpeg); >+ amdgpu_fence_process(&adev->vcn.inst->ring_jpeg); > break; > default: > DRM_ERROR("Unhandled interrupt: %d %d\n", >@@ -2198,7 +2200,7 @@ > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .get_rptr = vcn_v1_0_dec_ring_get_rptr, > .get_wptr = vcn_v1_0_dec_ring_get_wptr, > .set_wptr = vcn_v1_0_dec_ring_set_wptr, >@@ -2232,7 +2234,7 @@ > .nop = VCN_ENC_CMD_NO_OP, > .support_64bit_ptrs = false, > .no_user_fence = true, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .get_rptr = vcn_v1_0_enc_ring_get_rptr, > .get_wptr = vcn_v1_0_enc_ring_get_wptr, > .set_wptr = vcn_v1_0_enc_ring_set_wptr, >@@ -2264,7 +2266,7 @@ > .nop = PACKET0(0x81ff, 0), > .support_64bit_ptrs = false, > .no_user_fence = true, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .extra_dw = 64, > .get_rptr = vcn_v1_0_jpeg_ring_get_rptr, > .get_wptr = vcn_v1_0_jpeg_ring_get_wptr, >@@ -2295,7 +2297,7 @@ > > static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) > { >- adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; >+ adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; > DRM_INFO("VCN decode is enabled in VM mode\n"); > } > >@@ -2304,14 +2306,14 @@ > int i; > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) >- adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; >+ adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; > > DRM_INFO("VCN encode is enabled in VM mode\n"); > } > > static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev) > { >- adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs; >+ adev->vcn.inst->ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs; > DRM_INFO("VCN jpeg decode is enabled in VM mode\n"); > } > >@@ -2322,8 +2324,8 @@ > > static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) > { >- adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2; >- adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs; >+ adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; >+ adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; > } > > const struct amdgpu_ip_block_version vcn_v1_0_ip_block = >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 2019-08-31 15:08:26.826774600 -0500 >@@ -22,7 +22,7 @@ > */ > > #include <linux/firmware.h> >-#include <drm/drmP.h> >+ > #include "amdgpu.h" > #include "amdgpu_vcn.h" > #include "soc15.h" >@@ -92,6 +92,7 @@ > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > >+ adev->vcn.num_vcn_inst = 1; > adev->vcn.num_enc_rings = 2; > > vcn_v2_0_set_dec_ring_funcs(adev); >@@ -118,7 +119,7 @@ > /* VCN DEC TRAP */ > r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, > VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, >- &adev->vcn.irq); >+ &adev->vcn.inst->irq); > if (r) > return r; > >@@ -126,15 +127,14 @@ > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { > r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, > i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, >- &adev->vcn.irq); >+ &adev->vcn.inst->irq); > if (r) > return r; > } > > /* VCN JPEG TRAP */ > r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, >- VCN_2_0__SRCID__JPEG_DECODE, >- &adev->vcn.irq); >+ VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq); > if (r) > return r; > >@@ -156,49 +156,56 @@ > if (r) > return r; > >- ring = &adev->vcn.ring_dec; >+ ring = &adev->vcn.inst->ring_dec; > > ring->use_doorbell = true; > ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; > > sprintf(ring->name, "vcn_dec"); >- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); > if (r) > return r; > >+ adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; >+ adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; >+ adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; >+ adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; >+ adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; >+ adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; >+ > adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; >- adev->vcn.external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); >+ adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); > adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; >- adev->vcn.external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); >+ adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); > adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; >- adev->vcn.external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); >+ adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); > adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; >- adev->vcn.external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); >+ adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); > adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; >- adev->vcn.external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); >+ adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >- ring = &adev->vcn.ring_enc[i]; >+ ring = &adev->vcn.inst->ring_enc[i]; > ring->use_doorbell = true; > ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; > sprintf(ring->name, "vcn_enc%d", i); >- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); > if (r) > return r; > } > >- ring = &adev->vcn.ring_jpeg; >+ ring = &adev->vcn.inst->ring_jpeg; > ring->use_doorbell = true; > ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; > sprintf(ring->name, "vcn_jpeg"); >- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); > if (r) > return r; > > adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; > > adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; >- adev->vcn.external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); >+ adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); > > return 0; > } >@@ -234,11 +241,11 @@ > static int vcn_v2_0_hw_init(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; >- struct amdgpu_ring *ring = &adev->vcn.ring_dec; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; > int i, r; > > adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell, >- ring->doorbell_index); >+ ring->doorbell_index, 0); > > ring->sched.ready = true; > r = amdgpu_ring_test_ring(ring); >@@ -248,7 +255,7 @@ > } > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >- ring = &adev->vcn.ring_enc[i]; >+ ring = &adev->vcn.inst->ring_enc[i]; > ring->sched.ready = true; > r = amdgpu_ring_test_ring(ring); > if (r) { >@@ -257,7 +264,7 @@ > } > } > >- ring = &adev->vcn.ring_jpeg; >+ ring = &adev->vcn.inst->ring_jpeg; > ring->sched.ready = true; > r = amdgpu_ring_test_ring(ring); > if (r) { >@@ -283,7 +290,7 @@ > static int vcn_v2_0_hw_fini(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; >- struct amdgpu_ring *ring = &adev->vcn.ring_dec; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; > int i; > > if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || >@@ -294,11 +301,11 @@ > ring->sched.ready = false; > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >- ring = &adev->vcn.ring_enc[i]; >+ ring = &adev->vcn.inst->ring_enc[i]; > ring->sched.ready = false; > } > >- ring = &adev->vcn.ring_jpeg; >+ ring = &adev->vcn.inst->ring_jpeg; > ring->sched.ready = false; > > return 0; >@@ -368,9 +375,9 @@ > offset = 0; > } else { > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr)); >+ lower_32_bits(adev->vcn.inst->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr)); >+ upper_32_bits(adev->vcn.inst->gpu_addr)); > offset = size; > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, > AMDGPU_UVD_FIRMWARE_OFFSET >> 3); >@@ -380,17 +387,17 @@ > > /* cache window 1: stack */ > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr + offset)); >+ lower_32_bits(adev->vcn.inst->gpu_addr + offset)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr + offset)); >+ upper_32_bits(adev->vcn.inst->gpu_addr + offset)); > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); > > /* cache window 2: context */ > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, >- lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); >+ lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, >- upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); >+ upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); > WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); > >@@ -426,10 +433,10 @@ > } else { > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), >- lower_32_bits(adev->vcn.gpu_addr), 0, indirect); >+ lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), >- upper_32_bits(adev->vcn.gpu_addr), 0, indirect); >+ upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); > offset = size; > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), >@@ -447,10 +454,10 @@ > if (!indirect) { > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), >- lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect); >+ lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), >- upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect); >+ upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); > } else { >@@ -467,10 +474,10 @@ > /* cache window 2: context */ > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), >- lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); >+ lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), >- upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); >+ upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( > UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); > WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( >@@ -658,7 +665,7 @@ > */ > static int jpeg_v2_0_start(struct amdgpu_device *adev) > { >- struct amdgpu_ring *ring = &adev->vcn.ring_jpeg; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg; > uint32_t tmp; > int r = 0; > >@@ -920,7 +927,7 @@ > > static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) > { >- struct amdgpu_ring *ring = &adev->vcn.ring_dec; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; > uint32_t rb_bufsz, tmp; > > vcn_v2_0_enable_static_power_gating(adev); >@@ -1046,7 +1053,7 @@ > > static int vcn_v2_0_start(struct amdgpu_device *adev) > { >- struct amdgpu_ring *ring = &adev->vcn.ring_dec; >+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; > uint32_t rb_bufsz, tmp; > uint32_t lmi_swap_cntl; > int i, j, r; >@@ -1197,14 +1204,14 @@ > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > lower_32_bits(ring->wptr)); > >- ring = &adev->vcn.ring_enc[0]; >+ ring = &adev->vcn.inst->ring_enc[0]; > WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); > >- ring = &adev->vcn.ring_enc[1]; >+ ring = &adev->vcn.inst->ring_enc[1]; > WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); >@@ -1351,14 +1358,14 @@ > UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); > > /* Restore */ >- ring = &adev->vcn.ring_enc[0]; >+ ring = &adev->vcn.inst->ring_enc[0]; > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); > WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); > >- ring = &adev->vcn.ring_enc[1]; >+ ring = &adev->vcn.inst->ring_enc[1]; > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); > WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); >@@ -1480,11 +1487,13 @@ > * > * Write a start command to the ring. > */ >-static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) >+void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) > { >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); >+ struct amdgpu_device *adev = ring->adev; >+ >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); > amdgpu_ring_write(ring, 0); >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); > amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); > } > >@@ -1495,9 +1504,11 @@ > * > * Write a end command to the ring. > */ >-static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) >+void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) > { >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); >+ struct amdgpu_device *adev = ring->adev; >+ >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); > amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); > } > >@@ -1508,14 +1519,15 @@ > * > * Write a nop command to the ring. > */ >-static void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) >+void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) > { >+ struct amdgpu_device *adev = ring->adev; > int i; > > WARN_ON(ring->wptr % 2 || count % 2); > > for (i = 0; i < count / 2; i++) { >- amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); > amdgpu_ring_write(ring, 0); > } > } >@@ -1528,30 +1540,31 @@ > * > * Write a fence and a trap command to the ring. > */ >-static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, >- unsigned flags) >+void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, >+ unsigned flags) > { >- WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); >+ struct amdgpu_device *adev = ring->adev; > >- amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID_INTERNAL_OFFSET, 0)); >+ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); > amdgpu_ring_write(ring, seq); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); > amdgpu_ring_write(ring, addr & 0xffffffff); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); > amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); > amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); > amdgpu_ring_write(ring, 0); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); > amdgpu_ring_write(ring, 0); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); > > amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); > } >@@ -1564,44 +1577,46 @@ > * > * Write ring commands to execute the indirect buffer > */ >-static void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, >- struct amdgpu_job *job, >- struct amdgpu_ib *ib, >- uint32_t flags) >+void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, >+ struct amdgpu_job *job, >+ struct amdgpu_ib *ib, >+ uint32_t flags) > { >+ struct amdgpu_device *adev = ring->adev; > unsigned vmid = AMDGPU_JOB_GET_VMID(job); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); > amdgpu_ring_write(ring, vmid); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); > amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); >- amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); > amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); >- amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); > amdgpu_ring_write(ring, ib->length_dw); > } > >-static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, >- uint32_t reg, uint32_t val, >- uint32_t mask) >+void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, >+ uint32_t val, uint32_t mask) > { >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); >+ struct amdgpu_device *adev = ring->adev; >+ >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); > amdgpu_ring_write(ring, reg << 2); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); > amdgpu_ring_write(ring, val); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); > amdgpu_ring_write(ring, mask); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); > > amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); > } > >-static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, >- unsigned vmid, uint64_t pd_addr) >+void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, >+ unsigned vmid, uint64_t pd_addr) > { > struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; > uint32_t data0, data1, mask; >@@ -1615,16 +1630,18 @@ > vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); > } > >-static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, >- uint32_t reg, uint32_t val) >+void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, >+ uint32_t reg, uint32_t val) > { >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); >+ struct amdgpu_device *adev = ring->adev; >+ >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); > amdgpu_ring_write(ring, reg << 2); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); > amdgpu_ring_write(ring, val); > >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); > > amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); > } >@@ -1640,7 +1657,7 @@ > { > struct amdgpu_device *adev = ring->adev; > >- if (ring == &adev->vcn.ring_enc[0]) >+ if (ring == &adev->vcn.inst->ring_enc[0]) > return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); > else > return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); >@@ -1657,7 +1674,7 @@ > { > struct amdgpu_device *adev = ring->adev; > >- if (ring == &adev->vcn.ring_enc[0]) { >+ if (ring == &adev->vcn.inst->ring_enc[0]) { > if (ring->use_doorbell) > return adev->wb.wb[ring->wptr_offs]; > else >@@ -1681,7 +1698,7 @@ > { > struct amdgpu_device *adev = ring->adev; > >- if (ring == &adev->vcn.ring_enc[0]) { >+ if (ring == &adev->vcn.inst->ring_enc[0]) { > if (ring->use_doorbell) { > adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); > WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); >@@ -1706,8 +1723,8 @@ > * > * Write enc a fence and a trap command to the ring. > */ >-static void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, >- u64 seq, unsigned flags) >+void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, >+ u64 seq, unsigned flags) > { > WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); > >@@ -1718,7 +1735,7 @@ > amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); > } > >-static void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) >+void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) > { > amdgpu_ring_write(ring, VCN_ENC_CMD_END); > } >@@ -1731,10 +1748,10 @@ > * > * Write enc ring commands to execute the indirect buffer > */ >-static void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, >- struct amdgpu_job *job, >- struct amdgpu_ib *ib, >- uint32_t flags) >+void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, >+ struct amdgpu_job *job, >+ struct amdgpu_ib *ib, >+ uint32_t flags) > { > unsigned vmid = AMDGPU_JOB_GET_VMID(job); > >@@ -1745,9 +1762,8 @@ > amdgpu_ring_write(ring, ib->length_dw); > } > >-static void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, >- uint32_t reg, uint32_t val, >- uint32_t mask) >+void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, >+ uint32_t val, uint32_t mask) > { > amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); > amdgpu_ring_write(ring, reg << 2); >@@ -1755,8 +1771,8 @@ > amdgpu_ring_write(ring, val); > } > >-static void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, >- unsigned int vmid, uint64_t pd_addr) >+void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, >+ unsigned int vmid, uint64_t pd_addr) > { > struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; > >@@ -1767,8 +1783,7 @@ > lower_32_bits(pd_addr), 0xffffffff); > } > >-static void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, >- uint32_t reg, uint32_t val) >+void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) > { > amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); > amdgpu_ring_write(ring, reg << 2); >@@ -1832,7 +1847,7 @@ > * > * Write a start command to the ring. > */ >-static void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) >+void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) > { > amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, > 0, 0, PACKETJ_TYPE0)); >@@ -1850,7 +1865,7 @@ > * > * Write a end command to the ring. > */ >-static void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) >+void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) > { > amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, > 0, 0, PACKETJ_TYPE0)); >@@ -1869,8 +1884,8 @@ > * > * Write a fence and a trap command to the ring. > */ >-static void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, >- unsigned flags) >+void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, >+ unsigned flags) > { > WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); > >@@ -1918,10 +1933,10 @@ > * > * Write ring commands to execute the indirect buffer. > */ >-static void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, >- struct amdgpu_job *job, >- struct amdgpu_ib *ib, >- uint32_t flags) >+void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, >+ struct amdgpu_job *job, >+ struct amdgpu_ib *ib, >+ uint32_t flags) > { > unsigned vmid = AMDGPU_JOB_GET_VMID(job); > >@@ -1969,9 +1984,8 @@ > amdgpu_ring_write(ring, 0x2); > } > >-static void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, >- uint32_t reg, uint32_t val, >- uint32_t mask) >+void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, >+ uint32_t val, uint32_t mask) > { > uint32_t reg_offset = (reg << 2); > >@@ -1997,8 +2011,8 @@ > amdgpu_ring_write(ring, mask); > } > >-static void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, >- unsigned vmid, uint64_t pd_addr) >+void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, >+ unsigned vmid, uint64_t pd_addr) > { > struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; > uint32_t data0, data1, mask; >@@ -2012,8 +2026,7 @@ > vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); > } > >-static void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, >- uint32_t reg, uint32_t val) >+void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) > { > uint32_t reg_offset = (reg << 2); > >@@ -2031,7 +2044,7 @@ > amdgpu_ring_write(ring, val); > } > >-static void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) >+void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) > { > int i; > >@@ -2059,16 +2072,16 @@ > > switch (entry->src_id) { > case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: >- amdgpu_fence_process(&adev->vcn.ring_dec); >+ amdgpu_fence_process(&adev->vcn.inst->ring_dec); > break; > case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: >- amdgpu_fence_process(&adev->vcn.ring_enc[0]); >+ amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); > break; > case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: >- amdgpu_fence_process(&adev->vcn.ring_enc[1]); >+ amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); > break; > case VCN_2_0__SRCID__JPEG_DECODE: >- amdgpu_fence_process(&adev->vcn.ring_jpeg); >+ amdgpu_fence_process(&adev->vcn.inst->ring_jpeg); > break; > default: > DRM_ERROR("Unhandled interrupt: %d %d\n", >@@ -2086,20 +2099,20 @@ > unsigned i; > int r; > >- WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD); >+ WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); > r = amdgpu_ring_alloc(ring, 4); > if (r) > return r; >- amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); >+ amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); > amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); > amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); > amdgpu_ring_write(ring, 0xDEADBEEF); > amdgpu_ring_commit(ring); > for (i = 0; i < adev->usec_timeout; i++) { >- tmp = RREG32(adev->vcn.external.scratch9); >+ tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); > if (tmp == 0xDEADBEEF) > break; >- DRM_UDELAY(1); >+ udelay(1); > } > > if (i >= adev->usec_timeout) >@@ -2158,7 +2171,7 @@ > static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_DEC, > .align_mask = 0xf, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .get_rptr = vcn_v2_0_dec_ring_get_rptr, > .get_wptr = vcn_v2_0_dec_ring_get_wptr, > .set_wptr = vcn_v2_0_dec_ring_set_wptr, >@@ -2189,7 +2202,7 @@ > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .get_rptr = vcn_v2_0_enc_ring_get_rptr, > .get_wptr = vcn_v2_0_enc_ring_get_wptr, > .set_wptr = vcn_v2_0_enc_ring_set_wptr, >@@ -2218,7 +2231,7 @@ > static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_JPEG, > .align_mask = 0xf, >- .vmhub = AMDGPU_MMHUB, >+ .vmhub = AMDGPU_MMHUB_0, > .get_rptr = vcn_v2_0_jpeg_ring_get_rptr, > .get_wptr = vcn_v2_0_jpeg_ring_get_wptr, > .set_wptr = vcn_v2_0_jpeg_ring_set_wptr, >@@ -2247,7 +2260,7 @@ > > static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) > { >- adev->vcn.ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; >+ adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; > DRM_INFO("VCN decode is enabled in VM mode\n"); > } > >@@ -2256,14 +2269,14 @@ > int i; > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) >- adev->vcn.ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; >+ adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; > > DRM_INFO("VCN encode is enabled in VM mode\n"); > } > > static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev) > { >- adev->vcn.ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs; >+ adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs; > DRM_INFO("VCN jpeg decode is enabled in VM mode\n"); > } > >@@ -2274,8 +2287,8 @@ > > static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) > { >- adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2; >- adev->vcn.irq.funcs = &vcn_v2_0_irq_funcs; >+ adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; >+ adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; > } > > const struct amdgpu_ip_block_version vcn_v2_0_ip_block = >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h 2019-08-31 15:01:11.851736168 -0500 >@@ -24,6 +24,44 @@ > #ifndef __VCN_V2_0_H__ > #define __VCN_V2_0_H__ > >+extern void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring); >+extern void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring); >+extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); >+extern void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, >+ unsigned flags); >+extern void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, >+ struct amdgpu_ib *ib, uint32_t flags); >+extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, >+ uint32_t val, uint32_t mask); >+extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, >+ unsigned vmid, uint64_t pd_addr); >+extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, >+ uint32_t reg, uint32_t val); >+ >+extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring); >+extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, >+ u64 seq, unsigned flags); >+extern void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, >+ struct amdgpu_ib *ib, uint32_t flags); >+extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, >+ uint32_t val, uint32_t mask); >+extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, >+ unsigned int vmid, uint64_t pd_addr); >+extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); >+ >+extern void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring); >+extern void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring); >+extern void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, >+ unsigned flags); >+extern void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, >+ struct amdgpu_ib *ib, uint32_t flags); >+extern void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, >+ uint32_t val, uint32_t mask); >+extern void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, >+ unsigned vmid, uint64_t pd_addr); >+extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); >+extern void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count); >+ > extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block; > > #endif /* __VCN_V2_0_H__ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 2019-08-31 15:01:11.852736168 -0500 >@@ -0,0 +1,1414 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+ >+#include <linux/firmware.h> >+ >+#include "amdgpu.h" >+#include "amdgpu_vcn.h" >+#include "soc15.h" >+#include "soc15d.h" >+#include "vcn_v2_0.h" >+ >+#include "vcn/vcn_2_5_offset.h" >+#include "vcn/vcn_2_5_sh_mask.h" >+#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" >+ >+#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 >+#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f >+#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 >+#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 >+#define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 >+#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 >+#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d >+ >+#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 >+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 >+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 >+#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c >+ >+#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f >+ >+#define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 >+ >+static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); >+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); >+static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev); >+static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); >+static int vcn_v2_5_set_powergating_state(void *handle, >+ enum amd_powergating_state state); >+ >+static int amdgpu_ih_clientid_vcns[] = { >+ SOC15_IH_CLIENTID_VCN, >+ SOC15_IH_CLIENTID_VCN1 >+}; >+ >+/** >+ * vcn_v2_5_early_init - set function pointers >+ * >+ * @handle: amdgpu_device pointer >+ * >+ * Set ring and irq function pointers >+ */ >+static int vcn_v2_5_early_init(void *handle) >+{ >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ if (adev->asic_type == CHIP_ARCTURUS) { >+ u32 harvest; >+ int i; >+ >+ adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS; >+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) { >+ harvest = RREG32_SOC15(UVD, i, mmCC_UVD_HARVESTING); >+ if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) >+ adev->vcn.harvest_config |= 1 << i; >+ } >+ >+ if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | >+ AMDGPU_VCN_HARVEST_VCN1)) >+ /* both instances are harvested, disable the block */ >+ return -ENOENT; >+ } else >+ adev->vcn.num_vcn_inst = 1; >+ >+ adev->vcn.num_enc_rings = 2; >+ >+ vcn_v2_5_set_dec_ring_funcs(adev); >+ vcn_v2_5_set_enc_ring_funcs(adev); >+ vcn_v2_5_set_jpeg_ring_funcs(adev); >+ vcn_v2_5_set_irq_funcs(adev); >+ >+ return 0; >+} >+ >+/** >+ * vcn_v2_5_sw_init - sw init for VCN block >+ * >+ * @handle: amdgpu_device pointer >+ * >+ * Load firmware and sw initialization >+ */ >+static int vcn_v2_5_sw_init(void *handle) >+{ >+ struct amdgpu_ring *ring; >+ int i, j, r; >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ >+ for (j = 0; j < adev->vcn.num_vcn_inst; j++) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ /* VCN DEC TRAP */ >+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], >+ VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); >+ if (r) >+ return r; >+ >+ /* VCN ENC TRAP */ >+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], >+ i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); >+ if (r) >+ return r; >+ } >+ >+ /* VCN JPEG TRAP */ >+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], >+ VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[j].irq); >+ if (r) >+ return r; >+ } >+ >+ r = amdgpu_vcn_sw_init(adev); >+ if (r) >+ return r; >+ >+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { >+ const struct common_firmware_header *hdr; >+ hdr = (const struct common_firmware_header *)adev->vcn.fw->data; >+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; >+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; >+ adev->firmware.fw_size += >+ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); >+ >+ if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) { >+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; >+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; >+ adev->firmware.fw_size += >+ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); >+ } >+ DRM_INFO("PSP loading VCN firmware\n"); >+ } >+ >+ r = amdgpu_vcn_resume(adev); >+ if (r) >+ return r; >+ >+ for (j = 0; j < adev->vcn.num_vcn_inst; j++) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; >+ adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; >+ adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; >+ adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; >+ adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; >+ adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; >+ >+ adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; >+ adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9); >+ adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; >+ adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0); >+ adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; >+ adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1); >+ adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; >+ adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD); >+ adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; >+ adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP); >+ >+ adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; >+ adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH); >+ >+ ring = &adev->vcn.inst[j].ring_dec; >+ ring->use_doorbell = true; >+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8*j; >+ sprintf(ring->name, "vcn_dec_%d", j); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0); >+ if (r) >+ return r; >+ >+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >+ ring = &adev->vcn.inst[j].ring_enc[i]; >+ ring->use_doorbell = true; >+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i + 8*j; >+ sprintf(ring->name, "vcn_enc_%d.%d", j, i); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0); >+ if (r) >+ return r; >+ } >+ >+ ring = &adev->vcn.inst[j].ring_jpeg; >+ ring->use_doorbell = true; >+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8*j; >+ sprintf(ring->name, "vcn_jpeg_%d", j); >+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0); >+ if (r) >+ return r; >+ } >+ >+ return 0; >+} >+ >+/** >+ * vcn_v2_5_sw_fini - sw fini for VCN block >+ * >+ * @handle: amdgpu_device pointer >+ * >+ * VCN suspend and free up sw allocation >+ */ >+static int vcn_v2_5_sw_fini(void *handle) >+{ >+ int r; >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ >+ r = amdgpu_vcn_suspend(adev); >+ if (r) >+ return r; >+ >+ r = amdgpu_vcn_sw_fini(adev); >+ >+ return r; >+} >+ >+/** >+ * vcn_v2_5_hw_init - start and test VCN block >+ * >+ * @handle: amdgpu_device pointer >+ * >+ * Initialize the hardware, boot up the VCPU and do some testing >+ */ >+static int vcn_v2_5_hw_init(void *handle) >+{ >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ struct amdgpu_ring *ring; >+ int i, j, r; >+ >+ for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ ring = &adev->vcn.inst[j].ring_dec; >+ >+ adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell, >+ ring->doorbell_index, j); >+ >+ r = amdgpu_ring_test_ring(ring); >+ if (r) { >+ ring->sched.ready = false; >+ goto done; >+ } >+ >+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >+ ring = &adev->vcn.inst[j].ring_enc[i]; >+ ring->sched.ready = false; >+ continue; >+ r = amdgpu_ring_test_ring(ring); >+ if (r) { >+ ring->sched.ready = false; >+ goto done; >+ } >+ } >+ >+ ring = &adev->vcn.inst[j].ring_jpeg; >+ r = amdgpu_ring_test_ring(ring); >+ if (r) { >+ ring->sched.ready = false; >+ goto done; >+ } >+ } >+done: >+ if (!r) >+ DRM_INFO("VCN decode and encode initialized successfully.\n"); >+ >+ return r; >+} >+ >+/** >+ * vcn_v2_5_hw_fini - stop the hardware block >+ * >+ * @handle: amdgpu_device pointer >+ * >+ * Stop the VCN block, mark ring as not ready any more >+ */ >+static int vcn_v2_5_hw_fini(void *handle) >+{ >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ struct amdgpu_ring *ring; >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ ring = &adev->vcn.inst[i].ring_dec; >+ >+ if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) >+ vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); >+ >+ ring->sched.ready = false; >+ >+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >+ ring = &adev->vcn.inst[i].ring_enc[i]; >+ ring->sched.ready = false; >+ } >+ >+ ring = &adev->vcn.inst[i].ring_jpeg; >+ ring->sched.ready = false; >+ } >+ >+ return 0; >+} >+ >+/** >+ * vcn_v2_5_suspend - suspend VCN block >+ * >+ * @handle: amdgpu_device pointer >+ * >+ * HW fini and suspend VCN block >+ */ >+static int vcn_v2_5_suspend(void *handle) >+{ >+ int r; >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ >+ r = vcn_v2_5_hw_fini(adev); >+ if (r) >+ return r; >+ >+ r = amdgpu_vcn_suspend(adev); >+ >+ return r; >+} >+ >+/** >+ * vcn_v2_5_resume - resume VCN block >+ * >+ * @handle: amdgpu_device pointer >+ * >+ * Resume firmware and hw init VCN block >+ */ >+static int vcn_v2_5_resume(void *handle) >+{ >+ int r; >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ >+ r = amdgpu_vcn_resume(adev); >+ if (r) >+ return r; >+ >+ r = vcn_v2_5_hw_init(adev); >+ >+ return r; >+} >+ >+/** >+ * vcn_v2_5_mc_resume - memory controller programming >+ * >+ * @adev: amdgpu_device pointer >+ * >+ * Let the VCN memory controller know it's offsets >+ */ >+static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) >+{ >+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); >+ uint32_t offset; >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ /* cache window 0: fw */ >+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { >+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, >+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); >+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, >+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); >+ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); >+ offset = 0; >+ } else { >+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, >+ lower_32_bits(adev->vcn.inst[i].gpu_addr)); >+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, >+ upper_32_bits(adev->vcn.inst[i].gpu_addr)); >+ offset = size; >+ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, >+ AMDGPU_UVD_FIRMWARE_OFFSET >> 3); >+ } >+ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); >+ >+ /* cache window 1: stack */ >+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, >+ lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); >+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, >+ upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); >+ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0); >+ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); >+ >+ /* cache window 2: context */ >+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, >+ lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); >+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, >+ upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); >+ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0); >+ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); >+ } >+} >+ >+/** >+ * vcn_v2_5_disable_clock_gating - disable VCN clock gating >+ * >+ * @adev: amdgpu_device pointer >+ * @sw: enable SW clock gating >+ * >+ * Disable clock gating for VCN block >+ */ >+static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) >+{ >+ uint32_t data; >+ int ret = 0; >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ /* UVD disable CGC */ >+ data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); >+ if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) >+ data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; >+ else >+ data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; >+ data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; >+ data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; >+ WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); >+ >+ data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); >+ data &= ~(UVD_CGC_GATE__SYS_MASK >+ | UVD_CGC_GATE__UDEC_MASK >+ | UVD_CGC_GATE__MPEG2_MASK >+ | UVD_CGC_GATE__REGS_MASK >+ | UVD_CGC_GATE__RBC_MASK >+ | UVD_CGC_GATE__LMI_MC_MASK >+ | UVD_CGC_GATE__LMI_UMC_MASK >+ | UVD_CGC_GATE__IDCT_MASK >+ | UVD_CGC_GATE__MPRD_MASK >+ | UVD_CGC_GATE__MPC_MASK >+ | UVD_CGC_GATE__LBSI_MASK >+ | UVD_CGC_GATE__LRBBM_MASK >+ | UVD_CGC_GATE__UDEC_RE_MASK >+ | UVD_CGC_GATE__UDEC_CM_MASK >+ | UVD_CGC_GATE__UDEC_IT_MASK >+ | UVD_CGC_GATE__UDEC_DB_MASK >+ | UVD_CGC_GATE__UDEC_MP_MASK >+ | UVD_CGC_GATE__WCB_MASK >+ | UVD_CGC_GATE__VCPU_MASK >+ | UVD_CGC_GATE__MMSCH_MASK); >+ >+ WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); >+ >+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret); >+ >+ data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); >+ data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_CM_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_IT_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_DB_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_MP_MODE_MASK >+ | UVD_CGC_CTRL__SYS_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_MODE_MASK >+ | UVD_CGC_CTRL__MPEG2_MODE_MASK >+ | UVD_CGC_CTRL__REGS_MODE_MASK >+ | UVD_CGC_CTRL__RBC_MODE_MASK >+ | UVD_CGC_CTRL__LMI_MC_MODE_MASK >+ | UVD_CGC_CTRL__LMI_UMC_MODE_MASK >+ | UVD_CGC_CTRL__IDCT_MODE_MASK >+ | UVD_CGC_CTRL__MPRD_MODE_MASK >+ | UVD_CGC_CTRL__MPC_MODE_MASK >+ | UVD_CGC_CTRL__LBSI_MODE_MASK >+ | UVD_CGC_CTRL__LRBBM_MODE_MASK >+ | UVD_CGC_CTRL__WCB_MODE_MASK >+ | UVD_CGC_CTRL__VCPU_MODE_MASK >+ | UVD_CGC_CTRL__MMSCH_MODE_MASK); >+ WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); >+ >+ /* turn on */ >+ data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); >+ data |= (UVD_SUVD_CGC_GATE__SRE_MASK >+ | UVD_SUVD_CGC_GATE__SIT_MASK >+ | UVD_SUVD_CGC_GATE__SMP_MASK >+ | UVD_SUVD_CGC_GATE__SCM_MASK >+ | UVD_SUVD_CGC_GATE__SDB_MASK >+ | UVD_SUVD_CGC_GATE__SRE_H264_MASK >+ | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK >+ | UVD_SUVD_CGC_GATE__SIT_H264_MASK >+ | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK >+ | UVD_SUVD_CGC_GATE__SCM_H264_MASK >+ | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK >+ | UVD_SUVD_CGC_GATE__SDB_H264_MASK >+ | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK >+ | UVD_SUVD_CGC_GATE__SCLR_MASK >+ | UVD_SUVD_CGC_GATE__UVD_SC_MASK >+ | UVD_SUVD_CGC_GATE__ENT_MASK >+ | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK >+ | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK >+ | UVD_SUVD_CGC_GATE__SITE_MASK >+ | UVD_SUVD_CGC_GATE__SRE_VP9_MASK >+ | UVD_SUVD_CGC_GATE__SCM_VP9_MASK >+ | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK >+ | UVD_SUVD_CGC_GATE__SDB_VP9_MASK >+ | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); >+ WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); >+ >+ data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); >+ data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__IME_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); >+ WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); >+ } >+} >+ >+/** >+ * vcn_v2_5_enable_clock_gating - enable VCN clock gating >+ * >+ * @adev: amdgpu_device pointer >+ * @sw: enable SW clock gating >+ * >+ * Enable clock gating for VCN block >+ */ >+static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) >+{ >+ uint32_t data = 0; >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ /* enable UVD CGC */ >+ data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); >+ if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) >+ data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; >+ else >+ data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; >+ data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; >+ data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; >+ WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); >+ >+ data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); >+ data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_CM_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_IT_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_DB_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_MP_MODE_MASK >+ | UVD_CGC_CTRL__SYS_MODE_MASK >+ | UVD_CGC_CTRL__UDEC_MODE_MASK >+ | UVD_CGC_CTRL__MPEG2_MODE_MASK >+ | UVD_CGC_CTRL__REGS_MODE_MASK >+ | UVD_CGC_CTRL__RBC_MODE_MASK >+ | UVD_CGC_CTRL__LMI_MC_MODE_MASK >+ | UVD_CGC_CTRL__LMI_UMC_MODE_MASK >+ | UVD_CGC_CTRL__IDCT_MODE_MASK >+ | UVD_CGC_CTRL__MPRD_MODE_MASK >+ | UVD_CGC_CTRL__MPC_MODE_MASK >+ | UVD_CGC_CTRL__LBSI_MODE_MASK >+ | UVD_CGC_CTRL__LRBBM_MODE_MASK >+ | UVD_CGC_CTRL__WCB_MODE_MASK >+ | UVD_CGC_CTRL__VCPU_MODE_MASK); >+ WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); >+ >+ data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); >+ data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__IME_MODE_MASK >+ | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); >+ WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); >+ } >+} >+ >+/** >+ * jpeg_v2_5_start - start JPEG block >+ * >+ * @adev: amdgpu_device pointer >+ * >+ * Setup and start the JPEG block >+ */ >+static int jpeg_v2_5_start(struct amdgpu_device *adev) >+{ >+ struct amdgpu_ring *ring; >+ uint32_t tmp; >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ ring = &adev->vcn.inst[i].ring_jpeg; >+ /* disable anti hang mechanism */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0, >+ ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); >+ >+ /* JPEG disable CGC */ >+ tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL); >+ tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; >+ tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; >+ tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; >+ WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp); >+ >+ tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE); >+ tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK >+ | JPEG_CGC_GATE__JPEG2_DEC_MASK >+ | JPEG_CGC_GATE__JMCIF_MASK >+ | JPEG_CGC_GATE__JRBBM_MASK); >+ WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp); >+ >+ tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL); >+ tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK >+ | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK >+ | JPEG_CGC_CTRL__JMCIF_MODE_MASK >+ | JPEG_CGC_CTRL__JRBBM_MODE_MASK); >+ WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp); >+ >+ /* MJPEG global tiling registers */ >+ WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, >+ adev->gfx.config.gb_addr_config); >+ WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, >+ adev->gfx.config.gb_addr_config); >+ >+ /* enable JMI channel */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0, >+ ~UVD_JMI_CNTL__SOFT_RESET_MASK); >+ >+ /* enable System Interrupt for JRBC */ >+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN), >+ JPEG_SYS_INT_EN__DJRBC_MASK, >+ ~JPEG_SYS_INT_EN__DJRBC_MASK); >+ >+ WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_VMID, 0); >+ WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); >+ WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, >+ lower_32_bits(ring->gpu_addr)); >+ WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, >+ upper_32_bits(ring->gpu_addr)); >+ WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_RPTR, 0); >+ WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR, 0); >+ WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); >+ WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); >+ ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR); >+ } >+ >+ return 0; >+} >+ >+/** >+ * jpeg_v2_5_stop - stop JPEG block >+ * >+ * @adev: amdgpu_device pointer >+ * >+ * stop the JPEG block >+ */ >+static int jpeg_v2_5_stop(struct amdgpu_device *adev) >+{ >+ uint32_t tmp; >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ /* reset JMI */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), >+ UVD_JMI_CNTL__SOFT_RESET_MASK, >+ ~UVD_JMI_CNTL__SOFT_RESET_MASK); >+ >+ tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE); >+ tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK >+ |JPEG_CGC_GATE__JPEG2_DEC_MASK >+ |JPEG_CGC_GATE__JMCIF_MASK >+ |JPEG_CGC_GATE__JRBBM_MASK); >+ WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp); >+ >+ /* enable anti hang mechanism */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), >+ UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, >+ ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); >+ } >+ >+ return 0; >+} >+ >+static int vcn_v2_5_start(struct amdgpu_device *adev) >+{ >+ struct amdgpu_ring *ring; >+ uint32_t rb_bufsz, tmp; >+ int i, j, k, r; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ /* disable register anti-hang mechanism */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0, >+ ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); >+ >+ /* set uvd status busy */ >+ tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; >+ WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp); >+ } >+ >+ /*SW clock gating */ >+ vcn_v2_5_disable_clock_gating(adev); >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ /* enable VCPU clock */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), >+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); >+ >+ /* disable master interrupt */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0, >+ ~UVD_MASTINT_EN__VCPU_EN_MASK); >+ >+ /* setup mmUVD_LMI_CTRL */ >+ tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL); >+ tmp &= ~0xff; >+ WREG32_SOC15(UVD, i, mmUVD_LMI_CTRL, tmp | 0x8| >+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | >+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK | >+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | >+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); >+ >+ /* setup mmUVD_MPC_CNTL */ >+ tmp = RREG32_SOC15(UVD, i, mmUVD_MPC_CNTL); >+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; >+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; >+ WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); >+ >+ /* setup UVD_MPC_SET_MUXA0 */ >+ WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXA0, >+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | >+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | >+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | >+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); >+ >+ /* setup UVD_MPC_SET_MUXB0 */ >+ WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXB0, >+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | >+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | >+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | >+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); >+ >+ /* setup mmUVD_MPC_SET_MUX */ >+ WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUX, >+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | >+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | >+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); >+ } >+ >+ vcn_v2_5_mc_resume(adev); >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ /* VCN global tiling registers */ >+ WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG, >+ adev->gfx.config.gb_addr_config); >+ WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG, >+ adev->gfx.config.gb_addr_config); >+ >+ /* enable LMI MC and UMC channels */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, >+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); >+ >+ /* unblock VCPU register access */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0, >+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); >+ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, >+ ~UVD_VCPU_CNTL__BLK_RST_MASK); >+ >+ for (k = 0; k < 10; ++k) { >+ uint32_t status; >+ >+ for (j = 0; j < 100; ++j) { >+ status = RREG32_SOC15(UVD, i, mmUVD_STATUS); >+ if (status & 2) >+ break; >+ if (amdgpu_emu_mode == 1) >+ msleep(500); >+ else >+ mdelay(10); >+ } >+ r = 0; >+ if (status & 2) >+ break; >+ >+ DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), >+ UVD_VCPU_CNTL__BLK_RST_MASK, >+ ~UVD_VCPU_CNTL__BLK_RST_MASK); >+ mdelay(10); >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, >+ ~UVD_VCPU_CNTL__BLK_RST_MASK); >+ >+ mdelay(10); >+ r = -1; >+ } >+ >+ if (r) { >+ DRM_ERROR("VCN decode not responding, giving up!!!\n"); >+ return r; >+ } >+ >+ /* enable master interrupt */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), >+ UVD_MASTINT_EN__VCPU_EN_MASK, >+ ~UVD_MASTINT_EN__VCPU_EN_MASK); >+ >+ /* clear the busy bit of VCN_STATUS */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0, >+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); >+ >+ WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_VMID, 0); >+ >+ ring = &adev->vcn.inst[i].ring_dec; >+ /* force RBC into idle state */ >+ rb_bufsz = order_base_2(ring->ring_size); >+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); >+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); >+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); >+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); >+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); >+ WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp); >+ >+ /* programm the RB_BASE for ring buffer */ >+ WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, >+ lower_32_bits(ring->gpu_addr)); >+ WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, >+ upper_32_bits(ring->gpu_addr)); >+ >+ /* Initialize the ring buffer's read and write pointers */ >+ WREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR, 0); >+ >+ ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR); >+ WREG32_SOC15(UVD, i, mmUVD_RBC_RB_WPTR, >+ lower_32_bits(ring->wptr)); >+ ring = &adev->vcn.inst[i].ring_enc[0]; >+ WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); >+ WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); >+ WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO, ring->gpu_addr); >+ WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); >+ WREG32_SOC15(UVD, i, mmUVD_RB_SIZE, ring->ring_size / 4); >+ >+ ring = &adev->vcn.inst[i].ring_enc[1]; >+ WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); >+ WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); >+ WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); >+ WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); >+ WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4); >+ } >+ r = jpeg_v2_5_start(adev); >+ >+ return r; >+} >+ >+static int vcn_v2_5_stop(struct amdgpu_device *adev) >+{ >+ uint32_t tmp; >+ int i, r; >+ >+ r = jpeg_v2_5_stop(adev); >+ if (r) >+ return r; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ /* wait for vcn idle */ >+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); >+ if (r) >+ return r; >+ >+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | >+ UVD_LMI_STATUS__READ_CLEAN_MASK | >+ UVD_LMI_STATUS__WRITE_CLEAN_MASK | >+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; >+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r); >+ if (r) >+ return r; >+ >+ /* block LMI UMC channel */ >+ tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); >+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; >+ WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); >+ >+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| >+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; >+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r); >+ if (r) >+ return r; >+ >+ /* block VCPU register access */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), >+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK, >+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); >+ >+ /* reset VCPU */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), >+ UVD_VCPU_CNTL__BLK_RST_MASK, >+ ~UVD_VCPU_CNTL__BLK_RST_MASK); >+ >+ /* disable VCPU clock */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, >+ ~(UVD_VCPU_CNTL__CLK_EN_MASK)); >+ >+ /* clear status */ >+ WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); >+ >+ vcn_v2_5_enable_clock_gating(adev); >+ >+ /* enable register anti-hang mechanism */ >+ WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), >+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, >+ ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); >+ } >+ >+ return 0; >+} >+ >+/** >+ * vcn_v2_5_dec_ring_get_rptr - get read pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Returns the current hardware read pointer >+ */ >+static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); >+} >+ >+/** >+ * vcn_v2_5_dec_ring_get_wptr - get write pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Returns the current hardware write pointer >+ */ >+static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ if (ring->use_doorbell) >+ return adev->wb.wb[ring->wptr_offs]; >+ else >+ return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); >+} >+ >+/** >+ * vcn_v2_5_dec_ring_set_wptr - set write pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Commits the write pointer to the hardware >+ */ >+static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ if (ring->use_doorbell) { >+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); >+ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); >+ } else { >+ WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); >+ } >+} >+ >+static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { >+ .type = AMDGPU_RING_TYPE_VCN_DEC, >+ .align_mask = 0xf, >+ .vmhub = AMDGPU_MMHUB_1, >+ .get_rptr = vcn_v2_5_dec_ring_get_rptr, >+ .get_wptr = vcn_v2_5_dec_ring_get_wptr, >+ .set_wptr = vcn_v2_5_dec_ring_set_wptr, >+ .emit_frame_size = >+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + >+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + >+ 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ >+ 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ >+ 6, >+ .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ >+ .emit_ib = vcn_v2_0_dec_ring_emit_ib, >+ .emit_fence = vcn_v2_0_dec_ring_emit_fence, >+ .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, >+ .test_ring = amdgpu_vcn_dec_ring_test_ring, >+ .test_ib = amdgpu_vcn_dec_ring_test_ib, >+ .insert_nop = vcn_v2_0_dec_ring_insert_nop, >+ .insert_start = vcn_v2_0_dec_ring_insert_start, >+ .insert_end = vcn_v2_0_dec_ring_insert_end, >+ .pad_ib = amdgpu_ring_generic_pad_ib, >+ .begin_use = amdgpu_vcn_ring_begin_use, >+ .end_use = amdgpu_vcn_ring_end_use, >+ .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, >+ .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, >+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, >+}; >+ >+/** >+ * vcn_v2_5_enc_ring_get_rptr - get enc read pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Returns the current hardware enc read pointer >+ */ >+static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) >+ return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); >+ else >+ return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); >+} >+ >+/** >+ * vcn_v2_5_enc_ring_get_wptr - get enc write pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Returns the current hardware enc write pointer >+ */ >+static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { >+ if (ring->use_doorbell) >+ return adev->wb.wb[ring->wptr_offs]; >+ else >+ return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); >+ } else { >+ if (ring->use_doorbell) >+ return adev->wb.wb[ring->wptr_offs]; >+ else >+ return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); >+ } >+} >+ >+/** >+ * vcn_v2_5_enc_ring_set_wptr - set enc write pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Commits the enc write pointer to the hardware >+ */ >+static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { >+ if (ring->use_doorbell) { >+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); >+ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); >+ } else { >+ WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); >+ } >+ } else { >+ if (ring->use_doorbell) { >+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); >+ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); >+ } else { >+ WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); >+ } >+ } >+} >+ >+static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { >+ .type = AMDGPU_RING_TYPE_VCN_ENC, >+ .align_mask = 0x3f, >+ .nop = VCN_ENC_CMD_NO_OP, >+ .vmhub = AMDGPU_MMHUB_1, >+ .get_rptr = vcn_v2_5_enc_ring_get_rptr, >+ .get_wptr = vcn_v2_5_enc_ring_get_wptr, >+ .set_wptr = vcn_v2_5_enc_ring_set_wptr, >+ .emit_frame_size = >+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + >+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + >+ 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ >+ 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ >+ 1, /* vcn_v2_0_enc_ring_insert_end */ >+ .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ >+ .emit_ib = vcn_v2_0_enc_ring_emit_ib, >+ .emit_fence = vcn_v2_0_enc_ring_emit_fence, >+ .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, >+ .test_ring = amdgpu_vcn_enc_ring_test_ring, >+ .test_ib = amdgpu_vcn_enc_ring_test_ib, >+ .insert_nop = amdgpu_ring_insert_nop, >+ .insert_end = vcn_v2_0_enc_ring_insert_end, >+ .pad_ib = amdgpu_ring_generic_pad_ib, >+ .begin_use = amdgpu_vcn_ring_begin_use, >+ .end_use = amdgpu_vcn_ring_end_use, >+ .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, >+ .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, >+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, >+}; >+ >+/** >+ * vcn_v2_5_jpeg_ring_get_rptr - get read pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Returns the current hardware read pointer >+ */ >+static uint64_t vcn_v2_5_jpeg_ring_get_rptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR); >+} >+ >+/** >+ * vcn_v2_5_jpeg_ring_get_wptr - get write pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Returns the current hardware write pointer >+ */ >+static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ if (ring->use_doorbell) >+ return adev->wb.wb[ring->wptr_offs]; >+ else >+ return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR); >+} >+ >+/** >+ * vcn_v2_5_jpeg_ring_set_wptr - set write pointer >+ * >+ * @ring: amdgpu_ring pointer >+ * >+ * Commits the write pointer to the hardware >+ */ >+static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring) >+{ >+ struct amdgpu_device *adev = ring->adev; >+ >+ if (ring->use_doorbell) { >+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); >+ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); >+ } else { >+ WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); >+ } >+} >+ >+static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = { >+ .type = AMDGPU_RING_TYPE_VCN_JPEG, >+ .align_mask = 0xf, >+ .vmhub = AMDGPU_MMHUB_1, >+ .get_rptr = vcn_v2_5_jpeg_ring_get_rptr, >+ .get_wptr = vcn_v2_5_jpeg_ring_get_wptr, >+ .set_wptr = vcn_v2_5_jpeg_ring_set_wptr, >+ .emit_frame_size = >+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + >+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + >+ 8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */ >+ 18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */ >+ 8 + 16, >+ .emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */ >+ .emit_ib = vcn_v2_0_jpeg_ring_emit_ib, >+ .emit_fence = vcn_v2_0_jpeg_ring_emit_fence, >+ .emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush, >+ .test_ring = amdgpu_vcn_jpeg_ring_test_ring, >+ .test_ib = amdgpu_vcn_jpeg_ring_test_ib, >+ .insert_nop = vcn_v2_0_jpeg_ring_nop, >+ .insert_start = vcn_v2_0_jpeg_ring_insert_start, >+ .insert_end = vcn_v2_0_jpeg_ring_insert_end, >+ .pad_ib = amdgpu_ring_generic_pad_ib, >+ .begin_use = amdgpu_vcn_ring_begin_use, >+ .end_use = amdgpu_vcn_ring_end_use, >+ .emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg, >+ .emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait, >+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, >+}; >+ >+static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) >+{ >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; >+ adev->vcn.inst[i].ring_dec.me = i; >+ DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i); >+ } >+} >+ >+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) >+{ >+ int i, j; >+ >+ for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { >+ if (adev->vcn.harvest_config & (1 << j)) >+ continue; >+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) { >+ adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; >+ adev->vcn.inst[j].ring_enc[i].me = j; >+ } >+ DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j); >+ } >+} >+ >+static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev) >+{ >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ adev->vcn.inst[i].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs; >+ adev->vcn.inst[i].ring_jpeg.me = i; >+ DRM_INFO("VCN(%d) jpeg decode is enabled in VM mode\n", i); >+ } >+} >+ >+static bool vcn_v2_5_is_idle(void *handle) >+{ >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ int i, ret = 1; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); >+ } >+ >+ return ret; >+} >+ >+static int vcn_v2_5_wait_for_idle(void *handle) >+{ >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ int i, ret = 0; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, >+ UVD_STATUS__IDLE, ret); >+ if (ret) >+ return ret; >+ } >+ >+ return ret; >+} >+ >+static int vcn_v2_5_set_clockgating_state(void *handle, >+ enum amd_clockgating_state state) >+{ >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ bool enable = (state == AMD_CG_STATE_GATE) ? true : false; >+ >+ if (enable) { >+ if (vcn_v2_5_is_idle(handle)) >+ return -EBUSY; >+ vcn_v2_5_enable_clock_gating(adev); >+ } else { >+ vcn_v2_5_disable_clock_gating(adev); >+ } >+ >+ return 0; >+} >+ >+static int vcn_v2_5_set_powergating_state(void *handle, >+ enum amd_powergating_state state) >+{ >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; >+ int ret; >+ >+ if(state == adev->vcn.cur_state) >+ return 0; >+ >+ if (state == AMD_PG_STATE_GATE) >+ ret = vcn_v2_5_stop(adev); >+ else >+ ret = vcn_v2_5_start(adev); >+ >+ if(!ret) >+ adev->vcn.cur_state = state; >+ >+ return ret; >+} >+ >+static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev, >+ struct amdgpu_irq_src *source, >+ unsigned type, >+ enum amdgpu_interrupt_state state) >+{ >+ return 0; >+} >+ >+static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, >+ struct amdgpu_irq_src *source, >+ struct amdgpu_iv_entry *entry) >+{ >+ uint32_t ip_instance; >+ >+ switch (entry->client_id) { >+ case SOC15_IH_CLIENTID_VCN: >+ ip_instance = 0; >+ break; >+ case SOC15_IH_CLIENTID_VCN1: >+ ip_instance = 1; >+ break; >+ default: >+ DRM_ERROR("Unhandled client id: %d\n", entry->client_id); >+ return 0; >+ } >+ >+ DRM_DEBUG("IH: VCN TRAP\n"); >+ >+ switch (entry->src_id) { >+ case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: >+ amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); >+ break; >+ case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: >+ amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); >+ break; >+ case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: >+ amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); >+ break; >+ case VCN_2_0__SRCID__JPEG_DECODE: >+ amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_jpeg); >+ break; >+ default: >+ DRM_ERROR("Unhandled interrupt: %d %d\n", >+ entry->src_id, entry->src_data[0]); >+ break; >+ } >+ >+ return 0; >+} >+ >+static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = { >+ .set = vcn_v2_5_set_interrupt_state, >+ .process = vcn_v2_5_process_interrupt, >+}; >+ >+static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) >+{ >+ int i; >+ >+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { >+ if (adev->vcn.harvest_config & (1 << i)) >+ continue; >+ adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 2; >+ adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; >+ } >+} >+ >+static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { >+ .name = "vcn_v2_5", >+ .early_init = vcn_v2_5_early_init, >+ .late_init = NULL, >+ .sw_init = vcn_v2_5_sw_init, >+ .sw_fini = vcn_v2_5_sw_fini, >+ .hw_init = vcn_v2_5_hw_init, >+ .hw_fini = vcn_v2_5_hw_fini, >+ .suspend = vcn_v2_5_suspend, >+ .resume = vcn_v2_5_resume, >+ .is_idle = vcn_v2_5_is_idle, >+ .wait_for_idle = vcn_v2_5_wait_for_idle, >+ .check_soft_reset = NULL, >+ .pre_soft_reset = NULL, >+ .soft_reset = NULL, >+ .post_soft_reset = NULL, >+ .set_clockgating_state = vcn_v2_5_set_clockgating_state, >+ .set_powergating_state = vcn_v2_5_set_powergating_state, >+}; >+ >+const struct amdgpu_ip_block_version vcn_v2_5_ip_block = >+{ >+ .type = AMD_IP_BLOCK_TYPE_VCN, >+ .major = 2, >+ .minor = 5, >+ .rev = 0, >+ .funcs = &vcn_v2_5_ip_funcs, >+}; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h 2019-08-31 15:01:11.852736168 -0500 >@@ -0,0 +1,29 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ */ >+ >+#ifndef __VCN_V2_5_H__ >+#define __VCN_V2_5_H__ >+ >+extern const struct amdgpu_ip_block_version vcn_v2_5_ip_block; >+ >+#endif /* __VCN_V2_5_H__ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega10_ih.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega10_ih.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 2019-08-31 15:01:11.852736168 -0500 >@@ -50,7 +50,7 @@ > > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { > DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); > return; >@@ -64,7 +64,7 @@ > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, > RB_ENABLE, 1); >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, > ih_rb_cntl)) { > DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); >@@ -80,7 +80,7 @@ > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, > RB_ENABLE, 1); >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, > ih_rb_cntl)) { > DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); >@@ -106,7 +106,7 @@ > > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { > DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); > return; >@@ -125,7 +125,7 @@ > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, > RB_ENABLE, 0); >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, > ih_rb_cntl)) { > DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); >@@ -145,7 +145,7 @@ > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, > RB_ENABLE, 0); >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, > ih_rb_cntl)) { > DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); >@@ -219,7 +219,7 @@ > static int vega10_ih_irq_init(struct amdgpu_device *adev) > { > struct amdgpu_ih_ring *ih; >- u32 ih_rb_cntl; >+ u32 ih_rb_cntl, ih_chicken; > int ret = 0; > u32 tmp; > >@@ -234,11 +234,17 @@ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); > > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); >+ ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); > ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); >+ if (adev->irq.ih.use_bus_addr) { >+ ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); >+ } else { >+ ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_FBPA_ENABLE, 1); >+ } > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, > !!adev->irq.msi_enabled); > >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { > DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); > return -ETIMEDOUT; >@@ -247,6 +253,11 @@ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); > } > >+ if ((adev->asic_type == CHIP_ARCTURUS >+ && adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) >+ || adev->asic_type == CHIP_RENOIR) >+ WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); >+ > /* set the writeback address whether it's enabled or not */ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, > lower_32_bits(ih->wptr_addr)); >@@ -272,7 +283,7 @@ > WPTR_OVERFLOW_ENABLE, 0); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, > RB_FULL_DRAIN_ENABLE, 1); >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, > ih_rb_cntl)) { > DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); >@@ -299,7 +310,7 @@ > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); > ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); > >- if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { >+ if (amdgpu_sriov_vf(adev)) { > if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, > ih_rb_cntl)) { > DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 2019-08-31 15:01:11.852736168 -0500 >@@ -81,6 +81,10 @@ > adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3; > adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5; > adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7; >+ adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL64_VCN0_1; >+ adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_DOORBELL64_VCN2_3; >+ adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_DOORBELL64_VCN4_5; >+ adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_DOORBELL64_VCN6_7; > > adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL64_FIRST_NON_CP; > adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 2019-08-31 15:01:11.852736168 -0500 >@@ -50,6 +50,8 @@ > adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); > adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); > adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); >+ adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); >+ adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i])); > } > return 0; > } >@@ -85,6 +87,10 @@ > adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3; > adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5; > adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7; >+ adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_VEGA20_DOORBELL64_VCN0_1; >+ adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCN2_3; >+ adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCN4_5; >+ adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCN6_7; > > adev->doorbell_index.first_non_cp = AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP; > adev->doorbell_index.last_non_cp = AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vi.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vi.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vi.c 2019-08-31 15:01:11.852736168 -0500 >@@ -711,6 +711,12 @@ > return r; > } > >+static enum amd_reset_method >+vi_asic_reset_method(struct amdgpu_device *adev) >+{ >+ return AMD_RESET_METHOD_LEGACY; >+} >+ > static u32 vi_get_config_memsize(struct amdgpu_device *adev) > { > return RREG32(mmCONFIG_MEMSIZE); >@@ -1023,6 +1029,7 @@ > .read_bios_from_rom = &vi_read_bios_from_rom, > .read_register = &vi_read_register, > .reset = &vi_asic_reset, >+ .reset_method = &vi_asic_reset_method, > .set_vga_state = &vi_vga_set_state, > .get_xclk = &vi_get_xclk, > .set_uvd_clocks = &vi_set_uvd_clocks, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm 2019-08-31 15:01:11.853736168 -0500 >@@ -20,1105 +20,947 @@ > * OTHER DEALINGS IN THE SOFTWARE. > */ > >+var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 >+var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 >+var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 >+var SQ_WAVE_STATUS_HALT_MASK = 0x2000 > >-shader main >- >-asic(DEFAULT) >- >-type(CS) >+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 >+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 >+var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 >+var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 >+var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 >+var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 4 >+var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24 >+var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4 >+var SQ_WAVE_IB_STS2_WAVE64_SHIFT = 11 >+var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1 >+ >+var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 >+var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF >+var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 >+var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 >+var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 >+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF >+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 >+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 >+var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 >+var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 >+var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 >+var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 >+ >+var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 >+var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 >+var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT = 25 >+var SQ_WAVE_IB_STS_REPLAY_W64H_SIZE = 1 >+var SQ_WAVE_IB_STS_REPLAY_W64H_MASK = 0x02000000 >+var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 >+var SQ_WAVE_IB_STS_RCNT_SIZE = 6 >+var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x003F8000 >+var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF >+ >+var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 >+var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 >+ >+// bits [31:24] unused by SPI debug data >+var TTMP11_SAVE_REPLAY_W64H_SHIFT = 31 >+var TTMP11_SAVE_REPLAY_W64H_MASK = 0x80000000 >+var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 24 >+var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0x7F000000 >+ >+// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] >+// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE >+var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 >+var S_SAVE_BUF_RSRC_WORD3_MISC = 0x10807FAC >+ >+var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 >+var S_SAVE_SPI_INIT_ATC_SHIFT = 27 >+var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 >+var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 >+var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 >+var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 >+ >+var S_SAVE_PC_HI_RCNT_SHIFT = 26 >+var S_SAVE_PC_HI_RCNT_MASK = 0xFC000000 >+var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 25 >+var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x02000000 >+var S_SAVE_PC_HI_REPLAY_W64H_SHIFT = 24 >+var S_SAVE_PC_HI_REPLAY_W64H_MASK = 0x01000000 >+ >+var s_sgpr_save_num = 108 >+ >+var s_save_spi_init_lo = exec_lo >+var s_save_spi_init_hi = exec_hi >+var s_save_pc_lo = ttmp0 >+var s_save_pc_hi = ttmp1 >+var s_save_exec_lo = ttmp2 >+var s_save_exec_hi = ttmp3 >+var s_save_status = ttmp12 >+var s_save_trapsts = ttmp5 >+var s_save_xnack_mask = ttmp6 >+var s_wave_size = ttmp7 >+var s_save_buf_rsrc0 = ttmp8 >+var s_save_buf_rsrc1 = ttmp9 >+var s_save_buf_rsrc2 = ttmp10 >+var s_save_buf_rsrc3 = ttmp11 >+var s_save_mem_offset = ttmp14 >+var s_save_alloc_size = s_save_trapsts >+var s_save_tmp = s_save_buf_rsrc2 >+var s_save_m0 = ttmp15 >+ >+var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE >+var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC >+ >+var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 >+var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 >+var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 >+var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 >+var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 >+var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 >+var S_WAVE_SIZE = 25 >+ >+var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT >+var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK >+var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT >+var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK >+ >+var s_restore_spi_init_lo = exec_lo >+var s_restore_spi_init_hi = exec_hi >+var s_restore_mem_offset = ttmp12 >+var s_restore_alloc_size = ttmp3 >+var s_restore_tmp = ttmp6 >+var s_restore_mem_offset_save = s_restore_tmp >+var s_restore_m0 = s_restore_alloc_size >+var s_restore_mode = ttmp7 >+var s_restore_flat_scratch = ttmp2 >+var s_restore_pc_lo = ttmp0 >+var s_restore_pc_hi = ttmp1 >+var s_restore_exec_lo = ttmp14 >+var s_restore_exec_hi = ttmp15 >+var s_restore_status = ttmp4 >+var s_restore_trapsts = ttmp5 >+var s_restore_xnack_mask = ttmp13 >+var s_restore_buf_rsrc0 = ttmp8 >+var s_restore_buf_rsrc1 = ttmp9 >+var s_restore_buf_rsrc2 = ttmp10 >+var s_restore_buf_rsrc3 = ttmp11 >+var s_restore_size = ttmp7 > >-wave_size(32) >-/*************************************************************************/ >-/* control on how to run the shader */ >-/*************************************************************************/ >-//any hack that needs to be made to run this code in EMU (either becasue various EMU code are not ready or no compute save & restore in EMU run) >-var EMU_RUN_HACK = 0 >-var EMU_RUN_HACK_RESTORE_NORMAL = 0 >-var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 >-var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 >-var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK >-var SAVE_LDS = 0 >-var WG_BASE_ADDR_LO = 0x9000a000 >-var WG_BASE_ADDR_HI = 0x0 >-var WAVE_SPACE = 0x9000 //memory size that each wave occupies in workgroup state mem, increase from 5000 to 9000 for more SGPR need to be saved >-var CTX_SAVE_CONTROL = 0x0 >-var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL >-var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either becasue various RTL code are not ready or no compute save & restore in RTL run) >-var SGPR_SAVE_USE_SQC = 0 //use SQC D$ to do the write >-var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //need to change BUF_DATA_FORMAT in S_SAVE_BUF_RSRC_WORD3_MISC from 0 to BUF_DATA_FORMAT_32 if set to 1 (i.e. 0x00827FAC) >-var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing >-var SAVE_RESTORE_HWID_DDID = 0 >-var RESTORE_DDID_IN_SGPR18 = 0 >-/**************************************************************************/ >-/* variables */ >-/**************************************************************************/ >-var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 >-var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 >-var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 >+shader main >+ asic(DEFAULT) >+ type(CS) >+ wave_size(32) > >-var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 >-var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 >-var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 >-var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 >-var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 >-var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 4 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits >-var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24 >-var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4 >-var SQ_WAVE_IB_STS2_WAVE64_SHIFT = 11 >-var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1 >- >-var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 >-var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask >-var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 >-var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 >-var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 >-var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF >-var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 >-var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 >-var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 >-var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 >-var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 >- >-var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME >-var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME >-var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 //FIXME >-var SQ_WAVE_IB_STS_RCNT_SIZE = 6 //FIXME >-var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME >- >-var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 >-var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 >- >- >-/* Save */ >-var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes >-var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE >- >-var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit >-var S_SAVE_SPI_INIT_ATC_SHIFT = 27 >-var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype >-var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 >-var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG >-var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 >- >-var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used >-var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME >-var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME >-var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME >- >-var s_save_spi_init_lo = exec_lo >-var s_save_spi_init_hi = exec_hi >- >-var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3¡¯h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} >-var s_save_pc_hi = ttmp1 >-var s_save_exec_lo = ttmp2 >-var s_save_exec_hi = ttmp3 >-var s_save_status = ttmp4 >-var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine >-var s_wave_size = ttmp6 //ttmp6 is not needed now, since it's only 32bit xnack mask, now use it to determine wave32 or wave64 in EMU_HACK >-var s_save_xnack_mask = ttmp7 >-var s_save_buf_rsrc0 = ttmp8 >-var s_save_buf_rsrc1 = ttmp9 >-var s_save_buf_rsrc2 = ttmp10 >-var s_save_buf_rsrc3 = ttmp11 >- >-var s_save_mem_offset = ttmp14 >-var s_sgpr_save_num = 106 //in gfx10, all sgpr must be saved >-var s_save_alloc_size = s_save_trapsts //conflict >-var s_save_tmp = s_save_buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_tmp at the same time) >-var s_save_m0 = ttmp15 >- >-/* Restore */ >-var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE >-var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC >- >-var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit >-var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 >-var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype >-var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 >-var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG >-var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 >- >-var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT >-var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK >-var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT >-var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK >- >-var s_restore_spi_init_lo = exec_lo >-var s_restore_spi_init_hi = exec_hi >- >-var s_restore_mem_offset = ttmp12 >-var s_restore_alloc_size = ttmp3 >-var s_restore_tmp = ttmp6 >-var s_restore_mem_offset_save = s_restore_tmp //no conflict >- >-var s_restore_m0 = s_restore_alloc_size //no conflict >- >-var s_restore_mode = ttmp13 >-var s_restore_hwid1 = ttmp2 >-var s_restore_ddid = s_restore_hwid1 >-var s_restore_pc_lo = ttmp0 >-var s_restore_pc_hi = ttmp1 >-var s_restore_exec_lo = ttmp14 >-var s_restore_exec_hi = ttmp15 >-var s_restore_status = ttmp4 >-var s_restore_trapsts = ttmp5 >-//var s_restore_xnack_mask_lo = xnack_mask_lo >-//var s_restore_xnack_mask_hi = xnack_mask_hi >-var s_restore_xnack_mask = ttmp7 >-var s_restore_buf_rsrc0 = ttmp8 >-var s_restore_buf_rsrc1 = ttmp9 >-var s_restore_buf_rsrc2 = ttmp10 >-var s_restore_buf_rsrc3 = ttmp11 >-var s_restore_size = ttmp13 //ttmp13 has no conflict >- >-/**************************************************************************/ >-/* trap handler entry points */ >-/**************************************************************************/ >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore >- //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC >- s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC >- s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. >- s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE >- //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE >- s_branch L_SKIP_RESTORE //NOT restore, SAVE actually >- else >- s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save >- end >+ s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save > > L_JUMP_TO_RESTORE: >- s_branch L_RESTORE //restore >+ s_branch L_RESTORE > > L_SKIP_RESTORE: >- >- s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC >- s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save >- s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >- s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save >- s_cbranch_scc1 L_SAVE //this is the operation for save >- >- // ********* Handle non-CWSR traps ******************* >- if (!EMU_RUN_HACK) >- s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >- s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception >- s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. >- s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 >- >- L_EXCP_CASE: >- s_and_b32 ttmp1, ttmp1, 0xFFFF >- s_rfe_b64 [ttmp0, ttmp1] >- end >- // ********* End handling of non-CWSR traps ******************* >- >-/**************************************************************************/ >-/* save routine */ >-/**************************************************************************/ >+ s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC >+ s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK >+ s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >+ s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save >+ s_cbranch_scc1 L_SAVE >+ >+ // If STATUS.MEM_VIOL is asserted then halt the wave to prevent >+ // the exception raising again and blocking context save. >+ s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK >+ s_cbranch_scc0 L_FETCH_2ND_TRAP >+ s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK >+ >+L_FETCH_2ND_TRAP: >+ // Preserve and clear scalar XNACK state before issuing scalar loads. >+ // Save IB_STS.REPLAY_W64H[25], RCNT[21:16], FIRST_REPLAY[15] into >+ // unused space ttmp11[31:24]. >+ s_andn2_b32 ttmp11, ttmp11, (TTMP11_SAVE_REPLAY_W64H_MASK | TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK) >+ s_getreg_b32 ttmp2, hwreg(HW_REG_IB_STS) >+ s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_REPLAY_W64H_MASK >+ s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) >+ s_or_b32 ttmp11, ttmp11, ttmp3 >+ s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK >+ s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) >+ s_or_b32 ttmp11, ttmp11, ttmp3 >+ s_andn2_b32 ttmp2, ttmp2, (SQ_WAVE_IB_STS_REPLAY_W64H_MASK | SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK) >+ s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 >+ >+ // Read second-level TBA/TMA from first-level TMA and jump if available. >+ // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) >+ // ttmp12 holds SQ_WAVE_STATUS >+ s_getreg_b32 ttmp4, hwreg(HW_REG_SHADER_TMA_LO) >+ s_getreg_b32 ttmp5, hwreg(HW_REG_SHADER_TMA_HI) >+ s_lshl_b64 [ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 >+ s_load_dwordx2 [ttmp2, ttmp3], [ttmp4, ttmp5], 0x0 glc:1 // second-level TBA >+ s_waitcnt lgkmcnt(0) >+ s_load_dwordx2 [ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 glc:1 // second-level TMA >+ s_waitcnt lgkmcnt(0) >+ s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] >+ s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set >+ s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler >+ >+L_NO_NEXT_TRAP: >+ s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >+ s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK >+ s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. >+ s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 >+ s_addc_u32 ttmp1, ttmp1, 0 >+L_EXCP_CASE: >+ s_and_b32 ttmp1, ttmp1, 0xFFFF >+ >+ // Restore SQ_WAVE_IB_STS. >+ s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) >+ s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK >+ s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) >+ s_and_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_REPLAY_W64H_MASK >+ s_or_b32 ttmp2, ttmp2, ttmp3 >+ s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 >+ >+ // Restore SQ_WAVE_STATUS. >+ s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 >+ s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 >+ s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status > >-L_SAVE: >- >+ s_rfe_b64 [ttmp0, ttmp1] >+ >+L_SAVE: > //check whether there is mem_viol >- s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >- s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK >+ s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >+ s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK > s_cbranch_scc0 L_NO_PC_REWIND >- >+ > //if so, need rewind PC assuming GDS operation gets NACKed >- s_mov_b32 s_save_tmp, 0 //clear mem_viol bit >- s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp //clear mem_viol bit >- s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] >- s_sub_u32 s_save_pc_lo, s_save_pc_lo, 8 //pc[31:0]-8 >- s_subb_u32 s_save_pc_hi, s_save_pc_hi, 0x0 // -scc >+ s_mov_b32 s_save_tmp, 0 >+ s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp //clear mem_viol bit >+ s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] >+ s_sub_u32 s_save_pc_lo, s_save_pc_lo, 8 //pc[31:0]-8 >+ s_subb_u32 s_save_pc_hi, s_save_pc_hi, 0x0 > > L_NO_PC_REWIND: >- s_mov_b32 s_save_tmp, 0 //clear saveCtx bit >- s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit >+ s_mov_b32 s_save_tmp, 0 >+ s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit > >- //s_mov_b32 s_save_xnack_mask_lo, xnack_mask_lo //save XNACK_MASK >- //s_mov_b32 s_save_xnack_mask_hi, xnack_mask_hi >- s_getreg_b32 s_save_xnack_mask, hwreg(HW_REG_SHADER_XNACK_MASK) >- s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT >- s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT >- s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp >- s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY >- s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT >- s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp >- s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS >- s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG >+ s_getreg_b32 s_save_xnack_mask, hwreg(HW_REG_SHADER_XNACK_MASK) >+ s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) >+ s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT >+ s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp >+ s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) >+ s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT >+ s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp >+ s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT, SQ_WAVE_IB_STS_REPLAY_W64H_SIZE) >+ s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_REPLAY_W64H_SHIFT >+ s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp >+ s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY and REPLAY_W64H in IB_STS >+ s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG > > s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp >- >- /* inform SPI the readiness and wait for SPI's go signal */ >- s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI >- s_mov_b32 s_save_exec_hi, exec_hi >- s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive >- if (EMU_RUN_HACK) >- >- else >- s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC >- end >- >- L_SLEEP: >- s_sleep 0x2 >- >- if (EMU_RUN_HACK) >- >- else >- s_cbranch_execz L_SLEEP >- end >- >- >- /* setup Resource Contants */ >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) >- //calculate wd_addr using absolute thread id >- v_readlane_b32 s_save_tmp, v9, 0 >- //determine it is wave32 or wave64 >- s_getreg_b32 s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) >- s_cmp_eq_u32 s_wave_size, 0 >- s_cbranch_scc1 L_SAVE_WAVE32 >- s_lshr_b32 s_save_tmp, s_save_tmp, 6 //SAVE WAVE64 >- s_branch L_SAVE_CON >- L_SAVE_WAVE32: >- s_lshr_b32 s_save_tmp, s_save_tmp, 5 //SAVE WAVE32 >- L_SAVE_CON: >- s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE >- s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL >- else >- end >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) >- s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL >- else >- end >- >- >- s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo >- s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE >- s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited >- s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC >- s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK >- s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position >- s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC >- s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK >- s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position >- s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE >- >- s_mov_b32 s_save_m0, m0 //save M0 >- >- /* global mem offset */ >- s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 >- s_getreg_b32 s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) //get wave_save_size >- s_or_b32 s_wave_size, s_save_spi_init_hi, s_wave_size //share s_wave_size with exec_hi >- >- /* save VGPRs */ >- ////////////////////////////// >- L_SAVE_VGPR: >- >- s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_ENABLE_SAVE_VGPR_EXEC_HI >- s_mov_b32 exec_hi, 0x00000000 >- s_branch L_SAVE_VGPR_NORMAL >- L_ENABLE_SAVE_VGPR_EXEC_HI: >- s_mov_b32 exec_hi, 0xFFFFFFFF >- L_SAVE_VGPR_NORMAL: >- s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size >- //for wave32 and wave64, the num of vgpr function is the same? >- s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 >- s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible >- //determine it is wave32 or wave64 >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_SAVE_VGPR_WAVE64 >- >- //zhenxu added it for save vgpr for wave32 >- s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 7 //NUM_RECORDS in bytes (32 threads*4) >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_mov_b32 m0, 0x0 //VGPR initial index value =0 >- //s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 >- //s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later, doesn't need this in gfx10 >- >- L_SAVE_VGPR_WAVE32_LOOP: >- v_movrels_b32 v0, v0 //v0 = v[0+m0] >- >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else >- buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- end >- >- s_add_u32 m0, m0, 1 //next vgpr index >- s_add_u32 s_save_mem_offset, s_save_mem_offset, 128 //every buffer_store_dword does 128 bytes >- s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_VGPR_WAVE32_LOOP //VGPR save is complete? >- s_branch L_SAVE_LDS >- //save vgpr for wave32 ends >- >- L_SAVE_VGPR_WAVE64: >- s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_mov_b32 m0, 0x0 //VGPR initial index value =0 >- //s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 >- //s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later, doesn't need this in gfx10 >- >- L_SAVE_VGPR_WAVE64_LOOP: >- v_movrels_b32 v0, v0 //v0 = v[0+m0] >- >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else >- buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- end >- >- s_add_u32 m0, m0, 1 //next vgpr index >- s_add_u32 s_save_mem_offset, s_save_mem_offset, 256 //every buffer_store_dword does 256 bytes >- s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_VGPR_WAVE64_LOOP //VGPR save is complete? >- //s_set_gpr_idx_off >- // >- //Below part will be the save shared vgpr part (new for gfx10) >- s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) //shared_vgpr_size >- s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? >- s_cbranch_scc0 L_SAVE_LDS //no shared_vgpr used? jump to L_SAVE_LDS >- s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) >- //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. >- //save shared_vgpr will start from the index of m0 >- s_add_u32 s_save_alloc_size, s_save_alloc_size, m0 >- s_mov_b32 exec_lo, 0xFFFFFFFF >- s_mov_b32 exec_hi, 0x00000000 >- L_SAVE_SHARED_VGPR_WAVE64_LOOP: >- v_movrels_b32 v0, v0 //v0 = v[0+m0] >- buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- s_add_u32 m0, m0, 1 //next vgpr index >- s_add_u32 s_save_mem_offset, s_save_mem_offset, 128 //every buffer_store_dword does 256 bytes >- s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_SHARED_VGPR_WAVE64_LOOP //SHARED_VGPR save is complete? >- >- /* save LDS */ >- ////////////////////////////// >- L_SAVE_LDS: >- >- //Only check the first wave need LDS >- /* the first wave in the threadgroup */ >- s_barrier //FIXME not performance-optimal "LDS is used? wait for other waves in the same TG" >- s_and_b32 s_save_tmp, s_wave_size, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here >- s_cbranch_scc0 L_SAVE_SGPR >- >- s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_ENABLE_SAVE_LDS_EXEC_HI >- s_mov_b32 exec_hi, 0x00000000 >- s_branch L_SAVE_LDS_NORMAL >- L_ENABLE_SAVE_LDS_EXEC_HI: >- s_mov_b32 exec_hi, 0xFFFFFFFF >- L_SAVE_LDS_NORMAL: >- s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size >- s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? >- s_cbranch_scc0 L_SAVE_SGPR //no lds used? jump to L_SAVE_VGPR >- s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw >- s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes >- s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- //load 0~63*4(byte address) to vgpr v15 >- v_mbcnt_lo_u32_b32 v0, -1, 0 >- v_mbcnt_hi_u32_b32 v0, -1, v0 >- v_mul_u32_u24 v0, 4, v0 >- >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_mov_b32 m0, 0x0 >- s_cbranch_scc1 L_SAVE_LDS_LOOP_W64 >- >- L_SAVE_LDS_LOOP_W32: >- if (SAVE_LDS) >- ds_read_b32 v1, v0 >- s_waitcnt 0 //ensure data ready >- buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- //buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 //save lds to memory doesn't exist in 10 >- end >- s_add_u32 m0, m0, 128 //every buffer_store_lds does 128 bytes >- s_add_u32 s_save_mem_offset, s_save_mem_offset, 128 //mem offset increased by 128 bytes >- v_add_nc_u32 v0, v0, 128 >- s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_LDS_LOOP_W32 //LDS save is complete? >- s_branch L_SAVE_SGPR >- >- L_SAVE_LDS_LOOP_W64: >- if (SAVE_LDS) >- ds_read_b32 v1, v0 >- s_waitcnt 0 //ensure data ready >- buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- //buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 //save lds to memory doesn't exist in 10 >- end >- s_add_u32 m0, m0, 256 //every buffer_store_lds does 256 bytes >- s_add_u32 s_save_mem_offset, s_save_mem_offset, 256 //mem offset increased by 256 bytes >- v_add_nc_u32 v0, v0, 256 >- s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_LDS_LOOP_W64 //LDS save is complete? >- >- >- /* save SGPRs */ >- ////////////////////////////// >- //s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size >- //s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 >- //s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) >- //s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 3 //In gfx10, Number of SGPRs = (sgpr_size + 1) * 8 (non-zero value) >- L_SAVE_SGPR: >- //need to look at it is wave32 or wave64 >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_SAVE_SGPR_VMEM_WAVE64 >- if (SGPR_SAVE_USE_SQC) >- s_lshl_b32 s_save_buf_rsrc2, s_sgpr_save_num, 2 //NUM_RECORDS in bytes >- else >- s_lshl_b32 s_save_buf_rsrc2, s_sgpr_save_num, 7 //NUM_RECORDS in bytes (32 threads) >- end >- s_branch L_SAVE_SGPR_CONT >- L_SAVE_SGPR_VMEM_WAVE64: >- if (SGPR_SAVE_USE_SQC) >- s_lshl_b32 s_save_buf_rsrc2, s_sgpr_save_num, 2 //NUM_RECORDS in bytes >- else >- s_lshl_b32 s_save_buf_rsrc2, s_sgpr_save_num, 8 //NUM_RECORDS in bytes (64 threads) >- end >- L_SAVE_SGPR_CONT: >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- //s_mov_b32 m0, 0x0 //SGPR initial index value =0 >- //s_nop 0x0 //Manually inserted wait states >- >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- >- s_mov_b32 m0, 0x0 //SGPR initial index value =0 >- s_nop 0x0 //Manually inserted wait states >- >- s_cbranch_scc1 L_SAVE_SGPR_LOOP_WAVE64 >- >- L_SAVE_SGPR_LOOP_WAVE32: >- s_movrels_b32 s0, s0 //s0 = s[0+m0] >- //zhenxu, adding one more argument to save sgpr function, this is only for vmem, using sqc is not change >- write_sgpr_to_mem_wave32(s0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //PV: the best performance should be using s_buffer_store_dwordx4 >- s_add_u32 m0, m0, 1 //next sgpr index >- s_cmp_lt_u32 m0, s_sgpr_save_num //scc = (m0 < s_sgpr_save_num) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_SGPR_LOOP_WAVE32 //SGPR save is complete? >- s_branch L_SAVE_HWREG >- >- L_SAVE_SGPR_LOOP_WAVE64: >- s_movrels_b32 s0, s0 //s0 = s[0+m0] >- //zhenxu, adding one more argument to save sgpr function, this is only for vmem, using sqc is not change >- write_sgpr_to_mem_wave64(s0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //PV: the best performance should be using s_buffer_store_dwordx4 >- s_add_u32 m0, m0, 1 //next sgpr index >- s_cmp_lt_u32 m0, s_sgpr_save_num //scc = (m0 < s_sgpr_save_num) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_SGPR_LOOP_WAVE64 //SGPR save is complete? >- >- >- /* save HW registers */ >- ////////////////////////////// >- L_SAVE_HWREG: >- s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_SAVE_HWREG_WAVE64 >- >- write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //M0 >- >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) >- s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 >- s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over >- end >- >- write_sgpr_to_mem_wave32(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //PC >- write_sgpr_to_mem_wave32(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- write_sgpr_to_mem_wave32(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //EXEC >- write_sgpr_to_mem_wave32(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- write_sgpr_to_mem_wave32(s_save_status, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //STATUS >- >- //s_save_trapsts conflicts with s_save_alloc_size >- s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >- write_sgpr_to_mem_wave32(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //TRAPSTS >- >- //write_sgpr_to_mem_wave32(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //XNACK_MASK_LO >- write_sgpr_to_mem_wave32(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //XNACK_MASK_HI >- >- //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 >- s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE >- write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- if(SAVE_RESTORE_HWID_DDID) >- s_getreg_b32 s_save_m0, hwreg(HW_REG_HW_ID1) //HW_ID1, handler records the SE/SA/WGP/SIMD/wave of the original wave >- write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- end >- s_branch L_S_PGM_END_SAVED >- >- L_SAVE_HWREG_WAVE64: >- write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //M0 >- >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) >- s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 >- s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over >- end >- >- write_sgpr_to_mem_wave64(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //PC >- write_sgpr_to_mem_wave64(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- write_sgpr_to_mem_wave64(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //EXEC >- write_sgpr_to_mem_wave64(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- write_sgpr_to_mem_wave64(s_save_status, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //STATUS >- >- //s_save_trapsts conflicts with s_save_alloc_size >- s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >- write_sgpr_to_mem_wave64(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //TRAPSTS >- >- //write_sgpr_to_mem_wave64(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //XNACK_MASK_LO >- write_sgpr_to_mem_wave64(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) //XNACK_MASK_HI >- >- //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 >- s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE >- write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- >- >- if(SAVE_RESTORE_HWID_DDID) >- s_getreg_b32 s_save_m0, hwreg(HW_REG_HW_ID1) //HW_ID1, handler records the SE/SA/WGP/SIMD/wave of the original wave >- write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- >- /* save DDID */ >- ////////////////////////////// >- L_SAVE_DDID: >- //EXEC has been saved, no vector inst following >- s_mov_b32 exec_lo, 0x80000000 //Set MSB to 1. Cleared when draw index is returned >- s_sendmsg sendmsg(MSG_GET_DDID) >- >- L_WAIT_DDID_LOOP: >- s_nop 7 // sleep a bit >- s_bitcmp0_b32 exec_lo, 31 // test to see if MSB is cleared, meaning done >- s_cbranch_scc0 L_WAIT_DDID_LOOP >- >- s_mov_b32 s_save_m0, exec_lo >- >- >- s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_SAVE_DDID_WAVE64 >- >- write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- >- L_SAVE_DDID_WAVE64: >- write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) >- >- end >- >- L_S_PGM_END_SAVED: >- /* S_PGM_END_SAVED */ //FIXME graphics ONLY >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) >- s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] >- s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 >- s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over >- s_rfe_b64 s_save_pc_lo //Return to the main shader program >- else >- end >- >- >- s_branch L_END_PGM >- >- >- >-/**************************************************************************/ >-/* restore routine */ >-/**************************************************************************/ >+ >+ /* inform SPI the readiness and wait for SPI's go signal */ >+ s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI >+ s_mov_b32 s_save_exec_hi, exec_hi >+ s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive >+ >+ s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC >+ >+L_SLEEP: >+ // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause >+ // SQ hang, since the 7,8th wave could not get arbit to exec inst, while >+ // other waves are stuck into the sleep-loop and waiting for wrexec!=0 >+ s_sleep 0x2 >+ s_cbranch_execz L_SLEEP >+ >+ /* setup Resource Contants */ >+ s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo >+ s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi >+ s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE >+ s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited >+ s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC >+ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK >+ s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) >+ s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC >+ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK >+ s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) >+ s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE >+ >+ s_mov_b32 s_save_m0, m0 >+ >+ /* global mem offset */ >+ s_mov_b32 s_save_mem_offset, 0x0 >+ s_getreg_b32 s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) >+ s_lshl_b32 s_wave_size, s_wave_size, S_WAVE_SIZE >+ s_or_b32 s_wave_size, s_save_spi_init_hi, s_wave_size //share s_wave_size with exec_hi, it's at bit25 >+ >+ /* save HW registers */ >+ >+L_SAVE_HWREG: >+ // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) >+ get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) >+ get_svgpr_size_bytes(s_save_tmp) >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() >+ >+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) >+ write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) >+ write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) >+ write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) >+ write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) >+ write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) >+ >+ s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) >+ write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) >+ write_hwreg_to_mem(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset) >+ >+ s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) >+ write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) >+ >+ s_getreg_b32 s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO) >+ write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) >+ >+ s_getreg_b32 s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI) >+ write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) >+ >+ /* the first wave in the threadgroup */ >+ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK >+ s_mov_b32 s_save_exec_hi, 0x0 >+ s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] >+ >+ /* save SGPRs */ >+ // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... >+ >+ // SGPR SR memory offset : size(VGPR)+size(SVGPR) >+ get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) >+ get_svgpr_size_bytes(s_save_tmp) >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp >+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 >+ s_mov_b32 s_save_xnack_mask, s_save_buf_rsrc0 >+ s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset >+ s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 >+ >+ s_mov_b32 m0, 0x0 //SGPR initial index value =0 >+ s_nop 0x0 //Manually inserted wait states >+L_SAVE_SGPR_LOOP: >+ // SGPR is allocated in 16 SGPR granularity >+ s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] >+ s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] >+ s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] >+ s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] >+ s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] >+ s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] >+ s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] >+ s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] >+ >+ write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) >+ s_add_u32 m0, m0, 16 //next sgpr index >+ s_cmp_lt_u32 m0, 96 //scc = (m0 < first 96 SGPR) ? 1 : 0 >+ s_cbranch_scc1 L_SAVE_SGPR_LOOP //first 96 SGPR save is complete? >+ >+ //save the rest 12 SGPR >+ s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] >+ s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] >+ s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] >+ s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] >+ s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] >+ s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] >+ write_12sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) >+ >+ // restore s_save_buf_rsrc0,1 >+ s_mov_b32 s_save_buf_rsrc0, s_save_xnack_mask >+ >+ /* save first 4 VGPR, then LDS save could use */ >+ // each wave will alloc 4 vgprs at least... >+ >+ s_mov_b32 s_save_mem_offset, 0 >+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on >+ s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_cbranch_scc1 L_ENABLE_SAVE_4VGPR_EXEC_HI >+ s_mov_b32 exec_hi, 0x00000000 >+ s_branch L_SAVE_4VGPR_WAVE32 >+L_ENABLE_SAVE_4VGPR_EXEC_HI: >+ s_mov_b32 exec_hi, 0xFFFFFFFF >+ s_branch L_SAVE_4VGPR_WAVE64 >+L_SAVE_4VGPR_WAVE32: >+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ // VGPR Allocated in 4-GPR granularity >+ >+ buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128 >+ buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2 >+ buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3 >+ s_branch L_SAVE_LDS >+ >+L_SAVE_4VGPR_WAVE64: >+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ // VGPR Allocated in 4-GPR granularity >+ >+ buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 >+ buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 >+ buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 >+ >+ /* save LDS */ >+ >+L_SAVE_LDS: >+ // Change EXEC to all threads... >+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on >+ s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_cbranch_scc1 L_ENABLE_SAVE_LDS_EXEC_HI >+ s_mov_b32 exec_hi, 0x00000000 >+ s_branch L_SAVE_LDS_NORMAL >+L_ENABLE_SAVE_LDS_EXEC_HI: >+ s_mov_b32 exec_hi, 0xFFFFFFFF >+L_SAVE_LDS_NORMAL: >+ s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) >+ s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? >+ s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE >+ >+ s_barrier //LDS is used? wait for other waves in the same TG >+ s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK >+ s_cbranch_scc0 L_SAVE_LDS_DONE >+ >+ // first wave do LDS save; >+ >+ s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw >+ s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes >+ s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes >+ >+ // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) >+ // >+ get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) >+ get_svgpr_size_bytes(s_save_tmp) >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() >+ >+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ //load 0~63*4(byte address) to vgpr v0 >+ v_mbcnt_lo_u32_b32 v0, -1, 0 >+ v_mbcnt_hi_u32_b32 v0, -1, v0 >+ v_mul_u32_u24 v0, 4, v0 >+ >+ s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_mov_b32 m0, 0x0 >+ s_cbranch_scc1 L_SAVE_LDS_W64 >+ >+L_SAVE_LDS_W32: >+ s_mov_b32 s3, 128 >+ s_nop 0 >+ s_nop 0 >+ s_nop 0 >+L_SAVE_LDS_LOOP_W32: >+ ds_read_b32 v1, v0 >+ s_waitcnt 0 >+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >+ >+ s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 >+ v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes >+ s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_SAVE_LDS_LOOP_W32 //LDS save is complete? >+ >+ s_branch L_SAVE_LDS_DONE >+ >+L_SAVE_LDS_W64: >+ s_mov_b32 s3, 256 >+ s_nop 0 >+ s_nop 0 >+ s_nop 0 >+L_SAVE_LDS_LOOP_W64: >+ ds_read_b32 v1, v0 >+ s_waitcnt 0 >+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >+ >+ s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 >+ v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes >+ s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_SAVE_LDS_LOOP_W64 //LDS save is complete? >+ >+L_SAVE_LDS_DONE: >+ /* save VGPRs - set the Rest VGPRs */ >+L_SAVE_VGPR: >+ // VGPR SR memory offset: 0 >+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on >+ s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_cbranch_scc1 L_ENABLE_SAVE_VGPR_EXEC_HI >+ s_mov_b32 s_save_mem_offset, (0+128*4) // for the rest VGPRs >+ s_mov_b32 exec_hi, 0x00000000 >+ s_branch L_SAVE_VGPR_NORMAL >+L_ENABLE_SAVE_VGPR_EXEC_HI: >+ s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs >+ s_mov_b32 exec_hi, 0xFFFFFFFF >+L_SAVE_VGPR_NORMAL: >+ s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) >+ s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 >+ s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) >+ //determine it is wave32 or wave64 >+ s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_cbranch_scc1 L_SAVE_VGPR_WAVE64 >+ >+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ // VGPR Allocated in 4-GPR granularity >+ >+ // VGPR store using dw burst >+ s_mov_b32 m0, 0x4 //VGPR initial index value =4 >+ s_cmp_lt_u32 m0, s_save_alloc_size >+ s_cbranch_scc0 L_SAVE_VGPR_END >+ >+L_SAVE_VGPR_W32_LOOP: >+ v_movrels_b32 v0, v0 //v0 = v[0+m0] >+ v_movrels_b32 v1, v1 //v1 = v[1+m0] >+ v_movrels_b32 v2, v2 //v2 = v[2+m0] >+ v_movrels_b32 v3, v3 //v3 = v[3+m0] >+ >+ buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128 >+ buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2 >+ buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3 >+ >+ s_add_u32 m0, m0, 4 //next vgpr index >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, 128*4 //every buffer_store_dword does 128 bytes >+ s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_SAVE_VGPR_W32_LOOP //VGPR save is complete? >+ >+ s_branch L_SAVE_VGPR_END >+ >+L_SAVE_VGPR_WAVE64: >+ s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ // VGPR store using dw burst >+ s_mov_b32 m0, 0x4 //VGPR initial index value =4 >+ s_cmp_lt_u32 m0, s_save_alloc_size >+ s_cbranch_scc0 L_SAVE_VGPR_END >+ >+L_SAVE_VGPR_W64_LOOP: >+ v_movrels_b32 v0, v0 //v0 = v[0+m0] >+ v_movrels_b32 v1, v1 //v1 = v[1+m0] >+ v_movrels_b32 v2, v2 //v2 = v[2+m0] >+ v_movrels_b32 v3, v3 //v3 = v[3+m0] >+ >+ buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 >+ buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 >+ buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 >+ >+ s_add_u32 m0, m0, 4 //next vgpr index >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes >+ s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_SAVE_VGPR_W64_LOOP //VGPR save is complete? >+ >+ //Below part will be the save shared vgpr part (new for gfx10) >+ s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) >+ s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? >+ s_cbranch_scc0 L_SAVE_VGPR_END //no shared_vgpr used? jump to L_SAVE_LDS >+ s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) >+ //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. >+ //save shared_vgpr will start from the index of m0 >+ s_add_u32 s_save_alloc_size, s_save_alloc_size, m0 >+ s_mov_b32 exec_lo, 0xFFFFFFFF >+ s_mov_b32 exec_hi, 0x00000000 >+L_SAVE_SHARED_VGPR_WAVE64_LOOP: >+ v_movrels_b32 v0, v0 //v0 = v[0+m0] >+ buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >+ s_add_u32 m0, m0, 1 //next vgpr index >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, 128 >+ s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_SAVE_SHARED_VGPR_WAVE64_LOOP //SHARED_VGPR save is complete? >+ >+L_SAVE_VGPR_END: >+ s_branch L_END_PGM > > L_RESTORE: >- /* Setup Resource Contants */ >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) >- //calculate wd_addr using absolute thread id >- v_readlane_b32 s_restore_tmp, v9, 0 >- //determine it is wave32 or wave64 >- s_getreg_b32 s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) //change to ttmp13 >- s_cmp_eq_u32 s_restore_size, 0 >- s_cbranch_scc1 L_RESTORE_WAVE32 >- s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 //SAVE WAVE64 >- s_branch L_RESTORE_CON >- L_RESTORE_WAVE32: >- s_lshr_b32 s_restore_tmp, s_restore_tmp, 5 //SAVE WAVE32 >- L_RESTORE_CON: >- s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE >- s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL >- else >- end >- >- s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo >- s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi >- s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE >- s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) >- s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC >- s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK >- s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position >- s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC >- s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK >- s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position >- s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE >- //determine it is wave32 or wave64 >- s_getreg_b32 s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) >- s_or_b32 s_restore_size, s_restore_spi_init_hi, s_restore_size //share s_wave_size with exec_hi >- >- /* global mem offset */ >- s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 >- >- /* restore VGPRs */ >- ////////////////////////////// >- L_RESTORE_VGPR: >- >- s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead >- s_and_b32 m0, s_restore_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_ENABLE_RESTORE_VGPR_EXEC_HI >- s_mov_b32 exec_hi, 0x00000000 >- s_branch L_RESTORE_VGPR_NORMAL >- L_ENABLE_RESTORE_VGPR_EXEC_HI: >- s_mov_b32 exec_hi, 0xFFFFFFFF >- L_RESTORE_VGPR_NORMAL: >- s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size >- s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 >- s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) >- //determine it is wave32 or wave64 >- s_and_b32 m0, s_restore_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_RESTORE_VGPR_WAVE64 >- >- s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 7 //NUM_RECORDS in bytes (32 threads*4) >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last >- s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 >- s_mov_b32 m0, 1 //VGPR initial index value = 1 >- //s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 >- //s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later, might not need this in gfx10 >- >- L_RESTORE_VGPR_WAVE32_LOOP: >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else >- buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 >- end >- s_waitcnt vmcnt(0) //ensure data ready >- v_movreld_b32 v0, v0 //v[0+m0] = v0 >- s_add_u32 m0, m0, 1 //next vgpr index >- s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //every buffer_load_dword does 128 bytes >- s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete? >- //s_set_gpr_idx_off >- /* VGPR restore on v0 */ >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else >- buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 >- end >- >- s_branch L_RESTORE_LDS >- >- L_RESTORE_VGPR_WAVE64: >- s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last >- s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 >- s_mov_b32 m0, 1 //VGPR initial index value = 1 >- L_RESTORE_VGPR_WAVE64_LOOP: >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else >- buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 >- end >- s_waitcnt vmcnt(0) //ensure data ready >- v_movreld_b32 v0, v0 //v[0+m0] = v0 >- s_add_u32 m0, m0, 1 //next vgpr index >- s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //every buffer_load_dword does 256 bytes >- s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? >- //s_set_gpr_idx_off >- // >- //Below part will be the restore shared vgpr part (new for gfx10) >- s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) //shared_vgpr_size >- s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? >- s_cbranch_scc0 L_RESTORE_V0 //no shared_vgpr used? jump to L_SAVE_LDS >- s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) >- //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. >- //restore shared_vgpr will start from the index of m0 >- s_add_u32 s_restore_alloc_size, s_restore_alloc_size, m0 >- s_mov_b32 exec_lo, 0xFFFFFFFF >- s_mov_b32 exec_hi, 0x00000000 >- L_RESTORE_SHARED_VGPR_WAVE64_LOOP: >- buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 >- s_waitcnt vmcnt(0) //ensure data ready >- v_movreld_b32 v0, v0 //v[0+m0] = v0 >- s_add_u32 m0, m0, 1 //next vgpr index >- s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //every buffer_load_dword does 256 bytes >- s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_RESTORE_SHARED_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? >- >- s_mov_b32 exec_hi, 0xFFFFFFFF //restore back exec_hi before restoring V0!! >- >- /* VGPR restore on v0 */ >- L_RESTORE_V0: >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else >- buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 >- end >- >- >- /* restore LDS */ >- ////////////////////////////// >- L_RESTORE_LDS: >- >- //Only need to check the first wave >- /* the first wave in the threadgroup */ >- s_and_b32 s_restore_tmp, s_restore_size, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK >- s_cbranch_scc0 L_RESTORE_SGPR >- >- s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead >- s_and_b32 m0, s_restore_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_ENABLE_RESTORE_LDS_EXEC_HI >- s_mov_b32 exec_hi, 0x00000000 >- s_branch L_RESTORE_LDS_NORMAL >- L_ENABLE_RESTORE_LDS_EXEC_HI: >- s_mov_b32 exec_hi, 0xFFFFFFFF >- L_RESTORE_LDS_NORMAL: >- s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size >- s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? >- s_cbranch_scc0 L_RESTORE_SGPR //no lds used? jump to L_RESTORE_VGPR >- s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw >- s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes >- s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_and_b32 m0, s_wave_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_mov_b32 m0, 0x0 >- s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 >- >- L_RESTORE_LDS_LOOP_W32: >- if (SAVE_LDS) >- buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 >- s_waitcnt 0 >- end >- s_add_u32 m0, m0, 128 //every buffer_load_dword does 256 bytes >- s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //mem offset increased by 256 bytes >- s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_RESTORE_LDS_LOOP_W32 //LDS restore is complete? >- s_branch L_RESTORE_SGPR >- >- L_RESTORE_LDS_LOOP_W64: >- if (SAVE_LDS) >- buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 >- s_waitcnt 0 >- end >- s_add_u32 m0, m0, 256 //every buffer_load_dword does 256 bytes >- s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //mem offset increased by 256 bytes >- s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 //LDS restore is complete? >- >- >- /* restore SGPRs */ >- ////////////////////////////// >- //s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size >- //s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 >- //s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) >- //s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 3 //Number of SGPRs = (sgpr_size + 1) * 8 (non-zero value) >- L_RESTORE_SGPR: >- //need to look at it is wave32 or wave64 >- s_and_b32 m0, s_restore_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_RESTORE_SGPR_VMEM_WAVE64 >- if (SGPR_SAVE_USE_SQC) >- s_lshl_b32 s_restore_buf_rsrc2, s_sgpr_save_num, 2 //NUM_RECORDS in bytes >- else >- s_lshl_b32 s_restore_buf_rsrc2, s_sgpr_save_num, 7 //NUM_RECORDS in bytes (32 threads) >- end >- s_branch L_RESTORE_SGPR_CONT >- L_RESTORE_SGPR_VMEM_WAVE64: >- if (SGPR_SAVE_USE_SQC) >- s_lshl_b32 s_restore_buf_rsrc2, s_sgpr_save_num, 2 //NUM_RECORDS in bytes >- else >- s_lshl_b32 s_restore_buf_rsrc2, s_sgpr_save_num, 8 //NUM_RECORDS in bytes (64 threads) >- end >- >- L_RESTORE_SGPR_CONT: >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_and_b32 m0, s_restore_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_RESTORE_SGPR_WAVE64 >- >- read_sgpr_from_mem_wave32(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //save s0 to s_restore_tmp >- s_mov_b32 m0, 0x1 >- >- L_RESTORE_SGPR_LOOP_WAVE32: >- read_sgpr_from_mem_wave32(s0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //PV: further performance improvement can be made >- s_waitcnt lgkmcnt(0) //ensure data ready >- s_movreld_b32 s0, s0 //s[0+m0] = s0 >- s_nop 0 // hazard SALU M0=> S_MOVREL >- s_add_u32 m0, m0, 1 //next sgpr index >- s_cmp_lt_u32 m0, s_sgpr_save_num //scc = (m0 < s_restore_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_RESTORE_SGPR_LOOP_WAVE32 //SGPR restore (except s0) is complete? >- s_mov_b32 s0, s_restore_tmp /* SGPR restore on s0 */ >- s_branch L_RESTORE_HWREG >- >- L_RESTORE_SGPR_WAVE64: >- read_sgpr_from_mem_wave64(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //save s0 to s_restore_tmp >- s_mov_b32 m0, 0x1 //SGPR initial index value =1 //go on with with s1 >- >- L_RESTORE_SGPR_LOOP_WAVE64: >- read_sgpr_from_mem_wave64(s0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //PV: further performance improvement can be made >- s_waitcnt lgkmcnt(0) //ensure data ready >- s_movreld_b32 s0, s0 //s[0+m0] = s0 >- s_nop 0 // hazard SALU M0=> S_MOVREL >- s_add_u32 m0, m0, 1 //next sgpr index >- s_cmp_lt_u32 m0, s_sgpr_save_num //scc = (m0 < s_restore_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_RESTORE_SGPR_LOOP_WAVE64 //SGPR restore (except s0) is complete? >- s_mov_b32 s0, s_restore_tmp /* SGPR restore on s0 */ >- >- >- /* restore HW registers */ >- ////////////////////////////// >- L_RESTORE_HWREG: >- s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_and_b32 m0, s_restore_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_RESTORE_HWREG_WAVE64 >- >- read_sgpr_from_mem_wave32(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //M0 >- read_sgpr_from_mem_wave32(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //PC >- read_sgpr_from_mem_wave32(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) >- read_sgpr_from_mem_wave32(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //EXEC >- read_sgpr_from_mem_wave32(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) >- read_sgpr_from_mem_wave32(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //STATUS >- read_sgpr_from_mem_wave32(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //TRAPSTS >- //read_sgpr_from_mem_wave32(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //XNACK_MASK_LO >- //read_sgpr_from_mem_wave32(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //XNACK_MASK_HI >- read_sgpr_from_mem_wave32(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //XNACK_MASK >- read_sgpr_from_mem_wave32(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //MODE >- if(SAVE_RESTORE_HWID_DDID) >- read_sgpr_from_mem_wave32(s_restore_hwid1, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //HW_ID1 >- end >- s_branch L_RESTORE_HWREG_FINISH >- >- L_RESTORE_HWREG_WAVE64: >- read_sgpr_from_mem_wave64(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //M0 >- read_sgpr_from_mem_wave64(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //PC >- read_sgpr_from_mem_wave64(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) >- read_sgpr_from_mem_wave64(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //EXEC >- read_sgpr_from_mem_wave64(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) >- read_sgpr_from_mem_wave64(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //STATUS >- read_sgpr_from_mem_wave64(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //TRAPSTS >- //read_sgpr_from_mem_wave64(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //XNACK_MASK_LO >- //read_sgpr_from_mem_wave64(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //XNACK_MASK_HI >- read_sgpr_from_mem_wave64(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //XNACK_MASK >- read_sgpr_from_mem_wave64(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //MODE >- if(SAVE_RESTORE_HWID_DDID) >- read_sgpr_from_mem_wave64(s_restore_hwid1, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) //HW_ID1 >- end >- L_RESTORE_HWREG_FINISH: >- s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS >- >- >- >- if(SAVE_RESTORE_HWID_DDID) >- L_RESTORE_DDID: >- s_mov_b32 m0, s_restore_hwid1 //virture ttrace support: The save-context handler records the SE/SA/WGP/SIMD/wave of the original wave >- s_ttracedata //and then can output it as SHADER_DATA to ttrace on restore to provide a correlation across the save-restore >- >- s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- s_and_b32 m0, s_restore_size, 1 >- s_cmp_eq_u32 m0, 1 >- s_cbranch_scc1 L_RESTORE_DDID_WAVE64 >- >- read_sgpr_from_mem_wave32(s_restore_ddid, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) >- s_branch L_RESTORE_DDID_FINISH >- L_RESTORE_DDID_WAVE64: >- read_sgpr_from_mem_wave64(s_restore_ddid, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC) >- >- L_RESTORE_DDID_FINISH: >- s_waitcnt lgkmcnt(0) >- //s_mov_b32 m0, s_restore_ddid >- //s_ttracedata >- if (RESTORE_DDID_IN_SGPR18) >- s_mov_b32 s18, s_restore_ddid >- end >- >- end >- >- s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS >- >- //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) >- s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) >- s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over >- end >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) >- s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal >- s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over >- end >- >- s_mov_b32 m0, s_restore_m0 >- s_mov_b32 exec_lo, s_restore_exec_lo >- s_mov_b32 exec_hi, s_restore_exec_hi >- >- s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts >+ /* Setup Resource Contants */ >+ s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo >+ s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi >+ s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE >+ s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) >+ s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC >+ s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK >+ s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) >+ s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC >+ s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK >+ s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) >+ s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE >+ //determine it is wave32 or wave64 >+ s_getreg_b32 s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) >+ s_lshl_b32 s_restore_size, s_restore_size, S_WAVE_SIZE >+ s_or_b32 s_restore_size, s_restore_spi_init_hi, s_restore_size >+ >+ s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK >+ s_cbranch_scc0 L_RESTORE_VGPR >+ >+ /* restore LDS */ >+L_RESTORE_LDS: >+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on >+ s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_cbranch_scc1 L_ENABLE_RESTORE_LDS_EXEC_HI >+ s_mov_b32 exec_hi, 0x00000000 >+ s_branch L_RESTORE_LDS_NORMAL >+L_ENABLE_RESTORE_LDS_EXEC_HI: >+ s_mov_b32 exec_hi, 0xFFFFFFFF >+L_RESTORE_LDS_NORMAL: >+ s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) >+ s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? >+ s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR >+ s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw >+ s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes >+ s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes >+ >+ // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) >+ // >+ get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) >+ get_svgpr_size_bytes(s_restore_tmp) >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() >+ >+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_mov_b32 m0, 0x0 >+ s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 >+ >+L_RESTORE_LDS_LOOP_W32: >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW >+ s_add_u32 m0, m0, 128 // 128 DW >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //mem offset increased by 128DW >+ s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_RESTORE_LDS_LOOP_W32 //LDS restore is complete? >+ s_branch L_RESTORE_VGPR >+ >+L_RESTORE_LDS_LOOP_W64: >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW >+ s_add_u32 m0, m0, 256 // 256 DW >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //mem offset increased by 256DW >+ s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 //LDS restore is complete? >+ >+ /* restore VGPRs */ >+L_RESTORE_VGPR: >+ // VGPR SR memory offset : 0 >+ s_mov_b32 s_restore_mem_offset, 0x0 >+ s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on >+ s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_cbranch_scc1 L_ENABLE_RESTORE_VGPR_EXEC_HI >+ s_mov_b32 exec_hi, 0x00000000 >+ s_branch L_RESTORE_VGPR_NORMAL >+L_ENABLE_RESTORE_VGPR_EXEC_HI: >+ s_mov_b32 exec_hi, 0xFFFFFFFF >+L_RESTORE_VGPR_NORMAL: >+ s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) >+ s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 >+ s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) >+ //determine it is wave32 or wave64 >+ s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_cbranch_scc1 L_RESTORE_VGPR_WAVE64 >+ >+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ // VGPR load using dw burst >+ s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 >+ s_mov_b32 m0, 4 //VGPR initial index value = 4 >+ >+L_RESTORE_VGPR_WAVE32_LOOP: >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 >+ buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128 >+ buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*2 >+ buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*3 >+ s_waitcnt vmcnt(0) >+ v_movreld_b32 v0, v0 //v[0+m0] = v0 >+ v_movreld_b32 v1, v1 >+ v_movreld_b32 v2, v2 >+ v_movreld_b32 v3, v3 >+ s_add_u32 m0, m0, 4 //next vgpr index >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 //every buffer_load_dword does 128 bytes >+ s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete? >+ >+ /* VGPR restore on v0 */ >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 >+ buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128 >+ buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2 >+ buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3 >+ >+ s_branch L_RESTORE_SGPR >+ >+L_RESTORE_VGPR_WAVE64: >+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ // VGPR load using dw burst >+ s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be the last >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 >+ s_mov_b32 m0, 4 //VGPR initial index value = 4 >+ >+L_RESTORE_VGPR_WAVE64_LOOP: >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 >+ buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 >+ buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 >+ buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 >+ s_waitcnt vmcnt(0) >+ v_movreld_b32 v0, v0 //v[0+m0] = v0 >+ v_movreld_b32 v1, v1 >+ v_movreld_b32 v2, v2 >+ v_movreld_b32 v3, v3 >+ s_add_u32 m0, m0, 4 //next vgpr index >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes >+ s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? >+ >+ //Below part will be the restore shared vgpr part (new for gfx10) >+ s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) //shared_vgpr_size >+ s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? >+ s_cbranch_scc0 L_RESTORE_V0 //no shared_vgpr used? >+ s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) >+ //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. >+ //restore shared_vgpr will start from the index of m0 >+ s_add_u32 s_restore_alloc_size, s_restore_alloc_size, m0 >+ s_mov_b32 exec_lo, 0xFFFFFFFF >+ s_mov_b32 exec_hi, 0x00000000 >+L_RESTORE_SHARED_VGPR_WAVE64_LOOP: >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 >+ s_waitcnt vmcnt(0) >+ v_movreld_b32 v0, v0 //v[0+m0] = v0 >+ s_add_u32 m0, m0, 1 //next vgpr index >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 >+ s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 >+ s_cbranch_scc1 L_RESTORE_SHARED_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? >+ >+ s_mov_b32 exec_hi, 0xFFFFFFFF //restore back exec_hi before restoring V0!! >+ >+ /* VGPR restore on v0 */ >+L_RESTORE_V0: >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 >+ buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 >+ buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 >+ buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 >+ >+ /* restore SGPRs */ >+ //will be 2+8+16*6 >+ // SGPR SR memory offset : size(VGPR)+size(SVGPR) >+L_RESTORE_SGPR: >+ get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) >+ get_svgpr_size_bytes(s_restore_tmp) >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() >+ s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 20*4 //s108~s127 is not saved >+ >+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ s_mov_b32 m0, s_sgpr_save_num >+ >+ read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) >+ s_waitcnt lgkmcnt(0) >+ >+ s_sub_u32 m0, m0, 4 // Restore from S[0] to S[104] >+ s_nop 0 // hazard SALU M0=> S_MOVREL >+ >+ s_movreld_b64 s0, s0 //s[0+m0] = s0 >+ s_movreld_b64 s2, s2 >+ >+ read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) >+ s_waitcnt lgkmcnt(0) >+ >+ s_sub_u32 m0, m0, 8 // Restore from S[0] to S[96] >+ s_nop 0 // hazard SALU M0=> S_MOVREL >+ >+ s_movreld_b64 s0, s0 //s[0+m0] = s0 >+ s_movreld_b64 s2, s2 >+ s_movreld_b64 s4, s4 >+ s_movreld_b64 s6, s6 >+ >+ L_RESTORE_SGPR_LOOP: >+ read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) >+ s_waitcnt lgkmcnt(0) >+ >+ s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] >+ s_nop 0 // hazard SALU M0=> S_MOVREL >+ >+ s_movreld_b64 s0, s0 //s[0+m0] = s0 >+ s_movreld_b64 s2, s2 >+ s_movreld_b64 s4, s4 >+ s_movreld_b64 s6, s6 >+ s_movreld_b64 s8, s8 >+ s_movreld_b64 s10, s10 >+ s_movreld_b64 s12, s12 >+ s_movreld_b64 s14, s14 >+ >+ s_cmp_eq_u32 m0, 0 //scc = (m0 < s_sgpr_save_num) ? 1 : 0 >+ s_cbranch_scc0 L_RESTORE_SGPR_LOOP >+ >+ /* restore HW registers */ >+L_RESTORE_HWREG: >+ // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) >+ get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) >+ get_svgpr_size_bytes(s_restore_tmp) >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp >+ s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() >+ >+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >+ >+ read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) >+ read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) >+ s_waitcnt lgkmcnt(0) >+ >+ s_setreg_b32 hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO), s_restore_flat_scratch >+ >+ read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) >+ s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS >+ >+ s_setreg_b32 hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI), s_restore_flat_scratch >+ >+ s_mov_b32 s_restore_tmp, s_restore_pc_hi >+ s_and_b32 s_restore_pc_hi, s_restore_tmp, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS >+ >+ s_mov_b32 m0, s_restore_m0 >+ s_mov_b32 exec_lo, s_restore_exec_lo >+ s_mov_b32 exec_hi, s_restore_exec_hi >+ >+ s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts > s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 >- s_setreg_b32 hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask //restore xnack_mask >- s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts >- s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT >+ s_setreg_b32 hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask >+ s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts >+ s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT > s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 >- //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore >- s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode >- //reuse s_restore_m0 as a temp register >- s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK >- s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT >- s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT >- s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero >- s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 >- s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK >- s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT >- s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT >- s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 >- s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK >- s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT >- s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp >- s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status >- >- s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG //FIXME not performance-optimal at this time >- >- >-// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution >- s_rfe_b64 s_restore_pc_lo // s_restore_m0[0] is used to set STATUS.inst_atc >- >- >-/**************************************************************************/ >-/* the END */ >-/**************************************************************************/ >-L_END_PGM: >+ s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode >+ s_and_b32 s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_RCNT_MASK >+ s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT >+ s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT >+ s_mov_b32 s_restore_mode, 0x0 >+ s_or_b32 s_restore_mode, s_restore_mode, s_restore_m0 >+ s_and_b32 s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_FIRST_REPLAY_MASK >+ s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT >+ s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT >+ s_or_b32 s_restore_mode, s_restore_mode, s_restore_m0 >+ s_and_b32 s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_REPLAY_W64H_MASK >+ s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_REPLAY_W64H_SHIFT >+ s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT >+ s_or_b32 s_restore_mode, s_restore_mode, s_restore_m0 >+ >+ s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK >+ s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT >+ s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_mode >+ >+ s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 >+ s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 >+ s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu >+ >+ s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG >+ >+ s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution >+ >+L_END_PGM: > s_endpgm >- >-end >+end >+ >+function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) >+ s_mov_b32 exec_lo, m0 >+ s_mov_b32 m0, s_mem_offset >+ s_buffer_store_dword s, s_rsrc, m0 glc:1 >+ s_add_u32 s_mem_offset, s_mem_offset, 4 >+ s_mov_b32 m0, exec_lo >+end >+ >+ >+function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) >+ s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 >+ s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 >+ s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 >+ s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 >+ s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 >+ s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 >+end >+ >+function write_12sgpr_to_mem(s, s_rsrc, s_mem_offset) >+ s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 >+ s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 >+ s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 >+ s_add_u32 s_rsrc[0], s_rsrc[0], 4*12 >+ s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 >+end >+ >+ >+function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) >+ s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 >+ s_add_u32 s_mem_offset, s_mem_offset, 4 >+end >+ >+function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) >+ s_sub_u32 s_mem_offset, s_mem_offset, 4*16 >+ s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 >+end >+ >+function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset) >+ s_sub_u32 s_mem_offset, s_mem_offset, 4*8 >+ s_buffer_load_dwordx8 s, s_rsrc, s_mem_offset glc:1 >+end >+ >+function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset) >+ s_sub_u32 s_mem_offset, s_mem_offset, 4*4 >+ s_buffer_load_dwordx4 s, s_rsrc, s_mem_offset glc:1 >+end > > >-/**************************************************************************/ >-/* the helper functions */ >-/**************************************************************************/ >-function write_sgpr_to_mem_wave32(s, s_rsrc, s_mem_offset, use_sqc, use_mtbuf) >- if (use_sqc) >- s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on >- s_mov_b32 m0, s_mem_offset >- s_buffer_store_dword s, s_rsrc, m0 glc:1 >- s_add_u32 s_mem_offset, s_mem_offset, 4 >- s_mov_b32 m0, exec_lo >- elsif (use_mtbuf) >- v_mov_b32 v0, s >- tbuffer_store_format_x v0, v0, s_rsrc, s_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- s_add_u32 s_mem_offset, s_mem_offset, 128 >- else >- v_mov_b32 v0, s >- buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 >- s_add_u32 s_mem_offset, s_mem_offset, 128 >- end >+function get_lds_size_bytes(s_lds_size_byte) >+ s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) >+ s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW > end > >-function write_sgpr_to_mem_wave64(s, s_rsrc, s_mem_offset, use_sqc, use_mtbuf) >- if (use_sqc) >- s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on >- s_mov_b32 m0, s_mem_offset >- s_buffer_store_dword s, s_rsrc, m0 glc:1 >- s_add_u32 s_mem_offset, s_mem_offset, 4 >- s_mov_b32 m0, exec_lo >- elsif (use_mtbuf) >- v_mov_b32 v0, s >- tbuffer_store_format_x v0, v0, s_rsrc, s_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- s_add_u32 s_mem_offset, s_mem_offset, 256 >- else >- v_mov_b32 v0, s >- buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 >- s_add_u32 s_mem_offset, s_mem_offset, 256 >- end >+function get_vgpr_size_bytes(s_vgpr_size_byte, s_size) >+ s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) >+ s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 >+ s_lshr_b32 m0, s_size, S_WAVE_SIZE >+ s_and_b32 m0, m0, 1 >+ s_cmp_eq_u32 m0, 1 >+ s_cbranch_scc1 L_ENABLE_SHIFT_W64 >+ s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+7) //Number of VGPRs = (vgpr_size + 1) * 4 * 32 * 4 (non-zero value) >+ s_branch L_SHIFT_DONE >+L_ENABLE_SHIFT_W64: >+ s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) >+L_SHIFT_DONE: > end > >-function read_sgpr_from_mem_wave32(s, s_rsrc, s_mem_offset, use_sqc) >- s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 >- if (use_sqc) >- s_add_u32 s_mem_offset, s_mem_offset, 4 >- else >- s_add_u32 s_mem_offset, s_mem_offset, 128 >- end >+function get_svgpr_size_bytes(s_svgpr_size_byte) >+ s_getreg_b32 s_svgpr_size_byte, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) >+ s_lshl_b32 s_svgpr_size_byte, s_svgpr_size_byte, (3+7) > end > >-function read_sgpr_from_mem_wave64(s, s_rsrc, s_mem_offset, use_sqc) >- s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 >- if (use_sqc) >- s_add_u32 s_mem_offset, s_mem_offset, 4 >- else >- s_add_u32 s_mem_offset, s_mem_offset, 256 >- end >+function get_sgpr_size_bytes >+ return 512 > end > >+function get_hwreg_size_bytes >+ return 128 >+end >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm 2019-08-31 15:01:11.853736168 -0500 >@@ -24,78 +24,6 @@ > * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex > */ > >-/* HW (VI) source code for CWSR trap handler */ >-/* Version 18 + multiple trap handler */ >- >-// this performance-optimal version was originally from Seven Xu at SRDC >- >-// Revison #18 --... >-/* Rev History >-** #1. Branch from gc dv. //gfxip/gfx8/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) >-** #4. SR Memory Layout: >-** 1. VGPR-SGPR-HWREG-{LDS} >-** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. >-** #5. Update: 1. Accurate g8sr_ts_save_d timestamp >-** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) >-** #7. Update: 1. don't barrier if noLDS >-** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version >-** 2. Fix SQ issue by s_sleep 2 >-** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last >-** 2. optimize s_buffer save by burst 16sgprs... >-** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. >-** #11. Update 1. Add 2 more timestamp for debug version >-** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance >-** #13. Integ 1. Always use MUBUF for PV trap shader... >-** #14. Update 1. s_buffer_store soft clause... >-** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. >-** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree >-** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] >-** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... >-** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 >-** 2. FUNC - Handle non-CWSR traps >-*/ >- >-var G8SR_WDMEM_HWREG_OFFSET = 0 >-var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes >- >-// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. >- >-var G8SR_DEBUG_TIMESTAMP = 0 >-var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset >-var s_g8sr_ts_save_s = s[34:35] // save start >-var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi >-var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ >-var s_g8sr_ts_save_d = s[40:41] // save end >-var s_g8sr_ts_restore_s = s[42:43] // restore start >-var s_g8sr_ts_restore_d = s[44:45] // restore end >- >-var G8SR_VGPR_SR_IN_DWX4 = 0 >-var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes >-var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 >- >- >-/*************************************************************************/ >-/* control on how to run the shader */ >-/*************************************************************************/ >-//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) >-var EMU_RUN_HACK = 0 >-var EMU_RUN_HACK_RESTORE_NORMAL = 0 >-var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 >-var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 >-var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK >-var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK >-var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK >-var SAVE_LDS = 1 >-var WG_BASE_ADDR_LO = 0x9000a000 >-var WG_BASE_ADDR_HI = 0x0 >-var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem >-var CTX_SAVE_CONTROL = 0x0 >-var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL >-var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) >-var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write >-var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes >-var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing >- > /**************************************************************************/ > /* variables */ > /**************************************************************************/ >@@ -226,16 +154,7 @@ > type(CS) > > >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore >- //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC >- s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC >- s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. >- s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE >- //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE >- s_branch L_SKIP_RESTORE //NOT restore, SAVE actually >- else > s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save >- end > > L_JUMP_TO_RESTORE: > s_branch L_RESTORE //restore >@@ -249,7 +168,7 @@ > s_cbranch_scc1 L_SAVE //this is the operation for save > > // ********* Handle non-CWSR traps ******************* >-if (!EMU_RUN_HACK) >+ > /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */ > s_load_dwordx4 [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0 > s_waitcnt lgkmcnt(0) >@@ -268,7 +187,7 @@ > s_and_b32 ttmp1, ttmp1, 0xFFFF > set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC) > s_rfe_b64 [ttmp0, ttmp1] >-end >+ > // ********* End handling of non-CWSR traps ******************* > > /**************************************************************************/ >@@ -276,12 +195,6 @@ > /**************************************************************************/ > > L_SAVE: >- >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_save_s >- s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? >-end >- > s_mov_b32 s_save_tmp, 0 //clear saveCtx bit > s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit > >@@ -303,16 +216,7 @@ > s_mov_b32 s_save_exec_hi, exec_hi > s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive > >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_sq_save_msg >- s_waitcnt lgkmcnt(0) >-end >- >- if (EMU_RUN_HACK) >- >- else > s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC >- end > > // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. > s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) >@@ -321,36 +225,9 @@ > L_SLEEP: > s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 > >- if (EMU_RUN_HACK) >- >- else > s_cbranch_execz L_SLEEP >- end >- >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_spi_wrexec >- s_waitcnt lgkmcnt(0) >-end > > /* setup Resource Contants */ >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) >- //calculate wd_addr using absolute thread id >- v_readlane_b32 s_save_tmp, v9, 0 >- s_lshr_b32 s_save_tmp, s_save_tmp, 6 >- s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE >- s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL >- else >- end >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) >- s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL >- else >- end >- >- > s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo > s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi > s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE >@@ -383,22 +260,10 @@ > > > s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > > write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 >- >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) >- s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 >- s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over >- s_mov_b32 tba_lo, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO >- s_mov_b32 tba_hi, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI >- end >- > write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC > write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) > write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC >@@ -440,18 +305,8 @@ > s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 > s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) > >- if (SGPR_SAVE_USE_SQC) > s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes >- else >- s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) >- end >- >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- > > // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 > //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 >@@ -490,30 +345,14 @@ > s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on > s_mov_b32 exec_hi, 0xFFFFFFFF > >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- > > // VGPR Allocated in 4-GPR granularity > >-if G8SR_VGPR_SR_IN_DWX4 >- // the const stride for DWx4 is 4*4 bytes >- s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes >- >- buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- >- s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes >-else > buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 > buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 > buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 > buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 >-end > > > >@@ -549,64 +388,10 @@ > s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() > > >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- > s_mov_b32 m0, 0x0 //lds_offset initial value = 0 > > >-var LDS_DMA_ENABLE = 0 >-var UNROLL = 0 >-if UNROLL==0 && LDS_DMA_ENABLE==1 >- s_mov_b32 s3, 256*2 >- s_nop 0 >- s_nop 0 >- s_nop 0 >- L_SAVE_LDS_LOOP: >- //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? >- if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity >- buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW >- buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW >- end >- >- s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes >- s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes >- s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? >- >-elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss >- // store from higest LDS address to lowest >- s_mov_b32 s3, 256*2 >- s_sub_u32 m0, s_save_alloc_size, s3 >- s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 >- s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... >- s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest >- s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction >- s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc >- s_nop 0 >- s_nop 0 >- s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes >- s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved >- s_add_u32 s0, s0,s_save_alloc_size >- s_addc_u32 s1, s1, 0 >- s_setpc_b64 s[0:1] >- >- >- for var i =0; i< 128; i++ >- // be careful to make here a 64Byte aligned address, which could improve performance... >- buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW >- buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW >- >- if i!=127 >- s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline >- s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 >- end >- end >- >-else // BUFFER_STORE > v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 > v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid > v_mul_i32_i24 v2, v3, 8 // tid*8 >@@ -628,8 +413,6 @@ > // restore rsrc3 > s_mov_b32 s_save_buf_rsrc3, s0 > >-end >- > L_SAVE_LDS_DONE: > > >@@ -647,44 +430,8 @@ > s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 > s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible > s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- >- // VGPR Allocated in 4-GPR granularity > >-if G8SR_VGPR_SR_IN_DWX4 >- // the const stride for DWx4 is 4*4 bytes >- s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes >- >- s_mov_b32 m0, 4 // skip first 4 VGPRs >- s_cmp_lt_u32 m0, s_save_alloc_size >- s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs >- >- s_set_gpr_idx_on m0, 0x1 // This will change M0 >- s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 >-L_SAVE_VGPR_LOOP: >- v_mov_b32 v0, v0 // v0 = v[0+m0] >- v_mov_b32 v1, v1 >- v_mov_b32 v2, v2 >- v_mov_b32 v3, v3 >- >- >- buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- s_add_u32 m0, m0, 4 >- s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 >- s_cmp_lt_u32 m0, s_save_alloc_size >- s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? >- s_set_gpr_idx_off >-L_SAVE_VGPR_LOOP_END: >- >- s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes >-else > // VGPR store using dw burst > s_mov_b32 m0, 0x4 //VGPR initial index value =0 > s_cmp_lt_u32 m0, s_save_alloc_size >@@ -700,52 +447,18 @@ > v_mov_b32 v2, v2 //v0 = v[0+m0] > v_mov_b32 v3, v3 //v0 = v[0+m0] > >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else > buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 > buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 > buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 > buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 >- end > > s_add_u32 m0, m0, 4 //next vgpr index > s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes > s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 > s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? > s_set_gpr_idx_off >-end > > L_SAVE_VGPR_END: >- >- >- >- >- >- >- /* S_PGM_END_SAVED */ //FIXME graphics ONLY >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) >- s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] >- s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 >- s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over >- s_rfe_b64 s_save_pc_lo //Return to the main shader program >- else >- end >- >-// Save Done timestamp >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_save_d >- // SGPR SR memory offset : size(VGPR) >- get_vgpr_size_bytes(s_save_mem_offset) >- s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET >- s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? >- // Need reset rsrc2?? >- s_mov_b32 m0, s_save_mem_offset >- s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 >-end >- >- > s_branch L_END_PGM > > >@@ -756,27 +469,6 @@ > > L_RESTORE: > /* Setup Resource Contants */ >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) >- //calculate wd_addr using absolute thread id >- v_readlane_b32 s_restore_tmp, v9, 0 >- s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 >- s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE >- s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL >- else >- end >- >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_restore_s >- s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? >- // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... >- s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] >- s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. >-end >- >- >- > s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo > s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi > s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE >@@ -818,18 +510,12 @@ > s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? > > >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > s_mov_b32 m0, 0x0 //lds_offset initial value = 0 > > L_RESTORE_LDS_LOOP: >- if (SAVE_LDS) > buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW > buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW >- end > s_add_u32 m0, m0, 256*2 // 128 DW > s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW > s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 >@@ -848,40 +534,8 @@ > s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 > s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) > s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > >-if G8SR_VGPR_SR_IN_DWX4 >- get_vgpr_size_bytes(s_restore_mem_offset) >- s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 >- >- // the const stride for DWx4 is 4*4 bytes >- s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes >- >- s_mov_b32 m0, s_restore_alloc_size >- s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 >- >-L_RESTORE_VGPR_LOOP: >- buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 >- s_waitcnt vmcnt(0) >- s_sub_u32 m0, m0, 4 >- v_mov_b32 v0, v0 // v[0+m0] = v0 >- v_mov_b32 v1, v1 >- v_mov_b32 v2, v2 >- v_mov_b32 v3, v3 >- s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 >- s_cmp_eq_u32 m0, 0x8000 >- s_cbranch_scc0 L_RESTORE_VGPR_LOOP >- s_set_gpr_idx_off >- >- s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes >- >-else > // VGPR load using dw burst > s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last > s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 >@@ -890,14 +544,10 @@ > s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later > > L_RESTORE_VGPR_LOOP: >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else > buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 > buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 > buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 > buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 >- end > s_waitcnt vmcnt(0) //ensure data ready > v_mov_b32 v0, v0 //v[0+m0] = v0 > v_mov_b32 v1, v1 >@@ -909,16 +559,10 @@ > s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? > s_set_gpr_idx_off > /* VGPR restore on v0 */ >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else > buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 > buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 > buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 > buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 >- end >- >-end > > /* restore SGPRs */ > ////////////////////////////// >@@ -934,16 +578,8 @@ > s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 > s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) > >- if (SGPR_SAVE_USE_SQC) > s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes >- else >- s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) >- end >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111), > However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG >@@ -972,12 +608,6 @@ > ////////////////////////////// > L_RESTORE_HWREG: > >- >-if G8SR_DEBUG_TIMESTAMP >- s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo >- s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi >-end >- > // HWREG SR memory offset : size(VGPR)+size(SGPR) > get_vgpr_size_bytes(s_restore_mem_offset) > get_sgpr_size_bytes(s_restore_tmp) >@@ -985,11 +615,7 @@ > > > s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 > read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC >@@ -1006,16 +632,6 @@ > > s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS > >- //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) >- s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) >- s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over >- end >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) >- s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal >- s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over >- end >- > s_mov_b32 m0, s_restore_m0 > s_mov_b32 exec_lo, s_restore_exec_lo > s_mov_b32 exec_hi, s_restore_exec_hi >@@ -1048,11 +664,6 @@ > > s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time > >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_restore_d >- s_waitcnt lgkmcnt(0) >-end >- > // s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution > s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm 2019-08-31 15:01:11.853736168 -0500 >@@ -24,76 +24,9 @@ > * PROJECT=greenland ./sp3 cwsr_trap_handler_gfx9.asm -hex tmp.hex > */ > >-/* HW (GFX9) source code for CWSR trap handler */ >-/* Version 18 + multiple trap handler */ >- >-// this performance-optimal version was originally from Seven Xu at SRDC >- >-// Revison #18 --... >-/* Rev History >-** #1. Branch from gc dv. //gfxip/gfx9/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) >-** #4. SR Memory Layout: >-** 1. VGPR-SGPR-HWREG-{LDS} >-** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. >-** #5. Update: 1. Accurate g8sr_ts_save_d timestamp >-** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) >-** #7. Update: 1. don't barrier if noLDS >-** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version >-** 2. Fix SQ issue by s_sleep 2 >-** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last >-** 2. optimize s_buffer save by burst 16sgprs... >-** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. >-** #11. Update 1. Add 2 more timestamp for debug version >-** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance >-** #13. Integ 1. Always use MUBUF for PV trap shader... >-** #14. Update 1. s_buffer_store soft clause... >-** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. >-** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree >-** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] >-** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... >-** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 >-** 2. FUNC - Handle non-CWSR traps >-*/ >- >-var G8SR_WDMEM_HWREG_OFFSET = 0 >-var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes >- >-// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. >- >-var G8SR_DEBUG_TIMESTAMP = 0 >-var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset >-var s_g8sr_ts_save_s = s[34:35] // save start >-var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi >-var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ >-var s_g8sr_ts_save_d = s[40:41] // save end >-var s_g8sr_ts_restore_s = s[42:43] // restore start >-var s_g8sr_ts_restore_d = s[44:45] // restore end >- >-var G8SR_VGPR_SR_IN_DWX4 = 0 >-var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes >-var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 >- >- >-/*************************************************************************/ >-/* control on how to run the shader */ >-/*************************************************************************/ >-//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) >-var EMU_RUN_HACK = 0 >-var EMU_RUN_HACK_RESTORE_NORMAL = 0 >-var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 >-var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 >-var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK >-var SAVE_LDS = 1 >-var WG_BASE_ADDR_LO = 0x9000a000 >-var WG_BASE_ADDR_HI = 0x0 >-var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem >-var CTX_SAVE_CONTROL = 0x0 >-var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL >-var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) >-var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write >-var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes >-var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing > var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency >+var SAVE_AFTER_XNACK_ERROR = 1 //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger >+var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised > > /**************************************************************************/ > /* variables */ >@@ -107,6 +40,7 @@ > var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 > var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 > var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 >+var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK = 0x400000 > > var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 > var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 >@@ -127,12 +61,15 @@ > var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 > var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 > var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 >+var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 > > var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME > var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME > var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 > var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME > >+var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 >+ > var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 > var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 > >@@ -197,13 +134,15 @@ > var s_restore_spi_init_hi = exec_hi > > var s_restore_mem_offset = ttmp12 >+var s_restore_accvgpr_offset = ttmp13 > var s_restore_alloc_size = ttmp3 > var s_restore_tmp = ttmp2 > var s_restore_mem_offset_save = s_restore_tmp //no conflict >+var s_restore_accvgpr_offset_save = ttmp7 > > var s_restore_m0 = s_restore_alloc_size //no conflict > >-var s_restore_mode = ttmp7 >+var s_restore_mode = s_restore_accvgpr_offset_save > > var s_restore_pc_lo = ttmp0 > var s_restore_pc_hi = ttmp1 >@@ -226,20 +165,11 @@ > /* Shader Main*/ > > shader main >- asic(GFX9) >+ asic(DEFAULT) > type(CS) > > >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore >- //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC >- s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC >- s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. >- s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE >- //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE >- s_branch L_SKIP_RESTORE //NOT restore, SAVE actually >- else > s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save >- end > > L_JUMP_TO_RESTORE: > s_branch L_RESTORE //restore >@@ -248,12 +178,29 @@ > > s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC > s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save >+ >+if SINGLE_STEP_MISSED_WORKAROUND >+ // No single step exceptions if MODE.DEBUG_EN=0. >+ s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) >+ s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK >+ s_cbranch_scc0 L_NO_SINGLE_STEP_WORKAROUND >+ >+ // Second-level trap already handled exception if STATUS.HALT=1. >+ s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK >+ >+ // Prioritize single step exception over context save. >+ // Second-level trap will halt wave and RFE, re-entering for SAVECTX. >+ s_cbranch_scc0 L_FETCH_2ND_TRAP >+ >+L_NO_SINGLE_STEP_WORKAROUND: >+end >+ > s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) > s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save > s_cbranch_scc1 L_SAVE //this is the operation for save > > // ********* Handle non-CWSR traps ******************* >-if (!EMU_RUN_HACK) >+ > // Illegal instruction is a non-maskable exception which blocks context save. > // Halt the wavefront and return from the trap. > s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK >@@ -330,7 +277,7 @@ > set_status_without_spi_prio(s_save_status, ttmp2) > > s_rfe_b64 [ttmp0, ttmp1] >-end >+ > // ********* End handling of non-CWSR traps ******************* > > /**************************************************************************/ >@@ -338,12 +285,6 @@ > /**************************************************************************/ > > L_SAVE: >- >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_save_s >- s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? >-end >- > s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] > > s_mov_b32 s_save_tmp, 0 //clear saveCtx bit >@@ -365,16 +306,7 @@ > s_mov_b32 s_save_exec_hi, exec_hi > s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive > >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_sq_save_msg >- s_waitcnt lgkmcnt(0) >-end >- >- if (EMU_RUN_HACK) >- >- else > s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC >- end > > // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. > s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) >@@ -383,33 +315,7 @@ > L_SLEEP: > s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 > >- if (EMU_RUN_HACK) >- >- else > s_cbranch_execz L_SLEEP >- end >- >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_spi_wrexec >- s_waitcnt lgkmcnt(0) >-end >- >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) >- //calculate wd_addr using absolute thread id >- v_readlane_b32 s_save_tmp, v9, 0 >- s_lshr_b32 s_save_tmp, s_save_tmp, 6 >- s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE >- s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL >- else >- end >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) >- s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL >- else >- end > > // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic > // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 >@@ -459,20 +365,10 @@ > > > s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > > write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 >- >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) >- s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 >- s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over >- end >- > write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC > write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) > write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC >@@ -510,17 +406,9 @@ > s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 > s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) > >- if (SGPR_SAVE_USE_SQC) > s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes >- else >- s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) >- end > >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > > // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 >@@ -563,30 +451,25 @@ > s_mov_b32 xnack_mask_lo, 0x0 > s_mov_b32 xnack_mask_hi, 0x0 > >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > > // VGPR Allocated in 4-GPR granularity > >-if G8SR_VGPR_SR_IN_DWX4 >- // the const stride for DWx4 is 4*4 bytes >- s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes >- >- buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- >- s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes >-else >+if SAVE_AFTER_XNACK_ERROR >+ check_if_tcp_store_ok() >+ s_cbranch_scc1 L_SAVE_FIRST_VGPRS_WITH_TCP >+ >+ write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) >+ s_branch L_SAVE_LDS >+ >+L_SAVE_FIRST_VGPRS_WITH_TCP: >+end >+ > buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 > buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 > buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 > buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 >-end > > > >@@ -621,66 +504,34 @@ > s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() > > >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > s_mov_b32 m0, 0x0 //lds_offset initial value = 0 > > >-var LDS_DMA_ENABLE = 0 >-var UNROLL = 0 >-if UNROLL==0 && LDS_DMA_ENABLE==1 >- s_mov_b32 s3, 256*2 >- s_nop 0 >- s_nop 0 >- s_nop 0 >- L_SAVE_LDS_LOOP: >- //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? >- if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity >- buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW >- buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW >- end >- >- s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes >- s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes >- s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 >- s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? >- >-elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss >- // store from higest LDS address to lowest >- s_mov_b32 s3, 256*2 >- s_sub_u32 m0, s_save_alloc_size, s3 >- s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 >- s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... >- s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest >- s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction >- s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc >- s_nop 0 >- s_nop 0 >- s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes >- s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved >- s_add_u32 s0, s0,s_save_alloc_size >- s_addc_u32 s1, s1, 0 >- s_setpc_b64 s[0:1] >- >- >- for var i =0; i< 128; i++ >- // be careful to make here a 64Byte aligned address, which could improve performance... >- buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW >- buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW >- >- if i!=127 >- s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline >- s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 >- end >- end >- >-else // BUFFER_STORE > v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 > v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid >+ >+if SAVE_AFTER_XNACK_ERROR >+ check_if_tcp_store_ok() >+ s_cbranch_scc1 L_SAVE_LDS_WITH_TCP >+ >+ v_lshlrev_b32 v2, 2, v3 >+L_SAVE_LDS_LOOP_SQC: >+ ds_read2_b32 v[0:1], v2 offset0:0 offset1:0x40 >+ s_waitcnt lgkmcnt(0) >+ >+ write_vgprs_to_mem_with_sqc(v0, 2, s_save_buf_rsrc0, s_save_mem_offset) >+ >+ v_add_u32 v2, 0x200, v2 >+ v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size >+ s_cbranch_vccnz L_SAVE_LDS_LOOP_SQC >+ >+ s_branch L_SAVE_LDS_DONE >+ >+L_SAVE_LDS_WITH_TCP: >+end >+ > v_mul_i32_i24 v2, v3, 8 // tid*8 > v_mov_b32 v3, 256*2 > s_mov_b32 m0, 0x10000 >@@ -701,8 +552,6 @@ > // restore rsrc3 > s_mov_b32 s_save_buf_rsrc3, s0 > >-end >- > L_SAVE_LDS_DONE: > > >@@ -720,44 +569,9 @@ > s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 > s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible > s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) >- if (SWIZZLE_EN) >- s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end >- >- >- // VGPR Allocated in 4-GPR granularity > >-if G8SR_VGPR_SR_IN_DWX4 >- // the const stride for DWx4 is 4*4 bytes >- s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes >- >- s_mov_b32 m0, 4 // skip first 4 VGPRs >- s_cmp_lt_u32 m0, s_save_alloc_size >- s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs >- >- s_set_gpr_idx_on m0, 0x1 // This will change M0 >- s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 >-L_SAVE_VGPR_LOOP: >- v_mov_b32 v0, v0 // v0 = v[0+m0] >- v_mov_b32 v1, v1 >- v_mov_b32 v2, v2 >- v_mov_b32 v3, v3 >- >- >- buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >- s_add_u32 m0, m0, 4 >- s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 >- s_cmp_lt_u32 m0, s_save_alloc_size >- s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? >- s_set_gpr_idx_off >-L_SAVE_VGPR_LOOP_END: > >- s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes >-else > // VGPR store using dw burst > s_mov_b32 m0, 0x4 //VGPR initial index value =0 > s_cmp_lt_u32 m0, s_save_alloc_size >@@ -767,57 +581,82 @@ > s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 > s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later > >+if SAVE_AFTER_XNACK_ERROR >+ check_if_tcp_store_ok() >+ s_cbranch_scc1 L_SAVE_VGPR_LOOP >+ >+L_SAVE_VGPR_LOOP_SQC: >+ write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) >+ >+ s_add_u32 m0, m0, 4 >+ s_cmp_lt_u32 m0, s_save_alloc_size >+ s_cbranch_scc1 L_SAVE_VGPR_LOOP_SQC >+ >+ s_set_gpr_idx_off >+ s_branch L_SAVE_VGPR_END >+end >+ > L_SAVE_VGPR_LOOP: > v_mov_b32 v0, v0 //v0 = v[0+m0] > v_mov_b32 v1, v1 //v0 = v[0+m0] > v_mov_b32 v2, v2 //v0 = v[0+m0] > v_mov_b32 v3, v3 //v0 = v[0+m0] > >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else > buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 > buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 > buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 > buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 >- end > > s_add_u32 m0, m0, 4 //next vgpr index > s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes > s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 > s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? > s_set_gpr_idx_off >-end > > L_SAVE_VGPR_END: > >+if ASIC_TARGET_ARCTURUS >+ // Save ACC VGPRs >+ s_mov_b32 m0, 0x0 //VGPR initial index value =0 >+ s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 > >+if SAVE_AFTER_XNACK_ERROR >+ check_if_tcp_store_ok() >+ s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP > >+L_SAVE_ACCVGPR_LOOP_SQC: >+ for var vgpr = 0; vgpr < 4; ++ vgpr >+ v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] >+ end >+ >+ write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) > >+ s_add_u32 m0, m0, 4 >+ s_cmp_lt_u32 m0, s_save_alloc_size >+ s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP_SQC > >+ s_set_gpr_idx_off >+ s_branch L_SAVE_ACCVGPR_END >+end > >- /* S_PGM_END_SAVED */ //FIXME graphics ONLY >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) >- s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] >- s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 >- s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over >- s_rfe_b64 s_save_pc_lo //Return to the main shader program >- else >+L_SAVE_ACCVGPR_LOOP: >+ for var vgpr = 0; vgpr < 4; ++ vgpr >+ v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] > end > >-// Save Done timestamp >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_save_d >- // SGPR SR memory offset : size(VGPR) >- get_vgpr_size_bytes(s_save_mem_offset) >- s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET >- s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? >- // Need reset rsrc2?? >- s_mov_b32 m0, s_save_mem_offset >- s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 >-end >+ buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 >+ buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 >+ buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 >+ buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 >+ >+ s_add_u32 m0, m0, 4 >+ s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 >+ s_cmp_lt_u32 m0, s_save_alloc_size >+ s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP >+ s_set_gpr_idx_off > >+L_SAVE_ACCVGPR_END: >+end > > s_branch L_END_PGM > >@@ -829,27 +668,6 @@ > > L_RESTORE: > /* Setup Resource Contants */ >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) >- //calculate wd_addr using absolute thread id >- v_readlane_b32 s_restore_tmp, v9, 0 >- s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 >- s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE >- s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO >- s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI >- s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL >- else >- end >- >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_restore_s >- s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? >- // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... >- s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] >- s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. >-end >- >- >- > s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo > s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi > s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE >@@ -891,18 +709,12 @@ > s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? > > >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > s_mov_b32 m0, 0x0 //lds_offset initial value = 0 > > L_RESTORE_LDS_LOOP: >- if (SAVE_LDS) > buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW > buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW >- end > s_add_u32 m0, m0, 256*2 // 128 DW > s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW > s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 >@@ -921,56 +733,43 @@ > s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 > s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) > s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else >- s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > >-if G8SR_VGPR_SR_IN_DWX4 >- get_vgpr_size_bytes(s_restore_mem_offset) >- s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 >- >- // the const stride for DWx4 is 4*4 bytes >- s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes >- >- s_mov_b32 m0, s_restore_alloc_size >- s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 >- >-L_RESTORE_VGPR_LOOP: >- buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 >- s_waitcnt vmcnt(0) >- s_sub_u32 m0, m0, 4 >- v_mov_b32 v0, v0 // v[0+m0] = v0 >- v_mov_b32 v1, v1 >- v_mov_b32 v2, v2 >- v_mov_b32 v3, v3 >- s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 >- s_cmp_eq_u32 m0, 0x8000 >- s_cbranch_scc0 L_RESTORE_VGPR_LOOP >- s_set_gpr_idx_off >+if ASIC_TARGET_ARCTURUS >+ s_mov_b32 s_restore_accvgpr_offset, s_restore_buf_rsrc2 //ACC VGPRs at end of VGPRs >+end > >- s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 >- s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes >+ s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes > >-else > // VGPR load using dw burst > s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last > s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 >+if ASIC_TARGET_ARCTURUS >+ s_mov_b32 s_restore_accvgpr_offset_save, s_restore_accvgpr_offset >+ s_add_u32 s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4 >+end > s_mov_b32 m0, 4 //VGPR initial index value = 1 > s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 > s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later > > L_RESTORE_VGPR_LOOP: >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else >+ >+if ASIC_TARGET_ARCTURUS >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 >+ buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256 >+ buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*2 >+ buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*3 >+ s_add_u32 s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4 >+ s_waitcnt vmcnt(0) >+ >+ for var vgpr = 0; vgpr < 4; ++ vgpr >+ v_accvgpr_write acc[vgpr], v[vgpr] >+ end >+end >+ > buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 > buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 > buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 > buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 >- end > s_waitcnt vmcnt(0) //ensure data ready > v_mov_b32 v0, v0 //v[0+m0] = v0 > v_mov_b32 v1, v1 >@@ -982,16 +781,22 @@ > s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? > s_set_gpr_idx_off > /* VGPR restore on v0 */ >- if(USE_MTBUF_INSTEAD_OF_MUBUF) >- tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 >- else >+if ASIC_TARGET_ARCTURUS >+ buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 >+ buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256 >+ buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*2 >+ buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*3 >+ s_waitcnt vmcnt(0) >+ >+ for var vgpr = 0; vgpr < 4; ++ vgpr >+ v_accvgpr_write acc[vgpr], v[vgpr] >+ end >+end >+ > buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 > buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 > buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 > buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 >- end >- >-end > > /* restore SGPRs */ > ////////////////////////////// >@@ -1007,16 +812,8 @@ > s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 > s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) > >- if (SGPR_SAVE_USE_SQC) > s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes >- else >- s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) >- end >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > s_mov_b32 m0, s_restore_alloc_size > >@@ -1044,11 +841,6 @@ > L_RESTORE_HWREG: > > >-if G8SR_DEBUG_TIMESTAMP >- s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo >- s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi >-end >- > // HWREG SR memory offset : size(VGPR)+size(SGPR) > get_vgpr_size_bytes(s_restore_mem_offset) > get_sgpr_size_bytes(s_restore_tmp) >@@ -1056,11 +848,7 @@ > > > s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes >- if (SWIZZLE_EN) >- s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? >- else > s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes >- end > > read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 > read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC >@@ -1075,16 +863,6 @@ > > s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS > >- //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: >- if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) >- s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) >- s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over >- end >- if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) >- s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal >- s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over >- end >- > s_mov_b32 m0, s_restore_m0 > s_mov_b32 exec_lo, s_restore_exec_lo > s_mov_b32 exec_hi, s_restore_exec_hi >@@ -1131,11 +909,6 @@ > > s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time > >-if G8SR_DEBUG_TIMESTAMP >- s_memrealtime s_g8sr_ts_restore_d >- s_waitcnt lgkmcnt(0) >-end >- > // s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution > s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc > >@@ -1190,7 +963,39 @@ > s_sub_u32 s_mem_offset, s_mem_offset, 4*16 > end > >+function check_if_tcp_store_ok >+ // If STATUS.ALLOW_REPLAY=0 and TRAPSTS.XNACK_ERROR=1 then TCP stores will fail. >+ s_and_b32 s_save_tmp, s_save_status, SQ_WAVE_STATUS_ALLOW_REPLAY_MASK >+ s_cbranch_scc1 L_TCP_STORE_CHECK_DONE >+ >+ s_getreg_b32 s_save_tmp, hwreg(HW_REG_TRAPSTS) >+ s_andn2_b32 s_save_tmp, SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK, s_save_tmp >+ >+L_TCP_STORE_CHECK_DONE: >+end >+ >+function write_vgpr_to_mem_with_sqc(v, s_rsrc, s_mem_offset) >+ s_mov_b32 s4, 0 > >+L_WRITE_VGPR_LANE_LOOP: >+ for var lane = 0; lane < 4; ++ lane >+ v_readlane_b32 s[lane], v, s4 >+ s_add_u32 s4, s4, 1 >+ end >+ >+ s_buffer_store_dwordx4 s[0:3], s_rsrc, s_mem_offset glc:1 >+ ack_sqc_store_workaround() >+ >+ s_add_u32 s_mem_offset, s_mem_offset, 0x10 >+ s_cmp_eq_u32 s4, 0x40 >+ s_cbranch_scc0 L_WRITE_VGPR_LANE_LOOP >+end >+ >+function write_vgprs_to_mem_with_sqc(v, n_vgprs, s_rsrc, s_mem_offset) >+ for var vgpr = 0; vgpr < n_vgprs; ++ vgpr >+ write_vgpr_to_mem_with_sqc(v[vgpr], s_rsrc, s_mem_offset) >+ end >+end > > function get_lds_size_bytes(s_lds_size_byte) > // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW >@@ -1202,6 +1007,10 @@ > s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size > s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 > s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible >+ >+if ASIC_TARGET_ARCTURUS >+ s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, 1 // Double size for ACC VGPRs >+end > end > > function get_sgpr_size_bytes(s_sgpr_size_byte) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h 2019-08-31 15:01:11.852736168 -0500 >@@ -274,154 +274,227 @@ > > > static const uint32_t cwsr_trap_gfx9_hex[] = { >- 0xbf820001, 0xbf82015e, >+ 0xbf820001, 0xbf820248, > 0xb8f8f802, 0x89788678, >- 0xb8fbf803, 0x866eff7b, >- 0x00000400, 0xbf85003b, >- 0x866eff7b, 0x00000800, >- 0xbf850003, 0x866eff7b, >- 0x00000100, 0xbf84000c, >+ 0xb8eef801, 0x866eff6e, >+ 0x00000800, 0xbf840003, > 0x866eff78, 0x00002000, >- 0xbf840005, 0xbf8e0010, >- 0xb8eef803, 0x866eff6e, >- 0x00000400, 0xbf84fffb, >- 0x8778ff78, 0x00002000, >- 0x80ec886c, 0x82ed806d, >- 0xb8eef807, 0x866fff6e, >- 0x001f8000, 0x8e6f8b6f, >- 0x8977ff77, 0xfc000000, >- 0x87776f77, 0x896eff6e, >- 0x001f8000, 0xb96ef807, >- 0xb8faf812, 0xb8fbf813, >- 0x8efa887a, 0xc0071bbd, >- 0x00000000, 0xbf8cc07f, >- 0xc0071ebd, 0x00000008, >- 0xbf8cc07f, 0x86ee6e6e, >- 0xbf840001, 0xbe801d6e, >- 0xb8fbf803, 0x867bff7b, >- 0x000001ff, 0xbf850002, >- 0x806c846c, 0x826d806d, >+ 0xbf840016, 0xb8fbf803, >+ 0x866eff7b, 0x00000400, >+ 0xbf85003b, 0x866eff7b, >+ 0x00000800, 0xbf850003, >+ 0x866eff7b, 0x00000100, >+ 0xbf84000c, 0x866eff78, >+ 0x00002000, 0xbf840005, >+ 0xbf8e0010, 0xb8eef803, >+ 0x866eff6e, 0x00000400, >+ 0xbf84fffb, 0x8778ff78, >+ 0x00002000, 0x80ec886c, >+ 0x82ed806d, 0xb8eef807, >+ 0x866fff6e, 0x001f8000, >+ 0x8e6f8b6f, 0x8977ff77, >+ 0xfc000000, 0x87776f77, >+ 0x896eff6e, 0x001f8000, >+ 0xb96ef807, 0xb8faf812, >+ 0xb8fbf813, 0x8efa887a, >+ 0xc0071bbd, 0x00000000, >+ 0xbf8cc07f, 0xc0071ebd, >+ 0x00000008, 0xbf8cc07f, >+ 0x86ee6e6e, 0xbf840001, >+ 0xbe801d6e, 0xb8fbf803, >+ 0x867bff7b, 0x000001ff, >+ 0xbf850002, 0x806c846c, >+ 0x826d806d, 0x866dff6d, >+ 0x0000ffff, 0x8f6e8b77, >+ 0x866eff6e, 0x001f8000, >+ 0xb96ef807, 0x86fe7e7e, >+ 0x86ea6a6a, 0x8f6e8378, >+ 0xb96ee0c2, 0xbf800002, >+ 0xb9780002, 0xbe801f6c, > 0x866dff6d, 0x0000ffff, >- 0x8f6e8b77, 0x866eff6e, >- 0x001f8000, 0xb96ef807, >- 0x86fe7e7e, 0x86ea6a6a, >- 0x8f6e8378, 0xb96ee0c2, >- 0xbf800002, 0xb9780002, >- 0xbe801f6c, 0x866dff6d, >- 0x0000ffff, 0xbefa0080, >- 0xb97a0283, 0xb8fa2407, >- 0x8e7a9b7a, 0x876d7a6d, >- 0xb8fa03c7, 0x8e7a9a7a, >- 0x876d7a6d, 0xb8faf807, >- 0x867aff7a, 0x00007fff, >- 0xb97af807, 0xbeee007e, >- 0xbeef007f, 0xbefe0180, >- 0xbf900004, 0x877a8478, >- 0xb97af802, 0xbf8e0002, >- 0xbf88fffe, 0xb8fa2a05, >- 0x807a817a, 0x8e7a8a7a, >- 0xb8fb1605, 0x807b817b, >- 0x8e7b867b, 0x807a7b7a, >- 0x807a7e7a, 0x827b807f, >- 0x867bff7b, 0x0000ffff, >- 0xc04b1c3d, 0x00000050, >- 0xbf8cc07f, 0xc04b1d3d, >- 0x00000060, 0xbf8cc07f, >- 0xc0431e7d, 0x00000074, >- 0xbf8cc07f, 0xbef4007e, >- 0x8675ff7f, 0x0000ffff, >- 0x8775ff75, 0x00040000, >- 0xbef60080, 0xbef700ff, >- 0x00807fac, 0x867aff7f, >- 0x08000000, 0x8f7a837a, >- 0x87777a77, 0x867aff7f, >- 0x70000000, 0x8f7a817a, >- 0x87777a77, 0xbef1007c, >- 0xbef00080, 0xb8f02a05, >- 0x80708170, 0x8e708a70, >- 0xb8fa1605, 0x807a817a, >- 0x8e7a867a, 0x80707a70, >- 0xbef60084, 0xbef600ff, >- 0x01000000, 0xbefe007c, >- 0xbefc0070, 0xc0611c7a, >- 0x0000007c, 0xbf8cc07f, >- 0x80708470, 0xbefc007e, >+ 0xbefa0080, 0xb97a0283, >+ 0xb8fa2407, 0x8e7a9b7a, >+ 0x876d7a6d, 0xb8fa03c7, >+ 0x8e7a9a7a, 0x876d7a6d, >+ 0xb8faf807, 0x867aff7a, >+ 0x00007fff, 0xb97af807, >+ 0xbeee007e, 0xbeef007f, >+ 0xbefe0180, 0xbf900004, >+ 0x877a8478, 0xb97af802, >+ 0xbf8e0002, 0xbf88fffe, >+ 0xb8fa2a05, 0x807a817a, >+ 0x8e7a8a7a, 0xb8fb1605, >+ 0x807b817b, 0x8e7b867b, >+ 0x807a7b7a, 0x807a7e7a, >+ 0x827b807f, 0x867bff7b, >+ 0x0000ffff, 0xc04b1c3d, >+ 0x00000050, 0xbf8cc07f, >+ 0xc04b1d3d, 0x00000060, >+ 0xbf8cc07f, 0xc0431e7d, >+ 0x00000074, 0xbf8cc07f, >+ 0xbef4007e, 0x8675ff7f, >+ 0x0000ffff, 0x8775ff75, >+ 0x00040000, 0xbef60080, >+ 0xbef700ff, 0x00807fac, >+ 0x867aff7f, 0x08000000, >+ 0x8f7a837a, 0x87777a77, >+ 0x867aff7f, 0x70000000, >+ 0x8f7a817a, 0x87777a77, >+ 0xbef1007c, 0xbef00080, >+ 0xb8f02a05, 0x80708170, >+ 0x8e708a70, 0xb8fa1605, >+ 0x807a817a, 0x8e7a867a, >+ 0x80707a70, 0xbef60084, >+ 0xbef600ff, 0x01000000, > 0xbefe007c, 0xbefc0070, >- 0xc0611b3a, 0x0000007c, >+ 0xc0611c7a, 0x0000007c, > 0xbf8cc07f, 0x80708470, > 0xbefc007e, 0xbefe007c, >- 0xbefc0070, 0xc0611b7a, >+ 0xbefc0070, 0xc0611b3a, > 0x0000007c, 0xbf8cc07f, > 0x80708470, 0xbefc007e, > 0xbefe007c, 0xbefc0070, >- 0xc0611bba, 0x0000007c, >+ 0xc0611b7a, 0x0000007c, > 0xbf8cc07f, 0x80708470, > 0xbefc007e, 0xbefe007c, >- 0xbefc0070, 0xc0611bfa, >+ 0xbefc0070, 0xc0611bba, > 0x0000007c, 0xbf8cc07f, > 0x80708470, 0xbefc007e, > 0xbefe007c, 0xbefc0070, >- 0xc0611e3a, 0x0000007c, >- 0xbf8cc07f, 0x80708470, >- 0xbefc007e, 0xb8fbf803, >- 0xbefe007c, 0xbefc0070, >- 0xc0611efa, 0x0000007c, >+ 0xc0611bfa, 0x0000007c, > 0xbf8cc07f, 0x80708470, > 0xbefc007e, 0xbefe007c, >- 0xbefc0070, 0xc0611a3a, >+ 0xbefc0070, 0xc0611e3a, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0xb8fbf803, 0xbefe007c, >+ 0xbefc0070, 0xc0611efa, > 0x0000007c, 0xbf8cc07f, > 0x80708470, 0xbefc007e, > 0xbefe007c, 0xbefc0070, >- 0xc0611a7a, 0x0000007c, >- 0xbf8cc07f, 0x80708470, >- 0xbefc007e, 0xb8f1f801, >- 0xbefe007c, 0xbefc0070, >- 0xc0611c7a, 0x0000007c, >+ 0xc0611a3a, 0x0000007c, > 0xbf8cc07f, 0x80708470, >- 0xbefc007e, 0x867aff7f, >- 0x04000000, 0xbeef0080, >- 0x876f6f7a, 0xb8f02a05, >+ 0xbefc007e, 0xbefe007c, >+ 0xbefc0070, 0xc0611a7a, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0xb8f1f801, 0xbefe007c, >+ 0xbefc0070, 0xc0611c7a, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0x867aff7f, 0x04000000, >+ 0xbeef0080, 0x876f6f7a, >+ 0xb8f02a05, 0x80708170, >+ 0x8e708a70, 0xb8fb1605, >+ 0x807b817b, 0x8e7b847b, >+ 0x8e76827b, 0xbef600ff, >+ 0x01000000, 0xbef20174, >+ 0x80747074, 0x82758075, >+ 0xbefc0080, 0xbf800000, >+ 0xbe802b00, 0xbe822b02, >+ 0xbe842b04, 0xbe862b06, >+ 0xbe882b08, 0xbe8a2b0a, >+ 0xbe8c2b0c, 0xbe8e2b0e, >+ 0xc06b003a, 0x00000000, >+ 0xbf8cc07f, 0xc06b013a, >+ 0x00000010, 0xbf8cc07f, >+ 0xc06b023a, 0x00000020, >+ 0xbf8cc07f, 0xc06b033a, >+ 0x00000030, 0xbf8cc07f, >+ 0x8074c074, 0x82758075, >+ 0x807c907c, 0xbf0a7b7c, >+ 0xbf85ffe7, 0xbef40172, >+ 0xbef00080, 0xbefe00c1, >+ 0xbeff00c1, 0xbee80080, >+ 0xbee90080, 0xbef600ff, >+ 0x01000000, 0x867aff78, >+ 0x00400000, 0xbf850003, >+ 0xb8faf803, 0x897a7aff, >+ 0x10000000, 0xbf85004d, >+ 0xbe840080, 0xd2890000, >+ 0x00000900, 0x80048104, >+ 0xd2890001, 0x00000900, >+ 0x80048104, 0xd2890002, >+ 0x00000900, 0x80048104, >+ 0xd2890003, 0x00000900, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000901, >+ 0x80048104, 0xd2890001, >+ 0x00000901, 0x80048104, >+ 0xd2890002, 0x00000901, >+ 0x80048104, 0xd2890003, >+ 0x00000901, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0xbe840080, 0xd2890000, >+ 0x00000902, 0x80048104, >+ 0xd2890001, 0x00000902, >+ 0x80048104, 0xd2890002, >+ 0x00000902, 0x80048104, >+ 0xd2890003, 0x00000902, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000903, >+ 0x80048104, 0xd2890001, >+ 0x00000903, 0x80048104, >+ 0xd2890002, 0x00000903, >+ 0x80048104, 0xd2890003, >+ 0x00000903, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0xbf820008, 0xe0724000, >+ 0x701d0000, 0xe0724100, >+ 0x701d0100, 0xe0724200, >+ 0x701d0200, 0xe0724300, >+ 0x701d0300, 0xbefe00c1, >+ 0xbeff00c1, 0xb8fb4306, >+ 0x867bc17b, 0xbf840063, >+ 0xbf8a0000, 0x867aff6f, >+ 0x04000000, 0xbf84005f, >+ 0x8e7b867b, 0x8e7b827b, >+ 0xbef6007b, 0xb8f02a05, > 0x80708170, 0x8e708a70, >- 0xb8fb1605, 0x807b817b, >- 0x8e7b847b, 0x8e76827b, >- 0xbef600ff, 0x01000000, >- 0xbef20174, 0x80747074, >- 0x82758075, 0xbefc0080, >- 0xbf800000, 0xbe802b00, >- 0xbe822b02, 0xbe842b04, >- 0xbe862b06, 0xbe882b08, >- 0xbe8a2b0a, 0xbe8c2b0c, >- 0xbe8e2b0e, 0xc06b003a, >- 0x00000000, 0xbf8cc07f, >- 0xc06b013a, 0x00000010, >- 0xbf8cc07f, 0xc06b023a, >- 0x00000020, 0xbf8cc07f, >- 0xc06b033a, 0x00000030, >- 0xbf8cc07f, 0x8074c074, >- 0x82758075, 0x807c907c, >- 0xbf0a7b7c, 0xbf85ffe7, >- 0xbef40172, 0xbef00080, >- 0xbefe00c1, 0xbeff00c1, >- 0xbee80080, 0xbee90080, >+ 0xb8fa1605, 0x807a817a, >+ 0x8e7a867a, 0x80707a70, >+ 0x8070ff70, 0x00000080, > 0xbef600ff, 0x01000000, >- 0xe0724000, 0x701d0000, >- 0xe0724100, 0x701d0100, >- 0xe0724200, 0x701d0200, >- 0xe0724300, 0x701d0300, >- 0xbefe00c1, 0xbeff00c1, >- 0xb8fb4306, 0x867bc17b, >- 0xbf84002c, 0xbf8a0000, >- 0x867aff6f, 0x04000000, >- 0xbf840028, 0x8e7b867b, >- 0x8e7b827b, 0xbef6007b, >- 0xb8f02a05, 0x80708170, >- 0x8e708a70, 0xb8fa1605, >- 0x807a817a, 0x8e7a867a, >- 0x80707a70, 0x8070ff70, >- 0x00000080, 0xbef600ff, >- 0x01000000, 0xbefc0080, >- 0xd28c0002, 0x000100c1, >- 0xd28d0003, 0x000204c1, >+ 0xbefc0080, 0xd28c0002, >+ 0x000100c1, 0xd28d0003, >+ 0x000204c1, 0x867aff78, >+ 0x00400000, 0xbf850003, >+ 0xb8faf803, 0x897a7aff, >+ 0x10000000, 0xbf850030, >+ 0x24040682, 0xd86e4000, >+ 0x00000002, 0xbf8cc07f, >+ 0xbe840080, 0xd2890000, >+ 0x00000900, 0x80048104, >+ 0xd2890001, 0x00000900, >+ 0x80048104, 0xd2890002, >+ 0x00000900, 0x80048104, >+ 0xd2890003, 0x00000900, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000901, >+ 0x80048104, 0xd2890001, >+ 0x00000901, 0x80048104, >+ 0xd2890002, 0x00000901, >+ 0x80048104, 0xd2890003, >+ 0x00000901, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0x680404ff, 0x00000200, >+ 0xd0c9006a, 0x0000f702, >+ 0xbf87ffd2, 0xbf820015, > 0xd1060002, 0x00011103, > 0x7e0602ff, 0x00000200, > 0xbefc00ff, 0x00010000, >@@ -438,9 +511,53 @@ > 0x807b817b, 0x8e7b827b, > 0x8e76887b, 0xbef600ff, > 0x01000000, 0xbefc0084, >- 0xbf0a7b7c, 0xbf840015, >+ 0xbf0a7b7c, 0xbf84006d, > 0xbf11017c, 0x807bff7b, >- 0x00001000, 0x7e000300, >+ 0x00001000, 0x867aff78, >+ 0x00400000, 0xbf850003, >+ 0xb8faf803, 0x897a7aff, >+ 0x10000000, 0xbf850051, >+ 0xbe840080, 0xd2890000, >+ 0x00000900, 0x80048104, >+ 0xd2890001, 0x00000900, >+ 0x80048104, 0xd2890002, >+ 0x00000900, 0x80048104, >+ 0xd2890003, 0x00000900, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000901, >+ 0x80048104, 0xd2890001, >+ 0x00000901, 0x80048104, >+ 0xd2890002, 0x00000901, >+ 0x80048104, 0xd2890003, >+ 0x00000901, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0xbe840080, 0xd2890000, >+ 0x00000902, 0x80048104, >+ 0xd2890001, 0x00000902, >+ 0x80048104, 0xd2890002, >+ 0x00000902, 0x80048104, >+ 0xd2890003, 0x00000902, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000903, >+ 0x80048104, 0xd2890001, >+ 0x00000903, 0x80048104, >+ 0xd2890002, 0x00000903, >+ 0x80048104, 0xd2890003, >+ 0x00000903, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0x807c847c, 0xbf0a7b7c, >+ 0xbf85ffb1, 0xbf9c0000, >+ 0xbf820012, 0x7e000300, > 0x7e020301, 0x7e040302, > 0x7e060303, 0xe0724000, > 0x701d0000, 0xe0724100, >@@ -563,24 +680,47 @@ > }; > > static const uint32_t cwsr_trap_gfx10_hex[] = { >- 0xbf820001, 0xbf82012e, >- 0xb0804004, 0xb970f802, >- 0x8a708670, 0xb971f803, >- 0x8771ff71, 0x00000400, >- 0xbf850008, 0xb971f803, >- 0x8771ff71, 0x000001ff, >- 0xbf850001, 0x806c846c, >+ 0xbf820001, 0xbf8201c1, >+ 0xb0804004, 0xb978f802, >+ 0x8a788678, 0xb971f803, >+ 0x876eff71, 0x00000400, >+ 0xbf850033, 0x876eff71, >+ 0x00000100, 0xbf840002, >+ 0x8878ff78, 0x00002000, >+ 0x8a77ff77, 0xff000000, >+ 0xb96ef807, 0x876fff6e, >+ 0x02000000, 0x8f6f866f, >+ 0x88776f77, 0x876fff6e, >+ 0x003f8000, 0x8f6f896f, >+ 0x88776f77, 0x8a6eff6e, >+ 0x023f8000, 0xb9eef807, >+ 0xb970f812, 0xb971f813, >+ 0x8ff08870, 0xf4051bb8, >+ 0xfa000000, 0xbf8cc07f, >+ 0xf4051c38, 0xfa000008, >+ 0xbf8cc07f, 0x87ee6e6e, >+ 0xbf840001, 0xbe80206e, >+ 0xb971f803, 0x8771ff71, >+ 0x000001ff, 0xbf850002, >+ 0x806c846c, 0x826d806d, >+ 0x876dff6d, 0x0000ffff, >+ 0x906e8977, 0x876fff6e, >+ 0x003f8000, 0x906e8677, >+ 0x876eff6e, 0x02000000, >+ 0x886e6f6e, 0xb9eef807, >+ 0x87fe7e7e, 0x87ea6a6a, >+ 0xb9f8f802, 0xbe80226c, >+ 0xb971f803, 0x8771ff71, >+ 0x00000100, 0xbf840006, >+ 0xbef60380, 0xb9f60203, > 0x876dff6d, 0x0000ffff, >- 0xbe80226c, 0xb971f803, >- 0x8771ff71, 0x00000100, >- 0xbf840006, 0xbef60380, >- 0xb9f60203, 0x876dff6d, >- 0x0000ffff, 0x80ec886c, >- 0x82ed806d, 0xbef60380, >- 0xb9f60283, 0xb973f816, >- 0xb9762c07, 0x8f769c76, >- 0x886d766d, 0xb97603c7, >- 0x8f769b76, 0x886d766d, >+ 0x80ec886c, 0x82ed806d, >+ 0xbef60380, 0xb9f60283, >+ 0xb972f816, 0xb9762c07, >+ 0x8f769a76, 0x886d766d, >+ 0xb97603c7, 0x8f769976, >+ 0x886d766d, 0xb9760647, >+ 0x8f769876, 0x886d766d, > 0xb976f807, 0x8776ff76, > 0x00007fff, 0xb9f6f807, > 0xbeee037e, 0xbeef037f, >@@ -589,274 +729,833 @@ > 0xbef4037e, 0x8775ff7f, > 0x0000ffff, 0x8875ff75, > 0x00040000, 0xbef60380, >- 0xbef703ff, 0x00807fac, >+ 0xbef703ff, 0x10807fac, > 0x8776ff7f, 0x08000000, > 0x90768376, 0x88777677, > 0x8776ff7f, 0x70000000, > 0x90768176, 0x88777677, > 0xbefb037c, 0xbefa0380, >- 0xb97202dc, 0x8872727f, >- 0xbefe03c1, 0x877c8172, >- 0xbf06817c, 0xbf850002, >- 0xbeff0380, 0xbf820001, >- 0xbeff03c1, 0xb9712a05, >- 0x80718171, 0x8f718271, >- 0x877c8172, 0xbf06817c, >- 0xbf85000d, 0x8f768771, >+ 0xb97302dc, 0x8f739973, >+ 0x8873737f, 0xb97a2a05, >+ 0x807a817a, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbf850002, 0x8f7a897a, >+ 0xbf820001, 0x8f7a8a7a, >+ 0xb9761e06, 0x8f768a76, >+ 0x807a767a, 0x807aff7a, >+ 0x00000200, 0xbef603ff, >+ 0x01000000, 0xbefe037c, >+ 0xbefc037a, 0xf4611efa, >+ 0xf8000000, 0x807a847a, >+ 0xbefc037e, 0xbefe037c, >+ 0xbefc037a, 0xf4611b3a, >+ 0xf8000000, 0x807a847a, >+ 0xbefc037e, 0xbefe037c, >+ 0xbefc037a, 0xf4611b7a, >+ 0xf8000000, 0x807a847a, >+ 0xbefc037e, 0xbefe037c, >+ 0xbefc037a, 0xf4611bba, >+ 0xf8000000, 0x807a847a, >+ 0xbefc037e, 0xbefe037c, >+ 0xbefc037a, 0xf4611bfa, >+ 0xf8000000, 0x807a847a, >+ 0xbefc037e, 0xbefe037c, >+ 0xbefc037a, 0xf4611e3a, >+ 0xf8000000, 0x807a847a, >+ 0xbefc037e, 0xb971f803, >+ 0xbefe037c, 0xbefc037a, >+ 0xf4611c7a, 0xf8000000, >+ 0x807a847a, 0xbefc037e, >+ 0xbefe037c, 0xbefc037a, >+ 0xf4611cba, 0xf8000000, >+ 0x807a847a, 0xbefc037e, >+ 0xb97bf801, 0xbefe037c, >+ 0xbefc037a, 0xf4611efa, >+ 0xf8000000, 0x807a847a, >+ 0xbefc037e, 0xb97bf814, >+ 0xbefe037c, 0xbefc037a, >+ 0xf4611efa, 0xf8000000, >+ 0x807a847a, 0xbefc037e, >+ 0xb97bf815, 0xbefe037c, >+ 0xbefc037a, 0xf4611efa, >+ 0xf8000000, 0x807a847a, >+ 0xbefc037e, 0x8776ff7f, >+ 0x04000000, 0xbeef0380, >+ 0x886f6f76, 0xb97a2a05, >+ 0x807a817a, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbf850002, 0x8f7a897a, >+ 0xbf820001, 0x8f7a8a7a, >+ 0xb9761e06, 0x8f768a76, >+ 0x807a767a, 0xbef603ff, >+ 0x01000000, 0xbef20374, >+ 0x80747a74, 0x82758075, >+ 0xbefc0380, 0xbf800000, >+ 0xbe802f00, 0xbe822f02, >+ 0xbe842f04, 0xbe862f06, >+ 0xbe882f08, 0xbe8a2f0a, >+ 0xbe8c2f0c, 0xbe8e2f0e, >+ 0xf469003a, 0xfa000000, >+ 0xf469013a, 0xfa000010, >+ 0xf469023a, 0xfa000020, >+ 0xf469033a, 0xfa000030, >+ 0x8074c074, 0x82758075, >+ 0x807c907c, 0xbf0aff7c, >+ 0x00000060, 0xbf85ffea, >+ 0xbe802f00, 0xbe822f02, >+ 0xbe842f04, 0xbe862f06, >+ 0xbe882f08, 0xbe8a2f0a, >+ 0xf469003a, 0xfa000000, >+ 0xf469013a, 0xfa000010, >+ 0xf469023a, 0xfa000020, >+ 0x8074b074, 0x82758075, >+ 0xbef40372, 0xbefa0380, >+ 0xbefe03c1, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbf850002, 0xbeff0380, >+ 0xbf820002, 0xbeff03c1, >+ 0xbf82000b, 0xbef603ff, >+ 0x01000000, 0xe0704000, >+ 0x7a5d0000, 0xe0704080, >+ 0x7a5d0100, 0xe0704100, >+ 0x7a5d0200, 0xe0704180, >+ 0x7a5d0300, 0xbf82000a, > 0xbef603ff, 0x01000000, >- 0xbefc0380, 0x7e008700, > 0xe0704000, 0x7a5d0000, >- 0x807c817c, 0x807aff7a, >- 0x00000080, 0xbf0a717c, >- 0xbf85fff8, 0xbf82001b, >- 0x8f768871, 0xbef603ff, >- 0x01000000, 0xbefc0380, >- 0x7e008700, 0xe0704000, >- 0x7a5d0000, 0x807c817c, >- 0x807aff7a, 0x00000100, >- 0xbf0a717c, 0xbf85fff8, >- 0xb9711e06, 0x8771c171, >- 0xbf84000c, 0x8f718371, >- 0x80717c71, 0xbefe03c1, >- 0xbeff0380, 0x7e008700, >- 0xe0704000, 0x7a5d0000, >- 0x807c817c, 0x807aff7a, >- 0x00000080, 0xbf0a717c, >- 0xbf85fff8, 0xbf8a0000, >- 0x8776ff72, 0x04000000, >- 0xbf84002b, 0xbefe03c1, >- 0x877c8172, 0xbf06817c, >+ 0xe0704100, 0x7a5d0100, >+ 0xe0704200, 0x7a5d0200, >+ 0xe0704300, 0x7a5d0300, >+ 0xbefe03c1, 0x907c9973, >+ 0x877c817c, 0xbf06817c, > 0xbf850002, 0xbeff0380, > 0xbf820001, 0xbeff03c1, > 0xb9714306, 0x8771c171, >- 0xbf840021, 0x8f718671, >+ 0xbf840046, 0xbf8a0000, >+ 0x8776ff6f, 0x04000000, >+ 0xbf840042, 0x8f718671, > 0x8f718271, 0xbef60371, >+ 0xb97a2a05, 0x807a817a, >+ 0x907c9973, 0x877c817c, >+ 0xbf06817c, 0xbf850002, >+ 0x8f7a897a, 0xbf820001, >+ 0x8f7a8a7a, 0xb9761e06, >+ 0x8f768a76, 0x807a767a, >+ 0x807aff7a, 0x00000200, >+ 0x807aff7a, 0x00000080, > 0xbef603ff, 0x01000000, > 0xd7650000, 0x000100c1, > 0xd7660000, 0x000200c1, >- 0x16000084, 0x877c8172, >- 0xbf06817c, 0xbefc0380, >- 0xbf85000a, 0x807cff7c, >- 0x00000080, 0x807aff7a, >- 0x00000080, 0xd5250000, >- 0x0001ff00, 0x00000080, >- 0xbf0a717c, 0xbf85fff7, >- 0xbf820009, 0x807cff7c, >- 0x00000100, 0x807aff7a, >- 0x00000100, 0xd5250000, >- 0x0001ff00, 0x00000100, >- 0xbf0a717c, 0xbf85fff7, >- 0x877c8172, 0xbf06817c, >- 0xbf850003, 0x8f7687ff, >- 0x0000006a, 0xbf820002, >- 0x8f7688ff, 0x0000006a, >+ 0x16000084, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbefc0380, 0xbf850012, >+ 0xbe8303ff, 0x00000080, >+ 0xbf800000, 0xbf800000, >+ 0xbf800000, 0xd8d80000, >+ 0x01000000, 0xbf8c0000, >+ 0xe0704000, 0x7a5d0100, >+ 0x807c037c, 0x807a037a, >+ 0xd5250000, 0x0001ff00, >+ 0x00000080, 0xbf0a717c, >+ 0xbf85fff4, 0xbf820011, >+ 0xbe8303ff, 0x00000100, >+ 0xbf800000, 0xbf800000, >+ 0xbf800000, 0xd8d80000, >+ 0x01000000, 0xbf8c0000, >+ 0xe0704000, 0x7a5d0100, >+ 0x807c037c, 0x807a037a, >+ 0xd5250000, 0x0001ff00, >+ 0x00000100, 0xbf0a717c, >+ 0xbf85fff4, 0xbefe03c1, >+ 0x907c9973, 0x877c817c, >+ 0xbf06817c, 0xbf850004, >+ 0xbefa03ff, 0x00000200, >+ 0xbeff0380, 0xbf820003, >+ 0xbefa03ff, 0x00000400, >+ 0xbeff03c1, 0xb9712a05, >+ 0x80718171, 0x8f718271, >+ 0x907c9973, 0x877c817c, >+ 0xbf06817c, 0xbf850017, > 0xbef603ff, 0x01000000, >- 0x877c8172, 0xbf06817c, >- 0xbefc0380, 0xbf800000, >- 0xbf85000b, 0xbe802e00, >- 0x7e000200, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000080, 0x807c817c, >- 0xbf0aff7c, 0x0000006a, >- 0xbf85fff6, 0xbf82000a, >- 0xbe802e00, 0x7e000200, >- 0xe0704000, 0x7a5d0000, >- 0x807aff7a, 0x00000100, >- 0x807c817c, 0xbf0aff7c, >- 0x0000006a, 0xbf85fff6, >- 0xbef60384, 0xbef603ff, >- 0x01000000, 0x877c8172, >- 0xbf06817c, 0xbf850030, >- 0x7e00027b, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000080, 0x7e00026c, >- 0xe0704000, 0x7a5d0000, >- 0x807aff7a, 0x00000080, >- 0x7e00026d, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000080, 0x7e00026e, >- 0xe0704000, 0x7a5d0000, >- 0x807aff7a, 0x00000080, >- 0x7e00026f, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000080, 0x7e000270, >- 0xe0704000, 0x7a5d0000, >- 0x807aff7a, 0x00000080, >- 0xb971f803, 0x7e000271, >+ 0xbefc0384, 0xbf0a717c, >+ 0xbf840037, 0x7e008700, >+ 0x7e028701, 0x7e048702, >+ 0x7e068703, 0xe0704000, >+ 0x7a5d0000, 0xe0704080, >+ 0x7a5d0100, 0xe0704100, >+ 0x7a5d0200, 0xe0704180, >+ 0x7a5d0300, 0x807c847c, >+ 0x807aff7a, 0x00000200, >+ 0xbf0a717c, 0xbf85ffef, >+ 0xbf820025, 0xbef603ff, >+ 0x01000000, 0xbefc0384, >+ 0xbf0a717c, 0xbf840020, >+ 0x7e008700, 0x7e028701, >+ 0x7e048702, 0x7e068703, > 0xe0704000, 0x7a5d0000, >+ 0xe0704100, 0x7a5d0100, >+ 0xe0704200, 0x7a5d0200, >+ 0xe0704300, 0x7a5d0300, >+ 0x807c847c, 0x807aff7a, >+ 0x00000400, 0xbf0a717c, >+ 0xbf85ffef, 0xb9711e06, >+ 0x8771c171, 0xbf84000c, >+ 0x8f718371, 0x80717c71, >+ 0xbefe03c1, 0xbeff0380, >+ 0x7e008700, 0xe0704000, >+ 0x7a5d0000, 0x807c817c, > 0x807aff7a, 0x00000080, >- 0x7e000273, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000080, 0xb97bf801, >- 0x7e00027b, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000080, 0xbf82002f, >- 0x7e00027b, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000100, 0x7e00026c, >- 0xe0704000, 0x7a5d0000, >- 0x807aff7a, 0x00000100, >- 0x7e00026d, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000100, 0x7e00026e, >- 0xe0704000, 0x7a5d0000, >- 0x807aff7a, 0x00000100, >- 0x7e00026f, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000100, 0x7e000270, >- 0xe0704000, 0x7a5d0000, >- 0x807aff7a, 0x00000100, >- 0xb971f803, 0x7e000271, >- 0xe0704000, 0x7a5d0000, >- 0x807aff7a, 0x00000100, >- 0x7e000273, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000100, 0xb97bf801, >- 0x7e00027b, 0xe0704000, >- 0x7a5d0000, 0x807aff7a, >- 0x00000100, 0xbf820119, >- 0xbef4037e, 0x8775ff7f, >- 0x0000ffff, 0x8875ff75, >- 0x00040000, 0xbef60380, >- 0xbef703ff, 0x00807fac, >- 0x8772ff7f, 0x08000000, >- 0x90728372, 0x88777277, >- 0x8772ff7f, 0x70000000, >- 0x90728172, 0x88777277, >- 0xb97902dc, 0x8879797f, >- 0xbef80380, 0xbefe03c1, >- 0x877c8179, 0xbf06817c, >+ 0xbf0a717c, 0xbf85fff8, >+ 0xbf820141, 0xbef4037e, >+ 0x8775ff7f, 0x0000ffff, >+ 0x8875ff75, 0x00040000, >+ 0xbef60380, 0xbef703ff, >+ 0x10807fac, 0x8772ff7f, >+ 0x08000000, 0x90728372, >+ 0x88777277, 0x8772ff7f, >+ 0x70000000, 0x90728172, >+ 0x88777277, 0xb97302dc, >+ 0x8f739973, 0x8873737f, >+ 0x8772ff7f, 0x04000000, >+ 0xbf840036, 0xbefe03c1, >+ 0x907c9973, 0x877c817c, >+ 0xbf06817c, 0xbf850002, >+ 0xbeff0380, 0xbf820001, >+ 0xbeff03c1, 0xb96f4306, >+ 0x876fc16f, 0xbf84002b, >+ 0x8f6f866f, 0x8f6f826f, >+ 0xbef6036f, 0xb9782a05, >+ 0x80788178, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbf850002, 0x8f788978, >+ 0xbf820001, 0x8f788a78, >+ 0xb9721e06, 0x8f728a72, >+ 0x80787278, 0x8078ff78, >+ 0x00000200, 0x8078ff78, >+ 0x00000080, 0xbef603ff, >+ 0x01000000, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbefc0380, 0xbf850009, >+ 0xe0310000, 0x781d0000, >+ 0x807cff7c, 0x00000080, >+ 0x8078ff78, 0x00000080, >+ 0xbf0a6f7c, 0xbf85fff8, >+ 0xbf820008, 0xe0310000, >+ 0x781d0000, 0x807cff7c, >+ 0x00000100, 0x8078ff78, >+ 0x00000100, 0xbf0a6f7c, >+ 0xbf85fff8, 0xbef80380, >+ 0xbefe03c1, 0x907c9973, >+ 0x877c817c, 0xbf06817c, > 0xbf850002, 0xbeff0380, > 0xbf820001, 0xbeff03c1, > 0xb96f2a05, 0x806f816f, >- 0x8f6f826f, 0x877c8179, >- 0xbf06817c, 0xbf850013, >- 0x8f76876f, 0xbef603ff, >+ 0x8f6f826f, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbf850021, 0xbef603ff, > 0x01000000, 0xbef20378, >- 0x8078ff78, 0x00000080, >- 0xbefc0381, 0xe0304000, >- 0x785d0000, 0xbf8c3f70, >- 0x7e008500, 0x807c817c, >- 0x8078ff78, 0x00000080, >- 0xbf0a6f7c, 0xbf85fff7, >- 0xe0304000, 0x725d0000, >- 0xbf820023, 0x8f76886f, >+ 0x8078ff78, 0x00000200, >+ 0xbefc0384, 0xe0304000, >+ 0x785d0000, 0xe0304080, >+ 0x785d0100, 0xe0304100, >+ 0x785d0200, 0xe0304180, >+ 0x785d0300, 0xbf8c3f70, >+ 0x7e008500, 0x7e028501, >+ 0x7e048502, 0x7e068503, >+ 0x807c847c, 0x8078ff78, >+ 0x00000200, 0xbf0a6f7c, >+ 0xbf85ffee, 0xe0304000, >+ 0x725d0000, 0xe0304080, >+ 0x725d0100, 0xe0304100, >+ 0x725d0200, 0xe0304180, >+ 0x725d0300, 0xbf820031, > 0xbef603ff, 0x01000000, > 0xbef20378, 0x8078ff78, >- 0x00000100, 0xbefc0381, >+ 0x00000400, 0xbefc0384, > 0xe0304000, 0x785d0000, >+ 0xe0304100, 0x785d0100, >+ 0xe0304200, 0x785d0200, >+ 0xe0304300, 0x785d0300, > 0xbf8c3f70, 0x7e008500, >- 0x807c817c, 0x8078ff78, >- 0x00000100, 0xbf0a6f7c, >- 0xbf85fff7, 0xb96f1e06, >- 0x876fc16f, 0xbf84000e, >- 0x8f6f836f, 0x806f7c6f, >- 0xbefe03c1, 0xbeff0380, >- 0xe0304000, 0x785d0000, >- 0xbf8c3f70, 0x7e008500, >- 0x807c817c, 0x8078ff78, >- 0x00000080, 0xbf0a6f7c, >- 0xbf85fff7, 0xbeff03c1, >- 0xe0304000, 0x725d0000, >- 0x8772ff79, 0x04000000, >- 0xbf840020, 0xbefe03c1, >- 0x877c8179, 0xbf06817c, >- 0xbf850002, 0xbeff0380, >- 0xbf820001, 0xbeff03c1, >- 0xb96f4306, 0x876fc16f, >- 0xbf840016, 0x8f6f866f, >- 0x8f6f826f, 0xbef6036f, >- 0xbef603ff, 0x01000000, >- 0x877c8172, 0xbf06817c, >- 0xbefc0380, 0xbf850007, >- 0x807cff7c, 0x00000080, >- 0x8078ff78, 0x00000080, >- 0xbf0a6f7c, 0xbf85fffa, >- 0xbf820006, 0x807cff7c, >- 0x00000100, 0x8078ff78, >- 0x00000100, 0xbf0a6f7c, >- 0xbf85fffa, 0x877c8179, >- 0xbf06817c, 0xbf850003, >- 0x8f7687ff, 0x0000006a, >- 0xbf820002, 0x8f7688ff, >- 0x0000006a, 0xbef603ff, >- 0x01000000, 0x877c8179, >- 0xbf06817c, 0xbf850012, >- 0xf4211cba, 0xf0000000, >+ 0x7e028501, 0x7e048502, >+ 0x7e068503, 0x807c847c, >+ 0x8078ff78, 0x00000400, >+ 0xbf0a6f7c, 0xbf85ffee, >+ 0xb96f1e06, 0x876fc16f, >+ 0xbf84000e, 0x8f6f836f, >+ 0x806f7c6f, 0xbefe03c1, >+ 0xbeff0380, 0xe0304000, >+ 0x785d0000, 0xbf8c3f70, >+ 0x7e008500, 0x807c817c, > 0x8078ff78, 0x00000080, >- 0xbefc0381, 0xf421003a, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xbf8cc07f, >- 0xbe803000, 0xbf800000, >- 0x807c817c, 0xbf0aff7c, >- 0x0000006a, 0xbf85fff5, >- 0xbe800372, 0xbf820011, >- 0xf4211cba, 0xf0000000, >- 0x8078ff78, 0x00000100, >- 0xbefc0381, 0xf421003a, >- 0xf0000000, 0x8078ff78, >- 0x00000100, 0xbf8cc07f, >- 0xbe803000, 0xbf800000, >- 0x807c817c, 0xbf0aff7c, >- 0x0000006a, 0xbf85fff5, >- 0xbe800372, 0xbef60384, >- 0xbef603ff, 0x01000000, >- 0x877c8179, 0xbf06817c, >- 0xbf850025, 0xf4211bfa, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xf4211b3a, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xf4211b7a, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xf4211eba, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xf4211efa, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xf4211c3a, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xf4211c7a, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xf4211cfa, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xf4211e7a, >- 0xf0000000, 0x8078ff78, >- 0x00000080, 0xbf820024, >- 0xf4211bfa, 0xf0000000, >- 0x8078ff78, 0x00000100, >+ 0xbf0a6f7c, 0xbf85fff7, >+ 0xbeff03c1, 0xe0304000, >+ 0x725d0000, 0xe0304100, >+ 0x725d0100, 0xe0304200, >+ 0x725d0200, 0xe0304300, >+ 0x725d0300, 0xb9782a05, >+ 0x80788178, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbf850002, 0x8f788978, >+ 0xbf820001, 0x8f788a78, >+ 0xb9721e06, 0x8f728a72, >+ 0x80787278, 0x8078ff78, >+ 0x00000200, 0x80f8ff78, >+ 0x00000050, 0xbef603ff, >+ 0x01000000, 0xbefc03ff, >+ 0x0000006c, 0x80f89078, >+ 0xf429003a, 0xf0000000, >+ 0xbf8cc07f, 0x80fc847c, >+ 0xbf800000, 0xbe803100, >+ 0xbe823102, 0x80f8a078, >+ 0xf42d003a, 0xf0000000, >+ 0xbf8cc07f, 0x80fc887c, >+ 0xbf800000, 0xbe803100, >+ 0xbe823102, 0xbe843104, >+ 0xbe863106, 0x80f8c078, >+ 0xf431003a, 0xf0000000, >+ 0xbf8cc07f, 0x80fc907c, >+ 0xbf800000, 0xbe803100, >+ 0xbe823102, 0xbe843104, >+ 0xbe863106, 0xbe883108, >+ 0xbe8a310a, 0xbe8c310c, >+ 0xbe8e310e, 0xbf06807c, >+ 0xbf84fff0, 0xb9782a05, >+ 0x80788178, 0x907c9973, >+ 0x877c817c, 0xbf06817c, >+ 0xbf850002, 0x8f788978, >+ 0xbf820001, 0x8f788a78, >+ 0xb9721e06, 0x8f728a72, >+ 0x80787278, 0x8078ff78, >+ 0x00000200, 0xbef603ff, >+ 0x01000000, 0xf4211bfa, >+ 0xf0000000, 0x80788478, > 0xf4211b3a, 0xf0000000, >- 0x8078ff78, 0x00000100, >- 0xf4211b7a, 0xf0000000, >- 0x8078ff78, 0x00000100, >+ 0x80788478, 0xf4211b7a, >+ 0xf0000000, 0x80788478, > 0xf4211eba, 0xf0000000, >- 0x8078ff78, 0x00000100, >- 0xf4211efa, 0xf0000000, >- 0x8078ff78, 0x00000100, >+ 0x80788478, 0xf4211efa, >+ 0xf0000000, 0x80788478, > 0xf4211c3a, 0xf0000000, >- 0x8078ff78, 0x00000100, >- 0xf4211c7a, 0xf0000000, >- 0x8078ff78, 0x00000100, >- 0xf4211cfa, 0xf0000000, >- 0x8078ff78, 0x00000100, >+ 0x80788478, 0xf4211c7a, >+ 0xf0000000, 0x80788478, > 0xf4211e7a, 0xf0000000, >- 0x8078ff78, 0x00000100, >- 0xbf8cc07f, 0x876dff6d, >+ 0x80788478, 0xf4211cfa, >+ 0xf0000000, 0x80788478, >+ 0xf4211bba, 0xf0000000, >+ 0x80788478, 0xbf8cc07f, >+ 0xb9eef814, 0xf4211bba, >+ 0xf0000000, 0x80788478, >+ 0xbf8cc07f, 0xb9eef815, >+ 0xbef2036d, 0x876dff72, > 0x0000ffff, 0xbefc036f, > 0xbefe037a, 0xbeff037b, > 0x876f71ff, 0x000003ff, >- 0xb9ef4803, 0xb9f3f816, >+ 0xb9ef4803, 0xb9f9f816, > 0x876f71ff, 0xfffff800, > 0x906f8b6f, 0xb9efa2c3, >- 0xb9f9f801, 0x876fff6d, >- 0xf0000000, 0x906f9c6f, >- 0x8f6f906f, 0xbef20380, >- 0x88726f72, 0x876fff6d, >- 0x08000000, 0x906f9b6f, >- 0x8f6f8f6f, 0x88726f72, >- 0x876fff70, 0x00800000, >- 0x906f976f, 0xb9f2f807, >- 0xb9f0f802, 0xbf8a0000, >- 0xbe80226c, 0xbf810000, >+ 0xb9f3f801, 0x876fff72, >+ 0xfc000000, 0x906f9a6f, >+ 0x8f6f906f, 0xbef30380, >+ 0x88736f73, 0x876fff72, >+ 0x02000000, 0x906f996f, >+ 0x8f6f8f6f, 0x88736f73, >+ 0x876fff72, 0x01000000, >+ 0x906f986f, 0x8f6f996f, >+ 0x88736f73, 0x876fff70, >+ 0x00800000, 0x906f976f, >+ 0xb9f3f807, 0x87fe7e7e, >+ 0x87ea6a6a, 0xb9f0f802, >+ 0xbf8a0000, 0xbe80226c, >+ 0xbf810000, 0xbf9f0000, > 0xbf9f0000, 0xbf9f0000, > 0xbf9f0000, 0xbf9f0000, >- 0xbf9f0000, 0x00000000, >+}; >+static const uint32_t cwsr_trap_arcturus_hex[] = { >+ 0xbf820001, 0xbf8202c4, >+ 0xb8f8f802, 0x89788678, >+ 0xb8eef801, 0x866eff6e, >+ 0x00000800, 0xbf840003, >+ 0x866eff78, 0x00002000, >+ 0xbf840016, 0xb8fbf803, >+ 0x866eff7b, 0x00000400, >+ 0xbf85003b, 0x866eff7b, >+ 0x00000800, 0xbf850003, >+ 0x866eff7b, 0x00000100, >+ 0xbf84000c, 0x866eff78, >+ 0x00002000, 0xbf840005, >+ 0xbf8e0010, 0xb8eef803, >+ 0x866eff6e, 0x00000400, >+ 0xbf84fffb, 0x8778ff78, >+ 0x00002000, 0x80ec886c, >+ 0x82ed806d, 0xb8eef807, >+ 0x866fff6e, 0x001f8000, >+ 0x8e6f8b6f, 0x8977ff77, >+ 0xfc000000, 0x87776f77, >+ 0x896eff6e, 0x001f8000, >+ 0xb96ef807, 0xb8faf812, >+ 0xb8fbf813, 0x8efa887a, >+ 0xc0071bbd, 0x00000000, >+ 0xbf8cc07f, 0xc0071ebd, >+ 0x00000008, 0xbf8cc07f, >+ 0x86ee6e6e, 0xbf840001, >+ 0xbe801d6e, 0xb8fbf803, >+ 0x867bff7b, 0x000001ff, >+ 0xbf850002, 0x806c846c, >+ 0x826d806d, 0x866dff6d, >+ 0x0000ffff, 0x8f6e8b77, >+ 0x866eff6e, 0x001f8000, >+ 0xb96ef807, 0x86fe7e7e, >+ 0x86ea6a6a, 0x8f6e8378, >+ 0xb96ee0c2, 0xbf800002, >+ 0xb9780002, 0xbe801f6c, >+ 0x866dff6d, 0x0000ffff, >+ 0xbefa0080, 0xb97a0283, >+ 0xb8fa2407, 0x8e7a9b7a, >+ 0x876d7a6d, 0xb8fa03c7, >+ 0x8e7a9a7a, 0x876d7a6d, >+ 0xb8faf807, 0x867aff7a, >+ 0x00007fff, 0xb97af807, >+ 0xbeee007e, 0xbeef007f, >+ 0xbefe0180, 0xbf900004, >+ 0x877a8478, 0xb97af802, >+ 0xbf8e0002, 0xbf88fffe, >+ 0xb8fa2a05, 0x807a817a, >+ 0x8e7a8a7a, 0x8e7a817a, >+ 0xb8fb1605, 0x807b817b, >+ 0x8e7b867b, 0x807a7b7a, >+ 0x807a7e7a, 0x827b807f, >+ 0x867bff7b, 0x0000ffff, >+ 0xc04b1c3d, 0x00000050, >+ 0xbf8cc07f, 0xc04b1d3d, >+ 0x00000060, 0xbf8cc07f, >+ 0xc0431e7d, 0x00000074, >+ 0xbf8cc07f, 0xbef4007e, >+ 0x8675ff7f, 0x0000ffff, >+ 0x8775ff75, 0x00040000, >+ 0xbef60080, 0xbef700ff, >+ 0x00807fac, 0x867aff7f, >+ 0x08000000, 0x8f7a837a, >+ 0x87777a77, 0x867aff7f, >+ 0x70000000, 0x8f7a817a, >+ 0x87777a77, 0xbef1007c, >+ 0xbef00080, 0xb8f02a05, >+ 0x80708170, 0x8e708a70, >+ 0x8e708170, 0xb8fa1605, >+ 0x807a817a, 0x8e7a867a, >+ 0x80707a70, 0xbef60084, >+ 0xbef600ff, 0x01000000, >+ 0xbefe007c, 0xbefc0070, >+ 0xc0611c7a, 0x0000007c, >+ 0xbf8cc07f, 0x80708470, >+ 0xbefc007e, 0xbefe007c, >+ 0xbefc0070, 0xc0611b3a, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0xbefe007c, 0xbefc0070, >+ 0xc0611b7a, 0x0000007c, >+ 0xbf8cc07f, 0x80708470, >+ 0xbefc007e, 0xbefe007c, >+ 0xbefc0070, 0xc0611bba, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0xbefe007c, 0xbefc0070, >+ 0xc0611bfa, 0x0000007c, >+ 0xbf8cc07f, 0x80708470, >+ 0xbefc007e, 0xbefe007c, >+ 0xbefc0070, 0xc0611e3a, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0xb8fbf803, 0xbefe007c, >+ 0xbefc0070, 0xc0611efa, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0xbefe007c, 0xbefc0070, >+ 0xc0611a3a, 0x0000007c, >+ 0xbf8cc07f, 0x80708470, >+ 0xbefc007e, 0xbefe007c, >+ 0xbefc0070, 0xc0611a7a, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0xb8f1f801, 0xbefe007c, >+ 0xbefc0070, 0xc0611c7a, >+ 0x0000007c, 0xbf8cc07f, >+ 0x80708470, 0xbefc007e, >+ 0x867aff7f, 0x04000000, >+ 0xbeef0080, 0x876f6f7a, >+ 0xb8f02a05, 0x80708170, >+ 0x8e708a70, 0x8e708170, >+ 0xb8fb1605, 0x807b817b, >+ 0x8e7b847b, 0x8e76827b, >+ 0xbef600ff, 0x01000000, >+ 0xbef20174, 0x80747074, >+ 0x82758075, 0xbefc0080, >+ 0xbf800000, 0xbe802b00, >+ 0xbe822b02, 0xbe842b04, >+ 0xbe862b06, 0xbe882b08, >+ 0xbe8a2b0a, 0xbe8c2b0c, >+ 0xbe8e2b0e, 0xc06b003a, >+ 0x00000000, 0xbf8cc07f, >+ 0xc06b013a, 0x00000010, >+ 0xbf8cc07f, 0xc06b023a, >+ 0x00000020, 0xbf8cc07f, >+ 0xc06b033a, 0x00000030, >+ 0xbf8cc07f, 0x8074c074, >+ 0x82758075, 0x807c907c, >+ 0xbf0a7b7c, 0xbf85ffe7, >+ 0xbef40172, 0xbef00080, >+ 0xbefe00c1, 0xbeff00c1, >+ 0xbee80080, 0xbee90080, >+ 0xbef600ff, 0x01000000, >+ 0x867aff78, 0x00400000, >+ 0xbf850003, 0xb8faf803, >+ 0x897a7aff, 0x10000000, >+ 0xbf85004d, 0xbe840080, >+ 0xd2890000, 0x00000900, >+ 0x80048104, 0xd2890001, >+ 0x00000900, 0x80048104, >+ 0xd2890002, 0x00000900, >+ 0x80048104, 0xd2890003, >+ 0x00000900, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0xbe840080, 0xd2890000, >+ 0x00000901, 0x80048104, >+ 0xd2890001, 0x00000901, >+ 0x80048104, 0xd2890002, >+ 0x00000901, 0x80048104, >+ 0xd2890003, 0x00000901, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000902, >+ 0x80048104, 0xd2890001, >+ 0x00000902, 0x80048104, >+ 0xd2890002, 0x00000902, >+ 0x80048104, 0xd2890003, >+ 0x00000902, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0xbe840080, 0xd2890000, >+ 0x00000903, 0x80048104, >+ 0xd2890001, 0x00000903, >+ 0x80048104, 0xd2890002, >+ 0x00000903, 0x80048104, >+ 0xd2890003, 0x00000903, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbf820008, >+ 0xe0724000, 0x701d0000, >+ 0xe0724100, 0x701d0100, >+ 0xe0724200, 0x701d0200, >+ 0xe0724300, 0x701d0300, >+ 0xbefe00c1, 0xbeff00c1, >+ 0xb8fb4306, 0x867bc17b, >+ 0xbf840064, 0xbf8a0000, >+ 0x867aff6f, 0x04000000, >+ 0xbf840060, 0x8e7b867b, >+ 0x8e7b827b, 0xbef6007b, >+ 0xb8f02a05, 0x80708170, >+ 0x8e708a70, 0x8e708170, >+ 0xb8fa1605, 0x807a817a, >+ 0x8e7a867a, 0x80707a70, >+ 0x8070ff70, 0x00000080, >+ 0xbef600ff, 0x01000000, >+ 0xbefc0080, 0xd28c0002, >+ 0x000100c1, 0xd28d0003, >+ 0x000204c1, 0x867aff78, >+ 0x00400000, 0xbf850003, >+ 0xb8faf803, 0x897a7aff, >+ 0x10000000, 0xbf850030, >+ 0x24040682, 0xd86e4000, >+ 0x00000002, 0xbf8cc07f, >+ 0xbe840080, 0xd2890000, >+ 0x00000900, 0x80048104, >+ 0xd2890001, 0x00000900, >+ 0x80048104, 0xd2890002, >+ 0x00000900, 0x80048104, >+ 0xd2890003, 0x00000900, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000901, >+ 0x80048104, 0xd2890001, >+ 0x00000901, 0x80048104, >+ 0xd2890002, 0x00000901, >+ 0x80048104, 0xd2890003, >+ 0x00000901, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0x680404ff, 0x00000200, >+ 0xd0c9006a, 0x0000f702, >+ 0xbf87ffd2, 0xbf820015, >+ 0xd1060002, 0x00011103, >+ 0x7e0602ff, 0x00000200, >+ 0xbefc00ff, 0x00010000, >+ 0xbe800077, 0x8677ff77, >+ 0xff7fffff, 0x8777ff77, >+ 0x00058000, 0xd8ec0000, >+ 0x00000002, 0xbf8cc07f, >+ 0xe0765000, 0x701d0002, >+ 0x68040702, 0xd0c9006a, >+ 0x0000f702, 0xbf87fff7, >+ 0xbef70000, 0xbef000ff, >+ 0x00000400, 0xbefe00c1, >+ 0xbeff00c1, 0xb8fb2a05, >+ 0x807b817b, 0x8e7b827b, >+ 0x8e76887b, 0xbef600ff, >+ 0x01000000, 0xbefc0084, >+ 0xbf0a7b7c, 0xbf84006d, >+ 0xbf11017c, 0x807bff7b, >+ 0x00001000, 0x867aff78, >+ 0x00400000, 0xbf850003, >+ 0xb8faf803, 0x897a7aff, >+ 0x10000000, 0xbf850051, >+ 0xbe840080, 0xd2890000, >+ 0x00000900, 0x80048104, >+ 0xd2890001, 0x00000900, >+ 0x80048104, 0xd2890002, >+ 0x00000900, 0x80048104, >+ 0xd2890003, 0x00000900, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000901, >+ 0x80048104, 0xd2890001, >+ 0x00000901, 0x80048104, >+ 0xd2890002, 0x00000901, >+ 0x80048104, 0xd2890003, >+ 0x00000901, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0xbe840080, 0xd2890000, >+ 0x00000902, 0x80048104, >+ 0xd2890001, 0x00000902, >+ 0x80048104, 0xd2890002, >+ 0x00000902, 0x80048104, >+ 0xd2890003, 0x00000902, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000903, >+ 0x80048104, 0xd2890001, >+ 0x00000903, 0x80048104, >+ 0xd2890002, 0x00000903, >+ 0x80048104, 0xd2890003, >+ 0x00000903, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0x807c847c, 0xbf0a7b7c, >+ 0xbf85ffb1, 0xbf9c0000, >+ 0xbf820012, 0x7e000300, >+ 0x7e020301, 0x7e040302, >+ 0x7e060303, 0xe0724000, >+ 0x701d0000, 0xe0724100, >+ 0x701d0100, 0xe0724200, >+ 0x701d0200, 0xe0724300, >+ 0x701d0300, 0x807c847c, >+ 0x8070ff70, 0x00000400, >+ 0xbf0a7b7c, 0xbf85ffef, >+ 0xbf9c0000, 0xbefc0080, >+ 0xbf11017c, 0x867aff78, >+ 0x00400000, 0xbf850003, >+ 0xb8faf803, 0x897a7aff, >+ 0x10000000, 0xbf850059, >+ 0xd3d84000, 0x18000100, >+ 0xd3d84001, 0x18000101, >+ 0xd3d84002, 0x18000102, >+ 0xd3d84003, 0x18000103, >+ 0xbe840080, 0xd2890000, >+ 0x00000900, 0x80048104, >+ 0xd2890001, 0x00000900, >+ 0x80048104, 0xd2890002, >+ 0x00000900, 0x80048104, >+ 0xd2890003, 0x00000900, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000901, >+ 0x80048104, 0xd2890001, >+ 0x00000901, 0x80048104, >+ 0xd2890002, 0x00000901, >+ 0x80048104, 0xd2890003, >+ 0x00000901, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0xbe840080, 0xd2890000, >+ 0x00000902, 0x80048104, >+ 0xd2890001, 0x00000902, >+ 0x80048104, 0xd2890002, >+ 0x00000902, 0x80048104, >+ 0xd2890003, 0x00000902, >+ 0x80048104, 0xc069003a, >+ 0x00000070, 0xbf8cc07f, >+ 0x80709070, 0xbf06c004, >+ 0xbf84ffee, 0xbe840080, >+ 0xd2890000, 0x00000903, >+ 0x80048104, 0xd2890001, >+ 0x00000903, 0x80048104, >+ 0xd2890002, 0x00000903, >+ 0x80048104, 0xd2890003, >+ 0x00000903, 0x80048104, >+ 0xc069003a, 0x00000070, >+ 0xbf8cc07f, 0x80709070, >+ 0xbf06c004, 0xbf84ffee, >+ 0x807c847c, 0xbf0a7b7c, >+ 0xbf85ffa9, 0xbf9c0000, >+ 0xbf820016, 0xd3d84000, >+ 0x18000100, 0xd3d84001, >+ 0x18000101, 0xd3d84002, >+ 0x18000102, 0xd3d84003, >+ 0x18000103, 0xe0724000, >+ 0x701d0000, 0xe0724100, >+ 0x701d0100, 0xe0724200, >+ 0x701d0200, 0xe0724300, >+ 0x701d0300, 0x807c847c, >+ 0x8070ff70, 0x00000400, >+ 0xbf0a7b7c, 0xbf85ffeb, >+ 0xbf9c0000, 0xbf820106, >+ 0xbef4007e, 0x8675ff7f, >+ 0x0000ffff, 0x8775ff75, >+ 0x00040000, 0xbef60080, >+ 0xbef700ff, 0x00807fac, >+ 0x866eff7f, 0x08000000, >+ 0x8f6e836e, 0x87776e77, >+ 0x866eff7f, 0x70000000, >+ 0x8f6e816e, 0x87776e77, >+ 0x866eff7f, 0x04000000, >+ 0xbf84001f, 0xbefe00c1, >+ 0xbeff00c1, 0xb8ef4306, >+ 0x866fc16f, 0xbf84001a, >+ 0x8e6f866f, 0x8e6f826f, >+ 0xbef6006f, 0xb8f82a05, >+ 0x80788178, 0x8e788a78, >+ 0x8e788178, 0xb8ee1605, >+ 0x806e816e, 0x8e6e866e, >+ 0x80786e78, 0x8078ff78, >+ 0x00000080, 0xbef600ff, >+ 0x01000000, 0xbefc0080, >+ 0xe0510000, 0x781d0000, >+ 0xe0510100, 0x781d0000, >+ 0x807cff7c, 0x00000200, >+ 0x8078ff78, 0x00000200, >+ 0xbf0a6f7c, 0xbf85fff6, >+ 0xbef80080, 0xbefe00c1, >+ 0xbeff00c1, 0xb8ef2a05, >+ 0x806f816f, 0x8e6f826f, >+ 0x8e76886f, 0xbef90076, >+ 0xbef600ff, 0x01000000, >+ 0xbeee0078, 0x8078ff78, >+ 0x00000400, 0xbef30079, >+ 0x8079ff79, 0x00000400, >+ 0xbefc0084, 0xbf11087c, >+ 0x806fff6f, 0x00008000, >+ 0xe0524000, 0x791d0000, >+ 0xe0524100, 0x791d0100, >+ 0xe0524200, 0x791d0200, >+ 0xe0524300, 0x791d0300, >+ 0x8079ff79, 0x00000400, >+ 0xbf8c0f70, 0xd3d94000, >+ 0x18000100, 0xd3d94001, >+ 0x18000101, 0xd3d94002, >+ 0x18000102, 0xd3d94003, >+ 0x18000103, 0xe0524000, >+ 0x781d0000, 0xe0524100, >+ 0x781d0100, 0xe0524200, >+ 0x781d0200, 0xe0524300, >+ 0x781d0300, 0xbf8c0f70, >+ 0x7e000300, 0x7e020301, >+ 0x7e040302, 0x7e060303, >+ 0x807c847c, 0x8078ff78, >+ 0x00000400, 0xbf0a6f7c, >+ 0xbf85ffdb, 0xbf9c0000, >+ 0xe0524000, 0x731d0000, >+ 0xe0524100, 0x731d0100, >+ 0xe0524200, 0x731d0200, >+ 0xe0524300, 0x731d0300, >+ 0xbf8c0f70, 0xd3d94000, >+ 0x18000100, 0xd3d94001, >+ 0x18000101, 0xd3d94002, >+ 0x18000102, 0xd3d94003, >+ 0x18000103, 0xe0524000, >+ 0x6e1d0000, 0xe0524100, >+ 0x6e1d0100, 0xe0524200, >+ 0x6e1d0200, 0xe0524300, >+ 0x6e1d0300, 0xb8f82a05, >+ 0x80788178, 0x8e788a78, >+ 0x8e788178, 0xb8ee1605, >+ 0x806e816e, 0x8e6e866e, >+ 0x80786e78, 0x80f8c078, >+ 0xb8ef1605, 0x806f816f, >+ 0x8e6f846f, 0x8e76826f, >+ 0xbef600ff, 0x01000000, >+ 0xbefc006f, 0xc031003a, >+ 0x00000078, 0x80f8c078, >+ 0xbf8cc07f, 0x80fc907c, >+ 0xbf800000, 0xbe802d00, >+ 0xbe822d02, 0xbe842d04, >+ 0xbe862d06, 0xbe882d08, >+ 0xbe8a2d0a, 0xbe8c2d0c, >+ 0xbe8e2d0e, 0xbf06807c, >+ 0xbf84fff0, 0xb8f82a05, >+ 0x80788178, 0x8e788a78, >+ 0x8e788178, 0xb8ee1605, >+ 0x806e816e, 0x8e6e866e, >+ 0x80786e78, 0xbef60084, >+ 0xbef600ff, 0x01000000, >+ 0xc0211bfa, 0x00000078, >+ 0x80788478, 0xc0211b3a, >+ 0x00000078, 0x80788478, >+ 0xc0211b7a, 0x00000078, >+ 0x80788478, 0xc0211c3a, >+ 0x00000078, 0x80788478, >+ 0xc0211c7a, 0x00000078, >+ 0x80788478, 0xc0211eba, >+ 0x00000078, 0x80788478, >+ 0xc0211efa, 0x00000078, >+ 0x80788478, 0xc0211a3a, >+ 0x00000078, 0x80788478, >+ 0xc0211a7a, 0x00000078, >+ 0x80788478, 0xc0211cfa, >+ 0x00000078, 0x80788478, >+ 0xbf8cc07f, 0xbefc006f, >+ 0xbefe0070, 0xbeff0071, >+ 0x866f7bff, 0x000003ff, >+ 0xb96f4803, 0x866f7bff, >+ 0xfffff800, 0x8f6f8b6f, >+ 0xb96fa2c3, 0xb973f801, >+ 0xb8ee2a05, 0x806e816e, >+ 0x8e6e8a6e, 0x8e6e816e, >+ 0xb8ef1605, 0x806f816f, >+ 0x8e6f866f, 0x806e6f6e, >+ 0x806e746e, 0x826f8075, >+ 0x866fff6f, 0x0000ffff, >+ 0xc00b1c37, 0x00000050, >+ 0xc00b1d37, 0x00000060, >+ 0xc0031e77, 0x00000074, >+ 0xbf8cc07f, 0x866fff6d, >+ 0xf8000000, 0x8f6f9b6f, >+ 0x8e6f906f, 0xbeee0080, >+ 0x876e6f6e, 0x866fff6d, >+ 0x04000000, 0x8f6f9a6f, >+ 0x8e6f8f6f, 0x876e6f6e, >+ 0x866fff7a, 0x00800000, >+ 0x8f6f976f, 0xb96ef807, >+ 0x866dff6d, 0x0000ffff, >+ 0x86fe7e7e, 0x86ea6a6a, >+ 0x8f6e837a, 0xb96ee0c2, >+ 0xbf800002, 0xb97a0002, >+ 0xbf8a0000, 0x95806f6c, >+ 0xbf810000, 0x00000000, > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_crat.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_crat.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 2019-08-31 15:01:11.853736168 -0500 >@@ -662,6 +662,7 @@ > case CHIP_VEGA10: > case CHIP_VEGA12: > case CHIP_VEGA20: >+ case CHIP_ARCTURUS: > pcache_info = vega10_cache_info; > num_of_cache_types = ARRAY_SIZE(vega10_cache_info); > break; >@@ -788,7 +789,7 @@ > * is put in the code to ensure we don't overwrite. > */ > #define VCRAT_SIZE_FOR_CPU (2 * PAGE_SIZE) >-#define VCRAT_SIZE_FOR_GPU (3 * PAGE_SIZE) >+#define VCRAT_SIZE_FOR_GPU (4 * PAGE_SIZE) > > /* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node > * >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_device.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_device.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_device.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_device.c 2019-08-31 15:01:11.853736168 -0500 >@@ -42,6 +42,7 @@ > #ifdef KFD_SUPPORT_IOMMU_V2 > static const struct kfd_device_info kaveri_device_info = { > .asic_family = CHIP_KAVERI, >+ .asic_name = "kaveri", > .max_pasid_bits = 16, > /* max num of queues for KV.TODO should be a dynamic value */ > .max_no_of_hqd = 24, >@@ -60,6 +61,7 @@ > > static const struct kfd_device_info carrizo_device_info = { > .asic_family = CHIP_CARRIZO, >+ .asic_name = "carrizo", > .max_pasid_bits = 16, > /* max num of queues for CZ.TODO should be a dynamic value */ > .max_no_of_hqd = 24, >@@ -78,6 +80,7 @@ > > static const struct kfd_device_info raven_device_info = { > .asic_family = CHIP_RAVEN, >+ .asic_name = "raven", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 8, >@@ -96,6 +99,7 @@ > > static const struct kfd_device_info hawaii_device_info = { > .asic_family = CHIP_HAWAII, >+ .asic_name = "hawaii", > .max_pasid_bits = 16, > /* max num of queues for KV.TODO should be a dynamic value */ > .max_no_of_hqd = 24, >@@ -114,6 +118,7 @@ > > static const struct kfd_device_info tonga_device_info = { > .asic_family = CHIP_TONGA, >+ .asic_name = "tonga", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 4, >@@ -131,6 +136,7 @@ > > static const struct kfd_device_info fiji_device_info = { > .asic_family = CHIP_FIJI, >+ .asic_name = "fiji", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 4, >@@ -148,6 +154,7 @@ > > static const struct kfd_device_info fiji_vf_device_info = { > .asic_family = CHIP_FIJI, >+ .asic_name = "fiji", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 4, >@@ -166,6 +173,7 @@ > > static const struct kfd_device_info polaris10_device_info = { > .asic_family = CHIP_POLARIS10, >+ .asic_name = "polaris10", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 4, >@@ -183,6 +191,7 @@ > > static const struct kfd_device_info polaris10_vf_device_info = { > .asic_family = CHIP_POLARIS10, >+ .asic_name = "polaris10", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 4, >@@ -200,6 +209,7 @@ > > static const struct kfd_device_info polaris11_device_info = { > .asic_family = CHIP_POLARIS11, >+ .asic_name = "polaris11", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 4, >@@ -217,6 +227,7 @@ > > static const struct kfd_device_info polaris12_device_info = { > .asic_family = CHIP_POLARIS12, >+ .asic_name = "polaris12", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 4, >@@ -234,6 +245,7 @@ > > static const struct kfd_device_info vegam_device_info = { > .asic_family = CHIP_VEGAM, >+ .asic_name = "vegam", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 4, >@@ -251,6 +263,7 @@ > > static const struct kfd_device_info vega10_device_info = { > .asic_family = CHIP_VEGA10, >+ .asic_name = "vega10", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 8, >@@ -268,6 +281,7 @@ > > static const struct kfd_device_info vega10_vf_device_info = { > .asic_family = CHIP_VEGA10, >+ .asic_name = "vega10", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 8, >@@ -285,6 +299,7 @@ > > static const struct kfd_device_info vega12_device_info = { > .asic_family = CHIP_VEGA12, >+ .asic_name = "vega12", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 8, >@@ -302,6 +317,7 @@ > > static const struct kfd_device_info vega20_device_info = { > .asic_family = CHIP_VEGA20, >+ .asic_name = "vega20", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 8, >@@ -317,8 +333,27 @@ > .num_sdma_queues_per_engine = 8, > }; > >+static const struct kfd_device_info arcturus_device_info = { >+ .asic_family = CHIP_ARCTURUS, >+ .asic_name = "arcturus", >+ .max_pasid_bits = 16, >+ .max_no_of_hqd = 24, >+ .doorbell_size = 8, >+ .ih_ring_entry_size = 8 * sizeof(uint32_t), >+ .event_interrupt_class = &event_interrupt_class_v9, >+ .num_of_watch_points = 4, >+ .mqd_size_aligned = MQD_SIZE_ALIGNED, >+ .supports_cwsr = true, >+ .needs_iommu_device = false, >+ .needs_pci_atomics = false, >+ .num_sdma_engines = 2, >+ .num_xgmi_sdma_engines = 6, >+ .num_sdma_queues_per_engine = 8, >+}; >+ > static const struct kfd_device_info navi10_device_info = { > .asic_family = CHIP_NAVI10, >+ .asic_name = "navi10", > .max_pasid_bits = 16, > .max_no_of_hqd = 24, > .doorbell_size = 8, >@@ -452,7 +487,10 @@ > { 0x66a4, &vega20_device_info }, /* Vega20 */ > { 0x66a7, &vega20_device_info }, /* Vega20 */ > { 0x66af, &vega20_device_info }, /* Vega20 */ >- /* Navi10 */ >+ { 0x738C, &arcturus_device_info }, /* Arcturus */ >+ { 0x7388, &arcturus_device_info }, /* Arcturus */ >+ { 0x738E, &arcturus_device_info }, /* Arcturus */ >+ { 0x7390, &arcturus_device_info }, /* Arcturus vf */ > { 0x7310, &navi10_device_info }, /* Navi10 */ > { 0x7312, &navi10_device_info }, /* Navi10 */ > { 0x7318, &navi10_device_info }, /* Navi10 */ >@@ -536,6 +574,10 @@ > BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); > kfd->cwsr_isa = cwsr_trap_gfx8_hex; > kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); >+ } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { >+ BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); >+ kfd->cwsr_isa = cwsr_trap_arcturus_hex; >+ kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); > } else if (kfd->device_info->asic_family < CHIP_NAVI10) { > BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); > kfd->cwsr_isa = cwsr_trap_gfx9_hex; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 2019-08-31 15:01:11.853736168 -0500 >@@ -880,8 +880,8 @@ > } > > dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1; >- dqm->sdma_bitmap = (1ULL << get_num_sdma_queues(dqm)) - 1; >- dqm->xgmi_sdma_bitmap = (1ULL << get_num_xgmi_sdma_queues(dqm)) - 1; >+ dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); >+ dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); > > return 0; > } >@@ -1019,8 +1019,8 @@ > dqm->sdma_queue_count = 0; > dqm->xgmi_sdma_queue_count = 0; > dqm->active_runlist = false; >- dqm->sdma_bitmap = (1ULL << get_num_sdma_queues(dqm)) - 1; >- dqm->xgmi_sdma_bitmap = (1ULL << get_num_xgmi_sdma_queues(dqm)) - 1; >+ dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); >+ dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); > > INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); > >@@ -1786,6 +1786,7 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: > device_queue_manager_init_v9(&dqm->asic_ops); > break; > case CHIP_NAVI10: >@@ -1813,7 +1814,8 @@ > return NULL; > } > >-void deallocate_hiq_sdma_mqd(struct kfd_dev *dev, struct kfd_mem_obj *mqd) >+static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev, >+ struct kfd_mem_obj *mqd) > { > WARN(!mqd, "No hiq sdma mqd trunk to free"); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c 2019-08-31 15:01:11.853736168 -0500 >@@ -405,6 +405,7 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: > case CHIP_NAVI10: > kfd_init_apertures_v9(pdd, id); > break; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c 2019-08-31 15:01:11.853736168 -0500 >@@ -80,6 +80,7 @@ > source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || > source_id == SOC15_INTSRC_CP_BAD_OPCODE || > client_id == SOC15_IH_CLIENTID_VMC || >+ client_id == SOC15_IH_CLIENTID_VMC1 || > client_id == SOC15_IH_CLIENTID_UTCL2; > } > >@@ -104,6 +105,7 @@ > else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) > kfd_signal_hw_exception_event(pasid); > else if (client_id == SOC15_IH_CLIENTID_VMC || >+ client_id == SOC15_IH_CLIENTID_VMC1 || > client_id == SOC15_IH_CLIENTID_UTCL2) { > struct kfd_vm_fault_info info = {0}; > uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 2019-08-31 15:01:11.853736168 -0500 >@@ -330,6 +330,7 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: > kernel_queue_init_v9(&kq->ops_asic_specific); > break; > case CHIP_NAVI10: >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c 2019-08-31 15:01:11.853736168 -0500 >@@ -81,7 +81,8 @@ > packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; > packet->bitfields2.process_quantum = 1; > packet->bitfields2.pasid = qpd->pqm->process->pasid; >- packet->bitfields14.gds_size = qpd->gds_size; >+ packet->bitfields14.gds_size = qpd->gds_size & 0x3F; >+ packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF; > packet->bitfields14.num_gws = qpd->num_gws; > packet->bitfields14.num_oac = qpd->num_oac; > packet->bitfields14.sdma_enable = 1; >@@ -143,6 +144,34 @@ > return 0; > } > >+static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer, >+ struct scheduling_resources *res) >+{ >+ struct pm4_mes_set_resources *packet; >+ >+ packet = (struct pm4_mes_set_resources *)buffer; >+ memset(buffer, 0, sizeof(struct pm4_mes_set_resources)); >+ >+ packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES, >+ sizeof(struct pm4_mes_set_resources)); >+ >+ packet->bitfields2.queue_type = >+ queue_type__mes_set_resources__hsa_interface_queue_hiq; >+ packet->bitfields2.vmid_mask = res->vmid_mask; >+ packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100; >+ packet->bitfields7.oac_mask = res->oac_mask; >+ packet->bitfields8.gds_heap_base = res->gds_heap_base; >+ packet->bitfields8.gds_heap_size = res->gds_heap_size; >+ >+ packet->gws_mask_lo = lower_32_bits(res->gws_mask); >+ packet->gws_mask_hi = upper_32_bits(res->gws_mask); >+ >+ packet->queue_mask_lo = lower_32_bits(res->queue_mask); >+ packet->queue_mask_hi = upper_32_bits(res->queue_mask); >+ >+ return 0; >+} >+ > static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer, > struct queue *q, bool is_static) > { >@@ -161,6 +190,8 @@ > packet->bitfields2.engine_sel = > engine_sel__mes_map_queues__compute_vi; > packet->bitfields2.gws_control_queue = q->gws ? 1 : 0; >+ packet->bitfields2.extended_engine_sel = >+ extended_engine_sel__mes_map_queues__legacy_engine_sel; > packet->bitfields2.queue_type = > queue_type__mes_map_queues__normal_compute_vi; > >@@ -176,9 +207,15 @@ > break; > case KFD_QUEUE_TYPE_SDMA: > case KFD_QUEUE_TYPE_SDMA_XGMI: >- packet->bitfields2.engine_sel = q->properties.sdma_engine_id + >- engine_sel__mes_map_queues__sdma0_vi; > use_static = false; /* no static queues under SDMA */ >+ if (q->properties.sdma_engine_id < 2) >+ packet->bitfields2.engine_sel = q->properties.sdma_engine_id + >+ engine_sel__mes_map_queues__sdma0_vi; >+ else { >+ packet->bitfields2.extended_engine_sel = >+ extended_engine_sel__mes_map_queues__sdma0_to_7_sel; >+ packet->bitfields2.engine_sel = q->properties.sdma_engine_id; >+ } > break; > default: > WARN(1, "queue type %d", q->properties.type); >@@ -218,13 +255,23 @@ > switch (type) { > case KFD_QUEUE_TYPE_COMPUTE: > case KFD_QUEUE_TYPE_DIQ: >+ packet->bitfields2.extended_engine_sel = >+ extended_engine_sel__mes_unmap_queues__legacy_engine_sel; > packet->bitfields2.engine_sel = > engine_sel__mes_unmap_queues__compute; > break; > case KFD_QUEUE_TYPE_SDMA: > case KFD_QUEUE_TYPE_SDMA_XGMI: >- packet->bitfields2.engine_sel = >- engine_sel__mes_unmap_queues__sdma0 + sdma_engine; >+ if (sdma_engine < 2) { >+ packet->bitfields2.extended_engine_sel = >+ extended_engine_sel__mes_unmap_queues__legacy_engine_sel; >+ packet->bitfields2.engine_sel = >+ engine_sel__mes_unmap_queues__sdma0 + sdma_engine; >+ } else { >+ packet->bitfields2.extended_engine_sel = >+ extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel; >+ packet->bitfields2.engine_sel = sdma_engine; >+ } > break; > default: > WARN(1, "queue type %d", type); >@@ -326,7 +373,7 @@ > const struct packet_manager_funcs kfd_v9_pm_funcs = { > .map_process = pm_map_process_v9, > .runlist = pm_runlist_v9, >- .set_resources = pm_set_resources_vi, >+ .set_resources = pm_set_resources_v9, > .map_queues = pm_map_queues_v9, > .unmap_queues = pm_unmap_queues_v9, > .query_status = pm_query_status_v9, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c 2019-08-31 15:01:11.853736168 -0500 >@@ -98,8 +98,8 @@ > uint32_t *se_mask) > { > struct kfd_cu_info cu_info; >- uint32_t cu_per_sh[4] = {0}; >- int i, se, cu = 0; >+ uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0}; >+ int i, se, sh, cu = 0; > > amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info); > >@@ -107,8 +107,8 @@ > cu_mask_count = cu_info.cu_active_number; > > for (se = 0; se < cu_info.num_shader_engines; se++) >- for (i = 0; i < 4; i++) >- cu_per_sh[se] += hweight32(cu_info.cu_bitmap[se][i]); >+ for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) >+ cu_per_se[se] += hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]); > > /* Symmetrically map cu_mask to all SEs: > * cu_mask[0] bit0 -> se_mask[0] bit0; >@@ -128,6 +128,6 @@ > se = 0; > cu++; > } >- } while (cu >= cu_per_sh[se] && cu < 32); >+ } while (cu >= cu_per_se[se] && cu < 32); > } > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h 2019-08-31 15:01:11.853736168 -0500 >@@ -26,6 +26,8 @@ > > #include "kfd_priv.h" > >+#define KFD_MAX_NUM_SE 8 >+ > /** > * struct mqd_manager > * >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 2019-08-31 15:01:11.854736168 -0500 >@@ -46,7 +46,7 @@ > struct queue_properties *q) > { > struct v9_mqd *m; >- uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ >+ uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; > > if (q->cu_mask_count == 0) > return; >@@ -59,12 +59,20 @@ > m->compute_static_thread_mgmt_se1 = se_mask[1]; > m->compute_static_thread_mgmt_se2 = se_mask[2]; > m->compute_static_thread_mgmt_se3 = se_mask[3]; >+ m->compute_static_thread_mgmt_se4 = se_mask[4]; >+ m->compute_static_thread_mgmt_se5 = se_mask[5]; >+ m->compute_static_thread_mgmt_se6 = se_mask[6]; >+ m->compute_static_thread_mgmt_se7 = se_mask[7]; > >- pr_debug("update cu mask to %#x %#x %#x %#x\n", >+ pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", > m->compute_static_thread_mgmt_se0, > m->compute_static_thread_mgmt_se1, > m->compute_static_thread_mgmt_se2, >- m->compute_static_thread_mgmt_se3); >+ m->compute_static_thread_mgmt_se3, >+ m->compute_static_thread_mgmt_se4, >+ m->compute_static_thread_mgmt_se5, >+ m->compute_static_thread_mgmt_se6, >+ m->compute_static_thread_mgmt_se7); > } > > static void set_priority(struct v9_mqd *m, struct queue_properties *q) >@@ -125,6 +133,10 @@ > m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; > m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; > m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; >+ m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; >+ m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; >+ m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; >+ m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; > > m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | > 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c 2019-08-31 15:01:11.854736168 -0500 >@@ -239,6 +239,7 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: > pm->pmf = &kfd_v9_pm_funcs; > break; > case CHIP_NAVI10: >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h 2019-08-31 15:01:11.854736168 -0500 >@@ -83,10 +83,10 @@ > > union { > struct { >- uint32_t gds_heap_base:6; >- uint32_t reserved3:5; >- uint32_t gds_heap_size:6; >- uint32_t reserved4:15; >+ uint32_t gds_heap_base:10; >+ uint32_t reserved3:1; >+ uint32_t gds_heap_size:10; >+ uint32_t reserved4:11; > } bitfields8; > uint32_t ordinal8; > }; >@@ -179,7 +179,7 @@ > uint32_t num_gws:7; > uint32_t sdma_enable:1; > uint32_t num_oac:4; >- uint32_t reserved8:4; >+ uint32_t gds_size_hi:4; > uint32_t gds_size:6; > uint32_t num_queues:10; > } bitfields14; >@@ -260,6 +260,10 @@ > engine_sel__mes_map_queues__sdma1_vi = 3 > }; > >+enum mes_map_queues_extended_engine_sel_enum { >+ extended_engine_sel__mes_map_queues__legacy_engine_sel = 0, >+ extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1 >+}; > > struct pm4_mes_map_queues { > union { >@@ -269,7 +273,8 @@ > > union { > struct { >- uint32_t reserved1:4; >+ uint32_t reserved1:2; >+ enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2; > enum mes_map_queues_queue_sel_enum queue_sel:2; > uint32_t reserved5:6; > uint32_t gws_control_queue:1; >@@ -382,6 +387,11 @@ > engine_sel__mes_unmap_queues__sdmal = 3 > }; > >+enum mes_unmap_queues_extended_engine_sel_enum { >+ extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0, >+ extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1 >+}; >+ > struct pm4_mes_unmap_queues { > union { > union PM4_MES_TYPE_3_HEADER header; /* header */ >@@ -391,7 +401,7 @@ > union { > struct { > enum mes_unmap_queues_action_enum action:2; >- uint32_t reserved1:2; >+ enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2; > enum mes_unmap_queues_queue_sel_enum queue_sel:2; > uint32_t reserved2:20; > enum mes_unmap_queues_engine_sel_enum engine_sel:3; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_priv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_priv.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 2019-08-31 15:01:11.854736168 -0500 >@@ -195,6 +195,7 @@ > > struct kfd_device_info { > enum amd_asic_type asic_family; >+ const char *asic_name; > const struct kfd_event_interrupt_class *event_interrupt_class; > unsigned int max_pasid_bits; > unsigned int max_no_of_hqd; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_process.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_process.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_process.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_process.c 2019-08-31 15:01:11.854736168 -0500 >@@ -801,6 +801,8 @@ > return ret; > } > >+ amdgpu_vm_set_task_info(pdd->vm); >+ > ret = kfd_process_device_reserve_ib_mem(pdd); > if (ret) > goto err_reserve_ib_mem; >@@ -1042,7 +1044,6 @@ > { > struct delayed_work *dwork; > struct kfd_process *p; >- struct kfd_process_device *pdd; > int ret = 0; > > dwork = to_delayed_work(work); >@@ -1051,16 +1052,6 @@ > * lifetime of this thread, kfd_process p will be valid > */ > p = container_of(dwork, struct kfd_process, restore_work); >- >- /* Call restore_process_bos on the first KGD device. This function >- * takes care of restoring the whole process including other devices. >- * Restore can fail if enough memory is not available. If so, >- * reschedule again. >- */ >- pdd = list_first_entry(&p->per_device_data, >- struct kfd_process_device, >- per_device_list); >- > pr_debug("Started restoring pasid %d\n", p->pasid); > > /* Setting last_restore_timestamp before successful restoration. >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_topology.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_topology.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 2019-08-31 15:01:11.854736168 -0500 >@@ -406,8 +406,6 @@ > char *buffer) > { > struct kfd_topology_device *dev; >- char public_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE]; >- uint32_t i; > uint32_t log_max_watch_addr; > > /* Making sure that the buffer is an empty string */ >@@ -422,14 +420,8 @@ > if (strcmp(attr->name, "name") == 0) { > dev = container_of(attr, struct kfd_topology_device, > attr_name); >- for (i = 0; i < KFD_TOPOLOGY_PUBLIC_NAME_SIZE; i++) { >- public_name[i] = >- (char)dev->node_props.marketing_name[i]; >- if (dev->node_props.marketing_name[i] == 0) >- break; >- } >- public_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE-1] = 0x0; >- return sysfs_show_str_val(buffer, public_name); >+ >+ return sysfs_show_str_val(buffer, dev->node_props.name); > } > > dev = container_of(attr, struct kfd_topology_device, >@@ -1274,6 +1266,10 @@ > */ > > amdgpu_amdkfd_get_cu_info(dev->gpu->kgd, &cu_info); >+ >+ strncpy(dev->node_props.name, gpu->device_info->asic_name, >+ KFD_TOPOLOGY_PUBLIC_NAME_SIZE); >+ > dev->node_props.simd_arrays_per_engine = > cu_info.num_shader_arrays_per_engine; > >@@ -1321,6 +1317,7 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_RAVEN: >+ case CHIP_ARCTURUS: > case CHIP_NAVI10: > dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 << > HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) & >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_topology.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_topology.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_topology.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_topology.h 2019-08-31 15:01:11.854736168 -0500 >@@ -27,7 +27,7 @@ > #include <linux/list.h> > #include "kfd_crat.h" > >-#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128 >+#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32 > > #define HSA_CAP_HOT_PLUGGABLE 0x00000001 > #define HSA_CAP_ATS_PRESENT 0x00000002 >@@ -81,7 +81,7 @@ > int32_t drm_render_minor; > uint32_t num_sdma_engines; > uint32_t num_sdma_xgmi_engines; >- uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE]; >+ char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE]; > }; > > #define HSA_MEM_HEAP_TYPE_SYSTEM 0 >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 2019-08-31 15:01:12.261736204 -0500 >@@ -688,12 +688,15 @@ > */ > if (adev->flags & AMD_IS_APU && > adev->asic_type >= CHIP_CARRIZO && >- adev->asic_type < CHIP_RAVEN) >+ adev->asic_type <= CHIP_RAVEN) > init_data.flags.gpu_vm_support = true; > > if (amdgpu_dc_feature_mask & DC_FBC_MASK) > init_data.flags.fbc_support = true; > >+ if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) >+ init_data.flags.multi_mon_pp_mclk_switch = true; >+ > init_data.flags.power_down_display_on_boot = true; > > #ifdef CONFIG_DRM_AMD_DC_DCN2_0 >@@ -809,6 +812,9 @@ > case CHIP_VEGA12: > case CHIP_VEGA20: > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+ case CHIP_NAVI12: >+ case CHIP_RENOIR: > return 0; > case CHIP_RAVEN: > if (ASICREV_IS_PICASSO(adev->external_rev_id)) >@@ -2358,7 +2364,12 @@ > #if defined(CONFIG_DRM_AMD_DC_DCN1_0) > case CHIP_RAVEN: > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) >+ case CHIP_NAVI12: > case CHIP_NAVI10: >+ case CHIP_NAVI14: >+#endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ case CHIP_RENOIR: > #endif > if (dcn10_register_irq_handlers(dm->adev)) { > DRM_ERROR("DM: Failed to initialize IRQ\n"); >@@ -2428,8 +2439,7 @@ > { > int ret; > int s3_state; >- struct pci_dev *pdev = to_pci_dev(device); >- struct drm_device *drm_dev = pci_get_drvdata(pdev); >+ struct drm_device *drm_dev = dev_get_drvdata(device); > struct amdgpu_device *adev = drm_dev->dev_private; > > ret = kstrtoint(buf, 0, &s3_state); >@@ -2515,10 +2525,23 @@ > #endif > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > case CHIP_NAVI10: >+ case CHIP_NAVI12: > adev->mode_info.num_crtc = 6; > adev->mode_info.num_hpd = 6; > adev->mode_info.num_dig = 6; > break; >+ case CHIP_NAVI14: >+ adev->mode_info.num_crtc = 5; >+ adev->mode_info.num_hpd = 5; >+ adev->mode_info.num_dig = 5; >+ break; >+#endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ case CHIP_RENOIR: >+ adev->mode_info.num_crtc = 4; >+ adev->mode_info.num_hpd = 4; >+ adev->mode_info.num_dig = 4; >+ break; > #endif > default: > DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); >@@ -2665,7 +2688,7 @@ > const struct amdgpu_framebuffer *afb, > const enum surface_pixel_format format, > const enum dc_rotation_angle rotation, >- const union plane_size *plane_size, >+ const struct plane_size *plane_size, > const union dc_tiling_info *tiling_info, > const uint64_t info, > struct dc_plane_dcc_param *dcc, >@@ -2691,8 +2714,8 @@ > return -EINVAL; > > input.format = format; >- input.surface_size.width = plane_size->grph.surface_size.width; >- input.surface_size.height = plane_size->grph.surface_size.height; >+ input.surface_size.width = plane_size->surface_size.width; >+ input.surface_size.height = plane_size->surface_size.height; > input.swizzle_mode = tiling_info->gfx9.swizzle; > > if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) >@@ -2710,9 +2733,9 @@ > return -EINVAL; > > dcc->enable = 1; >- dcc->grph.meta_pitch = >+ dcc->meta_pitch = > AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; >- dcc->grph.independent_64b_blks = i64b; >+ dcc->independent_64b_blks = i64b; > > dcc_address = get_dcc_address(afb->address, info); > address->grph.meta_addr.low_part = lower_32_bits(dcc_address); >@@ -2728,7 +2751,7 @@ > const enum dc_rotation_angle rotation, > const uint64_t tiling_flags, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > struct dc_plane_dcc_param *dcc, > struct dc_plane_address *address) > { >@@ -2741,11 +2764,11 @@ > memset(address, 0, sizeof(*address)); > > if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { >- plane_size->grph.surface_size.x = 0; >- plane_size->grph.surface_size.y = 0; >- plane_size->grph.surface_size.width = fb->width; >- plane_size->grph.surface_size.height = fb->height; >- plane_size->grph.surface_pitch = >+ plane_size->surface_size.x = 0; >+ plane_size->surface_size.y = 0; >+ plane_size->surface_size.width = fb->width; >+ plane_size->surface_size.height = fb->height; >+ plane_size->surface_pitch = > fb->pitches[0] / fb->format->cpp[0]; > > address->type = PLN_ADDR_TYPE_GRAPHICS; >@@ -2754,20 +2777,20 @@ > } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { > uint64_t chroma_addr = afb->address + fb->offsets[1]; > >- plane_size->video.luma_size.x = 0; >- plane_size->video.luma_size.y = 0; >- plane_size->video.luma_size.width = fb->width; >- plane_size->video.luma_size.height = fb->height; >- plane_size->video.luma_pitch = >+ plane_size->surface_size.x = 0; >+ plane_size->surface_size.y = 0; >+ plane_size->surface_size.width = fb->width; >+ plane_size->surface_size.height = fb->height; >+ plane_size->surface_pitch = > fb->pitches[0] / fb->format->cpp[0]; > >- plane_size->video.chroma_size.x = 0; >- plane_size->video.chroma_size.y = 0; >+ plane_size->chroma_size.x = 0; >+ plane_size->chroma_size.y = 0; > /* TODO: set these based on surface format */ >- plane_size->video.chroma_size.width = fb->width / 2; >- plane_size->video.chroma_size.height = fb->height / 2; >+ plane_size->chroma_size.width = fb->width / 2; >+ plane_size->chroma_size.height = fb->height / 2; > >- plane_size->video.chroma_pitch = >+ plane_size->chroma_pitch = > fb->pitches[1] / fb->format->cpp[1]; > > address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; >@@ -2814,6 +2837,11 @@ > adev->asic_type == CHIP_VEGA20 || > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > adev->asic_type == CHIP_NAVI10 || >+ adev->asic_type == CHIP_NAVI14 || >+ adev->asic_type == CHIP_NAVI12 || >+#endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ adev->asic_type == CHIP_RENOIR || > #endif > adev->asic_type == CHIP_RAVEN) { > /* Fill GFX9 params */ >@@ -2995,6 +3023,8 @@ > plane_info->visible = true; > plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; > >+ plane_info->layer_index = 0; >+ > ret = fill_plane_color_attributes(plane_state, plane_info->format, > &plane_info->color_space); > if (ret) >@@ -3060,6 +3090,7 @@ > dc_plane_state->global_alpha = plane_info.global_alpha; > dc_plane_state->global_alpha_value = plane_info.global_alpha_value; > dc_plane_state->dcc = plane_info.dcc; >+ dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 > > /* > * Always set input transfer function, since plane state is refreshed >@@ -3503,6 +3534,10 @@ > bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; > int mode_refresh; > int preferred_refresh = 0; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ struct dsc_dec_dpcd_caps dsc_caps; >+ uint32_t link_bandwidth_kbps; >+#endif > > struct dc_sink *sink = NULL; > if (aconnector == NULL) { >@@ -3575,17 +3610,23 @@ > &mode, &aconnector->base, con_state, old_stream); > > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- /* stream->timing.flags.DSC = 0; */ >- /* */ >- /* if (aconnector->dc_link && */ >- /* aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */ >- /* aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */ >- /* if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */ >- /* &aconnector->dc_link->dpcd_caps.dsc_caps, */ >- /* dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */ >- /* &stream->timing, */ >- /* &stream->timing.dsc_cfg)) */ >- /* stream->timing.flags.DSC = 1; */ >+ stream->timing.flags.DSC = 0; >+ >+ if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { >+ dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, >+ aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw, >+ &dsc_caps); >+ link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, >+ dc_link_get_link_cap(aconnector->dc_link)); >+ >+ if (dsc_caps.is_dsc_supported) >+ if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, >+ &dsc_caps, >+ link_bandwidth_kbps, >+ &stream->timing, >+ &stream->timing.dsc_cfg)) >+ stream->timing.flags.DSC = 1; >+ } > #endif > > update_stream_scaling_settings(&mode, dm_state, stream); >@@ -3669,7 +3710,7 @@ > state->abm_level = cur->abm_level; > state->vrr_supported = cur->vrr_supported; > state->freesync_config = cur->freesync_config; >- state->crc_enabled = cur->crc_enabled; >+ state->crc_src = cur->crc_src; > state->cm_has_degamma = cur->cm_has_degamma; > state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; > >@@ -3739,6 +3780,7 @@ > .atomic_destroy_state = dm_crtc_destroy_state, > .set_crc_source = amdgpu_dm_crtc_set_crc_source, > .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, >+ .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, > .enable_vblank = dm_enable_vblank, > .disable_vblank = dm_disable_vblank, > }; >@@ -4458,7 +4500,7 @@ > } > > if (plane->type != DRM_PLANE_TYPE_CURSOR) >- domain = amdgpu_display_supported_domains(adev); >+ domain = amdgpu_display_supported_domains(adev, rbo->flags); > else > domain = AMDGPU_GEM_DOMAIN_VRAM; > >@@ -4548,20 +4590,10 @@ > static int dm_plane_atomic_async_check(struct drm_plane *plane, > struct drm_plane_state *new_plane_state) > { >- struct drm_plane_state *old_plane_state = >- drm_atomic_get_old_plane_state(new_plane_state->state, plane); >- > /* Only support async updates on cursor planes. */ > if (plane->type != DRM_PLANE_TYPE_CURSOR) > return -EINVAL; > >- /* >- * DRM calls prepare_fb and cleanup_fb on new_plane_state for >- * async commits so don't allow fb changes. >- */ >- if (old_plane_state->fb != new_plane_state->fb) >- return -EINVAL; >- > return 0; > } > >@@ -5705,11 +5737,11 @@ > * deadlock during GPU reset when this fence will not signal > * but we hold reservation lock for the BO. > */ >- r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true, >+ r = reservation_object_wait_timeout_rcu(abo->tbo.base.resv, true, > false, > msecs_to_jiffies(5000)); > if (unlikely(r <= 0)) >- DRM_ERROR("Waiting for fences timed out or interrupted!"); >+ DRM_ERROR("Waiting for fences timed out!"); > > /* > * TODO This might fail and hence better not used, wait >@@ -5733,8 +5765,14 @@ > bundle->surface_updates[planes_count].plane_info = > &bundle->plane_infos[planes_count]; > >+ /* >+ * Only allow immediate flips for fast updates that don't >+ * change FB pitch, DCC state, rotation or mirroing. >+ */ > bundle->flip_addrs[planes_count].flip_immediate = >- (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; >+ (crtc->state->pageflip_flags & >+ DRM_MODE_PAGE_FLIP_ASYNC) != 0 && >+ acrtc_state->update_type == UPDATE_TYPE_FAST; > > timestamp_ns = ktime_get_ns(); > bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); >@@ -5979,6 +6017,7 @@ > struct drm_crtc *crtc; > struct drm_crtc_state *old_crtc_state, *new_crtc_state; > int i; >+ enum amdgpu_dm_pipe_crc_source source; > > for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, > new_crtc_state, i) { >@@ -6004,9 +6043,11 @@ > > #ifdef CONFIG_DEBUG_FS > /* The stream has changed so CRC capture needs to re-enabled. */ >- if (dm_new_crtc_state->crc_enabled) { >- dm_new_crtc_state->crc_enabled = false; >- amdgpu_dm_crtc_set_crc_source(crtc, "auto"); >+ source = dm_new_crtc_state->crc_src; >+ if (amdgpu_dm_is_valid_crc_source(source)) { >+ amdgpu_dm_crtc_configure_crc_source( >+ crtc, dm_new_crtc_state, >+ dm_new_crtc_state->crc_src); > } > #endif > } >@@ -6057,23 +6098,8 @@ > > if (dm_old_crtc_state->interrupts_enabled && > (!dm_new_crtc_state->interrupts_enabled || >- drm_atomic_crtc_needs_modeset(new_crtc_state))) { >- /* >- * Drop the extra vblank reference added by CRC >- * capture if applicable. >- */ >- if (dm_new_crtc_state->crc_enabled) >- drm_crtc_vblank_put(crtc); >- >- /* >- * Only keep CRC capture enabled if there's >- * still a stream for the CRTC. >- */ >- if (!dm_new_crtc_state->stream) >- dm_new_crtc_state->crc_enabled = false; >- >+ drm_atomic_crtc_needs_modeset(new_crtc_state))) > manage_dm_interrupts(adev, acrtc, false); >- } > } > /* > * Add check here for SoC's that support hardware cursor plane, to >@@ -7045,6 +7071,12 @@ > continue; > > for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { >+ const struct amdgpu_framebuffer *amdgpu_fb = >+ to_amdgpu_framebuffer(new_plane_state->fb); >+ struct dc_plane_info plane_info; >+ struct dc_flip_addrs flip_addr; >+ uint64_t tiling_flags; >+ > new_plane_crtc = new_plane_state->crtc; > old_plane_crtc = old_plane_state->crtc; > new_dm_plane_state = to_dm_plane_state(new_plane_state); >@@ -7088,6 +7120,24 @@ > > updates[num_plane].scaling_info = &scaling_info; > >+ if (amdgpu_fb) { >+ ret = get_fb_info(amdgpu_fb, &tiling_flags); >+ if (ret) >+ goto cleanup; >+ >+ memset(&flip_addr, 0, sizeof(flip_addr)); >+ >+ ret = fill_dc_plane_info_and_addr( >+ dm->adev, new_plane_state, tiling_flags, >+ &plane_info, >+ &flip_addr.address); >+ if (ret) >+ goto cleanup; >+ >+ updates[num_plane].plane_info = &plane_info; >+ updates[num_plane].flip_addr = &flip_addr; >+ } >+ > num_plane++; > } > >@@ -7284,6 +7334,26 @@ > if (ret) > goto fail; > >+ if (state->legacy_cursor_update) { >+ /* >+ * This is a fast cursor update coming from the plane update >+ * helper, check if it can be done asynchronously for better >+ * performance. >+ */ >+ state->async_update = >+ !drm_atomic_helper_async_check(dev, state); >+ >+ /* >+ * Skip the remaining global validation if this is an async >+ * update. Cursor updates can be done without affecting >+ * state or bandwidth calcs and this avoids the performance >+ * penalty of locking the private state object and >+ * allocating a new dc_state. >+ */ >+ if (state->async_update) >+ return 0; >+ } >+ > /* Check scaling and underscan changes*/ > /* TODO Removed scaling changes validation due to inability to commit > * new stream into context w\o causing full reset. Need to >@@ -7336,13 +7406,37 @@ > ret = -EINVAL; > goto fail; > } >- } else if (state->legacy_cursor_update) { >+ } else { > /* >- * This is a fast cursor update coming from the plane update >- * helper, check if it can be done asynchronously for better >- * performance. >+ * The commit is a fast update. Fast updates shouldn't change >+ * the DC context, affect global validation, and can have their >+ * commit work done in parallel with other commits not touching >+ * the same resource. If we have a new DC context as part of >+ * the DM atomic state from validation we need to free it and >+ * retain the existing one instead. > */ >- state->async_update = !drm_atomic_helper_async_check(dev, state); >+ struct dm_atomic_state *new_dm_state, *old_dm_state; >+ >+ new_dm_state = dm_atomic_get_new_state(state); >+ old_dm_state = dm_atomic_get_old_state(state); >+ >+ if (new_dm_state && old_dm_state) { >+ if (new_dm_state->context) >+ dc_release_state(new_dm_state->context); >+ >+ new_dm_state->context = old_dm_state->context; >+ >+ if (old_dm_state->context) >+ dc_retain_state(old_dm_state->context); >+ } >+ } >+ >+ /* Store the overall update type for use later in atomic check. */ >+ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { >+ struct dm_crtc_state *dm_new_crtc_state = >+ to_dm_crtc_state(new_crtc_state); >+ >+ dm_new_crtc_state->update_type = (int)overall_update_type; > } > > /* Must be success */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c 2019-08-31 15:01:11.854736168 -0500 >@@ -30,23 +30,57 @@ > #include "amdgpu_dm.h" > #include "dc.h" > >-enum amdgpu_dm_pipe_crc_source { >- AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0, >- AMDGPU_DM_PIPE_CRC_SOURCE_AUTO, >- AMDGPU_DM_PIPE_CRC_SOURCE_MAX, >- AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1, >+static const char *const pipe_crc_sources[] = { >+ "none", >+ "crtc", >+ "crtc dither", >+ "dprx", >+ "dprx dither", >+ "auto", > }; > > static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) > { > if (!source || !strcmp(source, "none")) > return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; >- if (!strcmp(source, "auto")) >- return AMDGPU_DM_PIPE_CRC_SOURCE_AUTO; >+ if (!strcmp(source, "auto") || !strcmp(source, "crtc")) >+ return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; >+ if (!strcmp(source, "dprx")) >+ return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; >+ if (!strcmp(source, "crtc dither")) >+ return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; >+ if (!strcmp(source, "dprx dither")) >+ return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; > > return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; > } > >+static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) >+{ >+ return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || >+ (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); >+} >+ >+static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) >+{ >+ return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || >+ (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); >+} >+ >+static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) >+{ >+ return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || >+ (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || >+ (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); >+} >+ >+const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, >+ size_t *count) >+{ >+ *count = ARRAY_SIZE(pipe_crc_sources); >+ return pipe_crc_sources; >+} >+ > int > amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, > size_t *values_cnt) >@@ -63,14 +97,52 @@ > return 0; > } > >-int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) >+int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, >+ struct dm_crtc_state *dm_crtc_state, >+ enum amdgpu_dm_pipe_crc_source source) > { > struct amdgpu_device *adev = crtc->dev->dev_private; >- struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state); >- struct dc_stream_state *stream_state = crtc_state->stream; >- bool enable; >+ struct dc_stream_state *stream_state = dm_crtc_state->stream; >+ bool enable = amdgpu_dm_is_valid_crc_source(source); >+ int ret = 0; >+ >+ /* Configuration will be deferred to stream enable. */ >+ if (!stream_state) >+ return 0; >+ >+ mutex_lock(&adev->dm.dc_lock); >+ >+ /* Enable CRTC CRC generation if necessary. */ >+ if (dm_is_crc_source_crtc(source)) { >+ if (!dc_stream_configure_crc(stream_state->ctx->dc, >+ stream_state, enable, enable)) { >+ ret = -EINVAL; >+ goto unlock; >+ } >+ } >+ >+ /* Configure dithering */ >+ if (!dm_need_crc_dither(source)) >+ dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); >+ else >+ dc_stream_set_dither_option(stream_state, >+ DITHER_OPTION_DEFAULT); > >+unlock: >+ mutex_unlock(&adev->dm.dc_lock); >+ >+ return ret; >+} >+ >+int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) >+{ > enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); >+ struct drm_crtc_commit *commit; >+ struct dm_crtc_state *crtc_state; >+ struct drm_dp_aux *aux = NULL; >+ bool enable = false; >+ bool enabled = false; >+ int ret = 0; > > if (source < 0) { > DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", >@@ -78,41 +150,124 @@ > return -EINVAL; > } > >- if (!stream_state) { >- DRM_ERROR("No stream state for CRTC%d\n", crtc->index); >- return -EINVAL; >+ ret = drm_modeset_lock(&crtc->mutex, NULL); >+ if (ret) >+ return ret; >+ >+ spin_lock(&crtc->commit_lock); >+ commit = list_first_entry_or_null(&crtc->commit_list, >+ struct drm_crtc_commit, commit_entry); >+ if (commit) >+ drm_crtc_commit_get(commit); >+ spin_unlock(&crtc->commit_lock); >+ >+ if (commit) { >+ /* >+ * Need to wait for all outstanding programming to complete >+ * in commit tail since it can modify CRC related fields and >+ * hardware state. Since we're holding the CRTC lock we're >+ * guaranteed that no other commit work can be queued off >+ * before we modify the state below. >+ */ >+ ret = wait_for_completion_interruptible_timeout( >+ &commit->hw_done, 10 * HZ); >+ if (ret) >+ goto cleanup; > } > >- enable = (source == AMDGPU_DM_PIPE_CRC_SOURCE_AUTO); >+ enable = amdgpu_dm_is_valid_crc_source(source); >+ crtc_state = to_dm_crtc_state(crtc->state); > >- mutex_lock(&adev->dm.dc_lock); >- if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state, >- enable, enable)) { >- mutex_unlock(&adev->dm.dc_lock); >- return -EINVAL; >+ /* >+ * USER REQ SRC | CURRENT SRC | BEHAVIOR >+ * ----------------------------- >+ * None | None | Do nothing >+ * None | CRTC | Disable CRTC CRC, set default to dither >+ * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither >+ * None | CRTC DITHER | Disable CRTC CRC >+ * None | DPRX DITHER | Disable DPRX CRC, need 'aux' >+ * CRTC | XXXX | Enable CRTC CRC, no dither >+ * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither >+ * CRTC DITHER | XXXX | Enable CRTC CRC, set dither >+ * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither >+ */ >+ if (dm_is_crc_source_dprx(source) || >+ (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && >+ dm_is_crc_source_dprx(crtc_state->crc_src))) { >+ struct amdgpu_dm_connector *aconn = NULL; >+ struct drm_connector *connector; >+ struct drm_connector_list_iter conn_iter; >+ >+ drm_connector_list_iter_begin(crtc->dev, &conn_iter); >+ drm_for_each_connector_iter(connector, &conn_iter) { >+ if (!connector->state || connector->state->crtc != crtc) >+ continue; >+ >+ aconn = to_amdgpu_dm_connector(connector); >+ break; >+ } >+ drm_connector_list_iter_end(&conn_iter); >+ >+ if (!aconn) { >+ DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); >+ ret = -EINVAL; >+ goto cleanup; >+ } >+ >+ aux = &aconn->dm_dp_aux.aux; >+ >+ if (!aux) { >+ DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); >+ ret = -EINVAL; >+ goto cleanup; >+ } > } > >- /* When enabling CRC, we should also disable dithering. */ >- dc_stream_set_dither_option(stream_state, >- enable ? DITHER_OPTION_TRUN8 >- : DITHER_OPTION_DEFAULT); >- >- mutex_unlock(&adev->dm.dc_lock); >+ if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { >+ ret = -EINVAL; >+ goto cleanup; >+ } > > /* > * Reading the CRC requires the vblank interrupt handler to be > * enabled. Keep a reference until CRC capture stops. > */ >- if (!crtc_state->crc_enabled && enable) >- drm_crtc_vblank_get(crtc); >- else if (crtc_state->crc_enabled && !enable) >+ enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src); >+ if (!enabled && enable) { >+ ret = drm_crtc_vblank_get(crtc); >+ if (ret) >+ goto cleanup; >+ >+ if (dm_is_crc_source_dprx(source)) { >+ if (drm_dp_start_crc(aux, crtc)) { >+ DRM_DEBUG_DRIVER("dp start crc failed\n"); >+ ret = -EINVAL; >+ goto cleanup; >+ } >+ } >+ } else if (enabled && !enable) { > drm_crtc_vblank_put(crtc); >+ if (dm_is_crc_source_dprx(source)) { >+ if (drm_dp_stop_crc(aux)) { >+ DRM_DEBUG_DRIVER("dp stop crc failed\n"); >+ ret = -EINVAL; >+ goto cleanup; >+ } >+ } >+ } > >- crtc_state->crc_enabled = enable; >+ crtc_state->crc_src = source; > > /* Reset crc_skipped on dm state */ > crtc_state->crc_skip_count = 0; >- return 0; >+ >+cleanup: >+ if (commit) >+ drm_crtc_commit_put(commit); >+ >+ drm_modeset_unlock(&crtc->mutex); >+ >+ return ret; > } > > /** >@@ -135,7 +290,7 @@ > stream_state = crtc_state->stream; > > /* Early return if CRC capture is not enabled. */ >- if (!crtc_state->crc_enabled) >+ if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src)) > return; > > /* >@@ -149,10 +304,12 @@ > return; > } > >- if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, >- &crcs[0], &crcs[1], &crcs[2])) >- return; >+ if (dm_is_crc_source_crtc(crtc_state->crc_src)) { >+ if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, >+ &crcs[0], &crcs[1], &crcs[2])) >+ return; > >- drm_crtc_add_crc_entry(crtc, true, >- drm_crtc_accurate_vblank_count(crtc), crcs); >+ drm_crtc_add_crc_entry(crtc, true, >+ drm_crtc_accurate_vblank_count(crtc), crcs); >+ } > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h 2019-08-31 15:01:11.854736168 -0500 >@@ -0,0 +1,67 @@ >+/* >+ * Copyright 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ >+#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ >+ >+struct drm_crtc; >+struct dm_crtc_state; >+ >+enum amdgpu_dm_pipe_crc_source { >+ AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0, >+ AMDGPU_DM_PIPE_CRC_SOURCE_CRTC, >+ AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER, >+ AMDGPU_DM_PIPE_CRC_SOURCE_DPRX, >+ AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER, >+ AMDGPU_DM_PIPE_CRC_SOURCE_MAX, >+ AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1, >+}; >+ >+static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source) >+{ >+ return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) && >+ (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX); >+} >+ >+/* amdgpu_dm_crc.c */ >+#ifdef CONFIG_DEBUG_FS >+int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, >+ struct dm_crtc_state *dm_crtc_state, >+ enum amdgpu_dm_pipe_crc_source source); >+int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); >+int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, >+ const char *src_name, >+ size_t *values_cnt); >+const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, >+ size_t *count); >+void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); >+#else >+#define amdgpu_dm_crtc_set_crc_source NULL >+#define amdgpu_dm_crtc_verify_crc_source NULL >+#define amdgpu_dm_crtc_get_crc_sources NULL >+#define amdgpu_dm_crtc_handle_crc_irq(x) >+#endif >+ >+#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 2019-08-31 15:01:11.855736168 -0500 >@@ -1053,9 +1053,33 @@ > return 0; > } > >+static int mst_topo(struct seq_file *m, void *unused) >+{ >+ struct drm_info_node *node = (struct drm_info_node *)m->private; >+ struct drm_device *dev = node->minor->dev; >+ struct drm_connector *connector; >+ struct drm_connector_list_iter conn_iter; >+ struct amdgpu_dm_connector *aconnector; >+ >+ drm_connector_list_iter_begin(dev, &conn_iter); >+ drm_for_each_connector_iter(connector, &conn_iter) { >+ if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) >+ continue; >+ >+ aconnector = to_amdgpu_dm_connector(connector); >+ >+ seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); >+ drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); >+ } >+ drm_connector_list_iter_end(&conn_iter); >+ >+ return 0; >+} >+ > static const struct drm_info_list amdgpu_dm_debugfs_list[] = { > {"amdgpu_current_backlight_pwm", ¤t_backlight_read}, > {"amdgpu_target_backlight_pwm", &target_backlight_read}, >+ {"amdgpu_mst_topology", &mst_topo}, > }; > > /* >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 2019-08-31 15:01:11.854736168 -0500 >@@ -50,6 +50,7 @@ > > #include "irq_types.h" > #include "signal_types.h" >+#include "amdgpu_dm_crc.h" > > /* Forward declarations */ > struct amdgpu_device; >@@ -309,11 +310,12 @@ > bool cm_has_degamma; > bool cm_is_degamma_srgb; > >+ int update_type; > int active_planes; > bool interrupts_enabled; > > int crc_skip_count; >- bool crc_enabled; >+ enum amdgpu_dm_pipe_crc_source crc_src; > > bool freesync_timing_changed; > bool freesync_vrr_info_changed; >@@ -380,19 +382,6 @@ > void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, > struct edid *edid); > >-/* amdgpu_dm_crc.c */ >-#ifdef CONFIG_DEBUG_FS >-int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); >-int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, >- const char *src_name, >- size_t *values_cnt); >-void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); >-#else >-#define amdgpu_dm_crtc_set_crc_source NULL >-#define amdgpu_dm_crtc_verify_crc_source NULL >-#define amdgpu_dm_crtc_handle_crc_irq(x) >-#endif >- > #define MAX_COLOR_LUT_ENTRIES 4096 > /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ > #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 2019-08-31 15:01:11.855736168 -0500 >@@ -548,7 +548,9 @@ > bool enable > ) > { >- return false; >+ uint8_t enable_dsc = enable ? 1 : 0; >+ >+ return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1); > } > #endif > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 2019-08-31 15:01:11.855736168 -0500 >@@ -156,6 +156,26 @@ > kfree(amdgpu_dm_connector); > } > >+static int >+amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) >+{ >+ struct amdgpu_dm_connector *amdgpu_dm_connector = >+ to_amdgpu_dm_connector(connector); >+ struct drm_dp_mst_port *port = amdgpu_dm_connector->port; >+ >+ return drm_dp_mst_connector_late_register(connector, port); >+} >+ >+static void >+amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) >+{ >+ struct amdgpu_dm_connector *amdgpu_dm_connector = >+ to_amdgpu_dm_connector(connector); >+ struct drm_dp_mst_port *port = amdgpu_dm_connector->port; >+ >+ drm_dp_mst_connector_early_unregister(connector, port); >+} >+ > static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { > .detect = dm_dp_mst_detect, > .fill_modes = drm_helper_probe_single_connector_modes, >@@ -164,7 +184,9 @@ > .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, > .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, > .atomic_set_property = amdgpu_dm_connector_atomic_set_property, >- .atomic_get_property = amdgpu_dm_connector_atomic_get_property >+ .atomic_get_property = amdgpu_dm_connector_atomic_get_property, >+ .late_register = amdgpu_dm_mst_connector_late_register, >+ .early_unregister = amdgpu_dm_mst_connector_early_unregister, > }; > > static int dm_dp_mst_get_modes(struct drm_connector *connector) >@@ -388,7 +410,7 @@ > struct amdgpu_dm_connector *aconnector) > { > aconnector->dm_dp_aux.aux.name = "dmdc"; >- aconnector->dm_dp_aux.aux.dev = dm->adev->dev; >+ aconnector->dm_dp_aux.aux.dev = aconnector->base.kdev; > aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; > aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 2019-08-31 15:01:11.855736168 -0500 >@@ -151,18 +151,31 @@ > static enum smu_clk_type dc_to_smu_clock_type( > enum dm_pp_clock_type dm_pp_clk_type) > { >-#define DCCLK_MAP_SMUCLK(dcclk, smuclk) \ >- [dcclk] = smuclk >+ enum smu_clk_type smu_clk_type = SMU_CLK_COUNT; > >- static int dc_clk_type_map[] = { >- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DISPLAY_CLK, SMU_DISPCLK), >- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_ENGINE_CLK, SMU_GFXCLK), >- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_MEMORY_CLK, SMU_MCLK), >- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DCEFCLK, SMU_DCEFCLK), >- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_SOCCLK, SMU_SOCCLK), >- }; >+ switch (dm_pp_clk_type) { >+ case DM_PP_CLOCK_TYPE_DISPLAY_CLK: >+ smu_clk_type = SMU_DISPCLK; >+ break; >+ case DM_PP_CLOCK_TYPE_ENGINE_CLK: >+ smu_clk_type = SMU_GFXCLK; >+ break; >+ case DM_PP_CLOCK_TYPE_MEMORY_CLK: >+ smu_clk_type = SMU_MCLK; >+ break; >+ case DM_PP_CLOCK_TYPE_DCEFCLK: >+ smu_clk_type = SMU_DCEFCLK; >+ break; >+ case DM_PP_CLOCK_TYPE_SOCCLK: >+ smu_clk_type = SMU_SOCCLK; >+ break; >+ default: >+ DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n", >+ dm_pp_clk_type); >+ break; >+ } > >- return dc_clk_type_map[dm_pp_clk_type]; >+ return smu_clk_type; > } > > static enum amd_pp_clock_type dc_to_pp_clock_type( >@@ -334,7 +347,7 @@ > } > } else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) { > if (smu_get_clock_by_type(&adev->smu, >- dc_to_smu_clock_type(clk_type), >+ dc_to_pp_clock_type(clk_type), > &pp_clks)) { > get_default_clock_levels(clk_type, dc_clks); > return true; >@@ -419,7 +432,7 @@ > return false; > } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_latency) { > if (smu_get_clock_by_type_with_latency(&adev->smu, >- dc_to_pp_clock_type(clk_type), >+ dc_to_smu_clock_type(clk_type), > &pp_clks)) > return false; > } >@@ -801,6 +814,19 @@ > return PP_SMU_RESULT_OK; > } > >+enum pp_smu_status pp_nv_set_pstate_handshake_support( >+ struct pp_smu *pp, BOOLEAN pstate_handshake_supported) >+{ >+ const struct dc_context *ctx = pp->dm; >+ struct amdgpu_device *adev = ctx->driver_context; >+ struct smu_context *smu = &adev->smu; >+ >+ if (smu_display_disable_memory_clock_switch(smu, !pstate_handshake_supported)) >+ return PP_SMU_RESULT_FAIL; >+ >+ return PP_SMU_RESULT_OK; >+} >+ > enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp, > enum pp_smu_nv_clock_id clock_id, int mhz) > { >@@ -916,6 +942,7 @@ > funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks; > /*todo compare data with window driver */ > funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states; >+ funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support; > break; > #endif > default: >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 2019-08-31 15:01:11.855736168 -0500 >@@ -1881,8 +1881,6 @@ > > .get_device_tag = bios_parser_get_device_tag, > >- .get_firmware_info = bios_parser_get_firmware_info, >- > .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, > > .get_ss_entry_number = bios_parser_get_ss_entry_number, >@@ -1998,6 +1996,7 @@ > dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); > > bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); >+ bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; > > return true; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 2019-08-31 15:01:11.855736168 -0500 >@@ -2796,8 +2796,6 @@ > > .get_device_tag = bios_parser_get_device_tag, > >- .get_firmware_info = bios_parser_get_firmware_info, >- > .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, > > .get_ss_entry_number = bios_parser_get_ss_entry_number, >@@ -2922,6 +2920,7 @@ > dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version); > > bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); >+ bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; > > return true; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 2019-08-31 15:01:11.856736168 -0500 >@@ -67,6 +67,11 @@ > *h = dal_cmd_tbl_helper_dce112_get_table2(); > return true; > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ case DCN_VERSION_2_1: >+ *h = dal_cmd_tbl_helper_dce112_get_table2(); >+ return true; >+#endif > case DCE_VERSION_12_0: > case DCE_VERSION_12_1: > *h = dal_cmd_tbl_helper_dce112_get_table2(); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c 2019-08-31 15:01:11.856736168 -0500 >@@ -153,38 +153,10 @@ > > static uint8_t dig_encoder_sel_to_atom(enum engine_id id) > { >- uint8_t atom_dig_encoder_sel = 0; >- >- switch (id) { >- case ENGINE_ID_DIGA: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL; >- break; >- case ENGINE_ID_DIGB: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL; >- break; >- case ENGINE_ID_DIGC: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL; >- break; >- case ENGINE_ID_DIGD: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL; >- break; >- case ENGINE_ID_DIGE: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL; >- break; >- case ENGINE_ID_DIGF: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL; >- break; >- case ENGINE_ID_DIGG: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL; >- break; >- case ENGINE_ID_UNKNOWN: >- /* No DIG_FRONT is associated to DIG_BACKEND */ >- atom_dig_encoder_sel = 0; >- break; >- default: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL; >- break; >- } >+ /* On any ASIC after DCE80, we manually program the DIG_FE >+ * selection (see connect_dig_be_to_fe function of the link >+ * encoder), so translation should always return 0 (no FE). >+ */ > > return 0; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c 2019-08-31 15:01:11.856736168 -0500 >@@ -150,38 +150,10 @@ > > static uint8_t dig_encoder_sel_to_atom(enum engine_id id) > { >- uint8_t atom_dig_encoder_sel = 0; >- >- switch (id) { >- case ENGINE_ID_DIGA: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL; >- break; >- case ENGINE_ID_DIGB: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL; >- break; >- case ENGINE_ID_DIGC: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL; >- break; >- case ENGINE_ID_DIGD: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL; >- break; >- case ENGINE_ID_DIGE: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL; >- break; >- case ENGINE_ID_DIGF: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL; >- break; >- case ENGINE_ID_DIGG: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL; >- break; >- case ENGINE_ID_UNKNOWN: >- /* No DIG_FRONT is associated to DIG_BACKEND */ >- atom_dig_encoder_sel = 0; >- break; >- default: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL; >- break; >- } >+ /* On any ASIC after DCE80, we manually program the DIG_FE >+ * selection (see connect_dig_be_to_fe function of the link >+ * encoder), so translation should always return 0 (no FE). >+ */ > > return 0; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c 2019-08-31 15:01:11.856736168 -0500 >@@ -150,38 +150,10 @@ > > static uint8_t dig_encoder_sel_to_atom(enum engine_id id) > { >- uint8_t atom_dig_encoder_sel = 0; >- >- switch (id) { >- case ENGINE_ID_DIGA: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL; >- break; >- case ENGINE_ID_DIGB: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL; >- break; >- case ENGINE_ID_DIGC: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL; >- break; >- case ENGINE_ID_DIGD: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL; >- break; >- case ENGINE_ID_DIGE: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL; >- break; >- case ENGINE_ID_DIGF: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL; >- break; >- case ENGINE_ID_DIGG: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL; >- break; >- case ENGINE_ID_UNKNOWN: >- /* No DIG_FRONT is associated to DIG_BACKEND */ >- atom_dig_encoder_sel = 0; >- break; >- default: >- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL; >- break; >- } >+ /* On any ASIC after DCE80, we manually program the DIG_FE >+ * selection (see connect_dig_be_to_fe function of the link >+ * encoder), so translation should always return 0 (no FE). >+ */ > > return 0; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 2019-08-31 15:01:11.856736168 -0500 >@@ -25,6 +25,7 @@ > > #include <linux/slab.h> > >+#include "resource.h" > #include "dm_services.h" > #include "dce_calcs.h" > #include "dc.h" >@@ -2852,7 +2853,7 @@ > data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height); > data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width); > data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed( >- pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch); >+ pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch); > data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps); > data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps); > data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( >@@ -2977,6 +2978,32 @@ > data->number_of_displays = num_displays; > } > >+static bool all_displays_in_sync(const struct pipe_ctx pipe[], >+ int pipe_count) >+{ >+ const struct pipe_ctx *active_pipes[MAX_PIPES]; >+ int i, num_active_pipes = 0; >+ >+ for (i = 0; i < pipe_count; i++) { >+ if (!pipe[i].stream || pipe[i].top_pipe) >+ continue; >+ >+ active_pipes[num_active_pipes++] = &pipe[i]; >+ } >+ >+ if (!num_active_pipes) >+ return false; >+ >+ for (i = 1; i < num_active_pipes; ++i) { >+ if (!resource_are_streams_timing_synchronizable( >+ active_pipes[0]->stream, active_pipes[i]->stream)) { >+ return false; >+ } >+ } >+ >+ return true; >+} >+ > /** > * Return: > * true - Display(s) configuration supported. >@@ -2998,8 +3025,10 @@ > > populate_initial_data(pipe, pipe_count, data); > >- /*TODO: this should be taken out calcs output and assigned during timing sync for pplib use*/ >- calcs_output->all_displays_in_sync = false; >+ if (ctx->dc->config.multi_mon_pp_mclk_switch) >+ calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count); >+ else >+ calcs_output->all_displays_in_sync = false; > > if (data->number_of_displays != 0) { > uint8_t yclk_lvl, sclk_lvl; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 2019-08-31 15:01:11.857736168 -0500 >@@ -329,7 +329,7 @@ > dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0; > } > input->src.dcc_rate = 1; >- input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch; >+ input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch; > input->src.source_scan = dm_horz; > input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; > >@@ -705,6 +705,13 @@ > hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz); > } > >+ >+unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev) >+{ >+ /* we are ok with all levels */ >+ return 4; >+} >+ > bool dcn_validate_bandwidth( > struct dc *dc, > struct dc_state *context, >@@ -732,6 +739,7 @@ > > memset(v, 0, sizeof(*v)); > kernel_fpu_begin(); >+ > v->sr_exit_time = dc->dcn_soc->sr_exit_time; > v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time; > v->urgent_latency = dc->dcn_soc->urgent_latency; >@@ -1268,7 +1276,7 @@ > PERFORMANCE_TRACE_END(); > BW_VAL_TRACE_FINISH(); > >- if (bw_limit_pass && v->voltage_level != 5) >+ if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev)) > return true; > else > return false; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/Makefile 2019-08-31 15:01:11.856736168 -0500 >@@ -32,6 +32,10 @@ > > calcs_ccflags := -mhard-float -msse $(cc_stack_align) > >+ifdef CONFIG_CC_IS_CLANG >+calcs_ccflags += -msse2 >+endif >+ > CFLAGS_dcn_calcs.o := $(calcs_ccflags) > CFLAGS_dcn_calc_auto.o := $(calcs_ccflags) > CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c 2019-08-31 15:01:11.857736168 -0500 >@@ -37,6 +37,9 @@ > #include "dcn10/rv1_clk_mgr.h" > #include "dcn10/rv2_clk_mgr.h" > #include "dcn20/dcn20_clk_mgr.h" >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#include "dcn21/rn_clk_mgr.h" >+#endif > > > int clk_mgr_helper_get_active_display_cnt( >@@ -108,6 +111,12 @@ > > #if defined(CONFIG_DRM_AMD_DC_DCN1_0) > case FAMILY_RV: >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) { >+ rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); >+ break; >+ } >+#endif /* DCN2_1 */ > if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) { > rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); > break; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 2019-08-31 15:01:11.857736168 -0500 >@@ -273,18 +273,12 @@ > { > struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; > struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; >- struct integrated_info info = { { { 0 } } }; >- struct dc_firmware_info fw_info = { { 0 } }; > int i; > > if (bp->integrated_info) >- info = *bp->integrated_info; >- >- clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq; >+ clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; > if (clk_mgr_dce->dentist_vco_freq_khz == 0) { >- bp->funcs->get_firmware_info(bp, &fw_info); >- clk_mgr_dce->dentist_vco_freq_khz = >- fw_info.smu_gpu_pll_output_freq; >+ clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq; > if (clk_mgr_dce->dentist_vco_freq_khz == 0) > clk_mgr_dce->dentist_vco_freq_khz = 3600000; > } >@@ -317,9 +311,10 @@ > > /*Do not allow bad VBIOS/SBIOS to override with invalid values, > * check for > 100MHz*/ >- if (info.disp_clk_voltage[i].max_supported_clk >= 100000) >- clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = >- info.disp_clk_voltage[i].max_supported_clk; >+ if (bp->integrated_info) >+ if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000) >+ clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = >+ bp->integrated_info->disp_clk_voltage[i].max_supported_clk; > } > > if (!debug->disable_dfs_bypass && bp->integrated_info) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 2019-08-31 15:01:11.857736168 -0500 >@@ -34,6 +34,11 @@ > #include "rv1_clk_mgr_vbios_smu.h" > #include "rv1_clk_mgr_clk.h" > >+void rv1_init_clocks(struct clk_mgr *clk_mgr) >+{ >+ memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); >+} >+ > static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) > { > bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; >@@ -232,6 +237,7 @@ > } > > static struct clk_mgr_funcs rv1_clk_funcs = { >+ .init_clocks = rv1_init_clocks, > .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, > .update_clocks = rv1_update_clocks, > .enable_pme_wa = rv1_enable_pme_wa, >@@ -246,7 +252,6 @@ > { > struct dc_debug_options *debug = &ctx->dc->debug; > struct dc_bios *bp = ctx->dc_bios; >- struct dc_firmware_info fw_info = { { 0 } }; > > clk_mgr->base.ctx = ctx; > clk_mgr->pp_smu = pp_smu; >@@ -262,9 +267,8 @@ > > if (bp->integrated_info) > clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; >- if (clk_mgr->dentist_vco_freq_khz == 0) { >- bp->funcs->get_firmware_info(bp, &fw_info); >- clk_mgr->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq; >+ if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) { >+ clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq; > if (clk_mgr->dentist_vco_freq_khz == 0) > clk_mgr->dentist_vco_freq_khz = 3600000; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 2019-08-31 15:01:11.857736168 -0500 >@@ -26,8 +26,6 @@ > #include "dccg.h" > #include "clk_mgr_internal.h" > >- >-#include "dcn20/dcn20_clk_mgr.h" > #include "dce100/dce_clk_mgr.h" > #include "reg_helper.h" > #include "core_types.h" >@@ -106,7 +104,6 @@ > { > int i; > >- clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; > for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { > int dpp_inst, dppclk_khz; > >@@ -116,28 +113,75 @@ > dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; > dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; > clk_mgr->dccg->funcs->update_dpp_dto( >- clk_mgr->dccg, dpp_inst, dppclk_khz); >+ clk_mgr->dccg, dpp_inst, dppclk_khz, false); > } > } > >-void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) >+static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz) > { > int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR >- * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; >- int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR >- * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; >+ * clk_mgr->dentist_vco_freq_khz / khz; > > uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); >- uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); > > REG_UPDATE(DENTIST_DISPCLK_CNTL, >- DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); >-// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); >- REG_UPDATE(DENTIST_DISPCLK_CNTL, > DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); > REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); > } > >+static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz) >+{ >+ int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR >+ * clk_mgr->dentist_vco_freq_khz / khz; >+ >+ uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); >+ >+ REG_UPDATE(DENTIST_DISPCLK_CNTL, >+ DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); >+} >+ >+static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz) >+{ >+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); >+ struct dc *dc = clk_mgr_base->ctx->dc; >+ struct pp_smu_funcs_nv *pp_smu = NULL; >+ bool going_up = clk_mgr->base.clks.dispclk_khz < khz; >+ >+ if (dc->res_pool->pp_smu) >+ pp_smu = &dc->res_pool->pp_smu->nv_funcs; >+ >+ clk_mgr->base.clks.dispclk_khz = khz; >+ >+ if (going_up && pp_smu && pp_smu->set_voltage_by_freq) >+ pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); >+ >+ update_display_clk(clk_mgr, khz); >+ >+ if (!going_up && pp_smu && pp_smu->set_voltage_by_freq) >+ pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); >+} >+ >+static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz) >+{ >+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); >+ struct dc *dc = clk_mgr_base->ctx->dc; >+ struct pp_smu_funcs_nv *pp_smu = NULL; >+ bool going_up = clk_mgr->base.clks.dppclk_khz < khz; >+ >+ if (dc->res_pool->pp_smu) >+ pp_smu = &dc->res_pool->pp_smu->nv_funcs; >+ >+ clk_mgr->base.clks.dppclk_khz = khz; >+ clk_mgr->dccg->ref_dppclk = khz; >+ >+ if (going_up && pp_smu && pp_smu->set_voltage_by_freq) >+ pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); >+ >+ update_global_dpp_clk(clk_mgr, khz); >+ >+ if (!going_up && pp_smu && pp_smu->set_voltage_by_freq) >+ pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); >+} > > void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, > struct dc_state *context, >@@ -148,12 +192,21 @@ > struct dc *dc = clk_mgr_base->ctx->dc; > struct pp_smu_funcs_nv *pp_smu = NULL; > int display_count; >- bool update_dppclk = false; > bool update_dispclk = false; > bool enter_display_off = false; >- bool dpp_clock_lowered = false; > struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; >+ bool force_reset = false; >+ int i; >+ >+ if (dc->work_arounds.skip_clock_update) >+ return; > >+ if (clk_mgr_base->clks.dispclk_khz == 0 || >+ dc->debug.force_clock_mode & 0x1) { >+ //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. >+ force_reset = true; >+ //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. >+ } > display_count = clk_mgr_helper_get_active_display_cnt(dc, context); > if (dc->res_pool->pp_smu) > pp_smu = &dc->res_pool->pp_smu->nv_funcs; >@@ -172,6 +225,7 @@ > pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); > } > >+ > if (dc->debug.force_min_dcfclk_mhz > 0) > new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? > new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); >@@ -196,10 +250,13 @@ > } > > if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { >+ clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; >+ > clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; > if (pp_smu && pp_smu->set_pstate_handshake_support) > pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); > } >+ clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; > > if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { > clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; >@@ -207,35 +264,48 @@ > pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); > } > >- if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { >- if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) >- dpp_clock_lowered = true; >- clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; >+ if (dc->config.forced_clocks == false) { >+ // First update display clock >+ if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) >+ request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz); >+ >+ // Updating DPP clock requires some more logic >+ if (!safe_to_lower) { >+ // For pre-programming, we need to make sure any DPP clock that will go up has to go up >+ >+ // First raise the global reference if needed >+ if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz) >+ request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz); >+ >+ // Then raise any dividers that need raising >+ for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { >+ int dpp_inst, dppclk_khz; > >- if (pp_smu && pp_smu->set_voltage_by_freq) >- pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); >+ if (!context->res_ctx.pipe_ctx[i].plane_state) >+ continue; > >- update_dppclk = true; >- } >+ dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; >+ dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; > >- if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { >- clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; >- if (pp_smu && pp_smu->set_voltage_by_freq) >- pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); >- >- update_dispclk = true; >- } >- if (dc->config.forced_clocks == false) { >- if (dpp_clock_lowered) { >- // if clock is being lowered, increase DTO before lowering refclk >- dcn20_update_clocks_update_dpp_dto(clk_mgr, context); >- dcn20_update_clocks_update_dentist(clk_mgr); >+ clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true); >+ } > } else { >- // if clock is being raised, increase refclk before lowering DTO >- if (update_dppclk || update_dispclk) >- dcn20_update_clocks_update_dentist(clk_mgr); >- if (update_dppclk) >- dcn20_update_clocks_update_dpp_dto(clk_mgr, context); >+ // For post-programming, we can lower ref clk if needed, and unconditionally set all the DTOs >+ >+ if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz) >+ request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz); >+ >+ for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { >+ int dpp_inst, dppclk_khz; >+ >+ if (!context->res_ctx.pipe_ctx[i].plane_state) >+ continue; >+ >+ dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; >+ dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; >+ >+ clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false); >+ } > } > } > if (update_dispclk && >@@ -303,6 +373,7 @@ > memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); > // Assumption is that boot state always supports pstate > clk_mgr->clks.p_state_change_support = true; >+ clk_mgr->clks.prev_p_state_change_support = true; > } > > void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) >@@ -318,11 +389,32 @@ > } > } > >+void dcn2_get_clock(struct clk_mgr *clk_mgr, >+ struct dc_state *context, >+ enum dc_clock_type clock_type, >+ struct dc_clock_config *clock_cfg) >+{ >+ >+ if (clock_type == DC_CLOCK_TYPE_DISPCLK) { >+ clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; >+ clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; >+ clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; >+ clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; >+ } >+ if (clock_type == DC_CLOCK_TYPE_DPPCLK) { >+ clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; >+ clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; >+ clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; >+ clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; >+ } >+} >+ > static struct clk_mgr_funcs dcn2_funcs = { > .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, > .update_clocks = dcn2_update_clocks, > .init_clocks = dcn2_init_clocks, >- .enable_pme_wa = dcn2_enable_pme_wa >+ .enable_pme_wa = dcn2_enable_pme_wa, >+ .get_clock = dcn2_get_clock, > }; > > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h 2019-08-31 15:01:11.857736168 -0500 >@@ -45,4 +45,9 @@ > > uint32_t dentist_get_did_from_divider(int divider); > >+void dcn2_get_clock(struct clk_mgr *clk_mgr, >+ struct dc_state *context, >+ enum dc_clock_type clock_type, >+ struct dc_clock_config *clock_cfg); >+ > #endif //__DCN20_CLK_MGR_H__ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 2019-08-31 15:01:11.857736168 -0500 >@@ -0,0 +1,590 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#include "dccg.h" >+#include "clk_mgr_internal.h" >+ >+ >+#include "dcn20/dcn20_clk_mgr.h" >+#include "rn_clk_mgr.h" >+ >+ >+#include "dce100/dce_clk_mgr.h" >+#include "rn_clk_mgr_vbios_smu.h" >+#include "reg_helper.h" >+#include "core_types.h" >+#include "dm_helpers.h" >+ >+#include "atomfirmware.h" >+#include "clk/clk_10_0_2_offset.h" >+#include "clk/clk_10_0_2_sh_mask.h" >+#include "renoir_ip_offset.h" >+ >+ >+/* Constants */ >+ >+#define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */ >+ >+/* Macros */ >+ >+#define REG(reg_name) \ >+ (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) >+ >+void rn_update_clocks(struct clk_mgr *clk_mgr_base, >+ struct dc_state *context, >+ bool safe_to_lower) >+{ >+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); >+ struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; >+ struct dc *dc = clk_mgr_base->ctx->dc; >+ int display_count; >+ bool update_dppclk = false; >+ bool update_dispclk = false; >+ bool enter_display_off = false; >+ bool dpp_clock_lowered = false; >+ struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; >+ >+ display_count = clk_mgr_helper_get_active_display_cnt(dc, context); >+ >+ if (display_count == 0) >+ enter_display_off = true; >+ >+ if (enter_display_off == safe_to_lower) { >+ rn_vbios_smu_set_display_count(clk_mgr, display_count); >+ } >+ >+ if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { >+ clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; >+ rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); >+ } >+ >+ if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { >+ clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; >+ rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); >+ } >+ >+ if (should_set_clock(safe_to_lower, >+ new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { >+ clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; >+ rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); >+ } >+ >+ if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { >+ if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) >+ dpp_clock_lowered = true; >+ clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; >+ update_dppclk = true; >+ } >+ >+ if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { >+ clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; >+ rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); >+ >+ update_dispclk = true; >+ } >+ >+ if (dpp_clock_lowered) { >+ // if clock is being lowered, increase DTO before lowering refclk >+ dcn20_update_clocks_update_dpp_dto(clk_mgr, context); >+ rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); >+ } else { >+ // if clock is being raised, increase refclk before lowering DTO >+ if (update_dppclk || update_dispclk) >+ rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); >+ if (update_dppclk) >+ dcn20_update_clocks_update_dpp_dto(clk_mgr, context); >+ } >+ >+ if (update_dispclk && >+ dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { >+ /*update dmcu for wait_loop count*/ >+ dmcu->funcs->set_psr_wait_loop(dmcu, >+ clk_mgr_base->clks.dispclk_khz / 1000 / 7); >+ } >+} >+ >+ >+static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) >+{ >+ /* get FbMult value */ >+ struct fixed31_32 pll_req; >+ unsigned int fbmult_frac_val = 0; >+ unsigned int fbmult_int_val = 0; >+ >+ >+ /* >+ * Register value of fbmult is in 8.16 format, we are converting to 31.32 >+ * to leverage the fix point operations available in driver >+ */ >+ >+ REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ >+ REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ >+ >+ pll_req = dc_fixpt_from_int(fbmult_int_val); >+ >+ /* >+ * since fractional part is only 16 bit in register definition but is 32 bit >+ * in our fix point definiton, need to shift left by 16 to obtain correct value >+ */ >+ pll_req.value |= fbmult_frac_val << 16; >+ >+ /* multiply by REFCLK period */ >+ pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); >+ >+ /* integer part is now VCO frequency in kHz */ >+ return dc_fixpt_floor(pll_req); >+} >+ >+static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base) >+{ >+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); >+ >+ internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); >+ internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); >+ >+ internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider >+ internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); >+ >+ internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); >+ internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); >+ >+ internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); >+ internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); >+ >+ internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); >+ internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); >+} >+ >+/* This function collect raw clk register values */ >+static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, >+ struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) >+{ >+ struct rn_clk_internal internal = {0}; >+ char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; >+ unsigned int chars_printed = 0; >+ unsigned int remaining_buffer = log_info->bufSize; >+ >+ rn_dump_clk_registers_internal(&internal, clk_mgr_base); >+ >+ regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; >+ regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; >+ regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; >+ regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; >+ regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; >+ regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; >+ >+ regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; >+ if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) >+ regs_and_bypass->dppclk_bypass = 0; >+ regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; >+ if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) >+ regs_and_bypass->dcfclk_bypass = 0; >+ regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; >+ if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) >+ regs_and_bypass->dispclk_bypass = 0; >+ regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; >+ if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) >+ regs_and_bypass->dprefclk_bypass = 0; >+ >+ if (log_info->enabled) { >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", >+ regs_and_bypass->dcfclk, >+ regs_and_bypass->dcf_deep_sleep_divider, >+ regs_and_bypass->dcf_deep_sleep_allow, >+ bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n", >+ regs_and_bypass->dprefclk, >+ bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n", >+ regs_and_bypass->dispclk, >+ bypass_clks[(int) regs_and_bypass->dispclk_bypass]); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ //split >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n"); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ // REGISTER VALUES >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n"); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", >+ internal.CLK1_CLK3_CURRENT_CNT); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n", >+ internal.CLK1_CLK3_DS_CNTL); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n", >+ internal.CLK1_CLK3_ALLOW_DS); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n", >+ internal.CLK1_CLK2_CURRENT_CNT); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n", >+ internal.CLK1_CLK0_CURRENT_CNT); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", >+ internal.CLK1_CLK1_CURRENT_CNT); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", >+ internal.CLK1_CLK3_BYPASS_CNTL); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n", >+ internal.CLK1_CLK2_BYPASS_CNTL); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n", >+ internal.CLK1_CLK0_BYPASS_CNTL); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ >+ chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n", >+ internal.CLK1_CLK1_BYPASS_CNTL); >+ remaining_buffer -= chars_printed; >+ *log_info->sum_chars_printed += chars_printed; >+ log_info->pBuf += chars_printed; >+ } >+} >+ >+/* This function produce translated logical clk state values*/ >+void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s) >+{ >+ struct clk_state_registers_and_bypass sb = { 0 }; >+ struct clk_log_info log_info = { 0 }; >+ >+ rn_dump_clk_registers(&sb, clk_mgr_base, &log_info); >+ >+ s->dprefclk_khz = sb.dprefclk; >+} >+ >+void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) >+{ >+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); >+ >+ rn_vbios_smu_enable_pme_wa(clk_mgr); >+} >+ >+static struct clk_mgr_funcs dcn21_funcs = { >+ .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, >+ .update_clocks = rn_update_clocks, >+ .init_clocks = dcn2_init_clocks, >+ .enable_pme_wa = rn_enable_pme_wa, >+ /* .dump_clk_registers = rn_dump_clk_registers */ >+}; >+ >+struct clk_bw_params rn_bw_params = { >+ .vram_type = Ddr4MemType, >+ .num_channels = 1, >+ .clk_table = { >+ .entries = { >+ { >+ .voltage = 0, >+ .dcfclk_mhz = 400, >+ .fclk_mhz = 400, >+ .memclk_mhz = 800, >+ .socclk_mhz = 0, >+ }, >+ { >+ .voltage = 0, >+ .dcfclk_mhz = 483, >+ .fclk_mhz = 800, >+ .memclk_mhz = 1600, >+ .socclk_mhz = 0, >+ }, >+ { >+ .voltage = 0, >+ .dcfclk_mhz = 602, >+ .fclk_mhz = 1067, >+ .memclk_mhz = 1067, >+ .socclk_mhz = 0, >+ }, >+ { >+ .voltage = 0, >+ .dcfclk_mhz = 738, >+ .fclk_mhz = 1333, >+ .memclk_mhz = 1600, >+ .socclk_mhz = 0, >+ }, >+ }, >+ >+ .num_entries = 4, >+ }, >+ >+ .wm_table = { >+ .entries = { >+ { >+ .wm_inst = WM_A, >+ .wm_type = WM_TYPE_PSTATE_CHG, >+ .pstate_latency_us = 23.84, >+ .valid = true, >+ }, >+ { >+ .wm_inst = WM_B, >+ .wm_type = WM_TYPE_PSTATE_CHG, >+ .pstate_latency_us = 23.84, >+ .valid = true, >+ }, >+ { >+ .wm_inst = WM_C, >+ .wm_type = WM_TYPE_PSTATE_CHG, >+ .pstate_latency_us = 23.84, >+ .valid = true, >+ }, >+ { >+ .wm_inst = WM_D, >+ .wm_type = WM_TYPE_PSTATE_CHG, >+ .pstate_latency_us = 23.84, >+ .valid = true, >+ }, >+ }, >+ } >+}; >+ >+void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) >+{ >+ int i, num_valid_sets; >+ >+ num_valid_sets = 0; >+ >+ for (i = 0; i < WM_SET_COUNT; i++) { >+ /* skip empty entries, the smu array has no holes*/ >+ if (!bw_params->wm_table.entries[i].valid) >+ continue; >+ >+ ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; >+ ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;; >+ /* We will not select WM based on dcfclk, so leave it as unconstrained */ >+ ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; >+ ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >+ /* fclk wil be used to select WM*/ >+ >+ if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { >+ if (i == 0) >+ ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0; >+ else { >+ /* add 1 to make it non-overlapping with next lvl */ >+ ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1; >+ } >+ ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz; >+ >+ } else { >+ /* unconstrained for memory retraining */ >+ ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; >+ ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >+ >+ /* Modify previous watermark range to cover up to max */ >+ ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >+ } >+ num_valid_sets++; >+ } >+ >+ ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ >+ ranges->num_reader_wm_sets = num_valid_sets; >+ >+ /* modify the min and max to make sure we cover the whole range*/ >+ ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; >+ ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; >+ ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >+ ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >+ >+ /* This is for writeback only, does not matter currently as no writeback support*/ >+ ranges->num_writer_wm_sets = 1; >+ ranges->writer_wm_sets[0].wm_inst = WM_A; >+ ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; >+ ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >+ ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; >+ ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >+ >+} >+ >+void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id) >+{ >+ int i; >+ >+ ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); >+ >+ for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) { >+ if (clock_table->FClocks[i].Freq == 0) >+ break; >+ >+ bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i].Freq; >+ bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[i].Freq; >+ bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[i].Freq; >+ bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i].Freq; >+ bw_params->clk_table.entries[i].voltage = clock_table->FClocks[i].Vol; >+ } >+ bw_params->clk_table.num_entries = i; >+ >+ bw_params->vram_type = asic_id->vram_type; >+ bw_params->num_channels = asic_id->vram_width / DDR4_DRAM_WIDTH; >+ >+ for (i = 0; i < WM_SET_COUNT; i++) { >+ bw_params->wm_table.entries[i].wm_inst = i; >+ >+ if (clock_table->FClocks[i].Freq == 0) { >+ bw_params->wm_table.entries[i].valid = false; >+ continue; >+ } >+ >+ bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; >+ bw_params->wm_table.entries[i].valid = true; >+ } >+ >+ if (bw_params->vram_type == LpDdr4MemType) { >+ /* >+ * WM set D will be re-purposed for memory retraining >+ */ >+ bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; >+ bw_params->wm_table.entries[WM_D].wm_inst = WM_D; >+ bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; >+ bw_params->wm_table.entries[WM_D].valid = true; >+ } >+ >+} >+ >+void rn_clk_mgr_construct( >+ struct dc_context *ctx, >+ struct clk_mgr_internal *clk_mgr, >+ struct pp_smu_funcs *pp_smu, >+ struct dccg *dccg) >+{ >+ struct dc_debug_options *debug = &ctx->dc->debug; >+ struct dpm_clocks clock_table = { 0 }; >+ struct clk_state_registers_and_bypass s = { 0 }; >+ >+ clk_mgr->base.ctx = ctx; >+ clk_mgr->base.funcs = &dcn21_funcs; >+ >+ clk_mgr->pp_smu = pp_smu; >+ >+ clk_mgr->dccg = dccg; >+ clk_mgr->dfs_bypass_disp_clk = 0; >+ >+ clk_mgr->dprefclk_ss_percentage = 0; >+ clk_mgr->dprefclk_ss_divider = 1000; >+ clk_mgr->ss_on_dprefclk = false; >+ clk_mgr->dfs_ref_freq_khz = 48000; >+ >+ clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); >+ >+ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { >+ dcn21_funcs.update_clocks = dcn2_update_clocks_fpga; >+ clk_mgr->dentist_vco_freq_khz = 3600000; >+ clk_mgr->base.dprefclk_khz = 600000; >+ } else { >+ struct clk_log_info log_info = {0}; >+ >+ /* TODO: Check we get what we expect during bringup */ >+ clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr); >+ >+ /* in case we don't get a value from the register, use default */ >+ if (clk_mgr->dentist_vco_freq_khz == 0) >+ clk_mgr->dentist_vco_freq_khz = 3600000; >+ >+ rn_dump_clk_registers(&s, &clk_mgr->base, &log_info); >+ clk_mgr->base.dprefclk_khz = s.dprefclk; >+ >+ if (clk_mgr->base.dprefclk_khz != 600000) { >+ clk_mgr->base.dprefclk_khz = 600000; >+ ASSERT(1); //TODO: Renoir follow up. >+ } >+ >+ /* in case we don't get a value from the register, use default */ >+ if (clk_mgr->base.dprefclk_khz == 0) >+ clk_mgr->base.dprefclk_khz = 600000; >+ } >+ >+ dce_clock_read_ss_info(clk_mgr); >+ >+ clk_mgr->base.bw_params = &rn_bw_params; >+ >+ if (pp_smu) { >+ pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); >+ clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id); >+ } >+ >+ /* >+ * Notify SMU which set of WM should be selected for different ranges of fclk >+ * On Renoir there is a maximumum of 4 DF pstates supported, could be less >+ * depending on DDR speed and fused maximum fclk. >+ */ >+ if (!debug->disable_pplib_wm_range) { >+ struct pp_smu_wm_range_sets ranges = {0}; >+ >+ build_watermark_ranges(clk_mgr->base.bw_params, &ranges); >+ >+ /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ >+ if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) >+ pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges); >+ } >+ >+ /* enable powerfeatures when displaycount goes to 0 */ >+ if (!debug->disable_48mhz_pwrdwn) >+ rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr); >+} >+ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h 2019-08-31 15:01:11.857736168 -0500 >@@ -0,0 +1,39 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef __RN_CLK_MGR_H__ >+#define __RN_CLK_MGR_H__ >+ >+struct rn_clk_registers { >+ uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */ >+}; >+ >+ >+void rn_clk_mgr_construct(struct dc_context *ctx, >+ struct clk_mgr_internal *clk_mgr, >+ struct pp_smu_funcs *pp_smu, >+ struct dccg *dccg); >+ >+#endif //__RN_CLK_MGR_H__ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 2019-08-31 15:01:11.857736168 -0500 >@@ -0,0 +1,200 @@ >+/* >+ * Copyright 2012-16 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#include "core_types.h" >+#include "clk_mgr_internal.h" >+#include "reg_helper.h" >+ >+#include "renoir_ip_offset.h" >+ >+#include "mp/mp_12_0_0_offset.h" >+#include "mp/mp_12_0_0_sh_mask.h" >+ >+#define REG(reg_name) \ >+ (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) >+ >+#define FN(reg_name, field) \ >+ FD(reg_name##__##field) >+ >+#define VBIOSSMC_MSG_TestMessage 0x1 >+#define VBIOSSMC_MSG_GetSmuVersion 0x2 >+#define VBIOSSMC_MSG_PowerUpGfx 0x3 >+#define VBIOSSMC_MSG_SetDispclkFreq 0x4 >+#define VBIOSSMC_MSG_SetDprefclkFreq 0x5 >+#define VBIOSSMC_MSG_PowerDownGfx 0x6 >+#define VBIOSSMC_MSG_SetDppclkFreq 0x7 >+#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x8 >+#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x9 >+#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0xA >+#define VBIOSSMC_MSG_GetFclkFrequency 0xB >+#define VBIOSSMC_MSG_SetDisplayCount 0xC >+#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD >+#define VBIOSSMC_MSG_UpdatePmeRestore 0xE >+ >+int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) >+{ >+ /* First clear response register */ >+ REG_WRITE(MP1_SMN_C2PMSG_91, 0); >+ >+ /* Set the parameter register for the SMU message, unit is Mhz */ >+ REG_WRITE(MP1_SMN_C2PMSG_83, param); >+ >+ /* Trigger the message transaction by writing the message ID */ >+ REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); >+ >+ REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000); >+ >+ /* Actual dispclk set is returned in the parameter register */ >+ return REG_READ(MP1_SMN_C2PMSG_83); >+} >+ >+int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) >+{ >+ return rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_GetSmuVersion, >+ 0); >+} >+ >+ >+int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) >+{ >+ int actual_dispclk_set_mhz = -1; >+ struct dc *core_dc = clk_mgr->base.ctx->dc; >+ struct dmcu *dmcu = core_dc->res_pool->dmcu; >+ uint32_t clk = requested_dispclk_khz / 1000; >+ >+ if (clk <= 100) >+ clk = 101; >+ >+ /* Unit of SMU msg parameter is Mhz */ >+ actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_SetDispclkFreq, >+ clk); >+ >+ if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { >+ if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { >+ if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) >+ dmcu->funcs->set_psr_wait_loop(dmcu, >+ actual_dispclk_set_mhz / 7); >+ } >+ } >+ >+ return actual_dispclk_set_mhz * 1000; >+} >+ >+int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) >+{ >+ int actual_dprefclk_set_mhz = -1; >+ >+ actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_SetDprefclkFreq, >+ clk_mgr->base.dprefclk_khz / 1000); >+ >+ /* TODO: add code for programing DP DTO, currently this is down by command table */ >+ >+ return actual_dprefclk_set_mhz * 1000; >+} >+ >+int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) >+{ >+ int actual_dcfclk_set_mhz = -1; >+ >+ if (clk_mgr->smu_ver < 0xFFFFFFFF) >+ return actual_dcfclk_set_mhz; >+ >+ actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_SetHardMinDcfclkByFreq, >+ requested_dcfclk_khz / 1000); >+ >+ return actual_dcfclk_set_mhz * 1000; >+} >+ >+int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) >+{ >+ int actual_min_ds_dcfclk_mhz = -1; >+ >+ if (clk_mgr->smu_ver < 0xFFFFFFFF) >+ return actual_min_ds_dcfclk_mhz; >+ >+ actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_SetMinDeepSleepDcfclk, >+ requested_min_ds_dcfclk_khz / 1000); >+ >+ return actual_min_ds_dcfclk_mhz * 1000; >+} >+ >+void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz) >+{ >+ rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_SetPhyclkVoltageByFreq, >+ requested_phyclk_khz / 1000); >+} >+ >+int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) >+{ >+ int actual_dppclk_set_mhz = -1; >+ >+ uint32_t clk = requested_dpp_khz / 1000; >+ >+ if (clk <= 100) >+ clk = 101; >+ >+ actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_SetDppclkFreq, >+ clk); >+ >+ return actual_dppclk_set_mhz * 1000; >+} >+ >+void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count) >+{ >+ rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_SetDisplayCount, >+ display_count); >+} >+ >+void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr) >+{ >+ rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown, >+ 0); >+} >+ >+void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) >+{ >+ rn_vbios_smu_send_msg_with_param( >+ clk_mgr, >+ VBIOSSMC_MSG_UpdatePmeRestore, >+ 0); >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h 2019-08-31 15:01:11.857736168 -0500 >@@ -0,0 +1,40 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_ >+#define DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_ >+ >+int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); >+int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); >+int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); >+int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); >+int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); >+void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz); >+int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); >+void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count); >+void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr); >+void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); >+ >+#endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile 2019-08-31 15:01:11.857736168 -0500 >@@ -85,3 +85,13 @@ > AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20) > endif > >+ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+############################################################################### >+# DCN21 >+############################################################################### >+CLK_MGR_DCN21 = rn_clk_mgr.o rn_clk_mgr_vbios_smu.o >+ >+AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21)) >+ >+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21) >+endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc.c 2019-08-31 15:01:12.256736203 -0500 >@@ -181,13 +181,25 @@ > link = link_create(&link_init_params); > > if (link) { >- if (dc->config.edp_not_connected && >- link->connector_signal == SIGNAL_TYPE_EDP) { >- link_destroy(&link); >- } else { >+ bool should_destory_link = false; >+ >+ if (link->connector_signal == SIGNAL_TYPE_EDP) { >+ if (dc->config.edp_not_connected) >+ should_destory_link = true; >+ else if (dc->debug.remove_disconnect_edp) { >+ enum dc_connection_type type; >+ dc_link_detect_sink(link, &type); >+ if (type == dc_connection_none) >+ should_destory_link = true; >+ } >+ } >+ >+ if (!should_destory_link) { > dc->links[dc->link_count] = link; > link->dc = dc; > ++dc->link_count; >+ } else { >+ link_destroy(&link); > } > } > } >@@ -279,7 +291,9 @@ > dc->hwss.set_drr(&pipe, > 1, > adjust->v_total_min, >- adjust->v_total_max); >+ adjust->v_total_max, >+ adjust->v_total_mid, >+ adjust->v_total_mid_frame_num); > > ret = true; > } >@@ -675,6 +689,11 @@ > if (!dc->clk_mgr) > goto fail; > >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+ if (dc->res_pool->funcs->update_bw_bounding_box) >+ dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); >+#endif >+ > /* Creation of current_state must occur after dc->dml > * is initialized in dc_create_resource_pool because > * on creation it copies the contents of dc->dml >@@ -948,7 +967,7 @@ > { > struct timing_generator *tg; > struct dc_link *link = sink->link; >- unsigned int inst; >+ unsigned int enc_inst, tg_inst; > > /* Check for enabled DIG to identify enabled display */ > if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) >@@ -960,13 +979,22 @@ > * current implementation always map 1-to-1, so this code makes > * the same assumption and doesn't check OTG source. > */ >- inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1; >+ enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); > > /* Instance should be within the range of the pool */ >- if (inst >= dc->res_pool->pipe_count) >+ if (enc_inst >= dc->res_pool->pipe_count) >+ return false; >+ >+ if (enc_inst >= dc->res_pool->stream_enc_count) > return false; > >- tg = dc->res_pool->timing_generators[inst]; >+ tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg( >+ dc->res_pool->stream_enc[enc_inst]); >+ >+ if (tg_inst >= dc->res_pool->timing_generator_count) >+ return false; >+ >+ tg = dc->res_pool->timing_generators[tg_inst]; > > if (!tg->funcs->is_matching_timing) > return false; >@@ -979,10 +1007,11 @@ > > dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( > dc->res_pool->dp_clock_source, >- inst, &pix_clk_100hz); >+ tg_inst, &pix_clk_100hz); > > if (crtc_timing->pix_clk_100hz != pix_clk_100hz) > return false; >+ > } > > return true; >@@ -1065,7 +1094,7 @@ > if (result != DC_OK) > return result; > >- if (context->stream_count > 1) { >+ if (context->stream_count > 1 && !dc->debug.disable_timing_sync) { > enable_timing_multisync(dc, context); > program_timing_sync(dc, context); > } >@@ -1208,6 +1237,12 @@ > if (cur_pipe->bottom_pipe) > cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; > >+ if (cur_pipe->prev_odm_pipe) >+ cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; >+ >+ if (cur_pipe->next_odm_pipe) >+ cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; >+ > } > > for (i = 0; i < new_ctx->stream_count; i++) { >@@ -1239,6 +1274,55 @@ > kref_put(&context->refcount, dc_state_free); > } > >+bool dc_set_generic_gpio_for_stereo(bool enable, >+ struct gpio_service *gpio_service) >+{ >+ enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR; >+ struct gpio_pin_info pin_info; >+ struct gpio *generic; >+ struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config), >+ GFP_KERNEL); >+ >+ if (!config) >+ return false; >+ pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0); >+ >+ if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) { >+ kfree(config); >+ return false; >+ } else { >+ generic = dal_gpio_service_create_generic_mux( >+ gpio_service, >+ pin_info.offset, >+ pin_info.mask); >+ } >+ >+ if (!generic) { >+ kfree(config); >+ return false; >+ } >+ >+ gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT); >+ >+ config->enable_output_from_mux = enable; >+ config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC; >+ >+ if (gpio_result == GPIO_RESULT_OK) >+ gpio_result = dal_mux_setup_config(generic, config); >+ >+ if (gpio_result == GPIO_RESULT_OK) { >+ dal_gpio_close(generic); >+ dal_gpio_destroy_generic_mux(&generic); >+ kfree(config); >+ return true; >+ } else { >+ dal_gpio_close(generic); >+ dal_gpio_destroy_generic_mux(&generic); >+ kfree(config); >+ return false; >+ } >+} >+ > static bool is_surface_in_context( > const struct dc_state *context, > const struct dc_plane_state *plane_state) >@@ -1305,8 +1389,8 @@ > } > > if (u->plane_info->dcc.enable != u->surface->dcc.enable >- || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks >- || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch) { >+ || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks >+ || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) { > update_flags->bits.dcc_change = 1; > elevate_update_type(&update_type, UPDATE_TYPE_MED); > } >@@ -1320,9 +1404,9 @@ > elevate_update_type(&update_type, UPDATE_TYPE_FULL); > } > >- if (u->plane_info->plane_size.grph.surface_pitch != u->surface->plane_size.grph.surface_pitch >- || u->plane_info->plane_size.video.luma_pitch != u->surface->plane_size.video.luma_pitch >- || u->plane_info->plane_size.video.chroma_pitch != u->surface->plane_size.video.chroma_pitch) { >+ if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch >+ || u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch >+ || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) { > update_flags->bits.plane_size_change = 1; > elevate_update_type(&update_type, UPDATE_TYPE_MED); > } >@@ -1542,6 +1626,9 @@ > for (i = 0; i < surface_count; i++) > updates[i].surface->update_flags.raw = 0xFFFFFFFF; > >+ if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) >+ dc->optimized_required = true; >+ > return type; > } > >@@ -1618,6 +1705,8 @@ > srf_update->plane_info->dcc; > surface->sdr_white_level = > srf_update->plane_info->sdr_white_level; >+ surface->layer_index = >+ srf_update->plane_info->layer_index; > } > > if (srf_update->gamma && >@@ -1784,9 +1873,7 @@ > for (j = 0; j < dc->res_pool->pipe_count; j++) { > struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; > >- if (!pipe_ctx->top_pipe && >- pipe_ctx->stream && >- pipe_ctx->stream == stream) { >+ if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) { > > if (stream_update->periodic_interrupt0 && > dc->hwss.setup_periodic_interrupt) >@@ -1812,7 +1899,7 @@ > > if (stream_update->dither_option) { > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) >- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; > #endif > resource_build_bit_depth_reduction_params(pipe_ctx->stream, > &pipe_ctx->stream->bit_depth_params); >@@ -1820,10 +1907,12 @@ > &stream->bit_depth_params, > &stream->clamping); > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) >- if (odm_pipe) >+ while (odm_pipe) { > odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp, > &stream->bit_depth_params, > &stream->clamping); >+ odm_pipe = odm_pipe->next_odm_pipe; >+ } > #endif > } > >@@ -1840,13 +1929,21 @@ > > if (stream_update->dpms_off) { > dc->hwss.pipe_control_lock(dc, pipe_ctx, true); >+ > if (*stream_update->dpms_off) { >- core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE); >+ core_link_disable_stream(pipe_ctx); >+ /* for dpms, keep acquired resources*/ >+ if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) >+ pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); >+ > dc->hwss.optimize_bandwidth(dc, dc->current_state); > } else { >- dc->hwss.prepare_bandwidth(dc, dc->current_state); >+ if (!dc->optimize_seamless_boot) >+ dc->hwss.prepare_bandwidth(dc, dc->current_state); >+ > core_link_enable_stream(dc->current_state, pipe_ctx); > } >+ > dc->hwss.pipe_control_lock(dc, pipe_ctx, false); > } > >@@ -1936,6 +2033,7 @@ > struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; > > if (!pipe_ctx->top_pipe && >+ !pipe_ctx->prev_odm_pipe && > pipe_ctx->stream && > pipe_ctx->stream == stream) { > struct dc_stream_status *stream_status = NULL; >@@ -2050,7 +2148,7 @@ > enum surface_update_type update_type; > struct dc_state *context; > struct dc_context *dc_ctx = dc->ctx; >- int i, j; >+ int i; > > stream_status = dc_stream_get_status(stream); > context = dc->current_state; >@@ -2088,16 +2186,6 @@ > > copy_surface_update_to_plane(surface, &srf_updates[i]); > >- if (update_type >= UPDATE_TYPE_MED) { >- for (j = 0; j < dc->res_pool->pipe_count; j++) { >- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; >- >- if (pipe_ctx->plane_state != surface) >- continue; >- >- resource_build_scaling_params(pipe_ctx); >- } >- } > } > > copy_stream_update_to_stream(dc, context, stream, stream_update); >@@ -2187,6 +2275,14 @@ > dc_resource_state_construct(dc, dc->current_state); > > dc->hwss.init_hw(dc); >+ >+#ifdef CONFIG_DRM_AMD_DC_DCN2_0 >+ if (dc->hwss.init_sys_ctx != NULL && >+ dc->vm_pa_config.valid) { >+ dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config); >+ } >+#endif >+ > break; > default: > ASSERT(dc->current_state->stream_count == 0); >@@ -2387,3 +2483,14 @@ > info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz; > info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz; > } >+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping) >+{ >+ if (dc->hwss.set_clock) >+ return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping); >+ return DC_ERROR_UNEXPECTED; >+} >+void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) >+{ >+ if (dc->hwss.get_clock) >+ dc->hwss.get_clock(dc, clock_type, clock_cfg); >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_debug.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_debug.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_debug.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_debug.c 2019-08-31 15:01:11.857736168 -0500 >@@ -115,16 +115,16 @@ > plane_state->clip_rect.height); > > SURFACE_TRACE( >- "plane_state->plane_size.grph.surface_size.x = %d;\n" >- "plane_state->plane_size.grph.surface_size.y = %d;\n" >- "plane_state->plane_size.grph.surface_size.width = %d;\n" >- "plane_state->plane_size.grph.surface_size.height = %d;\n" >- "plane_state->plane_size.grph.surface_pitch = %d;\n", >- plane_state->plane_size.grph.surface_size.x, >- plane_state->plane_size.grph.surface_size.y, >- plane_state->plane_size.grph.surface_size.width, >- plane_state->plane_size.grph.surface_size.height, >- plane_state->plane_size.grph.surface_pitch); >+ "plane_state->plane_size.surface_size.x = %d;\n" >+ "plane_state->plane_size.surface_size.y = %d;\n" >+ "plane_state->plane_size.surface_size.width = %d;\n" >+ "plane_state->plane_size.surface_size.height = %d;\n" >+ "plane_state->plane_size.surface_pitch = %d;\n", >+ plane_state->plane_size.surface_size.x, >+ plane_state->plane_size.surface_size.y, >+ plane_state->plane_size.surface_size.width, >+ plane_state->plane_size.surface_size.height, >+ plane_state->plane_size.surface_pitch); > > > SURFACE_TRACE( >@@ -202,20 +202,20 @@ > SURFACE_TRACE( > "plane_info->color_space = %d;\n" > "plane_info->format = %d;\n" >- "plane_info->plane_size.grph.surface_pitch = %d;\n" >- "plane_info->plane_size.grph.surface_size.height = %d;\n" >- "plane_info->plane_size.grph.surface_size.width = %d;\n" >- "plane_info->plane_size.grph.surface_size.x = %d;\n" >- "plane_info->plane_size.grph.surface_size.y = %d;\n" >+ "plane_info->plane_size.surface_pitch = %d;\n" >+ "plane_info->plane_size.surface_size.height = %d;\n" >+ "plane_info->plane_size.surface_size.width = %d;\n" >+ "plane_info->plane_size.surface_size.x = %d;\n" >+ "plane_info->plane_size.surface_size.y = %d;\n" > "plane_info->rotation = %d;\n" > "plane_info->stereo_format = %d;\n", > update->plane_info->color_space, > update->plane_info->format, >- update->plane_info->plane_size.grph.surface_pitch, >- update->plane_info->plane_size.grph.surface_size.height, >- update->plane_info->plane_size.grph.surface_size.width, >- update->plane_info->plane_size.grph.surface_size.x, >- update->plane_info->plane_size.grph.surface_size.y, >+ update->plane_info->plane_size.surface_pitch, >+ update->plane_info->plane_size.surface_size.height, >+ update->plane_info->plane_size.surface_size.width, >+ update->plane_info->plane_size.surface_size.x, >+ update->plane_info->plane_size.surface_size.y, > update->plane_info->rotation, > update->plane_info->stereo_format); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link.c 2019-08-31 15:01:11.858736168 -0500 >@@ -45,10 +45,6 @@ > #include "dpcd_defs.h" > #include "dmcu.h" > #include "hw/clk_mgr.h" >-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) >-#include "resource.h" >-#endif >-#include "hw/clk_mgr.h" > > #define DC_LOGGER_INIT(logger) > >@@ -684,6 +680,56 @@ > return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0); > } > >+bool wait_for_alt_mode(struct dc_link *link) >+{ >+ >+ /** >+ * something is terribly wrong if time out is > 200ms. (5Hz) >+ * 500 microseconds * 400 tries us 200 ms >+ **/ >+ unsigned int sleep_time_in_microseconds = 500; >+ unsigned int tries_allowed = 400; >+ bool is_in_alt_mode; >+ unsigned long long enter_timestamp; >+ unsigned long long finish_timestamp; >+ unsigned long long time_taken_in_ns; >+ int tries_taken; >+ >+ DC_LOGGER_INIT(link->ctx->logger); >+ >+ if (link->link_enc->funcs->is_in_alt_mode == NULL) >+ return true; >+ >+ is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc); >+ DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode); >+ >+ if (is_in_alt_mode) >+ return true; >+ >+ enter_timestamp = dm_get_timestamp(link->ctx); >+ >+ for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) { >+ udelay(sleep_time_in_microseconds); >+ /* ask the link if alt mode is enabled, if so return ok */ >+ if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) { >+ >+ finish_timestamp = dm_get_timestamp(link->ctx); >+ time_taken_in_ns = dm_get_elapse_time_in_ns( >+ link->ctx, finish_timestamp, enter_timestamp); >+ DC_LOG_WARNING("Alt mode entered finished after %llu ms\n", >+ div_u64(time_taken_in_ns, 1000000)); >+ return true; >+ } >+ >+ } >+ finish_timestamp = dm_get_timestamp(link->ctx); >+ time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, >+ enter_timestamp); >+ DC_LOG_WARNING("Alt mode has timed out after %llu ms\n", >+ div_u64(time_taken_in_ns, 1000000)); >+ return false; >+} >+ > /** > * dc_link_detect() - Detect if a sink is attached to a given link > * >@@ -772,6 +818,15 @@ > } > > case SIGNAL_TYPE_DISPLAY_PORT: { >+ /* wa HPD high coming too early*/ >+ if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { >+ >+ /* if alt mode times out, return false */ >+ if (wait_for_alt_mode(link) == false) { >+ return false; >+ } >+ } >+ > if (!detect_dp( > link, > &sink_caps, >@@ -795,16 +850,9 @@ > dc_sink_release(prev_sink); > } else { > /* Empty dongle plug in */ >- for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) { >- int fail_count = 0; >- >- dp_verify_link_cap(link, >- &link->reported_link_cap, >- &fail_count); >- >- if (fail_count == 0) >- break; >- } >+ dp_verify_link_cap_with_retries(link, >+ &link->reported_link_cap, >+ LINK_TRAINING_MAX_VERIFY_RETRY); > } > return true; > } >@@ -908,17 +956,9 @@ > */ > > /* deal with non-mst cases */ >- for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) { >- int fail_count = 0; >- >- dp_verify_link_cap(link, >- &link->reported_link_cap, >- &fail_count); >- >- if (fail_count == 0) >- break; >- } >- >+ dp_verify_link_cap_with_retries(link, >+ &link->reported_link_cap, >+ LINK_TRAINING_MAX_VERIFY_RETRY); > } else { > // If edid is the same, then discard new sink and revert back to original sink > if (same_edid) { >@@ -1188,6 +1228,9 @@ > link->ctx = dc_ctx; > link->link_index = init_params->link_index; > >+ memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides)); >+ memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings)); >+ > link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index); > > if (link->link_id.type != OBJECT_TYPE_CONNECTOR) { >@@ -1384,57 +1427,6 @@ > *link = NULL; > } > >-static void dpcd_configure_panel_mode( >- struct dc_link *link, >- enum dp_panel_mode panel_mode) >-{ >- union dpcd_edp_config edp_config_set; >- bool panel_mode_edp = false; >- DC_LOGGER_INIT(link->ctx->logger); >- >- memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config)); >- >- if (DP_PANEL_MODE_DEFAULT != panel_mode) { >- >- switch (panel_mode) { >- case DP_PANEL_MODE_EDP: >- case DP_PANEL_MODE_SPECIAL: >- panel_mode_edp = true; >- break; >- >- default: >- break; >- } >- >- /*set edp panel mode in receiver*/ >- core_link_read_dpcd( >- link, >- DP_EDP_CONFIGURATION_SET, >- &edp_config_set.raw, >- sizeof(edp_config_set.raw)); >- >- if (edp_config_set.bits.PANEL_MODE_EDP >- != panel_mode_edp) { >- enum ddc_result result = DDC_RESULT_UNKNOWN; >- >- edp_config_set.bits.PANEL_MODE_EDP = >- panel_mode_edp; >- result = core_link_write_dpcd( >- link, >- DP_EDP_CONFIGURATION_SET, >- &edp_config_set.raw, >- sizeof(edp_config_set.raw)); >- >- ASSERT(result == DDC_RESULT_SUCESSFULL); >- } >- } >- DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d " >- "eDP panel mode enabled: %d \n", >- link->link_index, >- link->dpcd_caps.panel_mode_edp, >- panel_mode_edp); >-} >- > static void enable_stream_features(struct pipe_ctx *pipe_ctx) > { > struct dc_stream_state *stream = pipe_ctx->stream; >@@ -1466,6 +1458,19 @@ > struct dc_link *link = stream->link; > struct dc_link_settings link_settings = {0}; > enum dp_panel_mode panel_mode; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ bool fec_enable; >+#endif >+ int i; >+ bool apply_seamless_boot_optimization = false; >+ >+ // check for seamless boot >+ for (i = 0; i < state->stream_count; i++) { >+ if (state->streams[i]->apply_seamless_boot_optimization) { >+ apply_seamless_boot_optimization = true; >+ break; >+ } >+ } > > /* get link settings for video mode timing */ > decide_link_settings(stream, &link_settings); >@@ -1487,7 +1492,8 @@ > > pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = > link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; >- state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false); >+ if (!apply_seamless_boot_optimization) >+ state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false); > > dp_enable_link_phy( > link, >@@ -1502,18 +1508,19 @@ > } > > panel_mode = dp_get_panel_mode(link); >- dpcd_configure_panel_mode(link, panel_mode); >+ dp_set_panel_mode(link, panel_mode); > > skip_video_pattern = true; > > if (link_settings.link_rate == LINK_RATE_LOW) > skip_video_pattern = false; > >-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- dp_set_fec_ready(link, true); >-#endif >+ if (link->aux_access_disabled) { >+ dc_link_dp_perform_link_training_skip_aux(link, &link_settings); > >- if (perform_link_training_with_retries( >+ link->cur_link_settings = link_settings; >+ status = DC_OK; >+ } else if (perform_link_training_with_retries( > link, > &link_settings, > skip_video_pattern, >@@ -1525,7 +1532,12 @@ > status = DC_FAIL_DP_LINK_TRAINING; > > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- dp_set_fec_enable(link, true); >+ if (link->preferred_training_settings.fec_enable != NULL) >+ fec_enable = *link->preferred_training_settings.fec_enable; >+ else >+ fec_enable = true; >+ >+ dp_set_fec_enable(link, fec_enable); > #endif > return status; > } >@@ -2755,21 +2767,27 @@ > CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, > COLOR_DEPTH_UNDEFINED); > >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ if (pipe_ctx->stream->timing.flags.DSC) { >+ if (dc_is_dp_signal(pipe_ctx->stream->signal) || >+ dc_is_virtual_signal(pipe_ctx->stream->signal)) >+ dp_set_dsc_enable(pipe_ctx, true); >+ } >+#endif > core_dc->hwss.enable_stream(pipe_ctx); > >- if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) >- allocate_mst_payload(pipe_ctx); >- > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- if (pipe_ctx->stream->timing.flags.DSC && >- (dc_is_dp_signal(pipe_ctx->stream->signal) || >- dc_is_virtual_signal(pipe_ctx->stream->signal))) { >- dp_set_dsc_enable(pipe_ctx, true); >- pipe_ctx->stream_res.tg->funcs->wait_for_state( >- pipe_ctx->stream_res.tg, >- CRTC_STATE_VBLANK); >+ /* Set DPS PPS SDP (AKA "info frames") */ >+ if (pipe_ctx->stream->timing.flags.DSC) { >+ if (dc_is_dp_signal(pipe_ctx->stream->signal) || >+ dc_is_virtual_signal(pipe_ctx->stream->signal)) >+ dp_set_dsc_pps_sdp(pipe_ctx, true); > } > #endif >+ >+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) >+ allocate_mst_payload(pipe_ctx); >+ > core_dc->hwss.unblank_stream(pipe_ctx, > &pipe_ctx->stream->link->cur_link_settings); > >@@ -2786,7 +2804,7 @@ > #endif > } > >-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) >+void core_link_disable_stream(struct pipe_ctx *pipe_ctx) > { > struct dc *core_dc = pipe_ctx->stream->ctx->dc; > struct dc_stream_state *stream = pipe_ctx->stream; >@@ -2821,13 +2839,13 @@ > write_i2c_redriver_setting(pipe_ctx, false); > } > } >- core_dc->hwss.disable_stream(pipe_ctx, option); >+ core_dc->hwss.disable_stream(pipe_ctx); > > disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal); > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- if (pipe_ctx->stream->timing.flags.DSC && >- dc_is_dp_signal(pipe_ctx->stream->signal)) { >- dp_set_dsc_enable(pipe_ctx, false); >+ if (pipe_ctx->stream->timing.flags.DSC) { >+ if (dc_is_dp_signal(pipe_ctx->stream->signal)) >+ dp_set_dsc_enable(pipe_ctx, false); > } > #endif > } >@@ -2836,7 +2854,7 @@ > { > struct dc *core_dc = pipe_ctx->stream->ctx->dc; > >- if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) >+ if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) > return; > > core_dc->hwss.set_avmute(pipe_ctx, enable); >@@ -2999,8 +3017,10 @@ > for (i = 0; i < MAX_PIPES; i++) { > pipe = &dc->current_state->res_ctx.pipe_ctx[i]; > if (pipe->stream && pipe->stream->link) { >- if (pipe->stream->link == link) >+ if (pipe->stream->link == link) { >+ link_stream = pipe->stream; > break; >+ } > } > } > >@@ -3008,20 +3028,40 @@ > if (i == MAX_PIPES) > return; > >- link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream; >- > /* Cannot retrain link if backend is off */ > if (link_stream->dpms_off) > return; > >- if (link_stream) >- decide_link_settings(link_stream, &store_settings); >+ decide_link_settings(link_stream, &store_settings); > > if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) && > (store_settings.link_rate != LINK_RATE_UNKNOWN)) > dp_retrain_link_dp_test(link, &store_settings, false); > } > >+void dc_link_set_preferred_training_settings(struct dc *dc, >+ struct dc_link_settings *link_setting, >+ struct dc_link_training_overrides *lt_overrides, >+ struct dc_link *link, >+ bool skip_immediate_retrain) >+{ >+ if (lt_overrides != NULL) >+ link->preferred_training_settings = *lt_overrides; >+ else >+ memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings)); >+ >+ if (link_setting != NULL) { >+ link->preferred_link_setting = *link_setting; >+ } else { >+ link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN; >+ link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN; >+ } >+ >+ /* Retrain now, or wait until next stream update to apply */ >+ if (skip_immediate_retrain == false) >+ dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link); >+} >+ > void dc_link_enable_hpd(const struct dc_link *link) > { > dc_link_dp_enable_hpd(link); >@@ -3032,7 +3072,6 @@ > dc_link_dp_disable_hpd(link); > } > >- > void dc_link_set_test_pattern(struct dc_link *link, > enum dp_test_pattern test_pattern, > const struct link_training_settings *p_link_settings, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 2019-08-31 15:01:11.858736168 -0500 >@@ -294,7 +294,7 @@ > { > struct dc_link *link = ddc->link; > >- if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 && >+ if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 && > !memcmp(link->dpcd_caps.branch_dev_name, > DP_DVI_CONVERTER_ID_4, > sizeof(link->dpcd_caps.branch_dev_name))) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 2019-08-31 15:01:11.858736168 -0500 >@@ -49,7 +49,7 @@ > struct dc_link_settings link_setting_a, > struct dc_link_settings link_setting_b); > >-static void wait_for_training_aux_rd_interval( >+static uint32_t get_training_aux_rd_interval( > struct dc_link *link, > uint32_t default_wait_in_micro_secs) > { >@@ -68,15 +68,21 @@ > sizeof(training_rd_interval)); > > if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) >- default_wait_in_micro_secs = >- training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000; >+ default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000; > } > >- udelay(default_wait_in_micro_secs); >+ return default_wait_in_micro_secs; >+} >+ >+static void wait_for_training_aux_rd_interval( >+ struct dc_link *link, >+ uint32_t wait_in_micro_secs) >+{ >+ udelay(wait_in_micro_secs); > > DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n", > __func__, >- default_wait_in_micro_secs); >+ wait_in_micro_secs); > } > > static void dpcd_set_training_pattern( >@@ -95,27 +101,27 @@ > dpcd_pattern.v1_4.TRAINING_PATTERN_SET); > } > >-static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link) >+static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link) > { >- enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2; >+ enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2; > struct encoder_feature_support *features = &link->link_enc->features; > struct dpcd_caps *dpcd_caps = &link->dpcd_caps; > > if (features->flags.bits.IS_TPS3_CAPABLE) >- highest_tp = HW_DP_TRAINING_PATTERN_3; >+ highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3; > > if (features->flags.bits.IS_TPS4_CAPABLE) >- highest_tp = HW_DP_TRAINING_PATTERN_4; >+ highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4; > > if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && >- highest_tp >= HW_DP_TRAINING_PATTERN_4) >- return HW_DP_TRAINING_PATTERN_4; >+ highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4) >+ return DP_TRAINING_PATTERN_SEQUENCE_4; > > if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED && >- highest_tp >= HW_DP_TRAINING_PATTERN_3) >- return HW_DP_TRAINING_PATTERN_3; >+ highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3) >+ return DP_TRAINING_PATTERN_SEQUENCE_3; > >- return HW_DP_TRAINING_PATTERN_2; >+ return DP_TRAINING_PATTERN_SEQUENCE_2; > } > > static void dpcd_set_link_settings( >@@ -126,7 +132,7 @@ > > union down_spread_ctrl downspread = { {0} }; > union lane_count_set lane_count_set = { {0} }; >- enum hw_dp_training_pattern hw_tr_pattern; >+ enum dc_dp_training_pattern dp_tr_pattern; > > downspread.raw = (uint8_t) > (lt_settings->link_settings.link_spread); >@@ -134,21 +140,21 @@ > lane_count_set.bits.LANE_COUNT_SET = > lt_settings->link_settings.lane_count; > >- lane_count_set.bits.ENHANCED_FRAMING = 1; >- >+ lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing; > lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0; > >- hw_tr_pattern = get_supported_tp(link); >- if (hw_tr_pattern != HW_DP_TRAINING_PATTERN_4) { >+ dp_tr_pattern = get_supported_tp(link); >+ >+ if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) { > lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = > link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED; > } > > core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, >- &downspread.raw, sizeof(downspread)); >+ &downspread.raw, sizeof(downspread)); > > core_link_write_dpcd(link, DP_LANE_COUNT_SET, >- &lane_count_set.raw, 1); >+ &lane_count_set.raw, 1); > > if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && > lt_settings->link_settings.use_link_rate_set == true) { >@@ -162,46 +168,47 @@ > } > > if (rate) { >- DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n", >+ DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", > __func__, > DP_LINK_BW_SET, > lt_settings->link_settings.link_rate, > DP_LANE_COUNT_SET, > lt_settings->link_settings.lane_count, >+ lt_settings->enhanced_framing, > DP_DOWNSPREAD_CTRL, > lt_settings->link_settings.link_spread); > } else { >- DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x\n %x spread = %x\n", >+ DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n", > __func__, > DP_LINK_RATE_SET, > lt_settings->link_settings.link_rate_set, > DP_LANE_COUNT_SET, > lt_settings->link_settings.lane_count, >+ lt_settings->enhanced_framing, > DP_DOWNSPREAD_CTRL, > lt_settings->link_settings.link_spread); > } >- > } > > static enum dpcd_training_patterns >- hw_training_pattern_to_dpcd_training_pattern( >+ dc_dp_training_pattern_to_dpcd_training_pattern( > struct dc_link *link, >- enum hw_dp_training_pattern pattern) >+ enum dc_dp_training_pattern pattern) > { > enum dpcd_training_patterns dpcd_tr_pattern = > DPCD_TRAINING_PATTERN_VIDEOIDLE; > > switch (pattern) { >- case HW_DP_TRAINING_PATTERN_1: >+ case DP_TRAINING_PATTERN_SEQUENCE_1: > dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1; > break; >- case HW_DP_TRAINING_PATTERN_2: >+ case DP_TRAINING_PATTERN_SEQUENCE_2: > dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2; > break; >- case HW_DP_TRAINING_PATTERN_3: >+ case DP_TRAINING_PATTERN_SEQUENCE_3: > dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3; > break; >- case HW_DP_TRAINING_PATTERN_4: >+ case DP_TRAINING_PATTERN_SEQUENCE_4: > dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4; > break; > default: >@@ -212,13 +219,12 @@ > } > > return dpcd_tr_pattern; >- > } > > static void dpcd_set_lt_pattern_and_lane_settings( > struct dc_link *link, > const struct link_training_settings *lt_settings, >- enum hw_dp_training_pattern pattern) >+ enum dc_dp_training_pattern pattern) > { > union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } }; > const uint32_t dpcd_base_lt_offset = >@@ -233,7 +239,7 @@ > * DpcdAddress_TrainingPatternSet > *****************************************************************/ > dpcd_pattern.v1_4.TRAINING_PATTERN_SET = >- hw_training_pattern_to_dpcd_training_pattern(link, pattern); >+ dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern); > > dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset] > = dpcd_pattern.raw; >@@ -346,12 +352,20 @@ > { > uint32_t lane; > for (lane = 0; lane < src.link_settings.lane_count; lane++) { >- dest->lane_settings[lane].VOLTAGE_SWING = >- src.lane_settings[lane].VOLTAGE_SWING; >- dest->lane_settings[lane].PRE_EMPHASIS = >- src.lane_settings[lane].PRE_EMPHASIS; >- dest->lane_settings[lane].POST_CURSOR2 = >- src.lane_settings[lane].POST_CURSOR2; >+ if (dest->voltage_swing == NULL) >+ dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING; >+ else >+ dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing; >+ >+ if (dest->pre_emphasis == NULL) >+ dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS; >+ else >+ dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis; >+ >+ if (dest->post_cursor2 == NULL) >+ dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2; >+ else >+ dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2; > } > } > >@@ -754,15 +768,15 @@ > struct link_training_settings *lt_settings) > { > struct link_training_settings req_settings; >- enum hw_dp_training_pattern hw_tr_pattern; >+ enum dc_dp_training_pattern tr_pattern; > uint32_t retries_ch_eq; > enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; > union lane_align_status_updated dpcd_lane_status_updated = { {0} }; > union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } }; > >- hw_tr_pattern = get_supported_tp(link); >+ tr_pattern = lt_settings->pattern_for_eq; > >- dp_set_hw_training_pattern(link, hw_tr_pattern); >+ dp_set_hw_training_pattern(link, tr_pattern); > > for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT; > retries_ch_eq++) { >@@ -776,12 +790,12 @@ > dpcd_set_lt_pattern_and_lane_settings( > link, > lt_settings, >- hw_tr_pattern); >+ tr_pattern); > else > dpcd_set_lane_settings(link, lt_settings); > > /* 3. wait for receiver to lock-on*/ >- wait_for_training_aux_rd_interval(link, 400); >+ wait_for_training_aux_rd_interval(link, lt_settings->eq_pattern_time); > > /* 4. Read lane status and requested > * drive settings as set by the sink*/ >@@ -817,27 +831,16 @@ > { > uint32_t retries_cr; > uint32_t retry_count; >- uint32_t lane; > struct link_training_settings req_settings; >- enum dc_lane_count lane_count = >- lt_settings->link_settings.lane_count; >- enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1; >+ enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; >+ enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1; > union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; > union lane_align_status_updated dpcd_lane_status_updated; > > retries_cr = 0; > retry_count = 0; >- /* initial drive setting (VS/PE/PC2)*/ >- for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { >- lt_settings->lane_settings[lane].VOLTAGE_SWING = >- VOLTAGE_SWING_LEVEL0; >- lt_settings->lane_settings[lane].PRE_EMPHASIS = >- PRE_EMPHASIS_DISABLED; >- lt_settings->lane_settings[lane].POST_CURSOR2 = >- POST_CURSOR2_DISABLED; >- } > >- dp_set_hw_training_pattern(link, hw_tr_pattern); >+ dp_set_hw_training_pattern(link, tr_pattern); > > /* najeeb - The synaptics MST hub can put the LT in > * infinite loop by switching the VS >@@ -845,7 +848,7 @@ > /* between level 0 and level 1 continuously, here > * we try for CR lock for LinkTrainingMaxCRRetry count*/ > while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) && >- (retry_count < LINK_TRAINING_MAX_CR_RETRY)) { >+ (retry_count < LINK_TRAINING_MAX_CR_RETRY)) { > > memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status)); > memset(&dpcd_lane_status_updated, '\0', >@@ -863,7 +866,7 @@ > dpcd_set_lt_pattern_and_lane_settings( > link, > lt_settings, >- hw_tr_pattern); >+ tr_pattern); > else > dpcd_set_lane_settings( > link, >@@ -872,7 +875,7 @@ > /* 3. wait receiver to lock-on*/ > wait_for_training_aux_rd_interval( > link, >- 100); >+ lt_settings->cr_pattern_time); > > /* 4. Read lane status and requested drive > * settings as set by the sink >@@ -939,7 +942,7 @@ > * TPS4 must be used instead of POST_LT_ADJ_REQ. > */ > if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 || >- get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4) >+ get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4) > return status; > > if (status == LINK_TRAINING_SUCCESS && >@@ -947,7 +950,7 @@ > status = LINK_TRAINING_LQA_FAIL; > > lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count; >- lane_count_set.bits.ENHANCED_FRAMING = 1; >+ lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing; > lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0; > > core_link_write_dpcd( >@@ -959,24 +962,29 @@ > return status; > } > >-enum link_training_result dc_link_dp_perform_link_training( >- struct dc_link *link, >+static void initialize_training_settings( >+ struct dc_link *link, > const struct dc_link_settings *link_setting, >- bool skip_video_pattern) >+ const struct dc_link_training_overrides *overrides, >+ struct link_training_settings *lt_settings) > { >- enum link_training_result status = LINK_TRAINING_SUCCESS; >+ uint32_t lane; > >- char *link_rate = "Unknown"; >- char *lt_result = "Unknown"; >+ memset(lt_settings, '\0', sizeof(struct link_training_settings)); > >- struct link_training_settings lt_settings; >+ /* Initialize link settings */ >+ lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set; >+ lt_settings->link_settings.link_rate_set = link_setting->link_rate_set; > >- memset(<_settings, '\0', sizeof(lt_settings)); >+ if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) >+ lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate; >+ else >+ lt_settings->link_settings.link_rate = link_setting->link_rate; > >- lt_settings.link_settings.link_rate = link_setting->link_rate; >- lt_settings.link_settings.lane_count = link_setting->lane_count; >- lt_settings.link_settings.use_link_rate_set = link_setting->use_link_rate_set; >- lt_settings.link_settings.link_rate_set = link_setting->link_rate_set; >+ if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN) >+ lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count; >+ else >+ lt_settings->link_settings.lane_count = link_setting->lane_count; > > /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/ > >@@ -987,31 +995,75 @@ > * LINK_SPREAD_05_DOWNSPREAD_30KHZ : > * LINK_SPREAD_DISABLED; > */ >+ /* Initialize link spread */ > if (link->dp_ss_off) >- lt_settings.link_settings.link_spread = LINK_SPREAD_DISABLED; >+ lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED; >+ else if (overrides->downspread != NULL) >+ lt_settings->link_settings.link_spread >+ = *overrides->downspread >+ ? LINK_SPREAD_05_DOWNSPREAD_30KHZ >+ : LINK_SPREAD_DISABLED; > else >- lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ; >+ lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ; > >- /* 1. set link rate, lane count and spread*/ >- dpcd_set_link_settings(link, <_settings); >+ /* Initialize lane settings overrides */ >+ if (overrides->voltage_swing != NULL) >+ lt_settings->voltage_swing = overrides->voltage_swing; > >- /* 2. perform link training (set link training done >- * to false is done as well)*/ >- status = perform_clock_recovery_sequence(link, <_settings); >- if (status == LINK_TRAINING_SUCCESS) { >- status = perform_channel_equalization_sequence(link, >- <_settings); >- } >+ if (overrides->pre_emphasis != NULL) >+ lt_settings->pre_emphasis = overrides->pre_emphasis; > >- if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) { >- status = perform_link_training_int(link, >- <_settings, >- status); >+ if (overrides->post_cursor2 != NULL) >+ lt_settings->post_cursor2 = overrides->post_cursor2; >+ >+ /* Initialize lane settings (VS/PE/PC2) */ >+ for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { >+ lt_settings->lane_settings[lane].VOLTAGE_SWING = >+ lt_settings->voltage_swing != NULL ? >+ *lt_settings->voltage_swing : >+ VOLTAGE_SWING_LEVEL0; >+ lt_settings->lane_settings[lane].PRE_EMPHASIS = >+ lt_settings->pre_emphasis != NULL ? >+ *lt_settings->pre_emphasis >+ : PRE_EMPHASIS_DISABLED; >+ lt_settings->lane_settings[lane].POST_CURSOR2 = >+ lt_settings->post_cursor2 != NULL ? >+ *lt_settings->post_cursor2 >+ : POST_CURSOR2_DISABLED; > } > >- /* 6. print status message*/ >- switch (lt_settings.link_settings.link_rate) { >+ /* Initialize training timings */ >+ if (overrides->cr_pattern_time != NULL) >+ lt_settings->cr_pattern_time = *overrides->cr_pattern_time; >+ else >+ lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100); >+ >+ if (overrides->eq_pattern_time != NULL) >+ lt_settings->eq_pattern_time = *overrides->eq_pattern_time; >+ else >+ lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400); >+ >+ if (overrides->pattern_for_eq != NULL) >+ lt_settings->pattern_for_eq = *overrides->pattern_for_eq; >+ else >+ lt_settings->pattern_for_eq = get_supported_tp(link); >+ >+ if (overrides->enhanced_framing != NULL) >+ lt_settings->enhanced_framing = *overrides->enhanced_framing; >+ else >+ lt_settings->enhanced_framing = 1; >+} > >+static void print_status_message( >+ struct dc_link *link, >+ const struct link_training_settings *lt_settings, >+ enum link_training_result status) >+{ >+ char *link_rate = "Unknown"; >+ char *lt_result = "Unknown"; >+ char *lt_spread = "Disabled"; >+ >+ switch (lt_settings->link_settings.link_rate) { > case LINK_RATE_LOW: > link_rate = "RBR"; > break; >@@ -1057,13 +1109,122 @@ > break; > } > >+ switch (lt_settings->link_settings.link_spread) { >+ case LINK_SPREAD_DISABLED: >+ lt_spread = "Disabled"; >+ break; >+ case LINK_SPREAD_05_DOWNSPREAD_30KHZ: >+ lt_spread = "0.5% 30KHz"; >+ break; >+ case LINK_SPREAD_05_DOWNSPREAD_33KHZ: >+ lt_spread = "0.5% 33KHz"; >+ break; >+ default: >+ break; >+ } >+ > /* Connectivity log: link training */ >- CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d", >- link_rate, >- lt_settings.link_settings.lane_count, >- lt_result, >- lt_settings.lane_settings[0].VOLTAGE_SWING, >- lt_settings.lane_settings[0].PRE_EMPHASIS); >+ CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s", >+ link_rate, >+ lt_settings->link_settings.lane_count, >+ lt_result, >+ lt_settings->lane_settings[0].VOLTAGE_SWING, >+ lt_settings->lane_settings[0].PRE_EMPHASIS, >+ lt_spread); >+} >+ >+bool dc_link_dp_perform_link_training_skip_aux( >+ struct dc_link *link, >+ const struct dc_link_settings *link_setting) >+{ >+ struct link_training_settings lt_settings; >+ enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1; >+ >+ initialize_training_settings( >+ link, >+ link_setting, >+ &link->preferred_training_settings, >+ <_settings); >+ >+ /* 1. Perform_clock_recovery_sequence. */ >+ >+ /* transmit training pattern for clock recovery */ >+ dp_set_hw_training_pattern(link, pattern_for_cr); >+ >+ /* call HWSS to set lane settings*/ >+ dp_set_hw_lane_settings(link, <_settings); >+ >+ /* wait receiver to lock-on*/ >+ wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time); >+ >+ /* 2. Perform_channel_equalization_sequence. */ >+ >+ /* transmit training pattern for channel equalization. */ >+ dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq); >+ >+ /* call HWSS to set lane settings*/ >+ dp_set_hw_lane_settings(link, <_settings); >+ >+ /* wait receiver to lock-on. */ >+ wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time); >+ >+ /* 3. Perform_link_training_int. */ >+ >+ /* Mainlink output idle pattern. */ >+ dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); >+ >+ print_status_message(link, <_settings, LINK_TRAINING_SUCCESS); >+ >+ return true; >+} >+ >+enum link_training_result dc_link_dp_perform_link_training( >+ struct dc_link *link, >+ const struct dc_link_settings *link_setting, >+ bool skip_video_pattern) >+{ >+ enum link_training_result status = LINK_TRAINING_SUCCESS; >+ struct link_training_settings lt_settings; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ bool fec_enable; >+#endif >+ >+ initialize_training_settings( >+ link, >+ link_setting, >+ &link->preferred_training_settings, >+ <_settings); >+ >+ /* 1. set link rate, lane count and spread. */ >+ dpcd_set_link_settings(link, <_settings); >+ >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ if (link->preferred_training_settings.fec_enable != NULL) >+ fec_enable = *link->preferred_training_settings.fec_enable; >+ else >+ fec_enable = true; >+ >+ dp_set_fec_ready(link, fec_enable); >+#endif >+ >+ >+ /* 2. perform link training (set link training done >+ * to false is done as well) >+ */ >+ status = perform_clock_recovery_sequence(link, <_settings); >+ if (status == LINK_TRAINING_SUCCESS) { >+ status = perform_channel_equalization_sequence(link, >+ <_settings); >+ } >+ >+ if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) { >+ status = perform_link_training_int(link, >+ <_settings, >+ status); >+ } >+ >+ /* 6. print status message*/ >+ print_status_message(link, <_settings, status); > > if (status != LINK_TRAINING_SUCCESS) > link->ctx->dc->debug_data.ltFailCount++; >@@ -1071,7 +1232,6 @@ > return status; > } > >- > bool perform_link_training_with_retries( > struct dc_link *link, > const struct dc_link_settings *link_setting, >@@ -1096,6 +1256,146 @@ > return false; > } > >+static enum clock_source_id get_clock_source_id(struct dc_link *link) >+{ >+ enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED; >+ struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; >+ >+ if (dp_cs != NULL) { >+ dp_cs_id = dp_cs->id; >+ } else { >+ /* >+ * dp clock source is not initialized for some reason. >+ * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used >+ */ >+ ASSERT(dp_cs); >+ } >+ >+ return dp_cs_id; >+} >+ >+static void set_dp_mst_mode(struct dc_link *link, bool mst_enable) >+{ >+ if (mst_enable == false && >+ link->type == dc_connection_mst_branch) { >+ /* Disable MST on link. Use only local sink. */ >+ dp_disable_link_phy_mst(link, link->connector_signal); >+ >+ link->type = dc_connection_single; >+ link->local_sink = link->remote_sinks[0]; >+ link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT; >+ } else if (mst_enable == true && >+ link->type == dc_connection_single && >+ link->remote_sinks[0] != NULL) { >+ /* Re-enable MST on link. */ >+ dp_disable_link_phy(link, link->connector_signal); >+ dp_enable_mst_on_sink(link, true); >+ >+ link->type = dc_connection_mst_branch; >+ link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST; >+ } >+} >+ >+bool dc_link_dp_sync_lt_begin(struct dc_link *link) >+{ >+ /* Begin Sync LT. During this time, >+ * DPCD:600h must not be powered down. >+ */ >+ link->sync_lt_in_progress = true; >+ >+ /*Clear any existing preferred settings.*/ >+ memset(&link->preferred_training_settings, 0, >+ sizeof(struct dc_link_training_overrides)); >+ memset(&link->preferred_link_setting, 0, >+ sizeof(struct dc_link_settings)); >+ >+ return true; >+} >+ >+enum link_training_result dc_link_dp_sync_lt_attempt( >+ struct dc_link *link, >+ struct dc_link_settings *link_settings, >+ struct dc_link_training_overrides *lt_overrides) >+{ >+ struct link_training_settings lt_settings; >+ enum link_training_result lt_status = LINK_TRAINING_SUCCESS; >+ enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT; >+ enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ bool fec_enable = false; >+#endif >+ >+ initialize_training_settings( >+ link, >+ link_settings, >+ lt_overrides, >+ <_settings); >+ >+ /* Setup MST Mode */ >+ if (lt_overrides->mst_enable) >+ set_dp_mst_mode(link, *lt_overrides->mst_enable); >+ >+ /* Disable link */ >+ dp_disable_link_phy(link, link->connector_signal); >+ >+ /* Enable link */ >+ dp_cs_id = get_clock_source_id(link); >+ dp_enable_link_phy(link, link->connector_signal, >+ dp_cs_id, link_settings); >+ >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ /* Set FEC enable */ >+ fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable; >+ dp_set_fec_ready(link, fec_enable); >+#endif >+ >+ if (lt_overrides->alternate_scrambler_reset) { >+ if (*lt_overrides->alternate_scrambler_reset) >+ panel_mode = DP_PANEL_MODE_EDP; >+ else >+ panel_mode = DP_PANEL_MODE_DEFAULT; >+ } else >+ panel_mode = dp_get_panel_mode(link); >+ >+ dp_set_panel_mode(link, panel_mode); >+ >+ /* Attempt to train with given link training settings */ >+ >+ /* Set link rate, lane count and spread. */ >+ dpcd_set_link_settings(link, <_settings); >+ >+ /* 2. perform link training (set link training done >+ * to false is done as well) >+ */ >+ lt_status = perform_clock_recovery_sequence(link, <_settings); >+ if (lt_status == LINK_TRAINING_SUCCESS) { >+ lt_status = perform_channel_equalization_sequence(link, >+ <_settings); >+ } >+ >+ /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/ >+ /* 4. print status message*/ >+ print_status_message(link, <_settings, lt_status); >+ >+ return lt_status; >+} >+ >+bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down) >+{ >+ /* If input parameter is set, shut down phy. >+ * Still shouldn't turn off dp_receiver (DPCD:600h) >+ */ >+ if (link_down == true) { >+ dp_disable_link_phy(link, link->connector_signal); >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ dp_set_fec_ready(link, false); >+#endif >+ } >+ >+ link->sync_lt_in_progress = false; >+ return true; >+} >+ > static struct dc_link_settings get_max_link_cap(struct dc_link *link) > { > /* Set Default link settings */ >@@ -1250,7 +1550,6 @@ > bool success; > bool skip_link_training; > bool skip_video_pattern; >- struct clock_source *dp_cs; > enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL; > enum link_training_result status; > union hpd_irq_data irq_data; >@@ -1274,17 +1573,7 @@ > /* disable PHY done possible by BIOS, will be done by driver itself */ > dp_disable_link_phy(link, link->connector_signal); > >- dp_cs = link->dc->res_pool->dp_clock_source; >- >- if (dp_cs) >- dp_cs_id = dp_cs->id; >- else { >- /* >- * dp clock source is not initialized for some reason. >- * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used >- */ >- ASSERT(dp_cs); >- } >+ dp_cs_id = get_clock_source_id(link); > > /* link training starts with the maximum common settings > * supported by both sink and ASIC. >@@ -1354,6 +1643,33 @@ > return success; > } > >+bool dp_verify_link_cap_with_retries( >+ struct dc_link *link, >+ struct dc_link_settings *known_limit_link_setting, >+ int attempts) >+{ >+ uint8_t i = 0; >+ bool success = false; >+ >+ for (i = 0; i < attempts; i++) { >+ int fail_count = 0; >+ enum dc_connection_type type; >+ >+ memset(&link->verified_link_cap, 0, >+ sizeof(struct dc_link_settings)); >+ if (!dc_link_detect_sink(link, &type)) { >+ break; >+ } else if (dp_verify_link_cap(link, >+ &link->reported_link_cap, >+ &fail_count) && fail_count == 0) { >+ success = true; >+ break; >+ } >+ msleep(10); >+ } >+ return success; >+} >+ > static struct dc_link_settings get_common_supported_link_settings( > struct dc_link_settings link_setting_a, > struct dc_link_settings link_setting_b) >@@ -2156,6 +2472,11 @@ > union dpcd_rev rev; > union mstm_cap cap; > >+ if (link->preferred_training_settings.mst_enable && >+ *link->preferred_training_settings.mst_enable == false) { >+ return false; >+ } >+ > rev.raw = 0; > cap.raw = 0; > >@@ -2363,13 +2684,13 @@ > > if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) { > switch (link->dpcd_caps.branch_dev_id) { >- /* Some active dongles (DP-VGA, DP-DLDVI converters) power down >+ /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down > * all internal circuits including AUX communication preventing > * reading DPCD table and EDID (spec violation). > * Encoder will skip DP RX power down on disable_output to > * keep receiver powered all the time.*/ >- case DP_BRANCH_DEVICE_ID_1: >- case DP_BRANCH_DEVICE_ID_4: >+ case DP_BRANCH_DEVICE_ID_0010FA: >+ case DP_BRANCH_DEVICE_ID_0080E1: > link->wa_flags.dp_keep_receiver_powered = true; > break; > >@@ -2774,14 +3095,19 @@ > controller_test_pattern, color_depth); > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > else if (opp->funcs->opp_set_disp_pattern_generator) { >- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >+ struct pipe_ctx *odm_pipe; >+ int opp_cnt = 1; > >- if (bot_odm_pipe) { >- struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp; >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) >+ opp_cnt++; > >- bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, ¶ms); >- width /= 2; >- bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp, >+ width /= opp_cnt; >+ >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { >+ struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; >+ >+ odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms); >+ odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp, > controller_test_pattern, > color_depth, > NULL, >@@ -2810,14 +3136,18 @@ > color_depth); > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > else if (opp->funcs->opp_set_disp_pattern_generator) { >- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >+ struct pipe_ctx *odm_pipe; >+ int opp_cnt = 1; > >- if (bot_odm_pipe) { >- struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp; >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) >+ opp_cnt++; > >- bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, ¶ms); >- width /= 2; >- bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp, >+ width /= opp_cnt; >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { >+ struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; >+ >+ odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms); >+ odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp, > CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, > color_depth, > NULL, >@@ -2858,7 +3188,7 @@ > memset(&training_pattern, 0, sizeof(training_pattern)); > > for (i = 0; i < MAX_PIPES; i++) { >- if (pipes[i].stream->link == link) { >+ if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) { > pipe_ctx = &pipes[i]; > break; > } >@@ -3007,6 +3337,105 @@ > core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); > } > >+void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) >+{ >+ union dpcd_edp_config edp_config_set; >+ bool panel_mode_edp = false; >+ >+ memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config)); >+ >+ if (panel_mode != DP_PANEL_MODE_DEFAULT) { >+ >+ switch (panel_mode) { >+ case DP_PANEL_MODE_EDP: >+ case DP_PANEL_MODE_SPECIAL: >+ panel_mode_edp = true; >+ break; >+ >+ default: >+ break; >+ } >+ >+ /*set edp panel mode in receiver*/ >+ core_link_read_dpcd( >+ link, >+ DP_EDP_CONFIGURATION_SET, >+ &edp_config_set.raw, >+ sizeof(edp_config_set.raw)); >+ >+ if (edp_config_set.bits.PANEL_MODE_EDP >+ != panel_mode_edp) { >+ enum ddc_result result = DDC_RESULT_UNKNOWN; >+ >+ edp_config_set.bits.PANEL_MODE_EDP = >+ panel_mode_edp; >+ result = core_link_write_dpcd( >+ link, >+ DP_EDP_CONFIGURATION_SET, >+ &edp_config_set.raw, >+ sizeof(edp_config_set.raw)); >+ >+ ASSERT(result == DDC_RESULT_SUCESSFULL); >+ } >+ } >+ DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d " >+ "eDP panel mode enabled: %d \n", >+ link->link_index, >+ link->dpcd_caps.panel_mode_edp, >+ panel_mode_edp); >+} >+ >+enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) >+{ >+ /* We need to explicitly check that connector >+ * is not DP. Some Travis_VGA get reported >+ * by video bios as DP. >+ */ >+ if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { >+ >+ switch (link->dpcd_caps.branch_dev_id) { >+ case DP_BRANCH_DEVICE_ID_0022B9: >+ /* alternate scrambler reset is required for Travis >+ * for the case when external chip does not >+ * provide sink device id, alternate scrambler >+ * scheme will be overriden later by querying >+ * Encoder features >+ */ >+ if (strncmp( >+ link->dpcd_caps.branch_dev_name, >+ DP_VGA_LVDS_CONVERTER_ID_2, >+ sizeof( >+ link->dpcd_caps. >+ branch_dev_name)) == 0) { >+ return DP_PANEL_MODE_SPECIAL; >+ } >+ break; >+ case DP_BRANCH_DEVICE_ID_00001A: >+ /* alternate scrambler reset is required for Travis >+ * for the case when external chip does not provide >+ * sink device id, alternate scrambler scheme will >+ * be overriden later by querying Encoder feature >+ */ >+ if (strncmp(link->dpcd_caps.branch_dev_name, >+ DP_VGA_LVDS_CONVERTER_ID_3, >+ sizeof( >+ link->dpcd_caps. >+ branch_dev_name)) == 0) { >+ return DP_PANEL_MODE_SPECIAL; >+ } >+ break; >+ default: >+ break; >+ } >+ } >+ >+ if (link->dpcd_caps.panel_mode_edp) { >+ return DP_PANEL_MODE_EDP; >+ } >+ >+ return DP_PANEL_MODE_DEFAULT; >+} >+ > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > void dp_set_fec_ready(struct dc_link *link, bool ready) > { >@@ -3024,7 +3453,7 @@ > > if (link_enc->funcs->fec_set_ready && > link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { >- if (link->fec_state == dc_link_fec_not_ready && ready) { >+ if (ready) { > fec_config = 1; > if (core_link_write_dpcd(link, > DP_FEC_CONFIGURATION, >@@ -3033,9 +3462,11 @@ > link_enc->funcs->fec_set_ready(link_enc, true); > link->fec_state = dc_link_fec_ready; > } else { >+ link->link_enc->funcs->fec_set_ready(link->link_enc, false); >+ link->fec_state = dc_link_fec_not_ready; > dm_error("dpcd write failed to set fec_ready"); > } >- } else if (link->fec_state == dc_link_fec_ready && !ready) { >+ } else if (link->fec_state == dc_link_fec_ready) { > fec_config = 0; > core_link_write_dpcd(link, > DP_FEC_CONFIGURATION, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 2019-08-31 15:01:11.858736168 -0500 >@@ -25,10 +25,11 @@ > uint8_t *data, > uint32_t size) > { >- if (!dm_helpers_dp_read_dpcd(link->ctx, >- link, >- address, data, size)) >- return DC_ERROR_UNEXPECTED; >+ if (!link->aux_access_disabled && >+ !dm_helpers_dp_read_dpcd(link->ctx, >+ link, address, data, size)) { >+ return DC_ERROR_UNEXPECTED; >+ } > > return DC_OK; > } >@@ -39,10 +40,11 @@ > const uint8_t *data, > uint32_t size) > { >- if (!dm_helpers_dp_write_dpcd(link->ctx, >- link, >- address, data, size)) >- return DC_ERROR_UNEXPECTED; >+ if (!link->aux_access_disabled && >+ !dm_helpers_dp_write_dpcd(link->ctx, >+ link, address, data, size)) { >+ return DC_ERROR_UNEXPECTED; >+ } > > return DC_OK; > } >@@ -53,6 +55,9 @@ > > state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3; > >+ if (link->sync_lt_in_progress) >+ return; >+ > core_link_write_dpcd(link, DP_SET_POWER, &state, > sizeof(state)); > } >@@ -160,6 +165,10 @@ > break; > udelay(25); //MAx T7 is 50ms > } while (++tries < 300); >+ >+ if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0) >+ udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000); >+ > return result; > } > >@@ -203,21 +212,21 @@ > > bool dp_set_hw_training_pattern( > struct dc_link *link, >- enum hw_dp_training_pattern pattern) >+ enum dc_dp_training_pattern pattern) > { > enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; > > switch (pattern) { >- case HW_DP_TRAINING_PATTERN_1: >+ case DP_TRAINING_PATTERN_SEQUENCE_1: > test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1; > break; >- case HW_DP_TRAINING_PATTERN_2: >+ case DP_TRAINING_PATTERN_SEQUENCE_2: > test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2; > break; >- case HW_DP_TRAINING_PATTERN_3: >+ case DP_TRAINING_PATTERN_SEQUENCE_3: > test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3; > break; >- case HW_DP_TRAINING_PATTERN_4: >+ case DP_TRAINING_PATTERN_SEQUENCE_4: > test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4; > break; > default: >@@ -239,46 +248,6 @@ > encoder->funcs->dp_set_lane_settings(encoder, link_settings); > } > >-enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) >-{ >- /* We need to explicitly check that connector >- * is not DP. Some Travis_VGA get reported >- * by video bios as DP. >- */ >- if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { >- >- switch (link->dpcd_caps.branch_dev_id) { >- case DP_BRANCH_DEVICE_ID_2: >- if (strncmp( >- link->dpcd_caps.branch_dev_name, >- DP_VGA_LVDS_CONVERTER_ID_2, >- sizeof( >- link->dpcd_caps. >- branch_dev_name)) == 0) { >- return DP_PANEL_MODE_SPECIAL; >- } >- break; >- case DP_BRANCH_DEVICE_ID_3: >- if (strncmp(link->dpcd_caps.branch_dev_name, >- DP_VGA_LVDS_CONVERTER_ID_3, >- sizeof( >- link->dpcd_caps. >- branch_dev_name)) == 0) { >- return DP_PANEL_MODE_SPECIAL; >- } >- break; >- default: >- break; >- } >- } >- >- if (link->dpcd_caps.panel_mode_edp) { >- return DP_PANEL_MODE_EDP; >- } >- >- return DP_PANEL_MODE_DEFAULT; >-} >- > void dp_set_hw_test_pattern( > struct dc_link *link, > enum dp_test_pattern test_pattern, >@@ -306,7 +275,7 @@ > > for (i = 0; i < MAX_PIPES; i++) { > if (pipes[i].stream != NULL && >- !pipes[i].top_pipe && >+ !pipes[i].top_pipe && !pipes[i].prev_odm_pipe && > pipes[i].stream->link != NULL && > pipes[i].stream_res.stream_enc != NULL) { > udelay(100); >@@ -320,7 +289,9 @@ > > dp_receiver_power_ctrl(link, false); > >- link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE); >+ link->dc->hwss.disable_stream(&pipes[i]); >+ if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only) >+ (&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio); > > link->link_enc->funcs->disable_output( > link->link_enc, >@@ -373,10 +344,22 @@ > static void dsc_optc_config_log(struct display_stream_compressor *dsc, > struct dsc_optc_config *config) > { >- DC_LOG_DSC("Setting optc DSC config at DSC inst %d", dsc->inst); >- DC_LOG_DSC("\n\tbytes_per_pixel %d\n\tis_pixel_format_444 %d\n\tslice_width %d", >- config->bytes_per_pixel, >- config->is_pixel_format_444, config->slice_width); >+ uint32_t precision = 1 << 28; >+ uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; >+ uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; >+ uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; >+ >+ /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC >+ * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is >+ * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal >+ */ >+ ll_bytes_per_pix_fraq *= 10000000; >+ ll_bytes_per_pix_fraq /= precision; >+ >+ DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", >+ config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); >+ DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); >+ DC_LOG_DSC("\tslice_width %d", config->slice_width); > } > > static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) >@@ -392,55 +375,62 @@ > return result; > } > >-/* This has to be done after DSC was enabled on RX first, i.e. after dp_enable_dsc_on_rx() had been called >+/* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, >+ * i.e. after dp_enable_dsc_on_rx() had been called > */ >-static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) >+void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) > { > struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; > struct dc *core_dc = pipe_ctx->stream->ctx->dc; > struct dc_stream_state *stream = pipe_ctx->stream; >- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >+ struct pipe_ctx *odm_pipe; >+ int opp_cnt = 1; >+ >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) >+ opp_cnt++; > > if (enable) { >- /* TODO proper function */ > struct dsc_config dsc_cfg; > struct dsc_optc_config dsc_optc_cfg; > enum optc_dsc_mode optc_dsc_mode; >- uint8_t dsc_packed_pps[128]; > > /* Enable DSC hw block */ >- dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; >+ dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; > dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; > dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; > dsc_cfg.color_depth = stream->timing.display_color_depth; > dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; >+ ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); >+ dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; > >- dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps[0]); >- if (odm_pipe) { >- struct display_stream_compressor *bot_dsc = odm_pipe->stream_res.dsc; >- uint8_t dsc_packed_pps_odm[128]; >- >- dsc_cfg.pic_width /= 2; >- ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % 2 == 0); >- dsc_cfg.dc_dsc_cfg.num_slices_h /= 2; >- dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps_odm[0]); >- bot_dsc->funcs->dsc_set_config(bot_dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps_odm[0]); >- bot_dsc->funcs->dsc_enable(bot_dsc, odm_pipe->stream_res.opp->inst); >- } >+ dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); > dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { >+ struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; >+ >+ odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); >+ odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); >+ } >+ dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; >+ dsc_cfg.pic_width *= opp_cnt; > > optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; > >- dsc_optc_config_log(dsc, &dsc_optc_cfg); > /* Enable DSC in encoder */ >- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) && pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) >+ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { >+ DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); >+ dsc_optc_config_log(dsc, &dsc_optc_cfg); > pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, > optc_dsc_mode, > dsc_optc_cfg.bytes_per_pixel, >- dsc_optc_cfg.slice_width, >- &dsc_packed_pps[0]); >+ dsc_optc_cfg.slice_width); >+ >+ /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ >+ } > > /* Enable DSC in OPTC */ >+ DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); >+ dsc_optc_config_log(dsc, &dsc_optc_cfg); > pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, > optc_dsc_mode, > dsc_optc_cfg.bytes_per_pixel, >@@ -452,15 +442,18 @@ > OPTC_DSC_DISABLED, 0, 0); > > /* disable DSC in stream encoder */ >- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { >+ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { > pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( > pipe_ctx->stream_res.stream_enc, >- OPTC_DSC_DISABLED, 0, 0, NULL); >+ OPTC_DSC_DISABLED, 0, 0); >+ >+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( >+ pipe_ctx->stream_res.stream_enc, false, NULL); > } > > /* disable DSC block */ > pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); >- if (odm_pipe) >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) > odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); > } > } >@@ -489,6 +482,47 @@ > return result; > } > >+bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable) >+{ >+ struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; >+ struct dc *core_dc = pipe_ctx->stream->ctx->dc; >+ struct dc_stream_state *stream = pipe_ctx->stream; >+ >+ if (!pipe_ctx->stream->timing.flags.DSC || !dsc) >+ return false; >+ >+ if (enable) { >+ struct dsc_config dsc_cfg; >+ uint8_t dsc_packed_pps[128]; >+ >+ /* Enable DSC hw block */ >+ dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; >+ dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; >+ dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; >+ dsc_cfg.color_depth = stream->timing.display_color_depth; >+ dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; >+ >+ DC_LOG_DSC(" "); >+ dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); >+ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { >+ DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); >+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( >+ pipe_ctx->stream_res.stream_enc, >+ true, >+ &dsc_packed_pps[0]); >+ } >+ } else { >+ /* disable DSC PPS in stream encoder */ >+ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { >+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( >+ pipe_ctx->stream_res.stream_enc, false, NULL); >+ } >+ } >+ >+ return true; >+} >+ >+ > bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx) > { > struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; >@@ -499,8 +533,8 @@ > return false; > > dp_set_dsc_on_stream(pipe_ctx, true); >+ dp_set_dsc_pps_sdp(pipe_ctx, true); > return true; > } >- > #endif > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 2019-08-31 15:01:11.859736168 -0500 >@@ -52,6 +52,9 @@ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #include "dcn20/dcn20_resource.h" > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#include "dcn21/dcn21_resource.h" >+#endif > #include "dce120/dce120_resource.h" > > #define DC_LOGGER_INIT(logger) >@@ -101,6 +104,10 @@ > dc_version = DCN_VERSION_1_0; > if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) > dc_version = DCN_VERSION_1_01; >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) >+ dc_version = DCN_VERSION_2_1; >+#endif > break; > #endif > >@@ -168,17 +175,20 @@ > res_pool = dcn20_create_resource_pool(init_data, dc); > break; > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ case DCN_VERSION_2_1: >+ res_pool = dcn21_create_resource_pool(init_data, dc); >+ break; >+#endif > > default: > break; > } >- if (res_pool != NULL) { >- struct dc_firmware_info fw_info = { { 0 } }; > >- if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios, >- &fw_info) == BP_RESULT_OK) { >+ if (res_pool != NULL) { >+ if (dc->ctx->dc_bios->fw_info_valid) { > res_pool->ref_clocks.xtalin_clock_inKhz = >- fw_info.pll_info.crystal_frequency; >+ dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; > /* initialize with firmware data first, no all > * ASIC have DCCG SW component. FPGA or > * simulation need initialization of >@@ -265,12 +275,10 @@ > DC_ERR("DC: failed to create audio!\n"); > return false; > } >- > if (!aud->funcs->endpoint_valid(aud)) { > aud->funcs->destroy(&aud); > break; > } >- > pool->audios[i] = aud; > pool->audio_count++; > } >@@ -940,7 +948,14 @@ > data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c); > > } >+static bool are_rect_integer_multiples(struct rect src, struct rect dest) >+{ >+ if (dest.width >= src.width && dest.width % src.width == 0 && >+ dest.height >= src.height && dest.height % src.height == 0) >+ return true; > >+ return false; >+} > bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) > { > const struct dc_plane_state *plane_state = pipe_ctx->plane_state; >@@ -983,6 +998,15 @@ > if (pipe_ctx->plane_res.dpp != NULL) > res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( > pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); >+ >+ if (res && >+ plane_state->scaling_quality.integer_scaling && >+ are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport, >+ pipe_ctx->plane_res.scl_data.recout)) { >+ pipe_ctx->plane_res.scl_data.taps.v_taps = 1; >+ pipe_ctx->plane_res.scl_data.taps.h_taps = 1; >+ } >+ > if (!res) { > /* Try 24 bpp linebuffer */ > pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; >@@ -1103,25 +1127,21 @@ > struct dc_stream_state *stream) > { > int i; >+ > for (i = 0; i < MAX_PIPES; i++) { >- if (res_ctx->pipe_ctx[i].stream == stream && >- !res_ctx->pipe_ctx[i].top_pipe) { >+ if (res_ctx->pipe_ctx[i].stream == stream >+ && !res_ctx->pipe_ctx[i].top_pipe >+ && !res_ctx->pipe_ctx[i].prev_odm_pipe) > return &res_ctx->pipe_ctx[i]; >- break; >- } > } > return NULL; > } > >-static struct pipe_ctx *resource_get_tail_pipe_for_stream( >+static struct pipe_ctx *resource_get_tail_pipe( > struct resource_context *res_ctx, >- struct dc_stream_state *stream) >+ struct pipe_ctx *head_pipe) > { >- struct pipe_ctx *head_pipe, *tail_pipe; >- head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); >- >- if (!head_pipe) >- return NULL; >+ struct pipe_ctx *tail_pipe; > > tail_pipe = head_pipe->bottom_pipe; > >@@ -1137,31 +1157,20 @@ > * A free_pipe for a stream is defined here as a pipe > * that has no surface attached yet > */ >-static struct pipe_ctx *acquire_free_pipe_for_stream( >+static struct pipe_ctx *acquire_free_pipe_for_head( > struct dc_state *context, > const struct resource_pool *pool, >- struct dc_stream_state *stream) >+ struct pipe_ctx *head_pipe) > { > int i; > struct resource_context *res_ctx = &context->res_ctx; > >- struct pipe_ctx *head_pipe = NULL; >- >- /* Find head pipe, which has the back end set up*/ >- >- head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); >- >- if (!head_pipe) { >- ASSERT(0); >- return NULL; >- } >- > if (!head_pipe->plane_state) > return head_pipe; > > /* Re-use pipe already acquired for this stream if available*/ > for (i = pool->pipe_count - 1; i >= 0; i--) { >- if (res_ctx->pipe_ctx[i].stream == stream && >+ if (res_ctx->pipe_ctx[i].stream == head_pipe->stream && > !res_ctx->pipe_ctx[i].plane_state) { > return &res_ctx->pipe_ctx[i]; > } >@@ -1175,8 +1184,7 @@ > if (!pool->funcs->acquire_idle_pipe_for_layer) > return NULL; > >- return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream); >- >+ return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream); > } > > #if defined(CONFIG_DRM_AMD_DC_DCN1_0) >@@ -1190,7 +1198,7 @@ > for (i = 0; i < pool->pipe_count; i++) { > struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; > >- if (split_pipe->top_pipe && !dc_res_is_odm_head_pipe(split_pipe) && >+ if (split_pipe->top_pipe && > split_pipe->top_pipe->plane_state == split_pipe->plane_state) { > split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; > if (split_pipe->bottom_pipe) >@@ -1251,39 +1259,41 @@ > return false; > } > >- tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream); >- ASSERT(tail_pipe); >- >- free_pipe = acquire_free_pipe_for_stream(context, pool, stream); >+ /* retain new surface, but only once per stream */ >+ dc_plane_state_retain(plane_state); > >-#if defined(CONFIG_DRM_AMD_DC_DCN1_0) >- if (!free_pipe) { >- int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); >- if (pipe_idx >= 0) >- free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; >- } >-#endif >- if (!free_pipe) >- return false; >+ while (head_pipe) { >+ tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe); >+ ASSERT(tail_pipe); >+ >+ free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe); >+ >+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) >+ if (!free_pipe) { >+ int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); >+ if (pipe_idx >= 0) >+ free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; >+ } >+ #endif >+ if (!free_pipe) { >+ dc_plane_state_release(plane_state); >+ return false; >+ } > >- /* retain new surfaces */ >- dc_plane_state_retain(plane_state); >- free_pipe->plane_state = plane_state; >+ free_pipe->plane_state = plane_state; > >- if (head_pipe != free_pipe) { >- free_pipe->stream_res.tg = tail_pipe->stream_res.tg; >- free_pipe->stream_res.abm = tail_pipe->stream_res.abm; >- free_pipe->stream_res.opp = tail_pipe->stream_res.opp; >- free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; >- free_pipe->stream_res.audio = tail_pipe->stream_res.audio; >- free_pipe->clock_source = tail_pipe->clock_source; >- free_pipe->top_pipe = tail_pipe; >- tail_pipe->bottom_pipe = free_pipe; >- } else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) { >- ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp); >- free_pipe->bottom_pipe->plane_state = plane_state; >+ if (head_pipe != free_pipe) { >+ free_pipe->stream_res.tg = tail_pipe->stream_res.tg; >+ free_pipe->stream_res.abm = tail_pipe->stream_res.abm; >+ free_pipe->stream_res.opp = tail_pipe->stream_res.opp; >+ free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; >+ free_pipe->stream_res.audio = tail_pipe->stream_res.audio; >+ free_pipe->clock_source = tail_pipe->clock_source; >+ free_pipe->top_pipe = tail_pipe; >+ tail_pipe->bottom_pipe = free_pipe; >+ } >+ head_pipe = head_pipe->next_odm_pipe; > } >- > /* assign new surfaces*/ > stream_status->plane_states[stream_status->plane_count] = plane_state; > >@@ -1292,35 +1302,6 @@ > return true; > } > >-struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx) >-{ >- struct pipe_ctx *bottom_pipe = pipe_ctx->bottom_pipe; >- >- /* ODM should only be updated once per otg */ >- if (pipe_ctx->top_pipe) >- return NULL; >- >- while (bottom_pipe) { >- if (bottom_pipe->stream_res.opp != pipe_ctx->stream_res.opp) >- break; >- bottom_pipe = bottom_pipe->bottom_pipe; >- } >- >- return bottom_pipe; >-} >- >-bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx) >-{ >- struct pipe_ctx *top_pipe = pipe_ctx->top_pipe; >- >- if (!top_pipe) >- return false; >- if (top_pipe && top_pipe->stream_res.opp == pipe_ctx->stream_res.opp) >- return false; >- >- return true; >-} >- > bool dc_remove_plane_from_context( > const struct dc *dc, > struct dc_stream_state *stream, >@@ -1347,12 +1328,6 @@ > struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; > > if (pipe_ctx->plane_state == plane_state) { >- if (dc_res_is_odm_head_pipe(pipe_ctx)) { >- pipe_ctx->plane_state = NULL; >- pipe_ctx->bottom_pipe = NULL; >- continue; >- } >- > if (pipe_ctx->top_pipe) > pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; > >@@ -1367,13 +1342,10 @@ > * For head pipe detach surfaces from pipe for tail > * pipe just zero it out > */ >- if (!pipe_ctx->top_pipe) { >+ if (!pipe_ctx->top_pipe) > pipe_ctx->plane_state = NULL; >- if (!dc_res_get_odm_bottom_pipe(pipe_ctx)) >- pipe_ctx->bottom_pipe = NULL; >- } else { >+ else > memset(pipe_ctx, 0, sizeof(*pipe_ctx)); >- } > } > } > >@@ -1659,24 +1631,25 @@ > const struct resource_pool *pool, > enum engine_id id) > { >- int i; >- for (i = 0; i < pool->audio_count; i++) { >+ int i, available_audio_count; >+ >+ available_audio_count = pool->audio_count; >+ >+ for (i = 0; i < available_audio_count; i++) { > if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { > /*we have enough audio endpoint, find the matching inst*/ > if (id != i) > continue; >- > return pool->audios[i]; > } > } > >- /* use engine id to find free audio */ >- if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) { >+ /* use engine id to find free audio */ >+ if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) { > return pool->audios[id]; > } >- > /*not found the matching one, first come first serve*/ >- for (i = 0; i < pool->audio_count; i++) { >+ for (i = 0; i < available_audio_count; i++) { > if (res_ctx->is_audio_acquired[i] == false) { > return pool->audios[i]; > } >@@ -1736,51 +1709,46 @@ > { > int i; > struct dc_context *dc_ctx = dc->ctx; >- struct pipe_ctx *del_pipe = NULL; >- >- /* Release primary pipe */ >- for (i = 0; i < MAX_PIPES; i++) { >- if (new_ctx->res_ctx.pipe_ctx[i].stream == stream && >- !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { >- struct pipe_ctx *odm_pipe = >- dc_res_get_odm_bottom_pipe(&new_ctx->res_ctx.pipe_ctx[i]); >- >- del_pipe = &new_ctx->res_ctx.pipe_ctx[i]; >- >- ASSERT(del_pipe->stream_res.stream_enc); >- update_stream_engine_usage( >- &new_ctx->res_ctx, >- dc->res_pool, >- del_pipe->stream_res.stream_enc, >- false); >- >- if (del_pipe->stream_res.audio) >- update_audio_usage( >- &new_ctx->res_ctx, >- dc->res_pool, >- del_pipe->stream_res.audio, >- false); >- >- resource_unreference_clock_source(&new_ctx->res_ctx, >- dc->res_pool, >- del_pipe->clock_source); >- >- if (dc->res_pool->funcs->remove_stream_from_ctx) >- dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); >- >- memset(del_pipe, 0, sizeof(*del_pipe)); >- if (odm_pipe) >- memset(odm_pipe, 0, sizeof(*odm_pipe)); >- >- break; >- } >- } >+ struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream); >+ struct pipe_ctx *odm_pipe; > > if (!del_pipe) { > DC_ERROR("Pipe not found for stream %p !\n", stream); > return DC_ERROR_UNEXPECTED; > } > >+ odm_pipe = del_pipe->next_odm_pipe; >+ >+ /* Release primary pipe */ >+ ASSERT(del_pipe->stream_res.stream_enc); >+ update_stream_engine_usage( >+ &new_ctx->res_ctx, >+ dc->res_pool, >+ del_pipe->stream_res.stream_enc, >+ false); >+ >+ if (del_pipe->stream_res.audio) >+ update_audio_usage( >+ &new_ctx->res_ctx, >+ dc->res_pool, >+ del_pipe->stream_res.audio, >+ false); >+ >+ resource_unreference_clock_source(&new_ctx->res_ctx, >+ dc->res_pool, >+ del_pipe->clock_source); >+ >+ if (dc->res_pool->funcs->remove_stream_from_ctx) >+ dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); >+ >+ while (odm_pipe) { >+ struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; >+ >+ memset(odm_pipe, 0, sizeof(*odm_pipe)); >+ odm_pipe = next_odm_pipe; >+ } >+ memset(del_pipe, 0, sizeof(*del_pipe)); >+ > for (i = 0; i < new_ctx->stream_count; i++) > if (new_ctx->streams[i] == stream) > break; >@@ -1880,7 +1848,7 @@ > struct dc_stream_state *stream) > { > struct dc_link *link = stream->link; >- unsigned int inst; >+ unsigned int inst, tg_inst; > > /* Check for enabled DIG to identify enabled display */ > if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) >@@ -1892,28 +1860,37 @@ > * current implementation always map 1-to-1, so this code makes > * the same assumption and doesn't check OTG source. > */ >- inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1; >+ inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); > > /* Instance should be within the range of the pool */ > if (inst >= pool->pipe_count) > return -1; > >- if (!res_ctx->pipe_ctx[inst].stream) { >- struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst]; >+ if (inst >= pool->stream_enc_count) >+ return -1; >+ >+ tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]); > >- pipe_ctx->stream_res.tg = pool->timing_generators[inst]; >- pipe_ctx->plane_res.mi = pool->mis[inst]; >- pipe_ctx->plane_res.hubp = pool->hubps[inst]; >- pipe_ctx->plane_res.ipp = pool->ipps[inst]; >- pipe_ctx->plane_res.xfm = pool->transforms[inst]; >- pipe_ctx->plane_res.dpp = pool->dpps[inst]; >- pipe_ctx->stream_res.opp = pool->opps[inst]; >- if (pool->dpps[inst]) >- pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst; >- pipe_ctx->pipe_idx = inst; >+ if (tg_inst >= pool->timing_generator_count) >+ return false; >+ >+ if (!res_ctx->pipe_ctx[tg_inst].stream) { >+ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; >+ >+ pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; >+ pipe_ctx->plane_res.mi = pool->mis[tg_inst]; >+ pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; >+ pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; >+ pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; >+ pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; >+ pipe_ctx->stream_res.opp = pool->opps[tg_inst]; >+ >+ if (pool->dpps[tg_inst]) >+ pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; >+ pipe_ctx->pipe_idx = tg_inst; > > pipe_ctx->stream = stream; >- return inst; >+ return tg_inst; > } > > return -1; >@@ -2475,6 +2452,12 @@ > > if (cur_pipe->bottom_pipe) > cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; >+ >+ if (cur_pipe->next_odm_pipe) >+ cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; >+ >+ if (cur_pipe->prev_odm_pipe) >+ cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; > } > > for (i = 0; i < dst_ctx->stream_count; i++) { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_stream.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_stream.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 2019-08-31 15:01:11.859736168 -0500 >@@ -566,6 +566,7 @@ > > return ret; > } >+ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) > { >@@ -597,6 +598,14 @@ > struct hubp *hubp; > int i; > >+ /* Dynamic metadata is only supported on HDMI or DP */ >+ if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal)) >+ return false; >+ >+ /* Check hardware support */ >+ if (!dc->hwss.program_dmdata_engine) >+ return false; >+ > for (i = 0; i < MAX_PIPES; i++) { > pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; > if (pipe_ctx->stream == stream) >@@ -612,23 +621,7 @@ > > pipe_ctx->stream->dmdata_address = attr->address; > >- if (pipe_ctx->stream_res.stream_enc && >- pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL) { >- if (pipe_ctx->stream->dmdata_address.quad_part != 0) { >- /* if using dynamic meta, don't set up generic infopackets */ >- pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; >- pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata( >- pipe_ctx->stream_res.stream_enc, >- true, pipe_ctx->plane_res.hubp->inst, >- dc_is_dp_signal(pipe_ctx->stream->signal) ? >- dmdata_dp : dmdata_hdmi); >- } else >- pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata( >- pipe_ctx->stream_res.stream_enc, >- false, pipe_ctx->plane_res.hubp->inst, >- dc_is_dp_signal(pipe_ctx->stream->signal) ? >- dmdata_dp : dmdata_hdmi); >- } >+ dc->hwss.program_dmdata_engine(pipe_ctx); > > if (hubp->funcs->dmdata_set_attributes != NULL && > pipe_ctx->stream->dmdata_address.quad_part != 0) { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_surface.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_surface.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_surface.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_surface.c 2019-08-31 15:01:11.859736168 -0500 >@@ -60,7 +60,6 @@ > plane_state->lut3d_func = dc_create_3dlut_func(); > if (plane_state->lut3d_func != NULL) { > plane_state->lut3d_func->ctx = ctx; >- plane_state->lut3d_func->initialized = false; > } > plane_state->blend_tf = dc_create_transfer_func(); > if (plane_state->blend_tf != NULL) { >@@ -279,7 +278,7 @@ > goto alloc_fail; > > kref_init(&lut->refcount); >- lut->initialized = false; >+ lut->state.raw = 0; > > return lut; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_bios_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_bios_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_bios_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_bios_types.h 2019-08-31 15:01:11.859736168 -0500 >@@ -61,9 +61,6 @@ > struct graphics_object_id connector_object_id, > uint32_t device_tag_index, > struct connector_device_tag_info *info); >- enum bp_result (*get_firmware_info)( >- struct dc_bios *bios, >- struct dc_firmware_info *info); > enum bp_result (*get_spread_spectrum_info)( > struct dc_bios *bios, > enum as_signal_type signal, >@@ -152,6 +149,8 @@ > struct dc_context *ctx; > const struct bios_registers *regs; > struct integrated_info *integrated_info; >+ struct dc_firmware_info fw_info; >+ bool fw_info_valid; > }; > > #endif /* DC_BIOS_TYPES_H */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_dp_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_dp_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_dp_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_dp_types.h 2019-08-31 15:01:11.859736168 -0500 >@@ -90,6 +90,13 @@ > POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, > }; > >+enum dc_dp_training_pattern { >+ DP_TRAINING_PATTERN_SEQUENCE_1 = 0, >+ DP_TRAINING_PATTERN_SEQUENCE_2, >+ DP_TRAINING_PATTERN_SEQUENCE_3, >+ DP_TRAINING_PATTERN_SEQUENCE_4, >+}; >+ > struct dc_link_settings { > enum dc_lane_count lane_count; > enum dc_link_rate link_rate; >@@ -109,6 +116,23 @@ > struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; > }; > >+struct dc_link_training_overrides { >+ enum dc_voltage_swing *voltage_swing; >+ enum dc_pre_emphasis *pre_emphasis; >+ enum dc_post_cursor2 *post_cursor2; >+ >+ uint16_t *cr_pattern_time; >+ uint16_t *eq_pattern_time; >+ enum dc_dp_training_pattern *pattern_for_eq; >+ >+ enum dc_link_spread *downspread; >+ bool *alternate_scrambler_reset; >+ bool *enhanced_framing; >+ bool *mst_enable; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ bool *fec_enable; >+#endif >+}; > > union dpcd_rev { > struct { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 2019-08-31 15:01:11.859736168 -0500 >@@ -145,20 +145,20 @@ > if (channel_count > 2) { > > /* Based on HDMI spec 1.3 Table 7.5 */ >- if ((crtc_info->requested_pixel_clock <= 27000) && >+ if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && > (crtc_info->v_active <= 576) && > !(crtc_info->interlaced) && > !(crtc_info->pixel_repetition == 2 || > crtc_info->pixel_repetition == 4)) { > limit_freq_to_48_khz = true; > >- } else if ((crtc_info->requested_pixel_clock <= 27000) && >+ } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && > (crtc_info->v_active <= 576) && > (crtc_info->interlaced) && > (crtc_info->pixel_repetition == 2)) { > limit_freq_to_88_2_khz = true; > >- } else if ((crtc_info->requested_pixel_clock <= 54000) && >+ } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) && > (crtc_info->v_active <= 576) && > !(crtc_info->interlaced)) { > limit_freq_to_174_4_khz = true; >@@ -613,6 +613,8 @@ > > AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, > value); >+ DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n", >+ audio->inst, value, audio_info->display_name); > > /* > *write the port ID: >@@ -737,8 +739,8 @@ > > /* search pixel clock value for Azalia HDMI Audio */ > static void get_azalia_clock_info_hdmi( >- uint32_t crtc_pixel_clock_in_khz, >- uint32_t actual_pixel_clock_in_khz, >+ uint32_t crtc_pixel_clock_100hz, >+ uint32_t actual_pixel_clock_100Hz, > struct azalia_clock_info *azalia_clock_info) > { > /* audio_dto_phase= 24 * 10,000; >@@ -749,11 +751,11 @@ > /* audio_dto_module = PCLKFrequency * 10,000; > * [khz] -> [100Hz] */ > azalia_clock_info->audio_dto_module = >- actual_pixel_clock_in_khz * 10; >+ actual_pixel_clock_100Hz; > } > > static void get_azalia_clock_info_dp( >- uint32_t requested_pixel_clock_in_khz, >+ uint32_t requested_pixel_clock_100Hz, > const struct audio_pll_info *pll_info, > struct azalia_clock_info *azalia_clock_info) > { >@@ -792,15 +794,15 @@ > > /* calculate DTO settings */ > get_azalia_clock_info_hdmi( >- crtc_info->requested_pixel_clock, >- crtc_info->calculated_pixel_clock, >+ crtc_info->requested_pixel_clock_100Hz, >+ crtc_info->calculated_pixel_clock_100Hz, > &clock_info); > >- DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock = %d"\ >- "calculated_pixel_clock =%d\n"\ >+ DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ >+ "calculated_pixel_clock_100Hz =%d\n"\ > "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ >- crtc_info->requested_pixel_clock,\ >- crtc_info->calculated_pixel_clock,\ >+ crtc_info->requested_pixel_clock_100Hz,\ >+ crtc_info->calculated_pixel_clock_100Hz,\ > clock_info.audio_dto_module,\ > clock_info.audio_dto_phase); > >@@ -833,7 +835,7 @@ > > calculate DTO settings */ > get_azalia_clock_info_dp( >- crtc_info->requested_pixel_clock, >+ crtc_info->requested_pixel_clock_100Hz, > pll_info, > &clock_info); > >@@ -922,7 +924,6 @@ > .az_configure = dce_aud_az_configure, > .destroy = dce_aud_destroy, > }; >- > void dce_aud_destroy(struct audio **audio) > { > struct dce_audio *aud = DCE_AUD(*audio); >@@ -936,7 +937,7 @@ > unsigned int inst, > const struct dce_audio_registers *reg, > const struct dce_audio_shift *shifts, >- const struct dce_aduio_mask *masks >+ const struct dce_audio_mask *masks > ) > { > struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); >@@ -953,7 +954,6 @@ > audio->regs = reg; > audio->shifts = shifts; > audio->masks = masks; >- > return &audio->base; > } > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h 2019-08-31 15:01:11.859736168 -0500 >@@ -101,7 +101,7 @@ > uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO; > }; > >-struct dce_aduio_mask { >+struct dce_audio_mask { > uint32_t AZALIA_ENDPOINT_REG_INDEX; > uint32_t AZALIA_ENDPOINT_REG_DATA; > >@@ -125,7 +125,7 @@ > struct audio base; > const struct dce_audio_registers *regs; > const struct dce_audio_shift *shifts; >- const struct dce_aduio_mask *masks; >+ const struct dce_audio_mask *masks; > }; > > struct audio *dce_audio_create( >@@ -133,7 +133,7 @@ > unsigned int inst, > const struct dce_audio_registers *reg, > const struct dce_audio_shift *shifts, >- const struct dce_aduio_mask *masks); >+ const struct dce_audio_mask *masks); > > void dce_aud_destroy(struct audio **audio); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 2019-08-31 15:01:11.860736168 -0500 >@@ -30,6 +30,7 @@ > #include "core_types.h" > #include "dce_aux.h" > #include "dce/dce_11_0_sh_mask.h" >+#include "dm_event_log.h" > > #define CTX \ > aux110->base.ctx >@@ -252,6 +253,8 @@ > } > > REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1); >+ EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE, >+ request->action, request->address, request->length, request->data); > } > > static int read_channel_reply(struct dce_aux *engine, uint32_t size, >@@ -480,9 +483,13 @@ > *operation_result = get_channel_status(aux_engine, &returned_bytes); > > if (*operation_result == AUX_CHANNEL_OPERATION_SUCCEEDED) { >- read_channel_reply(aux_engine, payload->length, >+ int bytes_replied = 0; >+ bytes_replied = read_channel_reply(aux_engine, payload->length, > payload->data, payload->reply, > &status); >+ EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en, >+ EVENT_LOG_AUX_ORIGIN_NATIVE, *payload->reply, >+ bytes_replied, payload->data); > res = returned_bytes; > } else { > res = -1; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 2019-08-31 15:01:11.860736168 -0500 >@@ -1061,7 +1061,8 @@ > static const struct clock_source_funcs dcn20_clk_src_funcs = { > .cs_power_down = dce110_clock_source_power_down, > .program_pix_clk = dcn20_program_pix_clk, >- .get_pix_clk_dividers = dce112_get_pix_clk_dividers >+ .get_pix_clk_dividers = dce112_get_pix_clk_dividers, >+ .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz > }; > #endif > >@@ -1234,37 +1235,36 @@ > struct calc_pll_clock_source_init_data *init_data) > { > uint32_t i; >- struct dc_firmware_info fw_info = { { 0 } }; >+ struct dc_firmware_info *fw_info; > if (calc_pll_cs == NULL || > init_data == NULL || > init_data->bp == NULL) > return false; > >- if (init_data->bp->funcs->get_firmware_info( >- init_data->bp, >- &fw_info) != BP_RESULT_OK) >+ if (!init_data->bp->fw_info_valid) > return false; > >+ fw_info = &init_data->bp->fw_info; > calc_pll_cs->ctx = init_data->ctx; >- calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency; >+ calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency; > calc_pll_cs->min_vco_khz = >- fw_info.pll_info.min_output_pxl_clk_pll_frequency; >+ fw_info->pll_info.min_output_pxl_clk_pll_frequency; > calc_pll_cs->max_vco_khz = >- fw_info.pll_info.max_output_pxl_clk_pll_frequency; >+ fw_info->pll_info.max_output_pxl_clk_pll_frequency; > > if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0) > calc_pll_cs->max_pll_input_freq_khz = > init_data->max_override_input_pxl_clk_pll_freq_khz; > else > calc_pll_cs->max_pll_input_freq_khz = >- fw_info.pll_info.max_input_pxl_clk_pll_frequency; >+ fw_info->pll_info.max_input_pxl_clk_pll_frequency; > > if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0) > calc_pll_cs->min_pll_input_freq_khz = > init_data->min_override_input_pxl_clk_pll_freq_khz; > else > calc_pll_cs->min_pll_input_freq_khz = >- fw_info.pll_info.min_input_pxl_clk_pll_frequency; >+ fw_info->pll_info.min_input_pxl_clk_pll_frequency; > > calc_pll_cs->min_pix_clock_pll_post_divider = > init_data->min_pix_clk_pll_post_divider; >@@ -1316,7 +1316,6 @@ > const struct dce110_clk_src_shift *cs_shift, > const struct dce110_clk_src_mask *cs_mask) > { >- struct dc_firmware_info fw_info = { { 0 } }; > struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi; > struct calc_pll_clock_source_init_data calc_pll_cs_init_data; > >@@ -1329,14 +1328,12 @@ > clk_src->cs_shift = cs_shift; > clk_src->cs_mask = cs_mask; > >- if (clk_src->bios->funcs->get_firmware_info( >- clk_src->bios, &fw_info) != BP_RESULT_OK) { >+ if (!clk_src->bios->fw_info_valid) { > ASSERT_CRITICAL(false); > goto unexpected_failure; > } > >- clk_src->ext_clk_khz = >- fw_info.external_clock_source_frequency_for_dp; >+ clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; > > /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */ > calc_pll_cs_init_data.bp = bios; >@@ -1376,7 +1373,7 @@ > FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; > calc_pll_cs_init_data_hdmi.ctx = ctx; > >- clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency; >+ clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency; > > if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) > return true; >@@ -1419,8 +1416,6 @@ > const struct dce110_clk_src_shift *cs_shift, > const struct dce110_clk_src_mask *cs_mask) > { >- struct dc_firmware_info fw_info = { { 0 } }; >- > clk_src->base.ctx = ctx; > clk_src->bios = bios; > clk_src->base.id = id; >@@ -1430,13 +1425,12 @@ > clk_src->cs_shift = cs_shift; > clk_src->cs_mask = cs_mask; > >- if (clk_src->bios->funcs->get_firmware_info( >- clk_src->bios, &fw_info) != BP_RESULT_OK) { >+ if (!clk_src->bios->fw_info_valid) { > ASSERT_CRITICAL(false); > return false; > } > >- clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp; >+ clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; > > return true; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 2019-08-31 15:01:11.860736168 -0500 >@@ -78,6 +78,23 @@ > SRII(PIXEL_RATE_CNTL, OTG, 5) > #endif > >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ >+ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ >+ SRII(PHASE, DP_DTO, 0),\ >+ SRII(PHASE, DP_DTO, 1),\ >+ SRII(PHASE, DP_DTO, 2),\ >+ SRII(PHASE, DP_DTO, 3),\ >+ SRII(MODULO, DP_DTO, 0),\ >+ SRII(MODULO, DP_DTO, 1),\ >+ SRII(MODULO, DP_DTO, 2),\ >+ SRII(MODULO, DP_DTO, 3),\ >+ SRII(PIXEL_RATE_CNTL, OTG, 0),\ >+ SRII(PIXEL_RATE_CNTL, OTG, 1),\ >+ SRII(PIXEL_RATE_CNTL, OTG, 2),\ >+ SRII(PIXEL_RATE_CNTL, OTG, 3) >+#endif >+ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ > CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 2019-08-31 15:01:11.860736168 -0500 >@@ -62,6 +62,10 @@ > SRII(BLND_CONTROL, BLND, 4), \ > SRII(BLND_CONTROL, BLND, 5) > >+#define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ >+ SRII(PIXEL_RATE_CNTL, blk, inst), \ >+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) >+ > #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ > SRII(PIXEL_RATE_CNTL, blk, 0), \ > SRII(PIXEL_RATE_CNTL, blk, 1), \ >@@ -151,7 +155,10 @@ > SR(DCCG_GATE_DISABLE_CNTL2), \ > SR(DCFCLK_CNTL),\ > SR(DCFCLK_CNTL), \ >- SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ >+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) >+ >+ >+#define MMHUB_DCN_REG_LIST()\ > /* todo: get these from GVM instead of reading registers ourselves */\ > MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ > MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ >@@ -166,10 +173,14 @@ > MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ > MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) > >+ > #define HWSEQ_DCN1_REG_LIST()\ > HWSEQ_DCN_REG_LIST(), \ >- HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ >- HWSEQ_PHYPLL_REG_LIST(OTG), \ >+ MMHUB_DCN_REG_LIST(), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ > SR(DCHUBBUB_SDPIF_FB_BASE),\ > SR(DCHUBBUB_SDPIF_FB_OFFSET),\ > SR(DCHUBBUB_SDPIF_AGP_BASE),\ >@@ -202,8 +213,12 @@ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #define HWSEQ_DCN2_REG_LIST()\ > HWSEQ_DCN_REG_LIST(), \ >- HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ >- HWSEQ_PHYPLL_REG_LIST(OTG), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ > SR(MICROSECOND_TIME_BASE_DIV), \ > SR(MILLISECOND_TIME_BASE_DIV), \ > SR(DISPCLK_FREQ_CHANGE_CNTL), \ >@@ -227,8 +242,8 @@ > SR(DOMAIN7_PG_CONFIG), \ > SR(DOMAIN8_PG_CONFIG), \ > SR(DOMAIN9_PG_CONFIG), \ >- SR(DOMAIN10_PG_CONFIG), \ >- SR(DOMAIN11_PG_CONFIG), \ >+/* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ >+/* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ > SR(DOMAIN16_PG_CONFIG), \ > SR(DOMAIN17_PG_CONFIG), \ > SR(DOMAIN18_PG_CONFIG), \ >@@ -263,6 +278,59 @@ > BL_REG_LIST() > #endif > >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#define HWSEQ_DCN21_REG_LIST()\ >+ HWSEQ_DCN_REG_LIST(), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ >+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ >+ MMHUB_DCN_REG_LIST(), \ >+ SR(MICROSECOND_TIME_BASE_DIV), \ >+ SR(MILLISECOND_TIME_BASE_DIV), \ >+ SR(DISPCLK_FREQ_CHANGE_CNTL), \ >+ SR(RBBMIF_TIMEOUT_DIS), \ >+ SR(RBBMIF_TIMEOUT_DIS_2), \ >+ SR(DCHUBBUB_CRC_CTRL), \ >+ SR(DPP_TOP0_DPP_CRC_CTRL), \ >+ SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ >+ SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ >+ SR(MPC_CRC_CTRL), \ >+ SR(MPC_CRC_RESULT_GB), \ >+ SR(MPC_CRC_RESULT_C), \ >+ SR(MPC_CRC_RESULT_AR), \ >+ SR(DOMAIN0_PG_CONFIG), \ >+ SR(DOMAIN1_PG_CONFIG), \ >+ SR(DOMAIN2_PG_CONFIG), \ >+ SR(DOMAIN3_PG_CONFIG), \ >+ SR(DOMAIN4_PG_CONFIG), \ >+ SR(DOMAIN5_PG_CONFIG), \ >+ SR(DOMAIN6_PG_CONFIG), \ >+ SR(DOMAIN7_PG_CONFIG), \ >+ SR(DOMAIN16_PG_CONFIG), \ >+ SR(DOMAIN17_PG_CONFIG), \ >+ SR(DOMAIN18_PG_CONFIG), \ >+ SR(DOMAIN0_PG_STATUS), \ >+ SR(DOMAIN1_PG_STATUS), \ >+ SR(DOMAIN2_PG_STATUS), \ >+ SR(DOMAIN3_PG_STATUS), \ >+ SR(DOMAIN4_PG_STATUS), \ >+ SR(DOMAIN5_PG_STATUS), \ >+ SR(DOMAIN6_PG_STATUS), \ >+ SR(DOMAIN7_PG_STATUS), \ >+ SR(DOMAIN16_PG_STATUS), \ >+ SR(DOMAIN17_PG_STATUS), \ >+ SR(DOMAIN18_PG_STATUS), \ >+ SR(D1VGA_CONTROL), \ >+ SR(D2VGA_CONTROL), \ >+ SR(D3VGA_CONTROL), \ >+ SR(D4VGA_CONTROL), \ >+ SR(D5VGA_CONTROL), \ >+ SR(D6VGA_CONTROL), \ >+ SR(DC_IP_REQUEST_CNTL), \ >+ BL_REG_LIST() >+#endif >+ > struct dce_hwseq_registers { > > /* Backlight registers */ >@@ -401,36 +469,34 @@ > HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ > HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) > >+#define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\ >+ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ >+ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ >+ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ >+ HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) >+ > #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ > .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ > HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ > HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ > HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ > HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ >- HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) >+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ >+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) > > #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ > HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ > HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ >- HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ >- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) >+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ >+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) > > #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ > HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ > SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ > HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) > > #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ > HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ > HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) > > #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ >@@ -438,18 +504,15 @@ > SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ > SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ > SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ >- SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ >- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) >+ SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) > > #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ > HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ > HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ > HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ > HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ >- HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ >- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) >+ HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\ >+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) > > #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ > HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ >@@ -512,10 +575,7 @@ > HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ > HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ > HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \ >- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \ >- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) >+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) > > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ >@@ -576,6 +636,49 @@ > HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ > HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ > HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ >+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) >+#endif >+ >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ >+ HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ >+ HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ >+ HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ >+ HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ >+ HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ >+ HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ >+ HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ >+ HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ > HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ > HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) > #endif >@@ -612,9 +715,9 @@ > type ENABLE_L1_TLB;\ > type SYSTEM_ACCESS_MODE;\ > type LVTMA_BLON;\ >- type LVTMA_PWRSEQ_TARGET_STATE_R;\ > type LVTMA_DIGON;\ >- type LVTMA_DIGON_OVRD; >+ type LVTMA_DIGON_OVRD;\ >+ type LVTMA_PWRSEQ_TARGET_STATE_R; > > #define HWSEQ_DCN_REG_FIELD_LIST(type) \ > type HUBP_VTG_SEL; \ >@@ -696,7 +799,8 @@ > type D2VGA_MODE_ENABLE; \ > type D3VGA_MODE_ENABLE; \ > type D4VGA_MODE_ENABLE; \ >- type AZALIA_AUDIO_DTO_MODULE; >+ type AZALIA_AUDIO_DTO_MODULE;\ >+ type HPO_HDMISTREAMCLK_GATE_DIS; > > struct dce_hwseq_shift { > HWSEQ_REG_FIELD_LIST(uint8_t) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 2019-08-31 15:01:11.860736168 -0500 >@@ -25,6 +25,7 @@ > > #include <linux/delay.h> > >+#include "resource.h" > #include "dce_i2c.h" > #include "dce_i2c_hw.h" > #include "reg_helper.h" >@@ -99,17 +100,6 @@ > dce_i2c_hw->buffer_used_bytes; > } > >-uint32_t get_reference_clock( >- struct dc_bios *bios) >-{ >- struct dc_firmware_info info = { { 0 } }; >- >- if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK) >- return 0; >- >- return info.pll_info.crystal_frequency; >-} >- > static uint32_t get_speed( > const struct dce_i2c_hw *dce_i2c_hw) > { >@@ -401,7 +391,7 @@ > if (ddc->hw_info.hw_supported) { > enum gpio_ddc_line line = dal_ddc_get_line(ddc); > >- if (line < pool->pipe_count) >+ if (line < pool->res_cap->num_ddc) > dce_i2c_hw = pool->hw_i2cs[line]; > } > >@@ -632,7 +622,7 @@ > { > dce_i2c_hw->ctx = ctx; > dce_i2c_hw->engine_id = engine_id; >- dce_i2c_hw->reference_frequency = get_reference_clock(ctx->dc_bios) >> 1; >+ dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1; > dce_i2c_hw->regs = regs; > dce_i2c_hw->shifts = shifts; > dce_i2c_hw->masks = masks; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 2019-08-31 15:01:11.860736168 -0500 >@@ -391,10 +391,10 @@ > static void program_size_and_rotation( > struct dce_mem_input *dce_mi, > enum dc_rotation_angle rotation, >- const union plane_size *plane_size) >+ const struct plane_size *plane_size) > { >- const struct rect *in_rect = &plane_size->grph.surface_size; >- struct rect hw_rect = plane_size->grph.surface_size; >+ const struct rect *in_rect = &plane_size->surface_size; >+ struct rect hw_rect = plane_size->surface_size; > const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = { > [ROTATION_ANGLE_0] = 0, > [ROTATION_ANGLE_90] = 1, >@@ -423,7 +423,7 @@ > GRPH_Y_END, hw_rect.height); > > REG_SET(GRPH_PITCH, 0, >- GRPH_PITCH, plane_size->grph.surface_pitch); >+ GRPH_PITCH, plane_size->surface_pitch); > > REG_SET(HW_ROTATION, 0, > GRPH_ROTATION_ANGLE, rotation_angles[rotation]); >@@ -505,7 +505,7 @@ > struct mem_input *mi, > enum surface_pixel_format format, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > enum dc_rotation_angle rotation, > struct dc_plane_dcc_param *dcc, > bool horizontal_mirror) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 2019-08-31 15:01:11.860736168 -0500 >@@ -1038,6 +1038,24 @@ > } > > >+static void dce110_reset_hdmi_stream_attribute( >+ struct stream_encoder *enc) >+{ >+ struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); >+ if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) >+ REG_UPDATE_5(HDMI_CONTROL, >+ HDMI_PACKET_GEN_VERSION, 1, >+ HDMI_KEEPOUT_MODE, 1, >+ HDMI_DEEP_COLOR_ENABLE, 0, >+ HDMI_DATA_SCRAMBLE_EN, 0, >+ HDMI_CLOCK_CHANNEL_RATE, 0); >+ else >+ REG_UPDATE_3(HDMI_CONTROL, >+ HDMI_PACKET_GEN_VERSION, 1, >+ HDMI_KEEPOUT_MODE, 1, >+ HDMI_DEEP_COLOR_ENABLE, 0); >+} >+ > #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 > #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 > >@@ -1251,13 +1269,13 @@ > > static void get_audio_clock_info( > enum dc_color_depth color_depth, >- uint32_t crtc_pixel_clock_in_khz, >- uint32_t actual_pixel_clock_in_khz, >+ uint32_t crtc_pixel_clock_100Hz, >+ uint32_t actual_pixel_clock_100Hz, > struct audio_clock_info *audio_clock_info) > { > const struct audio_clock_info *clock_info; > uint32_t index; >- uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; >+ uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; > uint32_t audio_array_size; > > switch (color_depth) { >@@ -1294,16 +1312,16 @@ > } > > /* not found */ >- if (actual_pixel_clock_in_khz == 0) >- actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; >+ if (actual_pixel_clock_100Hz == 0) >+ actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; > > /* See HDMI spec the table entry under > * pixel clock of "Other". */ > audio_clock_info->pixel_clock_in_10khz = >- actual_pixel_clock_in_khz / 10; >- audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; >- audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; >- audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; >+ actual_pixel_clock_100Hz / 100; >+ audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; >+ audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; >+ audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; > > audio_clock_info->n_32khz = 4096; > audio_clock_info->n_44khz = 6272; >@@ -1369,14 +1387,14 @@ > > /* Program audio clock sample/regeneration parameters */ > get_audio_clock_info(crtc_info->color_depth, >- crtc_info->requested_pixel_clock, >- crtc_info->calculated_pixel_clock, >+ crtc_info->requested_pixel_clock_100Hz, >+ crtc_info->calculated_pixel_clock_100Hz, > &audio_clock_info); > DC_LOG_HW_AUDIO( >- "\n%s:Input::requested_pixel_clock = %d" \ >- "calculated_pixel_clock = %d \n", __func__, \ >- crtc_info->requested_pixel_clock, \ >- crtc_info->calculated_pixel_clock); >+ "\n%s:Input::requested_pixel_clock_100Hz = %d" \ >+ "calculated_pixel_clock_100Hz = %d \n", __func__, \ >+ crtc_info->requested_pixel_clock_100Hz, \ >+ crtc_info->calculated_pixel_clock_100Hz); > > /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ > REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); >@@ -1584,6 +1602,17 @@ > REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); > } > >+static unsigned int dig_source_otg( >+ struct stream_encoder *enc) >+{ >+ uint32_t tg_inst = 0; >+ struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); >+ >+ REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); >+ >+ return tg_inst; >+} >+ > static const struct stream_encoder_funcs dce110_str_enc_funcs = { > .dp_set_stream_attribute = > dce110_stream_encoder_dp_set_stream_attribute, >@@ -1618,6 +1647,8 @@ > .setup_stereo_sync = setup_stereo_sync, > .set_avmute = dce110_stream_encoder_set_avmute, > .dig_connect_to_otg = dig_connect_to_otg, >+ .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute, >+ .dig_source_otg = dig_source_otg, > }; > > void dce110_stream_encoder_construct( >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 2019-08-31 15:01:11.861736168 -0500 >@@ -304,7 +304,7 @@ > AUD_COMMON_MASK_SH_LIST(__SHIFT) > }; > >-static const struct dce_aduio_mask audio_mask = { >+static const struct dce_audio_mask audio_mask = { > AUD_COMMON_MASK_SH_LIST(_MASK) > }; > >@@ -910,7 +910,6 @@ > { > unsigned int i; > struct dc_context *ctx = dc->ctx; >- struct dc_firmware_info info; > struct dc_bios *bp; > > ctx->dc_bios->regs = &bios_regs; >@@ -921,8 +920,7 @@ > > bp = ctx->dc_bios; > >- if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && >- info.external_clock_source_frequency_for_dp != 0) { >+ if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { > pool->base.dp_clock_source = > dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 2019-08-31 15:01:11.861736168 -0500 >@@ -667,29 +667,7 @@ > link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, > pipe_ctx->stream_res.stream_enc->id, true); > >- /* update AVI info frame (HDMI, DP)*/ >- /* TODO: FPGA may change to hwss.update_info_frame */ >- >-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) >- if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL && >- pipe_ctx->plane_res.hubp != NULL) { >- if (pipe_ctx->stream->dmdata_address.quad_part != 0) { >- /* if using dynamic meta, don't set up generic infopackets */ >- pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; >- pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata( >- pipe_ctx->stream_res.stream_enc, >- true, pipe_ctx->plane_res.hubp->inst, >- dc_is_dp_signal(pipe_ctx->stream->signal) ? >- dmdata_dp : dmdata_hdmi); >- } else >- pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata( >- pipe_ctx->stream_res.stream_enc, >- false, pipe_ctx->plane_res.hubp->inst, >- dc_is_dp_signal(pipe_ctx->stream->signal) ? >- dmdata_dp : dmdata_hdmi); >- } >-#endif >- dce110_update_info_frame(pipe_ctx); >+ link->dc->hwss.update_info_frame(pipe_ctx); > > /* enable early control to avoid corruption on DP monitor*/ > active_total_with_borders = >@@ -753,7 +731,7 @@ > * @brief > * eDP only. > */ >-void hwss_edp_wait_for_hpd_ready( >+void dce110_edp_wait_for_hpd_ready( > struct dc_link *link, > bool power_up) > { >@@ -821,7 +799,7 @@ > } > } > >-void hwss_edp_power_control( >+void dce110_edp_power_control( > struct dc_link *link, > bool power_up) > { >@@ -903,7 +881,7 @@ > * @brief > * eDP only. Control the backlight of the eDP panel > */ >-void hwss_edp_backlight_control( >+void dce110_edp_backlight_control( > struct dc_link *link, > bool enable) > { >@@ -1003,7 +981,7 @@ > } > } > >-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) >+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) > { > struct dc *dc; > struct pp_smu_funcs *pp_smu = NULL; >@@ -1026,24 +1004,13 @@ > if (dc->res_pool->pp_smu) > pp_smu = dc->res_pool->pp_smu; > >- if (option != KEEP_ACQUIRED_RESOURCE || >- !dc->debug.az_endpoint_mute_only) >- /*only disalbe az_endpoint if power down or free*/ >- pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); >- > if (dc_is_dp_signal(pipe_ctx->stream->signal)) > pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( > pipe_ctx->stream_res.stream_enc); > else > pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( > pipe_ctx->stream_res.stream_enc); >- /*don't free audio if it is from retrain or internal disable stream*/ >- if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) { >- /*we have to dynamic arbitrate the audio endpoints*/ >- /*we free the resource, need reset is_audio_acquired*/ >- update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false); >- pipe_ctx->stream_res.audio = NULL; >- } >+ > if (clk_mgr->funcs->enable_pme_wa) > /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ > clk_mgr->funcs->enable_pme_wa(clk_mgr); >@@ -1056,21 +1023,24 @@ > } > } > >-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) >+void dce110_disable_stream(struct pipe_ctx *pipe_ctx) > { > struct dc_stream_state *stream = pipe_ctx->stream; > struct dc_link *link = stream->link; > struct dc *dc = pipe_ctx->stream->ctx->dc; > >- if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) >+ if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { > pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( > pipe_ctx->stream_res.stream_enc); >+ pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( >+ pipe_ctx->stream_res.stream_enc); >+ } > > if (dc_is_dp_signal(pipe_ctx->stream->signal)) > pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( > pipe_ctx->stream_res.stream_enc); > >- dc->hwss.disable_audio_stream(pipe_ctx, option); >+ dc->hwss.disable_audio_stream(pipe_ctx); > > link->link_enc->funcs->connect_dig_be_to_fe( > link->link_enc, >@@ -1174,27 +1144,27 @@ > stream->timing.flags.INTERLACE; > > audio_output->crtc_info.refresh_rate = >- (stream->timing.pix_clk_100hz*10000)/ >+ (stream->timing.pix_clk_100hz*100)/ > (stream->timing.h_total*stream->timing.v_total); > > audio_output->crtc_info.color_depth = > stream->timing.display_color_depth; > >- audio_output->crtc_info.requested_pixel_clock = >- pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; >+ audio_output->crtc_info.requested_pixel_clock_100Hz = >+ pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; > >- audio_output->crtc_info.calculated_pixel_clock = >- pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; >+ audio_output->crtc_info.calculated_pixel_clock_100Hz = >+ pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; > > /*for HDMI, audio ACR is with deep color ratio factor*/ > if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && >- audio_output->crtc_info.requested_pixel_clock == >- (stream->timing.pix_clk_100hz / 10)) { >+ audio_output->crtc_info.requested_pixel_clock_100Hz == >+ (stream->timing.pix_clk_100hz)) { > if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { >- audio_output->crtc_info.requested_pixel_clock = >- audio_output->crtc_info.requested_pixel_clock/2; >- audio_output->crtc_info.calculated_pixel_clock = >- pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/20; >+ audio_output->crtc_info.requested_pixel_clock_100Hz = >+ audio_output->crtc_info.requested_pixel_clock_100Hz/2; >+ audio_output->crtc_info.calculated_pixel_clock_100Hz = >+ pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; > > } > } >@@ -1360,7 +1330,7 @@ > struct drr_params params = {0}; > unsigned int event_triggers = 0; > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) >- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; > #endif > > if (dc->hwss.disable_stream_gating) { >@@ -1428,7 +1398,7 @@ > &stream->bit_depth_params, > &stream->clamping); > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) >- if (odm_pipe) { >+ while (odm_pipe) { > odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( > odm_pipe->stream_res.opp, > COLOR_SPACE_YCBCR601, >@@ -1439,6 +1409,7 @@ > odm_pipe->stream_res.opp, > &stream->bit_depth_params, > &stream->clamping); >+ odm_pipe = odm_pipe->next_odm_pipe; > } > #endif > >@@ -1748,7 +1719,8 @@ > ******************************************************************************/ > > static void set_drr(struct pipe_ctx **pipe_ctx, >- int num_pipes, int vmin, int vmax) >+ int num_pipes, unsigned int vmin, unsigned int vmax, >+ unsigned int vmid, unsigned int vmid_frame_number) > { > int i = 0; > struct drr_params params = {0}; >@@ -1932,8 +1904,25 @@ > /* Disable if new stream is null. O/w, if stream is > * disabled already, no need to disable again. > */ >- if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) >- core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); >+ if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { >+ core_link_disable_stream(pipe_ctx_old); >+ >+ /* free acquired resources*/ >+ if (pipe_ctx_old->stream_res.audio) { >+ /*disable az_endpoint*/ >+ pipe_ctx_old->stream_res.audio->funcs-> >+ az_disable(pipe_ctx_old->stream_res.audio); >+ >+ /*free audio*/ >+ if (dc->caps.dynamic_audio == true) { >+ /*we have to dynamic arbitrate the audio endpoints*/ >+ /*we free the resource, need reset is_audio_acquired*/ >+ update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, >+ pipe_ctx_old->stream_res.audio, false); >+ pipe_ctx_old->stream_res.audio = NULL; >+ } >+ } >+ } > > pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); > if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { >@@ -2098,7 +2087,7 @@ > if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) > continue; > >- if (pipe_ctx->top_pipe) >+ if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) > continue; > > status = apply_single_controller_ctx_to_hw( >@@ -2777,9 +2766,9 @@ > .setup_stereo = NULL, > .set_avmute = dce110_set_avmute, > .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, >- .edp_backlight_control = hwss_edp_backlight_control, >- .edp_power_control = hwss_edp_power_control, >- .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, >+ .edp_backlight_control = dce110_edp_backlight_control, >+ .edp_power_control = dce110_edp_power_control, >+ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, > .set_cursor_position = dce110_set_cursor_position, > .set_cursor_attribute = dce110_set_cursor_attribute > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h 2019-08-31 15:01:11.861736168 -0500 >@@ -42,7 +42,7 @@ > > void dce110_enable_stream(struct pipe_ctx *pipe_ctx); > >-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option); >+void dce110_disable_stream(struct pipe_ctx *pipe_ctx); > > void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, > struct dc_link_settings *link_settings); >@@ -50,7 +50,7 @@ > void dce110_blank_stream(struct pipe_ctx *pipe_ctx); > > void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx); >-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option); >+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx); > > void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); > >@@ -73,15 +73,15 @@ > > void dp_receiver_power_ctrl(struct dc_link *link, bool on); > >-void hwss_edp_power_control( >+void dce110_edp_power_control( > struct dc_link *link, > bool power_up); > >-void hwss_edp_backlight_control( >+void dce110_edp_backlight_control( > struct dc_link *link, > bool enable); > >-void hwss_edp_wait_for_hpd_ready( >+void dce110_edp_wait_for_hpd_ready( > struct dc_link *link, > bool power_up); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c 2019-08-31 15:01:11.861736168 -0500 >@@ -229,26 +229,26 @@ > static void program_size_and_rotation( > struct dce_mem_input *mem_input110, > enum dc_rotation_angle rotation, >- const union plane_size *plane_size) >+ const struct plane_size *plane_size) > { > uint32_t value = 0; >- union plane_size local_size = *plane_size; >+ struct plane_size local_size = *plane_size; > > if (rotation == ROTATION_ANGLE_90 || > rotation == ROTATION_ANGLE_270) { > >- swap(local_size.video.luma_size.x, >- local_size.video.luma_size.y); >- swap(local_size.video.luma_size.width, >- local_size.video.luma_size.height); >- swap(local_size.video.chroma_size.x, >- local_size.video.chroma_size.y); >- swap(local_size.video.chroma_size.width, >- local_size.video.chroma_size.height); >+ swap(local_size.surface_size.x, >+ local_size.surface_size.y); >+ swap(local_size.surface_size.width, >+ local_size.surface_size.height); >+ swap(local_size.chroma_size.x, >+ local_size.chroma_size.y); >+ swap(local_size.chroma_size.width, >+ local_size.chroma_size.height); > } > > value = 0; >- set_reg_field_value(value, local_size.video.luma_pitch, >+ set_reg_field_value(value, local_size.surface_pitch, > UNP_GRPH_PITCH_L, GRPH_PITCH_L); > > dm_write_reg( >@@ -257,7 +257,7 @@ > value); > > value = 0; >- set_reg_field_value(value, local_size.video.chroma_pitch, >+ set_reg_field_value(value, local_size.chroma_pitch, > UNP_GRPH_PITCH_C, GRPH_PITCH_C); > dm_write_reg( > mem_input110->base.ctx, >@@ -297,8 +297,8 @@ > value); > > value = 0; >- set_reg_field_value(value, local_size.video.luma_size.x + >- local_size.video.luma_size.width, >+ set_reg_field_value(value, local_size.surface_size.x + >+ local_size.surface_size.width, > UNP_GRPH_X_END_L, GRPH_X_END_L); > dm_write_reg( > mem_input110->base.ctx, >@@ -306,8 +306,8 @@ > value); > > value = 0; >- set_reg_field_value(value, local_size.video.chroma_size.x + >- local_size.video.chroma_size.width, >+ set_reg_field_value(value, local_size.chroma_size.x + >+ local_size.chroma_size.width, > UNP_GRPH_X_END_C, GRPH_X_END_C); > dm_write_reg( > mem_input110->base.ctx, >@@ -315,8 +315,8 @@ > value); > > value = 0; >- set_reg_field_value(value, local_size.video.luma_size.y + >- local_size.video.luma_size.height, >+ set_reg_field_value(value, local_size.surface_size.y + >+ local_size.surface_size.height, > UNP_GRPH_Y_END_L, GRPH_Y_END_L); > dm_write_reg( > mem_input110->base.ctx, >@@ -324,8 +324,8 @@ > value); > > value = 0; >- set_reg_field_value(value, local_size.video.chroma_size.y + >- local_size.video.chroma_size.height, >+ set_reg_field_value(value, local_size.chroma_size.y + >+ local_size.chroma_size.height, > UNP_GRPH_Y_END_C, GRPH_Y_END_C); > dm_write_reg( > mem_input110->base.ctx, >@@ -637,7 +637,7 @@ > struct mem_input *mem_input, > enum surface_pixel_format format, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > enum dc_rotation_angle rotation, > struct dc_plane_dcc_param *dcc, > bool horizotal_mirror) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 2019-08-31 15:01:11.861736168 -0500 >@@ -331,7 +331,7 @@ > AUD_COMMON_MASK_SH_LIST(__SHIFT) > }; > >-static const struct dce_aduio_mask audio_mask = { >+static const struct dce_audio_mask audio_mask = { > AUD_COMMON_MASK_SH_LIST(_MASK) > }; > >@@ -1274,7 +1274,6 @@ > { > unsigned int i; > struct dc_context *ctx = dc->ctx; >- struct dc_firmware_info info; > struct dc_bios *bp; > > ctx->dc_bios->regs = &bios_regs; >@@ -1300,8 +1299,7 @@ > > bp = ctx->dc_bios; > >- if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && >- info.external_clock_source_frequency_for_dp != 0) { >+ if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { > pool->base.dp_clock_source = > dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 2019-08-31 15:01:11.861736168 -0500 >@@ -337,7 +337,7 @@ > AUD_COMMON_MASK_SH_LIST(__SHIFT) > }; > >-static const struct dce_aduio_mask audio_mask = { >+static const struct dce_audio_mask audio_mask = { > AUD_COMMON_MASK_SH_LIST(_MASK) > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 2019-08-31 15:01:11.861736168 -0500 >@@ -352,7 +352,7 @@ > DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) > }; > >-static const struct dce_aduio_mask audio_mask = { >+static const struct dce_audio_mask audio_mask = { > DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 2019-08-31 15:01:11.861736168 -0500 >@@ -322,7 +322,7 @@ > AUD_COMMON_MASK_SH_LIST(__SHIFT) > }; > >-static const struct dce_aduio_mask audio_mask = { >+static const struct dce_audio_mask audio_mask = { > AUD_COMMON_MASK_SH_LIST(_MASK) > }; > >@@ -876,7 +876,6 @@ > { > unsigned int i; > struct dc_context *ctx = dc->ctx; >- struct dc_firmware_info info; > struct dc_bios *bp; > > ctx->dc_bios->regs = &bios_regs; >@@ -902,8 +901,7 @@ > > bp = ctx->dc_bios; > >- if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && >- info.external_clock_source_frequency_for_dp != 0) { >+ if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { > pool->base.dp_clock_source = > dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); > >@@ -1075,7 +1073,6 @@ > { > unsigned int i; > struct dc_context *ctx = dc->ctx; >- struct dc_firmware_info info; > struct dc_bios *bp; > > ctx->dc_bios->regs = &bios_regs; >@@ -1101,8 +1098,7 @@ > > bp = ctx->dc_bios; > >- if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && >- info.external_clock_source_frequency_for_dp != 0) { >+ if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { > pool->base.dp_clock_source = > dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); > >@@ -1274,7 +1270,6 @@ > { > unsigned int i; > struct dc_context *ctx = dc->ctx; >- struct dc_firmware_info info; > struct dc_bios *bp; > > ctx->dc_bios->regs = &bios_regs; >@@ -1300,8 +1295,7 @@ > > bp = ctx->dc_bios; > >- if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && >- info.external_clock_source_frequency_for_dp != 0) { >+ if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { > pool->base.dp_clock_source = > dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc.h 2019-08-31 15:01:11.859736168 -0500 >@@ -39,7 +39,7 @@ > #include "inc/hw/dmcu.h" > #include "dml/display_mode_lib.h" > >-#define DC_VER "3.2.35" >+#define DC_VER "3.2.48" > > #define MAX_SURFACES 3 > #define MAX_PLANES 6 >@@ -121,6 +121,7 @@ > struct dc_bug_wa { > bool no_connect_phy_config; > bool dedcn20_305_wa; >+ bool skip_clock_update; > }; > #endif > >@@ -219,7 +220,7 @@ > bool power_down_display_on_boot; > bool edp_not_connected; > bool forced_clocks; >- >+ bool multi_mon_pp_mclk_switch; > }; > > enum visual_confirm { >@@ -252,7 +253,10 @@ > struct dc_clocks { > int dispclk_khz; > int max_supported_dppclk_khz; >+ int max_supported_dispclk_khz; > int dppclk_khz; >+ int bw_dppclk_khz; /*a copy of dppclk_khz*/ >+ int bw_dispclk_khz; > int dcfclk_khz; > int socclk_khz; > int dcfclk_deep_sleep_khz; >@@ -260,6 +264,12 @@ > int phyclk_khz; > int dramclk_khz; > bool p_state_change_support; >+ >+ /* >+ * Elements below are not compared for the purposes of >+ * optimization required >+ */ >+ bool prev_p_state_change_support; > }; > > struct dc_bw_validation_profile { >@@ -341,6 +351,7 @@ > bool disable_pplib_wm_range; > enum wm_report_mode pplib_wm_report_mode; > unsigned int min_disp_clk_khz; >+ unsigned int min_dpp_clk_khz; > int sr_exit_time_dpm0_ns; > int sr_enter_plus_exit_time_dpm0_ns; > int sr_exit_time_ns; >@@ -367,6 +378,7 @@ > bool scl_reset_length10; > bool hdmi20_disable; > bool skip_detection_link_training; >+ bool remove_disconnect_edp; > unsigned int force_odm_combine; //bit vector based on otg inst > unsigned int force_fclk_khz; > bool disable_tri_buf; >@@ -374,10 +386,18 @@ > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > bool disable_fec; > #endif >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+ bool disable_48mhz_pwrdwn; >+#endif > /* This forces a hard min on the DCFCLK requested to SMU/PP > * watermarks are not affected. > */ > unsigned int force_min_dcfclk_mhz; >+ bool disable_timing_sync; >+#if defined(CONFIG_DRM_AMD_DC_DCN2_0) >+ bool cm_in_bypass; >+#endif >+ int force_clock_mode;/*every mode change.*/ > }; > > struct dc_debug_data { >@@ -406,6 +426,7 @@ > } gart_config; > > bool valid; >+ uint64_t page_table_default_page_addr; > }; > > struct dc_virtual_addr_space_config { >@@ -597,9 +618,12 @@ > TRANSFER_FUNCTION_UNITY, > TRANSFER_FUNCTION_HLG, > TRANSFER_FUNCTION_HLG12, >- TRANSFER_FUNCTION_GAMMA22 >+ TRANSFER_FUNCTION_GAMMA22, >+ TRANSFER_FUNCTION_GAMMA24, >+ TRANSFER_FUNCTION_GAMMA26 > }; > >+ > struct dc_transfer_func { > struct kref refcount; > enum dc_transfer_func_type type; >@@ -615,12 +639,26 @@ > > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > >+union dc_3dlut_state { >+ struct { >+ uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ >+ uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ >+ uint32_t rmu_mux_num:3; /*index of mux to use*/ >+ uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ >+ uint32_t mpc_rmu1_mux:4; >+ uint32_t mpc_rmu2_mux:4; >+ uint32_t reserved:15; >+ } bits; >+ uint32_t raw; >+}; >+ > > struct dc_3dlut { > struct kref refcount; > struct tetrahedral_params lut_3d; > uint32_t hdr_multiplier; >- bool initialized; >+ bool initialized; /*remove after diag fix*/ >+ union dc_3dlut_state state; > struct dc_context *ctx; > }; > #endif >@@ -682,7 +720,7 @@ > struct rect dst_rect; > struct rect clip_rect; > >- union plane_size plane_size; >+ struct plane_size plane_size; > union dc_tiling_info tiling_info; > > struct dc_plane_dcc_param dcc; >@@ -716,6 +754,7 @@ > bool visible; > bool flip_immediate; > bool horizontal_mirror; >+ int layer_index; > > union surface_update_flags update_flags; > /* private to DC core */ >@@ -731,7 +770,7 @@ > }; > > struct dc_plane_info { >- union plane_size plane_size; >+ struct plane_size plane_size; > union dc_tiling_info tiling_info; > struct dc_plane_dcc_param dcc; > enum surface_pixel_format format; >@@ -745,6 +784,7 @@ > bool global_alpha; > int global_alpha_value; > bool input_csc_enabled; >+ int layer_index; > }; > > struct dc_scaling_info { >@@ -834,6 +874,9 @@ > > void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); > >+bool dc_set_generic_gpio_for_stereo(bool enable, >+ struct gpio_service *gpio_service); >+ > /* > * fast_validate: we return after determining if we can support the new state, > * but before we populate the programming info >@@ -1020,6 +1063,8 @@ > > bool dc_is_dmcu_initialized(struct dc *dc); > >+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); >+void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); > #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) > /******************************************************************************* > * DSC Interfaces >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_hw_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_hw_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 2019-08-31 15:01:11.859736168 -0500 >@@ -115,42 +115,40 @@ > int height; > }; > >-union plane_size { >- /* Grph or Video will be selected >- * based on format above: >- * Use Video structure if >- * format >= DalPixelFormat_VideoBegin >- * else use Grph structure >+struct plane_size { >+ /* Graphic surface pitch in pixels. >+ * In LINEAR_GENERAL mode, pitch >+ * is 32 pixel aligned. > */ >- struct { >- struct rect surface_size; >- /* Graphic surface pitch in pixels. >- * In LINEAR_GENERAL mode, pitch >- * is 32 pixel aligned. >- */ >- int surface_pitch; >- } grph; >+ int surface_pitch; >+ int chroma_pitch; >+ struct rect surface_size; >+ struct rect chroma_size; > >- struct { >- struct rect luma_size; >- /* Graphic surface pitch in pixels. >- * In LINEAR_GENERAL mode, pitch is >- * 32 pixel aligned. >- */ >- int luma_pitch; >+ union { >+ struct { >+ struct rect surface_size; >+ int surface_pitch; >+ } grph; > >- struct rect chroma_size; >- /* Graphic surface pitch in pixels. >- * In LINEAR_GENERAL mode, pitch is >- * 32 pixel aligned. >- */ >- int chroma_pitch; >- } video; >+ struct { >+ struct rect luma_size; >+ int luma_pitch; >+ struct rect chroma_size; >+ int chroma_pitch; >+ } video; >+ }; > }; > > struct dc_plane_dcc_param { > bool enable; > >+ int meta_pitch; >+ bool independent_64b_blks; >+ >+ int meta_pitch_c; >+ bool independent_64b_blks_c; >+ > union { > struct { > int meta_pitch; >@@ -482,7 +480,6 @@ > * is_logical_identity indicates the given gamma ramp regardless of type is identity. > */ > bool is_identity; >- bool is_logical_identity; > }; > > /* Used by both ipp amd opp functions*/ >@@ -519,7 +516,8 @@ > uint32_t INVERT_PIXEL_DATA:1; > uint32_t ZERO_EXPANSION:1; > uint32_t MIN_MAX_INVERT:1; >- uint32_t RESERVED:25; >+ uint32_t ENABLE_CURSOR_DEGAMMA:1; >+ uint32_t RESERVED:24; > } bits; > uint32_t value; > }; >@@ -615,6 +613,7 @@ > uint32_t h_taps; > uint32_t v_taps_c; > uint32_t h_taps_c; >+ bool integer_scaling; > }; > > enum dc_timing_standard { >@@ -758,6 +757,8 @@ > struct dc_crtc_timing_adjust { > uint32_t v_total_min; > uint32_t v_total_max; >+ uint32_t v_total_mid; >+ uint32_t v_total_mid_frame_num; > }; > > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_link.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_link.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_link.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_link.h 2019-08-31 15:01:11.859736168 -0500 >@@ -83,6 +83,8 @@ > bool is_hpd_filter_disabled; > bool dp_ss_off; > bool link_state_valid; >+ bool aux_access_disabled; >+ bool sync_lt_in_progress; > > /* caps is the same as reported_link_cap. link_traing use > * reported_link_cap. Will clean up. TODO >@@ -92,6 +94,7 @@ > struct dc_link_settings cur_link_settings; > struct dc_lane_settings cur_lane_setting; > struct dc_link_settings preferred_link_setting; >+ struct dc_link_training_overrides preferred_training_settings; > > uint8_t ddc_hw_inst; > >@@ -217,11 +220,24 @@ > struct dc_link *link, > struct link_training_settings *lt_settings); > >+bool dc_link_dp_perform_link_training_skip_aux( >+ struct dc_link *link, >+ const struct dc_link_settings *link_setting); >+ > enum link_training_result dc_link_dp_perform_link_training( > struct dc_link *link, > const struct dc_link_settings *link_setting, > bool skip_video_pattern); > >+bool dc_link_dp_sync_lt_begin(struct dc_link *link); >+ >+enum link_training_result dc_link_dp_sync_lt_attempt( >+ struct dc_link *link, >+ struct dc_link_settings *link_setting, >+ struct dc_link_training_overrides *lt_settings); >+ >+bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down); >+ > void dc_link_dp_enable_hpd(const struct dc_link *link); > > void dc_link_dp_disable_hpd(const struct dc_link *link); >@@ -251,6 +267,11 @@ > void dc_link_set_preferred_link_settings(struct dc *dc, > struct dc_link_settings *link_setting, > struct dc_link *link); >+void dc_link_set_preferred_training_settings(struct dc *dc, >+ struct dc_link_settings *link_setting, >+ struct dc_link_training_overrides *lt_overrides, >+ struct dc_link *link, >+ bool skip_immediate_retrain); > void dc_link_enable_hpd(const struct dc_link *link); > void dc_link_disable_hpd(const struct dc_link *link); > void dc_link_set_test_pattern(struct dc_link *link, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 2019-08-31 15:01:11.861736168 -0500 >@@ -343,8 +343,8 @@ > region_start = -MAX_LOW_POINT; > region_end = NUMBER_REGIONS - MAX_LOW_POINT; > } else { >- /* 10 segments >- * segment is from 2^-10 to 2^0 >+ /* 11 segments >+ * segment is from 2^-10 to 2^1 > * There are less than 256 points, for optimization > */ > seg_distr[0] = 3; >@@ -357,9 +357,10 @@ > seg_distr[7] = 4; > seg_distr[8] = 4; > seg_distr[9] = 4; >+ seg_distr[10] = 1; > > region_start = -10; >- region_end = 0; >+ region_end = 1; > } > > for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 2019-08-31 15:01:11.862736169 -0500 >@@ -426,8 +426,9 @@ > > void dpp1_set_cursor_attributes( > struct dpp *dpp_base, >- enum dc_cursor_color_format color_format) >+ struct dc_cursor_attributes *cursor_attributes) > { >+ enum dc_cursor_color_format color_format = cursor_attributes->color_format; > struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); > > REG_UPDATE_2(CURSOR0_CONTROL, >@@ -456,6 +457,19 @@ > int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; > uint32_t cur_en = pos->enable ? 1 : 0; > >+ // Cursor width/height and hotspots need to be rotated for offset calculation >+ if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { >+ swap(width, height); >+ if (param->rotation == ROTATION_ANGLE_90) { >+ src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; >+ src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; >+ } >+ } else if (param->rotation == ROTATION_ANGLE_180) { >+ src_x_offset = pos->x - param->viewport.x; >+ src_y_offset = pos->y - param->viewport.y; >+ } >+ >+ > if (src_x_offset >= (int)param->viewport.width) > cur_en = 0; /* not visible beyond right edge*/ > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 2019-08-31 15:01:11.862736169 -0500 >@@ -1368,7 +1368,7 @@ > > void dpp1_set_cursor_attributes( > struct dpp *dpp_base, >- enum dc_cursor_color_format color_format); >+ struct dc_cursor_attributes *cursor_attributes); > > void dpp1_set_cursor_position( > struct dpp *dpp_base, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 2019-08-31 15:01:11.862736169 -0500 >@@ -104,7 +104,7 @@ > DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow); > } > >-bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub) >+bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub) > { > struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); > uint32_t enable = 0; >@@ -945,6 +945,8 @@ > .get_dcc_compression_cap = hubbub1_get_dcc_compression_cap, > .wm_read_state = hubbub1_wm_read_state, > .program_watermarks = hubbub1_program_watermarks, >+ .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, >+ .allow_self_refresh_control = hubbub1_allow_self_refresh_control, > }; > > void hubbub1_construct(struct hubbub *hubbub, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 2019-08-31 15:01:11.862736169 -0500 >@@ -119,6 +119,28 @@ > uint32_t DCN_VM_AGP_BOT; > uint32_t DCN_VM_AGP_TOP; > uint32_t DCN_VM_AGP_BASE; >+ uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB; >+ uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB; >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A; >+ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B; >+ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C; >+ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D; >+ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A; >+ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B; >+ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C; >+ uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D; >+ uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A; >+ uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B; >+ uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C; >+ uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D; >+ uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; >+ uint32_t DCHVM_CTRL0; >+ uint32_t DCHVM_MEM_CTRL; >+ uint32_t DCHVM_CLK_CTRL; >+ uint32_t DCHVM_RIOMMU_CTRL0; >+ uint32_t DCHVM_RIOMMU_STAT0; >+#endif > }; > > /* set field name */ >@@ -196,7 +218,9 @@ > type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ > type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ > type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ >- type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D >+ type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ >+ type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ >+ type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB > > #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ > type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\ >@@ -208,15 +232,68 @@ > type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\ > type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D > >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#define HUBBUB_HVM_REG_FIELD_LIST(type) \ >+ type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\ >+ type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\ >+ type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\ >+ type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\ >+ type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ >+ type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ >+ type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\ >+ type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\ >+ type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\ >+ type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\ >+ type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\ >+ type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\ >+ type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\ >+ type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\ >+ type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\ >+ type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\ >+ type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\ >+ type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\ >+ type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\ >+ type HOSTVM_INIT_REQ; \ >+ type HVM_GPUVMRET_PWR_REQ_DIS; \ >+ type HVM_GPUVMRET_FORCE_REQ; \ >+ type HVM_GPUVMRET_POWER_STATUS; \ >+ type HVM_DISPCLK_R_GATE_DIS; \ >+ type HVM_DISPCLK_G_GATE_DIS; \ >+ type HVM_DCFCLK_R_GATE_DIS; \ >+ type HVM_DCFCLK_G_GATE_DIS; \ >+ type TR_REQ_REQCLKREQ_MODE; \ >+ type TW_RSP_COMPCLKREQ_MODE; \ >+ type HOSTVM_PREFETCH_REQ; \ >+ type HOSTVM_POWERSTATUS; \ >+ type RIOMMU_ACTIVE; \ >+ type HOSTVM_PREFETCH_DONE >+#endif > > struct dcn_hubbub_shift { > DCN_HUBBUB_REG_FIELD_LIST(uint8_t); > HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ HUBBUB_HVM_REG_FIELD_LIST(uint8_t); >+#endif > }; > > struct dcn_hubbub_mask { > DCN_HUBBUB_REG_FIELD_LIST(uint32_t); > HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ HUBBUB_HVM_REG_FIELD_LIST(uint32_t); >+#endif > }; > > struct dc; >@@ -247,7 +324,7 @@ > > void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow); > >-bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub); >+bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub); > > void hubbub1_toggle_watermark_change_req( > struct hubbub *hubbub); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 2019-08-31 15:01:11.862736169 -0500 >@@ -163,7 +163,7 @@ > void hubp1_program_size( > struct hubp *hubp, > enum surface_pixel_format format, >- const union plane_size *plane_size, >+ const struct plane_size *plane_size, > struct dc_plane_dcc_param *dcc) > { > struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); >@@ -173,16 +173,16 @@ > * 444 or 420 luma > */ > if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { >- ASSERT(plane_size->video.chroma_pitch != 0); >+ ASSERT(plane_size->chroma_pitch != 0); > /* Chroma pitch zero can cause system hang! */ > >- pitch = plane_size->video.luma_pitch - 1; >- meta_pitch = dcc->video.meta_pitch_l - 1; >- pitch_c = plane_size->video.chroma_pitch - 1; >- meta_pitch_c = dcc->video.meta_pitch_c - 1; >+ pitch = plane_size->surface_pitch - 1; >+ meta_pitch = dcc->meta_pitch - 1; >+ pitch_c = plane_size->chroma_pitch - 1; >+ meta_pitch_c = dcc->meta_pitch_c - 1; > } else { >- pitch = plane_size->grph.surface_pitch - 1; >- meta_pitch = dcc->grph.meta_pitch - 1; >+ pitch = plane_size->surface_pitch - 1; >+ meta_pitch = dcc->meta_pitch - 1; > pitch_c = 0; > meta_pitch_c = 0; > } >@@ -509,7 +509,7 @@ > } > > void hubp1_dcc_control(struct hubp *hubp, bool enable, >- bool independent_64b_blks) >+ enum hubp_ind_block_size independent_64b_blks) > { > uint32_t dcc_en = enable ? 1 : 0; > uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; >@@ -526,13 +526,13 @@ > struct hubp *hubp, > enum surface_pixel_format format, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > enum dc_rotation_angle rotation, > struct dc_plane_dcc_param *dcc, > bool horizontal_mirror, > unsigned int compat_level) > { >- hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); >+ hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); > hubp1_program_tiling(hubp, tiling_info, format); > hubp1_program_size(hubp, format, plane_size, dcc); > hubp1_program_rotation(hubp, rotation, horizontal_mirror); >@@ -843,7 +843,7 @@ > PRI_VIEWPORT_Y_START_C, viewport_c->y); > } > >-void hubp1_read_state(struct hubp *hubp) >+void hubp1_read_state_common(struct hubp *hubp) > { > struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); > struct dcn_hubp_state *s = &hubp1->state; >@@ -859,24 +859,6 @@ > PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, > MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, > CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); >- REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, >- CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, >- MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, >- META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, >- MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, >- DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, >- MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, >- SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, >- PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); >- REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, >- CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, >- MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, >- META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, >- MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, >- DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, >- MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, >- SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, >- PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); > > /* DLG - Per hubp */ > REG_GET_2(BLANK_OFFSET_0, >@@ -1030,8 +1012,38 @@ > REG_GET_2(DCN_TTU_QOS_WM, > QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, > QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); >+ > } > >+void hubp1_read_state(struct hubp *hubp) >+{ >+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); >+ struct dcn_hubp_state *s = &hubp1->state; >+ struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; >+ >+ hubp1_read_state_common(hubp); >+ >+ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, >+ CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, >+ MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, >+ META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, >+ MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, >+ DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, >+ MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, >+ SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, >+ PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); >+ >+ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, >+ CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, >+ MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, >+ META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, >+ MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, >+ DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, >+ MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, >+ SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, >+ PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); >+ >+} > enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) > { > enum cursor_pitch hw_pitch; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 2019-08-31 15:01:11.862736169 -0500 >@@ -125,8 +125,6 @@ > SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ > SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ > SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ >- SR(DCHUBBUB_SDPIF_FB_BASE),\ >- SR(DCHUBBUB_SDPIF_FB_OFFSET),\ > SRI(CURSOR_SETTINS, HUBPREQ, id), \ > SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ > SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ >@@ -226,14 +224,6 @@ > uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \ > uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \ > uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \ >- uint32_t DCHUBBUB_SDPIF_FB_BASE; \ >- uint32_t DCHUBBUB_SDPIF_FB_OFFSET; \ >- uint32_t DCN_VM_FB_LOCATION_TOP; \ >- uint32_t DCN_VM_FB_LOCATION_BASE; \ >- uint32_t DCN_VM_FB_OFFSET; \ >- uint32_t DCN_VM_AGP_BASE; \ >- uint32_t DCN_VM_AGP_BOT; \ >- uint32_t DCN_VM_AGP_TOP; \ > uint32_t CURSOR_SETTINS; \ > uint32_t CURSOR_SETTINGS; \ > uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \ >@@ -249,7 +239,8 @@ > .field_name = reg_name ## __ ## field_name ## post_fix > > /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */ >-#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ >+/*1.x, 2.x, and 3.x*/ >+#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\ > HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ > HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ > HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ >@@ -265,7 +256,6 @@ > HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ > HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ > HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ >- HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ > HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ > HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ > HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ >@@ -372,12 +362,17 @@ > HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ > HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ > HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) >- >-#define HUBP_MASK_SH_LIST_DCN(mask_sh)\ >- HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh),\ >+/*2.x and 1.x only*/ >+#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ >+ HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ >+ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ > HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ > HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) > >+/*2.x and 1.x only*/ >+#define HUBP_MASK_SH_LIST_DCN(mask_sh)\ >+ HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh) >+ > /* Mask/shift struct generation macro for ASICs with VM */ > #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\ > HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ >@@ -412,8 +407,6 @@ > HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ > HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ > HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ >- HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\ >- HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ > HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ > HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ > HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ >@@ -434,7 +427,7 @@ > HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ > HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) > >-#define DCN_HUBP_REG_FIELD_LIST(type) \ >+#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \ > type HUBP_BLANK_EN;\ > type HUBP_DISABLE;\ > type HUBP_TTU_DISABLE;\ >@@ -459,7 +452,6 @@ > type ROTATION_ANGLE;\ > type H_MIRROR_EN;\ > type SURFACE_PIXEL_FORMAT;\ >- type ALPHA_PLANE_EN;\ > type SURFACE_FLIP_TYPE;\ > type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\ > type SURFACE_FLIP_IN_STEREOSYNC;\ >@@ -589,18 +581,6 @@ > type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\ > type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\ > type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\ >- type SDPIF_FB_TOP;\ >- type SDPIF_FB_BASE;\ >- type SDPIF_FB_OFFSET;\ >- type SDPIF_AGP_BASE;\ >- type SDPIF_AGP_BOT;\ >- type SDPIF_AGP_TOP;\ >- type FB_TOP;\ >- type FB_BASE;\ >- type FB_OFFSET;\ >- type AGP_BASE;\ >- type AGP_BOT;\ >- type AGP_TOP;\ > type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ > type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ > type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ >@@ -632,6 +612,10 @@ > type CURSOR_DST_X_OFFSET; \ > type OUTPUT_FP > >+#define DCN_HUBP_REG_FIELD_LIST(type) \ >+ DCN_HUBP_REG_FIELD_BASE_LIST(type);\ >+ type ALPHA_PLANE_EN >+ > struct dcn_mi_registers { > HUBP_COMMON_REG_VARIABLE_LIST; > }; >@@ -677,7 +661,7 @@ > struct hubp *hubp, > enum surface_pixel_format format, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > enum dc_rotation_angle rotation, > struct dc_plane_dcc_param *dcc, > bool horizontal_mirror, >@@ -699,7 +683,7 @@ > void hubp1_program_size( > struct hubp *hubp, > enum surface_pixel_format format, >- const union plane_size *plane_size, >+ const struct plane_size *plane_size, > struct dc_plane_dcc_param *dcc); > > void hubp1_program_rotation( >@@ -714,7 +698,7 @@ > > void hubp1_dcc_control(struct hubp *hubp, > bool enable, >- bool independent_64b_blks); >+ enum hubp_ind_block_size independent_64b_blks); > > #ifdef CONFIG_DRM_AMD_DC_DCN2_0 > bool hubp1_program_surface_flip_and_addr( >@@ -760,5 +744,6 @@ > struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); > > void hubp1_init(struct hubp *hubp); >+void hubp1_read_state_common(struct hubp *hubp); > > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 2019-08-31 15:01:11.863736169 -0500 >@@ -438,7 +438,7 @@ > return false; > } > >-static void enable_power_gating_plane( >+static void dcn10_enable_power_gating_plane( > struct dce_hwseq *hws, > bool enable) > { >@@ -460,7 +460,7 @@ > REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); > } > >-static void disable_vga( >+static void dcn10_disable_vga( > struct dce_hwseq *hws) > { > unsigned int in_vga1_mode = 0; >@@ -493,7 +493,7 @@ > REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1); > } > >-static void dpp_pg_control( >+static void dcn10_dpp_pg_control( > struct dce_hwseq *hws, > unsigned int dpp_inst, > bool power_on) >@@ -545,7 +545,7 @@ > } > } > >-static void hubp_pg_control( >+static void dcn10_hubp_pg_control( > struct dce_hwseq *hws, > unsigned int hubp_inst, > bool power_on) >@@ -605,8 +605,8 @@ > if (REG(DC_IP_REQUEST_CNTL)) { > REG_SET(DC_IP_REQUEST_CNTL, 0, > IP_REQUEST_EN, 1); >- dpp_pg_control(hws, plane_id, true); >- hubp_pg_control(hws, plane_id, true); >+ hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true); >+ hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true); > REG_SET(DC_IP_REQUEST_CNTL, 0, > IP_REQUEST_EN, 0); > DC_LOG_DEBUG( >@@ -627,7 +627,7 @@ > REG_SET(DC_IP_REQUEST_CNTL, 0, > IP_REQUEST_EN, 1); > >- hubp_pg_control(hws, 0, false); >+ dc->hwss.hubp_pg_control(hws, 0, false); > REG_SET(DC_IP_REQUEST_CNTL, 0, > IP_REQUEST_EN, 0); > >@@ -656,7 +656,7 @@ > REG_SET(DC_IP_REQUEST_CNTL, 0, > IP_REQUEST_EN, 1); > >- hubp_pg_control(hws, 0, true); >+ dc->hwss.hubp_pg_control(hws, 0, true); > REG_SET(DC_IP_REQUEST_CNTL, 0, > IP_REQUEST_EN, 0); > >@@ -664,10 +664,23 @@ > hws->wa_state.DEGVIDCN10_253_applied = true; > } > >-static void bios_golden_init(struct dc *dc) >+static void dcn10_bios_golden_init(struct dc *dc) > { > struct dc_bios *bp = dc->ctx->dc_bios; > int i; >+ bool allow_self_fresh_force_enable = true; >+ >+ if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) >+ allow_self_fresh_force_enable = >+ dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub); >+ >+ >+ /* WA for making DF sleep when idle after resume from S0i3. >+ * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by >+ * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 >+ * before calling command table and it changed to 1 after, >+ * it should be set back to 0. >+ */ > > /* initialize dcn global */ > bp->funcs->enable_disp_power_gating(bp, >@@ -678,6 +691,12 @@ > bp->funcs->enable_disp_power_gating(bp, > CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE); > } >+ >+ if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) >+ if (allow_self_fresh_force_enable == false && >+ dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub)) >+ dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true); >+ > } > > static void false_optc_underflow_wa( >@@ -702,7 +721,8 @@ > dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx); > } > >- tg->funcs->set_blank_data_double_buffer(tg, true); >+ if (tg->funcs->set_blank_data_double_buffer) >+ tg->funcs->set_blank_data_double_buffer(tg, true); > > if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow) > tg->funcs->clear_optc_underflow(tg); >@@ -808,11 +828,23 @@ > if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { > /* DPMS may already disable */ > if (!pipe_ctx->stream->dpms_off) >- core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); >- else if (pipe_ctx->stream_res.audio) { >- dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); >+ core_link_disable_stream(pipe_ctx); >+ else if (pipe_ctx->stream_res.audio) >+ dc->hwss.disable_audio_stream(pipe_ctx); >+ >+ if (pipe_ctx->stream_res.audio) { >+ /*disable az_endpoint*/ >+ pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); >+ >+ /*free audio*/ >+ if (dc->caps.dynamic_audio == true) { >+ /*we have to dynamic arbitrate the audio endpoints*/ >+ /*we free the resource, need reset is_audio_acquired*/ >+ update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, >+ pipe_ctx->stream_res.audio, false); >+ pipe_ctx->stream_res.audio = NULL; >+ } > } >- > } > > /* by upper caller loop, parent pipe: pipe0, will be reset last. >@@ -823,6 +855,9 @@ > pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); > > pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); >+ if (pipe_ctx->stream_res.tg->funcs->set_drr) >+ pipe_ctx->stream_res.tg->funcs->set_drr( >+ pipe_ctx->stream_res.tg, NULL); > } > > for (i = 0; i < dc->res_pool->pipe_count; i++) >@@ -968,7 +1003,7 @@ > dcn10_verify_allow_pstate_change_high(dc); > } > >-static void plane_atomic_power_down(struct dc *dc, >+static void dcn10_plane_atomic_power_down(struct dc *dc, > struct dpp *dpp, > struct hubp *hubp) > { >@@ -978,8 +1013,8 @@ > if (REG(DC_IP_REQUEST_CNTL)) { > REG_SET(DC_IP_REQUEST_CNTL, 0, > IP_REQUEST_EN, 1); >- dpp_pg_control(hws, dpp->inst, false); >- hubp_pg_control(hws, hubp->inst, false); >+ dc->hwss.dpp_pg_control(hws, dpp->inst, false); >+ dc->hwss.hubp_pg_control(hws, hubp->inst, false); > dpp->funcs->dpp_reset(dpp); > REG_SET(DC_IP_REQUEST_CNTL, 0, > IP_REQUEST_EN, 0); >@@ -991,7 +1026,7 @@ > /* disable HW used by plane. > * note: cannot disable until disconnect is complete > */ >-static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) >+static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) > { > struct hubp *hubp = pipe_ctx->plane_res.hubp; > struct dpp *dpp = pipe_ctx->plane_res.dpp; >@@ -1011,7 +1046,7 @@ > hubp->power_gated = true; > dc->optimized_required = false; /* We're powering off, no need to optimize */ > >- plane_atomic_power_down(dc, >+ dc->hwss.plane_atomic_power_down(dc, > pipe_ctx->plane_res.dpp, > pipe_ctx->plane_res.hubp); > >@@ -1030,7 +1065,7 @@ > if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) > return; > >- plane_atomic_disable(dc, pipe_ctx); >+ dc->hwss.plane_atomic_disable(dc, pipe_ctx); > > apply_DEGVIDCN10_253_wa(dc); > >@@ -1065,15 +1100,27 @@ > * command table. > */ > if (tg->funcs->is_tg_enabled(tg)) { >- tg->funcs->lock(tg); >- tg->funcs->set_blank(tg, true); >- hwss_wait_for_blank_complete(tg); >+ if (dc->hwss.init_blank != NULL) { >+ dc->hwss.init_blank(dc, tg); >+ tg->funcs->lock(tg); >+ } else { >+ tg->funcs->lock(tg); >+ tg->funcs->set_blank(tg, true); >+ hwss_wait_for_blank_complete(tg); >+ } > } > } > >- /* Cannot reset the MPC mux if seamless boot */ >- if (!can_apply_seamless_boot) >- dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc); >+ for (i = 0; i < dc->res_pool->pipe_count; i++) { >+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; >+ >+ /* Cannot reset the MPC mux if seamless boot */ >+ if (pipe_ctx->stream != NULL && can_apply_seamless_boot) >+ continue; >+ >+ dc->res_pool->mpc->funcs->mpc_init_single_inst( >+ dc->res_pool->mpc, i); >+ } > > for (i = 0; i < dc->res_pool->pipe_count; i++) { > struct timing_generator *tg = dc->res_pool->timing_generators[i]; >@@ -1111,12 +1158,12 @@ > dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; > pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; > >- hwss1_plane_atomic_disconnect(dc, pipe_ctx); >+ dc->hwss.plane_atomic_disconnect(dc, pipe_ctx); > > if (tg->funcs->is_tg_enabled(tg)) > tg->funcs->unlock(tg); > >- dcn10_disable_plane(dc, pipe_ctx); >+ dc->hwss.disable_plane(dc, pipe_ctx); > > pipe_ctx->stream_res.tg = NULL; > pipe_ctx->plane_res.hubp = NULL; >@@ -1132,8 +1179,17 @@ > struct dmcu *dmcu = dc->res_pool->dmcu; > struct dce_hwseq *hws = dc->hwseq; > struct dc_bios *dcb = dc->ctx->dc_bios; >+ struct resource_pool *res_pool = dc->res_pool; >+ >+ if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) >+ dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); >+ >+ // Initialize the dccg >+ if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init) >+ dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg); > > if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { >+ > REG_WRITE(REFCLK_CNTL, 0); > REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); > REG_WRITE(DIO_MEM_PWR_CTRL, 0); >@@ -1147,31 +1203,40 @@ > REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); > } > >- enable_power_gating_plane(dc->hwseq, true); >+ //Enable ability to power gate / don't force power on permanently >+ dc->hwss.enable_power_gating_plane(hws, true); > >- /* end of FPGA. Below if real ASIC */ > return; > } > >- if (!dcb->funcs->is_accelerated_mode(dcb)) { >- bool allow_self_fresh_force_enable = >- hububu1_is_allow_self_refresh_enabled( >- dc->res_pool->hubbub); >+ if (!dcb->funcs->is_accelerated_mode(dcb)) >+ dc->hwss.disable_vga(dc->hwseq); > >- bios_golden_init(dc); >+ dc->hwss.bios_golden_init(dc); >+ if (dc->ctx->dc_bios->fw_info_valid) { >+ res_pool->ref_clocks.xtalin_clock_inKhz = >+ dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; > >- /* WA for making DF sleep when idle after resume from S0i3. >- * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by >- * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 >- * before calling command table and it changed to 1 after, >- * it should be set back to 0. >- */ >- if (allow_self_fresh_force_enable == false && >- hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub)) >- hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true); >+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { >+ if (res_pool->dccg && res_pool->hubbub) { > >- disable_vga(dc->hwseq); >- } >+ (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, >+ dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, >+ &res_pool->ref_clocks.dccg_ref_clock_inKhz); >+ >+ (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, >+ res_pool->ref_clocks.dccg_ref_clock_inKhz, >+ &res_pool->ref_clocks.dchub_ref_clock_inKhz); >+ } else { >+ // Not all ASICs have DCCG sw component >+ res_pool->ref_clocks.dccg_ref_clock_inKhz = >+ res_pool->ref_clocks.xtalin_clock_inKhz; >+ res_pool->ref_clocks.dchub_ref_clock_inKhz = >+ res_pool->ref_clocks.xtalin_clock_inKhz; >+ } >+ } >+ } else >+ ASSERT_CRITICAL(false); > > for (i = 0; i < dc->link_count; i++) { > /* Power up AND update implementation according to the >@@ -1188,6 +1253,13 @@ > link->link_status.link_active = true; > } > >+ /* Power gate DSCs */ >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ for (i = 0; i < res_pool->res_cap->num_dsc; i++) >+ if (dc->hwss.dsc_pg_control != NULL) >+ dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); >+#endif >+ > /* If taking control over from VBIOS, we may want to optimize our first > * mode set, so we need to skip powering down pipes until we know which > * pipes we want to use. >@@ -1198,8 +1270,8 @@ > dc->hwss.init_pipes(dc, dc->current_state); > } > >- for (i = 0; i < dc->res_pool->audio_count; i++) { >- struct audio *audio = dc->res_pool->audios[i]; >+ for (i = 0; i < res_pool->audio_count; i++) { >+ struct audio *audio = res_pool->audios[i]; > > audio->funcs->hw_init(audio); > } >@@ -1227,9 +1299,7 @@ > REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); > } > >- enable_power_gating_plane(dc->hwseq, true); >- >- memset(&dc->clk_mgr->clks, 0, sizeof(dc->clk_mgr->clks)); >+ dc->hwss.enable_power_gating_plane(dc->hwseq, true); > } > > static void dcn10_reset_hw_ctx_wrap( >@@ -1366,6 +1436,34 @@ > return result; > } > >+#define MAX_NUM_HW_POINTS 0x200 >+ >+static void log_tf(struct dc_context *ctx, >+ struct dc_transfer_func *tf, uint32_t hw_points_num) >+{ >+ // DC_LOG_GAMMA is default logging of all hw points >+ // DC_LOG_ALL_GAMMA logs all points, not only hw points >+ // DC_LOG_ALL_TF_POINTS logs all channels of the tf >+ int i = 0; >+ >+ DC_LOGGER_INIT(ctx->logger); >+ DC_LOG_GAMMA("Gamma Correction TF"); >+ DC_LOG_ALL_GAMMA("Logging all tf points..."); >+ DC_LOG_ALL_TF_CHANNELS("Logging all channels..."); >+ >+ for (i = 0; i < hw_points_num; i++) { >+ DC_LOG_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value); >+ DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value); >+ DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value); >+ } >+ >+ for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) { >+ DC_LOG_ALL_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value); >+ DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value); >+ DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value); >+ } >+} >+ > static bool > dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, > const struct dc_stream_state *stream) >@@ -1394,6 +1492,13 @@ > } else > dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); > >+ if (stream != NULL && stream->ctx != NULL && >+ stream->out_transfer_func != NULL) { >+ log_tf(stream->ctx, >+ stream->out_transfer_func, >+ dpp->regamma_params.hw_points_num); >+ } >+ > return true; > } > >@@ -1786,7 +1891,7 @@ > } > } > >-static void program_gamut_remap(struct pipe_ctx *pipe_ctx) >+static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx) > { > int i = 0; > struct dpp_grph_csc_adjustment adjust; >@@ -1804,6 +1909,36 @@ > pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust); > } > >+ >+static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace) >+{ >+ if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) { >+ if (pipe_ctx->top_pipe) { >+ struct pipe_ctx *top = pipe_ctx->top_pipe; >+ >+ while (top->top_pipe) >+ top = top->top_pipe; // Traverse to top pipe_ctx >+ if (top->plane_state && top->plane_state->layer_index == 0) >+ return true; // Front MPO plane not hidden >+ } >+ } >+ return false; >+} >+ >+static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix) >+{ >+ // Override rear plane RGB bias to fix MPO brightness >+ uint16_t rgb_bias = matrix[3]; >+ >+ matrix[3] = 0; >+ matrix[7] = 0; >+ matrix[11] = 0; >+ pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); >+ matrix[3] = rgb_bias; >+ matrix[7] = rgb_bias; >+ matrix[11] = rgb_bias; >+} >+ > static void dcn10_program_output_csc(struct dc *dc, > struct pipe_ctx *pipe_ctx, > enum dc_color_space colorspace, >@@ -1811,8 +1946,25 @@ > int opp_id) > { > if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { >- if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) >- pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); >+ if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) { >+ >+ /* MPO is broken with RGB colorspaces when OCSC matrix >+ * brightness offset >= 0 on DCN1 due to OCSC before MPC >+ * Blending adds offsets from front + rear to rear plane >+ * >+ * Fix is to set RGB bias to 0 on rear plane, top plane >+ * black value pixels add offset instead of rear + front >+ */ >+ >+ int16_t rgb_bias = matrix[3]; >+ // matrix[3/7/11] are all the same offset value >+ >+ if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) { >+ dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix); >+ } else { >+ pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); >+ } >+ } > } else { > if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL) > pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); >@@ -2132,7 +2284,7 @@ > struct hubp *hubp = pipe_ctx->plane_res.hubp; > struct dpp *dpp = pipe_ctx->plane_res.dpp; > struct dc_plane_state *plane_state = pipe_ctx->plane_state; >- union plane_size size = plane_state->plane_size; >+ struct plane_size size = plane_state->plane_size; > unsigned int compat_level = 0; > > /* depends on DML calculation, DPP clock value may change dynamically */ >@@ -2152,7 +2304,8 @@ > dc->res_pool->dccg->funcs->update_dpp_dto( > dc->res_pool->dccg, > dpp->inst, >- pipe_ctx->plane_res.bw.dppclk_khz); >+ pipe_ctx->plane_res.bw.dppclk_khz, >+ false); > else > dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ? > dc->clk_mgr->clks.dispclk_khz / 2 : >@@ -2178,7 +2331,7 @@ > &pipe_ctx->ttu_regs); > } > >- size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; >+ size.surface_size = pipe_ctx->plane_res.scl_data.viewport; > > if (plane_state->update_flags.bits.full_update || > plane_state->update_flags.bits.bpp_change) >@@ -2216,7 +2369,7 @@ > > if (plane_state->update_flags.bits.full_update) { > /*gamut remap*/ >- program_gamut_remap(pipe_ctx); >+ dc->hwss.program_gamut_remap(pipe_ctx); > > dc->hwss.program_output_csc(dc, > pipe_ctx, >@@ -2388,7 +2541,7 @@ > if (pipe_ctx->stream != stream) > continue; > >- if (!pipe_ctx->top_pipe) >+ if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) > return pipe_ctx; > } > return NULL; >@@ -2453,7 +2606,7 @@ > if (old_pipe_ctx->stream_res.tg == tg && > old_pipe_ctx->plane_res.hubp && > old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) >- dcn10_disable_plane(dc, old_pipe_ctx); >+ dc->hwss.disable_plane(dc, old_pipe_ctx); > } > > if ((!pipe_ctx->plane_state || >@@ -2501,7 +2654,7 @@ > > for (i = 0; i < dc->res_pool->pipe_count; i++) > if (removed_pipe[i]) >- dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); >+ dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); > > for (i = 0; i < dc->res_pool->pipe_count; i++) > if (removed_pipe[i]) { >@@ -2593,8 +2746,9 @@ > dcn10_verify_allow_pstate_change_high(dc); > } > >-static void set_drr(struct pipe_ctx **pipe_ctx, >- int num_pipes, int vmin, int vmax) >+static void dcn10_set_drr(struct pipe_ctx **pipe_ctx, >+ int num_pipes, unsigned int vmin, unsigned int vmax, >+ unsigned int vmid, unsigned int vmid_frame_number) > { > int i = 0; > struct drr_params params = {0}; >@@ -2603,6 +2757,8 @@ > > params.vertical_total_max = vmax; > params.vertical_total_min = vmin; >+ params.vertical_total_mid = vmid; >+ params.vertical_total_mid_frame_num = vmid_frame_number; > > /* TODO: If multiple pipes are to be supported, you need > * some GSL stuff. Static screen triggers may be programmed differently >@@ -2618,7 +2774,7 @@ > } > } > >-static void get_position(struct pipe_ctx **pipe_ctx, >+static void dcn10_get_position(struct pipe_ctx **pipe_ctx, > int num_pipes, > struct crtc_position *position) > { >@@ -2630,7 +2786,7 @@ > pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); > } > >-static void set_static_screen_control(struct pipe_ctx **pipe_ctx, >+static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, > int num_pipes, const struct dc_static_screen_events *events) > { > unsigned int i; >@@ -2692,6 +2848,13 @@ > > dcn10_config_stereo_parameters(stream, &flags); > >+ if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) { >+ if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service)) >+ dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service); >+ } else { >+ dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service); >+ } >+ > pipe_ctx->stream_res.opp->funcs->opp_program_stereo( > pipe_ctx->stream_res.opp, > flags.PROGRAM_STEREO == 1 ? true:false, >@@ -2782,14 +2945,10 @@ > > static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) > { >- if (hws->ctx->dc->res_pool->hubbub != NULL) { >- struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0]; >+ struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub; > >- if (hubp->funcs->hubp_update_dchub) >- hubp->funcs->hubp_update_dchub(hubp, dh_data); >- else >- hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); >- } >+ /* In DCN, this programming sequence is owned by the hubbub */ >+ hubbub->funcs->update_dchub(hubbub, dh_data); > } > > static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) >@@ -2820,6 +2979,40 @@ > == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) > pos_cpy.enable = false; > >+ // Swap axis and mirror horizontally >+ if (param.rotation == ROTATION_ANGLE_90) { >+ uint32_t temp_x = pos_cpy.x; >+ pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width - >+ (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x; >+ pos_cpy.y = temp_x; >+ } >+ // Swap axis and mirror vertically >+ else if (param.rotation == ROTATION_ANGLE_270) { >+ uint32_t temp_y = pos_cpy.y; >+ if (pos_cpy.x > pipe_ctx->plane_res.scl_data.viewport.height) { >+ pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height; >+ pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x; >+ } else { >+ pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x; >+ } >+ pos_cpy.x = temp_y; >+ } >+ // Mirror horizontally and vertically >+ else if (param.rotation == ROTATION_ANGLE_180) { >+ if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) { >+ pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width >+ - pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x; >+ } else { >+ uint32_t temp_x = pos_cpy.x; >+ pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x; >+ if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width >+ || pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) { >+ pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width; >+ } >+ } >+ pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y; >+ } >+ > hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m); > dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height); > } >@@ -2831,7 +3024,7 @@ > pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes( > pipe_ctx->plane_res.hubp, attributes); > pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( >- pipe_ctx->plane_res.dpp, attributes->color_format); >+ pipe_ctx->plane_res.dpp, attributes); > } > > static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx) >@@ -3062,9 +3255,59 @@ > sdp_message_size); > } > } >+static enum dc_status dcn10_set_clock(struct dc *dc, >+ enum dc_clock_type clock_type, >+ uint32_t clk_khz, >+ uint32_t stepping) >+{ >+ struct dc_state *context = dc->current_state; >+ struct dc_clock_config clock_cfg = {0}; >+ struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk; >+ >+ if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock) >+ dc->clk_mgr->funcs->get_clock(dc->clk_mgr, >+ context, clock_type, &clock_cfg); >+ >+ if (!dc->clk_mgr->funcs->get_clock) >+ return DC_FAIL_UNSUPPORTED_1; >+ >+ if (clk_khz > clock_cfg.max_clock_khz) >+ return DC_FAIL_CLK_EXCEED_MAX; >+ >+ if (clk_khz < clock_cfg.min_clock_khz) >+ return DC_FAIL_CLK_BELOW_MIN; >+ >+ if (clk_khz < clock_cfg.bw_requirequired_clock_khz) >+ return DC_FAIL_CLK_BELOW_CFG_REQUIRED; >+ >+ /*update internal request clock for update clock use*/ >+ if (clock_type == DC_CLOCK_TYPE_DISPCLK) >+ current_clocks->dispclk_khz = clk_khz; >+ else if (clock_type == DC_CLOCK_TYPE_DPPCLK) >+ current_clocks->dppclk_khz = clk_khz; >+ else >+ return DC_ERROR_UNEXPECTED; >+ >+ if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks) >+ dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, >+ context, true); >+ return DC_OK; >+ >+} >+ >+static void dcn10_get_clock(struct dc *dc, >+ enum dc_clock_type clock_type, >+ struct dc_clock_config *clock_cfg) >+{ >+ struct dc_state *context = dc->current_state; >+ >+ if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock) >+ dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg); >+ >+} > > static const struct hw_sequencer_funcs dcn10_funcs = { >- .program_gamut_remap = program_gamut_remap, >+ .program_gamut_remap = dcn10_program_gamut_remap, > .init_hw = dcn10_init_hw, > .init_pipes = dcn10_init_pipes, > .apply_ctx_to_hw = dce110_apply_ctx_to_hw, >@@ -3097,18 +3340,18 @@ > .optimize_bandwidth = dcn10_optimize_bandwidth, > .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap, > .enable_stream_timing = dcn10_enable_stream_timing, >- .set_drr = set_drr, >- .get_position = get_position, >- .set_static_screen_control = set_static_screen_control, >+ .set_drr = dcn10_set_drr, >+ .get_position = dcn10_get_position, >+ .set_static_screen_control = dcn10_set_static_screen_control, > .setup_stereo = dcn10_setup_stereo, > .set_avmute = dce110_set_avmute, > .log_hw_state = dcn10_log_hw_state, > .get_hw_state = dcn10_get_hw_state, > .clear_status_bits = dcn10_clear_status_bits, > .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, >- .edp_backlight_control = hwss_edp_backlight_control, >- .edp_power_control = hwss_edp_power_control, >- .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, >+ .edp_backlight_control = dce110_edp_backlight_control, >+ .edp_power_control = dce110_edp_power_control, >+ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, > .set_cursor_position = dcn10_set_cursor_position, > .set_cursor_attribute = dcn10_set_cursor_attribute, > .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, >@@ -3116,7 +3359,18 @@ > .enable_stream_gating = NULL, > .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, > .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt, >- .did_underflow_occur = dcn10_did_underflow_occur >+ .set_clock = dcn10_set_clock, >+ .get_clock = dcn10_get_clock, >+ .did_underflow_occur = dcn10_did_underflow_occur, >+ .init_blank = NULL, >+ .disable_vga = dcn10_disable_vga, >+ .bios_golden_init = dcn10_bios_golden_init, >+ .plane_atomic_disable = dcn10_plane_atomic_disable, >+ .plane_atomic_power_down = dcn10_plane_atomic_power_down, >+ .enable_power_gating_plane = dcn10_enable_power_gating_plane, >+ .dpp_pg_control = dcn10_dpp_pg_control, >+ .hubp_pg_control = dcn10_hubp_pg_control, >+ .dsc_pg_control = NULL, > }; > > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 2019-08-31 15:01:11.863736169 -0500 >@@ -45,7 +45,7 @@ > #include "dcn10_cm_common.h" > #include "clk_mgr.h" > >-static unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...) >+unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...) > { > unsigned int ret_vsnprintf; > unsigned int chars_printed; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 2019-08-31 15:01:11.863736169 -0500 >@@ -89,6 +89,7 @@ > .disable_hpd = dcn10_link_encoder_disable_hpd, > .is_dig_enabled = dcn10_is_dig_enabled, > .get_dig_frontend = dcn10_get_dig_frontend, >+ .get_dig_mode = dcn10_get_dig_mode, > .destroy = dcn10_link_encoder_destroy > }; > >@@ -446,6 +447,46 @@ > } > } > >+unsigned int dcn10_get_dig_frontend(struct link_encoder *enc) >+{ >+ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); >+ int32_t value; >+ enum engine_id result; >+ >+ REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); >+ >+ switch (value) { >+ case DCN10_DIG_FE_SOURCE_SELECT_DIGA: >+ result = ENGINE_ID_DIGA; >+ break; >+ case DCN10_DIG_FE_SOURCE_SELECT_DIGB: >+ result = ENGINE_ID_DIGB; >+ break; >+ case DCN10_DIG_FE_SOURCE_SELECT_DIGC: >+ result = ENGINE_ID_DIGC; >+ break; >+ case DCN10_DIG_FE_SOURCE_SELECT_DIGD: >+ result = ENGINE_ID_DIGD; >+ break; >+ case DCN10_DIG_FE_SOURCE_SELECT_DIGE: >+ result = ENGINE_ID_DIGE; >+ break; >+ case DCN10_DIG_FE_SOURCE_SELECT_DIGF: >+ result = ENGINE_ID_DIGF; >+ break; >+ case DCN10_DIG_FE_SOURCE_SELECT_DIGG: >+ result = ENGINE_ID_DIGG; >+ break; >+ default: >+ // invalid source select DIG >+ ASSERT(false); >+ result = ENGINE_ID_UNKNOWN; >+ } >+ >+ return result; >+ >+} >+ > void enc1_configure_encoder( > struct dcn10_link_encoder *enc10, > const struct dc_link_settings *link_settings) >@@ -501,15 +542,6 @@ > return value; > } > >-unsigned int dcn10_get_dig_frontend(struct link_encoder *enc) >-{ >- struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); >- uint32_t value; >- >- REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); >- return value; >-} >- > static void link_encoder_disable(struct dcn10_link_encoder *enc10) > { > /* reset training pattern */ >@@ -1366,3 +1398,25 @@ > AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0, > AUX_RX_RECEIVE_WINDOW, 0); > } >+ >+enum signal_type dcn10_get_dig_mode( >+ struct link_encoder *enc) >+{ >+ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); >+ uint32_t value; >+ REG_GET(DIG_BE_CNTL, DIG_MODE, &value); >+ switch (value) { >+ case 1: >+ return SIGNAL_TYPE_DISPLAY_PORT; >+ case 2: >+ return SIGNAL_TYPE_DVI_SINGLE_LINK; >+ case 3: >+ return SIGNAL_TYPE_HDMI_TYPE_A; >+ case 5: >+ return SIGNAL_TYPE_DISPLAY_PORT_MST; >+ default: >+ return SIGNAL_TYPE_NONE; >+ } >+ return SIGNAL_TYPE_NONE; >+} >+ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 2019-08-31 15:01:11.863736169 -0500 >@@ -337,6 +337,7 @@ > type RDPCS_TX_FIFO_ERROR_MASK;\ > type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\ > type RDPCS_DPALT_4LANE_TOGGLE_MASK;\ >+ type RDPCS_PHY_DPALT_DISABLE;\ > type RDPCS_PHY_DPALT_DISABLE_ACK;\ > type RDPCS_PHY_DP_MPLLB_V2I;\ > type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\ >@@ -514,4 +515,6 @@ > > void dcn10_aux_initialize(struct dcn10_link_encoder *enc10); > >+enum signal_type dcn10_get_dig_mode( >+ struct link_encoder *enc); > #endif /* __DC_LINK_ENCODER__DCN10_H__ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 2019-08-31 15:01:11.863736169 -0500 >@@ -211,7 +211,7 @@ > } else { > new_mpcc->mpcc_bot = NULL; > REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); >- REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH); >+ REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY); > } > REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); > REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); >@@ -364,6 +364,24 @@ > } > } > >+void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) >+{ >+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); >+ int opp_id; >+ >+ REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); >+ >+ REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); >+ REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); >+ REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); >+ >+ mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id); >+ >+ if (opp_id < MAX_OPP && REG(MUX[opp_id])) >+ REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf); >+} >+ >+ > void mpc1_init_mpcc_list_from_hw( > struct mpc *mpc, > struct mpc_tree *tree) >@@ -433,6 +451,7 @@ > .insert_plane = mpc1_insert_plane, > .remove_mpcc = mpc1_remove_mpcc, > .mpc_init = mpc1_mpc_init, >+ .mpc_init_single_inst = mpc1_mpc_init_single_inst, > .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, > .wait_for_idle = mpc1_assert_idle_mpcc, > .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 2019-08-31 15:01:11.863736169 -0500 >@@ -149,6 +149,10 @@ > void mpc1_mpc_init( > struct mpc *mpc); > >+void mpc1_mpc_init_single_inst( >+ struct mpc *mpc, >+ unsigned int mpcc_id); >+ > void mpc1_assert_idle_mpcc( > struct mpc *mpc, > int id); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 2019-08-31 15:01:11.863736169 -0500 >@@ -154,7 +154,7 @@ > uint32_t h_sync_polarity, v_sync_polarity; > uint32_t start_point = 0; > uint32_t field_num = 0; >- uint32_t h_div_2; >+ enum h_timing_div_mode h_div = H_TIMING_NO_DIV; > > struct optc *optc1 = DCN10TG_FROM_TG(optc); > >@@ -285,10 +285,11 @@ > * of stereo handled in explicit call > */ > >- h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing); >- REG_UPDATE(OTG_H_TIMING_CNTL, >- OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf); >+ if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) >+ h_div = H_TIMING_DIV_BY2; > >+ REG_UPDATE(OTG_H_TIMING_CNTL, >+ OTG_H_TIMING_DIV_BY2, h_div); > } > > void optc1_set_vtg_params(struct timing_generator *optc, >@@ -824,6 +825,9 @@ > > REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, > MANUAL_FLOW_CONTROL, 1); >+ >+ REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, >+ MANUAL_FLOW_CONTROL, 0); > } > > >@@ -846,6 +850,18 @@ > params->vertical_total_max > 0 && > params->vertical_total_min > 0) { > >+ if (params->vertical_total_mid != 0) { >+ >+ REG_SET(OTG_V_TOTAL_MID, 0, >+ OTG_V_TOTAL_MID, params->vertical_total_mid - 1); >+ >+ REG_UPDATE_2(OTG_V_TOTAL_CONTROL, >+ OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, >+ OTG_VTOTAL_MID_FRAME_NUM, >+ (uint8_t)params->vertical_total_mid_frame_num); >+ >+ } >+ > REG_SET(OTG_V_TOTAL_MAX, 0, > OTG_V_TOTAL_MAX, params->vertical_total_max - 1); > >@@ -1513,7 +1529,6 @@ > optc1->min_v_blank_interlace = 5; > optc1->min_h_sync_width = 8; > optc1->min_v_sync_width = 1; >- optc1->comb_opp_id = 0xf; > } > > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 2019-08-31 15:01:11.863736169 -0500 >@@ -54,6 +54,7 @@ > SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ > SRI(OTG_STEREO_STATUS, OTG, inst),\ > SRI(OTG_V_TOTAL_MAX, OTG, inst),\ >+ SRI(OTG_V_TOTAL_MID, OTG, inst),\ > SRI(OTG_V_TOTAL_MIN, OTG, inst),\ > SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ > SRI(OTG_TRIGA_CNTL, OTG, inst),\ >@@ -125,6 +126,7 @@ > uint32_t OTG_3D_STRUCTURE_CONTROL; > uint32_t OTG_STEREO_STATUS; > uint32_t OTG_V_TOTAL_MAX; >+ uint32_t OTG_V_TOTAL_MID; > uint32_t OTG_V_TOTAL_MIN; > uint32_t OTG_V_TOTAL_CONTROL; > uint32_t OTG_TRIGA_CNTL; >@@ -214,12 +216,15 @@ > SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ > SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ > SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ >+ SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ > SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ > SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ > SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ > SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ > SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ > SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ >+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ >+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ > SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ > SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ > SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ >@@ -348,9 +353,12 @@ > type OTG_3D_STRUCTURE_V_UPDATE_MODE;\ > type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\ > type OTG_V_TOTAL_MAX;\ >+ type OTG_V_TOTAL_MID;\ > type OTG_V_TOTAL_MIN;\ > type OTG_V_TOTAL_MIN_SEL;\ > type OTG_V_TOTAL_MAX_SEL;\ >+ type OTG_VTOTAL_MID_REPLACING_MAX_EN;\ >+ type OTG_VTOTAL_MID_FRAME_NUM;\ > type OTG_FORCE_LOCK_ON_EVENT;\ > type OTG_SET_V_TOTAL_MIN_MASK_EN;\ > type OTG_SET_V_TOTAL_MIN_MASK;\ >@@ -494,7 +502,7 @@ > const struct dcn_optc_shift *tg_shift; > const struct dcn_optc_mask *tg_mask; > >- int comb_opp_id; >+ int opp_count; > > uint32_t max_h_total; > uint32_t max_v_total; >@@ -539,6 +547,10 @@ > void optc1_read_otg_state(struct optc *optc1, > struct dcn_otg_state *s); > >+bool optc1_is_matching_timing( >+ struct timing_generator *tg, >+ const struct dc_crtc_timing *otg_timing); >+ > bool optc1_validate_timing( > struct timing_generator *optc, > const struct dc_crtc_timing *timing); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 2019-08-31 15:01:11.864736169 -0500 >@@ -270,7 +270,7 @@ > DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) > }; > >-static const struct dce_aduio_mask audio_mask = { >+static const struct dce_audio_mask audio_mask = { > DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) > }; > >@@ -1416,6 +1416,14 @@ > > pool->base.pp_smu = dcn10_pp_smu_create(ctx); > >+ /* >+ * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * >+ * implemented. So AZ D3 should work.For issue 197007. * >+ */ >+ if (pool->base.pp_smu != NULL >+ && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) >+ dc->debug.az_endpoint_mute_only = false; >+ > if (!dc->debug.disable_pplib_clock_request) > dcn_bw_update_from_pplib(dc); > dcn_bw_sync_calcs_and_dml(dc); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 2019-08-31 15:01:11.864736169 -0500 >@@ -512,11 +512,12 @@ > enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); > > /* setup HDMI engine */ >- REG_UPDATE_5(HDMI_CONTROL, >+ REG_UPDATE_6(HDMI_CONTROL, > HDMI_PACKET_GEN_VERSION, 1, > HDMI_KEEPOUT_MODE, 1, > HDMI_DEEP_COLOR_ENABLE, 0, > HDMI_DATA_SCRAMBLE_EN, 0, >+ HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, > HDMI_CLOCK_CHANNEL_RATE, 0); > > >@@ -1003,6 +1004,19 @@ > REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); > } > >+void enc1_reset_hdmi_stream_attribute( >+ struct stream_encoder *enc) >+{ >+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); >+ >+ REG_UPDATE_5(HDMI_CONTROL, >+ HDMI_PACKET_GEN_VERSION, 1, >+ HDMI_KEEPOUT_MODE, 1, >+ HDMI_DEEP_COLOR_ENABLE, 0, >+ HDMI_DATA_SCRAMBLE_EN, 0, >+ HDMI_CLOCK_CHANNEL_RATE, 0); >+} >+ > > #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 > #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 >@@ -1196,13 +1210,13 @@ > > void get_audio_clock_info( > enum dc_color_depth color_depth, >- uint32_t crtc_pixel_clock_in_khz, >- uint32_t actual_pixel_clock_in_khz, >+ uint32_t crtc_pixel_clock_100Hz, >+ uint32_t actual_pixel_clock_100Hz, > struct audio_clock_info *audio_clock_info) > { > const struct audio_clock_info *clock_info; > uint32_t index; >- uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; >+ uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; > uint32_t audio_array_size; > > switch (color_depth) { >@@ -1239,16 +1253,16 @@ > } > > /* not found */ >- if (actual_pixel_clock_in_khz == 0) >- actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; >+ if (actual_pixel_clock_100Hz == 0) >+ actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; > > /* See HDMI spec the table entry under > * pixel clock of "Other". */ > audio_clock_info->pixel_clock_in_10khz = >- actual_pixel_clock_in_khz / 10; >- audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; >- audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; >- audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; >+ actual_pixel_clock_100Hz / 100; >+ audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; >+ audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; >+ audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; > > audio_clock_info->n_32khz = 4096; > audio_clock_info->n_44khz = 6272; >@@ -1308,14 +1322,14 @@ > > /* Program audio clock sample/regeneration parameters */ > get_audio_clock_info(crtc_info->color_depth, >- crtc_info->requested_pixel_clock, >- crtc_info->calculated_pixel_clock, >+ crtc_info->requested_pixel_clock_100Hz, >+ crtc_info->calculated_pixel_clock_100Hz, > &audio_clock_info); > DC_LOG_HW_AUDIO( >- "\n%s:Input::requested_pixel_clock = %d" \ >- "calculated_pixel_clock = %d \n", __func__, \ >- crtc_info->requested_pixel_clock, \ >- crtc_info->calculated_pixel_clock); >+ "\n%s:Input::requested_pixel_clock_100Hz = %d" \ >+ "calculated_pixel_clock_100Hz = %d \n", __func__, \ >+ crtc_info->requested_pixel_clock_100Hz, \ >+ crtc_info->calculated_pixel_clock_100Hz); > > /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ > REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); >@@ -1528,6 +1542,17 @@ > REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); > } > >+unsigned int enc1_dig_source_otg( >+ struct stream_encoder *enc) >+{ >+ uint32_t tg_inst = 0; >+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); >+ >+ REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); >+ >+ return tg_inst; >+} >+ > static const struct stream_encoder_funcs dcn10_str_enc_funcs = { > .dp_set_stream_attribute = > enc1_stream_encoder_dp_set_stream_attribute, >@@ -1562,6 +1587,8 @@ > .setup_stereo_sync = enc1_setup_stereo_sync, > .set_avmute = enc1_stream_encoder_set_avmute, > .dig_connect_to_otg = enc1_dig_connect_to_otg, >+ .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, >+ .dig_source_otg = enc1_dig_source_otg, > }; > > void dcn10_stream_encoder_construct( >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 2019-08-31 15:01:11.864736169 -0500 >@@ -89,7 +89,8 @@ > SRI(DP_VID_STREAM_CNTL, DP, id), \ > SRI(DP_VID_TIMING, DP, id), \ > SRI(DP_SEC_AUD_N, DP, id), \ >- SRI(DP_SEC_TIMESTAMP, DP, id) >+ SRI(DP_SEC_TIMESTAMP, DP, id), \ >+ SRI(DIG_CLOCK_PATTERN, DIG, id) > > #define SE_DCN_REG_LIST(id)\ > SE_COMMON_DCN_REG_LIST(id) >@@ -170,6 +171,7 @@ > uint32_t HDMI_METADATA_PACKET_CONTROL; > uint32_t DP_SEC_FRAMING4; > #endif >+ uint32_t DIG_CLOCK_PATTERN; > }; > > >@@ -189,6 +191,7 @@ > SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ > SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ > SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ >+ SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\ > SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ > SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ > SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ >@@ -297,7 +300,8 @@ > SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ > SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ > SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\ >- SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh) >+ SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\ >+ SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) > > #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ > SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) >@@ -374,6 +378,7 @@ > type HDMI_GC_SEND;\ > type HDMI_NULL_SEND;\ > type HDMI_DATA_SCRAMBLE_EN;\ >+ type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\ > type HDMI_AUDIO_INFO_SEND;\ > type AFMT_AUDIO_INFO_UPDATE;\ > type HDMI_AUDIO_INFO_LINE;\ >@@ -458,7 +463,8 @@ > type HDMI_DB_DISABLE;\ > type DP_VID_N_MUL;\ > type DP_VID_M_DOUBLE_VALUE_EN;\ >- type DIG_SOURCE_SELECT >+ type DIG_SOURCE_SELECT;\ >+ type DIG_CLOCK_PATTERN > > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #define SE_REG_FIELD_LIST_DCN2_0(type) \ >@@ -592,6 +598,9 @@ > struct stream_encoder *enc, > int tg_inst); > >+unsigned int enc1_dig_source_otg( >+ struct stream_encoder *enc); >+ > void enc1_stream_encoder_set_stream_attribute_helper( > struct dcn10_stream_encoder *enc1, > struct dc_crtc_timing *crtc_timing); >@@ -605,8 +614,11 @@ > > void get_audio_clock_info( > enum dc_color_depth color_depth, >- uint32_t crtc_pixel_clock_in_khz, >- uint32_t actual_pixel_clock_in_khz, >+ uint32_t crtc_pixel_clock_100Hz, >+ uint32_t actual_pixel_clock_100Hz, > struct audio_clock_info *audio_clock_info); > >+void enc1_reset_hdmi_stream_attribute( >+ struct stream_encoder *enc); >+ > #endif /* __DC_STREAM_ENCODER_DCN10_H__ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 2019-08-31 15:01:11.864736169 -0500 >@@ -44,12 +44,16 @@ > #define DC_LOGGER \ > dccg->ctx->logger > >-void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) >+void dccg2_update_dpp_dto(struct dccg *dccg, >+ int dpp_inst, >+ int req_dppclk, >+ bool reduce_divider_only) > { > struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); > > if (dccg->ref_dppclk && req_dppclk) { > int ref_dppclk = dccg->ref_dppclk; >+ int current_phase, current_modulo; > > ASSERT(req_dppclk <= ref_dppclk); > /* need to clamp to 8 bits */ >@@ -61,9 +65,28 @@ > if (req_dppclk > ref_dppclk) > req_dppclk = ref_dppclk; > } >- REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, >- DPPCLK0_DTO_PHASE, req_dppclk, >- DPPCLK0_DTO_MODULO, ref_dppclk); >+ >+ REG_GET_2(DPPCLK_DTO_PARAM[dpp_inst], >+ DPPCLK0_DTO_PHASE, ¤t_phase, >+ DPPCLK0_DTO_MODULO, ¤t_modulo); >+ >+ if (reduce_divider_only) { >+ // requested phase/modulo greater than current >+ if (req_dppclk * current_modulo >= current_phase * ref_dppclk) { >+ REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, >+ DPPCLK0_DTO_PHASE, req_dppclk, >+ DPPCLK0_DTO_MODULO, ref_dppclk); >+ } else { >+ REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, >+ DPPCLK0_DTO_PHASE, current_phase, >+ DPPCLK0_DTO_MODULO, current_modulo); >+ } >+ } else { >+ REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, >+ DPPCLK0_DTO_PHASE, req_dppclk, >+ DPPCLK0_DTO_MODULO, ref_dppclk); >+ } >+ > REG_UPDATE(DPPCLK_DTO_CTRL, > DPPCLK_DTO_ENABLE[dpp_inst], 1); > } else { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 2019-08-31 15:01:11.864736169 -0500 >@@ -97,7 +97,7 @@ > const struct dccg_mask *dccg_mask; > }; > >-void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); >+void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk, bool raise_divider_only); > > void dccg2_get_dccg_ref_freq(struct dccg *dccg, > unsigned int xtalin_freq_inKhz, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 2019-08-31 15:01:11.864736169 -0500 >@@ -72,6 +72,21 @@ > } > } > >+void dpp2_power_on_obuf( >+ struct dpp *dpp_base, >+ bool power_on) >+{ >+ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); >+ >+ REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); >+ >+ REG_UPDATE(OBUF_MEM_PWR_CTRL, >+ OBUF_MEM_PWR_FORCE, power_on == true ? 0:1); >+ >+ REG_UPDATE(DSCL_MEM_PWR_CTRL, >+ LUT_MEM_PWR_FORCE, power_on == true ? 0:1); >+} >+ > void dpp2_dummy_program_input_lut( > struct dpp *dpp_base, > const struct dc_gamma *gamma) >@@ -227,6 +242,7 @@ > CUR0_ENABLE, 0); > > } >+ dpp2_power_on_obuf(dpp_base, true); > > } > >@@ -326,14 +342,18 @@ > > void dpp2_set_cursor_attributes( > struct dpp *dpp_base, >- enum dc_cursor_color_format color_format) >+ struct dc_cursor_attributes *cursor_attributes) > { >+ enum dc_cursor_color_format color_format = cursor_attributes->color_format; > struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); > int cur_rom_en = 0; > > if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || >- color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) >- cur_rom_en = 1; >+ color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { >+ if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) { >+ cur_rom_en = 1; >+ } >+ } > > REG_UPDATE_3(CURSOR0_CONTROL, > CUR0_MODE, color_format, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 2019-08-31 15:01:11.865736169 -0500 >@@ -52,7 +52,12 @@ > { > struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); > >- REG_UPDATE(CM_CONTROL, CM_BYPASS, 0); >+ unsigned int cm_bypass_mode = 0; >+ //Temp, put CM in bypass mode >+ if (dpp_base->ctx->dc->debug.cm_in_bypass) >+ cm_bypass_mode = 1; >+ >+ REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode); > } > > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 2019-08-31 15:01:11.864736169 -0500 >@@ -162,7 +162,9 @@ > SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \ > SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \ > SRI(CM_SHAPER_LUT_DATA, CM, id), \ >- SRI(CURSOR_CONTROL, CURSOR0_, id) >+ SRI(CURSOR_CONTROL, CURSOR0_, id),\ >+ SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\ >+ SRI(DSCL_MEM_PWR_CTRL, DSCL, id) > > #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\ > TF_REG_LIST_SH_MASK_DCN(mask_sh), \ >@@ -554,7 +556,9 @@ > TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \ > TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ > TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ >- TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh) >+ TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\ >+ TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\ >+ TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh) > > #define TF_REG_FIELD_LIST_DCN2_0(type) \ > TF_REG_FIELD_LIST(type) \ >@@ -585,7 +589,9 @@ > type COLOR_KEYER_BLUE_HIGH; \ > type CUR0_PIX_INV_MODE; \ > type CUR0_PIXEL_ALPHA_MOD_EN; \ >- type CUR0_ROM_EN >+ type CUR0_ROM_EN;\ >+ type OBUF_MEM_PWR_FORCE;\ >+ type LUT_MEM_PWR_FORCE > > struct dcn2_dpp_shift { > TF_REG_FIELD_LIST_DCN2_0(uint8_t); >@@ -609,7 +615,9 @@ > uint32_t COLOR_KEYER_ALPHA; \ > uint32_t COLOR_KEYER_RED; \ > uint32_t COLOR_KEYER_GREEN; \ >- uint32_t COLOR_KEYER_BLUE >+ uint32_t COLOR_KEYER_BLUE; \ >+ uint32_t OBUF_MEM_PWR_CTRL;\ >+ uint32_t DSCL_MEM_PWR_CTRL > > struct dcn2_dpp_registers { > DPP_DCN2_REG_VARIABLE_LIST; >@@ -668,7 +676,7 @@ > > void dpp2_set_cursor_attributes( > struct dpp *dpp_base, >- enum dc_cursor_color_format color_format); >+ struct dc_cursor_attributes *cursor_attributes); > > void dpp2_dummy_program_input_lut( > struct dpp *dpp_base, >@@ -695,4 +703,7 @@ > const struct dcn2_dpp_shift *tf_shift, > const struct dcn2_dpp_mask *tf_mask); > >+void dpp2_power_on_obuf( >+ struct dpp *dpp_base, >+ bool power_on); > #endif /* __DC_HWSS_DCN20_H__ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 2019-08-31 15:01:11.865736169 -0500 >@@ -29,7 +29,7 @@ > #include "dsc/dscc_types.h" > > static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); >-static bool dsc_prepare_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, >+static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, > struct dsc_optc_config *dsc_optc_cfg); > static void dsc_init_reg_values(struct dsc_reg_values *reg_vals); > static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params); >@@ -42,7 +42,8 @@ > static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); > static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); > static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, >- struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps); >+ struct dsc_optc_config *dsc_optc_cfg); >+static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); > static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); > static void dsc2_disable(struct display_stream_compressor *dsc); > >@@ -51,6 +52,7 @@ > .dsc_read_state = dsc2_read_state, > .dsc_validate_stream = dsc2_validate_stream, > .dsc_set_config = dsc2_set_config, >+ .dsc_get_packed_pps = dsc2_get_packed_pps, > .dsc_enable = dsc2_enable, > .dsc_disable = dsc2_disable, > }; >@@ -116,8 +118,8 @@ > > dsc_enc_caps->color_formats.bits.RGB = 1; > dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; >- dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; >- dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; >+ dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 0; >+ dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; > dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; > > dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; >@@ -162,40 +164,61 @@ > static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) > { > struct dsc_optc_config dsc_optc_cfg; >+ struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); > >- if (dsc_cfg->pic_width > TO_DCN20_DSC(dsc)->max_image_width) >+ if (dsc_cfg->pic_width > dsc20->max_image_width) > return false; > >- return dsc_prepare_config(dsc, dsc_cfg, &dsc_optc_cfg); >+ return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); > } > > >-static void dsc_config_log(struct display_stream_compressor *dsc, >- const struct dsc_config *config) >+static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) > { >- DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); >- DC_LOG_DSC("\n\tnum_slices_h %d\n\tnum_slices_v %d\n\tbits_per_pixel %d\n\tcolor_depth %d", >- config->dc_dsc_cfg.num_slices_h, >- config->dc_dsc_cfg.num_slices_v, >+ DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); >+ DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); >+ DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", > config->dc_dsc_cfg.bits_per_pixel, >- config->color_depth); >+ config->dc_dsc_cfg.bits_per_pixel / 16, >+ ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); >+ DC_LOG_DSC("\tcolor_depth %d", config->color_depth); > } > > static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, >- struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps) >+ struct dsc_optc_config *dsc_optc_cfg) > { > bool is_config_ok; > struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); > >+ DC_LOG_DSC(" "); >+ DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); > dsc_config_log(dsc, dsc_cfg); >- is_config_ok = dsc_prepare_config(dsc, dsc_cfg, dsc_optc_cfg); >+ is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); > ASSERT(is_config_ok); >- drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc20->reg_vals.pps); >+ DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); > dsc_log_pps(dsc, &dsc20->reg_vals.pps); > dsc_write_to_registers(dsc, &dsc20->reg_vals); > } > > >+static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) >+{ >+ bool is_config_ok; >+ struct dsc_reg_values dsc_reg_vals; >+ struct dsc_optc_config dsc_optc_cfg; >+ >+ DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); >+ dsc_config_log(dsc, dsc_cfg); >+ DC_LOG_DSC("DSC Picture Parameter Set (PPS):"); >+ is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); >+ ASSERT(is_config_ok); >+ drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); >+ dsc_log_pps(dsc, &dsc_reg_vals.pps); >+ >+ return is_config_ok; >+} >+ >+ > static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) > { > struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); >@@ -232,7 +255,6 @@ > int i; > int bits_per_pixel = pps->bits_per_pixel; > >- DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); > DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); > DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); > DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); >@@ -282,13 +304,11 @@ > } > } > >-static bool dsc_prepare_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, >+static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, > struct dsc_optc_config *dsc_optc_cfg) > { > struct dsc_parameters dsc_params; > >- struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); >- > /* Validate input parameters */ > ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); > ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); >@@ -302,7 +322,7 @@ > dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); > ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 > >- if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_v || >+ if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || > !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || > !dsc_cfg->pic_width || !dsc_cfg->pic_height || > !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: >@@ -315,54 +335,54 @@ > return false; > } > >- dsc_init_reg_values(&dsc20->reg_vals); >+ dsc_init_reg_values(dsc_reg_vals); > > /* Copy input config */ >- dsc20->reg_vals.pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); >- dsc20->reg_vals.num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; >- dsc20->reg_vals.num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; >- dsc20->reg_vals.pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; >- dsc20->reg_vals.pps.pic_width = dsc_cfg->pic_width; >- dsc20->reg_vals.pps.pic_height = dsc_cfg->pic_height; >- dsc20->reg_vals.pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); >- dsc20->reg_vals.pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; >- dsc20->reg_vals.pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; >- dsc20->reg_vals.alternate_ich_encoding_en = dsc20->reg_vals.pps.dsc_version_minor == 1 ? 0 : 1; >+ dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); >+ dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; >+ dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; >+ dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; >+ dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; >+ dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; >+ dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); >+ dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; >+ dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; >+ dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; > > // TODO: in addition to validating slice height (pic height must be divisible by slice height), > // see what happens when the same condition doesn't apply for slice_width/pic_width. >- dsc20->reg_vals.pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; >- dsc20->reg_vals.pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; >+ dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; >+ dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; > >- ASSERT(dsc20->reg_vals.pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); >- if (!(dsc20->reg_vals.pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { >+ ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); >+ if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { > dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); > return false; > } > >- dsc20->reg_vals.bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; >- if (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) >- dsc20->reg_vals.pps.bits_per_pixel = dsc20->reg_vals.bpp_x32; >+ dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; >+ if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) >+ dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; > else >- dsc20->reg_vals.pps.bits_per_pixel = dsc20->reg_vals.bpp_x32 >> 1; >+ dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; > >- dsc20->reg_vals.pps.convert_rgb = dsc20->reg_vals.pixel_format == DSC_PIXFMT_RGB ? 1 : 0; >- dsc20->reg_vals.pps.native_422 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); >- dsc20->reg_vals.pps.native_420 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); >- dsc20->reg_vals.pps.simple_422 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); >+ dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; >+ dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); >+ dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); >+ dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); > >- if (dscc_compute_dsc_parameters(&dsc20->reg_vals.pps, &dsc_params)) { >+ if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) { > dm_output_to_console("%s: DSC config failed\n", __func__); > return false; > } > >- dsc_update_from_dsc_parameters(&dsc20->reg_vals, &dsc_params); >+ dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); > > dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; >- dsc_optc_cfg->slice_width = dsc20->reg_vals.pps.slice_width; >- dsc_optc_cfg->is_pixel_format_444 = dsc20->reg_vals.pixel_format == DSC_PIXFMT_RGB || >- dsc20->reg_vals.pixel_format == DSC_PIXFMT_YCBCR444 || >- dsc20->reg_vals.pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; >+ dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; >+ dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || >+ dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || >+ dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; > > return true; > } >@@ -427,6 +447,8 @@ > { > int i; > >+ memset(reg_vals, 0, sizeof(struct dsc_reg_values)); >+ > /* Non-PPS values */ > reg_vals->dsc_clock_enable = 1; > reg_vals->dsc_clock_gating_disable = 0; >@@ -436,7 +458,7 @@ > reg_vals->ich_reset_at_eol = 0; > reg_vals->alternate_ich_encoding_en = 0; > reg_vals->rc_buffer_model_size = 0; >- reg_vals->disable_ich = 0; >+ /*reg_vals->disable_ich = 0;*/ > reg_vals->dsc_dbg_en = 0; > > for (i = 0; i < 4; i++) >@@ -518,9 +540,11 @@ > ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, > NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); > >- REG_SET_2(DSCC_CONFIG1, 0, >+ REG_SET(DSCC_CONFIG1, 0, >+ DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); >+ /*REG_SET_2(DSCC_CONFIG1, 0, > DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, >- DSCC_DISABLE_ICH, reg_vals->disable_ich); >+ DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ > > REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, > DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 2019-08-31 15:01:11.865736169 -0500 >@@ -103,7 +103,7 @@ > DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \ > DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \ > DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \ >- DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh), \ >+ /*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \ > DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ > DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \ > DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \ >@@ -278,7 +278,7 @@ > type ALTERNATE_ICH_ENCODING_EN; \ > type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \ > type DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE; \ >- type DSCC_DISABLE_ICH; \ >+ /*type DSCC_DISABLE_ICH;*/ \ > type DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ > type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED; \ > type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED; \ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 2019-08-31 15:01:11.865736169 -0500 >@@ -26,6 +26,7 @@ > > #include "dcn20_hubbub.h" > #include "reg_helper.h" >+#include "clk_mgr.h" > > #define REG(reg)\ > hubbub1->regs->reg >@@ -379,6 +380,11 @@ > REG_SET(DCN_VM_AGP_BASE, 0, > AGP_BASE, pa_config->system_aperture.agp_base >> 24); > >+ REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, >+ DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF); >+ REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, >+ DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF); >+ > if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { > phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; > phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12; >@@ -397,54 +403,67 @@ > { > struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); > >- if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) { >- ASSERT(false); >- /*should not come here*/ >+ if (REG(DCN_VM_FB_LOCATION_TOP) == 0) > return; >- } >- /* TODO: port code from dal2 */ >+ > switch (dh_data->fb_mode) { > case FRAME_BUFFER_MODE_ZFB_ONLY: > /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ >- REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, >- SDPIF_FB_TOP, 0); >+ REG_UPDATE(DCN_VM_FB_LOCATION_TOP, >+ FB_TOP, 0); > >- REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, >- SDPIF_FB_BASE, 0x0FFFF); >+ REG_UPDATE(DCN_VM_FB_LOCATION_BASE, >+ FB_BASE, 0xFFFFFF); > >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, >- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); >- >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, >- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); >- >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, >- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + >- dh_data->zfb_size_in_byte - 1) >> 22); >+ /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ >+ REG_UPDATE(DCN_VM_AGP_BASE, >+ AGP_BASE, dh_data->zfb_phys_addr_base >> 24); >+ >+ /*This field defines the bottom range of the AGP aperture and represents the 24*/ >+ /*MSBs, bits [47:24] of the 48 address bits*/ >+ REG_UPDATE(DCN_VM_AGP_BOT, >+ AGP_BOT, dh_data->zfb_mc_base_addr >> 24); >+ >+ /*This field defines the top range of the AGP aperture and represents the 24*/ >+ /*MSBs, bits [47:24] of the 48 address bits*/ >+ REG_UPDATE(DCN_VM_AGP_TOP, >+ AGP_TOP, (dh_data->zfb_mc_base_addr + >+ dh_data->zfb_size_in_byte - 1) >> 24); > break; > case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: > /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ > >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, >- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); >- >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, >- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); >- >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, >- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + >- dh_data->zfb_size_in_byte - 1) >> 22); >+ /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ >+ REG_UPDATE(DCN_VM_AGP_BASE, >+ AGP_BASE, dh_data->zfb_phys_addr_base >> 24); >+ >+ /*This field defines the bottom range of the AGP aperture and represents the 24*/ >+ /*MSBs, bits [47:24] of the 48 address bits*/ >+ REG_UPDATE(DCN_VM_AGP_BOT, >+ AGP_BOT, dh_data->zfb_mc_base_addr >> 24); >+ >+ /*This field defines the top range of the AGP aperture and represents the 24*/ >+ /*MSBs, bits [47:24] of the 48 address bits*/ >+ REG_UPDATE(DCN_VM_AGP_TOP, >+ AGP_TOP, (dh_data->zfb_mc_base_addr + >+ dh_data->zfb_size_in_byte - 1) >> 24); > break; > case FRAME_BUFFER_MODE_LOCAL_ONLY: >- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, >- SDPIF_AGP_BASE, 0); >+ /*Should not touch FB LOCATION (should be done by VBIOS)*/ > >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, >- SDPIF_AGP_BOT, 0X03FFFF); >- >- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, >- SDPIF_AGP_TOP, 0); >+ /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ >+ REG_UPDATE(DCN_VM_AGP_BASE, >+ AGP_BASE, 0); >+ >+ /*This field defines the bottom range of the AGP aperture and represents the 24*/ >+ /*MSBs, bits [47:24] of the 48 address bits*/ >+ REG_UPDATE(DCN_VM_AGP_BOT, >+ AGP_BOT, 0xFFFFFF); >+ >+ /*This field defines the top range of the AGP aperture and represents the 24*/ >+ /*MSBs, bits [47:24] of the 48 address bits*/ >+ REG_UPDATE(DCN_VM_AGP_TOP, >+ AGP_TOP, 0); > break; > default: > break; >@@ -553,6 +572,16 @@ > */ > hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); > hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); >+ >+ /* >+ * There's a special case when going from p-state support to p-state unsupported >+ * here we are going to LOWER watermarks to go to dummy p-state only, but this has >+ * to be done prepare_bandwidth, not optimize >+ */ >+ if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true && >+ hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false) >+ safe_to_lower = true; >+ > hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); > > REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, >@@ -571,7 +600,7 @@ > .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap, > .wm_read_state = hubbub2_wm_read_state, > .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq, >- .program_watermarks = hubbub2_program_watermarks, >+ .program_watermarks = hubbub2_program_watermarks > }; > > void hubbub2_construct(struct dcn20_hubbub *hubbub, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h 2019-08-31 15:01:11.865736169 -0500 >@@ -29,13 +29,21 @@ > #include "dcn10/dcn10_hubbub.h" > #include "dcn20_vmid.h" > >+#define HUBBUB_REG_LIST_DCN20_COMMON()\ >+ HUBBUB_REG_LIST_DCN_COMMON(), \ >+ SR(DCHUBBUB_CRC_CTRL), \ >+ SR(DCN_VM_FB_LOCATION_BASE),\ >+ SR(DCN_VM_FB_LOCATION_TOP),\ >+ SR(DCN_VM_FB_OFFSET),\ >+ SR(DCN_VM_AGP_BOT),\ >+ SR(DCN_VM_AGP_TOP),\ >+ SR(DCN_VM_AGP_BASE) >+ > #define TO_DCN20_HUBBUB(hubbub)\ > container_of(hubbub, struct dcn20_hubbub, base) > >-#define HUBBUB_REG_LIST_DCN20(id)\ >+#define HUBBUB_REG_LIST_DCN20_COMMON()\ > HUBBUB_REG_LIST_DCN_COMMON(), \ >- HUBBUB_VM_REG_LIST(), \ >- HUBBUB_SR_WATERMARK_REG_LIST(), \ > SR(DCHUBBUB_CRC_CTRL), \ > SR(DCN_VM_FB_LOCATION_BASE),\ > SR(DCN_VM_FB_LOCATION_TOP),\ >@@ -44,6 +52,14 @@ > SR(DCN_VM_AGP_TOP),\ > SR(DCN_VM_AGP_BASE) > >+#define HUBBUB_REG_LIST_DCN20(id)\ >+ HUBBUB_REG_LIST_DCN20_COMMON(), \ >+ HUBBUB_SR_WATERMARK_REG_LIST(), \ >+ HUBBUB_VM_REG_LIST(),\ >+ SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\ >+ SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB) >+ >+ > #define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\ > HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ > HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ >@@ -53,7 +69,9 @@ > HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ > HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ > HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ >- HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh) >+ HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ >+ HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \ >+ HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh) > > struct dcn20_hubbub { > struct hubbub base; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 2019-08-31 15:01:11.865736169 -0500 >@@ -40,81 +40,6 @@ > #define FN(reg_name, field_name) \ > hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name > >-void hubp2_update_dchub( >- struct hubp *hubp, >- struct dchub_init_data *dh_data) >-{ >- struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >- if (REG(DCN_VM_FB_LOCATION_TOP) == 0) >- return; >- >- switch (dh_data->fb_mode) { >- case FRAME_BUFFER_MODE_ZFB_ONLY: >- /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ >- REG_UPDATE(DCN_VM_FB_LOCATION_TOP, >- FB_TOP, 0); >- >- REG_UPDATE(DCN_VM_FB_LOCATION_BASE, >- FB_BASE, 0xFFFFFF); >- >- /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ >- REG_UPDATE(DCN_VM_AGP_BASE, >- AGP_BASE, dh_data->zfb_phys_addr_base >> 24); >- >- /*This field defines the bottom range of the AGP aperture and represents the 24*/ >- /*MSBs, bits [47:24] of the 48 address bits*/ >- REG_UPDATE(DCN_VM_AGP_BOT, >- AGP_BOT, dh_data->zfb_mc_base_addr >> 24); >- >- /*This field defines the top range of the AGP aperture and represents the 24*/ >- /*MSBs, bits [47:24] of the 48 address bits*/ >- REG_UPDATE(DCN_VM_AGP_TOP, >- AGP_TOP, (dh_data->zfb_mc_base_addr + >- dh_data->zfb_size_in_byte - 1) >> 24); >- break; >- case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: >- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ >- >- /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ >- REG_UPDATE(DCN_VM_AGP_BASE, >- AGP_BASE, dh_data->zfb_phys_addr_base >> 24); >- >- /*This field defines the bottom range of the AGP aperture and represents the 24*/ >- /*MSBs, bits [47:24] of the 48 address bits*/ >- REG_UPDATE(DCN_VM_AGP_BOT, >- AGP_BOT, dh_data->zfb_mc_base_addr >> 24); >- >- /*This field defines the top range of the AGP aperture and represents the 24*/ >- /*MSBs, bits [47:24] of the 48 address bits*/ >- REG_UPDATE(DCN_VM_AGP_TOP, >- AGP_TOP, (dh_data->zfb_mc_base_addr + >- dh_data->zfb_size_in_byte - 1) >> 24); >- break; >- case FRAME_BUFFER_MODE_LOCAL_ONLY: >- /*Should not touch FB LOCATION (should be done by VBIOS)*/ >- >- /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ >- REG_UPDATE(DCN_VM_AGP_BASE, >- AGP_BASE, 0); >- >- /*This field defines the bottom range of the AGP aperture and represents the 24*/ >- /*MSBs, bits [47:24] of the 48 address bits*/ >- REG_UPDATE(DCN_VM_AGP_BOT, >- AGP_BOT, 0xFFFFFF); >- >- /*This field defines the top range of the AGP aperture and represents the 24*/ >- /*MSBs, bits [47:24] of the 48 address bits*/ >- REG_UPDATE(DCN_VM_AGP_TOP, >- AGP_TOP, 0); >- break; >- default: >- break; >- } >- >- dh_data->dchub_initialzied = true; >- dh_data->dchub_info_valid = false; >-} >- > void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, > struct vm_system_aperture_param *apt) > { >@@ -156,7 +81,85 @@ > { > struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); > >- hubp1_program_deadline(hubp, dlg_attr, ttu_attr); >+ /* DLG - Per hubp */ >+ REG_SET_2(BLANK_OFFSET_0, 0, >+ REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, >+ DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); >+ >+ REG_SET(BLANK_OFFSET_1, 0, >+ MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); >+ >+ REG_SET(DST_DIMENSIONS, 0, >+ REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); >+ >+ REG_SET_2(DST_AFTER_SCALER, 0, >+ REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, >+ DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); >+ >+ REG_SET(REF_FREQ_TO_PIX_FREQ, 0, >+ REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); >+ >+ /* DLG - Per luma/chroma */ >+ REG_SET(VBLANK_PARAMETERS_1, 0, >+ REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); >+ >+ if (REG(NOM_PARAMETERS_0)) >+ REG_SET(NOM_PARAMETERS_0, 0, >+ DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); >+ >+ if (REG(NOM_PARAMETERS_1)) >+ REG_SET(NOM_PARAMETERS_1, 0, >+ REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); >+ >+ REG_SET(NOM_PARAMETERS_4, 0, >+ DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); >+ >+ REG_SET(NOM_PARAMETERS_5, 0, >+ REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); >+ >+ REG_SET_2(PER_LINE_DELIVERY, 0, >+ REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, >+ REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); >+ >+ REG_SET(VBLANK_PARAMETERS_2, 0, >+ REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); >+ >+ if (REG(NOM_PARAMETERS_2)) >+ REG_SET(NOM_PARAMETERS_2, 0, >+ DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); >+ >+ if (REG(NOM_PARAMETERS_3)) >+ REG_SET(NOM_PARAMETERS_3, 0, >+ REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); >+ >+ REG_SET(NOM_PARAMETERS_6, 0, >+ DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); >+ >+ REG_SET(NOM_PARAMETERS_7, 0, >+ REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); >+ >+ /* TTU - per hubp */ >+ REG_SET_2(DCN_TTU_QOS_WM, 0, >+ QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, >+ QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); >+ >+ /* TTU - per luma/chroma */ >+ /* Assumed surf0 is luma and 1 is chroma */ >+ >+ REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, >+ REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, >+ QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, >+ QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); >+ >+ REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, >+ REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, >+ QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, >+ QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); >+ >+ REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, >+ REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, >+ QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, >+ QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); > > REG_SET(FLIP_PARAMETERS_1, 0, > REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); >@@ -184,6 +187,39 @@ > REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); > } > >+void hubp2_program_requestor( >+ struct hubp *hubp, >+ struct _vcs_dpi_display_rq_regs_st *rq_regs) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ >+ REG_UPDATE(HUBPRET_CONTROL, >+ DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); >+ REG_SET_4(DCN_EXPANSION_MODE, 0, >+ DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, >+ PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, >+ MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, >+ CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); >+ REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, >+ CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, >+ MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, >+ META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, >+ MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, >+ DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, >+ MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, >+ SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, >+ PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); >+ REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, >+ CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, >+ MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, >+ META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, >+ MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, >+ DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, >+ MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, >+ SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, >+ PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); >+} >+ > static void hubp2_setup( > struct hubp *hubp, > struct _vcs_dpi_display_dlg_regs_st *dlg_attr, >@@ -196,7 +232,7 @@ > */ > > hubp2_vready_at_or_After_vsync(hubp, pipe_dest); >- hubp1_program_requestor(hubp, rq_regs); >+ hubp2_program_requestor(hubp, rq_regs); > hubp2_program_deadline(hubp, dlg_attr, ttu_attr); > > } >@@ -283,11 +319,205 @@ > PIPE_ALIGNED, 0); > } > >+void hubp2_program_size( >+ struct hubp *hubp, >+ enum surface_pixel_format format, >+ const struct plane_size *plane_size, >+ struct dc_plane_dcc_param *dcc) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; >+ bool use_pitch_c = false; >+ >+ /* Program data and meta surface pitch (calculation from addrlib) >+ * 444 or 420 luma >+ */ >+ use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN >+ && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; >+ if (use_pitch_c) { >+ ASSERT(plane_size->chroma_pitch != 0); >+ /* Chroma pitch zero can cause system hang! */ >+ >+ pitch = plane_size->surface_pitch - 1; >+ meta_pitch = dcc->meta_pitch - 1; >+ pitch_c = plane_size->chroma_pitch - 1; >+ meta_pitch_c = dcc->meta_pitch_c - 1; >+ } else { >+ pitch = plane_size->surface_pitch - 1; >+ meta_pitch = dcc->meta_pitch - 1; >+ pitch_c = 0; >+ meta_pitch_c = 0; >+ } >+ >+ if (!dcc->enable) { >+ meta_pitch = 0; >+ meta_pitch_c = 0; >+ } >+ >+ REG_UPDATE_2(DCSURF_SURFACE_PITCH, >+ PITCH, pitch, META_PITCH, meta_pitch); >+ >+ use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; >+ if (use_pitch_c) >+ REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, >+ PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); >+} >+ >+void hubp2_program_rotation( >+ struct hubp *hubp, >+ enum dc_rotation_angle rotation, >+ bool horizontal_mirror) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ uint32_t mirror; >+ >+ >+ if (horizontal_mirror) >+ mirror = 1; >+ else >+ mirror = 0; >+ >+ /* Program rotation angle and horz mirror - no mirror */ >+ if (rotation == ROTATION_ANGLE_0) >+ REG_UPDATE_2(DCSURF_SURFACE_CONFIG, >+ ROTATION_ANGLE, 0, >+ H_MIRROR_EN, mirror); >+ else if (rotation == ROTATION_ANGLE_90) >+ REG_UPDATE_2(DCSURF_SURFACE_CONFIG, >+ ROTATION_ANGLE, 1, >+ H_MIRROR_EN, mirror); >+ else if (rotation == ROTATION_ANGLE_180) >+ REG_UPDATE_2(DCSURF_SURFACE_CONFIG, >+ ROTATION_ANGLE, 2, >+ H_MIRROR_EN, mirror); >+ else if (rotation == ROTATION_ANGLE_270) >+ REG_UPDATE_2(DCSURF_SURFACE_CONFIG, >+ ROTATION_ANGLE, 3, >+ H_MIRROR_EN, mirror); >+} >+ >+void hubp2_dcc_control(struct hubp *hubp, bool enable, >+ enum hubp_ind_block_size independent_64b_blks) >+{ >+ uint32_t dcc_en = enable ? 1 : 0; >+ uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ >+ REG_UPDATE_4(DCSURF_SURFACE_CONTROL, >+ PRIMARY_SURFACE_DCC_EN, dcc_en, >+ PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, >+ SECONDARY_SURFACE_DCC_EN, dcc_en, >+ SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); >+} >+ >+void hubp2_program_pixel_format( >+ struct hubp *hubp, >+ enum surface_pixel_format format) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ uint32_t red_bar = 3; >+ uint32_t blue_bar = 2; >+ >+ /* swap for ABGR format */ >+ if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 >+ || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 >+ || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS >+ || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { >+ red_bar = 2; >+ blue_bar = 3; >+ } >+ >+ REG_UPDATE_2(HUBPRET_CONTROL, >+ CROSSBAR_SRC_CB_B, blue_bar, >+ CROSSBAR_SRC_CR_R, red_bar); >+ >+ /* Mapping is same as ipp programming (cnvc) */ >+ >+ switch (format) { >+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 1); >+ break; >+ case SURFACE_PIXEL_FORMAT_GRPH_RGB565: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 3); >+ break; >+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: >+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 8); >+ break; >+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: >+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: >+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 10); >+ break; >+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 22); >+ break; >+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: >+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 24); >+ break; >+ >+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 65); >+ break; >+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 64); >+ break; >+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 67); >+ break; >+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 66); >+ break; >+ case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 12); >+ break; >+#if defined(CONFIG_DRM_AMD_DC_DCN2_0) >+ case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 112); >+ break; >+ case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 113); >+ break; >+ case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 114); >+ break; >+ case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 118); >+ break; >+ case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: >+ REG_UPDATE(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, 119); >+ break; >+#endif >+ default: >+ BREAK_TO_DEBUGGER(); >+ break; >+ } >+ >+ /* don't see the need of program the xbar in DCN 1.0 */ >+} >+ > void hubp2_program_surface_config( > struct hubp *hubp, > enum surface_pixel_format format, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > enum dc_rotation_angle rotation, > struct dc_plane_dcc_param *dcc, > bool horizontal_mirror, >@@ -295,11 +525,11 @@ > { > struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); > >- hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); >+ hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); > hubp2_program_tiling(hubp2, tiling_info, format); >- hubp1_program_size(hubp, format, plane_size, dcc); >- hubp1_program_rotation(hubp, rotation, horizontal_mirror); >- hubp1_program_pixel_format(hubp, format); >+ hubp2_program_size(hubp, format, plane_size, dcc); >+ hubp2_program_rotation(hubp, rotation, horizontal_mirror); >+ hubp2_program_pixel_format(hubp, format); > } > > enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( >@@ -652,28 +882,388 @@ > REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); > } > >+bool hubp2_is_flip_pending(struct hubp *hubp) >+{ >+ uint32_t flip_pending = 0; >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ struct dc_plane_address earliest_inuse_address; >+ >+ REG_GET(DCSURF_FLIP_CONTROL, >+ SURFACE_FLIP_PENDING, &flip_pending); >+ >+ REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, >+ SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); >+ >+ REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, >+ SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); >+ >+ if (flip_pending) >+ return true; >+ >+ if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) >+ return true; >+ >+ return false; >+} >+ >+void hubp2_set_blank(struct hubp *hubp, bool blank) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ uint32_t blank_en = blank ? 1 : 0; >+ >+ REG_UPDATE_2(DCHUBP_CNTL, >+ HUBP_BLANK_EN, blank_en, >+ HUBP_TTU_DISABLE, blank_en); >+ >+ if (blank) { >+ uint32_t reg_val = REG_READ(DCHUBP_CNTL); >+ >+ if (reg_val) { >+ /* init sequence workaround: in case HUBP is >+ * power gated, this wait would timeout. >+ * >+ * we just wrote reg_val to non-0, if it stay 0 >+ * it means HUBP is gated >+ */ >+ REG_WAIT(DCHUBP_CNTL, >+ HUBP_NO_OUTSTANDING_REQ, 1, >+ 1, 200); >+ } >+ >+ hubp->mpcc_id = 0xf; >+ hubp->opp_id = OPP_ID_INVALID; >+ } >+} >+ >+void hubp2_cursor_set_position( >+ struct hubp *hubp, >+ const struct dc_cursor_position *pos, >+ const struct dc_cursor_mi_param *param) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; >+ int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; >+ int x_hotspot = pos->x_hotspot; >+ int y_hotspot = pos->y_hotspot; >+ int cursor_height = (int)hubp->curs_attr.height; >+ int cursor_width = (int)hubp->curs_attr.width; >+ uint32_t dst_x_offset; >+ uint32_t cur_en = pos->enable ? 1 : 0; >+ >+ /* >+ * Guard aganst cursor_set_position() from being called with invalid >+ * attributes >+ * >+ * TODO: Look at combining cursor_set_position() and >+ * cursor_set_attributes() into cursor_update() >+ */ >+ if (hubp->curs_attr.address.quad_part == 0) >+ return; >+ >+ // Rotated cursor width/height and hotspots tweaks for offset calculation >+ if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { >+ swap(cursor_height, cursor_width); >+ if (param->rotation == ROTATION_ANGLE_90) { >+ src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; >+ src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; >+ } >+ } else if (param->rotation == ROTATION_ANGLE_180) { >+ src_x_offset = pos->x - param->viewport.x; >+ src_y_offset = pos->y - param->viewport.y; >+ } >+ >+ if (param->mirror) { >+ x_hotspot = param->viewport.width - x_hotspot; >+ src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; >+ } >+ >+ dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; >+ dst_x_offset *= param->ref_clk_khz; >+ dst_x_offset /= param->pixel_clk_khz; >+ >+ ASSERT(param->h_scale_ratio.value); >+ >+ if (param->h_scale_ratio.value) >+ dst_x_offset = dc_fixpt_floor(dc_fixpt_div( >+ dc_fixpt_from_int(dst_x_offset), >+ param->h_scale_ratio)); >+ >+ if (src_x_offset >= (int)param->viewport.width) >+ cur_en = 0; /* not visible beyond right edge*/ >+ >+ if (src_x_offset + cursor_width <= 0) >+ cur_en = 0; /* not visible beyond left edge*/ >+ >+ if (src_y_offset >= (int)param->viewport.height) >+ cur_en = 0; /* not visible beyond bottom edge*/ >+ >+ if (src_y_offset + cursor_height <= 0) >+ cur_en = 0; /* not visible beyond top edge*/ >+ >+ if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) >+ hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); >+ >+ REG_UPDATE(CURSOR_CONTROL, >+ CURSOR_ENABLE, cur_en); >+ >+ REG_SET_2(CURSOR_POSITION, 0, >+ CURSOR_X_POSITION, pos->x, >+ CURSOR_Y_POSITION, pos->y); >+ >+ REG_SET_2(CURSOR_HOT_SPOT, 0, >+ CURSOR_HOT_SPOT_X, x_hotspot, >+ CURSOR_HOT_SPOT_Y, y_hotspot); >+ >+ REG_SET(CURSOR_DST_OFFSET, 0, >+ CURSOR_DST_X_OFFSET, dst_x_offset); >+ /* TODO Handle surface pixel formats other than 4:4:4 */ >+} >+ >+void hubp2_clk_cntl(struct hubp *hubp, bool enable) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ uint32_t clk_enable = enable ? 1 : 0; >+ >+ REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); >+} >+ >+void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ >+ REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); >+} >+ >+void hubp2_clear_underflow(struct hubp *hubp) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ >+ REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); >+} >+ >+void hubp2_read_state_common(struct hubp *hubp) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ struct dcn_hubp_state *s = &hubp2->state; >+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; >+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; >+ struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; >+ >+ /* Requester */ >+ REG_GET(HUBPRET_CONTROL, >+ DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); >+ REG_GET_4(DCN_EXPANSION_MODE, >+ DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, >+ PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, >+ MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, >+ CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); >+ >+ /* DLG - Per hubp */ >+ REG_GET_2(BLANK_OFFSET_0, >+ REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, >+ DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); >+ >+ REG_GET(BLANK_OFFSET_1, >+ MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); >+ >+ REG_GET(DST_DIMENSIONS, >+ REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); >+ >+ REG_GET_2(DST_AFTER_SCALER, >+ REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, >+ DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); >+ >+ if (REG(PREFETCH_SETTINS)) >+ REG_GET_2(PREFETCH_SETTINS, >+ DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, >+ VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); >+ else >+ REG_GET_2(PREFETCH_SETTINGS, >+ DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, >+ VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); >+ >+ REG_GET_2(VBLANK_PARAMETERS_0, >+ DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, >+ DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); >+ >+ REG_GET(REF_FREQ_TO_PIX_FREQ, >+ REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); >+ >+ /* DLG - Per luma/chroma */ >+ REG_GET(VBLANK_PARAMETERS_1, >+ REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); >+ >+ REG_GET(VBLANK_PARAMETERS_3, >+ REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); >+ >+ if (REG(NOM_PARAMETERS_0)) >+ REG_GET(NOM_PARAMETERS_0, >+ DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); >+ >+ if (REG(NOM_PARAMETERS_1)) >+ REG_GET(NOM_PARAMETERS_1, >+ REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); >+ >+ REG_GET(NOM_PARAMETERS_4, >+ DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); >+ >+ REG_GET(NOM_PARAMETERS_5, >+ REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); >+ >+ REG_GET_2(PER_LINE_DELIVERY_PRE, >+ REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, >+ REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); >+ >+ REG_GET_2(PER_LINE_DELIVERY, >+ REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, >+ REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); >+ >+ if (REG(PREFETCH_SETTINS_C)) >+ REG_GET(PREFETCH_SETTINS_C, >+ VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); >+ else >+ REG_GET(PREFETCH_SETTINGS_C, >+ VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); >+ >+ REG_GET(VBLANK_PARAMETERS_2, >+ REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); >+ >+ REG_GET(VBLANK_PARAMETERS_4, >+ REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); >+ >+ if (REG(NOM_PARAMETERS_2)) >+ REG_GET(NOM_PARAMETERS_2, >+ DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); >+ >+ if (REG(NOM_PARAMETERS_3)) >+ REG_GET(NOM_PARAMETERS_3, >+ REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); >+ >+ REG_GET(NOM_PARAMETERS_6, >+ DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); >+ >+ REG_GET(NOM_PARAMETERS_7, >+ REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); >+ >+ /* TTU - per hubp */ >+ REG_GET_2(DCN_TTU_QOS_WM, >+ QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, >+ QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); >+ >+ REG_GET_2(DCN_GLOBAL_TTU_CNTL, >+ MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, >+ QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); >+ >+ /* TTU - per luma/chroma */ >+ /* Assumed surf0 is luma and 1 is chroma */ >+ >+ REG_GET_3(DCN_SURF0_TTU_CNTL0, >+ REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, >+ QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, >+ QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); >+ >+ REG_GET(DCN_SURF0_TTU_CNTL1, >+ REFCYC_PER_REQ_DELIVERY_PRE, >+ &ttu_attr->refcyc_per_req_delivery_pre_l); >+ >+ REG_GET_3(DCN_SURF1_TTU_CNTL0, >+ REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, >+ QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, >+ QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); >+ >+ REG_GET(DCN_SURF1_TTU_CNTL1, >+ REFCYC_PER_REQ_DELIVERY_PRE, >+ &ttu_attr->refcyc_per_req_delivery_pre_c); >+ >+ /* Rest of hubp */ >+ REG_GET(DCSURF_SURFACE_CONFIG, >+ SURFACE_PIXEL_FORMAT, &s->pixel_format); >+ >+ REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, >+ SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); >+ >+ REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, >+ SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); >+ >+ REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, >+ PRI_VIEWPORT_WIDTH, &s->viewport_width, >+ PRI_VIEWPORT_HEIGHT, &s->viewport_height); >+ >+ REG_GET_2(DCSURF_SURFACE_CONFIG, >+ ROTATION_ANGLE, &s->rotation_angle, >+ H_MIRROR_EN, &s->h_mirror_en); >+ >+ REG_GET(DCSURF_TILING_CONFIG, >+ SW_MODE, &s->sw_mode); >+ >+ REG_GET(DCSURF_SURFACE_CONTROL, >+ PRIMARY_SURFACE_DCC_EN, &s->dcc_en); >+ >+ REG_GET_3(DCHUBP_CNTL, >+ HUBP_BLANK_EN, &s->blank_en, >+ HUBP_TTU_DISABLE, &s->ttu_disable, >+ HUBP_UNDERFLOW_STATUS, &s->underflow_status); >+ >+ REG_GET(DCN_GLOBAL_TTU_CNTL, >+ MIN_TTU_VBLANK, &s->min_ttu_vblank); >+ >+ REG_GET_2(DCN_TTU_QOS_WM, >+ QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, >+ QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); >+ >+} >+ >+void hubp2_read_state(struct hubp *hubp) >+{ >+ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); >+ struct dcn_hubp_state *s = &hubp2->state; >+ struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; >+ >+ hubp2_read_state_common(hubp); >+ >+ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, >+ CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, >+ MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, >+ META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, >+ MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, >+ DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, >+ MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, >+ SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, >+ PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); >+ >+ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, >+ CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, >+ MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, >+ META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, >+ MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, >+ DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, >+ MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, >+ SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, >+ PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); >+ >+} >+ > static struct hubp_funcs dcn20_hubp_funcs = { > .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, > .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, > .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, > .hubp_program_surface_config = hubp2_program_surface_config, >- .hubp_is_flip_pending = hubp1_is_flip_pending, >+ .hubp_is_flip_pending = hubp2_is_flip_pending, > .hubp_setup = hubp2_setup, > .hubp_setup_interdependent = hubp2_setup_interdependent, > .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, >- .set_blank = hubp1_set_blank, >- .dcc_control = hubp1_dcc_control, >- .hubp_update_dchub = hubp2_update_dchub, >+ .set_blank = hubp2_set_blank, >+ .dcc_control = hubp2_dcc_control, > .mem_program_viewport = min_set_viewport, > .set_cursor_attributes = hubp2_cursor_set_attributes, >- .set_cursor_position = hubp1_cursor_set_position, >- .hubp_clk_cntl = hubp1_clk_cntl, >- .hubp_vtg_sel = hubp1_vtg_sel, >+ .set_cursor_position = hubp2_cursor_set_position, >+ .hubp_clk_cntl = hubp2_clk_cntl, >+ .hubp_vtg_sel = hubp2_vtg_sel, > .dmdata_set_attributes = hubp2_dmdata_set_attributes, > .dmdata_load = hubp2_dmdata_load, > .dmdata_status_done = hubp2_dmdata_status_done, >- .hubp_read_state = hubp1_read_state, >- .hubp_clear_underflow = hubp1_clear_underflow, >+ .hubp_read_state = hubp2_read_state, >+ .hubp_clear_underflow = hubp2_clear_underflow, > .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, > .hubp_init = hubp1_init, > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 2019-08-31 15:01:11.865736169 -0500 >@@ -38,12 +38,6 @@ > SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\ > SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\ > SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\ >- SR(DCN_VM_FB_LOCATION_TOP),\ >- SR(DCN_VM_FB_LOCATION_BASE),\ >- SR(DCN_VM_FB_OFFSET),\ >- SR(DCN_VM_AGP_BASE),\ >- SR(DCN_VM_AGP_BOT),\ >- SR(DCN_VM_AGP_TOP),\ > SRI(CURSOR_SETTINGS, HUBPREQ, id), \ > SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ > SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ >@@ -72,8 +66,8 @@ > SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ > SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB) > >-#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ >- HUBP_MASK_SH_LIST_DCN(mask_sh),\ >+#define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\ >+ HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ > HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ > HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ > HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ >@@ -82,12 +76,6 @@ > HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ > HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ > HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ >- HUBP_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh),\ >- HUBP_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh),\ >- HUBP_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh),\ >- HUBP_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh),\ >- HUBP_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh),\ >- HUBP_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh),\ > HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ > HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ > HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ >@@ -127,13 +115,21 @@ > HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ > HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) > >+/*DCN2.x and DCN1.x*/ >+#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ >+ HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\ >+ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ >+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ >+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) >+ >+/*DCN2.0 specific*/ > #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\ > HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\ > HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ > HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ > HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) > >- >+/*DCN2.x */ > #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \ > HUBP_COMMON_REG_VARIABLE_LIST; \ > uint32_t DMDATA_ADDRESS_HIGH; \ >@@ -149,14 +145,22 @@ > uint32_t FLIP_PARAMETERS_2;\ > uint32_t DCN_CUR1_TTU_CNTL0;\ > uint32_t DCN_CUR1_TTU_CNTL1;\ >- uint32_t VMID_SETTINGS_0;\ >+ uint32_t VMID_SETTINGS_0 >+ >+ >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ >+ DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \ > uint32_t FLIP_PARAMETERS_3;\ > uint32_t FLIP_PARAMETERS_4;\ >+ uint32_t FLIP_PARAMETERS_5;\ >+ uint32_t FLIP_PARAMETERS_6;\ > uint32_t VBLANK_PARAMETERS_5;\ > uint32_t VBLANK_PARAMETERS_6 >+#endif > > #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ >- DCN_HUBP_REG_FIELD_LIST(type); \ >+ DCN_HUBP_REG_FIELD_BASE_LIST(type); \ > type DMDATA_ADDRESS_HIGH;\ > type DMDATA_MODE;\ > type DMDATA_UPDATED;\ >@@ -180,17 +184,41 @@ > type SURFACE_TRIPLE_BUFFER_ENABLE;\ > type VMID > >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \ >+ DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\ >+ type REFCYC_PER_VM_GROUP_FLIP;\ >+ type REFCYC_PER_VM_REQ_FLIP;\ >+ type REFCYC_PER_VM_GROUP_VBLANK;\ >+ type REFCYC_PER_VM_REQ_VBLANK;\ >+ type REFCYC_PER_PTE_GROUP_FLIP_C; \ >+ type REFCYC_PER_META_CHUNK_FLIP_C; \ >+ type VM_GROUP_SIZE >+#endif >+ > > struct dcn_hubp2_registers { >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ DCN21_HUBP_REG_COMMON_VARIABLE_LIST; >+#else > DCN2_HUBP_REG_COMMON_VARIABLE_LIST; >+#endif > }; > > struct dcn_hubp2_shift { >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); >+#else > DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); >+#endif > }; > > struct dcn_hubp2_mask { >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); >+#else > DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); >+#endif > }; > > struct dcn20_hubp { >@@ -217,10 +245,6 @@ > void hubp2_vready_at_or_After_vsync(struct hubp *hubp, > struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); > >-void hubp2_update_dchub( >- struct hubp *hubp, >- struct dchub_init_data *dh_data); >- > void hubp2_cursor_set_attributes( > struct hubp *hubp, > const struct dc_cursor_attributes *attr); >@@ -262,16 +286,53 @@ > const struct dc_plane_address *address, > bool flip_immediate); > >+void hubp2_dcc_control(struct hubp *hubp, bool enable, >+ enum hubp_ind_block_size independent_64b_blks); >+ >+void hubp2_program_size( >+ struct hubp *hubp, >+ enum surface_pixel_format format, >+ const struct plane_size *plane_size, >+ struct dc_plane_dcc_param *dcc); >+ >+void hubp2_program_rotation( >+ struct hubp *hubp, >+ enum dc_rotation_angle rotation, >+ bool horizontal_mirror); >+ >+void hubp2_program_pixel_format( >+ struct hubp *hubp, >+ enum surface_pixel_format format); >+ > void hubp2_program_surface_config( > struct hubp *hubp, > enum surface_pixel_format format, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > enum dc_rotation_angle rotation, > struct dc_plane_dcc_param *dcc, > bool horizontal_mirror, > unsigned int compat_level); > >+bool hubp2_is_flip_pending(struct hubp *hubp); >+ >+void hubp2_set_blank(struct hubp *hubp, bool blank); >+ >+void hubp2_cursor_set_position( >+ struct hubp *hubp, >+ const struct dc_cursor_position *pos, >+ const struct dc_cursor_mi_param *param); >+ >+void hubp2_clk_cntl(struct hubp *hubp, bool enable); >+ >+void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst); >+ >+void hubp2_clear_underflow(struct hubp *hubp); >+ >+void hubp2_read_state_common(struct hubp *hubp); >+ >+void hubp2_read_state(struct hubp *hubp); >+ > #endif /* __DC_MEM_INPUT_DCN20_H__ */ > > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 2019-08-31 15:01:11.865736169 -0500 >@@ -64,23 +64,7 @@ > #define FN(reg_name, field_name) \ > hws->shifts->field_name, hws->masks->field_name > >-static void bios_golden_init(struct dc *dc) >-{ >- struct dc_bios *bp = dc->ctx->dc_bios; >- int i; >- >- /* initialize dcn global */ >- bp->funcs->enable_disp_power_gating(bp, >- CONTROLLER_ID_D0, ASIC_PIPE_INIT); >- >- for (i = 0; i < dc->res_pool->pipe_count; i++) { >- /* initialize dcn per pipe */ >- bp->funcs->enable_disp_power_gating(bp, >- CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE); >- } >-} >- >-static void enable_power_gating_plane( >+static void dcn20_enable_power_gating_plane( > struct dce_hwseq *hws, > bool enable) > { >@@ -94,28 +78,34 @@ > REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); > REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); > REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); >- REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); >- /*Do not power gate DCHUB5, should be left at HW default, power on permanently*/ >- /*REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, force_on);*/ >+ if (REG(DOMAIN8_PG_CONFIG)) >+ REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); >+ if (REG(DOMAIN10_PG_CONFIG)) >+ REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); > > /* DPP0/1/2/3/4/5 */ > REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); > REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); > REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); > REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); >- REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); >- /*Do not power gate DPP5, should be left at HW default, power on permanently*/ >- /*REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, force_on);*/ >+ if (REG(DOMAIN9_PG_CONFIG)) >+ REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); >+ if (REG(DOMAIN11_PG_CONFIG)) >+ REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); > >+ /* DCS0/1/2/3/4/5 */ > REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); > REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); > REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); >- REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); >- REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); >- REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); >+ if (REG(DOMAIN19_PG_CONFIG)) >+ REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); >+ if (REG(DOMAIN20_PG_CONFIG)) >+ REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); >+ if (REG(DOMAIN21_PG_CONFIG)) >+ REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); > } > >-static void dcn20_dccg_init(struct dce_hwseq *hws) >+void dcn20_dccg_init(struct dce_hwseq *hws) > { > /* > * set MICROSECOND_TIME_BASE_DIV >@@ -138,8 +128,46 @@ > /* This value is dependent on the hardware pipeline delay so set once per SOC */ > REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); > } >+void dcn20_display_init(struct dc *dc) >+{ >+ struct dce_hwseq *hws = dc->hwseq; >+ >+ /* RBBMIF >+ * disable RBBMIF timeout detection for all clients >+ * Ensure RBBMIF does not drop register accesses due to the per-client timeout >+ */ >+ REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); >+ REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); > >-static void disable_vga( >+ /* DCCG */ >+ dcn20_dccg_init(hws); >+ >+ REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0); >+ >+ /* DCHUB/MMHUBBUB >+ * set global timer refclk divider >+ * 100Mhz refclk -> 2 >+ * 27Mhz refclk -> 1 >+ * 48Mhz refclk -> 1 >+ */ >+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); >+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); >+ REG_WRITE(REFCLK_CNTL, 0); >+ >+ /* OPTC >+ * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc >+ */ >+ >+ /* AZ >+ * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser, >+ * if not, it should be programmed according to the ref clock >+ */ >+ REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64); >+ /* Enable controller clock gating */ >+ REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1); >+} >+ >+void dcn20_disable_vga( > struct dce_hwseq *hws) > { > REG_WRITE(D1VGA_CONTROL, 0); >@@ -163,7 +191,7 @@ > } > > /* Blank pixel data during initialization */ >-static void dcn20_init_blank( >+void dcn20_init_blank( > struct dc *dc, > struct timing_generator *tg) > { >@@ -442,29 +470,6 @@ > } > > >- >-static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx) >-{ >- struct dce_hwseq *hws = dc->hwseq; >- struct dpp *dpp = pipe_ctx->plane_res.dpp; >- >- DC_LOGGER_INIT(dc->ctx->logger); >- >- if (REG(DC_IP_REQUEST_CNTL)) { >- REG_SET(DC_IP_REQUEST_CNTL, 0, >- IP_REQUEST_EN, 1); >- dcn20_dpp_pg_control(hws, dpp->inst, false); >- dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false); >- dpp->funcs->dpp_reset(dpp); >- REG_SET(DC_IP_REQUEST_CNTL, 0, >- IP_REQUEST_EN, 0); >- DC_LOG_DEBUG( >- "Power gated front end %d\n", pipe_ctx->pipe_idx); >- } >-} >- >- >- > /* disable HW used by plane. > * note: cannot disable until disconnect is complete > */ >@@ -490,7 +495,9 @@ > hubp->power_gated = true; > dc->optimized_required = false; /* We're powering off, no need to optimize */ > >- dcn20_plane_atomic_power_down(dc, pipe_ctx); >+ dc->hwss.plane_atomic_power_down(dc, >+ pipe_ctx->plane_res.dpp, >+ pipe_ctx->plane_res.hubp); > > pipe_ctx->stream = NULL; > memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); >@@ -514,199 +521,6 @@ > pipe_ctx->pipe_idx); > } > >-static void dcn20_init_hw(struct dc *dc) >-{ >- int i, j; >- struct abm *abm = dc->res_pool->abm; >- struct dmcu *dmcu = dc->res_pool->dmcu; >- struct dce_hwseq *hws = dc->hwseq; >- struct dc_bios *dcb = dc->ctx->dc_bios; >- struct resource_pool *res_pool = dc->res_pool; >- struct dc_state *context = dc->current_state; >- struct dc_firmware_info fw_info = { { 0 } }; >- >- if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) >- dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); >- >- // Initialize the dccg >- if (res_pool->dccg->funcs->dccg_init) >- res_pool->dccg->funcs->dccg_init(res_pool->dccg); >- >- //Enable ability to power gate / don't force power on permanently >- enable_power_gating_plane(dc->hwseq, true); >- >- if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { >- REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); >- REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); >- >- dcn20_dccg_init(hws); >- >- REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); >- REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); >- REG_WRITE(REFCLK_CNTL, 0); >- } else { >- if (!dcb->funcs->is_accelerated_mode(dcb)) { >- bios_golden_init(dc); >- if (dc->ctx->dc_bios->funcs->get_firmware_info( >- dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { >- res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency; >- >- if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { >- if (res_pool->dccg && res_pool->hubbub) { >- >- (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, >- fw_info.pll_info.crystal_frequency, >- &res_pool->ref_clocks.dccg_ref_clock_inKhz); >- >- (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, >- res_pool->ref_clocks.dccg_ref_clock_inKhz, >- &res_pool->ref_clocks.dchub_ref_clock_inKhz); >- } else { >- // Not all ASICs have DCCG sw component >- res_pool->ref_clocks.dccg_ref_clock_inKhz = >- res_pool->ref_clocks.xtalin_clock_inKhz; >- res_pool->ref_clocks.dchub_ref_clock_inKhz = >- res_pool->ref_clocks.xtalin_clock_inKhz; >- } >- } >- } else >- ASSERT_CRITICAL(false); >- disable_vga(dc->hwseq); >- } >- >- for (i = 0; i < dc->link_count; i++) { >- /* Power up AND update implementation according to the >- * required signal (which may be different from the >- * default signal on connector). >- */ >- struct dc_link *link = dc->links[i]; >- >- link->link_enc->funcs->hw_init(link->link_enc); >- } >- } >- >- /* Blank pixel data with OPP DPG */ >- for (i = 0; i < dc->res_pool->timing_generator_count; i++) { >- struct timing_generator *tg = dc->res_pool->timing_generators[i]; >- >- if (tg->funcs->is_tg_enabled(tg)) { >- dcn20_init_blank(dc, tg); >- } >- } >- >- for (i = 0; i < res_pool->timing_generator_count; i++) { >- struct timing_generator *tg = dc->res_pool->timing_generators[i]; >- >- if (tg->funcs->is_tg_enabled(tg)) >- tg->funcs->lock(tg); >- } >- >- for (i = 0; i < dc->res_pool->pipe_count; i++) { >- struct dpp *dpp = res_pool->dpps[i]; >- >- dpp->funcs->dpp_reset(dpp); >- } >- >- /* Reset all MPCC muxes */ >- res_pool->mpc->funcs->mpc_init(res_pool->mpc); >- >- /* initialize OPP mpc_tree parameter */ >- for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { >- res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; >- res_pool->opps[i]->mpc_tree_params.opp_list = NULL; >- for (j = 0; j < MAX_PIPES; j++) >- res_pool->opps[i]->mpcc_disconnect_pending[j] = false; >- } >- >- for (i = 0; i < dc->res_pool->pipe_count; i++) { >- struct timing_generator *tg = dc->res_pool->timing_generators[i]; >- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; >- struct hubp *hubp = dc->res_pool->hubps[i]; >- struct dpp *dpp = dc->res_pool->dpps[i]; >- >- pipe_ctx->stream_res.tg = tg; >- pipe_ctx->pipe_idx = i; >- >- pipe_ctx->plane_res.hubp = hubp; >- pipe_ctx->plane_res.dpp = dpp; >- pipe_ctx->plane_res.mpcc_inst = dpp->inst; >- hubp->mpcc_id = dpp->inst; >- hubp->opp_id = OPP_ID_INVALID; >- hubp->power_gated = false; >- pipe_ctx->stream_res.opp = NULL; >- >- hubp->funcs->hubp_init(hubp); >- >- //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; >- //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; >- dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; >- pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; >- /*to do*/ >- hwss1_plane_atomic_disconnect(dc, pipe_ctx); >- } >- >- /* initialize DWB pointer to MCIF_WB */ >- for (i = 0; i < res_pool->res_cap->num_dwb; i++) >- res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; >- >- for (i = 0; i < dc->res_pool->timing_generator_count; i++) { >- struct timing_generator *tg = dc->res_pool->timing_generators[i]; >- >- if (tg->funcs->is_tg_enabled(tg)) >- tg->funcs->unlock(tg); >- } >- >- for (i = 0; i < dc->res_pool->pipe_count; i++) { >- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; >- >- dc->hwss.disable_plane(dc, pipe_ctx); >- >- pipe_ctx->stream_res.tg = NULL; >- pipe_ctx->plane_res.hubp = NULL; >- } >- >- for (i = 0; i < dc->res_pool->timing_generator_count; i++) { >- struct timing_generator *tg = dc->res_pool->timing_generators[i]; >- >- tg->funcs->tg_init(tg); >- } >- >- /* end of FPGA. Below if real ASIC */ >- if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) >- return; >- >- >- for (i = 0; i < res_pool->audio_count; i++) { >- struct audio *audio = res_pool->audios[i]; >- >- audio->funcs->hw_init(audio); >- } >- >- if (abm != NULL) { >- abm->funcs->init_backlight(abm); >- abm->funcs->abm_init(abm); >- } >- >- if (dmcu != NULL) >- dmcu->funcs->dmcu_init(dmcu); >- >- if (abm != NULL && dmcu != NULL) >- abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); >- >- /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ >- REG_WRITE(DIO_MEM_PWR_CTRL, 0); >- >- if (!dc->debug.disable_clock_gate) { >- /* enable all DCN clock gating */ >- REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); >- >- REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); >- >- REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); >- } >- >-} >- > enum dc_status dcn20_enable_stream_timing( > struct pipe_ctx *pipe_ctx, > struct dc_state *context, >@@ -715,11 +529,9 @@ > struct dc_stream_state *stream = pipe_ctx->stream; > struct drr_params params = {0}; > unsigned int event_triggers = 0; >- >- >-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) >- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >-#endif >+ struct pipe_ctx *odm_pipe; >+ int opp_cnt = 1; >+ int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; > > /* by upper caller loop, pipe0 is parent pipe and be called first. > * back end is set up by for pipe0. Other children pipe share back end >@@ -730,12 +542,17 @@ > > /* TODO check if timing_changed, disable stream if timing changed */ > >- if (odm_pipe) >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { >+ opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; >+ opp_cnt++; >+ } >+ >+ if (opp_cnt > 1) > pipe_ctx->stream_res.tg->funcs->set_odm_combine( > pipe_ctx->stream_res.tg, >- odm_pipe->stream_res.opp->inst, >- pipe_ctx->stream->timing.h_addressable/2, >- pipe_ctx->stream->timing.pixel_encoding); >+ opp_inst, opp_cnt, >+ &pipe_ctx->stream->timing); >+ > /* HW program guide assume display already disable > * by unplug sequence. OTG assume stop. > */ >@@ -759,11 +576,7 @@ > pipe_ctx->stream->signal, > true); > >- if (pipe_ctx->stream_res.tg->funcs->setup_global_lock) >- pipe_ctx->stream_res.tg->funcs->setup_global_lock( >- pipe_ctx->stream_res.tg); >- >- if (odm_pipe) >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) > odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( > odm_pipe->stream_res.opp, > true); >@@ -784,6 +597,8 @@ > > params.vertical_total_min = stream->adjust.v_total_min; > params.vertical_total_max = stream->adjust.v_total_max; >+ params.vertical_total_mid = stream->adjust.v_total_mid; >+ params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; > if (pipe_ctx->stream_res.tg->funcs->set_drr) > pipe_ctx->stream_res.tg->funcs->set_drr( > pipe_ctx->stream_res.tg, ¶ms); >@@ -814,6 +629,10 @@ > { > struct mpc *mpc = dc->res_pool->mpc; > enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; >+ int mpcc_id = pipe_ctx->plane_res.hubp->inst; >+ >+ if (mpc->funcs->power_on_mpc_mem_pwr) >+ mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); > > if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { > if (mpc->funcs->set_output_csc != NULL) >@@ -843,7 +662,9 @@ > * if programming for all pipes is required then remove condition > * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. > */ >- if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx)) >+ if (mpc->funcs->power_on_mpc_mem_pwr) >+ mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); >+ if (pipe_ctx->top_pipe == NULL > && mpc->funcs->set_output_gamma && stream->out_transfer_func) { > if (stream->out_transfer_func->type == TF_TYPE_HWPWL) > params = &stream->out_transfer_func->pwl; >@@ -909,14 +730,14 @@ > > result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); > if (plane_state->lut3d_func && >- plane_state->lut3d_func->initialized == true) >+ plane_state->lut3d_func->state.bits.initialized == 1) > result = dpp_base->funcs->dpp_program_3dlut(dpp_base, > &plane_state->lut3d_func->lut_3d); > else > result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); > > if (plane_state->lut3d_func && >- plane_state->lut3d_func->initialized == true && >+ plane_state->lut3d_func->state.bits.initialized == 1 && > plane_state->lut3d_func->hdr_multiplier != 0) > dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, > plane_state->lut3d_func->hdr_multiplier); >@@ -1005,14 +826,20 @@ > > static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) > { >- struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >+ struct pipe_ctx *odm_pipe; >+ int opp_cnt = 1; >+ int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; > >- if (combine_pipe) >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { >+ opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; >+ opp_cnt++; >+ } >+ >+ if (opp_cnt > 1) > pipe_ctx->stream_res.tg->funcs->set_odm_combine( > pipe_ctx->stream_res.tg, >- combine_pipe->stream_res.opp->inst, >- pipe_ctx->plane_res.scl_data.h_active, >- pipe_ctx->stream->timing.pixel_encoding); >+ opp_inst, opp_cnt, >+ &pipe_ctx->stream->timing); > else > pipe_ctx->stream_res.tg->funcs->set_odm_bypass( > pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); >@@ -1028,7 +855,8 @@ > struct dc_stream_state *stream = pipe_ctx->stream; > enum dc_color_space color_space = stream->output_color_space; > enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; >- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >+ struct pipe_ctx *odm_pipe; >+ int odm_cnt = 1; > > int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; > int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; >@@ -1036,8 +864,10 @@ > /* get opp dpg blank color */ > color_space_to_black_color(dc, color_space, &black_color); > >- if (bot_odm_pipe) >- width = width / 2; >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) >+ odm_cnt++; >+ >+ width = width / odm_cnt; > > if (blank) { > if (stream_res->abm) >@@ -1057,10 +887,10 @@ > width, > height); > >- if (bot_odm_pipe) { >- bot_odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( >- bot_odm_pipe->stream_res.opp, >- dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ? >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { >+ odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( >+ odm_pipe->stream_res.opp, >+ dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? > CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, > stream->timing.display_color_depth, > &black_color, >@@ -1106,6 +936,9 @@ > /* enable DCFCLK current DCHUB */ > pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); > >+ /* initialize HUBP on power up */ >+ pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); >+ > /* make sure OPP_PIPE_CLOCK_EN = 1 */ > pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( > pipe_ctx->stream_res.opp, >@@ -1201,7 +1034,7 @@ > struct pipe_ctx *pipe_ctx, > struct dc_state *context) > { >- if (pipe_ctx->top_pipe == NULL) { >+ if (pipe_ctx->top_pipe == NULL && !pipe_ctx->prev_odm_pipe) { > bool blank = !is_pipe_tree_visible(pipe_ctx); > > pipe_ctx->stream_res.tg->funcs->program_global_sync( >@@ -1223,8 +1056,13 @@ > if (pipe_ctx->plane_state != NULL) > dcn20_program_pipe(dc, pipe_ctx, context); > >- if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) >+ if (pipe_ctx->bottom_pipe != NULL) { >+ ASSERT(pipe_ctx->bottom_pipe != pipe_ctx); > dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); >+ } else if (pipe_ctx->next_odm_pipe != NULL) { >+ ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx); >+ dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context); >+ } > } > > void dcn20_pipe_control_lock_global( >@@ -1265,17 +1103,6 @@ > if (pipe->plane_state != NULL) > flip_immediate = pipe->plane_state->flip_immediate; > >- if (flip_immediate && lock) { >- while (pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) { >- udelay(1); >- } >- >- if (pipe->bottom_pipe != NULL) >- while (pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp)) { >- udelay(1); >- } >- } >- > /* In flip immediate and pipe splitting case, we need to use GSL > * for synchronization. Only do setup on locking and on flip type change. > */ >@@ -1303,18 +1130,32 @@ > int num_planes, > struct dc_state *context) > { >- >+ const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; > int i; > struct timing_generator *tg; > bool removed_pipe[6] = { false }; > bool interdependent_update = false; > struct pipe_ctx *top_pipe_to_program = > find_top_pipe_for_stream(dc, context, stream); >+ struct pipe_ctx *prev_top_pipe_to_program = >+ find_top_pipe_for_stream(dc, dc->current_state, stream); > DC_LOGGER_INIT(dc->ctx->logger); > > if (!top_pipe_to_program) > return; > >+ /* Carry over GSL groups in case the context is changing. */ >+ for (i = 0; i < dc->res_pool->pipe_count; i++) { >+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; >+ struct pipe_ctx *old_pipe_ctx = >+ &dc->current_state->res_ctx.pipe_ctx[i]; >+ >+ if (pipe_ctx->stream == stream && >+ pipe_ctx->stream == old_pipe_ctx->stream) >+ pipe_ctx->stream_res.gsl_group = >+ old_pipe_ctx->stream_res.gsl_group; >+ } >+ > tg = top_pipe_to_program->stream_res.tg; > > interdependent_update = top_pipe_to_program->plane_state && >@@ -1345,7 +1186,7 @@ > if (old_pipe_ctx->stream_res.tg == tg && > old_pipe_ctx->plane_res.hubp && > old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) >- dcn20_disable_plane(dc, old_pipe_ctx); >+ dc->hwss.disable_plane(dc, old_pipe_ctx); > } > > if ((!pipe_ctx->plane_state || >@@ -1391,6 +1232,22 @@ > for (i = 0; i < dc->res_pool->pipe_count; i++) > if (removed_pipe[i]) > dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); >+ >+ /* >+ * If we are enabling a pipe, we need to wait for pending clear as this is a critical >+ * part of the enable operation otherwise, DM may request an immediate flip which >+ * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which >+ * is unsupported on DCN. >+ */ >+ i = 0; >+ if (num_planes > 0 && top_pipe_to_program && >+ (prev_top_pipe_to_program == NULL || prev_top_pipe_to_program->plane_state == NULL)) { >+ while (i < TIMEOUT_FOR_PIPE_ENABLE_MS && >+ top_pipe_to_program->plane_res.hubp->funcs->hubp_is_flip_pending(top_pipe_to_program->plane_res.hubp)) { >+ i += 1; >+ msleep(1); >+ } >+ } > } > > >@@ -1400,16 +1257,16 @@ > { > struct hubbub *hubbub = dc->res_pool->hubbub; > >+ dc->clk_mgr->funcs->update_clocks( >+ dc->clk_mgr, >+ context, >+ false); >+ > /* program dchubbub watermarks */ > hubbub->funcs->program_watermarks(hubbub, > &context->bw_ctx.bw.dcn.watermarks, > dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, > false); >- >- dc->clk_mgr->funcs->update_clocks( >- dc->clk_mgr, >- context, >- false); > } > > void dcn20_optimize_bandwidth( >@@ -1462,8 +1319,8 @@ > > pipe_ctx->stream_res.tg->funcs->set_vtg_params( > pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); >- >- dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); >+ if (pipe_ctx->prev_odm_pipe == NULL) >+ dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); > } > > pipe_ctx->plane_res.hubp->funcs->hubp_setup( >@@ -1553,12 +1410,15 @@ > { > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > struct dce_hwseq *hws = dc->hwseq; >- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); > > if (pipe_ctx->stream_res.dsc) { >+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; >+ > dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); >- if (bot_odm_pipe) >- dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, true); >+ while (odm_pipe) { >+ dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); >+ odm_pipe = odm_pipe->next_odm_pipe; >+ } > } > #endif > } >@@ -1567,12 +1427,15 @@ > { > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > struct dce_hwseq *hws = dc->hwseq; >- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); > > if (pipe_ctx->stream_res.dsc) { >+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; >+ > dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); >- if (bot_odm_pipe) >- dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, false); >+ while (odm_pipe) { >+ dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); >+ odm_pipe = odm_pipe->next_odm_pipe; >+ } > } > #endif > } >@@ -1597,9 +1460,9 @@ > hubp->funcs->dmdata_set_attributes(hubp, &attr); > } > >-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option) >+void dcn20_disable_stream(struct pipe_ctx *pipe_ctx) > { >- dce110_disable_stream(pipe_ctx, option); >+ dce110_disable_stream(pipe_ctx); > } > > static void dcn20_init_vm_ctx( >@@ -1637,6 +1500,7 @@ > config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; > config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; > config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; >+ config.page_table_default_page_addr = pa_config->page_table_default_page_addr; > > return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); > } >@@ -1702,18 +1566,22 @@ > struct encoder_unblank_param params = { { 0 } }; > struct dc_stream_state *stream = pipe_ctx->stream; > struct dc_link *link = stream->link; >- params.odm = dc_res_get_odm_bottom_pipe(pipe_ctx); >+ struct pipe_ctx *odm_pipe; > >+ params.opp_cnt = 1; >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { >+ params.opp_cnt++; >+ } > /* only 3 items below are used by unblank */ > params.timing = pipe_ctx->stream->timing; > > params.link_settings.link_rate = link_settings->link_rate; > > if (dc_is_dp_signal(pipe_ctx->stream->signal)) { >- if (optc1_is_two_pixels_per_containter(&stream->timing) || params.odm) >+ if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) > params.timing.pix_clk_100hz /= 2; > pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( >- pipe_ctx->stream_res.stream_enc, params.odm); >+ pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); > pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); > } > >@@ -1749,14 +1617,29 @@ > if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { > /* DPMS may already disable */ > if (!pipe_ctx->stream->dpms_off) >- core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); >- else if (pipe_ctx->stream_res.audio) { >- dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); >+ core_link_disable_stream(pipe_ctx); >+ else if (pipe_ctx->stream_res.audio) >+ dc->hwss.disable_audio_stream(pipe_ctx); >+ >+ /* free acquired resources */ >+ if (pipe_ctx->stream_res.audio) { >+ /*disable az_endpoint*/ >+ pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); >+ >+ /*free audio*/ >+ if (dc->caps.dynamic_audio == true) { >+ /*we have to dynamic arbitrate the audio endpoints*/ >+ /*we free the resource, need reset is_audio_acquired*/ >+ update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, >+ pipe_ctx->stream_res.audio, false); >+ pipe_ctx->stream_res.audio = NULL; >+ } > } > } > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- else if (pipe_ctx->stream_res.dsc) >+ else if (pipe_ctx->stream_res.dsc) { > dp_set_dsc_enable(pipe_ctx, false); >+ } > #endif > > /* by upper caller loop, parent pipe: pipe0, will be reset last. >@@ -1770,6 +1653,10 @@ > if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) > pipe_ctx->stream_res.tg->funcs->set_odm_bypass( > pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); >+ >+ if (pipe_ctx->stream_res.tg->funcs->set_drr) >+ pipe_ctx->stream_res.tg->funcs->set_drr( >+ pipe_ctx->stream_res.tg, NULL); > } > > for (i = 0; i < dc->res_pool->pipe_count; i++) >@@ -1799,7 +1686,7 @@ > if (!pipe_ctx_old->stream) > continue; > >- if (pipe_ctx_old->top_pipe) >+ if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) > continue; > > if (!pipe_ctx->stream || >@@ -1819,7 +1706,7 @@ > { > struct hubp *hubp = pipe_ctx->plane_res.hubp; > struct mpcc_blnd_cfg blnd_cfg = { {0} }; >- bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; >+ bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; > int mpcc_id; > struct mpcc *new_mpcc; > struct mpc *mpc = dc->res_pool->mpc; >@@ -2012,14 +1899,198 @@ > > } > >+static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) >+{ >+ enum dc_lane_count lane_count = >+ pipe_ctx->stream->link->cur_link_settings.lane_count; >+ >+ struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; >+ struct dc_link *link = pipe_ctx->stream->link; >+ >+ uint32_t active_total_with_borders; >+ uint32_t early_control = 0; >+ struct timing_generator *tg = pipe_ctx->stream_res.tg; >+ >+ /* For MST, there are multiply stream go to only one link. >+ * connect DIG back_end to front_end while enable_stream and >+ * disconnect them during disable_stream >+ * BY this, it is logic clean to separate stream and link >+ */ >+ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, >+ pipe_ctx->stream_res.stream_enc->id, true); >+ >+ if (link->dc->hwss.program_dmdata_engine) >+ link->dc->hwss.program_dmdata_engine(pipe_ctx); >+ >+ link->dc->hwss.update_info_frame(pipe_ctx); >+ >+ /* enable early control to avoid corruption on DP monitor*/ >+ active_total_with_borders = >+ timing->h_addressable >+ + timing->h_border_left >+ + timing->h_border_right; >+ >+ if (lane_count != 0) >+ early_control = active_total_with_borders % lane_count; >+ >+ if (early_control == 0) >+ early_control = lane_count; >+ >+ tg->funcs->set_early_control(tg, early_control); >+ >+ /* enable audio only within mode set */ >+ if (pipe_ctx->stream_res.audio != NULL) { >+ if (dc_is_dp_signal(pipe_ctx->stream->signal)) >+ pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); >+ } >+} >+ >+static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) >+{ >+ struct dc_stream_state *stream = pipe_ctx->stream; >+ struct hubp *hubp = pipe_ctx->plane_res.hubp; >+ bool enable = false; >+ struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; >+ enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) >+ ? dmdata_dp >+ : dmdata_hdmi; >+ >+ /* if using dynamic meta, don't set up generic infopackets */ >+ if (pipe_ctx->stream->dmdata_address.quad_part != 0) { >+ pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; >+ enable = true; >+ } >+ >+ if (!hubp) >+ return; >+ >+ if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) >+ return; >+ >+ stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, >+ hubp->inst, mode); >+} >+ >+static void dcn20_fpga_init_hw(struct dc *dc) >+{ >+ int i, j; >+ struct dce_hwseq *hws = dc->hwseq; >+ struct resource_pool *res_pool = dc->res_pool; >+ struct dc_state *context = dc->current_state; >+ >+ if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) >+ dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); >+ >+ // Initialize the dccg >+ if (res_pool->dccg->funcs->dccg_init) >+ res_pool->dccg->funcs->dccg_init(res_pool->dccg); >+ >+ //Enable ability to power gate / don't force power on permanently >+ dc->hwss.enable_power_gating_plane(hws, true); >+ >+ // Specific to FPGA dccg and registers >+ REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); >+ REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); >+ >+ dcn20_dccg_init(hws); >+ >+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); >+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); >+ REG_WRITE(REFCLK_CNTL, 0); >+ // >+ >+ >+ /* Blank pixel data with OPP DPG */ >+ for (i = 0; i < dc->res_pool->timing_generator_count; i++) { >+ struct timing_generator *tg = dc->res_pool->timing_generators[i]; >+ >+ if (tg->funcs->is_tg_enabled(tg)) >+ dcn20_init_blank(dc, tg); >+ } >+ >+ for (i = 0; i < res_pool->timing_generator_count; i++) { >+ struct timing_generator *tg = dc->res_pool->timing_generators[i]; >+ >+ if (tg->funcs->is_tg_enabled(tg)) >+ tg->funcs->lock(tg); >+ } >+ >+ for (i = 0; i < dc->res_pool->pipe_count; i++) { >+ struct dpp *dpp = res_pool->dpps[i]; >+ >+ dpp->funcs->dpp_reset(dpp); >+ } >+ >+ /* Reset all MPCC muxes */ >+ res_pool->mpc->funcs->mpc_init(res_pool->mpc); >+ >+ /* initialize OPP mpc_tree parameter */ >+ for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { >+ res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; >+ res_pool->opps[i]->mpc_tree_params.opp_list = NULL; >+ for (j = 0; j < MAX_PIPES; j++) >+ res_pool->opps[i]->mpcc_disconnect_pending[j] = false; >+ } >+ >+ for (i = 0; i < dc->res_pool->pipe_count; i++) { >+ struct timing_generator *tg = dc->res_pool->timing_generators[i]; >+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; >+ struct hubp *hubp = dc->res_pool->hubps[i]; >+ struct dpp *dpp = dc->res_pool->dpps[i]; >+ >+ pipe_ctx->stream_res.tg = tg; >+ pipe_ctx->pipe_idx = i; >+ >+ pipe_ctx->plane_res.hubp = hubp; >+ pipe_ctx->plane_res.dpp = dpp; >+ pipe_ctx->plane_res.mpcc_inst = dpp->inst; >+ hubp->mpcc_id = dpp->inst; >+ hubp->opp_id = OPP_ID_INVALID; >+ hubp->power_gated = false; >+ pipe_ctx->stream_res.opp = NULL; >+ >+ hubp->funcs->hubp_init(hubp); >+ >+ //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; >+ //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; >+ dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; >+ pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; >+ /*to do*/ >+ hwss1_plane_atomic_disconnect(dc, pipe_ctx); >+ } >+ >+ /* initialize DWB pointer to MCIF_WB */ >+ for (i = 0; i < res_pool->res_cap->num_dwb; i++) >+ res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; >+ >+ for (i = 0; i < dc->res_pool->timing_generator_count; i++) { >+ struct timing_generator *tg = dc->res_pool->timing_generators[i]; >+ >+ if (tg->funcs->is_tg_enabled(tg)) >+ tg->funcs->unlock(tg); >+ } >+ >+ for (i = 0; i < dc->res_pool->pipe_count; i++) { >+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; >+ >+ dc->hwss.disable_plane(dc, pipe_ctx); >+ >+ pipe_ctx->stream_res.tg = NULL; >+ pipe_ctx->plane_res.hubp = NULL; >+ } >+ >+ for (i = 0; i < dc->res_pool->timing_generator_count; i++) { >+ struct timing_generator *tg = dc->res_pool->timing_generators[i]; >+ >+ tg->funcs->tg_init(tg); >+ } >+} >+ > void dcn20_hw_sequencer_construct(struct dc *dc) > { > dcn10_hw_sequencer_construct(dc); >- dc->hwss.init_hw = dcn20_init_hw; >- dc->hwss.init_pipes = NULL; > dc->hwss.unblank_stream = dcn20_unblank_stream; > dc->hwss.update_plane_addr = dcn20_update_plane_addr; >- dc->hwss.disable_plane = dcn20_disable_plane, > dc->hwss.enable_stream_timing = dcn20_enable_stream_timing; > dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer; > dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func; >@@ -2036,6 +2107,8 @@ > dc->hwss.update_odm = dcn20_update_odm; > dc->hwss.blank_pixel_data = dcn20_blank_pixel_data; > dc->hwss.dmdata_status_done = dcn20_dmdata_status_done; >+ dc->hwss.program_dmdata_engine = dcn20_program_dmdata_engine; >+ dc->hwss.enable_stream = dcn20_enable_stream; > dc->hwss.disable_stream = dcn20_disable_stream; > dc->hwss.init_sys_ctx = dcn20_init_sys_ctx; > dc->hwss.init_vm_ctx = dcn20_init_vm_ctx; >@@ -2045,5 +2118,23 @@ > dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap; > dc->hwss.update_mpcc = dcn20_update_mpcc; > dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl; >- dc->hwss.did_underflow_occur = dcn10_did_underflow_occur; >+ dc->hwss.init_blank = dcn20_init_blank; >+ dc->hwss.disable_plane = dcn20_disable_plane; >+ dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable; >+ dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane; >+ dc->hwss.dpp_pg_control = dcn20_dpp_pg_control; >+ dc->hwss.hubp_pg_control = dcn20_hubp_pg_control; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ dc->hwss.dsc_pg_control = dcn20_dsc_pg_control; >+#else >+ dc->hwss.dsc_pg_control = NULL; >+#endif >+ dc->hwss.disable_vga = dcn20_disable_vga; >+ >+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { >+ dc->hwss.init_hw = dcn20_fpga_init_hw; >+ dc->hwss.init_pipes = NULL; >+ } >+ >+ > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 2019-08-31 15:01:11.865736169 -0500 >@@ -75,7 +75,7 @@ > > void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx); > >-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option); >+void dcn20_disable_stream(struct pipe_ctx *pipe_ctx); > > void dcn20_program_tripleBuffer( > const struct dc *dc, >@@ -91,13 +91,9 @@ > void dcn20_setup_gsl_group_as_lock(const struct dc *dc, > struct pipe_ctx *pipe_ctx, > bool enable); >-void dcn20_pipe_control_lock( >- struct dc *dc, >- struct pipe_ctx *pipe, >- bool lock); >-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx); >-void dcn20_enable_plane( >- struct dc *dc, >- struct pipe_ctx *pipe_ctx, >- struct dc_state *context); >+void dcn20_dccg_init(struct dce_hwseq *hws); >+void dcn20_init_blank( >+ struct dc *dc, >+ struct timing_generator *tg); >+void dcn20_display_init(struct dc *dc); > #endif /* __DC_HWSS_DCN20_H__ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 2019-08-31 15:01:11.866736169 -0500 >@@ -341,6 +341,7 @@ > .fec_set_enable = enc2_fec_set_enable, > .fec_set_ready = enc2_fec_set_ready, > .fec_is_active = enc2_fec_is_active, >+ .get_dig_mode = dcn10_get_dig_mode, > .get_dig_frontend = dcn10_get_dig_frontend, > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 2019-08-31 15:01:11.866736169 -0500 >@@ -233,14 +233,14 @@ > reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; > } > >-static void mpc20_power_on_ogam_lut( >+void mpc20_power_on_ogam_lut( > struct mpc *mpc, int mpcc_id, > bool power_on) > { > struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); > > REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, >- MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1); >+ MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0); > > } > >@@ -368,6 +368,11 @@ > { > struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); > >+ if (mpc->ctx->dc->debug.cm_in_bypass) { >+ REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); >+ return; >+ } >+ > if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) { > /*hw fixed in new review*/ > return; >@@ -390,10 +395,16 @@ > enum dc_lut_mode next_mode; > struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); > >+ if (mpc->ctx->dc->debug.cm_in_bypass) { >+ REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); >+ return; >+ } >+ > if (params == NULL) { > REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); > return; > } >+ > current_mode = mpc20_get_ogam_current(mpc, mpcc_id); > if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) > next_mode = LUT_RAM_B; >@@ -435,23 +446,22 @@ > { > struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); > unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled; >- REG_GET(MPCC_STATUS[mpcc_id], MPCC_DISABLED, &mpc_disabled); >- >- if (mpc_disabled) { >- ASSERT(0); >- return; >- } > > REG_GET(MPCC_TOP_SEL[mpcc_id], > MPCC_TOP_SEL, &top_sel); > >- if (top_sel == 0xf) { >- REG_GET_2(MPCC_STATUS[mpcc_id], >- MPCC_BUSY, &mpc_busy, >- MPCC_IDLE, &mpc_idle); >+ REG_GET_3(MPCC_STATUS[mpcc_id], >+ MPCC_BUSY, &mpc_busy, >+ MPCC_IDLE, &mpc_idle, >+ MPCC_DISABLED, &mpc_disabled); > >- ASSERT(mpc_busy == 0); >- ASSERT(mpc_idle == 1); >+ if (top_sel == 0xf) { >+ ASSERT(!mpc_busy); >+ ASSERT(mpc_idle); >+ ASSERT(mpc_disabled); >+ } else { >+ ASSERT(!mpc_disabled); >+ ASSERT(!mpc_idle); > } > } > >@@ -488,6 +498,7 @@ > .insert_plane = mpc1_insert_plane, > .remove_mpcc = mpc1_remove_mpcc, > .mpc_init = mpc1_mpc_init, >+ .mpc_init_single_inst = mpc1_mpc_init_single_inst, > .update_blending = mpc2_update_blending, > .get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp, > .wait_for_idle = mpc2_assert_idle_mpcc, >@@ -498,6 +509,7 @@ > .set_output_csc = mpc2_set_output_csc, > .set_ocsc_default = mpc2_set_ocsc_default, > .set_output_gamma = mpc2_set_output_gamma, >+ .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut, > }; > > void dcn20_mpc_construct(struct dcn20_mpc *mpc20, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 2019-08-31 15:01:11.866736169 -0500 >@@ -159,6 +159,7 @@ > SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\ > SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\ > SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ >+ SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ > SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ > SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\ > SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\ >@@ -173,6 +174,7 @@ > SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ > SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh) > >+ > #define MPC_REG_FIELD_LIST_DCN2_0(type) \ > MPC_REG_FIELD_LIST(type)\ > type MPCC_BG_BPC;\ >@@ -217,7 +219,8 @@ > type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\ > type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\ > type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\ >- type MPCC_DISABLED; >+ type MPCC_DISABLED;\ >+ type MPCC_OGAM_MEM_PWR_DIS; > > struct dcn20_mpc_registers { > MPC_REG_VARIABLE_LIST_DCN2_0 >@@ -282,4 +285,5 @@ > > void mpc2_assert_idle_mpcc(struct mpc *mpc, int id); > void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id); >+void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on); > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 2019-08-31 15:01:11.866736169 -0500 >@@ -332,7 +332,6 @@ > .opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator, > .dpg_is_blanked = opp2_dpg_is_blanked, > .opp_dpg_set_blank_color = opp2_dpg_set_blank_color, >- .opp_convert_pti = NULL, > .opp_destroy = opp1_destroy, > .opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel, > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 2019-08-31 15:01:11.866736169 -0500 >@@ -191,15 +191,6 @@ > uint32_t dsc_slice_width) > { > struct optc *optc1 = DCN10TG_FROM_TG(optc); >- uint32_t data_format = 0; >- /* skip if dsc mode is not changed */ >- data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL)); >- >- data_format = data_format & 0x30; /* bit5:4 */ >- data_format = data_format >> 4; >- >- if (data_format == dsc_mode) >- return; > > REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, > OPTC_DSC_MODE, dsc_mode); >@@ -224,7 +215,6 @@ > struct optc *optc1 = DCN10TG_FROM_TG(optc); > uint32_t h_div_2 = 0; > >- optc1->comb_opp_id = 0xf; > REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, > OPTC_NUM_OF_INPUT_SEGMENT, 0, > OPTC_SEG0_SRC_SEL, optc->inst, >@@ -236,13 +226,16 @@ > OTG_H_TIMING_DIV_BY2, h_div_2); > REG_SET(OPTC_MEMORY_CONFIG, 0, > OPTC_MEM_SEL, 0); >+ optc1->opp_count = 1; > } > >-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, >- int mpcc_hactive, enum dc_pixel_encoding pixel_encoding) >+void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, >+ struct dc_crtc_timing *timing) > { > struct optc *optc1 = DCN10TG_FROM_TG(optc); > /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */ >+ int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) >+ / opp_cnt; > int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf; > uint32_t data_fmt = 0; > >@@ -257,23 +250,24 @@ > REG_SET(OPTC_MEMORY_CONFIG, 0, > OPTC_MEM_SEL, memory_mask << (optc->inst * 4)); > >- if (pixel_encoding == PIXEL_ENCODING_YCBCR422) >+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) > data_fmt = 1; >- else if (pixel_encoding == PIXEL_ENCODING_YCBCR420) >+ else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) > data_fmt = 2; > > REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); > >+ ASSERT(opp_cnt == 2); > REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, > OPTC_NUM_OF_INPUT_SEGMENT, 1, >- OPTC_SEG0_SRC_SEL, optc->inst, >- OPTC_SEG1_SRC_SEL, combine_opp_id); >+ OPTC_SEG0_SRC_SEL, opp_id[0], >+ OPTC_SEG1_SRC_SEL, opp_id[1]); > > REG_UPDATE(OPTC_WIDTH_CONTROL, > OPTC_SEGMENT_WIDTH, mpcc_hactive); > > REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); >- optc1->comb_opp_id = combine_opp_id; >+ optc1->opp_count = opp_cnt; > } > > void optc2_get_optc_source(struct timing_generator *optc, >@@ -339,65 +333,6 @@ > > } > >- >-void optc2_setup_global_lock(struct timing_generator *optc) >-{ >- struct optc *optc1 = DCN10TG_FROM_TG(optc); >- uint32_t v_blank_start = 0; >- uint32_t h_blank_start = 0, h_total = 0; >- >- REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1); >- >- REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20); >- >- REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); >- >- REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); >- >- REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &h_total); >- REG_UPDATE_2(OTG_GLOBAL_CONTROL1, >- MASTER_UPDATE_LOCK_DB_X, >- h_blank_start - 200 - 1, >- MASTER_UPDATE_LOCK_DB_Y, >- v_blank_start - 1); >-} >- >-void optc2_lock_global(struct timing_generator *optc) >-{ >- struct optc *optc1 = DCN10TG_FROM_TG(optc); >- >- REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1); >- >- REG_SET(OTG_GLOBAL_CONTROL0, 0, >- OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); >- REG_SET(OTG_MASTER_UPDATE_LOCK, 0, >- OTG_MASTER_UPDATE_LOCK, 1); >- >- /* Should be fast, status does not update on maximus */ >- if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) >- REG_WAIT(OTG_MASTER_UPDATE_LOCK, >- UPDATE_LOCK_STATUS, 1, >- 1, 10); >-} >- >-void optc2_lock(struct timing_generator *optc) >-{ >- struct optc *optc1 = DCN10TG_FROM_TG(optc); >- >- REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0); >- >- REG_SET(OTG_GLOBAL_CONTROL0, 0, >- OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); >- REG_SET(OTG_MASTER_UPDATE_LOCK, 0, >- OTG_MASTER_UPDATE_LOCK, 1); >- >- /* Should be fast, status does not update on maximus */ >- if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) >- REG_WAIT(OTG_MASTER_UPDATE_LOCK, >- UPDATE_LOCK_STATUS, 1, >- 1, 10); >-} >- > void optc2_lock_doublebuffer_enable(struct timing_generator *optc) > { > struct optc *optc1 = DCN10TG_FROM_TG(optc); >@@ -492,10 +427,8 @@ > .triplebuffer_lock = optc2_triplebuffer_lock, > .triplebuffer_unlock = optc2_triplebuffer_unlock, > .disable_reset_trigger = optc1_disable_reset_trigger, >- .lock = optc2_lock, >+ .lock = optc1_lock, > .unlock = optc1_unlock, >- .lock_global = optc2_lock_global, >- .setup_global_lock = optc2_setup_global_lock, > .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable, > .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable, > .enable_optc_clock = optc1_enable_optc_clock, >@@ -522,7 +455,8 @@ > .set_gsl_source_select = optc2_set_gsl_source_select, > .set_vtg_params = optc1_set_vtg_params, > .program_manual_trigger = optc2_program_manual_trigger, >- .setup_manual_trigger = optc2_setup_manual_trigger >+ .setup_manual_trigger = optc2_setup_manual_trigger, >+ .is_matching_timing = optc1_is_matching_timing > }; > > void dcn20_timing_generator_init(struct optc *optc1) >@@ -537,6 +471,5 @@ > optc1->min_v_blank_interlace = 5; > optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue. > optc1->min_v_sync_width = 1; >- optc1->comb_opp_id = 0xf; > } > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 2019-08-31 15:01:11.866736169 -0500 >@@ -96,8 +96,8 @@ > void optc2_set_odm_bypass(struct timing_generator *optc, > const struct dc_crtc_timing *dc_crtc_timing); > >-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, >- int mpcc_hactive, enum dc_pixel_encoding pixel_encoding); >+void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, >+ struct dc_crtc_timing *timing); > > void optc2_get_optc_source(struct timing_generator *optc, > uint32_t *num_of_src_opp, >@@ -106,9 +106,6 @@ > > void optc2_triplebuffer_lock(struct timing_generator *optc); > void optc2_triplebuffer_unlock(struct timing_generator *optc); >-void optc2_lock(struct timing_generator *optc); >-void optc2_lock_global(struct timing_generator *optc); >-void optc2_setup_global_lock(struct timing_generator *optc); > void optc2_lock_doublebuffer_disable(struct timing_generator *optc); > void optc2_lock_doublebuffer_enable(struct timing_generator *optc); > void optc2_program_manual_trigger(struct timing_generator *optc); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 2019-08-31 15:01:11.866736169 -0500 >@@ -82,6 +82,7 @@ > > #include "amdgpu_socbb.h" > >+/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */ > #define SOC_BOUNDING_BOX_VALID false > #define DC_LOGGER_INIT(logger) > >@@ -156,8 +157,119 @@ > .xfc_fill_constant_bytes = 0, > }; > >-struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 }; >+struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { >+ /* Defaults that get patched on driver load from firmware. */ >+ .clock_limits = { >+ { >+ .state = 0, >+ .dcfclk_mhz = 560.0, >+ .fabricclk_mhz = 560.0, >+ .dispclk_mhz = 513.0, >+ .dppclk_mhz = 513.0, >+ .phyclk_mhz = 540.0, >+ .socclk_mhz = 560.0, >+ .dscclk_mhz = 171.0, >+ .dram_speed_mts = 8960.0, >+ }, >+ { >+ .state = 1, >+ .dcfclk_mhz = 694.0, >+ .fabricclk_mhz = 694.0, >+ .dispclk_mhz = 642.0, >+ .dppclk_mhz = 642.0, >+ .phyclk_mhz = 600.0, >+ .socclk_mhz = 694.0, >+ .dscclk_mhz = 214.0, >+ .dram_speed_mts = 11104.0, >+ }, >+ { >+ .state = 2, >+ .dcfclk_mhz = 875.0, >+ .fabricclk_mhz = 875.0, >+ .dispclk_mhz = 734.0, >+ .dppclk_mhz = 734.0, >+ .phyclk_mhz = 810.0, >+ .socclk_mhz = 875.0, >+ .dscclk_mhz = 245.0, >+ .dram_speed_mts = 14000.0, >+ }, >+ { >+ .state = 3, >+ .dcfclk_mhz = 1000.0, >+ .fabricclk_mhz = 1000.0, >+ .dispclk_mhz = 1100.0, >+ .dppclk_mhz = 1100.0, >+ .phyclk_mhz = 810.0, >+ .socclk_mhz = 1000.0, >+ .dscclk_mhz = 367.0, >+ .dram_speed_mts = 16000.0, >+ }, >+ { >+ .state = 4, >+ .dcfclk_mhz = 1200.0, >+ .fabricclk_mhz = 1200.0, >+ .dispclk_mhz = 1284.0, >+ .dppclk_mhz = 1284.0, >+ .phyclk_mhz = 810.0, >+ .socclk_mhz = 1200.0, >+ .dscclk_mhz = 428.0, >+ .dram_speed_mts = 16000.0, >+ }, >+ /*Extra state, no dispclk ramping*/ >+ { >+ .state = 5, >+ .dcfclk_mhz = 1200.0, >+ .fabricclk_mhz = 1200.0, >+ .dispclk_mhz = 1284.0, >+ .dppclk_mhz = 1284.0, >+ .phyclk_mhz = 810.0, >+ .socclk_mhz = 1200.0, >+ .dscclk_mhz = 428.0, >+ .dram_speed_mts = 16000.0, >+ }, >+ }, >+ .num_states = 5, >+ .sr_exit_time_us = 8.6, >+ .sr_enter_plus_exit_time_us = 10.9, >+ .urgent_latency_us = 4.0, >+ .urgent_latency_pixel_data_only_us = 4.0, >+ .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, >+ .urgent_latency_vm_data_only_us = 4.0, >+ .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, >+ .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, >+ .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, >+ .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, >+ .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, >+ .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, >+ .max_avg_sdp_bw_use_normal_percent = 40.0, >+ .max_avg_dram_bw_use_normal_percent = 40.0, >+ .writeback_latency_us = 12.0, >+ .ideal_dram_bw_after_urgent_percent = 40.0, >+ .max_request_size_bytes = 256, >+ .dram_channel_width_bytes = 2, >+ .fabric_datapath_to_dcn_data_return_bytes = 64, >+ .dcn_downspread_percent = 0.5, >+ .downspread_percent = 0.38, >+ .dram_page_open_time_ns = 50.0, >+ .dram_rw_turnaround_time_ns = 17.5, >+ .dram_return_buffer_per_channel_bytes = 8192, >+ .round_trip_ping_latency_dcfclk_cycles = 131, >+ .urgent_out_of_order_return_per_channel_bytes = 256, >+ .channel_interleave_bytes = 256, >+ .num_banks = 8, >+ .num_chans = 16, >+ .vmm_page_size_bytes = 4096, >+ .dram_clock_change_latency_us = 404.0, >+ .dummy_pstate_latency_us = 5.0, >+ .writeback_dram_clock_change_latency_us = 23.0, >+ .return_bus_width_bytes = 64, >+ .dispclk_dppclk_vco_speed_mhz = 3850, >+ .xfc_bus_transport_time_us = 20, >+ .xfc_xbuf_latency_tolerance_us = 4, >+ .use_urgent_burst_bw = 0 >+}; > >+struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; > > #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL > #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f >@@ -314,7 +426,7 @@ > DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) > }; > >-static const struct dce_aduio_mask audio_mask = { >+static const struct dce_audio_mask audio_mask = { > DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) > }; > >@@ -695,6 +807,16 @@ > .fp16 = 1 > } > }; >+static const struct resource_caps res_cap_nv14 = { >+ .num_timing_generator = 5, >+ .num_opp = 5, >+ .num_video_plane = 5, >+ .num_audio = 6, >+ .num_stream_encoder = 5, >+ .num_pll = 5, >+ .num_dwb = 0, >+ .num_ddc = 5, >+}; > > static const struct dc_debug_options debug_defaults_drv = { > .disable_dmcu = true, >@@ -1197,7 +1319,11 @@ > struct pixel_clk_params *pixel_clk_params) > { > const struct dc_stream_state *stream = pipe_ctx->stream; >- bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL; >+ struct pipe_ctx *odm_pipe; >+ int opp_cnt = 1; >+ >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) >+ opp_cnt++; > > pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; > pixel_clk_params->encoder_object_id = stream->link->link_enc->id; >@@ -1215,7 +1341,9 @@ > if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) > pixel_clk_params->color_depth = COLOR_DEPTH_888; > >- if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine) >+ if (opp_cnt == 4) >+ pixel_clk_params->requested_pix_clk_100hz /= 4; >+ else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) > pixel_clk_params->requested_pix_clk_100hz /= 2; > > if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) >@@ -1359,22 +1487,16 @@ > for (i = 0; i < MAX_PIPES; i++) { > if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { > pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; >- break; >+ >+ if (pipe_ctx->stream_res.dsc) >+ release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); > } > } > > if (!pipe_ctx) > return DC_ERROR_UNEXPECTED; >- >- if (pipe_ctx->stream_res.dsc) { >- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); >- >- release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); >- if (odm_pipe) >- release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); >- } >- >- return DC_OK; >+ else >+ return DC_OK; > } > #endif > >@@ -1473,17 +1595,92 @@ > } > } > >-static bool dcn20_split_stream_for_combine( >+static bool dcn20_split_stream_for_odm( >+ struct resource_context *res_ctx, >+ const struct resource_pool *pool, >+ struct pipe_ctx *prev_odm_pipe, >+ struct pipe_ctx *next_odm_pipe) >+{ >+ int pipe_idx = next_odm_pipe->pipe_idx; >+ >+ *next_odm_pipe = *prev_odm_pipe; >+ >+ next_odm_pipe->pipe_idx = pipe_idx; >+ next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; >+ next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; >+ next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; >+ next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; >+ next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; >+ next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ next_odm_pipe->stream_res.dsc = NULL; >+#endif >+ if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { >+ ASSERT(!next_odm_pipe->next_odm_pipe); >+ next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; >+ next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; >+ } >+ prev_odm_pipe->next_odm_pipe = next_odm_pipe; >+ next_odm_pipe->prev_odm_pipe = prev_odm_pipe; >+ ASSERT(next_odm_pipe->top_pipe == NULL); >+ >+ if (prev_odm_pipe->plane_state) { >+ struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; >+ int new_width; >+ >+ /* HACTIVE halved for odm combine */ >+ sd->h_active /= 2; >+ /* Calculate new vp and recout for left pipe */ >+ /* Need at least 16 pixels width per side */ >+ if (sd->recout.x + 16 >= sd->h_active) >+ return false; >+ new_width = sd->h_active - sd->recout.x; >+ sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( >+ sd->ratios.horz, sd->recout.width - new_width)); >+ sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( >+ sd->ratios.horz_c, sd->recout.width - new_width)); >+ sd->recout.width = new_width; >+ >+ /* Calculate new vp and recout for right pipe */ >+ sd = &next_odm_pipe->plane_res.scl_data; >+ /* HACTIVE halved for odm combine */ >+ sd->h_active /= 2; >+ /* Need at least 16 pixels width per side */ >+ if (new_width <= 16) >+ return false; >+ new_width = sd->recout.width + sd->recout.x - sd->h_active; >+ sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( >+ sd->ratios.horz, sd->recout.width - new_width)); >+ sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( >+ sd->ratios.horz_c, sd->recout.width - new_width)); >+ sd->recout.width = new_width; >+ sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( >+ sd->ratios.horz, sd->h_active - sd->recout.x)); >+ sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( >+ sd->ratios.horz_c, sd->h_active - sd->recout.x)); >+ sd->recout.x = 0; >+ } >+ next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ if (next_odm_pipe->stream->timing.flags.DSC == 1) { >+ acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc); >+ ASSERT(next_odm_pipe->stream_res.dsc); >+ if (next_odm_pipe->stream_res.dsc == NULL) >+ return false; >+ } >+#endif >+ >+ return true; >+} >+ >+static void dcn20_split_stream_for_mpc( > struct resource_context *res_ctx, > const struct resource_pool *pool, > struct pipe_ctx *primary_pipe, >- struct pipe_ctx *secondary_pipe, >- bool is_odm_combine) >+ struct pipe_ctx *secondary_pipe) > { > int pipe_idx = secondary_pipe->pipe_idx; >- struct scaler_data *sd = &primary_pipe->plane_res.scl_data; > struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; >- int new_width; > > *secondary_pipe = *primary_pipe; > secondary_pipe->bottom_pipe = sec_bot_pipe; >@@ -1506,57 +1703,9 @@ > primary_pipe->bottom_pipe = secondary_pipe; > secondary_pipe->top_pipe = primary_pipe; > >- if (is_odm_combine) { >- if (primary_pipe->plane_state) { >- /* HACTIVE halved for odm combine */ >- sd->h_active /= 2; >- /* Copy scl_data to secondary pipe */ >- secondary_pipe->plane_res.scl_data = *sd; >- >- /* Calculate new vp and recout for left pipe */ >- /* Need at least 16 pixels width per side */ >- if (sd->recout.x + 16 >= sd->h_active) >- return false; >- new_width = sd->h_active - sd->recout.x; >- sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( >- sd->ratios.horz, sd->recout.width - new_width)); >- sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( >- sd->ratios.horz_c, sd->recout.width - new_width)); >- sd->recout.width = new_width; >- >- /* Calculate new vp and recout for right pipe */ >- sd = &secondary_pipe->plane_res.scl_data; >- new_width = sd->recout.width + sd->recout.x - sd->h_active; >- /* Need at least 16 pixels width per side */ >- if (new_width <= 16) >- return false; >- sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( >- sd->ratios.horz, sd->recout.width - new_width)); >- sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( >- sd->ratios.horz_c, sd->recout.width - new_width)); >- sd->recout.width = new_width; >- sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( >- sd->ratios.horz, sd->h_active - sd->recout.x)); >- sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( >- sd->ratios.horz_c, sd->h_active - sd->recout.x)); >- sd->recout.x = 0; >- } >- secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx]; >-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- if (secondary_pipe->stream->timing.flags.DSC == 1) { >- acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc); >- ASSERT(secondary_pipe->stream_res.dsc); >- if (secondary_pipe->stream_res.dsc == NULL) >- return false; >- } >-#endif >- } else { >- ASSERT(primary_pipe->plane_state); >- resource_build_scaling_params(primary_pipe); >- resource_build_scaling_params(secondary_pipe); >- } >- >- return true; >+ ASSERT(primary_pipe->plane_state); >+ resource_build_scaling_params(primary_pipe); >+ resource_build_scaling_params(secondary_pipe); > } > > void dcn20_populate_dml_writeback_from_context( >@@ -1669,6 +1818,19 @@ > pipes[pipe_cnt].dout.dp_lanes = 4; > pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; > pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; >+ pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe >+ || res_ctx->pipe_ctx[i].next_odm_pipe; >+ pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; >+ if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state >+ == res_ctx->pipe_ctx[i].plane_state) >+ pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; >+ else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { >+ struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; >+ >+ while (first_pipe->prev_odm_pipe) >+ first_pipe = first_pipe->prev_odm_pipe; >+ pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; >+ } > > switch (res_ctx->pipe_ctx[i].stream->signal) { > case SIGNAL_TYPE_DISPLAY_PORT_MST: >@@ -1721,7 +1883,6 @@ > break; > } > >- > switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { > case PIXEL_ENCODING_RGB: > case PIXEL_ENCODING_YCBCR444: >@@ -1743,10 +1904,6 @@ > pipes[pipe_cnt].dout.output_format = dm_444; > pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; > } >- pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; >- if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state >- == res_ctx->pipe_ctx[i].plane_state) >- pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; > > /* todo: default max for now, until there is logic reflecting this in dc*/ > pipes[pipe_cnt].dout.output_bpc = 12; >@@ -1795,14 +1952,6 @@ > && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) > || (res_ctx->pipe_ctx[i].top_pipe > && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln); >- pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe >- && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln >- && res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp >- != res_ctx->pipe_ctx[i].stream_res.opp) >- || (res_ctx->pipe_ctx[i].top_pipe >- && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln >- && res_ctx->pipe_ctx[i].top_pipe->stream_res.opp >- != res_ctx->pipe_ctx[i].stream_res.opp); > pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 > || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; > pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; >@@ -1812,13 +1961,13 @@ > pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; > pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; > if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { >- pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch; >- pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch; >- pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l; >- pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c; >+ pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; >+ pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; >+ pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; >+ pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; > } else { >- pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch; >- pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch; >+ pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; >+ pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; > } > pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; > pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; >@@ -1986,20 +2135,24 @@ > struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; > struct dc_stream_state *stream = pipe_ctx->stream; > struct dsc_config dsc_cfg; >+ struct pipe_ctx *odm_pipe; >+ int opp_cnt = 1; >+ >+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) >+ opp_cnt++; > > /* Only need to validate top pipe */ >- if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC) >+ if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) > continue; > >- dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left >- + stream->timing.h_border_right; >+ dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left >+ + stream->timing.h_border_right) / opp_cnt; > dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top > + stream->timing.v_border_bottom; >- if (dc_res_get_odm_bottom_pipe(pipe_ctx)) >- dsc_cfg.pic_width /= 2; > dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; > dsc_cfg.color_depth = stream->timing.display_color_depth; > dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; >+ dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; > > if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) > return false; >@@ -2008,15 +2161,93 @@ > } > #endif > >-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, >- bool fast_validate) >+static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, >+ struct resource_context *res_ctx, >+ const struct resource_pool *pool, >+ const struct pipe_ctx *primary_pipe) > { >- bool out = false; >+ struct pipe_ctx *secondary_pipe = NULL; > >- BW_VAL_TRACE_SETUP(); >+ if (dc && primary_pipe) { >+ int j; >+ int preferred_pipe_idx = 0; >+ >+ /* first check the prev dc state: >+ * if this primary pipe has a bottom pipe in prev. state >+ * and if the bottom pipe is still available (which it should be), >+ * pick that pipe as secondary >+ * Same logic applies for ODM pipes. Since mpo is not allowed with odm >+ * check in else case. >+ */ >+ if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { >+ preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; >+ if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { >+ secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; >+ secondary_pipe->pipe_idx = preferred_pipe_idx; >+ } >+ } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { >+ preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; >+ if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { >+ secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; >+ secondary_pipe->pipe_idx = preferred_pipe_idx; >+ } >+ } >+ >+ /* >+ * if this primary pipe does not have a bottom pipe in prev. state >+ * start backward and find a pipe that did not used to be a bottom pipe in >+ * prev. dc state. This way we make sure we keep the same assignment as >+ * last state and will not have to reprogram every pipe >+ */ >+ if (secondary_pipe == NULL) { >+ for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { >+ if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) { >+ preferred_pipe_idx = j; >+ >+ if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { >+ secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; >+ secondary_pipe->pipe_idx = preferred_pipe_idx; >+ break; >+ } >+ } >+ } >+ } >+ /* >+ * We should never hit this assert unless assignments are shuffled around >+ * if this happens we will prob. hit a vsync tdr >+ */ >+ ASSERT(secondary_pipe); >+ /* >+ * search backwards for the second pipe to keep pipe >+ * assignment more consistent >+ */ >+ if (secondary_pipe == NULL) { >+ for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { >+ preferred_pipe_idx = j; >+ >+ if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { >+ secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; >+ secondary_pipe->pipe_idx = preferred_pipe_idx; >+ break; >+ } >+ } >+ } >+ } >+ >+ return secondary_pipe; >+} >+ >+bool dcn20_fast_validate_bw( >+ struct dc *dc, >+ struct dc_state *context, >+ display_e2e_pipe_params_st *pipes, >+ int *pipe_cnt_out, >+ int *pipe_split_from, >+ int *vlevel_out) >+{ >+ bool out = false; > > int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit; >- int pipe_split_from[MAX_PIPES]; > bool odm_capable = context->bw_ctx.dml.ip.odm_capable; > bool force_split = false; > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >@@ -2024,15 +2255,44 @@ > #endif > int split_threshold = dc->res_pool->pipe_count / 2; > bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC; >- display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); >- DC_LOGGER_INIT(dc->ctx->logger); > >- BW_VAL_TRACE_COUNT(); > > ASSERT(pipes); > if (!pipes) > return false; > >+ /* merge previously split odm pipes since mode support needs to make the decision */ >+ for (i = 0; i < dc->res_pool->pipe_count; i++) { >+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; >+ struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; >+ >+ if (pipe->prev_odm_pipe) >+ continue; >+ >+ pipe->next_odm_pipe = NULL; >+ while (odm_pipe) { >+ struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; >+ >+ odm_pipe->plane_state = NULL; >+ odm_pipe->stream = NULL; >+ odm_pipe->top_pipe = NULL; >+ odm_pipe->bottom_pipe = NULL; >+ odm_pipe->prev_odm_pipe = NULL; >+ odm_pipe->next_odm_pipe = NULL; >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ if (odm_pipe->stream_res.dsc) >+ release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); >+#endif >+ /* Clear plane_res and stream_res */ >+ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); >+ memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); >+ odm_pipe = next_odm_pipe; >+ } >+ if (pipe->plane_state) >+ resource_build_scaling_params(pipe); >+ } >+ >+ /* merge previously mpc split pipes since mode support needs to make the decision */ > for (i = 0; i < dc->res_pool->pipe_count; i++) { > struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; > struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; >@@ -2040,7 +2300,6 @@ > if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) > continue; > >- /* merge previously split pipe since mode support needs to make the decision */ > pipe->bottom_pipe = hsplit_pipe->bottom_pipe; > if (hsplit_pipe->bottom_pipe) > hsplit_pipe->bottom_pipe->top_pipe = pipe; >@@ -2048,10 +2307,7 @@ > hsplit_pipe->stream = NULL; > hsplit_pipe->top_pipe = NULL; > hsplit_pipe->bottom_pipe = NULL; >-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc) >- release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc); >-#endif >+ > /* Clear plane_res and stream_res */ > memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); > memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); >@@ -2066,8 +2322,9 @@ > pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, > &context->res_ctx, pipes); > >+ *pipe_cnt_out = pipe_cnt; >+ > if (!pipe_cnt) { >- BW_VAL_TRACE_SKIP(pass); > out = true; > goto validate_out; > } >@@ -2160,17 +2417,12 @@ > } > if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) > context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; >- if (dc->config.forced_clocks == true) { >- context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] = >- context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; >- } > if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { >- hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe); >+ hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); > ASSERT(hsplit_pipe); >- if (!dcn20_split_stream_for_combine( >+ if (!dcn20_split_stream_for_odm( > &context->res_ctx, dc->res_pool, >- pipe, hsplit_pipe, >- true)) >+ pipe, hsplit_pipe)) > goto validate_fail; > pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; > dcn20_build_mapped_resource(dc, context, pipe->stream); >@@ -2206,16 +2458,20 @@ > if (need_split3d || need_split || force_split) { > if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { > /* pipe not split previously needs split */ >- hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe); >+ hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); > ASSERT(hsplit_pipe || force_split); > if (!hsplit_pipe) > continue; > >- if (!dcn20_split_stream_for_combine( >+ if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { >+ if (!dcn20_split_stream_for_odm( >+ &context->res_ctx, dc->res_pool, >+ pipe, hsplit_pipe)) >+ goto validate_fail; >+ } else >+ dcn20_split_stream_for_mpc( > &context->res_ctx, dc->res_pool, >- pipe, hsplit_pipe, >- context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])) >- goto validate_fail; >+ pipe, hsplit_pipe); > pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; > } > } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { >@@ -2232,13 +2488,26 @@ > } > #endif > >- BW_VAL_TRACE_END_VOLTAGE_LEVEL(); >+ *vlevel_out = vlevel; > >- if (fast_validate) { >- BW_VAL_TRACE_SKIP(fast); >- out = true; >- goto validate_out; >- } >+ out = true; >+ goto validate_out; >+ >+validate_fail: >+ out = false; >+ >+validate_out: >+ return out; >+} >+ >+void dcn20_calculate_wm( >+ struct dc *dc, struct dc_state *context, >+ display_e2e_pipe_params_st *pipes, >+ int *out_pipe_cnt, >+ int *pipe_split_from, >+ int vlevel) >+{ >+ int pipe_cnt, i, pipe_idx; > > for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { > if (!context->res_ctx.pipe_ctx[i].stream) >@@ -2265,10 +2534,16 @@ > else > pipes[pipe_cnt].pipe.dest.odm_combine = 0; > } >+ > if (dc->config.forced_clocks) { > pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; > pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; > } >+ if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) >+ pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; >+ if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) >+ pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; >+ > pipe_cnt++; > } > >@@ -2281,6 +2556,8 @@ > &context->res_ctx, pipes); > } > >+ *out_pipe_cnt = pipe_cnt; >+ > pipes[0].clks_cfg.voltage = vlevel; > pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; > pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; >@@ -2327,6 +2604,17 @@ > context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; > context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; > context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; >+} >+ >+void dcn20_calculate_dlg_params( >+ struct dc *dc, struct dc_state *context, >+ display_e2e_pipe_params_st *pipes, >+ int pipe_cnt, >+ int vlevel) >+{ >+ int i, j, pipe_idx, pipe_idx_unsplit; >+ bool visited[MAX_PIPES] = { 0 }; >+ > /* Writeback MCIF_WB arbitration parameters */ > dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); > >@@ -2335,32 +2623,69 @@ > context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; > context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; > context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; >- context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; >+ context->bw_ctx.bw.dcn.clk.fclk_khz = 0; > context->bw_ctx.bw.dcn.clk.p_state_change_support = > context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] > != dm_dram_clock_change_unsupported; > context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; > >- BW_VAL_TRACE_END_WATERMARKS(); >+ /* >+ * An artifact of dml pipe split/odm is that pipes get merged back together for >+ * calculation. Therefore we need to only extract for first pipe in ascending index order >+ * and copy into the other split half. >+ */ >+ for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) { >+ if (!context->res_ctx.pipe_ctx[i].stream) >+ continue; >+ >+ if (!visited[pipe_idx]) { >+ display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src; >+ display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest; >+ >+ dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; >+ dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; >+ dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; >+ dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; >+ /* >+ * j iterates inside pipes array, unlike i which iterates inside >+ * pipe_ctx array >+ */ >+ if (src->is_hsplit) >+ for (j = pipe_idx + 1; j < pipe_cnt; j++) { >+ display_pipe_source_params_st *src_j = &pipes[j].pipe.src; >+ display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest; >+ >+ if (src_j->is_hsplit && !visited[j] >+ && src->hsplit_grp == src_j->hsplit_grp) { >+ dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; >+ dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; >+ dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; >+ dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; >+ visited[j] = true; >+ } >+ } >+ visited[pipe_idx] = true; >+ pipe_idx_unsplit++; >+ } >+ pipe_idx++; >+ } > > for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { > if (!context->res_ctx.pipe_ctx[i].stream) > continue; >- pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx]; >- pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx]; >- pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx]; >- pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx]; > if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) > context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; > context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; >-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz = >- context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000; >-#endif >+ ASSERT(visited[pipe_idx]); > context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; > pipe_idx++; > } >+ /*save a original dppclock copy*/ >+ context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; >+ context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; >+ context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; >+ context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; > > for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { > bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; >@@ -2383,8 +2708,43 @@ > pipes[pipe_idx].pipe); > pipe_idx++; > } >+} >+ >+static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, >+ bool fast_validate) >+{ >+ bool out = false; >+ >+ BW_VAL_TRACE_SETUP(); >+ >+ int vlevel = 0; >+ int pipe_split_from[MAX_PIPES]; >+ int pipe_cnt = 0; >+ display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); >+ DC_LOGGER_INIT(dc->ctx->logger); >+ >+ BW_VAL_TRACE_COUNT(); >+ >+ out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); >+ >+ if (pipe_cnt == 0) >+ goto validate_out; >+ >+ if (!out) >+ goto validate_fail; >+ >+ BW_VAL_TRACE_END_VOLTAGE_LEVEL(); >+ >+ if (fast_validate) { >+ BW_VAL_TRACE_SKIP(fast); >+ goto validate_out; >+ } >+ >+ dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); >+ dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); >+ >+ BW_VAL_TRACE_END_WATERMARKS(); > >- out = true; > goto validate_out; > > validate_fail: >@@ -2402,6 +2762,50 @@ > return out; > } > >+ >+bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, >+ bool fast_validate) >+{ >+ bool voltage_supported = false; >+ bool full_pstate_supported = false; >+ bool dummy_pstate_supported = false; >+ double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; >+ >+ if (fast_validate) >+ return dcn20_validate_bandwidth_internal(dc, context, true); >+ >+ >+ // Best case, we support full UCLK switch latency >+ voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); >+ full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; >+ >+ if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || >+ (voltage_supported && full_pstate_supported)) { >+ context->bw_ctx.bw.dcn.clk.p_state_change_support = true; >+ goto restore_dml_state; >+ } >+ >+ // Fallback: Try to only support G6 temperature read latency >+ context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; >+ >+ voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); >+ dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; >+ >+ if (voltage_supported && dummy_pstate_supported) { >+ context->bw_ctx.bw.dcn.clk.p_state_change_support = false; >+ goto restore_dml_state; >+ } >+ >+ // ERROR: fallback is supposed to always work. >+ ASSERT(false); >+ >+restore_dml_state: >+ memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); >+ context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; >+ >+ return voltage_supported; >+} >+ > struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( > struct dc_state *state, > const struct resource_pool *pool, >@@ -2576,9 +2980,6 @@ > && max_clocks.uClockInKhz != 0) > bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; > >- // HACK: Force every uclk to max for now to "disable" uclk switching. >- bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; >- > if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) > && max_clocks.fabricClockInKhz != 0) > bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); >@@ -2674,6 +3075,10 @@ > num_calculated_states++; > } > >+ calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; >+ calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; >+ calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; >+ > memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); > bb->num_states = num_calculated_states; > >@@ -2711,6 +3116,27 @@ > kernel_fpu_end(); > } > >+static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( >+ uint32_t hw_internal_rev) >+{ >+ if (ASICREV_IS_NAVI12_P(hw_internal_rev)) >+ return &dcn2_0_nv12_soc; >+ >+ return &dcn2_0_soc; >+} >+ >+static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( >+ uint32_t hw_internal_rev) >+{ >+ /* NV12 and NV10 */ >+ return &dcn2_0_ip; >+} >+ >+static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) >+{ >+ return DML_PROJECT_NAVI10v2; >+} >+ > #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) > #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) > >@@ -2718,6 +3144,11 @@ > struct dcn20_resource_pool *pool) > { > const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; >+ struct _vcs_dpi_soc_bounding_box_st *loaded_bb = >+ get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); >+ struct _vcs_dpi_ip_params_st *loaded_ip = >+ get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); >+ > DC_LOGGER_INIT(dc->ctx->logger); > > if (!bb && !SOC_BOUNDING_BOX_VALID) { >@@ -2728,103 +3159,103 @@ > if (bb && !SOC_BOUNDING_BOX_VALID) { > int i; > >- dcn2_0_soc.sr_exit_time_us = >+ dcn2_0_nv12_soc.sr_exit_time_us = > fixed16_to_double_to_cpu(bb->sr_exit_time_us); >- dcn2_0_soc.sr_enter_plus_exit_time_us = >+ dcn2_0_nv12_soc.sr_enter_plus_exit_time_us = > fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); >- dcn2_0_soc.urgent_latency_us = >+ dcn2_0_nv12_soc.urgent_latency_us = > fixed16_to_double_to_cpu(bb->urgent_latency_us); >- dcn2_0_soc.urgent_latency_pixel_data_only_us = >+ dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us = > fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); >- dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us = >+ dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us = > fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); >- dcn2_0_soc.urgent_latency_vm_data_only_us = >+ dcn2_0_nv12_soc.urgent_latency_vm_data_only_us = > fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); >- dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = >+ dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = > le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); >- dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = >+ dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = > le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); >- dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = >+ dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = > le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); >- dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = >+ dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = > fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); >- dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = >+ dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = > fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); >- dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = >+ dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = > fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); >- dcn2_0_soc.max_avg_sdp_bw_use_normal_percent = >+ dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent = > fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); >- dcn2_0_soc.max_avg_dram_bw_use_normal_percent = >+ dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent = > fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); >- dcn2_0_soc.writeback_latency_us = >+ dcn2_0_nv12_soc.writeback_latency_us = > fixed16_to_double_to_cpu(bb->writeback_latency_us); >- dcn2_0_soc.ideal_dram_bw_after_urgent_percent = >+ dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent = > fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); >- dcn2_0_soc.max_request_size_bytes = >+ dcn2_0_nv12_soc.max_request_size_bytes = > le32_to_cpu(bb->max_request_size_bytes); >- dcn2_0_soc.dram_channel_width_bytes = >+ dcn2_0_nv12_soc.dram_channel_width_bytes = > le32_to_cpu(bb->dram_channel_width_bytes); >- dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes = >+ dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes = > le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); >- dcn2_0_soc.dcn_downspread_percent = >+ dcn2_0_nv12_soc.dcn_downspread_percent = > fixed16_to_double_to_cpu(bb->dcn_downspread_percent); >- dcn2_0_soc.downspread_percent = >+ dcn2_0_nv12_soc.downspread_percent = > fixed16_to_double_to_cpu(bb->downspread_percent); >- dcn2_0_soc.dram_page_open_time_ns = >+ dcn2_0_nv12_soc.dram_page_open_time_ns = > fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); >- dcn2_0_soc.dram_rw_turnaround_time_ns = >+ dcn2_0_nv12_soc.dram_rw_turnaround_time_ns = > fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); >- dcn2_0_soc.dram_return_buffer_per_channel_bytes = >+ dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes = > le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); >- dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles = >+ dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles = > le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); >- dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes = >+ dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes = > le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); >- dcn2_0_soc.channel_interleave_bytes = >+ dcn2_0_nv12_soc.channel_interleave_bytes = > le32_to_cpu(bb->channel_interleave_bytes); >- dcn2_0_soc.num_banks = >+ dcn2_0_nv12_soc.num_banks = > le32_to_cpu(bb->num_banks); >- dcn2_0_soc.num_chans = >+ dcn2_0_nv12_soc.num_chans = > le32_to_cpu(bb->num_chans); >- dcn2_0_soc.vmm_page_size_bytes = >+ dcn2_0_nv12_soc.vmm_page_size_bytes = > le32_to_cpu(bb->vmm_page_size_bytes); >- dcn2_0_soc.dram_clock_change_latency_us = >+ dcn2_0_nv12_soc.dram_clock_change_latency_us = > fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); > // HACK!! Lower uclock latency switch time so we don't switch >- dcn2_0_soc.dram_clock_change_latency_us = 10; >- dcn2_0_soc.writeback_dram_clock_change_latency_us = >+ dcn2_0_nv12_soc.dram_clock_change_latency_us = 10; >+ dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us = > fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); >- dcn2_0_soc.return_bus_width_bytes = >+ dcn2_0_nv12_soc.return_bus_width_bytes = > le32_to_cpu(bb->return_bus_width_bytes); >- dcn2_0_soc.dispclk_dppclk_vco_speed_mhz = >+ dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz = > le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); >- dcn2_0_soc.xfc_bus_transport_time_us = >+ dcn2_0_nv12_soc.xfc_bus_transport_time_us = > le32_to_cpu(bb->xfc_bus_transport_time_us); >- dcn2_0_soc.xfc_xbuf_latency_tolerance_us = >+ dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us = > le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); >- dcn2_0_soc.use_urgent_burst_bw = >+ dcn2_0_nv12_soc.use_urgent_burst_bw = > le32_to_cpu(bb->use_urgent_burst_bw); >- dcn2_0_soc.num_states = >+ dcn2_0_nv12_soc.num_states = > le32_to_cpu(bb->num_states); > >- for (i = 0; i < dcn2_0_soc.num_states; i++) { >- dcn2_0_soc.clock_limits[i].state = >+ for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) { >+ dcn2_0_nv12_soc.clock_limits[i].state = > le32_to_cpu(bb->clock_limits[i].state); >- dcn2_0_soc.clock_limits[i].dcfclk_mhz = >+ dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz = > fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); >- dcn2_0_soc.clock_limits[i].fabricclk_mhz = >+ dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz = > fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); >- dcn2_0_soc.clock_limits[i].dispclk_mhz = >+ dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz = > fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); >- dcn2_0_soc.clock_limits[i].dppclk_mhz = >+ dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz = > fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); >- dcn2_0_soc.clock_limits[i].phyclk_mhz = >+ dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz = > fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); >- dcn2_0_soc.clock_limits[i].socclk_mhz = >+ dcn2_0_nv12_soc.clock_limits[i].socclk_mhz = > fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); >- dcn2_0_soc.clock_limits[i].dscclk_mhz = >+ dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz = > fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); >- dcn2_0_soc.clock_limits[i].dram_speed_mts = >+ dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts = > fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); > } > } >@@ -2833,7 +3264,6 @@ > struct pp_smu_nv_clock_table max_clocks = {0}; > unsigned int uclk_states[8] = {0}; > unsigned int num_states = 0; >- int i; > enum pp_smu_status status; > bool clock_limits_available = false; > bool uclk_states_available = false; >@@ -2855,19 +3285,15 @@ > clock_limits_available = (status == PP_SMU_RESULT_OK); > } > >- // HACK: Use the max uclk_states value for all elements. >- for (i = 0; i < num_states; i++) >- uclk_states[i] = uclk_states[num_states - 1]; >- > if (clock_limits_available && uclk_states_available && num_states) >- update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states); >+ update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); > else if (clock_limits_available) >- cap_soc_clocks(&dcn2_0_soc, max_clocks); >+ cap_soc_clocks(loaded_bb, max_clocks); > } > >- dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator; >- dcn2_0_ip.max_num_dpp = pool->base.pipe_count; >- patch_bounding_box(dc, &dcn2_0_soc); >+ loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; >+ loaded_ip->max_num_dpp = pool->base.pipe_count; >+ patch_bounding_box(dc, loaded_bb); > > return true; > } >@@ -2880,19 +3306,30 @@ > int i; > struct dc_context *ctx = dc->ctx; > struct irq_service_init_data init_data; >+ struct _vcs_dpi_soc_bounding_box_st *loaded_bb = >+ get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); >+ struct _vcs_dpi_ip_params_st *loaded_ip = >+ get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); >+ enum dml_project dml_project_version = >+ get_dml_project_version(ctx->asic_id.hw_internal_rev); > > ctx->dc_bios->regs = &bios_regs; >- >- pool->base.res_cap = &res_cap_nv10; > pool->base.funcs = &dcn20_res_pool_funcs; > >+ if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { >+ pool->base.res_cap = &res_cap_nv14; >+ pool->base.pipe_count = 5; >+ pool->base.mpcc_count = 5; >+ } else { >+ pool->base.res_cap = &res_cap_nv10; >+ pool->base.pipe_count = 6; >+ pool->base.mpcc_count = 6; >+ } > /************************************************* > * Resource + asic cap harcoding * > *************************************************/ > pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; > >- pool->base.pipe_count = 6; >- pool->base.mpcc_count = 6; > dc->caps.max_downscale_ratio = 200; > dc->caps.i2c_speed_in_khz = 100; > dc->caps.max_cursor_size = 256; >@@ -2998,7 +3435,7 @@ > goto create_fail; > } > >- dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10); >+ dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); > > if (!dc->debug.disable_pplib_wm_range) { > struct pp_smu_wm_range_sets ranges = {0}; >@@ -3006,7 +3443,7 @@ > > ranges.num_reader_wm_sets = 0; > >- if (dcn2_0_soc.num_states == 1) { >+ if (loaded_bb->num_states == 1) { > ranges.reader_wm_sets[0].wm_inst = i; > ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; > ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >@@ -3014,13 +3451,13 @@ > ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; > > ranges.num_reader_wm_sets = 1; >- } else if (dcn2_0_soc.num_states > 1) { >- for (i = 0; i < 4 && i < dcn2_0_soc.num_states; i++) { >+ } else if (loaded_bb->num_states > 1) { >+ for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { > ranges.reader_wm_sets[i].wm_inst = i; > ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; > ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; >- ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (dcn2_0_soc.clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; >- ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16; >+ ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; >+ ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; > > ranges.num_reader_wm_sets = i + 1; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 2019-08-31 15:01:11.866736169 -0500 >@@ -116,6 +116,18 @@ > display_e2e_pipe_params_st *pipes, > int pipe_cnt); > bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate); >+bool dcn20_fast_validate_bw( >+ struct dc *dc, >+ struct dc_state *context, >+ display_e2e_pipe_params_st *pipes, >+ int *pipe_cnt_out, >+ int *pipe_split_from, >+ int *vlevel_out); >+void dcn20_calculate_dlg_params( >+ struct dc *dc, struct dc_state *context, >+ display_e2e_pipe_params_st *pipes, >+ int pipe_cnt, >+ int vlevel); > > enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream); > enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 2019-08-31 15:01:11.866736169 -0500 >@@ -207,9 +207,8 @@ > > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > >- > /* Update GSP7 SDP 128 byte long */ >-static void enc2_send_gsp7_128_info_packet( >+static void enc2_update_gsp7_128_info_packet( > struct dcn10_stream_encoder *enc1, > const struct dc_info_packet_128 *info_packet) > { >@@ -277,18 +276,9 @@ > static void enc2_dp_set_dsc_config(struct stream_encoder *enc, > enum optc_dsc_mode dsc_mode, > uint32_t dsc_bytes_per_pixel, >- uint32_t dsc_slice_width, >- uint8_t *dsc_packed_pps) >+ uint32_t dsc_slice_width) > { > struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); >- uint32_t dsc_value = 0; >- >- dsc_value = REG_READ(DP_DSC_CNTL); >- >- /* dsc disable skip */ >- if ((dsc_value & 0x3) == 0x0) >- return; >- > > REG_UPDATE_2(DP_DSC_CNTL, > DP_DSC_MODE, dsc_mode, >@@ -296,8 +286,16 @@ > > REG_SET(DP_DSC_BYTES_PER_PIXEL, 0, > DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); >+} >+ > >- if (dsc_mode != OPTC_DSC_DISABLED) { >+static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, >+ bool enable, >+ uint8_t *dsc_packed_pps) >+{ >+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); >+ >+ if (enable) { > struct dc_info_packet_128 pps_sdp; > > ASSERT(dsc_packed_pps); >@@ -309,7 +307,7 @@ > pps_sdp.hb2 = 127; > pps_sdp.hb3 = 0; > memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb)); >- enc2_send_gsp7_128_info_packet(enc1, &pps_sdp); >+ enc2_update_gsp7_128_info_packet(enc1, &pps_sdp); > > /* Enable Generic Stream Packet 7 (GSP) transmission */ > //REG_UPDATE(DP_SEC_CNTL, >@@ -340,9 +338,8 @@ > REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0); > } > } >-#endif > >-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ > /* this function read dsc related register fields to be logged later in dcn10_log_hw_state > * into a dcn_dsc_state struct. > */ >@@ -373,7 +370,7 @@ > * > * Ensure the OTG master update lock is set when changing DME configuration. > */ >-static void enc2_set_dynamic_metadata(struct stream_encoder *enc, >+void enc2_set_dynamic_metadata(struct stream_encoder *enc, > bool enable_dme, > uint32_t hubp_requestor_id, > enum dynamic_metadata_mode dmdata_mode) >@@ -463,7 +460,7 @@ > uint64_t m_vid_l = n_vid; > > /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ >- if (is_two_pixels_per_containter(¶m->timing) || param->odm) { >+ if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { > /*this logic should be the same in get_pixel_clock_parameters() */ > n_multiply = 1; > } >@@ -580,14 +577,14 @@ > .setup_stereo_sync = enc1_setup_stereo_sync, > .set_avmute = enc1_stream_encoder_set_avmute, > .dig_connect_to_otg = enc1_dig_connect_to_otg, >+ .dig_source_otg = enc1_dig_source_otg, > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > .enc_read_state = enc2_read_state, >-#endif >- >-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > .dp_set_dsc_config = enc2_dp_set_dsc_config, >+ .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, > #endif > .set_dynamic_metadata = enc2_set_dynamic_metadata, >+ .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, > }; > > void dcn20_stream_encoder_construct( >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 2019-08-31 15:01:11.866736169 -0500 >@@ -104,4 +104,9 @@ > struct stream_encoder *enc, > const struct encoder_unblank_param *param); > >+void enc2_set_dynamic_metadata(struct stream_encoder *enc, >+ bool enable_dme, >+ uint32_t hubp_requestor_id, >+ enum dynamic_metadata_mode dmdata_mode); >+ > #endif /* __DC_STREAM_ENCODER_DCN20_H__ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/Makefile 2019-08-31 15:01:11.864736169 -0500 >@@ -18,6 +18,10 @@ > > CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align) > >+ifdef CONFIG_CC_IS_CLANG >+CFLAGS_dcn20_resource.o += -msse2 >+endif >+ > AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20)) > > AMD_DISPLAY_FILES += $(AMD_DAL_DCN20) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 2019-08-31 15:01:11.866736169 -0500 >@@ -0,0 +1,595 @@ >+/* >+* Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+#include "dm_services.h" >+#include "dcn20/dcn20_hubbub.h" >+#include "dcn21_hubbub.h" >+#include "reg_helper.h" >+ >+#define REG(reg)\ >+ hubbub1->regs->reg >+#define DC_LOGGER \ >+ hubbub1->base.ctx->logger >+#define CTX \ >+ hubbub1->base.ctx >+ >+#undef FN >+#define FN(reg_name, field_name) \ >+ hubbub1->shifts->field_name, hubbub1->masks->field_name >+ >+#define REG(reg)\ >+ hubbub1->regs->reg >+ >+#define CTX \ >+ hubbub1->base.ctx >+ >+#undef FN >+#define FN(reg_name, field_name) \ >+ hubbub1->shifts->field_name, hubbub1->masks->field_name >+ >+#ifdef NUM_VMID >+#undef NUM_VMID >+#endif >+#define NUM_VMID 1 >+ >+static uint32_t convert_and_clamp( >+ uint32_t wm_ns, >+ uint32_t refclk_mhz, >+ uint32_t clamp_value) >+{ >+ uint32_t ret_val = 0; >+ ret_val = wm_ns * refclk_mhz; >+ ret_val /= 1000; >+ >+ if (ret_val > clamp_value) >+ ret_val = clamp_value; >+ >+ return ret_val; >+} >+ >+void dcn21_dchvm_init(struct hubbub *hubbub) >+{ >+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); >+ >+ //Init DCHVM block >+ REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1); >+ >+ //Poll until RIOMMU_ACTIVE = 1 >+ //TODO: Figure out interval us and retry count >+ REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100); >+ >+ //Reflect the power status of DCHUBBUB >+ REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1); >+ >+ //Start rIOMMU prefetching >+ REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1); >+ >+ // Enable dynamic clock gating >+ REG_UPDATE_4(DCHVM_CLK_CTRL, >+ HVM_DISPCLK_R_GATE_DIS, 0, >+ HVM_DISPCLK_G_GATE_DIS, 0, >+ HVM_DCFCLK_R_GATE_DIS, 0, >+ HVM_DCFCLK_G_GATE_DIS, 0); >+ >+ //Poll until HOSTVM_PREFETCH_DONE = 1 >+ //TODO: Figure out interval us and retry count >+ REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100); >+} >+ >+static int hubbub21_init_dchub(struct hubbub *hubbub, >+ struct dcn_hubbub_phys_addr_config *pa_config) >+{ >+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); >+ >+ REG_SET(DCN_VM_FB_LOCATION_BASE, 0, >+ FB_BASE, pa_config->system_aperture.fb_base); >+ REG_SET(DCN_VM_FB_LOCATION_TOP, 0, >+ FB_TOP, pa_config->system_aperture.fb_top); >+ REG_SET(DCN_VM_FB_OFFSET, 0, >+ FB_OFFSET, pa_config->system_aperture.fb_offset); >+ REG_SET(DCN_VM_AGP_BOT, 0, >+ AGP_BOT, pa_config->system_aperture.agp_bot); >+ REG_SET(DCN_VM_AGP_TOP, 0, >+ AGP_TOP, pa_config->system_aperture.agp_top); >+ REG_SET(DCN_VM_AGP_BASE, 0, >+ AGP_BASE, pa_config->system_aperture.agp_base); >+ >+ dcn21_dchvm_init(hubbub); >+ >+ return NUM_VMID; >+} >+ >+static void hubbub21_program_urgent_watermarks( >+ struct hubbub *hubbub, >+ struct dcn_watermark_set *watermarks, >+ unsigned int refclk_mhz, >+ bool safe_to_lower) >+{ >+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); >+ uint32_t prog_wm_value; >+ >+ /* Repeat for water mark set A, B, C and D. */ >+ /* clock state A */ >+ if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { >+ hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns; >+ prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, >+ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value); >+ >+ DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->a.urgent_ns, prog_wm_value); >+ } >+ >+ /* determine the transfer time for a quantity of data for a particular requestor.*/ >+ if (safe_to_lower || watermarks->a.frac_urg_bw_flip >+ > hubbub1->watermarks.a.frac_urg_bw_flip) { >+ hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; >+ >+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, >+ DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip); >+ } >+ >+ if (safe_to_lower || watermarks->a.frac_urg_bw_nom >+ > hubbub1->watermarks.a.frac_urg_bw_nom) { >+ hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; >+ >+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, >+ DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom); >+ } >+ >+ /* clock state B */ >+ if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) { >+ hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns; >+ prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, >+ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, prog_wm_value); >+ >+ DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->b.urgent_ns, prog_wm_value); >+ } >+ >+ /* determine the transfer time for a quantity of data for a particular requestor.*/ >+ if (safe_to_lower || watermarks->a.frac_urg_bw_flip >+ > hubbub1->watermarks.a.frac_urg_bw_flip) { >+ hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; >+ >+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, >+ DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->a.frac_urg_bw_flip); >+ } >+ >+ if (safe_to_lower || watermarks->a.frac_urg_bw_nom >+ > hubbub1->watermarks.a.frac_urg_bw_nom) { >+ hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; >+ >+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, >+ DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom); >+ } >+ >+ /* clock state C */ >+ if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) { >+ hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns; >+ prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, >+ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, prog_wm_value); >+ >+ DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->c.urgent_ns, prog_wm_value); >+ } >+ >+ /* determine the transfer time for a quantity of data for a particular requestor.*/ >+ if (safe_to_lower || watermarks->a.frac_urg_bw_flip >+ > hubbub1->watermarks.a.frac_urg_bw_flip) { >+ hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; >+ >+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, >+ DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->a.frac_urg_bw_flip); >+ } >+ >+ if (safe_to_lower || watermarks->a.frac_urg_bw_nom >+ > hubbub1->watermarks.a.frac_urg_bw_nom) { >+ hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; >+ >+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, >+ DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom); >+ } >+ >+ /* clock state D */ >+ if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) { >+ hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns; >+ prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, >+ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, prog_wm_value); >+ >+ DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->d.urgent_ns, prog_wm_value); >+ } >+ >+ /* determine the transfer time for a quantity of data for a particular requestor.*/ >+ if (safe_to_lower || watermarks->a.frac_urg_bw_flip >+ > hubbub1->watermarks.a.frac_urg_bw_flip) { >+ hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; >+ >+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, >+ DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->a.frac_urg_bw_flip); >+ } >+ >+ if (safe_to_lower || watermarks->a.frac_urg_bw_nom >+ > hubbub1->watermarks.a.frac_urg_bw_nom) { >+ hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; >+ >+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, >+ DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom); >+ } >+} >+ >+static void hubbub21_program_stutter_watermarks( >+ struct hubbub *hubbub, >+ struct dcn_watermark_set *watermarks, >+ unsigned int refclk_mhz, >+ bool safe_to_lower) >+{ >+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); >+ uint32_t prog_wm_value; >+ >+ /* clock state A */ >+ if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns >+ > hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) { >+ hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = >+ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, >+ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); >+ } >+ >+ if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns >+ > hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) { >+ hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns = >+ watermarks->a.cstate_pstate.cstate_exit_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->a.cstate_pstate.cstate_exit_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, >+ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); >+ } >+ >+ /* clock state B */ >+ if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns >+ > hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) { >+ hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = >+ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, >+ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); >+ } >+ >+ if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns >+ > hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) { >+ hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns = >+ watermarks->b.cstate_pstate.cstate_exit_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->b.cstate_pstate.cstate_exit_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, >+ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); >+ } >+ >+ /* clock state C */ >+ if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns >+ > hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) { >+ hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = >+ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, >+ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); >+ } >+ >+ if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns >+ > hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) { >+ hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns = >+ watermarks->c.cstate_pstate.cstate_exit_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->c.cstate_pstate.cstate_exit_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, >+ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); >+ } >+ >+ /* clock state D */ >+ if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns >+ > hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) { >+ hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = >+ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, >+ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); >+ } >+ >+ if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns >+ > hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) { >+ hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns = >+ watermarks->d.cstate_pstate.cstate_exit_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->d.cstate_pstate.cstate_exit_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, >+ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n" >+ "HW register value = 0x%x\n", >+ watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); >+ } >+} >+ >+static void hubbub21_program_pstate_watermarks( >+ struct hubbub *hubbub, >+ struct dcn_watermark_set *watermarks, >+ unsigned int refclk_mhz, >+ bool safe_to_lower) >+{ >+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); >+ uint32_t prog_wm_value; >+ >+ /* clock state A */ >+ if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns >+ > hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) { >+ hubbub1->watermarks.a.cstate_pstate.pstate_change_ns = >+ watermarks->a.cstate_pstate.pstate_change_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->a.cstate_pstate.pstate_change_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0, >+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" >+ "HW register value = 0x%x\n\n", >+ watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); >+ } >+ >+ /* clock state B */ >+ if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns >+ > hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) { >+ hubbub1->watermarks.b.cstate_pstate.pstate_change_ns = >+ watermarks->b.cstate_pstate.pstate_change_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->b.cstate_pstate.pstate_change_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0, >+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n" >+ "HW register value = 0x%x\n\n", >+ watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); >+ } >+ >+ /* clock state C */ >+ if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns >+ > hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) { >+ hubbub1->watermarks.c.cstate_pstate.pstate_change_ns = >+ watermarks->c.cstate_pstate.pstate_change_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->c.cstate_pstate.pstate_change_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0, >+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n" >+ "HW register value = 0x%x\n\n", >+ watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); >+ } >+ >+ /* clock state D */ >+ if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns >+ > hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) { >+ hubbub1->watermarks.d.cstate_pstate.pstate_change_ns = >+ watermarks->d.cstate_pstate.pstate_change_ns; >+ prog_wm_value = convert_and_clamp( >+ watermarks->d.cstate_pstate.pstate_change_ns, >+ refclk_mhz, 0x1fffff); >+ REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0, >+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value, >+ DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); >+ DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" >+ "HW register value = 0x%x\n\n", >+ watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); >+ } >+} >+ >+void hubbub21_program_watermarks( >+ struct hubbub *hubbub, >+ struct dcn_watermark_set *watermarks, >+ unsigned int refclk_mhz, >+ bool safe_to_lower) >+{ >+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); >+ >+ hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); >+ hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); >+ hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); >+ >+ /* >+ * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric. >+ * If the memory controller is fully utilized and the DCHub requestors are >+ * well ahead of their amortized schedule, then it is safe to prevent the next winner >+ * from being committed and sent to the fabric. >+ * The utilization of the memory controller is approximated by ensuring that >+ * the number of outstanding requests is greater than a threshold specified >+ * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule, >+ * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles. >+ * >+ * TODO: Revisit request limit after figure out right number. request limit for Renoir isn't decided yet, set maximum value (0x1FF) >+ * to turn off it for now. >+ */ >+ REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, >+ DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); >+ REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND, >+ DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF, >+ DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA); >+ REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, >+ DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF); >+ >+ hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); >+} >+ >+void hubbub21_wm_read_state(struct hubbub *hubbub, >+ struct dcn_hubbub_wm *wm) >+{ >+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); >+ struct dcn_hubbub_wm_set *s; >+ >+ memset(wm, 0, sizeof(struct dcn_hubbub_wm)); >+ >+ s = &wm->sets[0]; >+ s->wm_set = 0; >+ REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, >+ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, >+ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, >+ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, >+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_chanage); >+ >+ s = &wm->sets[1]; >+ s->wm_set = 1; >+ REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, >+ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, >+ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, >+ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, >+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_chanage); >+ >+ s = &wm->sets[2]; >+ s->wm_set = 2; >+ REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, >+ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, >+ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, >+ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, >+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_chanage); >+ >+ s = &wm->sets[3]; >+ s->wm_set = 3; >+ REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, >+ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, >+ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, >+ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit); >+ >+ REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, >+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage); >+} >+ >+ >+static const struct hubbub_funcs hubbub21_funcs = { >+ .update_dchub = hubbub2_update_dchub, >+ .init_dchub_sys_ctx = hubbub21_init_dchub, >+ .init_vm_ctx = NULL, >+ .dcc_support_swizzle = hubbub2_dcc_support_swizzle, >+ .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, >+ .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap, >+ .wm_read_state = hubbub21_wm_read_state, >+ .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq, >+ .program_watermarks = hubbub21_program_watermarks, >+}; >+ >+void hubbub21_construct(struct dcn20_hubbub *hubbub, >+ struct dc_context *ctx, >+ const struct dcn_hubbub_registers *hubbub_regs, >+ const struct dcn_hubbub_shift *hubbub_shift, >+ const struct dcn_hubbub_mask *hubbub_mask) >+{ >+ hubbub->base.ctx = ctx; >+ >+ hubbub->base.funcs = &hubbub21_funcs; >+ >+ hubbub->regs = hubbub_regs; >+ hubbub->shifts = hubbub_shift; >+ hubbub->masks = hubbub_mask; >+ >+ hubbub->debug_test_index_pstate = 0xB; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h 2019-08-31 15:01:11.866736169 -0500 >@@ -0,0 +1,132 @@ >+/* >+* Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+#ifndef DAL_DC_DCN21_DCN21_HUBBUB_H_ >+#define DAL_DC_DCN21_DCN21_HUBBUB_H_ >+ >+#include "dcn20/dcn20_hubbub.h" >+ >+#define HUBBUB_HVM_REG_LIST() \ >+ SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ >+ SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ >+ SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ >+ SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ >+ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ >+ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ >+ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ >+ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ >+ SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ >+ SR(DCHVM_CTRL0), \ >+ SR(DCHVM_MEM_CTRL), \ >+ SR(DCHVM_CLK_CTRL), \ >+ SR(DCHVM_RIOMMU_CTRL0), \ >+ SR(DCHVM_RIOMMU_STAT0) >+ >+#define HUBBUB_REG_LIST_DCN21()\ >+ HUBBUB_REG_LIST_DCN_COMMON(), \ >+ HUBBUB_SR_WATERMARK_REG_LIST(), \ >+ HUBBUB_HVM_REG_LIST(), \ >+ SR(DCHUBBUB_CRC_CTRL), \ >+ SR(DCN_VM_FB_LOCATION_BASE),\ >+ SR(DCN_VM_FB_LOCATION_TOP),\ >+ SR(DCN_VM_FB_OFFSET),\ >+ SR(DCN_VM_AGP_BOT),\ >+ SR(DCN_VM_AGP_TOP),\ >+ SR(DCN_VM_AGP_BASE) >+ >+#define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \ >+ HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \ >+ HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \ >+ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \ >+ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \ >+ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \ >+ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \ >+ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \ >+ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \ >+ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \ >+ HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \ >+ HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \ >+ HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \ >+ HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \ >+ HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \ >+ HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh) >+ >+#define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\ >+ HUBBUB_MASK_SH_LIST_HVM(mask_sh),\ >+ HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ >+ HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ >+ HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ >+ HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ >+ HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ >+ HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ >+ HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ >+ HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ >+ HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh) >+ >+void dcn21_dchvm_init(struct hubbub *hubbub); >+void hubbub21_program_watermarks( >+ struct hubbub *hubbub, >+ struct dcn_watermark_set *watermarks, >+ unsigned int refclk_mhz, >+ bool safe_to_lower); >+ >+void hubbub21_wm_read_state(struct hubbub *hubbub, >+ struct dcn_hubbub_wm *wm); >+ >+void hubbub21_construct(struct dcn20_hubbub *hubbub, >+ struct dc_context *ctx, >+ const struct dcn_hubbub_registers *hubbub_regs, >+ const struct dcn_hubbub_shift *hubbub_shift, >+ const struct dcn_hubbub_mask *hubbub_mask); >+ >+#endif /* DAL_DC_DCN21_DCN21_HUBBUB_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 2019-08-31 15:01:11.866736169 -0500 >@@ -0,0 +1,244 @@ >+/* >+* Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+#include "dcn21_hubp.h" >+ >+#include "dm_services.h" >+#include "reg_helper.h" >+ >+#define REG(reg)\ >+ hubp21->hubp_regs->reg >+ >+#define CTX \ >+ hubp21->base.ctx >+ >+#undef FN >+#define FN(reg_name, field_name) \ >+ hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name >+ >+/* >+ * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. >+ * As a result, if S/W updates any of these registers during a mode change, >+ * the current frame before the mode change will use the new value right away >+ * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. >+ * >+ * REFCYC_PER_VM_GROUP_FLIP[22:0] >+ * REFCYC_PER_VM_GROUP_VBLANK[22:0] >+ * REFCYC_PER_VM_REQ_FLIP[22:0] >+ * REFCYC_PER_VM_REQ_VBLANK[22:0] >+ * >+ * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated >+ * when flipping to a new surface >+ * >+ * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated >+ * during prefetch period of a frame. The prefetch starts at a pre-determined >+ * number of lines before the display active per frame >+ * >+ * DCN may underflow due to incorrectly programming these registers >+ * during VM stage of prefetch/iflip. First lines of display active >+ * or a sub-region of active using a new surface will be corrupted >+ * until the VM data returns at flip/mode change transitions >+ * >+ * Work around: >+ * workaround is always opt to use the more aggressive settings. >+ * On any mode switch, if the new reg values are smaller than the current values, >+ * then update the regs with the new values. >+ * >+ * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 >+ * >+ */ >+void apply_DEDCN21_142_wa_for_hostvm_deadline( >+ struct hubp *hubp, >+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr) >+{ >+ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); >+ uint32_t cur_value; >+ >+ REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); >+ if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) >+ REG_SET(VBLANK_PARAMETERS_5, 0, >+ REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); >+ >+ REG_GET(VBLANK_PARAMETERS_6, >+ REFCYC_PER_VM_REQ_VBLANK, >+ &cur_value); >+ if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) >+ REG_SET(VBLANK_PARAMETERS_6, 0, >+ REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); >+ >+ REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); >+ if (cur_value > dlg_attr->refcyc_per_vm_group_flip) >+ REG_SET(FLIP_PARAMETERS_3, 0, >+ REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); >+ >+ REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); >+ if (cur_value > dlg_attr->refcyc_per_vm_req_flip) >+ REG_SET(FLIP_PARAMETERS_4, 0, >+ REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); >+ >+ REG_SET(FLIP_PARAMETERS_5, 0, >+ REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); >+ REG_SET(FLIP_PARAMETERS_6, 0, >+ REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); >+} >+ >+void hubp21_program_deadline( >+ struct hubp *hubp, >+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr, >+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr) >+{ >+ hubp2_program_deadline(hubp, dlg_attr, ttu_attr); >+ >+ apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); >+} >+ >+void hubp21_program_requestor( >+ struct hubp *hubp, >+ struct _vcs_dpi_display_rq_regs_st *rq_regs) >+{ >+ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); >+ >+ REG_UPDATE(HUBPRET_CONTROL, >+ DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); >+ REG_SET_4(DCN_EXPANSION_MODE, 0, >+ DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, >+ PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, >+ MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, >+ CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); >+ REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, >+ CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, >+ MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, >+ META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, >+ MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, >+ DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, >+ VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, >+ SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, >+ PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); >+ REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, >+ CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, >+ MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, >+ META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, >+ MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, >+ DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, >+ SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, >+ PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); >+} >+ >+static void hubp21_setup( >+ struct hubp *hubp, >+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr, >+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr, >+ struct _vcs_dpi_display_rq_regs_st *rq_regs, >+ struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) >+{ >+ /* otg is locked when this func is called. Register are double buffered. >+ * disable the requestors is not needed >+ */ >+ >+ hubp2_vready_at_or_After_vsync(hubp, pipe_dest); >+ hubp21_program_requestor(hubp, rq_regs); >+ hubp21_program_deadline(hubp, dlg_attr, ttu_attr); >+ >+} >+ >+void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, >+ struct vm_system_aperture_param *apt) >+{ >+ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); >+ >+ PHYSICAL_ADDRESS_LOC mc_vm_apt_default; >+ PHYSICAL_ADDRESS_LOC mc_vm_apt_low; >+ PHYSICAL_ADDRESS_LOC mc_vm_apt_high; >+ >+ // The format of default addr is 48:12 of the 48 bit addr >+ mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; >+ >+ // The format of high/low are 48:18 of the 48 bit addr >+ mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; >+ mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; >+ >+ REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, >+ MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); >+ >+ REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, >+ MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); >+ >+ REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, >+ ENABLE_L1_TLB, 1, >+ SYSTEM_ACCESS_MODE, 0x3); >+} >+ >+void hubp21_init(struct hubp *hubp) >+{ >+ // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta >+ // This is a chicken bit to enable the ECO fix. >+ >+ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); >+ //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; >+ REG_WRITE(HUBPREQ_DEBUG, 1 << 26); >+} >+static struct hubp_funcs dcn21_hubp_funcs = { >+ .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, >+ .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, >+ .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, >+ .hubp_program_surface_config = hubp2_program_surface_config, >+ .hubp_is_flip_pending = hubp1_is_flip_pending, >+ .hubp_setup = hubp21_setup, >+ .hubp_setup_interdependent = hubp2_setup_interdependent, >+ .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, >+ .set_blank = hubp1_set_blank, >+ .dcc_control = hubp1_dcc_control, >+ .mem_program_viewport = min_set_viewport, >+ .set_cursor_attributes = hubp2_cursor_set_attributes, >+ .set_cursor_position = hubp1_cursor_set_position, >+ .hubp_clk_cntl = hubp1_clk_cntl, >+ .hubp_vtg_sel = hubp1_vtg_sel, >+ .dmdata_set_attributes = hubp2_dmdata_set_attributes, >+ .dmdata_load = hubp2_dmdata_load, >+ .dmdata_status_done = hubp2_dmdata_status_done, >+ .hubp_read_state = hubp1_read_state, >+ .hubp_clear_underflow = hubp1_clear_underflow, >+ .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, >+ .hubp_init = hubp21_init, >+}; >+ >+bool hubp21_construct( >+ struct dcn21_hubp *hubp21, >+ struct dc_context *ctx, >+ uint32_t inst, >+ const struct dcn_hubp2_registers *hubp_regs, >+ const struct dcn_hubp2_shift *hubp_shift, >+ const struct dcn_hubp2_mask *hubp_mask) >+{ >+ hubp21->base.funcs = &dcn21_hubp_funcs; >+ hubp21->base.ctx = ctx; >+ hubp21->hubp_regs = hubp_regs; >+ hubp21->hubp_shift = hubp_shift; >+ hubp21->hubp_mask = hubp_mask; >+ hubp21->base.inst = inst; >+ hubp21->base.opp_id = OPP_ID_INVALID; >+ hubp21->base.mpcc_id = 0xf; >+ >+ return true; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 2019-08-31 15:01:11.866736169 -0500 >@@ -0,0 +1,133 @@ >+/* >+* Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef DAL_DC_DCN21_DCN21_HUBP_H_ >+#define DAL_DC_DCN21_DCN21_HUBP_H_ >+ >+#include "../dcn20/dcn20_hubp.h" >+#include "../dcn10/dcn10_hubp.h" >+ >+#define TO_DCN21_HUBP(hubp)\ >+ container_of(hubp, struct dcn21_hubp, base) >+ >+#define HUBP_REG_LIST_DCN21(id)\ >+ HUBP_REG_LIST_DCN2_COMMON(id),\ >+ SRI(FLIP_PARAMETERS_3, HUBPREQ, id),\ >+ SRI(FLIP_PARAMETERS_4, HUBPREQ, id),\ >+ SRI(FLIP_PARAMETERS_5, HUBPREQ, id),\ >+ SRI(FLIP_PARAMETERS_6, HUBPREQ, id),\ >+ SRI(VBLANK_PARAMETERS_5, HUBPREQ, id),\ >+ SRI(VBLANK_PARAMETERS_6, HUBPREQ, id) >+ >+#define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\ >+ HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ >+ HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ >+ HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ >+ HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ >+ HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ >+ HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ >+ HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ >+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ >+ HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ >+ HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ >+ HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ >+ HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ >+ HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ >+ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ >+ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ >+ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ >+ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ >+ HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ >+ HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ >+ HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ >+ HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ >+ HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ >+ HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\ >+ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\ >+ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\ >+ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\ >+ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\ >+ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\ >+ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\ >+ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh) >+ >+#define HUBP_MASK_SH_LIST_DCN21(mask_sh)\ >+ HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\ >+ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh) >+ >+ >+struct dcn21_hubp { >+ struct hubp base; >+ struct dcn_hubp_state state; >+ const struct dcn_hubp2_registers *hubp_regs; >+ const struct dcn_hubp2_shift *hubp_shift; >+ const struct dcn_hubp2_mask *hubp_mask; >+}; >+ >+bool hubp21_construct( >+ struct dcn21_hubp *hubp21, >+ struct dc_context *ctx, >+ uint32_t inst, >+ const struct dcn_hubp2_registers *hubp_regs, >+ const struct dcn_hubp2_shift *hubp_shift, >+ const struct dcn_hubp2_mask *hubp_mask); >+ >+void apply_DEDCN21_142_wa_for_hostvm_deadline( >+ struct hubp *hubp, >+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr); >+ >+void hubp21_program_deadline( >+ struct hubp *hubp, >+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr, >+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr); >+ >+void hubp21_program_requestor( >+ struct hubp *hubp, >+ struct _vcs_dpi_display_rq_regs_st *rq_regs); >+#endif /* DAL_DC_DCN21_DCN21_HUBP_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 2019-08-31 15:01:11.866736169 -0500 >@@ -0,0 +1,1680 @@ >+/* >+* Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#include "dm_services.h" >+#include "dc.h" >+ >+#include "resource.h" >+#include "include/irq_service_interface.h" >+#include "dcn20/dcn20_resource.h" >+ >+#include "clk_mgr.h" >+#include "dcn10/dcn10_hubp.h" >+#include "dcn10/dcn10_ipp.h" >+#include "dcn20/dcn20_hubbub.h" >+#include "dcn20/dcn20_mpc.h" >+#include "dcn20/dcn20_hubp.h" >+#include "dcn21_hubp.h" >+#include "irq/dcn21/irq_service_dcn21.h" >+#include "dcn20/dcn20_dpp.h" >+#include "dcn20/dcn20_optc.h" >+#include "dcn20/dcn20_hwseq.h" >+#include "dce110/dce110_hw_sequencer.h" >+#include "dcn20/dcn20_opp.h" >+#include "dcn20/dcn20_dsc.h" >+#include "dcn20/dcn20_link_encoder.h" >+#include "dcn20/dcn20_stream_encoder.h" >+#include "dce/dce_clock_source.h" >+#include "dce/dce_audio.h" >+#include "dce/dce_hwseq.h" >+#include "virtual/virtual_stream_encoder.h" >+#include "dce110/dce110_resource.h" >+#include "dml/display_mode_vba.h" >+#include "dcn20/dcn20_dccg.h" >+#include "dcn21_hubbub.h" >+#include "dcn10/dcn10_resource.h" >+ >+#include "dcn20/dcn20_dwb.h" >+#include "dcn20/dcn20_mmhubbub.h" >+ >+#include "renoir_ip_offset.h" >+#include "dcn/dcn_2_1_0_offset.h" >+#include "dcn/dcn_2_1_0_sh_mask.h" >+ >+#include "nbio/nbio_7_0_offset.h" >+ >+#include "mmhub/mmhub_2_0_0_offset.h" >+#include "mmhub/mmhub_2_0_0_sh_mask.h" >+ >+#include "reg_helper.h" >+#include "dce/dce_abm.h" >+#include "dce/dce_dmcu.h" >+#include "dce/dce_aux.h" >+#include "dce/dce_i2c.h" >+#include "dcn21_resource.h" >+#include "vm_helper.h" >+#include "dcn20/dcn20_vmid.h" >+ >+#define SOC_BOUNDING_BOX_VALID false >+#define DC_LOGGER_INIT(logger) >+ >+ >+struct _vcs_dpi_ip_params_st dcn2_1_ip = { >+ .gpuvm_enable = 0, >+ .hostvm_enable = 0, >+ .gpuvm_max_page_table_levels = 1, >+ .hostvm_max_page_table_levels = 4, >+ .hostvm_cached_page_table_levels = 2, >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ .num_dsc = 3, >+#else >+ .num_dsc = 0, >+#endif >+ .rob_buffer_size_kbytes = 168, >+ .det_buffer_size_kbytes = 164, >+ .dpte_buffer_size_in_pte_reqs_luma = 44, >+ .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo >+ .dpp_output_buffer_pixels = 2560, >+ .opp_output_buffer_lines = 1, >+ .pixel_chunk_size_kbytes = 8, >+ .pte_enable = 1, >+ .max_page_table_levels = 4, >+ .pte_chunk_size_kbytes = 2, >+ .meta_chunk_size_kbytes = 2, >+ .writeback_chunk_size_kbytes = 2, >+ .line_buffer_size_bits = 789504, >+ .is_line_buffer_bpp_fixed = 0, >+ .line_buffer_fixed_bpp = 0, >+ .dcc_supported = true, >+ .max_line_buffer_lines = 12, >+ .writeback_luma_buffer_size_kbytes = 12, >+ .writeback_chroma_buffer_size_kbytes = 8, >+ .writeback_chroma_line_buffer_width_pixels = 4, >+ .writeback_max_hscl_ratio = 1, >+ .writeback_max_vscl_ratio = 1, >+ .writeback_min_hscl_ratio = 1, >+ .writeback_min_vscl_ratio = 1, >+ .writeback_max_hscl_taps = 12, >+ .writeback_max_vscl_taps = 12, >+ .writeback_line_buffer_luma_buffer_size = 0, >+ .writeback_line_buffer_chroma_buffer_size = 14643, >+ .cursor_buffer_size = 8, >+ .cursor_chunk_size = 2, >+ .max_num_otg = 4, >+ .max_num_dpp = 4, >+ .max_num_wb = 1, >+ .max_dchub_pscl_bw_pix_per_clk = 4, >+ .max_pscl_lb_bw_pix_per_clk = 2, >+ .max_lb_vscl_bw_pix_per_clk = 4, >+ .max_vscl_hscl_bw_pix_per_clk = 4, >+ .max_hscl_ratio = 4, >+ .max_vscl_ratio = 4, >+ .hscl_mults = 4, >+ .vscl_mults = 4, >+ .max_hscl_taps = 8, >+ .max_vscl_taps = 8, >+ .dispclk_ramp_margin_percent = 1, >+ .underscan_factor = 1.10, >+ .min_vblank_lines = 32, // >+ .dppclk_delay_subtotal = 77, // >+ .dppclk_delay_scl_lb_only = 16, >+ .dppclk_delay_scl = 50, >+ .dppclk_delay_cnvc_formatter = 8, >+ .dppclk_delay_cnvc_cursor = 6, >+ .dispclk_delay_subtotal = 87, // >+ .dcfclk_cstate_latency = 10, // SRExitTime >+ .max_inter_dcn_tile_repeaters = 8, >+ >+ .xfc_supported = false, >+ .xfc_fill_bw_overhead_percent = 10.0, >+ .xfc_fill_constant_bytes = 0, >+ .ptoi_supported = 0 >+}; >+ >+struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { >+ .clock_limits = { >+ { >+ .state = 0, >+ .dcfclk_mhz = 304.0, >+ .fabricclk_mhz = 600.0, >+ .dispclk_mhz = 618.0, >+ .dppclk_mhz = 440.0, >+ .phyclk_mhz = 600.0, >+ .socclk_mhz = 278.0, >+ .dscclk_mhz = 205.67, >+ .dram_speed_mts = 1600.0, >+ }, >+ { >+ .state = 1, >+ .dcfclk_mhz = 304.0, >+ .fabricclk_mhz = 600.0, >+ .dispclk_mhz = 618.0, >+ .dppclk_mhz = 618.0, >+ .phyclk_mhz = 600.0, >+ .socclk_mhz = 278.0, >+ .dscclk_mhz = 205.67, >+ .dram_speed_mts = 1600.0, >+ }, >+ { >+ .state = 2, >+ .dcfclk_mhz = 608.0, >+ .fabricclk_mhz = 1066.0, >+ .dispclk_mhz = 888.0, >+ .dppclk_mhz = 888.0, >+ .phyclk_mhz = 810.0, >+ .socclk_mhz = 278.0, >+ .dscclk_mhz = 287.67, >+ .dram_speed_mts = 2133.0, >+ }, >+ { >+ .state = 3, >+ .dcfclk_mhz = 676.0, >+ .fabricclk_mhz = 1600.0, >+ .dispclk_mhz = 1015.0, >+ .dppclk_mhz = 1015.0, >+ .phyclk_mhz = 810.0, >+ .socclk_mhz = 715.0, >+ .dscclk_mhz = 318.334, >+ .dram_speed_mts = 4266.0, >+ }, >+ { >+ .state = 4, >+ .dcfclk_mhz = 810.0, >+ .fabricclk_mhz = 1600.0, >+ .dispclk_mhz = 1015.0, >+ .dppclk_mhz = 1015.0, >+ .phyclk_mhz = 810.0, >+ .socclk_mhz = 953.0, >+ .dscclk_mhz = 318.334, >+ .dram_speed_mts = 4266.0, >+ }, >+ /*Extra state, no dispclk ramping*/ >+ { >+ .state = 5, >+ .dcfclk_mhz = 810.0, >+ .fabricclk_mhz = 1600.0, >+ .dispclk_mhz = 1015.0, >+ .dppclk_mhz = 1015.0, >+ .phyclk_mhz = 810.0, >+ .socclk_mhz = 953.0, >+ .dscclk_mhz = 318.334, >+ .dram_speed_mts = 4266.0, >+ }, >+ >+ }, >+ >+ .sr_exit_time_us = 9.0, >+ .sr_enter_plus_exit_time_us = 11.0, >+ .urgent_latency_us = 4.0, >+ .urgent_latency_pixel_data_only_us = 4.0, >+ .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, >+ .urgent_latency_vm_data_only_us = 4.0, >+ .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, >+ .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, >+ .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, >+ .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, >+ .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, >+ .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, >+ .max_avg_sdp_bw_use_normal_percent = 60.0, >+ .max_avg_dram_bw_use_normal_percent = 100.0, >+ .writeback_latency_us = 12.0, >+ .max_request_size_bytes = 256, >+ .dram_channel_width_bytes = 4, >+ .fabric_datapath_to_dcn_data_return_bytes = 32, >+ .dcn_downspread_percent = 0.5, >+ .downspread_percent = 0.5, >+ .dram_page_open_time_ns = 50.0, >+ .dram_rw_turnaround_time_ns = 17.5, >+ .dram_return_buffer_per_channel_bytes = 8192, >+ .round_trip_ping_latency_dcfclk_cycles = 128, >+ .urgent_out_of_order_return_per_channel_bytes = 4096, >+ .channel_interleave_bytes = 256, >+ .num_banks = 8, >+ .num_chans = 4, >+ .vmm_page_size_bytes = 4096, >+ .dram_clock_change_latency_us = 23.84, >+ .return_bus_width_bytes = 64, >+ .dispclk_dppclk_vco_speed_mhz = 3550, >+ .xfc_bus_transport_time_us = 4, >+ .xfc_xbuf_latency_tolerance_us = 4, >+ .use_urgent_burst_bw = 1, >+ .num_states = 5 >+}; >+ >+#ifndef MAX >+#define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) >+#endif >+#ifndef MIN >+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) >+#endif >+ >+/* begin ********************* >+ * macros to expend register list macro defined in HW object header file */ >+ >+/* DCN */ >+/* TODO awful hack. fixup dcn20_dwb.h */ >+#undef BASE_INNER >+#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg >+ >+#define BASE(seg) BASE_INNER(seg) >+ >+#define SR(reg_name)\ >+ .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ >+ mm ## reg_name >+ >+#define SRI(reg_name, block, id)\ >+ .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ >+ mm ## block ## id ## _ ## reg_name >+ >+#define SRIR(var_name, reg_name, block, id)\ >+ .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ >+ mm ## block ## id ## _ ## reg_name >+ >+#define SRII(reg_name, block, id)\ >+ .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ >+ mm ## block ## id ## _ ## reg_name >+ >+#define DCCG_SRII(reg_name, block, id)\ >+ .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ >+ mm ## block ## id ## _ ## reg_name >+ >+/* NBIO */ >+#define NBIO_BASE_INNER(seg) \ >+ NBIF0_BASE__INST0_SEG ## seg >+ >+#define NBIO_BASE(seg) \ >+ NBIO_BASE_INNER(seg) >+ >+#define NBIO_SR(reg_name)\ >+ .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ >+ mm ## reg_name >+ >+/* MMHUB */ >+#define MMHUB_BASE_INNER(seg) \ >+ MMHUB_BASE__INST0_SEG ## seg >+ >+#define MMHUB_BASE(seg) \ >+ MMHUB_BASE_INNER(seg) >+ >+#define MMHUB_SR(reg_name)\ >+ .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ >+ mmMM ## reg_name >+ >+#define clk_src_regs(index, pllid)\ >+[index] = {\ >+ CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ >+} >+ >+static const struct dce110_clk_src_regs clk_src_regs[] = { >+ clk_src_regs(0, A), >+ clk_src_regs(1, B), >+ clk_src_regs(2, C), >+ clk_src_regs(3, D), >+ clk_src_regs(4, E), >+}; >+ >+static const struct dce110_clk_src_shift cs_shift = { >+ CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) >+}; >+ >+static const struct dce110_clk_src_mask cs_mask = { >+ CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) >+}; >+ >+static const struct bios_registers bios_regs = { >+ NBIO_SR(BIOS_SCRATCH_3), >+ NBIO_SR(BIOS_SCRATCH_6) >+}; >+ >+#ifdef CONFIG_DRM_AMD_DC_DMUB >+static const struct dcn21_dmcub_registers dmcub_regs = { >+ DMCUB_REG_LIST_DCN() >+}; >+ >+static const struct dcn21_dmcub_shift dmcub_shift = { >+ DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT) >+}; >+ >+static const struct dcn21_dmcub_mask dmcub_mask = { >+ DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK) >+}; >+#endif >+ >+#define audio_regs(id)\ >+[id] = {\ >+ AUD_COMMON_REG_LIST(id)\ >+} >+ >+static const struct dce_audio_registers audio_regs[] = { >+ audio_regs(0), >+ audio_regs(1), >+ audio_regs(2), >+ audio_regs(3), >+ audio_regs(4), >+ audio_regs(5), >+}; >+ >+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ >+ SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ >+ SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ >+ AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) >+ >+static const struct dce_audio_shift audio_shift = { >+ DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) >+}; >+ >+static const struct dce_audio_mask audio_mask = { >+ DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) >+}; >+ >+static const struct dccg_registers dccg_regs = { >+ DCCG_COMMON_REG_LIST_DCN_BASE() >+}; >+ >+static const struct dccg_shift dccg_shift = { >+ DCCG_MASK_SH_LIST_DCN2(__SHIFT) >+}; >+ >+static const struct dccg_mask dccg_mask = { >+ DCCG_MASK_SH_LIST_DCN2(_MASK) >+}; >+ >+#define opp_regs(id)\ >+[id] = {\ >+ OPP_REG_LIST_DCN20(id),\ >+} >+ >+static const struct dcn20_opp_registers opp_regs[] = { >+ opp_regs(0), >+ opp_regs(1), >+ opp_regs(2), >+ opp_regs(3), >+ opp_regs(4), >+ opp_regs(5), >+}; >+ >+static const struct dcn20_opp_shift opp_shift = { >+ OPP_MASK_SH_LIST_DCN20(__SHIFT) >+}; >+ >+static const struct dcn20_opp_mask opp_mask = { >+ OPP_MASK_SH_LIST_DCN20(_MASK) >+}; >+ >+#define tg_regs(id)\ >+[id] = {TG_COMMON_REG_LIST_DCN2_0(id)} >+ >+static const struct dcn_optc_registers tg_regs[] = { >+ tg_regs(0), >+ tg_regs(1), >+ tg_regs(2), >+ tg_regs(3) >+}; >+ >+static const struct dcn_optc_shift tg_shift = { >+ TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) >+}; >+ >+static const struct dcn_optc_mask tg_mask = { >+ TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) >+}; >+ >+static const struct dcn20_mpc_registers mpc_regs = { >+ MPC_REG_LIST_DCN2_0(0), >+ MPC_REG_LIST_DCN2_0(1), >+ MPC_REG_LIST_DCN2_0(2), >+ MPC_REG_LIST_DCN2_0(3), >+ MPC_REG_LIST_DCN2_0(4), >+ MPC_REG_LIST_DCN2_0(5), >+ MPC_OUT_MUX_REG_LIST_DCN2_0(0), >+ MPC_OUT_MUX_REG_LIST_DCN2_0(1), >+ MPC_OUT_MUX_REG_LIST_DCN2_0(2), >+ MPC_OUT_MUX_REG_LIST_DCN2_0(3) >+}; >+ >+static const struct dcn20_mpc_shift mpc_shift = { >+ MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) >+}; >+ >+static const struct dcn20_mpc_mask mpc_mask = { >+ MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) >+}; >+ >+#define hubp_regs(id)\ >+[id] = {\ >+ HUBP_REG_LIST_DCN21(id)\ >+} >+ >+static const struct dcn_hubp2_registers hubp_regs[] = { >+ hubp_regs(0), >+ hubp_regs(1), >+ hubp_regs(2), >+ hubp_regs(3) >+}; >+ >+static const struct dcn_hubp2_shift hubp_shift = { >+ HUBP_MASK_SH_LIST_DCN21(__SHIFT) >+}; >+ >+static const struct dcn_hubp2_mask hubp_mask = { >+ HUBP_MASK_SH_LIST_DCN21(_MASK) >+}; >+ >+static const struct dcn_hubbub_registers hubbub_reg = { >+ HUBBUB_REG_LIST_DCN21() >+}; >+ >+static const struct dcn_hubbub_shift hubbub_shift = { >+ HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) >+}; >+ >+static const struct dcn_hubbub_mask hubbub_mask = { >+ HUBBUB_MASK_SH_LIST_DCN21(_MASK) >+}; >+ >+ >+#define vmid_regs(id)\ >+[id] = {\ >+ DCN20_VMID_REG_LIST(id)\ >+} >+ >+static const struct dcn_vmid_registers vmid_regs[] = { >+ vmid_regs(0), >+ vmid_regs(1), >+ vmid_regs(2), >+ vmid_regs(3), >+ vmid_regs(4), >+ vmid_regs(5), >+ vmid_regs(6), >+ vmid_regs(7), >+ vmid_regs(8), >+ vmid_regs(9), >+ vmid_regs(10), >+ vmid_regs(11), >+ vmid_regs(12), >+ vmid_regs(13), >+ vmid_regs(14), >+ vmid_regs(15) >+}; >+ >+static const struct dcn20_vmid_shift vmid_shifts = { >+ DCN20_VMID_MASK_SH_LIST(__SHIFT) >+}; >+ >+static const struct dcn20_vmid_mask vmid_masks = { >+ DCN20_VMID_MASK_SH_LIST(_MASK) >+}; >+ >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+#define dsc_regsDCN20(id)\ >+[id] = {\ >+ DSC_REG_LIST_DCN20(id)\ >+} >+ >+static const struct dcn20_dsc_registers dsc_regs[] = { >+ dsc_regsDCN20(0), >+ dsc_regsDCN20(1), >+ dsc_regsDCN20(2), >+ dsc_regsDCN20(3), >+ dsc_regsDCN20(4), >+ dsc_regsDCN20(5) >+}; >+ >+static const struct dcn20_dsc_shift dsc_shift = { >+ DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) >+}; >+ >+static const struct dcn20_dsc_mask dsc_mask = { >+ DSC_REG_LIST_SH_MASK_DCN20(_MASK) >+}; >+#endif >+ >+#define ipp_regs(id)\ >+[id] = {\ >+ IPP_REG_LIST_DCN20(id),\ >+} >+ >+static const struct dcn10_ipp_registers ipp_regs[] = { >+ ipp_regs(0), >+ ipp_regs(1), >+ ipp_regs(2), >+ ipp_regs(3), >+}; >+ >+static const struct dcn10_ipp_shift ipp_shift = { >+ IPP_MASK_SH_LIST_DCN20(__SHIFT) >+}; >+ >+static const struct dcn10_ipp_mask ipp_mask = { >+ IPP_MASK_SH_LIST_DCN20(_MASK), >+}; >+ >+#define opp_regs(id)\ >+[id] = {\ >+ OPP_REG_LIST_DCN20(id),\ >+} >+ >+ >+#define aux_engine_regs(id)\ >+[id] = {\ >+ AUX_COMMON_REG_LIST0(id), \ >+ .AUXN_IMPCAL = 0, \ >+ .AUXP_IMPCAL = 0, \ >+ .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ >+} >+ >+static const struct dce110_aux_registers aux_engine_regs[] = { >+ aux_engine_regs(0), >+ aux_engine_regs(1), >+ aux_engine_regs(2), >+ aux_engine_regs(3), >+ aux_engine_regs(4), >+}; >+ >+#define tf_regs(id)\ >+[id] = {\ >+ TF_REG_LIST_DCN20(id),\ >+} >+ >+static const struct dcn2_dpp_registers tf_regs[] = { >+ tf_regs(0), >+ tf_regs(1), >+ tf_regs(2), >+ tf_regs(3), >+}; >+ >+static const struct dcn2_dpp_shift tf_shift = { >+ TF_REG_LIST_SH_MASK_DCN20(__SHIFT) >+}; >+ >+static const struct dcn2_dpp_mask tf_mask = { >+ TF_REG_LIST_SH_MASK_DCN20(_MASK) >+}; >+ >+#define stream_enc_regs(id)\ >+[id] = {\ >+ SE_DCN2_REG_LIST(id)\ >+} >+ >+static const struct dcn10_stream_enc_registers stream_enc_regs[] = { >+ stream_enc_regs(0), >+ stream_enc_regs(1), >+ stream_enc_regs(2), >+ stream_enc_regs(3), >+ stream_enc_regs(4), >+}; >+ >+static const struct dcn10_stream_encoder_shift se_shift = { >+ SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) >+}; >+ >+static const struct dcn10_stream_encoder_mask se_mask = { >+ SE_COMMON_MASK_SH_LIST_DCN20(_MASK) >+}; >+ >+static struct input_pixel_processor *dcn21_ipp_create( >+ struct dc_context *ctx, uint32_t inst) >+{ >+ struct dcn10_ipp *ipp = >+ kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); >+ >+ if (!ipp) { >+ BREAK_TO_DEBUGGER(); >+ return NULL; >+ } >+ >+ dcn20_ipp_construct(ipp, ctx, inst, >+ &ipp_regs[inst], &ipp_shift, &ipp_mask); >+ return &ipp->base; >+} >+ >+static struct dpp *dcn21_dpp_create( >+ struct dc_context *ctx, >+ uint32_t inst) >+{ >+ struct dcn20_dpp *dpp = >+ kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); >+ >+ if (!dpp) >+ return NULL; >+ >+ if (dpp2_construct(dpp, ctx, inst, >+ &tf_regs[inst], &tf_shift, &tf_mask)) >+ return &dpp->base; >+ >+ BREAK_TO_DEBUGGER(); >+ kfree(dpp); >+ return NULL; >+} >+ >+static struct dce_aux *dcn21_aux_engine_create( >+ struct dc_context *ctx, >+ uint32_t inst) >+{ >+ struct aux_engine_dce110 *aux_engine = >+ kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); >+ >+ if (!aux_engine) >+ return NULL; >+ >+ dce110_aux_engine_construct(aux_engine, ctx, inst, >+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, >+ &aux_engine_regs[inst]); >+ >+ return &aux_engine->base; >+} >+ >+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } >+ >+static const struct dce_i2c_registers i2c_hw_regs[] = { >+ i2c_inst_regs(1), >+ i2c_inst_regs(2), >+ i2c_inst_regs(3), >+ i2c_inst_regs(4), >+ i2c_inst_regs(5), >+}; >+ >+static const struct dce_i2c_shift i2c_shifts = { >+ I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) >+}; >+ >+static const struct dce_i2c_mask i2c_masks = { >+ I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) >+}; >+ >+struct dce_i2c_hw *dcn21_i2c_hw_create( >+ struct dc_context *ctx, >+ uint32_t inst) >+{ >+ struct dce_i2c_hw *dce_i2c_hw = >+ kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); >+ >+ if (!dce_i2c_hw) >+ return NULL; >+ >+ dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, >+ &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); >+ >+ return dce_i2c_hw; >+} >+ >+static const struct resource_caps res_cap_rn = { >+ .num_timing_generator = 4, >+ .num_opp = 4, >+ .num_video_plane = 4, >+ .num_audio = 6, // 6 audio endpoints. 4 audio streams >+ .num_stream_encoder = 5, >+ .num_pll = 5, // maybe 3 because the last two used for USB-c >+ .num_dwb = 1, >+ .num_ddc = 5, >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ .num_dsc = 3, >+#endif >+}; >+ >+#ifdef DIAGS_BUILD >+static const struct resource_caps res_cap_rn_FPGA_4pipe = { >+ .num_timing_generator = 4, >+ .num_opp = 4, >+ .num_video_plane = 4, >+ .num_audio = 7, >+ .num_stream_encoder = 4, >+ .num_pll = 4, >+ .num_dwb = 1, >+ .num_ddc = 4, >+ .num_dsc = 0, >+}; >+ >+static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { >+ .num_timing_generator = 2, >+ .num_opp = 2, >+ .num_video_plane = 2, >+ .num_audio = 7, >+ .num_stream_encoder = 2, >+ .num_pll = 4, >+ .num_dwb = 1, >+ .num_ddc = 4, >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ .num_dsc = 2, >+#endif >+}; >+#endif >+ >+static const struct dc_plane_cap plane_cap = { >+ .type = DC_PLANE_TYPE_DCN_UNIVERSAL, >+ .blends_with_above = true, >+ .blends_with_below = true, >+ .per_pixel_alpha = true, >+ >+ .pixel_format_support = { >+ .argb8888 = true, >+ .nv12 = true, >+ .fp16 = true >+ }, >+ >+ .max_upscale_factor = { >+ .argb8888 = 16000, >+ .nv12 = 16000, >+ .fp16 = 16000 >+ }, >+ >+ .max_downscale_factor = { >+ .argb8888 = 250, >+ .nv12 = 250, >+ .fp16 = 250 >+ } >+}; >+ >+static const struct dc_debug_options debug_defaults_drv = { >+ .disable_dmcu = true, >+ .force_abm_enable = false, >+ .timing_trace = false, >+ .clock_trace = true, >+ .disable_pplib_clock_request = true, >+ .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, >+ .force_single_disp_pipe_split = true, >+ .disable_dcc = DCC_ENABLE, >+ .vsr_support = true, >+ .performance_trace = false, >+ .max_downscale_src_width = 5120,/*upto 5K*/ >+ .disable_pplib_wm_range = false, >+ .scl_reset_length10 = true, >+ .sanity_checks = true, >+ .disable_48mhz_pwrdwn = true, >+}; >+ >+static const struct dc_debug_options debug_defaults_diags = { >+ .disable_dmcu = true, >+ .force_abm_enable = false, >+ .timing_trace = true, >+ .clock_trace = true, >+ .disable_dpp_power_gate = true, >+ .disable_hubp_power_gate = true, >+ .disable_clock_gate = true, >+ .disable_pplib_clock_request = true, >+ .disable_pplib_wm_range = true, >+ .disable_stutter = true, >+ .disable_48mhz_pwrdwn = true, >+}; >+ >+enum dcn20_clk_src_array_id { >+ DCN20_CLK_SRC_PLL0, >+ DCN20_CLK_SRC_PLL1, >+ DCN20_CLK_SRC_TOTAL_DCN21 >+}; >+ >+static void destruct(struct dcn21_resource_pool *pool) >+{ >+ unsigned int i; >+ >+ for (i = 0; i < pool->base.stream_enc_count; i++) { >+ if (pool->base.stream_enc[i] != NULL) { >+ kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); >+ pool->base.stream_enc[i] = NULL; >+ } >+ } >+ >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { >+ if (pool->base.dscs[i] != NULL) >+ dcn20_dsc_destroy(&pool->base.dscs[i]); >+ } >+#endif >+ >+ if (pool->base.mpc != NULL) { >+ kfree(TO_DCN20_MPC(pool->base.mpc)); >+ pool->base.mpc = NULL; >+ } >+ if (pool->base.hubbub != NULL) { >+ kfree(pool->base.hubbub); >+ pool->base.hubbub = NULL; >+ } >+ for (i = 0; i < pool->base.pipe_count; i++) { >+ if (pool->base.dpps[i] != NULL) >+ dcn20_dpp_destroy(&pool->base.dpps[i]); >+ >+ if (pool->base.ipps[i] != NULL) >+ pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); >+ >+ if (pool->base.hubps[i] != NULL) { >+ kfree(TO_DCN20_HUBP(pool->base.hubps[i])); >+ pool->base.hubps[i] = NULL; >+ } >+ >+ if (pool->base.irqs != NULL) { >+ dal_irq_service_destroy(&pool->base.irqs); >+ } >+ } >+ >+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) { >+ if (pool->base.engines[i] != NULL) >+ dce110_engine_destroy(&pool->base.engines[i]); >+ if (pool->base.hw_i2cs[i] != NULL) { >+ kfree(pool->base.hw_i2cs[i]); >+ pool->base.hw_i2cs[i] = NULL; >+ } >+ if (pool->base.sw_i2cs[i] != NULL) { >+ kfree(pool->base.sw_i2cs[i]); >+ pool->base.sw_i2cs[i] = NULL; >+ } >+ } >+ >+ for (i = 0; i < pool->base.res_cap->num_opp; i++) { >+ if (pool->base.opps[i] != NULL) >+ pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); >+ } >+ >+ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { >+ if (pool->base.timing_generators[i] != NULL) { >+ kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); >+ pool->base.timing_generators[i] = NULL; >+ } >+ } >+ >+ for (i = 0; i < pool->base.res_cap->num_dwb; i++) { >+ if (pool->base.dwbc[i] != NULL) { >+ kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); >+ pool->base.dwbc[i] = NULL; >+ } >+ if (pool->base.mcif_wb[i] != NULL) { >+ kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); >+ pool->base.mcif_wb[i] = NULL; >+ } >+ } >+ >+ for (i = 0; i < pool->base.audio_count; i++) { >+ if (pool->base.audios[i]) >+ dce_aud_destroy(&pool->base.audios[i]); >+ } >+ >+ for (i = 0; i < pool->base.clk_src_count; i++) { >+ if (pool->base.clock_sources[i] != NULL) { >+ dcn20_clock_source_destroy(&pool->base.clock_sources[i]); >+ pool->base.clock_sources[i] = NULL; >+ } >+ } >+ >+ if (pool->base.dp_clock_source != NULL) { >+ dcn20_clock_source_destroy(&pool->base.dp_clock_source); >+ pool->base.dp_clock_source = NULL; >+ } >+ >+ >+ if (pool->base.abm != NULL) >+ dce_abm_destroy(&pool->base.abm); >+ >+ if (pool->base.dmcu != NULL) >+ dce_dmcu_destroy(&pool->base.dmcu); >+ >+#ifdef CONFIG_DRM_AMD_DC_DMUB >+ if (pool->base.dmcub != NULL) >+ dcn21_dmcub_destroy(&pool->base.dmcub); >+#endif >+ >+ if (pool->base.dccg != NULL) >+ dcn_dccg_destroy(&pool->base.dccg); >+ >+ if (pool->base.pp_smu != NULL) >+ dcn20_pp_smu_destroy(&pool->base.pp_smu); >+} >+ >+ >+static void calculate_wm_set_for_vlevel( >+ int vlevel, >+ struct wm_range_table_entry *table_entry, >+ struct dcn_watermarks *wm_set, >+ struct display_mode_lib *dml, >+ display_e2e_pipe_params_st *pipes, >+ int pipe_cnt) >+{ >+ double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; >+ >+ ASSERT(vlevel < dml->soc.num_states); >+ /* only pipe 0 is read for voltage and dcf/soc clocks */ >+ pipes[0].clks_cfg.voltage = vlevel; >+ pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; >+ pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; >+ >+ dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; >+ >+ wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; >+ wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; >+ wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; >+ wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; >+ wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; >+ wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; >+#endif >+ dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; >+ >+} >+ >+void dcn21_calculate_wm( >+ struct dc *dc, struct dc_state *context, >+ display_e2e_pipe_params_st *pipes, >+ int *out_pipe_cnt, >+ int *pipe_split_from, >+ int vlevel_req) >+{ >+ int pipe_cnt, i, pipe_idx; >+ int vlevel, vlevel_max; >+ struct wm_range_table_entry *table_entry; >+ struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; >+ >+ ASSERT(bw_params); >+ >+ for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { >+ if (!context->res_ctx.pipe_ctx[i].stream) >+ continue; >+ >+ pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; >+ pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; >+ >+ if (pipe_split_from[i] < 0) { >+ pipes[pipe_cnt].clks_cfg.dppclk_mhz = >+ context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; >+ if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) >+ pipes[pipe_cnt].pipe.dest.odm_combine = >+ context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; >+ else >+ pipes[pipe_cnt].pipe.dest.odm_combine = 0; >+ pipe_idx++; >+ } else { >+ pipes[pipe_cnt].clks_cfg.dppclk_mhz = >+ context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; >+ if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) >+ pipes[pipe_cnt].pipe.dest.odm_combine = >+ context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; >+ else >+ pipes[pipe_cnt].pipe.dest.odm_combine = 0; >+ } >+ pipe_cnt++; >+ } >+ >+ if (pipe_cnt != pipe_idx) { >+ if (dc->res_pool->funcs->populate_dml_pipes) >+ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, >+ &context->res_ctx, pipes); >+ else >+ pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, >+ &context->res_ctx, pipes); >+ } >+ >+ *out_pipe_cnt = pipe_cnt; >+ >+ vlevel_max = bw_params->clk_table.num_entries - 1; >+ >+ >+ /* WM Set D */ >+ table_entry = &bw_params->wm_table.entries[WM_D]; >+ if (table_entry->wm_type == WM_TYPE_RETRAINING) >+ vlevel = 0; >+ else >+ vlevel = vlevel_max; >+ calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, >+ &context->bw_ctx.dml, pipes, pipe_cnt); >+ /* WM Set C */ >+ table_entry = &bw_params->wm_table.entries[WM_C]; >+ vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); >+ calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, >+ &context->bw_ctx.dml, pipes, pipe_cnt); >+ /* WM Set B */ >+ table_entry = &bw_params->wm_table.entries[WM_B]; >+ vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); >+ calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, >+ &context->bw_ctx.dml, pipes, pipe_cnt); >+ >+ /* WM Set A */ >+ table_entry = &bw_params->wm_table.entries[WM_A]; >+ vlevel = MIN(vlevel_req, vlevel_max); >+ calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, >+ &context->bw_ctx.dml, pipes, pipe_cnt); >+} >+ >+ >+bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, >+ bool fast_validate) >+{ >+ bool out = false; >+ >+ BW_VAL_TRACE_SETUP(); >+ >+ int vlevel = 0; >+ int pipe_split_from[MAX_PIPES]; >+ int pipe_cnt = 0; >+ display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); >+ DC_LOGGER_INIT(dc->ctx->logger); >+ >+ BW_VAL_TRACE_COUNT(); >+ >+ out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); >+ >+ if (pipe_cnt == 0) >+ goto validate_out; >+ >+ if (!out) >+ goto validate_fail; >+ >+ BW_VAL_TRACE_END_VOLTAGE_LEVEL(); >+ >+ if (fast_validate) { >+ BW_VAL_TRACE_SKIP(fast); >+ goto validate_out; >+ } >+ >+ dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); >+ dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); >+ >+ BW_VAL_TRACE_END_WATERMARKS(); >+ >+ goto validate_out; >+ >+validate_fail: >+ DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", >+ dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); >+ >+ BW_VAL_TRACE_SKIP(fail); >+ out = false; >+ >+validate_out: >+ kfree(pipes); >+ >+ BW_VAL_TRACE_FINISH(); >+ >+ return out; >+} >+static void dcn21_destroy_resource_pool(struct resource_pool **pool) >+{ >+ struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); >+ >+ destruct(dcn21_pool); >+ kfree(dcn21_pool); >+ *pool = NULL; >+} >+ >+static struct clock_source *dcn21_clock_source_create( >+ struct dc_context *ctx, >+ struct dc_bios *bios, >+ enum clock_source_id id, >+ const struct dce110_clk_src_regs *regs, >+ bool dp_clk_src) >+{ >+ struct dce110_clk_src *clk_src = >+ kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); >+ >+ if (!clk_src) >+ return NULL; >+ >+ if (dcn20_clk_src_construct(clk_src, ctx, bios, id, >+ regs, &cs_shift, &cs_mask)) { >+ clk_src->base.dp_clk_src = dp_clk_src; >+ return &clk_src->base; >+ } >+ >+ BREAK_TO_DEBUGGER(); >+ return NULL; >+} >+ >+static struct hubp *dcn21_hubp_create( >+ struct dc_context *ctx, >+ uint32_t inst) >+{ >+ struct dcn21_hubp *hubp21 = >+ kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); >+ >+ if (!hubp21) >+ return NULL; >+ >+ if (hubp21_construct(hubp21, ctx, inst, >+ &hubp_regs[inst], &hubp_shift, &hubp_mask)) >+ return &hubp21->base; >+ >+ BREAK_TO_DEBUGGER(); >+ kfree(hubp21); >+ return NULL; >+} >+ >+static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) >+{ >+ int i; >+ >+ struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), >+ GFP_KERNEL); >+ >+ if (!hubbub) >+ return NULL; >+ >+ hubbub21_construct(hubbub, ctx, >+ &hubbub_reg, >+ &hubbub_shift, >+ &hubbub_mask); >+ >+ for (i = 0; i < res_cap_rn.num_vmid; i++) { >+ struct dcn20_vmid *vmid = &hubbub->vmid[i]; >+ >+ vmid->ctx = ctx; >+ >+ vmid->regs = &vmid_regs[i]; >+ vmid->shifts = &vmid_shifts; >+ vmid->masks = &vmid_masks; >+ } >+ >+ return &hubbub->base; >+} >+ >+struct output_pixel_processor *dcn21_opp_create( >+ struct dc_context *ctx, uint32_t inst) >+{ >+ struct dcn20_opp *opp = >+ kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); >+ >+ if (!opp) { >+ BREAK_TO_DEBUGGER(); >+ return NULL; >+ } >+ >+ dcn20_opp_construct(opp, ctx, inst, >+ &opp_regs[inst], &opp_shift, &opp_mask); >+ return &opp->base; >+} >+ >+struct timing_generator *dcn21_timing_generator_create( >+ struct dc_context *ctx, >+ uint32_t instance) >+{ >+ struct optc *tgn10 = >+ kzalloc(sizeof(struct optc), GFP_KERNEL); >+ >+ if (!tgn10) >+ return NULL; >+ >+ tgn10->base.inst = instance; >+ tgn10->base.ctx = ctx; >+ >+ tgn10->tg_regs = &tg_regs[instance]; >+ tgn10->tg_shift = &tg_shift; >+ tgn10->tg_mask = &tg_mask; >+ >+ dcn20_timing_generator_init(tgn10); >+ >+ return &tgn10->base; >+} >+ >+struct mpc *dcn21_mpc_create(struct dc_context *ctx) >+{ >+ struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), >+ GFP_KERNEL); >+ >+ if (!mpc20) >+ return NULL; >+ >+ dcn20_mpc_construct(mpc20, ctx, >+ &mpc_regs, >+ &mpc_shift, >+ &mpc_mask, >+ 6); >+ >+ return &mpc20->base; >+} >+ >+static void read_dce_straps( >+ struct dc_context *ctx, >+ struct resource_straps *straps) >+{ >+ generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), >+ FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); >+ >+} >+ >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ >+struct display_stream_compressor *dcn21_dsc_create( >+ struct dc_context *ctx, uint32_t inst) >+{ >+ struct dcn20_dsc *dsc = >+ kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); >+ >+ if (!dsc) { >+ BREAK_TO_DEBUGGER(); >+ return NULL; >+ } >+ >+ dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); >+ return &dsc->base; >+} >+#endif >+ >+static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) >+{ >+ struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); >+ struct clk_limit_table *clk_table = &bw_params->clk_table; >+ int i; >+ >+ dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; >+ dcn2_1_ip.max_num_dpp = pool->base.pipe_count; >+ dcn2_1_soc.num_chans = bw_params->num_channels; >+ dcn2_1_soc.num_states = 0; >+ >+ for (i = 0; i < clk_table->num_entries; i++) { >+ >+ dcn2_1_soc.clock_limits[i].state = i; >+ dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; >+ dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; >+ dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; >+ /* This is probably wrong, TODO: find correct calculation */ >+ dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000; >+ dcn2_1_soc.num_states++; >+ } >+} >+ >+/* Temporary Place holder until we can get them from fuse */ >+static struct dpm_clocks dummy_clocks = { >+ .DcfClocks = { >+ {.Freq = 400, .Vol = 1}, >+ {.Freq = 483, .Vol = 1}, >+ {.Freq = 602, .Vol = 1}, >+ {.Freq = 738, .Vol = 1} }, >+ .SocClocks = { >+ {.Freq = 300, .Vol = 1}, >+ {.Freq = 400, .Vol = 1}, >+ {.Freq = 400, .Vol = 1}, >+ {.Freq = 400, .Vol = 1} }, >+ .FClocks = { >+ {.Freq = 400, .Vol = 1}, >+ {.Freq = 800, .Vol = 1}, >+ {.Freq = 1067, .Vol = 1}, >+ {.Freq = 1600, .Vol = 1} }, >+ .MemClocks = { >+ {.Freq = 800, .Vol = 1}, >+ {.Freq = 1600, .Vol = 1}, >+ {.Freq = 1067, .Vol = 1}, >+ {.Freq = 1600, .Vol = 1} }, >+ >+}; >+ >+enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, >+ struct pp_smu_wm_range_sets *ranges) >+{ >+ return PP_SMU_RESULT_OK; >+} >+ >+enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, >+ struct dpm_clocks *clock_table) >+{ >+ *clock_table = dummy_clocks; >+ return PP_SMU_RESULT_OK; >+} >+ >+struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) >+{ >+ struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); >+ >+ pp_smu->ctx.ver = PP_SMU_VER_RN; >+ >+ pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; >+ pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; >+ >+ return pp_smu; >+} >+ >+void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) >+{ >+ if (pp_smu && *pp_smu) { >+ kfree(*pp_smu); >+ *pp_smu = NULL; >+ } >+} >+ >+static struct audio *dcn21_create_audio( >+ struct dc_context *ctx, unsigned int inst) >+{ >+ return dce_audio_create(ctx, inst, >+ &audio_regs[inst], &audio_shift, &audio_mask); >+} >+ >+static struct dc_cap_funcs cap_funcs = { >+ .get_dcc_compression_cap = dcn20_get_dcc_compression_cap >+}; >+ >+struct stream_encoder *dcn21_stream_encoder_create( >+ enum engine_id eng_id, >+ struct dc_context *ctx) >+{ >+ struct dcn10_stream_encoder *enc1 = >+ kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); >+ >+ if (!enc1) >+ return NULL; >+ >+ dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, >+ &stream_enc_regs[eng_id], >+ &se_shift, &se_mask); >+ >+ return &enc1->base; >+} >+ >+static const struct dce_hwseq_registers hwseq_reg = { >+ HWSEQ_DCN21_REG_LIST() >+}; >+ >+static const struct dce_hwseq_shift hwseq_shift = { >+ HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) >+}; >+ >+static const struct dce_hwseq_mask hwseq_mask = { >+ HWSEQ_DCN21_MASK_SH_LIST(_MASK) >+}; >+ >+static struct dce_hwseq *dcn21_hwseq_create( >+ struct dc_context *ctx) >+{ >+ struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); >+ >+ if (hws) { >+ hws->ctx = ctx; >+ hws->regs = &hwseq_reg; >+ hws->shifts = &hwseq_shift; >+ hws->masks = &hwseq_mask; >+ } >+ return hws; >+} >+ >+static const struct resource_create_funcs res_create_funcs = { >+ .read_dce_straps = read_dce_straps, >+ .create_audio = dcn21_create_audio, >+ .create_stream_encoder = dcn21_stream_encoder_create, >+ .create_hwseq = dcn21_hwseq_create, >+}; >+ >+static const struct resource_create_funcs res_create_maximus_funcs = { >+ .read_dce_straps = NULL, >+ .create_audio = NULL, >+ .create_stream_encoder = NULL, >+ .create_hwseq = dcn21_hwseq_create, >+}; >+ >+static struct resource_funcs dcn21_res_pool_funcs = { >+ .destroy = dcn21_destroy_resource_pool, >+ .link_enc_create = dcn20_link_encoder_create, >+ .validate_bandwidth = dcn21_validate_bandwidth, >+ .add_stream_to_ctx = dcn20_add_stream_to_ctx, >+ .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, >+ .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, >+ .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, >+ .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, >+ .set_mcif_arb_params = dcn20_set_mcif_arb_params, >+ .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, >+ .update_bw_bounding_box = update_bw_bounding_box >+}; >+ >+static bool construct( >+ uint8_t num_virtual_links, >+ struct dc *dc, >+ struct dcn21_resource_pool *pool) >+{ >+ int i; >+ struct dc_context *ctx = dc->ctx; >+ struct irq_service_init_data init_data; >+ >+ ctx->dc_bios->regs = &bios_regs; >+ >+ pool->base.res_cap = &res_cap_rn; >+#ifdef DIAGS_BUILD >+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) >+ //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; >+ pool->base.res_cap = &res_cap_rn_FPGA_4pipe; >+#endif >+ >+ pool->base.funcs = &dcn21_res_pool_funcs; >+ >+ /************************************************* >+ * Resource + asic cap harcoding * >+ *************************************************/ >+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; >+ >+ pool->base.pipe_count = 4; >+ dc->caps.max_downscale_ratio = 200; >+ dc->caps.i2c_speed_in_khz = 100; >+ dc->caps.max_cursor_size = 256; >+ dc->caps.dmdata_alloc_size = 2048; >+ dc->caps.hw_3d_lut = true; >+ >+ dc->caps.max_slave_planes = 1; >+ dc->caps.post_blend_color_processing = true; >+ dc->caps.force_dp_tps4_for_cp2520 = true; >+ >+ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) >+ dc->debug = debug_defaults_drv; >+ else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { >+ pool->base.pipe_count = 4; >+ dc->debug = debug_defaults_diags; >+ } else >+ dc->debug = debug_defaults_diags; >+ >+ // Init the vm_helper >+ if (dc->vm_helper) >+ vm_helper_init(dc->vm_helper, 16); >+ >+ /************************************************* >+ * Create resources * >+ *************************************************/ >+ >+ pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = >+ dcn21_clock_source_create(ctx, ctx->dc_bios, >+ CLOCK_SOURCE_COMBO_PHY_PLL0, >+ &clk_src_regs[0], false); >+ pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = >+ dcn21_clock_source_create(ctx, ctx->dc_bios, >+ CLOCK_SOURCE_COMBO_PHY_PLL1, >+ &clk_src_regs[1], false); >+ >+ pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; >+ >+ /* todo: not reuse phy_pll registers */ >+ pool->base.dp_clock_source = >+ dcn21_clock_source_create(ctx, ctx->dc_bios, >+ CLOCK_SOURCE_ID_DP_DTO, >+ &clk_src_regs[0], true); >+ >+ for (i = 0; i < pool->base.clk_src_count; i++) { >+ if (pool->base.clock_sources[i] == NULL) { >+ dm_error("DC: failed to create clock sources!\n"); >+ BREAK_TO_DEBUGGER(); >+ goto create_fail; >+ } >+ } >+ >+ pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); >+ if (pool->base.dccg == NULL) { >+ dm_error("DC: failed to create dccg!\n"); >+ BREAK_TO_DEBUGGER(); >+ goto create_fail; >+ } >+ >+#ifdef CONFIG_DRM_AMD_DC_DMUB >+ pool->base.dmcub = dcn21_dmcub_create(ctx, >+ &dmcub_regs, >+ &dmcub_shift, >+ &dmcub_mask); >+ if (pool->base.dmcub == NULL) { >+ dm_error("DC: failed to create dmcub!\n"); >+ BREAK_TO_DEBUGGER(); >+ goto create_fail; >+ } >+#endif >+ >+ pool->base.pp_smu = dcn21_pp_smu_create(ctx); >+ >+ dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); >+ >+ init_data.ctx = dc->ctx; >+ pool->base.irqs = dal_irq_service_dcn21_create(&init_data); >+ if (!pool->base.irqs) >+ goto create_fail; >+ >+ /* mem input -> ipp -> dpp -> opp -> TG */ >+ for (i = 0; i < pool->base.pipe_count; i++) { >+ pool->base.hubps[i] = dcn21_hubp_create(ctx, i); >+ if (pool->base.hubps[i] == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error( >+ "DC: failed to create memory input!\n"); >+ goto create_fail; >+ } >+ >+ pool->base.ipps[i] = dcn21_ipp_create(ctx, i); >+ if (pool->base.ipps[i] == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error( >+ "DC: failed to create input pixel processor!\n"); >+ goto create_fail; >+ } >+ >+ pool->base.dpps[i] = dcn21_dpp_create(ctx, i); >+ if (pool->base.dpps[i] == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error( >+ "DC: failed to create dpps!\n"); >+ goto create_fail; >+ } >+ } >+ >+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) { >+ pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); >+ if (pool->base.engines[i] == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error( >+ "DC:failed to create aux engine!!\n"); >+ goto create_fail; >+ } >+ pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); >+ if (pool->base.hw_i2cs[i] == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error( >+ "DC:failed to create hw i2c!!\n"); >+ goto create_fail; >+ } >+ pool->base.sw_i2cs[i] = NULL; >+ } >+ >+ for (i = 0; i < pool->base.res_cap->num_opp; i++) { >+ pool->base.opps[i] = dcn21_opp_create(ctx, i); >+ if (pool->base.opps[i] == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error( >+ "DC: failed to create output pixel processor!\n"); >+ goto create_fail; >+ } >+ } >+ >+ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { >+ pool->base.timing_generators[i] = dcn21_timing_generator_create( >+ ctx, i); >+ if (pool->base.timing_generators[i] == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error("DC: failed to create tg!\n"); >+ goto create_fail; >+ } >+ } >+ >+ pool->base.timing_generator_count = i; >+ >+ pool->base.mpc = dcn21_mpc_create(ctx); >+ if (pool->base.mpc == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error("DC: failed to create mpc!\n"); >+ goto create_fail; >+ } >+ >+ pool->base.hubbub = dcn21_hubbub_create(ctx); >+ if (pool->base.hubbub == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error("DC: failed to create hubbub!\n"); >+ goto create_fail; >+ } >+ >+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { >+ pool->base.dscs[i] = dcn21_dsc_create(ctx, i); >+ if (pool->base.dscs[i] == NULL) { >+ BREAK_TO_DEBUGGER(); >+ dm_error("DC: failed to create display stream compressor %d!\n", i); >+ goto create_fail; >+ } >+ } >+#endif >+ >+ if (!dcn20_dwbc_create(ctx, &pool->base)) { >+ BREAK_TO_DEBUGGER(); >+ dm_error("DC: failed to create dwbc!\n"); >+ goto create_fail; >+ } >+ if (!dcn20_mmhubbub_create(ctx, &pool->base)) { >+ BREAK_TO_DEBUGGER(); >+ dm_error("DC: failed to create mcif_wb!\n"); >+ goto create_fail; >+ } >+ >+ if (!resource_construct(num_virtual_links, dc, &pool->base, >+ (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? >+ &res_create_funcs : &res_create_maximus_funcs))) >+ goto create_fail; >+ >+ dcn20_hw_sequencer_construct(dc); >+ >+ dc->caps.max_planes = pool->base.pipe_count; >+ >+ for (i = 0; i < dc->caps.max_planes; ++i) >+ dc->caps.planes[i] = plane_cap; >+ >+ dc->cap_funcs = cap_funcs; >+ >+ return true; >+ >+create_fail: >+ >+ destruct(pool); >+ >+ return false; >+} >+ >+struct resource_pool *dcn21_create_resource_pool( >+ const struct dc_init_data *init_data, >+ struct dc *dc) >+{ >+ struct dcn21_resource_pool *pool = >+ kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); >+ >+ if (!pool) >+ return NULL; >+ >+ if (construct(init_data->num_virtual_links, dc, pool)) >+ return &pool->base; >+ >+ BREAK_TO_DEBUGGER(); >+ kfree(pool); >+ return NULL; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h 2019-08-31 15:01:11.867736169 -0500 >@@ -0,0 +1,45 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef _DCN21_RESOURCE_H_ >+#define _DCN21_RESOURCE_H_ >+ >+#include "core_types.h" >+ >+#define TO_DCN21_RES_POOL(pool)\ >+ container_of(pool, struct dcn21_resource_pool, base) >+ >+struct dc; >+struct resource_pool; >+struct _vcs_dpi_display_pipe_params_st; >+ >+struct dcn21_resource_pool { >+ struct resource_pool base; >+}; >+struct resource_pool *dcn21_create_resource_pool( >+ const struct dc_init_data *init_data, >+ struct dc *dc); >+ >+#endif /* _DCN21_RESOURCE_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/Makefile 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/Makefile 2019-08-31 15:01:11.866736169 -0500 >@@ -0,0 +1,10 @@ >+# >+# Makefile for DCN21. >+ >+DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o >+ >+CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4 >+ >+AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21)) >+ >+AMD_DISPLAY_FILES += $(AMD_DAL_DCN21) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_types.h 2019-08-31 15:01:11.859736168 -0500 >@@ -202,6 +202,7 @@ > unsigned int dppowerup_delay; > unsigned int extra_t12_ms; > unsigned int extra_delay_backlight_off; >+ unsigned int extra_t7_ms; > }; > > struct dc_edid_caps { >@@ -725,6 +726,19 @@ > unsigned int phyClock; > }; > >+ >+enum dc_clock_type { >+ DC_CLOCK_TYPE_DISPCLK = 0, >+ DC_CLOCK_TYPE_DPPCLK = 1, >+}; >+ >+struct dc_clock_config { >+ uint32_t max_clock_khz; >+ uint32_t min_clock_khz; >+ uint32_t bw_requirequired_clock_khz; >+ uint32_t current_clock_khz;/*current clock in use*/ >+}; >+ > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > /* DSC DPCD capabilities */ > union dsc_slice_caps1 { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 2019-08-31 15:01:11.867736169 -0500 >@@ -0,0 +1,5136 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#include "../display_mode_lib.h" >+#include "display_mode_vba_20v2.h" >+#include "../dml_inline_defs.h" >+ >+/* >+ * NOTE: >+ * This file is gcc-parseable HW gospel, coming straight from HW engineers. >+ * >+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd >+ * ways. Unless there is something clearly wrong with it the code should >+ * remain as-is as it provides us with a guarantee from HW that it is correct. >+ */ >+ >+#define BPP_INVALID 0 >+#define BPP_BLENDED_PIPE 0xffffffff >+ >+static double adjust_ReturnBW( >+ struct display_mode_lib *mode_lib, >+ double ReturnBW, >+ bool DCCEnabledAnyPlane, >+ double ReturnBandwidthToDCN); >+static unsigned int dscceComputeDelay( >+ unsigned int bpc, >+ double bpp, >+ unsigned int sliceWidth, >+ unsigned int numSlices, >+ enum output_format_class pixelFormat); >+static unsigned int dscComputeDelay(enum output_format_class pixelFormat); >+static bool CalculateDelayAfterScaler( >+ struct display_mode_lib *mode_lib, >+ double ReturnBW, >+ double ReadBandwidthPlaneLuma, >+ double ReadBandwidthPlaneChroma, >+ double TotalDataReadBandwidth, >+ double DisplayPipeLineDeliveryTimeLuma, >+ double DisplayPipeLineDeliveryTimeChroma, >+ double DPPCLK, >+ double DISPCLK, >+ double PixelClock, >+ unsigned int DSCDelay, >+ unsigned int DPPPerPlane, >+ bool ScalerEnabled, >+ unsigned int NumberOfCursors, >+ double DPPCLKDelaySubtotal, >+ double DPPCLKDelaySCL, >+ double DPPCLKDelaySCLLBOnly, >+ double DPPCLKDelayCNVCFormater, >+ double DPPCLKDelayCNVCCursor, >+ double DISPCLKDelaySubtotal, >+ unsigned int ScalerRecoutWidth, >+ enum output_format_class OutputFormat, >+ unsigned int HTotal, >+ unsigned int SwathWidthSingleDPPY, >+ double BytePerPixelDETY, >+ double BytePerPixelDETC, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ bool Interlace, >+ bool ProgressiveToInterlaceUnitInOPP, >+ double *DSTXAfterScaler, >+ double *DSTYAfterScaler >+ ); >+// Super monster function with some 45 argument >+static bool CalculatePrefetchSchedule( >+ struct display_mode_lib *mode_lib, >+ double DPPCLK, >+ double DISPCLK, >+ double PixelClock, >+ double DCFCLKDeepSleep, >+ unsigned int DPPPerPlane, >+ unsigned int NumberOfCursors, >+ unsigned int VBlank, >+ unsigned int HTotal, >+ unsigned int MaxInterDCNTileRepeaters, >+ unsigned int VStartup, >+ unsigned int PageTableLevels, >+ bool GPUVMEnable, >+ bool DynamicMetadataEnable, >+ unsigned int DynamicMetadataLinesBeforeActiveRequired, >+ unsigned int DynamicMetadataTransmittedBytes, >+ bool DCCEnable, >+ double UrgentLatencyPixelDataOnly, >+ double UrgentExtraLatency, >+ double TCalc, >+ unsigned int PDEAndMetaPTEBytesFrame, >+ unsigned int MetaRowByte, >+ unsigned int PixelPTEBytesPerRow, >+ double PrefetchSourceLinesY, >+ unsigned int SwathWidthY, >+ double BytePerPixelDETY, >+ double VInitPreFillY, >+ unsigned int MaxNumSwathY, >+ double PrefetchSourceLinesC, >+ double BytePerPixelDETC, >+ double VInitPreFillC, >+ unsigned int MaxNumSwathC, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ double TWait, >+ bool XFCEnabled, >+ double XFCRemoteSurfaceFlipDelay, >+ bool InterlaceEnable, >+ bool ProgressiveToInterlaceUnitInOPP, >+ double DSTXAfterScaler, >+ double DSTYAfterScaler, >+ double *DestinationLinesForPrefetch, >+ double *PrefetchBandwidth, >+ double *DestinationLinesToRequestVMInVBlank, >+ double *DestinationLinesToRequestRowInVBlank, >+ double *VRatioPrefetchY, >+ double *VRatioPrefetchC, >+ double *RequiredPrefetchPixDataBW, >+ double *Tno_bw, >+ unsigned int *VUpdateOffsetPix, >+ double *VUpdateWidthPix, >+ double *VReadyOffsetPix); >+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); >+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed); >+static double CalculatePrefetchSourceLines( >+ struct display_mode_lib *mode_lib, >+ double VRatio, >+ double vtaps, >+ bool Interlace, >+ bool ProgressiveToInterlaceUnitInOPP, >+ unsigned int SwathHeight, >+ unsigned int ViewportYStart, >+ double *VInitPreFill, >+ unsigned int *MaxNumSwath); >+static unsigned int CalculateVMAndRowBytes( >+ struct display_mode_lib *mode_lib, >+ bool DCCEnable, >+ unsigned int BlockHeight256Bytes, >+ unsigned int BlockWidth256Bytes, >+ enum source_format_class SourcePixelFormat, >+ unsigned int SurfaceTiling, >+ unsigned int BytePerPixel, >+ enum scan_direction_class ScanDirection, >+ unsigned int ViewportWidth, >+ unsigned int ViewportHeight, >+ unsigned int SwathWidthY, >+ bool GPUVMEnable, >+ unsigned int VMMPageSize, >+ unsigned int PTEBufferSizeInRequestsLuma, >+ unsigned int PDEProcessingBufIn64KBReqs, >+ unsigned int Pitch, >+ unsigned int DCCMetaPitch, >+ unsigned int *MacroTileWidth, >+ unsigned int *MetaRowByte, >+ unsigned int *PixelPTEBytesPerRow, >+ bool *PTEBufferSizeNotExceeded, >+ unsigned int *dpte_row_height, >+ unsigned int *meta_row_height); >+static double CalculateTWait( >+ unsigned int PrefetchMode, >+ double DRAMClockChangeLatency, >+ double UrgentLatencyPixelDataOnly, >+ double SREnterPlusExitTime); >+static double CalculateRemoteSurfaceFlipDelay( >+ struct display_mode_lib *mode_lib, >+ double VRatio, >+ double SwathWidth, >+ double Bpp, >+ double LineTime, >+ double XFCTSlvVupdateOffset, >+ double XFCTSlvVupdateWidth, >+ double XFCTSlvVreadyOffset, >+ double XFCXBUFLatencyTolerance, >+ double XFCFillBWOverhead, >+ double XFCSlvChunkSize, >+ double XFCBusTransportTime, >+ double TCalc, >+ double TWait, >+ double *SrcActiveDrainRate, >+ double *TInitXFill, >+ double *TslvChk); >+static void CalculateActiveRowBandwidth( >+ bool GPUVMEnable, >+ enum source_format_class SourcePixelFormat, >+ double VRatio, >+ bool DCCEnable, >+ double LineTime, >+ unsigned int MetaRowByteLuma, >+ unsigned int MetaRowByteChroma, >+ unsigned int meta_row_height_luma, >+ unsigned int meta_row_height_chroma, >+ unsigned int PixelPTEBytesPerRowLuma, >+ unsigned int PixelPTEBytesPerRowChroma, >+ unsigned int dpte_row_height_luma, >+ unsigned int dpte_row_height_chroma, >+ double *meta_row_bw, >+ double *dpte_row_bw, >+ double *qual_row_bw); >+static void CalculateFlipSchedule( >+ struct display_mode_lib *mode_lib, >+ double UrgentExtraLatency, >+ double UrgentLatencyPixelDataOnly, >+ unsigned int GPUVMMaxPageTableLevels, >+ bool GPUVMEnable, >+ double BandwidthAvailableForImmediateFlip, >+ unsigned int TotImmediateFlipBytes, >+ enum source_format_class SourcePixelFormat, >+ unsigned int ImmediateFlipBytes, >+ double LineTime, >+ double VRatio, >+ double Tno_bw, >+ double PDEAndMetaPTEBytesFrame, >+ unsigned int MetaRowByte, >+ unsigned int PixelPTEBytesPerRow, >+ bool DCCEnable, >+ unsigned int dpte_row_height, >+ unsigned int meta_row_height, >+ double qual_row_bw, >+ double *DestinationLinesToRequestVMInImmediateFlip, >+ double *DestinationLinesToRequestRowInImmediateFlip, >+ double *final_flip_bw, >+ bool *ImmediateFlipSupportedForPipe); >+static double CalculateWriteBackDelay( >+ enum source_format_class WritebackPixelFormat, >+ double WritebackHRatio, >+ double WritebackVRatio, >+ unsigned int WritebackLumaHTaps, >+ unsigned int WritebackLumaVTaps, >+ unsigned int WritebackChromaHTaps, >+ unsigned int WritebackChromaVTaps, >+ unsigned int WritebackDestinationWidth); >+ >+static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib); >+static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation( >+ struct display_mode_lib *mode_lib); >+ >+void dml20v2_recalculate(struct display_mode_lib *mode_lib) >+{ >+ ModeSupportAndSystemConfiguration(mode_lib); >+ mode_lib->vba.FabricAndDRAMBandwidth = dml_min( >+ mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, >+ mode_lib->vba.FabricClock * mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000.0; >+ PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib); >+ dml20v2_DisplayPipeConfiguration(mode_lib); >+ dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib); >+} >+ >+static double adjust_ReturnBW( >+ struct display_mode_lib *mode_lib, >+ double ReturnBW, >+ bool DCCEnabledAnyPlane, >+ double ReturnBandwidthToDCN) >+{ >+ double CriticalCompression; >+ >+ if (DCCEnabledAnyPlane >+ && ReturnBandwidthToDCN >+ > mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0) >+ ReturnBW = >+ dml_min( >+ ReturnBW, >+ ReturnBandwidthToDCN * 4 >+ * (1.0 >+ - mode_lib->vba.UrgentLatencyPixelDataOnly >+ / ((mode_lib->vba.ROBBufferSizeInKByte >+ - mode_lib->vba.PixelChunkSizeInKByte) >+ * 1024 >+ / ReturnBandwidthToDCN >+ - mode_lib->vba.DCFCLK >+ * mode_lib->vba.ReturnBusWidth >+ / 4) >+ + mode_lib->vba.UrgentLatencyPixelDataOnly)); >+ >+ CriticalCompression = 2.0 * mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK >+ * mode_lib->vba.UrgentLatencyPixelDataOnly >+ / (ReturnBandwidthToDCN * mode_lib->vba.UrgentLatencyPixelDataOnly >+ + (mode_lib->vba.ROBBufferSizeInKByte >+ - mode_lib->vba.PixelChunkSizeInKByte) >+ * 1024); >+ >+ if (DCCEnabledAnyPlane && CriticalCompression > 1.0 && CriticalCompression < 4.0) >+ ReturnBW = >+ dml_min( >+ ReturnBW, >+ 4.0 * ReturnBandwidthToDCN >+ * (mode_lib->vba.ROBBufferSizeInKByte >+ - mode_lib->vba.PixelChunkSizeInKByte) >+ * 1024 >+ * mode_lib->vba.ReturnBusWidth >+ * mode_lib->vba.DCFCLK >+ * mode_lib->vba.UrgentLatencyPixelDataOnly >+ / dml_pow( >+ (ReturnBandwidthToDCN >+ * mode_lib->vba.UrgentLatencyPixelDataOnly >+ + (mode_lib->vba.ROBBufferSizeInKByte >+ - mode_lib->vba.PixelChunkSizeInKByte) >+ * 1024), >+ 2)); >+ >+ return ReturnBW; >+} >+ >+static unsigned int dscceComputeDelay( >+ unsigned int bpc, >+ double bpp, >+ unsigned int sliceWidth, >+ unsigned int numSlices, >+ enum output_format_class pixelFormat) >+{ >+ // valid bpc = source bits per component in the set of {8, 10, 12} >+ // valid bpp = increments of 1/16 of a bit >+ // min = 6/7/8 in N420/N422/444, respectively >+ // max = such that compression is 1:1 >+ //valid sliceWidth = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode) >+ //valid numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} >+ //valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420} >+ >+ // fixed value >+ unsigned int rcModelSize = 8192; >+ >+ // N422/N420 operate at 2 pixels per clock >+ unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, l, >+ Delay, pixels; >+ >+ if (pixelFormat == dm_n422 || pixelFormat == dm_420) >+ pixelsPerClock = 2; >+ // #all other modes operate at 1 pixel per clock >+ else >+ pixelsPerClock = 1; >+ >+ //initial transmit delay as per PPS >+ initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); >+ >+ //compute ssm delay >+ if (bpc == 8) >+ D = 81; >+ else if (bpc == 10) >+ D = 89; >+ else >+ D = 113; >+ >+ //divide by pixel per cycle to compute slice width as seen by DSC >+ w = sliceWidth / pixelsPerClock; >+ >+ //422 mode has an additional cycle of delay >+ if (pixelFormat == dm_s422) >+ s = 1; >+ else >+ s = 0; >+ >+ //main calculation for the dscce >+ ix = initalXmitDelay + 45; >+ wx = (w + 2) / 3; >+ p = 3 * wx - w; >+ l0 = ix / w; >+ a = ix + p * l0; >+ ax = (a + 2) / 3 + D + 6 + 1; >+ l = (ax + wx - 1) / wx; >+ if ((ix % w) == 0 && p != 0) >+ lstall = 1; >+ else >+ lstall = 0; >+ Delay = l * wx * (numSlices - 1) + ax + s + lstall + 22; >+ >+ //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels >+ pixels = Delay * 3 * pixelsPerClock; >+ return pixels; >+} >+ >+static unsigned int dscComputeDelay(enum output_format_class pixelFormat) >+{ >+ unsigned int Delay = 0; >+ >+ if (pixelFormat == dm_420) { >+ // sfr >+ Delay = Delay + 2; >+ // dsccif >+ Delay = Delay + 0; >+ // dscc - input deserializer >+ Delay = Delay + 3; >+ // dscc gets pixels every other cycle >+ Delay = Delay + 2; >+ // dscc - input cdc fifo >+ Delay = Delay + 12; >+ // dscc gets pixels every other cycle >+ Delay = Delay + 13; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output cdc fifo >+ Delay = Delay + 7; >+ // dscc gets pixels every other cycle >+ Delay = Delay + 3; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output serializer >+ Delay = Delay + 1; >+ // sft >+ Delay = Delay + 1; >+ } else if (pixelFormat == dm_n422) { >+ // sfr >+ Delay = Delay + 2; >+ // dsccif >+ Delay = Delay + 1; >+ // dscc - input deserializer >+ Delay = Delay + 5; >+ // dscc - input cdc fifo >+ Delay = Delay + 25; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output cdc fifo >+ Delay = Delay + 10; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output serializer >+ Delay = Delay + 1; >+ // sft >+ Delay = Delay + 1; >+ } else { >+ // sfr >+ Delay = Delay + 2; >+ // dsccif >+ Delay = Delay + 0; >+ // dscc - input deserializer >+ Delay = Delay + 3; >+ // dscc - input cdc fifo >+ Delay = Delay + 12; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output cdc fifo >+ Delay = Delay + 7; >+ // dscc - output serializer >+ Delay = Delay + 1; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // sft >+ Delay = Delay + 1; >+ } >+ >+ return Delay; >+} >+ >+static bool CalculateDelayAfterScaler( >+ struct display_mode_lib *mode_lib, >+ double ReturnBW, >+ double ReadBandwidthPlaneLuma, >+ double ReadBandwidthPlaneChroma, >+ double TotalDataReadBandwidth, >+ double DisplayPipeLineDeliveryTimeLuma, >+ double DisplayPipeLineDeliveryTimeChroma, >+ double DPPCLK, >+ double DISPCLK, >+ double PixelClock, >+ unsigned int DSCDelay, >+ unsigned int DPPPerPlane, >+ bool ScalerEnabled, >+ unsigned int NumberOfCursors, >+ double DPPCLKDelaySubtotal, >+ double DPPCLKDelaySCL, >+ double DPPCLKDelaySCLLBOnly, >+ double DPPCLKDelayCNVCFormater, >+ double DPPCLKDelayCNVCCursor, >+ double DISPCLKDelaySubtotal, >+ unsigned int ScalerRecoutWidth, >+ enum output_format_class OutputFormat, >+ unsigned int HTotal, >+ unsigned int SwathWidthSingleDPPY, >+ double BytePerPixelDETY, >+ double BytePerPixelDETC, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ bool Interlace, >+ bool ProgressiveToInterlaceUnitInOPP, >+ double *DSTXAfterScaler, >+ double *DSTYAfterScaler >+ ) >+{ >+ unsigned int DPPCycles, DISPCLKCycles; >+ double DataFabricLineDeliveryTimeLuma; >+ double DataFabricLineDeliveryTimeChroma; >+ double DSTTotalPixelsAfterScaler; >+ >+ DataFabricLineDeliveryTimeLuma = SwathWidthSingleDPPY * SwathHeightY * dml_ceil(BytePerPixelDETY, 1) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneLuma / TotalDataReadBandwidth); >+ mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(mode_lib->vba.LastPixelOfLineExtraWatermark, DataFabricLineDeliveryTimeLuma - DisplayPipeLineDeliveryTimeLuma); >+ >+ if (BytePerPixelDETC != 0) { >+ DataFabricLineDeliveryTimeChroma = SwathWidthSingleDPPY / 2 * SwathHeightC * dml_ceil(BytePerPixelDETC, 2) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneChroma / TotalDataReadBandwidth); >+ mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(mode_lib->vba.LastPixelOfLineExtraWatermark, DataFabricLineDeliveryTimeChroma - DisplayPipeLineDeliveryTimeChroma); >+ } >+ >+ if (ScalerEnabled) >+ DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL; >+ else >+ DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly; >+ >+ DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor; >+ >+ DISPCLKCycles = DISPCLKDelaySubtotal; >+ >+ if (DPPCLK == 0.0 || DISPCLK == 0.0) >+ return true; >+ >+ *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK >+ + DSCDelay; >+ >+ if (DPPPerPlane > 1) >+ *DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth; >+ >+ if (OutputFormat == dm_420 || (Interlace && ProgressiveToInterlaceUnitInOPP)) >+ *DSTYAfterScaler = 1; >+ else >+ *DSTYAfterScaler = 0; >+ >+ DSTTotalPixelsAfterScaler = ((double) (*DSTYAfterScaler * HTotal)) + *DSTXAfterScaler; >+ *DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / HTotal, 1); >+ *DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * HTotal)); >+ >+ return true; >+} >+ >+static bool CalculatePrefetchSchedule( >+ struct display_mode_lib *mode_lib, >+ double DPPCLK, >+ double DISPCLK, >+ double PixelClock, >+ double DCFCLKDeepSleep, >+ unsigned int DPPPerPlane, >+ unsigned int NumberOfCursors, >+ unsigned int VBlank, >+ unsigned int HTotal, >+ unsigned int MaxInterDCNTileRepeaters, >+ unsigned int VStartup, >+ unsigned int PageTableLevels, >+ bool GPUVMEnable, >+ bool DynamicMetadataEnable, >+ unsigned int DynamicMetadataLinesBeforeActiveRequired, >+ unsigned int DynamicMetadataTransmittedBytes, >+ bool DCCEnable, >+ double UrgentLatencyPixelDataOnly, >+ double UrgentExtraLatency, >+ double TCalc, >+ unsigned int PDEAndMetaPTEBytesFrame, >+ unsigned int MetaRowByte, >+ unsigned int PixelPTEBytesPerRow, >+ double PrefetchSourceLinesY, >+ unsigned int SwathWidthY, >+ double BytePerPixelDETY, >+ double VInitPreFillY, >+ unsigned int MaxNumSwathY, >+ double PrefetchSourceLinesC, >+ double BytePerPixelDETC, >+ double VInitPreFillC, >+ unsigned int MaxNumSwathC, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ double TWait, >+ bool XFCEnabled, >+ double XFCRemoteSurfaceFlipDelay, >+ bool InterlaceEnable, >+ bool ProgressiveToInterlaceUnitInOPP, >+ double DSTXAfterScaler, >+ double DSTYAfterScaler, >+ double *DestinationLinesForPrefetch, >+ double *PrefetchBandwidth, >+ double *DestinationLinesToRequestVMInVBlank, >+ double *DestinationLinesToRequestRowInVBlank, >+ double *VRatioPrefetchY, >+ double *VRatioPrefetchC, >+ double *RequiredPrefetchPixDataBW, >+ double *Tno_bw, >+ unsigned int *VUpdateOffsetPix, >+ double *VUpdateWidthPix, >+ double *VReadyOffsetPix) >+{ >+ bool MyError = false; >+ double TotalRepeaterDelayTime; >+ double Tdm, LineTime, Tsetup; >+ double dst_y_prefetch_equ; >+ double Tsw_oto; >+ double prefetch_bw_oto; >+ double Tvm_oto; >+ double Tr0_oto; >+ double Tpre_oto; >+ double dst_y_prefetch_oto; >+ double TimeForFetchingMetaPTE = 0; >+ double TimeForFetchingRowInVBlank = 0; >+ double LinesToRequestPrefetchPixelData = 0; >+ >+ *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); >+ TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); >+ *VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) >+ * PixelClock; >+ >+ *VReadyOffsetPix = dml_max( >+ 150.0 / DPPCLK, >+ TotalRepeaterDelayTime + 20.0 / DCFCLKDeepSleep + 10.0 / DPPCLK) >+ * PixelClock; >+ >+ Tsetup = (double) (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; >+ >+ LineTime = (double) HTotal / PixelClock; >+ >+ if (DynamicMetadataEnable) { >+ double Tdmbf, Tdmec, Tdmsks; >+ >+ Tdm = dml_max(0.0, UrgentExtraLatency - TCalc); >+ Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; >+ Tdmec = LineTime; >+ if (DynamicMetadataLinesBeforeActiveRequired == 0) >+ Tdmsks = VBlank * LineTime / 2.0; >+ else >+ Tdmsks = DynamicMetadataLinesBeforeActiveRequired * LineTime; >+ if (InterlaceEnable && !ProgressiveToInterlaceUnitInOPP) >+ Tdmsks = Tdmsks / 2; >+ if (VStartup * LineTime >+ < Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) { >+ MyError = true; >+ } >+ } else >+ Tdm = 0; >+ >+ if (GPUVMEnable) { >+ if (PageTableLevels == 4) >+ *Tno_bw = UrgentExtraLatency + UrgentLatencyPixelDataOnly; >+ else if (PageTableLevels == 3) >+ *Tno_bw = UrgentExtraLatency; >+ else >+ *Tno_bw = 0; >+ } else if (DCCEnable) >+ *Tno_bw = LineTime; >+ else >+ *Tno_bw = LineTime / 4; >+ >+ dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime >+ - (Tsetup + Tdm) / LineTime >+ - (DSTYAfterScaler + DSTXAfterScaler / HTotal); >+ >+ Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime; >+ >+ prefetch_bw_oto = (MetaRowByte + PixelPTEBytesPerRow >+ + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1) >+ + PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2)) >+ / Tsw_oto; >+ >+ if (GPUVMEnable == true) { >+ Tvm_oto = >+ dml_max( >+ *Tno_bw + PDEAndMetaPTEBytesFrame / prefetch_bw_oto, >+ dml_max( >+ UrgentExtraLatency >+ + UrgentLatencyPixelDataOnly >+ * (PageTableLevels >+ - 1), >+ LineTime / 4.0)); >+ } else >+ Tvm_oto = LineTime / 4.0; >+ >+ if ((GPUVMEnable == true || DCCEnable == true)) { >+ Tr0_oto = dml_max( >+ (MetaRowByte + PixelPTEBytesPerRow) / prefetch_bw_oto, >+ dml_max(UrgentLatencyPixelDataOnly, dml_max(LineTime - Tvm_oto, LineTime / 4))); >+ } else >+ Tr0_oto = LineTime - Tvm_oto; >+ >+ Tpre_oto = Tvm_oto + Tr0_oto + Tsw_oto; >+ >+ dst_y_prefetch_oto = Tpre_oto / LineTime; >+ >+ if (dst_y_prefetch_oto < dst_y_prefetch_equ) >+ *DestinationLinesForPrefetch = dst_y_prefetch_oto; >+ else >+ *DestinationLinesForPrefetch = dst_y_prefetch_equ; >+ >+ *DestinationLinesForPrefetch = dml_floor(4.0 * (*DestinationLinesForPrefetch + 0.125), 1) >+ / 4; >+ >+ dml_print("DML: VStartup: %d\n", VStartup); >+ dml_print("DML: TCalc: %f\n", TCalc); >+ dml_print("DML: TWait: %f\n", TWait); >+ dml_print("DML: XFCRemoteSurfaceFlipDelay: %f\n", XFCRemoteSurfaceFlipDelay); >+ dml_print("DML: LineTime: %f\n", LineTime); >+ dml_print("DML: Tsetup: %f\n", Tsetup); >+ dml_print("DML: Tdm: %f\n", Tdm); >+ dml_print("DML: DSTYAfterScaler: %f\n", DSTYAfterScaler); >+ dml_print("DML: DSTXAfterScaler: %f\n", DSTXAfterScaler); >+ dml_print("DML: HTotal: %d\n", HTotal); >+ >+ *PrefetchBandwidth = 0; >+ *DestinationLinesToRequestVMInVBlank = 0; >+ *DestinationLinesToRequestRowInVBlank = 0; >+ *VRatioPrefetchY = 0; >+ *VRatioPrefetchC = 0; >+ *RequiredPrefetchPixDataBW = 0; >+ if (*DestinationLinesForPrefetch > 1) { >+ *PrefetchBandwidth = (PDEAndMetaPTEBytesFrame + 2 * MetaRowByte >+ + 2 * PixelPTEBytesPerRow >+ + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1) >+ + PrefetchSourceLinesC * SwathWidthY / 2 >+ * dml_ceil(BytePerPixelDETC, 2)) >+ / (*DestinationLinesForPrefetch * LineTime - *Tno_bw); >+ if (GPUVMEnable) { >+ TimeForFetchingMetaPTE = >+ dml_max( >+ *Tno_bw >+ + (double) PDEAndMetaPTEBytesFrame >+ / *PrefetchBandwidth, >+ dml_max( >+ UrgentExtraLatency >+ + UrgentLatencyPixelDataOnly >+ * (PageTableLevels >+ - 1), >+ LineTime / 4)); >+ } else { >+ if (NumberOfCursors > 0 || XFCEnabled) >+ TimeForFetchingMetaPTE = LineTime / 4; >+ else >+ TimeForFetchingMetaPTE = 0.0; >+ } >+ >+ if ((GPUVMEnable == true || DCCEnable == true)) { >+ TimeForFetchingRowInVBlank = >+ dml_max( >+ (MetaRowByte + PixelPTEBytesPerRow) >+ / *PrefetchBandwidth, >+ dml_max( >+ UrgentLatencyPixelDataOnly, >+ dml_max( >+ LineTime >+ - TimeForFetchingMetaPTE, >+ LineTime >+ / 4.0))); >+ } else { >+ if (NumberOfCursors > 0 || XFCEnabled) >+ TimeForFetchingRowInVBlank = LineTime - TimeForFetchingMetaPTE; >+ else >+ TimeForFetchingRowInVBlank = 0.0; >+ } >+ >+ *DestinationLinesToRequestVMInVBlank = dml_floor( >+ 4.0 * (TimeForFetchingMetaPTE / LineTime + 0.125), >+ 1) / 4.0; >+ >+ *DestinationLinesToRequestRowInVBlank = dml_floor( >+ 4.0 * (TimeForFetchingRowInVBlank / LineTime + 0.125), >+ 1) / 4.0; >+ >+ LinesToRequestPrefetchPixelData = >+ *DestinationLinesForPrefetch >+ - ((NumberOfCursors > 0 || GPUVMEnable >+ || DCCEnable) ? >+ (*DestinationLinesToRequestVMInVBlank >+ + *DestinationLinesToRequestRowInVBlank) : >+ 0.0); >+ >+ if (LinesToRequestPrefetchPixelData > 0) { >+ >+ *VRatioPrefetchY = (double) PrefetchSourceLinesY >+ / LinesToRequestPrefetchPixelData; >+ *VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0); >+ if ((SwathHeightY > 4) && (VInitPreFillY > 3)) { >+ if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) { >+ *VRatioPrefetchY = >+ dml_max( >+ (double) PrefetchSourceLinesY >+ / LinesToRequestPrefetchPixelData, >+ (double) MaxNumSwathY >+ * SwathHeightY >+ / (LinesToRequestPrefetchPixelData >+ - (VInitPreFillY >+ - 3.0) >+ / 2.0)); >+ *VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0); >+ } else { >+ MyError = true; >+ *VRatioPrefetchY = 0; >+ } >+ } >+ >+ *VRatioPrefetchC = (double) PrefetchSourceLinesC >+ / LinesToRequestPrefetchPixelData; >+ *VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0); >+ >+ if ((SwathHeightC > 4)) { >+ if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) { >+ *VRatioPrefetchC = >+ dml_max( >+ *VRatioPrefetchC, >+ (double) MaxNumSwathC >+ * SwathHeightC >+ / (LinesToRequestPrefetchPixelData >+ - (VInitPreFillC >+ - 3.0) >+ / 2.0)); >+ *VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0); >+ } else { >+ MyError = true; >+ *VRatioPrefetchC = 0; >+ } >+ } >+ >+ *RequiredPrefetchPixDataBW = >+ DPPPerPlane >+ * ((double) PrefetchSourceLinesY >+ / LinesToRequestPrefetchPixelData >+ * dml_ceil( >+ BytePerPixelDETY, >+ 1) >+ + (double) PrefetchSourceLinesC >+ / LinesToRequestPrefetchPixelData >+ * dml_ceil( >+ BytePerPixelDETC, >+ 2) >+ / 2) >+ * SwathWidthY / LineTime; >+ } else { >+ MyError = true; >+ *VRatioPrefetchY = 0; >+ *VRatioPrefetchC = 0; >+ *RequiredPrefetchPixDataBW = 0; >+ } >+ >+ } else { >+ MyError = true; >+ } >+ >+ if (MyError) { >+ *PrefetchBandwidth = 0; >+ TimeForFetchingMetaPTE = 0; >+ TimeForFetchingRowInVBlank = 0; >+ *DestinationLinesToRequestVMInVBlank = 0; >+ *DestinationLinesToRequestRowInVBlank = 0; >+ *DestinationLinesForPrefetch = 0; >+ LinesToRequestPrefetchPixelData = 0; >+ *VRatioPrefetchY = 0; >+ *VRatioPrefetchC = 0; >+ *RequiredPrefetchPixDataBW = 0; >+ } >+ >+ return MyError; >+} >+ >+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed) >+{ >+ return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1); >+} >+ >+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed) >+{ >+ return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1); >+} >+ >+static double CalculatePrefetchSourceLines( >+ struct display_mode_lib *mode_lib, >+ double VRatio, >+ double vtaps, >+ bool Interlace, >+ bool ProgressiveToInterlaceUnitInOPP, >+ unsigned int SwathHeight, >+ unsigned int ViewportYStart, >+ double *VInitPreFill, >+ unsigned int *MaxNumSwath) >+{ >+ unsigned int MaxPartialSwath; >+ >+ if (ProgressiveToInterlaceUnitInOPP) >+ *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); >+ else >+ *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); >+ >+ if (!mode_lib->vba.IgnoreViewportPositioning) { >+ >+ *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; >+ >+ if (*VInitPreFill > 1.0) >+ MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; >+ else >+ MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) >+ % SwathHeight; >+ MaxPartialSwath = dml_max(1U, MaxPartialSwath); >+ >+ } else { >+ >+ if (ViewportYStart != 0) >+ dml_print( >+ "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); >+ >+ *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); >+ >+ if (*VInitPreFill > 1.0) >+ MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; >+ else >+ MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) >+ % SwathHeight; >+ } >+ >+ return *MaxNumSwath * SwathHeight + MaxPartialSwath; >+} >+ >+static unsigned int CalculateVMAndRowBytes( >+ struct display_mode_lib *mode_lib, >+ bool DCCEnable, >+ unsigned int BlockHeight256Bytes, >+ unsigned int BlockWidth256Bytes, >+ enum source_format_class SourcePixelFormat, >+ unsigned int SurfaceTiling, >+ unsigned int BytePerPixel, >+ enum scan_direction_class ScanDirection, >+ unsigned int ViewportWidth, >+ unsigned int ViewportHeight, >+ unsigned int SwathWidth, >+ bool GPUVMEnable, >+ unsigned int VMMPageSize, >+ unsigned int PTEBufferSizeInRequestsLuma, >+ unsigned int PDEProcessingBufIn64KBReqs, >+ unsigned int Pitch, >+ unsigned int DCCMetaPitch, >+ unsigned int *MacroTileWidth, >+ unsigned int *MetaRowByte, >+ unsigned int *PixelPTEBytesPerRow, >+ bool *PTEBufferSizeNotExceeded, >+ unsigned int *dpte_row_height, >+ unsigned int *meta_row_height) >+{ >+ unsigned int MetaRequestHeight; >+ unsigned int MetaRequestWidth; >+ unsigned int MetaSurfWidth; >+ unsigned int MetaSurfHeight; >+ unsigned int MPDEBytesFrame; >+ unsigned int MetaPTEBytesFrame; >+ unsigned int DCCMetaSurfaceBytes; >+ >+ unsigned int MacroTileSizeBytes; >+ unsigned int MacroTileHeight; >+ unsigned int DPDE0BytesFrame; >+ unsigned int ExtraDPDEBytesFrame; >+ unsigned int PDEAndMetaPTEBytesFrame; >+ >+ if (DCCEnable == true) { >+ MetaRequestHeight = 8 * BlockHeight256Bytes; >+ MetaRequestWidth = 8 * BlockWidth256Bytes; >+ if (ScanDirection == dm_horz) { >+ *meta_row_height = MetaRequestHeight; >+ MetaSurfWidth = dml_ceil((double) SwathWidth - 1, MetaRequestWidth) >+ + MetaRequestWidth; >+ *MetaRowByte = MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0; >+ } else { >+ *meta_row_height = MetaRequestWidth; >+ MetaSurfHeight = dml_ceil((double) SwathWidth - 1, MetaRequestHeight) >+ + MetaRequestHeight; >+ *MetaRowByte = MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0; >+ } >+ if (ScanDirection == dm_horz) { >+ DCCMetaSurfaceBytes = DCCMetaPitch >+ * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) >+ + 64 * BlockHeight256Bytes) * BytePerPixel >+ / 256; >+ } else { >+ DCCMetaSurfaceBytes = DCCMetaPitch >+ * (dml_ceil( >+ (double) ViewportHeight - 1, >+ 64 * BlockHeight256Bytes) >+ + 64 * BlockHeight256Bytes) * BytePerPixel >+ / 256; >+ } >+ if (GPUVMEnable == true) { >+ MetaPTEBytesFrame = (dml_ceil( >+ (double) (DCCMetaSurfaceBytes - VMMPageSize) >+ / (8 * VMMPageSize), >+ 1) + 1) * 64; >+ MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); >+ } else { >+ MetaPTEBytesFrame = 0; >+ MPDEBytesFrame = 0; >+ } >+ } else { >+ MetaPTEBytesFrame = 0; >+ MPDEBytesFrame = 0; >+ *MetaRowByte = 0; >+ } >+ >+ if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_lvp) { >+ MacroTileSizeBytes = 256; >+ MacroTileHeight = BlockHeight256Bytes; >+ } else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x >+ || SurfaceTiling == dm_sw_4kb_d || SurfaceTiling == dm_sw_4kb_d_x) { >+ MacroTileSizeBytes = 4096; >+ MacroTileHeight = 4 * BlockHeight256Bytes; >+ } else if (SurfaceTiling == dm_sw_64kb_s || SurfaceTiling == dm_sw_64kb_s_t >+ || SurfaceTiling == dm_sw_64kb_s_x || SurfaceTiling == dm_sw_64kb_d >+ || SurfaceTiling == dm_sw_64kb_d_t || SurfaceTiling == dm_sw_64kb_d_x >+ || SurfaceTiling == dm_sw_64kb_r_x) { >+ MacroTileSizeBytes = 65536; >+ MacroTileHeight = 16 * BlockHeight256Bytes; >+ } else { >+ MacroTileSizeBytes = 262144; >+ MacroTileHeight = 32 * BlockHeight256Bytes; >+ } >+ *MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight; >+ >+ if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { >+ if (ScanDirection == dm_horz) { >+ DPDE0BytesFrame = >+ 64 >+ * (dml_ceil( >+ ((Pitch >+ * (dml_ceil( >+ ViewportHeight >+ - 1, >+ MacroTileHeight) >+ + MacroTileHeight) >+ * BytePerPixel) >+ - MacroTileSizeBytes) >+ / (8 >+ * 2097152), >+ 1) + 1); >+ } else { >+ DPDE0BytesFrame = >+ 64 >+ * (dml_ceil( >+ ((Pitch >+ * (dml_ceil( >+ (double) SwathWidth >+ - 1, >+ MacroTileHeight) >+ + MacroTileHeight) >+ * BytePerPixel) >+ - MacroTileSizeBytes) >+ / (8 >+ * 2097152), >+ 1) + 1); >+ } >+ ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); >+ } else { >+ DPDE0BytesFrame = 0; >+ ExtraDPDEBytesFrame = 0; >+ } >+ >+ PDEAndMetaPTEBytesFrame = MetaPTEBytesFrame + MPDEBytesFrame + DPDE0BytesFrame >+ + ExtraDPDEBytesFrame; >+ >+ if (GPUVMEnable == true) { >+ unsigned int PTERequestSize; >+ unsigned int PixelPTEReqHeight; >+ unsigned int PixelPTEReqWidth; >+ double FractionOfPTEReturnDrop; >+ unsigned int EffectivePDEProcessingBufIn64KBReqs; >+ >+ if (SurfaceTiling == dm_sw_linear) { >+ PixelPTEReqHeight = 1; >+ PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel; >+ PTERequestSize = 64; >+ FractionOfPTEReturnDrop = 0; >+ } else if (MacroTileSizeBytes == 4096) { >+ PixelPTEReqHeight = MacroTileHeight; >+ PixelPTEReqWidth = 8 * *MacroTileWidth; >+ PTERequestSize = 64; >+ if (ScanDirection == dm_horz) >+ FractionOfPTEReturnDrop = 0; >+ else >+ FractionOfPTEReturnDrop = 7 / 8; >+ } else if (VMMPageSize == 4096 && MacroTileSizeBytes > 4096) { >+ PixelPTEReqHeight = 16 * BlockHeight256Bytes; >+ PixelPTEReqWidth = 16 * BlockWidth256Bytes; >+ PTERequestSize = 128; >+ FractionOfPTEReturnDrop = 0; >+ } else { >+ PixelPTEReqHeight = MacroTileHeight; >+ PixelPTEReqWidth = 8 * *MacroTileWidth; >+ PTERequestSize = 64; >+ FractionOfPTEReturnDrop = 0; >+ } >+ >+ if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) >+ EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs / 2; >+ else >+ EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs; >+ >+ if (SurfaceTiling == dm_sw_linear) { >+ *dpte_row_height = >+ dml_min( >+ 128, >+ 1 >+ << (unsigned int) dml_floor( >+ dml_log2( >+ dml_min( >+ (double) PTEBufferSizeInRequestsLuma >+ * PixelPTEReqWidth, >+ EffectivePDEProcessingBufIn64KBReqs >+ * 65536.0 >+ / BytePerPixel) >+ / Pitch), >+ 1)); >+ *PixelPTEBytesPerRow = PTERequestSize >+ * (dml_ceil( >+ (double) (Pitch * *dpte_row_height - 1) >+ / PixelPTEReqWidth, >+ 1) + 1); >+ } else if (ScanDirection == dm_horz) { >+ *dpte_row_height = PixelPTEReqHeight; >+ *PixelPTEBytesPerRow = PTERequestSize >+ * (dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) >+ + 1); >+ } else { >+ *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); >+ *PixelPTEBytesPerRow = PTERequestSize >+ * (dml_ceil( >+ ((double) SwathWidth - 1) >+ / PixelPTEReqHeight, >+ 1) + 1); >+ } >+ if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) >+ <= 64 * PTEBufferSizeInRequestsLuma) { >+ *PTEBufferSizeNotExceeded = true; >+ } else { >+ *PTEBufferSizeNotExceeded = false; >+ } >+ } else { >+ *PixelPTEBytesPerRow = 0; >+ *PTEBufferSizeNotExceeded = true; >+ } >+ >+ return PDEAndMetaPTEBytesFrame; >+} >+ >+static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation( >+ struct display_mode_lib *mode_lib) >+{ >+ unsigned int j, k; >+ >+ mode_lib->vba.WritebackDISPCLK = 0.0; >+ mode_lib->vba.DISPCLKWithRamping = 0; >+ mode_lib->vba.DISPCLKWithoutRamping = 0; >+ mode_lib->vba.GlobalDPPCLK = 0.0; >+ >+ // dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation >+ // >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.WritebackEnable[k]) { >+ mode_lib->vba.WritebackDISPCLK = >+ dml_max( >+ mode_lib->vba.WritebackDISPCLK, >+ CalculateWriteBackDISPCLK( >+ mode_lib->vba.WritebackPixelFormat[k], >+ mode_lib->vba.PixelClock[k], >+ mode_lib->vba.WritebackHRatio[k], >+ mode_lib->vba.WritebackVRatio[k], >+ mode_lib->vba.WritebackLumaHTaps[k], >+ mode_lib->vba.WritebackLumaVTaps[k], >+ mode_lib->vba.WritebackChromaHTaps[k], >+ mode_lib->vba.WritebackChromaVTaps[k], >+ mode_lib->vba.WritebackDestinationWidth[k], >+ mode_lib->vba.HTotal[k], >+ mode_lib->vba.WritebackChromaLineBufferWidth)); >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.HRatio[k] > 1) { >+ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput >+ * mode_lib->vba.HRatio[k] >+ / dml_ceil( >+ mode_lib->vba.htaps[k] >+ / 6.0, >+ 1)); >+ } else { >+ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput); >+ } >+ >+ mode_lib->vba.DPPCLKUsingSingleDPPLuma = >+ mode_lib->vba.PixelClock[k] >+ * dml_max( >+ mode_lib->vba.vtaps[k] / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k]), >+ dml_max( >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k], >+ 1.0)); >+ >+ if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6) >+ && mode_lib->vba.DPPCLKUsingSingleDPPLuma >+ < 2 * mode_lib->vba.PixelClock[k]) { >+ mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k]; >+ } >+ >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { >+ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0; >+ mode_lib->vba.DPPCLKUsingSingleDPP[k] = >+ mode_lib->vba.DPPCLKUsingSingleDPPLuma; >+ } else { >+ if (mode_lib->vba.HRatio[k] > 1) { >+ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = >+ dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput >+ * mode_lib->vba.HRatio[k] >+ / 2 >+ / dml_ceil( >+ mode_lib->vba.HTAPsChroma[k] >+ / 6.0, >+ 1.0)); >+ } else { >+ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput); >+ } >+ mode_lib->vba.DPPCLKUsingSingleDPPChroma = >+ mode_lib->vba.PixelClock[k] >+ * dml_max( >+ mode_lib->vba.VTAPsChroma[k] >+ / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k] >+ / 2), >+ dml_max( >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / 4 >+ / mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k], >+ 1.0)); >+ >+ if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6) >+ && mode_lib->vba.DPPCLKUsingSingleDPPChroma >+ < 2 * mode_lib->vba.PixelClock[k]) { >+ mode_lib->vba.DPPCLKUsingSingleDPPChroma = 2 >+ * mode_lib->vba.PixelClock[k]; >+ } >+ >+ mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max( >+ mode_lib->vba.DPPCLKUsingSingleDPPLuma, >+ mode_lib->vba.DPPCLKUsingSingleDPPChroma); >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.BlendingAndTiming[k] != k) >+ continue; >+ if (mode_lib->vba.ODMCombineEnabled[k]) { >+ mode_lib->vba.DISPCLKWithRamping = >+ dml_max( >+ mode_lib->vba.DISPCLKWithRamping, >+ mode_lib->vba.PixelClock[k] / 2 >+ * (1 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100) >+ * (1 >+ + mode_lib->vba.DISPCLKRampingMargin >+ / 100)); >+ mode_lib->vba.DISPCLKWithoutRamping = >+ dml_max( >+ mode_lib->vba.DISPCLKWithoutRamping, >+ mode_lib->vba.PixelClock[k] / 2 >+ * (1 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100)); >+ } else if (!mode_lib->vba.ODMCombineEnabled[k]) { >+ mode_lib->vba.DISPCLKWithRamping = >+ dml_max( >+ mode_lib->vba.DISPCLKWithRamping, >+ mode_lib->vba.PixelClock[k] >+ * (1 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100) >+ * (1 >+ + mode_lib->vba.DISPCLKRampingMargin >+ / 100)); >+ mode_lib->vba.DISPCLKWithoutRamping = >+ dml_max( >+ mode_lib->vba.DISPCLKWithoutRamping, >+ mode_lib->vba.PixelClock[k] >+ * (1 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100)); >+ } >+ } >+ >+ mode_lib->vba.DISPCLKWithRamping = dml_max( >+ mode_lib->vba.DISPCLKWithRamping, >+ mode_lib->vba.WritebackDISPCLK); >+ mode_lib->vba.DISPCLKWithoutRamping = dml_max( >+ mode_lib->vba.DISPCLKWithoutRamping, >+ mode_lib->vba.WritebackDISPCLK); >+ >+ ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0); >+ mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp( >+ mode_lib->vba.DISPCLKWithRamping, >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp( >+ mode_lib->vba.DISPCLKWithoutRamping, >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ mode_lib->vba.MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown( >+ mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ if (mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity >+ > mode_lib->vba.MaxDispclkRoundedToDFSGranularity) { >+ mode_lib->vba.DISPCLK_calculated = >+ mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity; >+ } else if (mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity >+ > mode_lib->vba.MaxDispclkRoundedToDFSGranularity) { >+ mode_lib->vba.DISPCLK_calculated = mode_lib->vba.MaxDispclkRoundedToDFSGranularity; >+ } else { >+ mode_lib->vba.DISPCLK_calculated = >+ mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity; >+ } >+ DTRACE(" dispclk_mhz (calculated) = %f", mode_lib->vba.DISPCLK_calculated); >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.DPPPerPlane[k] == 0) { >+ mode_lib->vba.DPPCLK_calculated[k] = 0; >+ } else { >+ mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k] >+ / mode_lib->vba.DPPPerPlane[k] >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100); >+ } >+ mode_lib->vba.GlobalDPPCLK = dml_max( >+ mode_lib->vba.GlobalDPPCLK, >+ mode_lib->vba.DPPCLK_calculated[k]); >+ } >+ mode_lib->vba.GlobalDPPCLK = RoundToDFSGranularityUp( >+ mode_lib->vba.GlobalDPPCLK, >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255 >+ * dml_ceil( >+ mode_lib->vba.DPPCLK_calculated[k] * 255 >+ / mode_lib->vba.GlobalDPPCLK, >+ 1); >+ DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]); >+ } >+ >+ // Urgent Watermark >+ mode_lib->vba.DCCEnabledAnyPlane = false; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) >+ if (mode_lib->vba.DCCEnable[k]) >+ mode_lib->vba.DCCEnabledAnyPlane = true; >+ >+ mode_lib->vba.ReturnBandwidthToDCN = dml_min( >+ mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK, >+ mode_lib->vba.FabricAndDRAMBandwidth * 1000) >+ * mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100; >+ >+ mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBandwidthToDCN; >+ mode_lib->vba.ReturnBW = adjust_ReturnBW( >+ mode_lib, >+ mode_lib->vba.ReturnBW, >+ mode_lib->vba.DCCEnabledAnyPlane, >+ mode_lib->vba.ReturnBandwidthToDCN); >+ >+ // Let's do this calculation again?? >+ mode_lib->vba.ReturnBandwidthToDCN = dml_min( >+ mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK, >+ mode_lib->vba.FabricAndDRAMBandwidth * 1000); >+ mode_lib->vba.ReturnBW = adjust_ReturnBW( >+ mode_lib, >+ mode_lib->vba.ReturnBW, >+ mode_lib->vba.DCCEnabledAnyPlane, >+ mode_lib->vba.ReturnBandwidthToDCN); >+ >+ DTRACE(" dcfclk_mhz = %f", mode_lib->vba.DCFCLK); >+ DTRACE(" return_bw_to_dcn = %f", mode_lib->vba.ReturnBandwidthToDCN); >+ DTRACE(" return_bus_bw = %f", mode_lib->vba.ReturnBW); >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ bool MainPlaneDoesODMCombine = false; >+ >+ if (mode_lib->vba.SourceScan[k] == dm_horz) >+ mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k]; >+ else >+ mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k]; >+ >+ if (mode_lib->vba.ODMCombineEnabled[k] == true) >+ MainPlaneDoesODMCombine = true; >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) >+ if (mode_lib->vba.BlendingAndTiming[k] == j >+ && mode_lib->vba.ODMCombineEnabled[j] == true) >+ MainPlaneDoesODMCombine = true; >+ >+ if (MainPlaneDoesODMCombine == true) >+ mode_lib->vba.SwathWidthY[k] = dml_min( >+ (double) mode_lib->vba.SwathWidthSingleDPPY[k], >+ dml_round( >+ mode_lib->vba.HActive[k] / 2.0 >+ * mode_lib->vba.HRatio[k])); >+ else { >+ if (mode_lib->vba.DPPPerPlane[k] == 0) { >+ mode_lib->vba.SwathWidthY[k] = 0; >+ } else { >+ mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k] >+ / mode_lib->vba.DPPPerPlane[k]; >+ } >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { >+ mode_lib->vba.BytePerPixelDETY[k] = 8; >+ mode_lib->vba.BytePerPixelDETC[k] = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { >+ mode_lib->vba.BytePerPixelDETY[k] = 4; >+ mode_lib->vba.BytePerPixelDETC[k] = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { >+ mode_lib->vba.BytePerPixelDETY[k] = 2; >+ mode_lib->vba.BytePerPixelDETC[k] = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) { >+ mode_lib->vba.BytePerPixelDETY[k] = 1; >+ mode_lib->vba.BytePerPixelDETC[k] = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { >+ mode_lib->vba.BytePerPixelDETY[k] = 1; >+ mode_lib->vba.BytePerPixelDETC[k] = 2; >+ } else { // dm_420_10 >+ mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0; >+ mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0; >+ } >+ } >+ >+ mode_lib->vba.TotalDataReadBandwidth = 0.0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k] >+ * dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) >+ * mode_lib->vba.VRatio[k]; >+ mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k] >+ / 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2) >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) >+ * mode_lib->vba.VRatio[k] / 2; >+ DTRACE( >+ " read_bw[%i] = %fBps", >+ k, >+ mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k]); >+ mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k]; >+ } >+ >+ mode_lib->vba.TotalDCCActiveDPP = 0; >+ mode_lib->vba.TotalActiveDPP = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP >+ + mode_lib->vba.DPPPerPlane[k]; >+ if (mode_lib->vba.DCCEnable[k]) >+ mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP >+ + mode_lib->vba.DPPPerPlane[k]; >+ } >+ >+ mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency = >+ (mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK >+ + mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly >+ * mode_lib->vba.NumberOfChannels >+ / mode_lib->vba.ReturnBW; >+ >+ mode_lib->vba.LastPixelOfLineExtraWatermark = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.VRatio[k] <= 1.0) >+ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] = >+ (double) mode_lib->vba.SwathWidthY[k] >+ * mode_lib->vba.DPPPerPlane[k] >+ / mode_lib->vba.HRatio[k] >+ / mode_lib->vba.PixelClock[k]; >+ else >+ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] = >+ (double) mode_lib->vba.SwathWidthY[k] >+ / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] >+ / mode_lib->vba.DPPCLK[k]; >+ >+ if (mode_lib->vba.BytePerPixelDETC[k] == 0) >+ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0; >+ else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) >+ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = >+ mode_lib->vba.SwathWidthY[k] / 2.0 >+ * mode_lib->vba.DPPPerPlane[k] >+ / (mode_lib->vba.HRatio[k] / 2.0) >+ / mode_lib->vba.PixelClock[k]; >+ else >+ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = >+ mode_lib->vba.SwathWidthY[k] / 2.0 >+ / mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] >+ / mode_lib->vba.DPPCLK[k]; >+ } >+ >+ mode_lib->vba.UrgentExtraLatency = mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency >+ + (mode_lib->vba.TotalActiveDPP * mode_lib->vba.PixelChunkSizeInKByte >+ + mode_lib->vba.TotalDCCActiveDPP >+ * mode_lib->vba.MetaChunkSize) * 1024.0 >+ / mode_lib->vba.ReturnBW; >+ >+ if (mode_lib->vba.GPUVMEnable) >+ mode_lib->vba.UrgentExtraLatency += mode_lib->vba.TotalActiveDPP >+ * mode_lib->vba.PTEGroupSize / mode_lib->vba.ReturnBW; >+ >+ mode_lib->vba.UrgentWatermark = mode_lib->vba.UrgentLatencyPixelDataOnly >+ + mode_lib->vba.LastPixelOfLineExtraWatermark >+ + mode_lib->vba.UrgentExtraLatency; >+ >+ DTRACE(" urgent_extra_latency = %fus", mode_lib->vba.UrgentExtraLatency); >+ DTRACE(" wm_urgent = %fus", mode_lib->vba.UrgentWatermark); >+ >+ mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly; >+ >+ mode_lib->vba.TotalActiveWriteback = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.WritebackEnable[k]) >+ mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k]; >+ } >+ >+ if (mode_lib->vba.TotalActiveWriteback <= 1) >+ mode_lib->vba.WritebackUrgentWatermark = mode_lib->vba.WritebackLatency; >+ else >+ mode_lib->vba.WritebackUrgentWatermark = mode_lib->vba.WritebackLatency >+ + mode_lib->vba.WritebackChunkSize * 1024.0 / 32 >+ / mode_lib->vba.SOCCLK; >+ >+ DTRACE(" wm_wb_urgent = %fus", mode_lib->vba.WritebackUrgentWatermark); >+ >+ // NB P-State/DRAM Clock Change Watermark >+ mode_lib->vba.DRAMClockChangeWatermark = mode_lib->vba.DRAMClockChangeLatency >+ + mode_lib->vba.UrgentWatermark; >+ >+ DTRACE(" wm_pstate_change = %fus", mode_lib->vba.DRAMClockChangeWatermark); >+ >+ DTRACE(" calculating wb pstate watermark"); >+ DTRACE(" total wb outputs %d", mode_lib->vba.TotalActiveWriteback); >+ DTRACE(" socclk frequency %f Mhz", mode_lib->vba.SOCCLK); >+ >+ if (mode_lib->vba.TotalActiveWriteback <= 1) >+ mode_lib->vba.WritebackDRAMClockChangeWatermark = >+ mode_lib->vba.DRAMClockChangeLatency >+ + mode_lib->vba.WritebackLatency; >+ else >+ mode_lib->vba.WritebackDRAMClockChangeWatermark = >+ mode_lib->vba.DRAMClockChangeLatency >+ + mode_lib->vba.WritebackLatency >+ + mode_lib->vba.WritebackChunkSize * 1024.0 / 32 >+ / mode_lib->vba.SOCCLK; >+ >+ DTRACE(" wm_wb_pstate %fus", mode_lib->vba.WritebackDRAMClockChangeWatermark); >+ >+ // Stutter Efficiency >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k] >+ / mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k]; >+ mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor( >+ mode_lib->vba.LinesInDETY[k], >+ mode_lib->vba.SwathHeightY[k]); >+ mode_lib->vba.FullDETBufferingTimeY[k] = >+ mode_lib->vba.LinesInDETYRoundedDownToSwath[k] >+ * (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) >+ / mode_lib->vba.VRatio[k]; >+ if (mode_lib->vba.BytePerPixelDETC[k] > 0) { >+ mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k] >+ / mode_lib->vba.BytePerPixelDETC[k] >+ / (mode_lib->vba.SwathWidthY[k] / 2); >+ mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor( >+ mode_lib->vba.LinesInDETC[k], >+ mode_lib->vba.SwathHeightC[k]); >+ mode_lib->vba.FullDETBufferingTimeC[k] = >+ mode_lib->vba.LinesInDETCRoundedDownToSwath[k] >+ * (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) >+ / (mode_lib->vba.VRatio[k] / 2); >+ } else { >+ mode_lib->vba.LinesInDETC[k] = 0; >+ mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0; >+ mode_lib->vba.FullDETBufferingTimeC[k] = 999999; >+ } >+ } >+ >+ mode_lib->vba.MinFullDETBufferingTime = 999999.0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.FullDETBufferingTimeY[k] >+ < mode_lib->vba.MinFullDETBufferingTime) { >+ mode_lib->vba.MinFullDETBufferingTime = >+ mode_lib->vba.FullDETBufferingTimeY[k]; >+ mode_lib->vba.FrameTimeForMinFullDETBufferingTime = >+ (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]; >+ } >+ if (mode_lib->vba.FullDETBufferingTimeC[k] >+ < mode_lib->vba.MinFullDETBufferingTime) { >+ mode_lib->vba.MinFullDETBufferingTime = >+ mode_lib->vba.FullDETBufferingTimeC[k]; >+ mode_lib->vba.FrameTimeForMinFullDETBufferingTime = >+ (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]; >+ } >+ } >+ >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond = 0.0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.DCCEnable[k]) { >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond = >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond >+ + mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ / mode_lib->vba.DCCRate[k] >+ / 1000 >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k] >+ / mode_lib->vba.DCCRate[k] >+ / 1000; >+ } else { >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond = >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond >+ + mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ / 1000 >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k] >+ / 1000; >+ } >+ if (mode_lib->vba.DCCEnable[k]) { >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond = >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond >+ + mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ / 1000 / 256 >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k] >+ / 1000 / 256; >+ } >+ if (mode_lib->vba.GPUVMEnable) { >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond = >+ mode_lib->vba.AverageReadBandwidthGBytePerSecond >+ + mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ / 1000 / 512 >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k] >+ / 1000 / 512; >+ } >+ } >+ >+ mode_lib->vba.PartOfBurstThatFitsInROB = >+ dml_min( >+ mode_lib->vba.MinFullDETBufferingTime >+ * mode_lib->vba.TotalDataReadBandwidth, >+ mode_lib->vba.ROBBufferSizeInKByte * 1024 >+ * mode_lib->vba.TotalDataReadBandwidth >+ / (mode_lib->vba.AverageReadBandwidthGBytePerSecond >+ * 1000)); >+ mode_lib->vba.StutterBurstTime = mode_lib->vba.PartOfBurstThatFitsInROB >+ * (mode_lib->vba.AverageReadBandwidthGBytePerSecond * 1000) >+ / mode_lib->vba.TotalDataReadBandwidth / mode_lib->vba.ReturnBW >+ + (mode_lib->vba.MinFullDETBufferingTime >+ * mode_lib->vba.TotalDataReadBandwidth >+ - mode_lib->vba.PartOfBurstThatFitsInROB) >+ / (mode_lib->vba.DCFCLK * 64); >+ if (mode_lib->vba.TotalActiveWriteback == 0) { >+ mode_lib->vba.StutterEfficiencyNotIncludingVBlank = (1 >+ - (mode_lib->vba.SRExitTime + mode_lib->vba.StutterBurstTime) >+ / mode_lib->vba.MinFullDETBufferingTime) * 100; >+ } else { >+ mode_lib->vba.StutterEfficiencyNotIncludingVBlank = 0; >+ } >+ >+ mode_lib->vba.SmallestVBlank = 999999; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) { >+ mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k] >+ - mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]; >+ } else { >+ mode_lib->vba.VBlankTime = 0; >+ } >+ mode_lib->vba.SmallestVBlank = dml_min( >+ mode_lib->vba.SmallestVBlank, >+ mode_lib->vba.VBlankTime); >+ } >+ >+ mode_lib->vba.StutterEfficiency = (mode_lib->vba.StutterEfficiencyNotIncludingVBlank / 100 >+ * (mode_lib->vba.FrameTimeForMinFullDETBufferingTime >+ - mode_lib->vba.SmallestVBlank) >+ + mode_lib->vba.SmallestVBlank) >+ / mode_lib->vba.FrameTimeForMinFullDETBufferingTime * 100; >+ >+ // dml_ml->vba.DCFCLK Deep Sleep >+ mode_lib->vba.DCFCLKDeepSleep = 8.0; >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) { >+ if (mode_lib->vba.BytePerPixelDETC[k] > 0) { >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = >+ dml_max( >+ 1.1 * mode_lib->vba.SwathWidthY[k] >+ * dml_ceil( >+ mode_lib->vba.BytePerPixelDETY[k], >+ 1) / 32 >+ / mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], >+ 1.1 * mode_lib->vba.SwathWidthY[k] / 2.0 >+ * dml_ceil( >+ mode_lib->vba.BytePerPixelDETC[k], >+ 2) / 32 >+ / mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]); >+ } else >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k] >+ * dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0 >+ / mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k]; >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max( >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k], >+ mode_lib->vba.PixelClock[k] / 16.0); >+ mode_lib->vba.DCFCLKDeepSleep = dml_max( >+ mode_lib->vba.DCFCLKDeepSleep, >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k]); >+ >+ DTRACE( >+ " dcfclk_deepsleep_per_plane[%i] = %fMHz", >+ k, >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k]); >+ } >+ >+ DTRACE(" dcfclk_deepsleep_mhz = %fMHz", mode_lib->vba.DCFCLKDeepSleep); >+ >+ // Stutter Watermark >+ mode_lib->vba.StutterExitWatermark = mode_lib->vba.SRExitTime >+ + mode_lib->vba.LastPixelOfLineExtraWatermark >+ + mode_lib->vba.UrgentExtraLatency + 10 / mode_lib->vba.DCFCLKDeepSleep; >+ mode_lib->vba.StutterEnterPlusExitWatermark = mode_lib->vba.SREnterPlusExitTime >+ + mode_lib->vba.LastPixelOfLineExtraWatermark >+ + mode_lib->vba.UrgentExtraLatency; >+ >+ DTRACE(" wm_cstate_exit = %fus", mode_lib->vba.StutterExitWatermark); >+ DTRACE(" wm_cstate_enter_exit = %fus", mode_lib->vba.StutterEnterPlusExitWatermark); >+ >+ // Urgent Latency Supported >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.EffectiveDETPlusLBLinesLuma = >+ dml_floor( >+ mode_lib->vba.LinesInDETY[k] >+ + dml_min( >+ mode_lib->vba.LinesInDETY[k] >+ * mode_lib->vba.DPPCLK[k] >+ * mode_lib->vba.BytePerPixelDETY[k] >+ * mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] >+ / (mode_lib->vba.ReturnBW >+ / mode_lib->vba.DPPPerPlane[k]), >+ (double) mode_lib->vba.EffectiveLBLatencyHidingSourceLinesLuma), >+ mode_lib->vba.SwathHeightY[k]); >+ >+ mode_lib->vba.UrgentLatencySupportUsLuma = mode_lib->vba.EffectiveDETPlusLBLinesLuma >+ * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) >+ / mode_lib->vba.VRatio[k] >+ - mode_lib->vba.EffectiveDETPlusLBLinesLuma >+ * mode_lib->vba.SwathWidthY[k] >+ * mode_lib->vba.BytePerPixelDETY[k] >+ / (mode_lib->vba.ReturnBW >+ / mode_lib->vba.DPPPerPlane[k]); >+ >+ if (mode_lib->vba.BytePerPixelDETC[k] > 0) { >+ mode_lib->vba.EffectiveDETPlusLBLinesChroma = >+ dml_floor( >+ mode_lib->vba.LinesInDETC[k] >+ + dml_min( >+ mode_lib->vba.LinesInDETC[k] >+ * mode_lib->vba.DPPCLK[k] >+ * mode_lib->vba.BytePerPixelDETC[k] >+ * mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] >+ / (mode_lib->vba.ReturnBW >+ / mode_lib->vba.DPPPerPlane[k]), >+ (double) mode_lib->vba.EffectiveLBLatencyHidingSourceLinesChroma), >+ mode_lib->vba.SwathHeightC[k]); >+ mode_lib->vba.UrgentLatencySupportUsChroma = >+ mode_lib->vba.EffectiveDETPlusLBLinesChroma >+ * (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) >+ / (mode_lib->vba.VRatio[k] / 2) >+ - mode_lib->vba.EffectiveDETPlusLBLinesChroma >+ * (mode_lib->vba.SwathWidthY[k] >+ / 2) >+ * mode_lib->vba.BytePerPixelDETC[k] >+ / (mode_lib->vba.ReturnBW >+ / mode_lib->vba.DPPPerPlane[k]); >+ mode_lib->vba.UrgentLatencySupportUs[k] = dml_min( >+ mode_lib->vba.UrgentLatencySupportUsLuma, >+ mode_lib->vba.UrgentLatencySupportUsChroma); >+ } else { >+ mode_lib->vba.UrgentLatencySupportUs[k] = >+ mode_lib->vba.UrgentLatencySupportUsLuma; >+ } >+ } >+ >+ mode_lib->vba.MinUrgentLatencySupportUs = 999999; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.MinUrgentLatencySupportUs = dml_min( >+ mode_lib->vba.MinUrgentLatencySupportUs, >+ mode_lib->vba.UrgentLatencySupportUs[k]); >+ } >+ >+ // Non-Urgent Latency Tolerance >+ mode_lib->vba.NonUrgentLatencyTolerance = mode_lib->vba.MinUrgentLatencySupportUs >+ - mode_lib->vba.UrgentWatermark; >+ >+ // DSCCLK >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { >+ mode_lib->vba.DSCCLK_calculated[k] = 0.0; >+ } else { >+ if (mode_lib->vba.OutputFormat[k] == dm_420 >+ || mode_lib->vba.OutputFormat[k] == dm_n422) >+ mode_lib->vba.DSCFormatFactor = 2; >+ else >+ mode_lib->vba.DSCFormatFactor = 1; >+ if (mode_lib->vba.ODMCombineEnabled[k]) >+ mode_lib->vba.DSCCLK_calculated[k] = >+ mode_lib->vba.PixelClockBackEnd[k] / 6 >+ / mode_lib->vba.DSCFormatFactor >+ / (1 >+ - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100); >+ else >+ mode_lib->vba.DSCCLK_calculated[k] = >+ mode_lib->vba.PixelClockBackEnd[k] / 3 >+ / mode_lib->vba.DSCFormatFactor >+ / (1 >+ - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100); >+ } >+ } >+ >+ // DSC Delay >+ // TODO >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ double bpp = mode_lib->vba.OutputBpp[k]; >+ unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; >+ >+ if (mode_lib->vba.DSCEnabled[k] && bpp != 0) { >+ if (!mode_lib->vba.ODMCombineEnabled[k]) { >+ mode_lib->vba.DSCDelay[k] = >+ dscceComputeDelay( >+ mode_lib->vba.DSCInputBitPerComponent[k], >+ bpp, >+ dml_ceil( >+ (double) mode_lib->vba.HActive[k] >+ / mode_lib->vba.NumberOfDSCSlices[k], >+ 1), >+ slices, >+ mode_lib->vba.OutputFormat[k]) >+ + dscComputeDelay( >+ mode_lib->vba.OutputFormat[k]); >+ } else { >+ mode_lib->vba.DSCDelay[k] = >+ 2 >+ * (dscceComputeDelay( >+ mode_lib->vba.DSCInputBitPerComponent[k], >+ bpp, >+ dml_ceil( >+ (double) mode_lib->vba.HActive[k] >+ / mode_lib->vba.NumberOfDSCSlices[k], >+ 1), >+ slices / 2.0, >+ mode_lib->vba.OutputFormat[k]) >+ + dscComputeDelay( >+ mode_lib->vba.OutputFormat[k])); >+ } >+ mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k] >+ * mode_lib->vba.PixelClock[k] >+ / mode_lib->vba.PixelClockBackEnd[k]; >+ } else { >+ mode_lib->vba.DSCDelay[k] = 0; >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) // NumberOfPlanes >+ if (j != k && mode_lib->vba.BlendingAndTiming[k] == j >+ && mode_lib->vba.DSCEnabled[j]) >+ mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j]; >+ >+ // Prefetch >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ unsigned int PDEAndMetaPTEBytesFrameY; >+ unsigned int PixelPTEBytesPerRowY; >+ unsigned int MetaRowByteY; >+ unsigned int MetaRowByteC; >+ unsigned int PDEAndMetaPTEBytesFrameC; >+ unsigned int PixelPTEBytesPerRowC; >+ >+ Calculate256BBlockSizes( >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), >+ dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), >+ &mode_lib->vba.BlockHeight256BytesY[k], >+ &mode_lib->vba.BlockHeight256BytesC[k], >+ &mode_lib->vba.BlockWidth256BytesY[k], >+ &mode_lib->vba.BlockWidth256BytesC[k]); >+ PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes( >+ mode_lib, >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.BlockHeight256BytesY[k], >+ mode_lib->vba.BlockWidth256BytesY[k], >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), >+ mode_lib->vba.SourceScan[k], >+ mode_lib->vba.ViewportWidth[k], >+ mode_lib->vba.ViewportHeight[k], >+ mode_lib->vba.SwathWidthY[k], >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.VMMPageSize, >+ mode_lib->vba.PTEBufferSizeInRequestsLuma, >+ mode_lib->vba.PDEProcessingBufIn64KBReqs, >+ mode_lib->vba.PitchY[k], >+ mode_lib->vba.DCCMetaPitchY[k], >+ &mode_lib->vba.MacroTileWidthY[k], >+ &MetaRowByteY, >+ &PixelPTEBytesPerRowY, >+ &mode_lib->vba.PTEBufferSizeNotExceeded[mode_lib->vba.VoltageLevel][0], >+ &mode_lib->vba.dpte_row_height[k], >+ &mode_lib->vba.meta_row_height[k]); >+ mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.vtaps[k], >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ mode_lib->vba.SwathHeightY[k], >+ mode_lib->vba.ViewportYStartY[k], >+ &mode_lib->vba.VInitPreFillY[k], >+ &mode_lib->vba.MaxNumSwathY[k]); >+ >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) { >+ PDEAndMetaPTEBytesFrameC = >+ CalculateVMAndRowBytes( >+ mode_lib, >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.BlockHeight256BytesC[k], >+ mode_lib->vba.BlockWidth256BytesC[k], >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil( >+ mode_lib->vba.BytePerPixelDETC[k], >+ 2), >+ mode_lib->vba.SourceScan[k], >+ mode_lib->vba.ViewportWidth[k] / 2, >+ mode_lib->vba.ViewportHeight[k] / 2, >+ mode_lib->vba.SwathWidthY[k] / 2, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.VMMPageSize, >+ mode_lib->vba.PTEBufferSizeInRequestsLuma, >+ mode_lib->vba.PDEProcessingBufIn64KBReqs, >+ mode_lib->vba.PitchC[k], >+ 0, >+ &mode_lib->vba.MacroTileWidthC[k], >+ &MetaRowByteC, >+ &PixelPTEBytesPerRowC, >+ &mode_lib->vba.PTEBufferSizeNotExceeded[mode_lib->vba.VoltageLevel][0], >+ &mode_lib->vba.dpte_row_height_chroma[k], >+ &mode_lib->vba.meta_row_height_chroma[k]); >+ mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines( >+ mode_lib, >+ mode_lib->vba.VRatio[k] / 2, >+ mode_lib->vba.VTAPsChroma[k], >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ mode_lib->vba.SwathHeightC[k], >+ mode_lib->vba.ViewportYStartC[k], >+ &mode_lib->vba.VInitPreFillC[k], >+ &mode_lib->vba.MaxNumSwathC[k]); >+ } else { >+ PixelPTEBytesPerRowC = 0; >+ PDEAndMetaPTEBytesFrameC = 0; >+ MetaRowByteC = 0; >+ mode_lib->vba.MaxNumSwathC[k] = 0; >+ mode_lib->vba.PrefetchSourceLinesC[k] = 0; >+ } >+ >+ mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC; >+ mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY >+ + PDEAndMetaPTEBytesFrameC; >+ mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC; >+ >+ CalculateActiveRowBandwidth( >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ MetaRowByteY, >+ MetaRowByteC, >+ mode_lib->vba.meta_row_height[k], >+ mode_lib->vba.meta_row_height_chroma[k], >+ PixelPTEBytesPerRowY, >+ PixelPTEBytesPerRowC, >+ mode_lib->vba.dpte_row_height[k], >+ mode_lib->vba.dpte_row_height_chroma[k], >+ &mode_lib->vba.meta_row_bw[k], >+ &mode_lib->vba.dpte_row_bw[k], >+ &mode_lib->vba.qual_row_bw[k]); >+ } >+ >+ mode_lib->vba.TCalc = 24.0 / mode_lib->vba.DCFCLKDeepSleep; >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = >+ mode_lib->vba.WritebackLatency >+ + CalculateWriteBackDelay( >+ mode_lib->vba.WritebackPixelFormat[k], >+ mode_lib->vba.WritebackHRatio[k], >+ mode_lib->vba.WritebackVRatio[k], >+ mode_lib->vba.WritebackLumaHTaps[k], >+ mode_lib->vba.WritebackLumaVTaps[k], >+ mode_lib->vba.WritebackChromaHTaps[k], >+ mode_lib->vba.WritebackChromaVTaps[k], >+ mode_lib->vba.WritebackDestinationWidth[k]) >+ / mode_lib->vba.DISPCLK; >+ } else >+ mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) { >+ if (mode_lib->vba.BlendingAndTiming[j] == k >+ && mode_lib->vba.WritebackEnable[j] == true) { >+ mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = >+ dml_max( >+ mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k], >+ mode_lib->vba.WritebackLatency >+ + CalculateWriteBackDelay( >+ mode_lib->vba.WritebackPixelFormat[j], >+ mode_lib->vba.WritebackHRatio[j], >+ mode_lib->vba.WritebackVRatio[j], >+ mode_lib->vba.WritebackLumaHTaps[j], >+ mode_lib->vba.WritebackLumaVTaps[j], >+ mode_lib->vba.WritebackChromaHTaps[j], >+ mode_lib->vba.WritebackChromaVTaps[j], >+ mode_lib->vba.WritebackDestinationWidth[j]) >+ / mode_lib->vba.DISPCLK); >+ } >+ } >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) >+ if (mode_lib->vba.BlendingAndTiming[k] == j) >+ mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = >+ mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][j]; >+ >+ mode_lib->vba.VStartupLines = 13; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.MaxVStartupLines[k] = >+ mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] >+ - dml_max( >+ 1.0, >+ dml_ceil( >+ mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] >+ / (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]), >+ 1)); >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) >+ mode_lib->vba.MaximumMaxVStartupLines = dml_max( >+ mode_lib->vba.MaximumMaxVStartupLines, >+ mode_lib->vba.MaxVStartupLines[k]); >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.cursor_bw[k] = 0.0; >+ for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j) >+ mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j] >+ * mode_lib->vba.CursorBPP[k][j] / 8.0 >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) >+ * mode_lib->vba.VRatio[k]; >+ } >+ >+ do { >+ double MaxTotalRDBandwidth = 0; >+ bool DestinationLineTimesForPrefetchLessThan2 = false; >+ bool VRatioPrefetchMoreThan4 = false; >+ bool prefetch_vm_bw_valid = true; >+ bool prefetch_row_bw_valid = true; >+ double TWait = CalculateTWait( >+ mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], >+ mode_lib->vba.DRAMClockChangeLatency, >+ mode_lib->vba.UrgentLatencyPixelDataOnly, >+ mode_lib->vba.SREnterPlusExitTime); >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.XFCEnabled[k] == true) { >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = >+ CalculateRemoteSurfaceFlipDelay( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.SwathWidthY[k], >+ dml_ceil( >+ mode_lib->vba.BytePerPixelDETY[k], >+ 1), >+ mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.XFCTSlvVupdateOffset, >+ mode_lib->vba.XFCTSlvVupdateWidth, >+ mode_lib->vba.XFCTSlvVreadyOffset, >+ mode_lib->vba.XFCXBUFLatencyTolerance, >+ mode_lib->vba.XFCFillBWOverhead, >+ mode_lib->vba.XFCSlvChunkSize, >+ mode_lib->vba.XFCBusTransportTime, >+ mode_lib->vba.TCalc, >+ TWait, >+ &mode_lib->vba.SrcActiveDrainRate, >+ &mode_lib->vba.TInitXFill, >+ &mode_lib->vba.TslvChk); >+ } else { >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0; >+ } >+ >+ CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBW, mode_lib->vba.ReadBandwidthPlaneLuma[k], mode_lib->vba.ReadBandwidthPlaneChroma[k], mode_lib->vba.TotalDataReadBandwidth, >+ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k], >+ mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode_lib->vba.DPPPerPlane[k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], >+ mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, >+ mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], >+ mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]); >+ >+ mode_lib->vba.ErrorResult[k] = >+ CalculatePrefetchSchedule( >+ mode_lib, >+ mode_lib->vba.DPPCLK[k], >+ mode_lib->vba.DISPCLK, >+ mode_lib->vba.PixelClock[k], >+ mode_lib->vba.DCFCLKDeepSleep, >+ mode_lib->vba.DPPPerPlane[k], >+ mode_lib->vba.NumberOfCursors[k], >+ mode_lib->vba.VTotal[k] >+ - mode_lib->vba.VActive[k], >+ mode_lib->vba.HTotal[k], >+ mode_lib->vba.MaxInterDCNTileRepeaters, >+ dml_min( >+ mode_lib->vba.VStartupLines, >+ mode_lib->vba.MaxVStartupLines[k]), >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.DynamicMetadataEnable[k], >+ mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], >+ mode_lib->vba.DynamicMetadataTransmittedBytes[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.UrgentLatencyPixelDataOnly, >+ mode_lib->vba.UrgentExtraLatency, >+ mode_lib->vba.TCalc, >+ mode_lib->vba.PDEAndMetaPTEBytesFrame[k], >+ mode_lib->vba.MetaRowByte[k], >+ mode_lib->vba.PixelPTEBytesPerRow[k], >+ mode_lib->vba.PrefetchSourceLinesY[k], >+ mode_lib->vba.SwathWidthY[k], >+ mode_lib->vba.BytePerPixelDETY[k], >+ mode_lib->vba.VInitPreFillY[k], >+ mode_lib->vba.MaxNumSwathY[k], >+ mode_lib->vba.PrefetchSourceLinesC[k], >+ mode_lib->vba.BytePerPixelDETC[k], >+ mode_lib->vba.VInitPreFillC[k], >+ mode_lib->vba.MaxNumSwathC[k], >+ mode_lib->vba.SwathHeightY[k], >+ mode_lib->vba.SwathHeightC[k], >+ TWait, >+ mode_lib->vba.XFCEnabled[k], >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay, >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ mode_lib->vba.DSTXAfterScaler[k], >+ mode_lib->vba.DSTYAfterScaler[k], >+ &mode_lib->vba.DestinationLinesForPrefetch[k], >+ &mode_lib->vba.PrefetchBandwidth[k], >+ &mode_lib->vba.DestinationLinesToRequestVMInVBlank[k], >+ &mode_lib->vba.DestinationLinesToRequestRowInVBlank[k], >+ &mode_lib->vba.VRatioPrefetchY[k], >+ &mode_lib->vba.VRatioPrefetchC[k], >+ &mode_lib->vba.RequiredPrefetchPixDataBWLuma[k], >+ &mode_lib->vba.Tno_bw[k], >+ &mode_lib->vba.VUpdateOffsetPix[k], >+ &mode_lib->vba.VUpdateWidthPix[k], >+ &mode_lib->vba.VReadyOffsetPix[k]); >+ >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ mode_lib->vba.VStartup[k] = dml_min( >+ mode_lib->vba.VStartupLines, >+ mode_lib->vba.MaxVStartupLines[k]); >+ if (mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata >+ != 0) { >+ mode_lib->vba.VStartup[k] = >+ mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; >+ } >+ } else { >+ mode_lib->vba.VStartup[k] = >+ dml_min( >+ mode_lib->vba.VStartupLines, >+ mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ >+ if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0) >+ mode_lib->vba.prefetch_vm_bw[k] = 0; >+ else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) { >+ mode_lib->vba.prefetch_vm_bw[k] = >+ (double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k] >+ / (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]); >+ } else { >+ mode_lib->vba.prefetch_vm_bw[k] = 0; >+ prefetch_vm_bw_valid = false; >+ } >+ if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k] >+ == 0) >+ mode_lib->vba.prefetch_row_bw[k] = 0; >+ else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) { >+ mode_lib->vba.prefetch_row_bw[k] = >+ (double) (mode_lib->vba.MetaRowByte[k] >+ + mode_lib->vba.PixelPTEBytesPerRow[k]) >+ / (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]); >+ } else { >+ mode_lib->vba.prefetch_row_bw[k] = 0; >+ prefetch_row_bw_valid = false; >+ } >+ >+ MaxTotalRDBandwidth = >+ MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k] >+ + dml_max( >+ mode_lib->vba.prefetch_vm_bw[k], >+ dml_max( >+ mode_lib->vba.prefetch_row_bw[k], >+ dml_max( >+ mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k], >+ mode_lib->vba.RequiredPrefetchPixDataBWLuma[k]) >+ + mode_lib->vba.meta_row_bw[k] >+ + mode_lib->vba.dpte_row_bw[k])); >+ >+ if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2) >+ DestinationLineTimesForPrefetchLessThan2 = true; >+ if (mode_lib->vba.VRatioPrefetchY[k] > 4 >+ || mode_lib->vba.VRatioPrefetchC[k] > 4) >+ VRatioPrefetchMoreThan4 = true; >+ } >+ >+ if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && prefetch_vm_bw_valid >+ && prefetch_row_bw_valid && !VRatioPrefetchMoreThan4 >+ && !DestinationLineTimesForPrefetchLessThan2) >+ mode_lib->vba.PrefetchModeSupported = true; >+ else { >+ mode_lib->vba.PrefetchModeSupported = false; >+ dml_print( >+ "DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid\n"); >+ } >+ >+ if (mode_lib->vba.PrefetchModeSupported == true) { >+ double final_flip_bw[DC__NUM_DPP__MAX]; >+ unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX]; >+ double total_dcn_read_bw_with_flip = 0; >+ >+ mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.ReturnBW; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.BandwidthAvailableForImmediateFlip = >+ mode_lib->vba.BandwidthAvailableForImmediateFlip >+ - mode_lib->vba.cursor_bw[k] >+ - dml_max( >+ mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k] >+ + mode_lib->vba.qual_row_bw[k], >+ mode_lib->vba.PrefetchBandwidth[k]); >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ ImmediateFlipBytes[k] = 0; >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { >+ ImmediateFlipBytes[k] = >+ mode_lib->vba.PDEAndMetaPTEBytesFrame[k] >+ + mode_lib->vba.MetaRowByte[k] >+ + mode_lib->vba.PixelPTEBytesPerRow[k]; >+ } >+ } >+ mode_lib->vba.TotImmediateFlipBytes = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { >+ mode_lib->vba.TotImmediateFlipBytes = >+ mode_lib->vba.TotImmediateFlipBytes >+ + ImmediateFlipBytes[k]; >+ } >+ } >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ CalculateFlipSchedule( >+ mode_lib, >+ mode_lib->vba.UrgentExtraLatency, >+ mode_lib->vba.UrgentLatencyPixelDataOnly, >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.BandwidthAvailableForImmediateFlip, >+ mode_lib->vba.TotImmediateFlipBytes, >+ mode_lib->vba.SourcePixelFormat[k], >+ ImmediateFlipBytes[k], >+ mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.Tno_bw[k], >+ mode_lib->vba.PDEAndMetaPTEBytesFrame[k], >+ mode_lib->vba.MetaRowByte[k], >+ mode_lib->vba.PixelPTEBytesPerRow[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.dpte_row_height[k], >+ mode_lib->vba.meta_row_height[k], >+ mode_lib->vba.qual_row_bw[k], >+ &mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k], >+ &mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k], >+ &final_flip_bw[k], >+ &mode_lib->vba.ImmediateFlipSupportedForPipe[k]); >+ } >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ total_dcn_read_bw_with_flip = >+ total_dcn_read_bw_with_flip >+ + mode_lib->vba.cursor_bw[k] >+ + dml_max( >+ mode_lib->vba.prefetch_vm_bw[k], >+ dml_max( >+ mode_lib->vba.prefetch_row_bw[k], >+ final_flip_bw[k] >+ + dml_max( >+ mode_lib->vba.ReadBandwidthPlaneLuma[k] >+ + mode_lib->vba.ReadBandwidthPlaneChroma[k], >+ mode_lib->vba.RequiredPrefetchPixDataBWLuma[k]))); >+ } >+ mode_lib->vba.ImmediateFlipSupported = true; >+ if (total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) { >+ mode_lib->vba.ImmediateFlipSupported = false; >+ } >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) { >+ mode_lib->vba.ImmediateFlipSupported = false; >+ } >+ } >+ } else { >+ mode_lib->vba.ImmediateFlipSupported = false; >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.ErrorResult[k]) { >+ mode_lib->vba.PrefetchModeSupported = false; >+ dml_print( >+ "DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid\n"); >+ } >+ } >+ >+ mode_lib->vba.VStartupLines = mode_lib->vba.VStartupLines + 1; >+ } while (!((mode_lib->vba.PrefetchModeSupported >+ && (!mode_lib->vba.ImmediateFlipSupport >+ || mode_lib->vba.ImmediateFlipSupported)) >+ || mode_lib->vba.MaximumMaxVStartupLines < mode_lib->vba.VStartupLines)); >+ >+ //Display Pipeline Delivery Time in Prefetch >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.VRatioPrefetchY[k] <= 1) { >+ mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = >+ mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k] >+ / mode_lib->vba.HRatio[k] >+ / mode_lib->vba.PixelClock[k]; >+ } else { >+ mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = >+ mode_lib->vba.SwathWidthY[k] >+ / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] >+ / mode_lib->vba.DPPCLK[k]; >+ } >+ if (mode_lib->vba.BytePerPixelDETC[k] == 0) { >+ mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0; >+ } else { >+ if (mode_lib->vba.VRatioPrefetchC[k] <= 1) { >+ mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = >+ mode_lib->vba.SwathWidthY[k] >+ * mode_lib->vba.DPPPerPlane[k] >+ / mode_lib->vba.HRatio[k] >+ / mode_lib->vba.PixelClock[k]; >+ } else { >+ mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = >+ mode_lib->vba.SwathWidthY[k] >+ / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] >+ / mode_lib->vba.DPPCLK[k]; >+ } >+ } >+ } >+ >+ // Min TTUVBlank >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) { >+ mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true; >+ mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true; >+ mode_lib->vba.MinTTUVBlank[k] = dml_max( >+ mode_lib->vba.DRAMClockChangeWatermark, >+ dml_max( >+ mode_lib->vba.StutterEnterPlusExitWatermark, >+ mode_lib->vba.UrgentWatermark)); >+ } else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) { >+ mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false; >+ mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true; >+ mode_lib->vba.MinTTUVBlank[k] = dml_max( >+ mode_lib->vba.StutterEnterPlusExitWatermark, >+ mode_lib->vba.UrgentWatermark); >+ } else { >+ mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false; >+ mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false; >+ mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark; >+ } >+ if (!mode_lib->vba.DynamicMetadataEnable[k]) >+ mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc >+ + mode_lib->vba.MinTTUVBlank[k]; >+ } >+ >+ // DCC Configuration >+ mode_lib->vba.ActiveDPPs = 0; >+ // NB P-State/DRAM Clock Change Support >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k]; >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ double EffectiveLBLatencyHidingY; >+ double EffectiveLBLatencyHidingC; >+ double DPPOutputBufferLinesY; >+ double DPPOutputBufferLinesC; >+ double DPPOPPBufferingY; >+ double MaxDETBufferingTimeY; >+ double ActiveDRAMClockChangeLatencyMarginY; >+ >+ mode_lib->vba.LBLatencyHidingSourceLinesY = >+ dml_min( >+ mode_lib->vba.MaxLineBufferLines, >+ (unsigned int) dml_floor( >+ (double) mode_lib->vba.LineBufferSize >+ / mode_lib->vba.LBBitPerPixel[k] >+ / (mode_lib->vba.SwathWidthY[k] >+ / dml_max( >+ mode_lib->vba.HRatio[k], >+ 1.0)), >+ 1)) - (mode_lib->vba.vtaps[k] - 1); >+ >+ mode_lib->vba.LBLatencyHidingSourceLinesC = >+ dml_min( >+ mode_lib->vba.MaxLineBufferLines, >+ (unsigned int) dml_floor( >+ (double) mode_lib->vba.LineBufferSize >+ / mode_lib->vba.LBBitPerPixel[k] >+ / (mode_lib->vba.SwathWidthY[k] >+ / 2.0 >+ / dml_max( >+ mode_lib->vba.HRatio[k] >+ / 2, >+ 1.0)), >+ 1)) >+ - (mode_lib->vba.VTAPsChroma[k] - 1); >+ >+ EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY >+ / mode_lib->vba.VRatio[k] >+ * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); >+ >+ EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC >+ / (mode_lib->vba.VRatio[k] / 2) >+ * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); >+ >+ if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) { >+ DPPOutputBufferLinesY = mode_lib->vba.DPPOutputBufferPixels >+ / mode_lib->vba.SwathWidthY[k]; >+ } else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) { >+ DPPOutputBufferLinesY = 0.5; >+ } else { >+ DPPOutputBufferLinesY = 1; >+ } >+ >+ if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) { >+ DPPOutputBufferLinesC = mode_lib->vba.DPPOutputBufferPixels >+ / (mode_lib->vba.SwathWidthY[k] / 2); >+ } else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) { >+ DPPOutputBufferLinesC = 0.5; >+ } else { >+ DPPOutputBufferLinesC = 1; >+ } >+ >+ DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) >+ * (DPPOutputBufferLinesY + mode_lib->vba.OPPOutputBufferLines); >+ MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k] >+ + (mode_lib->vba.LinesInDETY[k] >+ - mode_lib->vba.LinesInDETYRoundedDownToSwath[k]) >+ / mode_lib->vba.SwathHeightY[k] >+ * (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]); >+ >+ ActiveDRAMClockChangeLatencyMarginY = DPPOPPBufferingY + EffectiveLBLatencyHidingY >+ + MaxDETBufferingTimeY - mode_lib->vba.DRAMClockChangeWatermark; >+ >+ if (mode_lib->vba.ActiveDPPs > 1) { >+ ActiveDRAMClockChangeLatencyMarginY = >+ ActiveDRAMClockChangeLatencyMarginY >+ - (1 - 1 / (mode_lib->vba.ActiveDPPs - 1)) >+ * mode_lib->vba.SwathHeightY[k] >+ * (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]); >+ } >+ >+ if (mode_lib->vba.BytePerPixelDETC[k] > 0) { >+ double DPPOPPBufferingC = (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) >+ * (DPPOutputBufferLinesC >+ + mode_lib->vba.OPPOutputBufferLines); >+ double MaxDETBufferingTimeC = >+ mode_lib->vba.FullDETBufferingTimeC[k] >+ + (mode_lib->vba.LinesInDETC[k] >+ - mode_lib->vba.LinesInDETCRoundedDownToSwath[k]) >+ / mode_lib->vba.SwathHeightC[k] >+ * (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]); >+ double ActiveDRAMClockChangeLatencyMarginC = DPPOPPBufferingC >+ + EffectiveLBLatencyHidingC + MaxDETBufferingTimeC >+ - mode_lib->vba.DRAMClockChangeWatermark; >+ >+ if (mode_lib->vba.ActiveDPPs > 1) { >+ ActiveDRAMClockChangeLatencyMarginC = >+ ActiveDRAMClockChangeLatencyMarginC >+ - (1 >+ - 1 >+ / (mode_lib->vba.ActiveDPPs >+ - 1)) >+ * mode_lib->vba.SwathHeightC[k] >+ * (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]); >+ } >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( >+ ActiveDRAMClockChangeLatencyMarginY, >+ ActiveDRAMClockChangeLatencyMarginC); >+ } else { >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = >+ ActiveDRAMClockChangeLatencyMarginY; >+ } >+ >+ if (mode_lib->vba.WritebackEnable[k]) { >+ double WritebackDRAMClockChangeLatencyMargin; >+ >+ if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { >+ WritebackDRAMClockChangeLatencyMargin = >+ (double) (mode_lib->vba.WritebackInterfaceLumaBufferSize >+ + mode_lib->vba.WritebackInterfaceChromaBufferSize) >+ / (mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) >+ * 4) >+ - mode_lib->vba.WritebackDRAMClockChangeWatermark; >+ } else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { >+ WritebackDRAMClockChangeLatencyMargin = >+ dml_min( >+ (double) mode_lib->vba.WritebackInterfaceLumaBufferSize >+ * 8.0 / 10, >+ 2.0 >+ * mode_lib->vba.WritebackInterfaceChromaBufferSize >+ * 8 / 10) >+ / (mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k])) >+ - mode_lib->vba.WritebackDRAMClockChangeWatermark; >+ } else { >+ WritebackDRAMClockChangeLatencyMargin = >+ dml_min( >+ (double) mode_lib->vba.WritebackInterfaceLumaBufferSize, >+ 2.0 >+ * mode_lib->vba.WritebackInterfaceChromaBufferSize) >+ / (mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k])) >+ - mode_lib->vba.WritebackDRAMClockChangeWatermark; >+ } >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], >+ WritebackDRAMClockChangeLatencyMargin); >+ } >+ } >+ >+ mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] >+ < mode_lib->vba.MinActiveDRAMClockChangeMargin) { >+ mode_lib->vba.MinActiveDRAMClockChangeMargin = >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; >+ } >+ } >+ >+ mode_lib->vba.MinActiveDRAMClockChangeLatencySupported = >+ mode_lib->vba.MinActiveDRAMClockChangeMargin >+ + mode_lib->vba.DRAMClockChangeLatency; >+ >+ if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) { >+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; >+ } else { >+ if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) { >+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vblank; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) { >+ mode_lib->vba.DRAMClockChangeSupport[0][0] = >+ dm_dram_clock_change_unsupported; >+ } >+ } >+ } else { >+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_unsupported; >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.soc.num_states; k++) >+ for (j = 0; j < 2; j++) >+ mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0]; >+ >+ //XFC Parameters: >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.XFCEnabled[k] == true) { >+ double TWait; >+ >+ mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset; >+ mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth; >+ mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset; >+ TWait = CalculateTWait( >+ mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], >+ mode_lib->vba.DRAMClockChangeLatency, >+ mode_lib->vba.UrgentLatencyPixelDataOnly, >+ mode_lib->vba.SREnterPlusExitTime); >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = CalculateRemoteSurfaceFlipDelay( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.SwathWidthY[k], >+ dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.XFCTSlvVupdateOffset, >+ mode_lib->vba.XFCTSlvVupdateWidth, >+ mode_lib->vba.XFCTSlvVreadyOffset, >+ mode_lib->vba.XFCXBUFLatencyTolerance, >+ mode_lib->vba.XFCFillBWOverhead, >+ mode_lib->vba.XFCSlvChunkSize, >+ mode_lib->vba.XFCBusTransportTime, >+ mode_lib->vba.TCalc, >+ TWait, >+ &mode_lib->vba.SrcActiveDrainRate, >+ &mode_lib->vba.TInitXFill, >+ &mode_lib->vba.TslvChk); >+ mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = >+ dml_floor( >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay >+ / (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]), >+ 1); >+ mode_lib->vba.XFCTransferDelay[k] = >+ dml_ceil( >+ mode_lib->vba.XFCBusTransportTime >+ / (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]), >+ 1); >+ mode_lib->vba.XFCPrechargeDelay[k] = >+ dml_ceil( >+ (mode_lib->vba.XFCBusTransportTime >+ + mode_lib->vba.TInitXFill >+ + mode_lib->vba.TslvChk) >+ / (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]), >+ 1); >+ mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance >+ * mode_lib->vba.SrcActiveDrainRate; >+ mode_lib->vba.FinalFillMargin = >+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] >+ + mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]) >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k] >+ * mode_lib->vba.SrcActiveDrainRate >+ + mode_lib->vba.XFCFillConstant; >+ mode_lib->vba.FinalFillLevel = mode_lib->vba.XFCRemoteSurfaceFlipDelay >+ * mode_lib->vba.SrcActiveDrainRate >+ + mode_lib->vba.FinalFillMargin; >+ mode_lib->vba.RemainingFillLevel = dml_max( >+ 0.0, >+ mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel); >+ mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel >+ / (mode_lib->vba.SrcActiveDrainRate >+ * mode_lib->vba.XFCFillBWOverhead / 100); >+ mode_lib->vba.XFCPrefetchMargin[k] = >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay >+ + mode_lib->vba.TFinalxFill >+ + (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] >+ + mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]) >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]; >+ } else { >+ mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0; >+ mode_lib->vba.XFCSlaveVupdateWidth[k] = 0; >+ mode_lib->vba.XFCSlaveVReadyOffset[k] = 0; >+ mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0; >+ mode_lib->vba.XFCPrechargeDelay[k] = 0; >+ mode_lib->vba.XFCTransferDelay[k] = 0; >+ mode_lib->vba.XFCPrefetchMargin[k] = 0; >+ } >+ } >+ { >+ unsigned int VStartupMargin = 0; >+ bool FirstMainPlane = true; >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) >+ * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; >+ >+ if (FirstMainPlane) { >+ VStartupMargin = Margin; >+ FirstMainPlane = false; >+ } else >+ VStartupMargin = dml_min(VStartupMargin, Margin); >+ } >+ >+ if (mode_lib->vba.UseMaximumVStartup) { >+ if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) { >+ //only use max vstart if it is not drr or lateflip. >+ mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]; >+ } >+ } >+ } >+} >+} >+ >+static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) >+{ >+ double BytePerPixDETY; >+ double BytePerPixDETC; >+ double Read256BytesBlockHeightY; >+ double Read256BytesBlockHeightC; >+ double Read256BytesBlockWidthY; >+ double Read256BytesBlockWidthC; >+ double MaximumSwathHeightY; >+ double MaximumSwathHeightC; >+ double MinimumSwathHeightY; >+ double MinimumSwathHeightC; >+ double SwathWidth; >+ double SwathWidthGranularityY; >+ double SwathWidthGranularityC; >+ double RoundedUpMaxSwathSizeBytesY; >+ double RoundedUpMaxSwathSizeBytesC; >+ unsigned int j, k; >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ bool MainPlaneDoesODMCombine = false; >+ >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { >+ BytePerPixDETY = 8; >+ BytePerPixDETC = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { >+ BytePerPixDETY = 4; >+ BytePerPixDETC = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { >+ BytePerPixDETY = 2; >+ BytePerPixDETC = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) { >+ BytePerPixDETY = 1; >+ BytePerPixDETC = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { >+ BytePerPixDETY = 1; >+ BytePerPixDETC = 2; >+ } else { >+ BytePerPixDETY = 4.0 / 3.0; >+ BytePerPixDETC = 8.0 / 3.0; >+ } >+ >+ if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ Read256BytesBlockHeightY = 1; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { >+ Read256BytesBlockHeightY = 4; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { >+ Read256BytesBlockHeightY = 8; >+ } else { >+ Read256BytesBlockHeightY = 16; >+ } >+ Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1) >+ / Read256BytesBlockHeightY; >+ Read256BytesBlockHeightC = 0; >+ Read256BytesBlockWidthC = 0; >+ } else { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ Read256BytesBlockHeightY = 1; >+ Read256BytesBlockHeightC = 1; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { >+ Read256BytesBlockHeightY = 16; >+ Read256BytesBlockHeightC = 8; >+ } else { >+ Read256BytesBlockHeightY = 8; >+ Read256BytesBlockHeightC = 8; >+ } >+ Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1) >+ / Read256BytesBlockHeightY; >+ Read256BytesBlockWidthC = 256 / dml_ceil(BytePerPixDETC, 2) >+ / Read256BytesBlockHeightC; >+ } >+ >+ if (mode_lib->vba.SourceScan[k] == dm_horz) { >+ MaximumSwathHeightY = Read256BytesBlockHeightY; >+ MaximumSwathHeightC = Read256BytesBlockHeightC; >+ } else { >+ MaximumSwathHeightY = Read256BytesBlockWidthY; >+ MaximumSwathHeightC = Read256BytesBlockWidthC; >+ } >+ >+ if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear >+ || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ && (mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_4kb_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_4kb_s_x >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s_t >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s_x >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_var_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_var_s_x) >+ && mode_lib->vba.SourceScan[k] == dm_horz)) { >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 >+ && mode_lib->vba.SourceScan[k] != dm_horz) { >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ } else { >+ MinimumSwathHeightY = MaximumSwathHeightY / 2.0; >+ } >+ MinimumSwathHeightC = MaximumSwathHeightC; >+ } else { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ MinimumSwathHeightC = MaximumSwathHeightC; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 >+ && mode_lib->vba.SourceScan[k] == dm_horz) { >+ MinimumSwathHeightY = MaximumSwathHeightY / 2.0; >+ MinimumSwathHeightC = MaximumSwathHeightC; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 >+ && mode_lib->vba.SourceScan[k] == dm_horz) { >+ MinimumSwathHeightC = MaximumSwathHeightC / 2.0; >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ } else { >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ MinimumSwathHeightC = MaximumSwathHeightC; >+ } >+ } >+ >+ if (mode_lib->vba.SourceScan[k] == dm_horz) { >+ SwathWidth = mode_lib->vba.ViewportWidth[k]; >+ } else { >+ SwathWidth = mode_lib->vba.ViewportHeight[k]; >+ } >+ >+ if (mode_lib->vba.ODMCombineEnabled[k] == true) { >+ MainPlaneDoesODMCombine = true; >+ } >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) { >+ if (mode_lib->vba.BlendingAndTiming[k] == j >+ && mode_lib->vba.ODMCombineEnabled[j] == true) { >+ MainPlaneDoesODMCombine = true; >+ } >+ } >+ >+ if (MainPlaneDoesODMCombine == true) { >+ SwathWidth = dml_min( >+ SwathWidth, >+ mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]); >+ } else { >+ if (mode_lib->vba.DPPPerPlane[k] == 0) >+ SwathWidth = 0; >+ else >+ SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k]; >+ } >+ >+ SwathWidthGranularityY = 256 / dml_ceil(BytePerPixDETY, 1) / MaximumSwathHeightY; >+ RoundedUpMaxSwathSizeBytesY = (dml_ceil( >+ (double) (SwathWidth - 1), >+ SwathWidthGranularityY) + SwathWidthGranularityY) * BytePerPixDETY >+ * MaximumSwathHeightY; >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { >+ RoundedUpMaxSwathSizeBytesY = dml_ceil(RoundedUpMaxSwathSizeBytesY, 256) >+ + 256; >+ } >+ if (MaximumSwathHeightC > 0) { >+ SwathWidthGranularityC = 256.0 / dml_ceil(BytePerPixDETC, 2) >+ / MaximumSwathHeightC; >+ RoundedUpMaxSwathSizeBytesC = (dml_ceil( >+ (double) (SwathWidth / 2.0 - 1), >+ SwathWidthGranularityC) + SwathWidthGranularityC) >+ * BytePerPixDETC * MaximumSwathHeightC; >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { >+ RoundedUpMaxSwathSizeBytesC = dml_ceil( >+ RoundedUpMaxSwathSizeBytesC, >+ 256) + 256; >+ } >+ } else >+ RoundedUpMaxSwathSizeBytesC = 0.0; >+ >+ if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC >+ <= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) { >+ mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; >+ mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; >+ } else { >+ mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; >+ mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; >+ } >+ >+ if (mode_lib->vba.SwathHeightC[k] == 0) { >+ mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024; >+ mode_lib->vba.DETBufferSizeC[k] = 0; >+ } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { >+ mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte >+ * 1024.0 / 2; >+ mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte >+ * 1024.0 / 2; >+ } else { >+ mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte >+ * 1024.0 * 2 / 3; >+ mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte >+ * 1024.0 / 3; >+ } >+ } >+} >+ >+static double CalculateTWait( >+ unsigned int PrefetchMode, >+ double DRAMClockChangeLatency, >+ double UrgentLatencyPixelDataOnly, >+ double SREnterPlusExitTime) >+{ >+ if (PrefetchMode == 0) { >+ return dml_max( >+ DRAMClockChangeLatency + UrgentLatencyPixelDataOnly, >+ dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly)); >+ } else if (PrefetchMode == 1) { >+ return dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly); >+ } else { >+ return UrgentLatencyPixelDataOnly; >+ } >+} >+ >+static double CalculateRemoteSurfaceFlipDelay( >+ struct display_mode_lib *mode_lib, >+ double VRatio, >+ double SwathWidth, >+ double Bpp, >+ double LineTime, >+ double XFCTSlvVupdateOffset, >+ double XFCTSlvVupdateWidth, >+ double XFCTSlvVreadyOffset, >+ double XFCXBUFLatencyTolerance, >+ double XFCFillBWOverhead, >+ double XFCSlvChunkSize, >+ double XFCBusTransportTime, >+ double TCalc, >+ double TWait, >+ double *SrcActiveDrainRate, >+ double *TInitXFill, >+ double *TslvChk) >+{ >+ double TSlvSetup, AvgfillRate, result; >+ >+ *SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime; >+ TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth + XFCTSlvVreadyOffset; >+ *TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100); >+ AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100); >+ *TslvChk = XFCSlvChunkSize / AvgfillRate; >+ dml_print( >+ "DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f\n", >+ *SrcActiveDrainRate); >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n", TSlvSetup); >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n", *TInitXFill); >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n", AvgfillRate); >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n", *TslvChk); >+ result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk + *TInitXFill; // TODO: This doesn't seem to match programming guide >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f\n", result); >+ return result; >+} >+ >+static double CalculateWriteBackDelay( >+ enum source_format_class WritebackPixelFormat, >+ double WritebackHRatio, >+ double WritebackVRatio, >+ unsigned int WritebackLumaHTaps, >+ unsigned int WritebackLumaVTaps, >+ unsigned int WritebackChromaHTaps, >+ unsigned int WritebackChromaVTaps, >+ unsigned int WritebackDestinationWidth) >+{ >+ double CalculateWriteBackDelay = >+ dml_max( >+ dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio, >+ WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) >+ * dml_ceil( >+ WritebackDestinationWidth >+ / 4.0, >+ 1) >+ + dml_ceil(1.0 / WritebackVRatio, 1) >+ * (dml_ceil( >+ WritebackLumaVTaps >+ / 4.0, >+ 1) + 4)); >+ >+ if (WritebackPixelFormat != dm_444_32) { >+ CalculateWriteBackDelay = >+ dml_max( >+ CalculateWriteBackDelay, >+ dml_max( >+ dml_ceil( >+ WritebackChromaHTaps >+ / 2.0, >+ 1) >+ / (2 >+ * WritebackHRatio), >+ WritebackChromaVTaps >+ * dml_ceil( >+ 1 >+ / (2 >+ * WritebackVRatio), >+ 1) >+ * dml_ceil( >+ WritebackDestinationWidth >+ / 2.0 >+ / 2.0, >+ 1) >+ + dml_ceil( >+ 1 >+ / (2 >+ * WritebackVRatio), >+ 1) >+ * (dml_ceil( >+ WritebackChromaVTaps >+ / 4.0, >+ 1) >+ + 4))); >+ } >+ return CalculateWriteBackDelay; >+} >+ >+static void CalculateActiveRowBandwidth( >+ bool GPUVMEnable, >+ enum source_format_class SourcePixelFormat, >+ double VRatio, >+ bool DCCEnable, >+ double LineTime, >+ unsigned int MetaRowByteLuma, >+ unsigned int MetaRowByteChroma, >+ unsigned int meta_row_height_luma, >+ unsigned int meta_row_height_chroma, >+ unsigned int PixelPTEBytesPerRowLuma, >+ unsigned int PixelPTEBytesPerRowChroma, >+ unsigned int dpte_row_height_luma, >+ unsigned int dpte_row_height_chroma, >+ double *meta_row_bw, >+ double *dpte_row_bw, >+ double *qual_row_bw) >+{ >+ if (DCCEnable != true) { >+ *meta_row_bw = 0; >+ } else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) { >+ *meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime) >+ + VRatio / 2 * MetaRowByteChroma >+ / (meta_row_height_chroma * LineTime); >+ } else { >+ *meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime); >+ } >+ >+ if (GPUVMEnable != true) { >+ *dpte_row_bw = 0; >+ } else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) { >+ *dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime) >+ + VRatio / 2 * PixelPTEBytesPerRowChroma >+ / (dpte_row_height_chroma * LineTime); >+ } else { >+ *dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime); >+ } >+ >+ if ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10)) { >+ *qual_row_bw = *meta_row_bw + *dpte_row_bw; >+ } else { >+ *qual_row_bw = 0; >+ } >+} >+ >+static void CalculateFlipSchedule( >+ struct display_mode_lib *mode_lib, >+ double UrgentExtraLatency, >+ double UrgentLatencyPixelDataOnly, >+ unsigned int GPUVMMaxPageTableLevels, >+ bool GPUVMEnable, >+ double BandwidthAvailableForImmediateFlip, >+ unsigned int TotImmediateFlipBytes, >+ enum source_format_class SourcePixelFormat, >+ unsigned int ImmediateFlipBytes, >+ double LineTime, >+ double VRatio, >+ double Tno_bw, >+ double PDEAndMetaPTEBytesFrame, >+ unsigned int MetaRowByte, >+ unsigned int PixelPTEBytesPerRow, >+ bool DCCEnable, >+ unsigned int dpte_row_height, >+ unsigned int meta_row_height, >+ double qual_row_bw, >+ double *DestinationLinesToRequestVMInImmediateFlip, >+ double *DestinationLinesToRequestRowInImmediateFlip, >+ double *final_flip_bw, >+ bool *ImmediateFlipSupportedForPipe) >+{ >+ double min_row_time = 0.0; >+ >+ if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) { >+ *DestinationLinesToRequestVMInImmediateFlip = 0.0; >+ *DestinationLinesToRequestRowInImmediateFlip = 0.0; >+ *final_flip_bw = qual_row_bw; >+ *ImmediateFlipSupportedForPipe = true; >+ } else { >+ double TimeForFetchingMetaPTEImmediateFlip; >+ double TimeForFetchingRowInVBlankImmediateFlip; >+ >+ if (GPUVMEnable == true) { >+ mode_lib->vba.ImmediateFlipBW[0] = BandwidthAvailableForImmediateFlip >+ * ImmediateFlipBytes / TotImmediateFlipBytes; >+ TimeForFetchingMetaPTEImmediateFlip = >+ dml_max( >+ Tno_bw >+ + PDEAndMetaPTEBytesFrame >+ / mode_lib->vba.ImmediateFlipBW[0], >+ dml_max( >+ UrgentExtraLatency >+ + UrgentLatencyPixelDataOnly >+ * (GPUVMMaxPageTableLevels >+ - 1), >+ LineTime / 4.0)); >+ } else { >+ TimeForFetchingMetaPTEImmediateFlip = 0; >+ } >+ >+ *DestinationLinesToRequestVMInImmediateFlip = dml_floor( >+ 4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime + 0.125), >+ 1) / 4.0; >+ >+ if ((GPUVMEnable == true || DCCEnable == true)) { >+ mode_lib->vba.ImmediateFlipBW[0] = BandwidthAvailableForImmediateFlip >+ * ImmediateFlipBytes / TotImmediateFlipBytes; >+ TimeForFetchingRowInVBlankImmediateFlip = dml_max( >+ (MetaRowByte + PixelPTEBytesPerRow) >+ / mode_lib->vba.ImmediateFlipBW[0], >+ dml_max(UrgentLatencyPixelDataOnly, LineTime / 4.0)); >+ } else { >+ TimeForFetchingRowInVBlankImmediateFlip = 0; >+ } >+ >+ *DestinationLinesToRequestRowInImmediateFlip = dml_floor( >+ 4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime + 0.125), >+ 1) / 4.0; >+ >+ if (GPUVMEnable == true) { >+ *final_flip_bw = >+ dml_max( >+ PDEAndMetaPTEBytesFrame >+ / (*DestinationLinesToRequestVMInImmediateFlip >+ * LineTime), >+ (MetaRowByte + PixelPTEBytesPerRow) >+ / (TimeForFetchingRowInVBlankImmediateFlip >+ * LineTime)); >+ } else if (MetaRowByte + PixelPTEBytesPerRow > 0) { >+ *final_flip_bw = (MetaRowByte + PixelPTEBytesPerRow) >+ / (TimeForFetchingRowInVBlankImmediateFlip * LineTime); >+ } else { >+ *final_flip_bw = 0; >+ } >+ >+ if (GPUVMEnable && !DCCEnable) >+ min_row_time = dpte_row_height * LineTime / VRatio; >+ else if (!GPUVMEnable && DCCEnable) >+ min_row_time = meta_row_height * LineTime / VRatio; >+ else >+ min_row_time = dml_min(dpte_row_height, meta_row_height) * LineTime >+ / VRatio; >+ >+ if (*DestinationLinesToRequestVMInImmediateFlip >= 8 >+ || *DestinationLinesToRequestRowInImmediateFlip >= 16 >+ || TimeForFetchingMetaPTEImmediateFlip >+ + 2 * TimeForFetchingRowInVBlankImmediateFlip >+ > min_row_time) >+ *ImmediateFlipSupportedForPipe = false; >+ else >+ *ImmediateFlipSupportedForPipe = true; >+ } >+} >+ >+static unsigned int TruncToValidBPP( >+ double DecimalBPP, >+ bool DSCEnabled, >+ enum output_encoder_class Output, >+ enum output_format_class Format, >+ unsigned int DSCInputBitPerComponent) >+{ >+ if (Output == dm_hdmi) { >+ if (Format == dm_420) { >+ if (DecimalBPP >= 18) >+ return 18; >+ else if (DecimalBPP >= 15) >+ return 15; >+ else if (DecimalBPP >= 12) >+ return 12; >+ else >+ return BPP_INVALID; >+ } else if (Format == dm_444) { >+ if (DecimalBPP >= 36) >+ return 36; >+ else if (DecimalBPP >= 30) >+ return 30; >+ else if (DecimalBPP >= 24) >+ return 24; >+ else if (DecimalBPP >= 18) >+ return 18; >+ else >+ return BPP_INVALID; >+ } else { >+ if (DecimalBPP / 1.5 >= 24) >+ return 24; >+ else if (DecimalBPP / 1.5 >= 20) >+ return 20; >+ else if (DecimalBPP / 1.5 >= 16) >+ return 16; >+ else >+ return BPP_INVALID; >+ } >+ } else { >+ if (DSCEnabled) { >+ if (Format == dm_420) { >+ if (DecimalBPP < 6) >+ return BPP_INVALID; >+ else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1 / 16) >+ return 1.5 * DSCInputBitPerComponent - 1 / 16; >+ else >+ return dml_floor(16 * DecimalBPP, 1) / 16; >+ } else if (Format == dm_n422) { >+ if (DecimalBPP < 7) >+ return BPP_INVALID; >+ else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1 / 16) >+ return 2 * DSCInputBitPerComponent - 1 / 16; >+ else >+ return dml_floor(16 * DecimalBPP, 1) / 16; >+ } else { >+ if (DecimalBPP < 8) >+ return BPP_INVALID; >+ else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1 / 16) >+ return 3 * DSCInputBitPerComponent - 1 / 16; >+ else >+ return dml_floor(16 * DecimalBPP, 1) / 16; >+ } >+ } else if (Format == dm_420) { >+ if (DecimalBPP >= 18) >+ return 18; >+ else if (DecimalBPP >= 15) >+ return 15; >+ else if (DecimalBPP >= 12) >+ return 12; >+ else >+ return BPP_INVALID; >+ } else if (Format == dm_s422 || Format == dm_n422) { >+ if (DecimalBPP >= 24) >+ return 24; >+ else if (DecimalBPP >= 20) >+ return 20; >+ else if (DecimalBPP >= 16) >+ return 16; >+ else >+ return BPP_INVALID; >+ } else { >+ if (DecimalBPP >= 36) >+ return 36; >+ else if (DecimalBPP >= 30) >+ return 30; >+ else if (DecimalBPP >= 24) >+ return 24; >+ else if (DecimalBPP >= 18) >+ return 18; >+ else >+ return BPP_INVALID; >+ } >+ } >+} >+ >+void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) >+{ >+ struct vba_vars_st *locals = &mode_lib->vba; >+ >+ int i; >+ unsigned int j, k, m; >+ >+ /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ >+ >+ /*Scale Ratio, taps Support Check*/ >+ >+ mode_lib->vba.ScaleRatioAndTapsSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.ScalerEnabled[k] == false >+ && ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) >+ || mode_lib->vba.HRatio[k] != 1.0 >+ || mode_lib->vba.htaps[k] != 1.0 >+ || mode_lib->vba.VRatio[k] != 1.0 >+ || mode_lib->vba.vtaps[k] != 1.0)) { >+ mode_lib->vba.ScaleRatioAndTapsSupport = false; >+ } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 >+ || mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0 >+ || (mode_lib->vba.htaps[k] > 1.0 >+ && (mode_lib->vba.htaps[k] % 2) == 1) >+ || mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio >+ || mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio >+ || mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k] >+ || mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k] >+ || (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8 >+ && (mode_lib->vba.HRatio[k] / 2.0 >+ > mode_lib->vba.HTAPsChroma[k] >+ || mode_lib->vba.VRatio[k] / 2.0 >+ > mode_lib->vba.VTAPsChroma[k]))) { >+ mode_lib->vba.ScaleRatioAndTapsSupport = false; >+ } >+ } >+ /*Source Format, Pixel Format and Scan Support Check*/ >+ >+ mode_lib->vba.SourceFormatPixelAndScanSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear >+ && mode_lib->vba.SourceScan[k] != dm_horz) >+ || ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x) >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_64) >+ || (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x >+ && (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8 >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_420_8 >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_420_10)) >+ || (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_gfx7_2d_thin_lvp) >+ && !((mode_lib->vba.SourcePixelFormat[k] >+ == dm_444_64 >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_444_32) >+ && mode_lib->vba.SourceScan[k] >+ == dm_horz >+ && mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp >+ == true >+ && mode_lib->vba.DCCEnable[k] >+ == false)) >+ || (mode_lib->vba.DCCEnable[k] == true >+ && (mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_linear >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_420_8 >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_420_10)))) { >+ mode_lib->vba.SourceFormatPixelAndScanSupport = false; >+ } >+ } >+ /*Bandwidth Support Check*/ >+ >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { >+ locals->BytePerPixelInDETY[k] = 8.0; >+ locals->BytePerPixelInDETC[k] = 0.0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { >+ locals->BytePerPixelInDETY[k] = 4.0; >+ locals->BytePerPixelInDETC[k] = 0.0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) { >+ locals->BytePerPixelInDETY[k] = 2.0; >+ locals->BytePerPixelInDETC[k] = 0.0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) { >+ locals->BytePerPixelInDETY[k] = 1.0; >+ locals->BytePerPixelInDETC[k] = 0.0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { >+ locals->BytePerPixelInDETY[k] = 1.0; >+ locals->BytePerPixelInDETC[k] = 2.0; >+ } else { >+ locals->BytePerPixelInDETY[k] = 4.0 / 3; >+ locals->BytePerPixelInDETC[k] = 8.0 / 3; >+ } >+ if (mode_lib->vba.SourceScan[k] == dm_horz) { >+ locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k]; >+ } else { >+ locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k]; >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0) >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; >+ locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0) >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0; >+ locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k]; >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true >+ && mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { >+ locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) * 4.0; >+ } else if (mode_lib->vba.WritebackEnable[k] == true >+ && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { >+ locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) * 3.0; >+ } else if (mode_lib->vba.WritebackEnable[k] == true) { >+ locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) * 1.5; >+ } else { >+ locals->WriteBandwidth[k] = 0.0; >+ } >+ } >+ mode_lib->vba.DCCEnabledInAnyPlane = false; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.DCCEnable[k] == true) { >+ mode_lib->vba.DCCEnabledInAnyPlane = true; >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->FabricAndDRAMBandwidthPerState[i] = dml_min( >+ mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels >+ * mode_lib->vba.DRAMChannelWidth, >+ mode_lib->vba.FabricClockPerState[i] >+ * mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000; >+ locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth * locals->DCFCLKPerState[i], >+ locals->FabricAndDRAMBandwidthPerState[i] * 1000) >+ * locals->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100; >+ >+ locals->ReturnBWPerState[i] = locals->ReturnBWToDCNPerState; >+ >+ if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) { >+ locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i], >+ locals->ReturnBWToDCNPerState * 4 * (1 - locals->UrgentLatency / >+ ((locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024 >+ / (locals->ReturnBWToDCNPerState - locals->DCFCLKPerState[i] >+ * locals->ReturnBusWidth / 4) + locals->UrgentLatency))); >+ } >+ locals->CriticalPoint = 2 * locals->ReturnBusWidth * locals->DCFCLKPerState[i] * >+ locals->UrgentLatency / (locals->ReturnBWToDCNPerState * locals->UrgentLatency >+ + (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024); >+ >+ if (locals->DCCEnabledInAnyPlane && locals->CriticalPoint > 1 && locals->CriticalPoint < 4) { >+ locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i], >+ 4 * locals->ReturnBWToDCNPerState * >+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024 >+ * locals->ReturnBusWidth * locals->DCFCLKPerState[i] * locals->UrgentLatency / >+ dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency >+ + (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024), 2)); >+ } >+ >+ locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth * >+ locals->DCFCLKPerState[i], locals->FabricAndDRAMBandwidthPerState[i] * 1000); >+ >+ if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) { >+ locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i], >+ locals->ReturnBWToDCNPerState * 4 * (1 - locals->UrgentLatency / >+ ((locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024 >+ / (locals->ReturnBWToDCNPerState - locals->DCFCLKPerState[i] >+ * locals->ReturnBusWidth / 4) + locals->UrgentLatency))); >+ } >+ locals->CriticalPoint = 2 * locals->ReturnBusWidth * locals->DCFCLKPerState[i] * >+ locals->UrgentLatency / (locals->ReturnBWToDCNPerState * locals->UrgentLatency >+ + (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024); >+ >+ if (locals->DCCEnabledInAnyPlane && locals->CriticalPoint > 1 && locals->CriticalPoint < 4) { >+ locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i], >+ 4 * locals->ReturnBWToDCNPerState * >+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024 >+ * locals->ReturnBusWidth * locals->DCFCLKPerState[i] * locals->UrgentLatency / >+ dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency >+ + (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024), 2)); >+ } >+ } >+ /*Writeback Latency support check*/ >+ >+ mode_lib->vba.WritebackLatencySupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { >+ if (locals->WriteBandwidth[k] >+ > (mode_lib->vba.WritebackInterfaceLumaBufferSize >+ + mode_lib->vba.WritebackInterfaceChromaBufferSize) >+ / mode_lib->vba.WritebackLatency) { >+ mode_lib->vba.WritebackLatencySupport = false; >+ } >+ } else { >+ if (locals->WriteBandwidth[k] >+ > 1.5 >+ * dml_min( >+ mode_lib->vba.WritebackInterfaceLumaBufferSize, >+ 2.0 >+ * mode_lib->vba.WritebackInterfaceChromaBufferSize) >+ / mode_lib->vba.WritebackLatency) { >+ mode_lib->vba.WritebackLatencySupport = false; >+ } >+ } >+ } >+ } >+ /*Re-ordering Buffer Support Check*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i] = >+ (mode_lib->vba.RoundTripPingLatencyCycles + 32.0) / mode_lib->vba.DCFCLKPerState[i] >+ + locals->UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels / locals->ReturnBWPerState[i]; >+ if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024.0 / locals->ReturnBWPerState[i] >+ > locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i]) { >+ locals->ROBSupport[i] = true; >+ } else { >+ locals->ROBSupport[i] = false; >+ } >+ } >+ /*Writeback Mode Support Check*/ >+ >+ mode_lib->vba.TotalNumberOfActiveWriteback = 0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0) >+ mode_lib->vba.ActiveWritebacksPerPlane[k] = 1; >+ mode_lib->vba.TotalNumberOfActiveWriteback = >+ mode_lib->vba.TotalNumberOfActiveWriteback >+ + mode_lib->vba.ActiveWritebacksPerPlane[k]; >+ } >+ } >+ mode_lib->vba.WritebackModeSupport = true; >+ if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback) { >+ mode_lib->vba.WritebackModeSupport = false; >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true >+ && mode_lib->vba.Writeback10bpc420Supported != true >+ && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { >+ mode_lib->vba.WritebackModeSupport = false; >+ } >+ } >+ /*Writeback Scale Ratio and Taps Support Check*/ >+ >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false >+ && (mode_lib->vba.WritebackHRatio[k] != 1.0 >+ || mode_lib->vba.WritebackVRatio[k] != 1.0)) { >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; >+ } >+ if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio >+ || mode_lib->vba.WritebackVRatio[k] >+ > mode_lib->vba.WritebackMaxVSCLRatio >+ || mode_lib->vba.WritebackHRatio[k] >+ < mode_lib->vba.WritebackMinHSCLRatio >+ || mode_lib->vba.WritebackVRatio[k] >+ < mode_lib->vba.WritebackMinVSCLRatio >+ || mode_lib->vba.WritebackLumaHTaps[k] >+ > mode_lib->vba.WritebackMaxHSCLTaps >+ || mode_lib->vba.WritebackLumaVTaps[k] >+ > mode_lib->vba.WritebackMaxVSCLTaps >+ || mode_lib->vba.WritebackHRatio[k] >+ > mode_lib->vba.WritebackLumaHTaps[k] >+ || mode_lib->vba.WritebackVRatio[k] >+ > mode_lib->vba.WritebackLumaVTaps[k] >+ || (mode_lib->vba.WritebackLumaHTaps[k] > 2.0 >+ && ((mode_lib->vba.WritebackLumaHTaps[k] % 2) >+ == 1)) >+ || (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32 >+ && (mode_lib->vba.WritebackChromaHTaps[k] >+ > mode_lib->vba.WritebackMaxHSCLTaps >+ || mode_lib->vba.WritebackChromaVTaps[k] >+ > mode_lib->vba.WritebackMaxVSCLTaps >+ || 2.0 >+ * mode_lib->vba.WritebackHRatio[k] >+ > mode_lib->vba.WritebackChromaHTaps[k] >+ || 2.0 >+ * mode_lib->vba.WritebackVRatio[k] >+ > mode_lib->vba.WritebackChromaVTaps[k] >+ || (mode_lib->vba.WritebackChromaHTaps[k] > 2.0 >+ && ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) { >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; >+ } >+ if (mode_lib->vba.WritebackVRatio[k] < 1.0) { >+ mode_lib->vba.WritebackLumaVExtra = >+ dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0); >+ } else { >+ mode_lib->vba.WritebackLumaVExtra = -1; >+ } >+ if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32 >+ && mode_lib->vba.WritebackLumaVTaps[k] >+ > (mode_lib->vba.WritebackLineBufferLumaBufferSize >+ + mode_lib->vba.WritebackLineBufferChromaBufferSize) >+ / 3.0 >+ / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackLumaVExtra) >+ || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 >+ && mode_lib->vba.WritebackLumaVTaps[k] >+ > mode_lib->vba.WritebackLineBufferLumaBufferSize >+ * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackLumaVExtra) >+ || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 >+ && mode_lib->vba.WritebackLumaVTaps[k] >+ > mode_lib->vba.WritebackLineBufferLumaBufferSize >+ * 8.0 / 10.0 >+ / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackLumaVExtra)) { >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; >+ } >+ if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) { >+ mode_lib->vba.WritebackChromaVExtra = 0.0; >+ } else { >+ mode_lib->vba.WritebackChromaVExtra = -1; >+ } >+ if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 >+ && mode_lib->vba.WritebackChromaVTaps[k] >+ > mode_lib->vba.WritebackLineBufferChromaBufferSize >+ * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackChromaVExtra) >+ || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 >+ && mode_lib->vba.WritebackChromaVTaps[k] >+ > mode_lib->vba.WritebackLineBufferChromaBufferSize >+ * 8.0 / 10.0 >+ / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackChromaVExtra)) { >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; >+ } >+ } >+ } >+ /*Maximum DISPCLK/DPPCLK Support check*/ >+ >+ mode_lib->vba.WritebackRequiredDISPCLK = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ mode_lib->vba.WritebackRequiredDISPCLK = >+ dml_max( >+ mode_lib->vba.WritebackRequiredDISPCLK, >+ CalculateWriteBackDISPCLK( >+ mode_lib->vba.WritebackPixelFormat[k], >+ mode_lib->vba.PixelClock[k], >+ mode_lib->vba.WritebackHRatio[k], >+ mode_lib->vba.WritebackVRatio[k], >+ mode_lib->vba.WritebackLumaHTaps[k], >+ mode_lib->vba.WritebackLumaVTaps[k], >+ mode_lib->vba.WritebackChromaHTaps[k], >+ mode_lib->vba.WritebackChromaVTaps[k], >+ mode_lib->vba.WritebackDestinationWidth[k], >+ mode_lib->vba.HTotal[k], >+ mode_lib->vba.WritebackChromaLineBufferWidth)); >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.HRatio[k] > 1.0) { >+ locals->PSCL_FACTOR[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput >+ * mode_lib->vba.HRatio[k] >+ / dml_ceil( >+ mode_lib->vba.htaps[k] >+ / 6.0, >+ 1.0)); >+ } else { >+ locals->PSCL_FACTOR[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput); >+ } >+ if (locals->BytePerPixelInDETC[k] == 0.0) { >+ locals->PSCL_FACTOR_CHROMA[k] = 0.0; >+ locals->MinDPPCLKUsingSingleDPP[k] = >+ mode_lib->vba.PixelClock[k] >+ * dml_max3( >+ mode_lib->vba.vtaps[k] / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k]), >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / locals->PSCL_FACTOR[k], >+ 1.0); >+ if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0) >+ && locals->MinDPPCLKUsingSingleDPP[k] >+ < 2.0 * mode_lib->vba.PixelClock[k]) { >+ locals->MinDPPCLKUsingSingleDPP[k] = 2.0 >+ * mode_lib->vba.PixelClock[k]; >+ } >+ } else { >+ if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) { >+ locals->PSCL_FACTOR_CHROMA[k] = >+ dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput >+ * mode_lib->vba.HRatio[k] >+ / 2.0 >+ / dml_ceil( >+ mode_lib->vba.HTAPsChroma[k] >+ / 6.0, >+ 1.0)); >+ } else { >+ locals->PSCL_FACTOR_CHROMA[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput); >+ } >+ locals->MinDPPCLKUsingSingleDPP[k] = >+ mode_lib->vba.PixelClock[k] >+ * dml_max5( >+ mode_lib->vba.vtaps[k] / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k]), >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / locals->PSCL_FACTOR[k], >+ mode_lib->vba.VTAPsChroma[k] >+ / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k] >+ / 2.0), >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / 4.0 >+ / locals->PSCL_FACTOR_CHROMA[k], >+ 1.0); >+ if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0 >+ || mode_lib->vba.HTAPsChroma[k] > 6.0 >+ || mode_lib->vba.VTAPsChroma[k] > 6.0) >+ && locals->MinDPPCLKUsingSingleDPP[k] >+ < 2.0 * mode_lib->vba.PixelClock[k]) { >+ locals->MinDPPCLKUsingSingleDPP[k] = 2.0 >+ * mode_lib->vba.PixelClock[k]; >+ } >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ Calculate256BBlockSizes( >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(locals->BytePerPixelInDETY[k], 1.0), >+ dml_ceil(locals->BytePerPixelInDETC[k], 2.0), >+ &locals->Read256BlockHeightY[k], >+ &locals->Read256BlockHeightC[k], >+ &locals->Read256BlockWidthY[k], >+ &locals->Read256BlockWidthC[k]); >+ if (mode_lib->vba.SourceScan[k] == dm_horz) { >+ locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k]; >+ locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k]; >+ } else { >+ locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k]; >+ locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k]; >+ } >+ if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear >+ || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ && (mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_4kb_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_4kb_s_x >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s_t >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s_x >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_var_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_var_s_x) >+ && mode_lib->vba.SourceScan[k] == dm_horz)) { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; >+ } else { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] >+ / 2.0; >+ } >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; >+ } else { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 >+ && mode_lib->vba.SourceScan[k] == dm_horz) { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] >+ / 2.0; >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 >+ && mode_lib->vba.SourceScan[k] == dm_horz) { >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k] >+ / 2.0; >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; >+ } else { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; >+ } >+ } >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ mode_lib->vba.MaximumSwathWidthSupport = 8192.0; >+ } else { >+ mode_lib->vba.MaximumSwathWidthSupport = 5120.0; >+ } >+ mode_lib->vba.MaximumSwathWidthInDETBuffer = >+ dml_min( >+ mode_lib->vba.MaximumSwathWidthSupport, >+ mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0 >+ / (locals->BytePerPixelInDETY[k] >+ * locals->MinSwathHeightY[k] >+ + locals->BytePerPixelInDETC[k] >+ / 2.0 >+ * locals->MinSwathHeightC[k])); >+ if (locals->BytePerPixelInDETC[k] == 0.0) { >+ mode_lib->vba.MaximumSwathWidthInLineBuffer = >+ mode_lib->vba.LineBufferSize >+ * dml_max(mode_lib->vba.HRatio[k], 1.0) >+ / mode_lib->vba.LBBitPerPixel[k] >+ / (mode_lib->vba.vtaps[k] >+ + dml_max( >+ dml_ceil( >+ mode_lib->vba.VRatio[k], >+ 1.0) >+ - 2, >+ 0.0)); >+ } else { >+ mode_lib->vba.MaximumSwathWidthInLineBuffer = >+ dml_min( >+ mode_lib->vba.LineBufferSize >+ * dml_max( >+ mode_lib->vba.HRatio[k], >+ 1.0) >+ / mode_lib->vba.LBBitPerPixel[k] >+ / (mode_lib->vba.vtaps[k] >+ + dml_max( >+ dml_ceil( >+ mode_lib->vba.VRatio[k], >+ 1.0) >+ - 2, >+ 0.0)), >+ 2.0 * mode_lib->vba.LineBufferSize >+ * dml_max( >+ mode_lib->vba.HRatio[k] >+ / 2.0, >+ 1.0) >+ / mode_lib->vba.LBBitPerPixel[k] >+ / (mode_lib->vba.VTAPsChroma[k] >+ + dml_max( >+ dml_ceil( >+ mode_lib->vba.VRatio[k] >+ / 2.0, >+ 1.0) >+ - 2, >+ 0.0))); >+ } >+ locals->MaximumSwathWidth[k] = dml_min( >+ mode_lib->vba.MaximumSwathWidthInDETBuffer, >+ mode_lib->vba.MaximumSwathWidthInLineBuffer); >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown( >+ mode_lib->vba.MaxDispclk[i], >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown( >+ mode_lib->vba.MaxDppclk[i], >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ locals->RequiredDISPCLK[i][j] = 0.0; >+ locals->DISPCLK_DPPCLK_Support[i][j] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = >+ mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) >+ * (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0); >+ if (mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine >= mode_lib->vba.MaxDispclk[i] >+ && i == mode_lib->vba.soc.num_states) >+ mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k] >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ >+ mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1 + mode_lib->vba.DISPCLKRampingMargin / 100.0); >+ if (mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine >= mode_lib->vba.MaxDispclk[i] >+ && i == mode_lib->vba.soc.num_states) >+ mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) { >+ locals->ODMCombineEnablePerState[i][k] = false; >+ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine; >+ } else { >+ locals->ODMCombineEnablePerState[i][k] = true; >+ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; >+ } >+ if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity >+ && locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k] >+ && locals->ODMCombineEnablePerState[i][k] == false) { >+ locals->NoOfDPP[i][j][k] = 1; >+ locals->RequiredDPPCLK[i][j][k] = >+ locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ } else { >+ locals->NoOfDPP[i][j][k] = 2; >+ locals->RequiredDPPCLK[i][j][k] = >+ locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; >+ } >+ locals->RequiredDISPCLK[i][j] = dml_max( >+ locals->RequiredDISPCLK[i][j], >+ mode_lib->vba.PlaneRequiredDISPCLK); >+ if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) >+ > mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity) >+ || (mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) { >+ locals->DISPCLK_DPPCLK_Support[i][j] = false; >+ } >+ } >+ locals->TotalNumberOfActiveDPP[i][j] = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) >+ locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; >+ if (j == 1) { >+ while (locals->TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP >+ && locals->TotalNumberOfActiveDPP[i][j] < 2 * mode_lib->vba.NumberOfActivePlanes) { >+ double BWOfNonSplitPlaneOfMaximumBandwidth; >+ unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth; >+ >+ BWOfNonSplitPlaneOfMaximumBandwidth = 0; >+ NumberOfNonSplitPlaneOfMaximumBandwidth = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) { >+ BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k]; >+ NumberOfNonSplitPlaneOfMaximumBandwidth = k; >+ } >+ } >+ locals->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2; >+ locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = >+ locals->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth] >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2; >+ locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + 1; >+ } >+ } >+ if (locals->TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP) { >+ locals->RequiredDISPCLK[i][j] = 0.0; >+ locals->DISPCLK_DPPCLK_Support[i][j] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->ODMCombineEnablePerState[i][k] = false; >+ if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) { >+ locals->NoOfDPP[i][j][k] = 1; >+ locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] >+ * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ } else { >+ locals->NoOfDPP[i][j][k] = 2; >+ locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] >+ * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; >+ } >+ if (i != mode_lib->vba.soc.num_states) { >+ mode_lib->vba.PlaneRequiredDISPCLK = >+ mode_lib->vba.PixelClock[k] >+ * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) >+ * (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0); >+ } else { >+ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k] >+ * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ } >+ locals->RequiredDISPCLK[i][j] = dml_max( >+ locals->RequiredDISPCLK[i][j], >+ mode_lib->vba.PlaneRequiredDISPCLK); >+ if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) >+ > mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity >+ || mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) >+ locals->DISPCLK_DPPCLK_Support[i][j] = false; >+ } >+ locals->TotalNumberOfActiveDPP[i][j] = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) >+ locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; >+ } >+ locals->RequiredDISPCLK[i][j] = dml_max( >+ locals->RequiredDISPCLK[i][j], >+ mode_lib->vba.WritebackRequiredDISPCLK); >+ if (mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity >+ < mode_lib->vba.WritebackRequiredDISPCLK) { >+ locals->DISPCLK_DPPCLK_Support[i][j] = false; >+ } >+ } >+ } >+ /*Viewport Size Check*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->ViewportSizeSupport[i] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->ODMCombineEnablePerState[i][k] == true) { >+ if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])) >+ > locals->MaximumSwathWidth[k]) { >+ locals->ViewportSizeSupport[i] = false; >+ } >+ } else { >+ if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) { >+ locals->ViewportSizeSupport[i] = false; >+ } >+ } >+ } >+ } >+ /*Total Available Pipes Support Check*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ if (locals->TotalNumberOfActiveDPP[i][j] <= mode_lib->vba.MaxNumDPP) >+ locals->TotalAvailablePipesSupport[i][j] = true; >+ else >+ locals->TotalAvailablePipesSupport[i][j] = false; >+ } >+ } >+ /*Total Available OTG Support Check*/ >+ >+ mode_lib->vba.TotalNumberOfActiveOTG = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG >+ + 1.0; >+ } >+ } >+ if (mode_lib->vba.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG) { >+ mode_lib->vba.NumberOfOTGSupport = true; >+ } else { >+ mode_lib->vba.NumberOfOTGSupport = false; >+ } >+ /*Display IO and DSC Support Check*/ >+ >+ mode_lib->vba.NonsupportedDSCInputBPC = false; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0 >+ || mode_lib->vba.DSCInputBitPerComponent[k] == 10.0 >+ || mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) { >+ mode_lib->vba.NonsupportedDSCInputBPC = true; >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->RequiresDSC[i][k] = 0; >+ locals->RequiresFEC[i][k] = 0; >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ if (mode_lib->vba.Output[k] == dm_hdmi) { >+ locals->RequiresDSC[i][k] = 0; >+ locals->RequiresFEC[i][k] = 0; >+ locals->OutputBppPerState[i][k] = TruncToValidBPP( >+ dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, >+ false, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ } else if (mode_lib->vba.Output[k] == dm_dp >+ || mode_lib->vba.Output[k] == dm_edp) { >+ if (mode_lib->vba.Output[k] == dm_edp) { >+ mode_lib->vba.EffectiveFECOverhead = 0.0; >+ } else { >+ mode_lib->vba.EffectiveFECOverhead = >+ mode_lib->vba.FECOverhead; >+ } >+ if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { >+ mode_lib->vba.Outbpp = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ false, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ mode_lib->vba.OutbppDSC = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ true, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ if (mode_lib->vba.DSCEnabled[k] == true) { >+ locals->RequiresDSC[i][k] = true; >+ if (mode_lib->vba.Output[k] == dm_dp) { >+ locals->RequiresFEC[i][k] = true; >+ } else { >+ locals->RequiresFEC[i][k] = false; >+ } >+ mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC; >+ } else { >+ locals->RequiresDSC[i][k] = false; >+ locals->RequiresFEC[i][k] = false; >+ } >+ locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; >+ } >+ if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { >+ mode_lib->vba.Outbpp = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ false, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ mode_lib->vba.OutbppDSC = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ true, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ if (mode_lib->vba.DSCEnabled[k] == true) { >+ locals->RequiresDSC[i][k] = true; >+ if (mode_lib->vba.Output[k] == dm_dp) { >+ locals->RequiresFEC[i][k] = true; >+ } else { >+ locals->RequiresFEC[i][k] = false; >+ } >+ mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC; >+ } else { >+ locals->RequiresDSC[i][k] = false; >+ locals->RequiresFEC[i][k] = false; >+ } >+ locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; >+ } >+ if (mode_lib->vba.Outbpp == BPP_INVALID >+ && mode_lib->vba.PHYCLKPerState[i] >+ >= 810.0) { >+ mode_lib->vba.Outbpp = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ false, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ mode_lib->vba.OutbppDSC = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ true, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) { >+ locals->RequiresDSC[i][k] = true; >+ if (mode_lib->vba.Output[k] == dm_dp) { >+ locals->RequiresFEC[i][k] = true; >+ } else { >+ locals->RequiresFEC[i][k] = false; >+ } >+ mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC; >+ } else { >+ locals->RequiresDSC[i][k] = false; >+ locals->RequiresFEC[i][k] = false; >+ } >+ locals->OutputBppPerState[i][k] = >+ mode_lib->vba.Outbpp; >+ } >+ } >+ } else { >+ locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE; >+ } >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->DIOSupport[i] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->OutputBppPerState[i][k] == BPP_INVALID >+ || (mode_lib->vba.OutputFormat[k] == dm_420 >+ && mode_lib->vba.Interlace[k] == true >+ && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { >+ locals->DIOSupport[i] = false; >+ } >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->DSCCLKRequiredMoreThanSupported[i] = false; >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ if ((mode_lib->vba.Output[k] == dm_dp >+ || mode_lib->vba.Output[k] == dm_edp)) { >+ if (mode_lib->vba.OutputFormat[k] == dm_420 >+ || mode_lib->vba.OutputFormat[k] >+ == dm_n422) { >+ mode_lib->vba.DSCFormatFactor = 2; >+ } else { >+ mode_lib->vba.DSCFormatFactor = 1; >+ } >+ if (locals->RequiresDSC[i][k] == true) { >+ if (locals->ODMCombineEnablePerState[i][k] >+ == true) { >+ if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor >+ > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) { >+ locals->DSCCLKRequiredMoreThanSupported[i] = >+ true; >+ } >+ } else { >+ if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor >+ > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) { >+ locals->DSCCLKRequiredMoreThanSupported[i] = >+ true; >+ } >+ } >+ } >+ } >+ } >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->NotEnoughDSCUnits[i] = false; >+ mode_lib->vba.TotalDSCUnitsRequired = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->RequiresDSC[i][k] == true) { >+ if (locals->ODMCombineEnablePerState[i][k] == true) { >+ mode_lib->vba.TotalDSCUnitsRequired = >+ mode_lib->vba.TotalDSCUnitsRequired + 2.0; >+ } else { >+ mode_lib->vba.TotalDSCUnitsRequired = >+ mode_lib->vba.TotalDSCUnitsRequired + 1.0; >+ } >+ } >+ } >+ if (mode_lib->vba.TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC) { >+ locals->NotEnoughDSCUnits[i] = true; >+ } >+ } >+ /*DSC Delay per state*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.BlendingAndTiming[k] != k) { >+ mode_lib->vba.slices = 0; >+ } else if (locals->RequiresDSC[i][k] == 0 >+ || locals->RequiresDSC[i][k] == false) { >+ mode_lib->vba.slices = 0; >+ } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { >+ mode_lib->vba.slices = dml_ceil( >+ mode_lib->vba.PixelClockBackEnd[k] / 400.0, >+ 4.0); >+ } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { >+ mode_lib->vba.slices = 8.0; >+ } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { >+ mode_lib->vba.slices = 4.0; >+ } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { >+ mode_lib->vba.slices = 2.0; >+ } else { >+ mode_lib->vba.slices = 1.0; >+ } >+ if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE >+ || locals->OutputBppPerState[i][k] == BPP_INVALID) { >+ mode_lib->vba.bpp = 0.0; >+ } else { >+ mode_lib->vba.bpp = locals->OutputBppPerState[i][k]; >+ } >+ if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) { >+ if (locals->ODMCombineEnablePerState[i][k] == false) { >+ locals->DSCDelayPerState[i][k] = >+ dscceComputeDelay( >+ mode_lib->vba.DSCInputBitPerComponent[k], >+ mode_lib->vba.bpp, >+ dml_ceil( >+ mode_lib->vba.HActive[k] >+ / mode_lib->vba.slices, >+ 1.0), >+ mode_lib->vba.slices, >+ mode_lib->vba.OutputFormat[k]) >+ + dscComputeDelay( >+ mode_lib->vba.OutputFormat[k]); >+ } else { >+ locals->DSCDelayPerState[i][k] = >+ 2.0 * (dscceComputeDelay( >+ mode_lib->vba.DSCInputBitPerComponent[k], >+ mode_lib->vba.bpp, >+ dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), >+ mode_lib->vba.slices / 2, >+ mode_lib->vba.OutputFormat[k]) >+ + dscComputeDelay(mode_lib->vba.OutputFormat[k])); >+ } >+ locals->DSCDelayPerState[i][k] = >+ locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k]; >+ } else { >+ locals->DSCDelayPerState[i][k] = 0.0; >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) { >+ for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true) >+ locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m]; >+ } >+ } >+ } >+ } >+ >+ //Prefetch Check >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->ODMCombineEnablePerState[i][k] == true) >+ locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); >+ else >+ locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; >+ locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k]; >+ locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY) >+ + locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; >+ if (locals->SourcePixelFormat[k] == dm_420_10) { >+ locals->RoundedUpMaxSwathSizeBytesY = dml_ceil(locals->RoundedUpMaxSwathSizeBytesY, 256) + 256; >+ } >+ if (locals->MaxSwathHeightC[k] > 0) { >+ locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k]; >+ >+ locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC) >+ + locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k]; >+ } >+ if (locals->SourcePixelFormat[k] == dm_420_10) { >+ locals->RoundedUpMaxSwathSizeBytesC = dml_ceil(locals->RoundedUpMaxSwathSizeBytesC, 256) + 256; >+ } else { >+ locals->RoundedUpMaxSwathSizeBytesC = 0; >+ } >+ >+ if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte * 1024 / 2) { >+ locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; >+ locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; >+ } else { >+ locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k]; >+ locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k]; >+ } >+ >+ if (locals->BytePerPixelInDETC[k] == 0) { >+ locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; >+ locals->LinesInDETChroma = 0; >+ } else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) { >+ locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] / >+ locals->SwathWidthYPerState[i][j][k]; >+ locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2); >+ } else { >+ locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; >+ locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); >+ } >+ >+ locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines, >+ dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] >+ / dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1); >+ >+ locals->EffectiveLBLatencyHidingSourceLinesChroma = dml_min(locals->MaxLineBufferLines, >+ dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] >+ / (locals->SwathWidthYPerState[i][j][k] / 2 >+ / dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1); >+ >+ locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma + dml_min( >+ locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] * >+ locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i], >+ locals->EffectiveLBLatencyHidingSourceLinesLuma), >+ locals->SwathHeightYPerState[i][j][k]); >+ >+ locals->EffectiveDETLBLinesChroma = dml_floor(locals->LinesInDETChroma + dml_min( >+ locals->LinesInDETChroma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETC[k] * >+ locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i], >+ locals->EffectiveLBLatencyHidingSourceLinesChroma), >+ locals->SwathHeightCPerState[i][j][k]); >+ >+ if (locals->BytePerPixelInDETC[k] == 0) { >+ locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k]) >+ / locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] * >+ dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]); >+ } else { >+ locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min( >+ locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k]) >+ / locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] * >+ dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]), >+ locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) - >+ locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 * >+ dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k])); >+ } >+ } >+ } >+ } >+ >+ for (i = 0; i <= locals->soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ locals->UrgentLatencySupport[i][j] = true; >+ for (k = 0; k < locals->NumberOfActivePlanes; k++) { >+ if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency) >+ locals->UrgentLatencySupport[i][j] = false; >+ } >+ } >+ } >+ >+ >+ /*Prefetch Check*/ >+ for (i = 0; i <= locals->soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ locals->TotalNumberOfDCCActiveDPP[i][j] = 0; >+ for (k = 0; k < locals->NumberOfActivePlanes; k++) { >+ if (locals->DCCEnable[k] == true) { >+ locals->TotalNumberOfDCCActiveDPP[i][j] = >+ locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; >+ } >+ } >+ } >+ } >+ >+ CalculateMinAndMaxPrefetchMode(locals->AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &locals->MinPrefetchMode, &locals->MaxPrefetchMode); >+ >+ locals->MaxTotalVActiveRDBandwidth = 0; >+ for (k = 0; k < locals->NumberOfActivePlanes; k++) { >+ locals->MaxTotalVActiveRDBandwidth = locals->MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k]; >+ } >+ >+ for (i = 0; i <= locals->soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ for (k = 0; k < locals->NumberOfActivePlanes; k++) { >+ locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k]; >+ locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k]; >+ locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k]; >+ locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k]; >+ locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k]; >+ mode_lib->vba.ProjectedDCFCLKDeepSleep = dml_max( >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ mode_lib->vba.PixelClock[k] / 16.0); >+ if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) { >+ if (mode_lib->vba.VRatio[k] <= 1.0) { >+ mode_lib->vba.ProjectedDCFCLKDeepSleep = >+ dml_max( >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ 1.1 >+ * dml_ceil( >+ mode_lib->vba.BytePerPixelInDETY[k], >+ 1.0) >+ / 64.0 >+ * mode_lib->vba.HRatio[k] >+ * mode_lib->vba.PixelClock[k] >+ / mode_lib->vba.NoOfDPP[i][j][k]); >+ } else { >+ mode_lib->vba.ProjectedDCFCLKDeepSleep = >+ dml_max( >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ 1.1 >+ * dml_ceil( >+ mode_lib->vba.BytePerPixelInDETY[k], >+ 1.0) >+ / 64.0 >+ * mode_lib->vba.PSCL_FACTOR[k] >+ * mode_lib->vba.RequiredDPPCLK[i][j][k]); >+ } >+ } else { >+ if (mode_lib->vba.VRatio[k] <= 1.0) { >+ mode_lib->vba.ProjectedDCFCLKDeepSleep = >+ dml_max( >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ 1.1 >+ * dml_ceil( >+ mode_lib->vba.BytePerPixelInDETY[k], >+ 1.0) >+ / 32.0 >+ * mode_lib->vba.HRatio[k] >+ * mode_lib->vba.PixelClock[k] >+ / mode_lib->vba.NoOfDPP[i][j][k]); >+ } else { >+ mode_lib->vba.ProjectedDCFCLKDeepSleep = >+ dml_max( >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ 1.1 >+ * dml_ceil( >+ mode_lib->vba.BytePerPixelInDETY[k], >+ 1.0) >+ / 32.0 >+ * mode_lib->vba.PSCL_FACTOR[k] >+ * mode_lib->vba.RequiredDPPCLK[i][j][k]); >+ } >+ if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) { >+ mode_lib->vba.ProjectedDCFCLKDeepSleep = >+ dml_max( >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ 1.1 >+ * dml_ceil( >+ mode_lib->vba.BytePerPixelInDETC[k], >+ 2.0) >+ / 32.0 >+ * mode_lib->vba.HRatio[k] >+ / 2.0 >+ * mode_lib->vba.PixelClock[k] >+ / mode_lib->vba.NoOfDPP[i][j][k]); >+ } else { >+ mode_lib->vba.ProjectedDCFCLKDeepSleep = >+ dml_max( >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ 1.1 >+ * dml_ceil( >+ mode_lib->vba.BytePerPixelInDETC[k], >+ 2.0) >+ / 32.0 >+ * mode_lib->vba.PSCL_FACTOR_CHROMA[k] >+ * mode_lib->vba.RequiredDPPCLK[i][j][k]); >+ } >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes( >+ mode_lib, >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.Read256BlockHeightY[k], >+ mode_lib->vba.Read256BlockWidthY[k], >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), >+ mode_lib->vba.SourceScan[k], >+ mode_lib->vba.ViewportWidth[k], >+ mode_lib->vba.ViewportHeight[k], >+ mode_lib->vba.SwathWidthYPerState[i][j][k], >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.VMMPageSize, >+ mode_lib->vba.PTEBufferSizeInRequestsLuma, >+ mode_lib->vba.PDEProcessingBufIn64KBReqs, >+ mode_lib->vba.PitchY[k], >+ mode_lib->vba.DCCMetaPitchY[k], >+ &mode_lib->vba.MacroTileWidthY[k], >+ &mode_lib->vba.MetaRowBytesY, >+ &mode_lib->vba.DPTEBytesPerRowY, >+ &mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k], >+ &mode_lib->vba.dpte_row_height[k], >+ &mode_lib->vba.meta_row_height[k]); >+ mode_lib->vba.PrefetchLinesY[k] = CalculatePrefetchSourceLines( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.vtaps[k], >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ mode_lib->vba.SwathHeightYPerState[i][j][k], >+ mode_lib->vba.ViewportYStartY[k], >+ &mode_lib->vba.PrefillY[k], >+ &mode_lib->vba.MaxNumSwY[k]); >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) { >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes( >+ mode_lib, >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.Read256BlockHeightY[k], >+ mode_lib->vba.Read256BlockWidthY[k], >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), >+ mode_lib->vba.SourceScan[k], >+ mode_lib->vba.ViewportWidth[k] / 2.0, >+ mode_lib->vba.ViewportHeight[k] / 2.0, >+ mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.VMMPageSize, >+ mode_lib->vba.PTEBufferSizeInRequestsLuma, >+ mode_lib->vba.PDEProcessingBufIn64KBReqs, >+ mode_lib->vba.PitchC[k], >+ 0.0, >+ &mode_lib->vba.MacroTileWidthC[k], >+ &mode_lib->vba.MetaRowBytesC, >+ &mode_lib->vba.DPTEBytesPerRowC, >+ &mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k], >+ &mode_lib->vba.dpte_row_height_chroma[k], >+ &mode_lib->vba.meta_row_height_chroma[k]); >+ mode_lib->vba.PrefetchLinesC[k] = CalculatePrefetchSourceLines( >+ mode_lib, >+ mode_lib->vba.VRatio[k] / 2.0, >+ mode_lib->vba.VTAPsChroma[k], >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ mode_lib->vba.SwathHeightCPerState[i][j][k], >+ mode_lib->vba.ViewportYStartC[k], >+ &mode_lib->vba.PrefillC[k], >+ &mode_lib->vba.MaxNumSwC[k]); >+ } else { >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0; >+ mode_lib->vba.MetaRowBytesC = 0.0; >+ mode_lib->vba.DPTEBytesPerRowC = 0.0; >+ locals->PrefetchLinesC[k] = 0.0; >+ locals->PTEBufferSizeNotExceededC[i][j][k] = true; >+ locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; >+ } >+ locals->PDEAndMetaPTEBytesPerFrame[k] = >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameY + mode_lib->vba.PDEAndMetaPTEBytesPerFrameC; >+ locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC; >+ locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC; >+ >+ CalculateActiveRowBandwidth( >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.MetaRowBytesY, >+ mode_lib->vba.MetaRowBytesC, >+ mode_lib->vba.meta_row_height[k], >+ mode_lib->vba.meta_row_height_chroma[k], >+ mode_lib->vba.DPTEBytesPerRowY, >+ mode_lib->vba.DPTEBytesPerRowC, >+ mode_lib->vba.dpte_row_height[k], >+ mode_lib->vba.dpte_row_height_chroma[k], >+ &mode_lib->vba.meta_row_bw[k], >+ &mode_lib->vba.dpte_row_bw[k], >+ &mode_lib->vba.qual_row_bw[k]); >+ } >+ mode_lib->vba.ExtraLatency = >+ mode_lib->vba.UrgentRoundTripAndOutOfOrderLatencyPerState[i] >+ + (mode_lib->vba.TotalNumberOfActiveDPP[i][j] >+ * mode_lib->vba.PixelChunkSizeInKByte >+ + mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j] >+ * mode_lib->vba.MetaChunkSize) >+ * 1024.0 >+ / mode_lib->vba.ReturnBWPerState[i]; >+ if (mode_lib->vba.GPUVMEnable == true) { >+ mode_lib->vba.ExtraLatency = mode_lib->vba.ExtraLatency >+ + mode_lib->vba.TotalNumberOfActiveDPP[i][j] >+ * mode_lib->vba.PTEGroupSize >+ / mode_lib->vba.ReturnBWPerState[i]; >+ } >+ mode_lib->vba.TimeCalc = 24.0 / mode_lib->vba.ProjectedDCFCLKDeepSleep; >+ >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency >+ + CalculateWriteBackDelay( >+ mode_lib->vba.WritebackPixelFormat[k], >+ mode_lib->vba.WritebackHRatio[k], >+ mode_lib->vba.WritebackVRatio[k], >+ mode_lib->vba.WritebackLumaHTaps[k], >+ mode_lib->vba.WritebackLumaVTaps[k], >+ mode_lib->vba.WritebackChromaHTaps[k], >+ mode_lib->vba.WritebackChromaVTaps[k], >+ mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; >+ } else { >+ locals->WritebackDelay[i][k] = 0.0; >+ } >+ for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) { >+ if (mode_lib->vba.BlendingAndTiming[m] == k >+ && mode_lib->vba.WritebackEnable[m] >+ == true) { >+ locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k], >+ mode_lib->vba.WritebackLatency + CalculateWriteBackDelay( >+ mode_lib->vba.WritebackPixelFormat[m], >+ mode_lib->vba.WritebackHRatio[m], >+ mode_lib->vba.WritebackVRatio[m], >+ mode_lib->vba.WritebackLumaHTaps[m], >+ mode_lib->vba.WritebackLumaVTaps[m], >+ mode_lib->vba.WritebackChromaHTaps[m], >+ mode_lib->vba.WritebackChromaVTaps[m], >+ mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); >+ } >+ } >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == m) { >+ locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m]; >+ } >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ for (m = 0; m < locals->NumberOfCursors[k]; m++) >+ locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m] >+ / 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k]; >+ } >+ >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] >+ - dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0)); >+ } >+ >+ mode_lib->vba.NextPrefetchMode = mode_lib->vba.MinPrefetchMode; >+ do { >+ mode_lib->vba.PrefetchMode[i][j] = mode_lib->vba.NextPrefetchMode; >+ mode_lib->vba.NextPrefetchMode = mode_lib->vba.NextPrefetchMode + 1; >+ >+ mode_lib->vba.TWait = CalculateTWait( >+ mode_lib->vba.PrefetchMode[i][j], >+ mode_lib->vba.DRAMClockChangeLatency, >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.SREnterPlusExitTime); >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ >+ if (mode_lib->vba.XFCEnabled[k] == true) { >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = >+ CalculateRemoteSurfaceFlipDelay( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ locals->SwathWidthYPerState[i][j][k], >+ dml_ceil(locals->BytePerPixelInDETY[k], 1.0), >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.XFCTSlvVupdateOffset, >+ mode_lib->vba.XFCTSlvVupdateWidth, >+ mode_lib->vba.XFCTSlvVreadyOffset, >+ mode_lib->vba.XFCXBUFLatencyTolerance, >+ mode_lib->vba.XFCFillBWOverhead, >+ mode_lib->vba.XFCSlvChunkSize, >+ mode_lib->vba.XFCBusTransportTime, >+ mode_lib->vba.TimeCalc, >+ mode_lib->vba.TWait, >+ &mode_lib->vba.SrcActiveDrainRate, >+ &mode_lib->vba.TInitXFill, >+ &mode_lib->vba.TslvChk); >+ } else { >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0.0; >+ } >+ >+ CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBWPerState[i], mode_lib->vba.ReadBandwidthLuma[k], mode_lib->vba.ReadBandwidthChroma[k], mode_lib->vba.MaxTotalVActiveRDBandwidth, >+ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k], >+ mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], >+ mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, >+ mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], >+ mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]); >+ >+ mode_lib->vba.IsErrorResult[i][j][k] = >+ CalculatePrefetchSchedule( >+ mode_lib, >+ mode_lib->vba.RequiredDPPCLK[i][j][k], >+ mode_lib->vba.RequiredDISPCLK[i][j], >+ mode_lib->vba.PixelClock[k], >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ mode_lib->vba.NoOfDPP[i][j][k], >+ mode_lib->vba.NumberOfCursors[k], >+ mode_lib->vba.VTotal[k] >+ - mode_lib->vba.VActive[k], >+ mode_lib->vba.HTotal[k], >+ mode_lib->vba.MaxInterDCNTileRepeaters, >+ mode_lib->vba.MaximumVStartup[k], >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.DynamicMetadataEnable[k], >+ mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], >+ mode_lib->vba.DynamicMetadataTransmittedBytes[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.UrgentLatencyPixelDataOnly, >+ mode_lib->vba.ExtraLatency, >+ mode_lib->vba.TimeCalc, >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k], >+ mode_lib->vba.MetaRowBytes[k], >+ mode_lib->vba.DPTEBytesPerRow[k], >+ mode_lib->vba.PrefetchLinesY[k], >+ mode_lib->vba.SwathWidthYPerState[i][j][k], >+ mode_lib->vba.BytePerPixelInDETY[k], >+ mode_lib->vba.PrefillY[k], >+ mode_lib->vba.MaxNumSwY[k], >+ mode_lib->vba.PrefetchLinesC[k], >+ mode_lib->vba.BytePerPixelInDETC[k], >+ mode_lib->vba.PrefillC[k], >+ mode_lib->vba.MaxNumSwC[k], >+ mode_lib->vba.SwathHeightYPerState[i][j][k], >+ mode_lib->vba.SwathHeightCPerState[i][j][k], >+ mode_lib->vba.TWait, >+ mode_lib->vba.XFCEnabled[k], >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay, >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ mode_lib->vba.DSTXAfterScaler[k], >+ mode_lib->vba.DSTYAfterScaler[k], >+ &mode_lib->vba.LineTimesForPrefetch[k], >+ &mode_lib->vba.PrefetchBW[k], >+ &mode_lib->vba.LinesForMetaPTE[k], >+ &mode_lib->vba.LinesForMetaAndDPTERow[k], >+ &mode_lib->vba.VRatioPreY[i][j][k], >+ &mode_lib->vba.VRatioPreC[i][j][k], >+ &mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k], >+ &mode_lib->vba.Tno_bw[k], >+ &mode_lib->vba.VUpdateOffsetPix[k], >+ &mode_lib->vba.VUpdateWidthPix[k], >+ &mode_lib->vba.VReadyOffsetPix[k]); >+ } >+ mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0; >+ mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0; >+ locals->prefetch_vm_bw_valid = true; >+ locals->prefetch_row_bw_valid = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->PDEAndMetaPTEBytesPerFrame[k] == 0) >+ locals->prefetch_vm_bw[k] = 0; >+ else if (locals->LinesForMetaPTE[k] > 0) >+ locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[k] >+ / (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]); >+ else { >+ locals->prefetch_vm_bw[k] = 0; >+ locals->prefetch_vm_bw_valid = false; >+ } >+ if (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k] == 0) >+ locals->prefetch_row_bw[k] = 0; >+ else if (locals->LinesForMetaAndDPTERow[k] > 0) >+ locals->prefetch_row_bw[k] = (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k]) >+ / (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]); >+ else { >+ locals->prefetch_row_bw[k] = 0; >+ locals->prefetch_row_bw_valid = false; >+ } >+ >+ mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = mode_lib->vba.MaximumReadBandwidthWithPrefetch >+ + mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]; >+ mode_lib->vba.MaximumReadBandwidthWithPrefetch = >+ mode_lib->vba.MaximumReadBandwidthWithPrefetch >+ + mode_lib->vba.cursor_bw[k] >+ + dml_max3( >+ mode_lib->vba.prefetch_vm_bw[k], >+ mode_lib->vba.prefetch_row_bw[k], >+ dml_max(mode_lib->vba.ReadBandwidth[k], >+ mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]) >+ + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]); >+ } >+ locals->BandwidthWithoutPrefetchSupported[i] = true; >+ if (mode_lib->vba.MaximumReadBandwidthWithoutPrefetch > locals->ReturnBWPerState[i]) { >+ locals->BandwidthWithoutPrefetchSupported[i] = false; >+ } >+ >+ locals->PrefetchSupported[i][j] = true; >+ if (mode_lib->vba.MaximumReadBandwidthWithPrefetch > locals->ReturnBWPerState[i]) { >+ locals->PrefetchSupported[i][j] = false; >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->LineTimesForPrefetch[k] < 2.0 >+ || locals->LinesForMetaPTE[k] >= 8.0 >+ || locals->LinesForMetaAndDPTERow[k] >= 16.0 >+ || mode_lib->vba.IsErrorResult[i][j][k] == true) { >+ locals->PrefetchSupported[i][j] = false; >+ } >+ } >+ locals->VRatioInPrefetchSupported[i][j] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->VRatioPreY[i][j][k] > 4.0 >+ || locals->VRatioPreC[i][j][k] > 4.0 >+ || mode_lib->vba.IsErrorResult[i][j][k] == true) { >+ locals->VRatioInPrefetchSupported[i][j] = false; >+ } >+ } >+ } while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true) >+ && mode_lib->vba.NextPrefetchMode < mode_lib->vba.MaxPrefetchMode); >+ >+ if (mode_lib->vba.PrefetchSupported[i][j] == true >+ && mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) { >+ mode_lib->vba.BandwidthAvailableForImmediateFlip = >+ mode_lib->vba.ReturnBWPerState[i]; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.BandwidthAvailableForImmediateFlip = >+ mode_lib->vba.BandwidthAvailableForImmediateFlip >+ - mode_lib->vba.cursor_bw[k] >+ - dml_max( >+ mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k], >+ mode_lib->vba.PrefetchBW[k]); >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.ImmediateFlipBytes[k] = 0.0; >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { >+ mode_lib->vba.ImmediateFlipBytes[k] = >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k] >+ + mode_lib->vba.MetaRowBytes[k] >+ + mode_lib->vba.DPTEBytesPerRow[k]; >+ } >+ } >+ mode_lib->vba.TotImmediateFlipBytes = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { >+ mode_lib->vba.TotImmediateFlipBytes = >+ mode_lib->vba.TotImmediateFlipBytes >+ + mode_lib->vba.ImmediateFlipBytes[k]; >+ } >+ } >+ >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ CalculateFlipSchedule( >+ mode_lib, >+ mode_lib->vba.ExtraLatency, >+ mode_lib->vba.UrgentLatencyPixelDataOnly, >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.BandwidthAvailableForImmediateFlip, >+ mode_lib->vba.TotImmediateFlipBytes, >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.ImmediateFlipBytes[k], >+ mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.Tno_bw[k], >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k], >+ mode_lib->vba.MetaRowBytes[k], >+ mode_lib->vba.DPTEBytesPerRow[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.dpte_row_height[k], >+ mode_lib->vba.meta_row_height[k], >+ mode_lib->vba.qual_row_bw[k], >+ &mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k], >+ &mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k], >+ &mode_lib->vba.final_flip_bw[k], >+ &mode_lib->vba.ImmediateFlipSupportedForPipe[k]); >+ } >+ mode_lib->vba.total_dcn_read_bw_with_flip = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.total_dcn_read_bw_with_flip = >+ mode_lib->vba.total_dcn_read_bw_with_flip >+ + mode_lib->vba.cursor_bw[k] >+ + dml_max3( >+ mode_lib->vba.prefetch_vm_bw[k], >+ mode_lib->vba.prefetch_row_bw[k], >+ mode_lib->vba.final_flip_bw[k] >+ + dml_max( >+ mode_lib->vba.ReadBandwidth[k], >+ mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])); >+ } >+ mode_lib->vba.ImmediateFlipSupportedForState[i][j] = true; >+ if (mode_lib->vba.total_dcn_read_bw_with_flip >+ > mode_lib->vba.ReturnBWPerState[i]) { >+ mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false; >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) { >+ mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false; >+ } >+ } >+ } else { >+ mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false; >+ } >+ } >+ } >+ >+ /*Vertical Active BW support*/ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i] = dml_min(mode_lib->vba.ReturnBusWidth * >+ mode_lib->vba.DCFCLKPerState[i], mode_lib->vba.FabricAndDRAMBandwidthPerState[i] * 1000) * >+ mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation / 100; >+ if (mode_lib->vba.MaxTotalVActiveRDBandwidth <= mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i]) >+ mode_lib->vba.TotalVerticalActiveBandwidthSupport[i] = true; >+ else >+ mode_lib->vba.TotalVerticalActiveBandwidthSupport[i] = false; >+ } >+ >+ /*PTE Buffer Size Check*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ locals->PTEBufferSizeNotExceeded[i][j] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->PTEBufferSizeNotExceededY[i][j][k] == false >+ || locals->PTEBufferSizeNotExceededC[i][j][k] == false) { >+ locals->PTEBufferSizeNotExceeded[i][j] = false; >+ } >+ } >+ } >+ } >+ /*Cursor Support Check*/ >+ mode_lib->vba.CursorSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ for (j = 0; j < 2; j++) { >+ if (mode_lib->vba.CursorWidth[k][j] > 0.0) { >+ if (dml_floor( >+ dml_floor( >+ mode_lib->vba.CursorBufferSize >+ - mode_lib->vba.CursorChunkSize, >+ mode_lib->vba.CursorChunkSize) * 1024.0 >+ / (mode_lib->vba.CursorWidth[k][j] >+ * mode_lib->vba.CursorBPP[k][j] >+ / 8.0), >+ 1.0) >+ * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) >+ / mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly >+ || (mode_lib->vba.CursorBPP[k][j] == 64.0 >+ && mode_lib->vba.Cursor64BppSupport == false)) { >+ mode_lib->vba.CursorSupport = false; >+ } >+ } >+ } >+ } >+ /*Valid Pitch Check*/ >+ >+ mode_lib->vba.PitchSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->AlignedYPitch[k] = dml_ceil( >+ dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]), >+ locals->MacroTileWidthY[k]); >+ if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) { >+ mode_lib->vba.PitchSupport = false; >+ } >+ if (mode_lib->vba.DCCEnable[k] == true) { >+ locals->AlignedDCCMetaPitch[k] = dml_ceil( >+ dml_max( >+ mode_lib->vba.DCCMetaPitchY[k], >+ mode_lib->vba.ViewportWidth[k]), >+ 64.0 * locals->Read256BlockWidthY[k]); >+ } else { >+ locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k]; >+ } >+ if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) { >+ mode_lib->vba.PitchSupport = false; >+ } >+ if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) { >+ locals->AlignedCPitch[k] = dml_ceil( >+ dml_max( >+ mode_lib->vba.PitchC[k], >+ mode_lib->vba.ViewportWidth[k] / 2.0), >+ locals->MacroTileWidthC[k]); >+ } else { >+ locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k]; >+ } >+ if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) { >+ mode_lib->vba.PitchSupport = false; >+ } >+ } >+ /*Mode Support, Voltage State and SOC Configuration*/ >+ >+ for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { >+ for (j = 0; j < 2; j++) { >+ enum dm_validation_status status = DML_VALIDATION_OK; >+ >+ if (mode_lib->vba.ScaleRatioAndTapsSupport != true) { >+ status = DML_FAIL_SCALE_RATIO_TAP; >+ } else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) { >+ status = DML_FAIL_SOURCE_PIXEL_FORMAT; >+ } else if (locals->ViewportSizeSupport[i] != true) { >+ status = DML_FAIL_VIEWPORT_SIZE; >+ } else if (locals->DIOSupport[i] != true) { >+ status = DML_FAIL_DIO_SUPPORT; >+ } else if (locals->NotEnoughDSCUnits[i] != false) { >+ status = DML_FAIL_NOT_ENOUGH_DSC; >+ } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) { >+ status = DML_FAIL_DSC_CLK_REQUIRED; >+ } else if (locals->UrgentLatencySupport[i][j] != true) { >+ status = DML_FAIL_URGENT_LATENCY; >+ } else if (locals->ROBSupport[i] != true) { >+ status = DML_FAIL_REORDERING_BUFFER; >+ } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) { >+ status = DML_FAIL_DISPCLK_DPPCLK; >+ } else if (locals->TotalAvailablePipesSupport[i][j] != true) { >+ status = DML_FAIL_TOTAL_AVAILABLE_PIPES; >+ } else if (mode_lib->vba.NumberOfOTGSupport != true) { >+ status = DML_FAIL_NUM_OTG; >+ } else if (mode_lib->vba.WritebackModeSupport != true) { >+ status = DML_FAIL_WRITEBACK_MODE; >+ } else if (mode_lib->vba.WritebackLatencySupport != true) { >+ status = DML_FAIL_WRITEBACK_LATENCY; >+ } else if (mode_lib->vba.WritebackScaleRatioAndTapsSupport != true) { >+ status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP; >+ } else if (mode_lib->vba.CursorSupport != true) { >+ status = DML_FAIL_CURSOR_SUPPORT; >+ } else if (mode_lib->vba.PitchSupport != true) { >+ status = DML_FAIL_PITCH_SUPPORT; >+ } else if (locals->PrefetchSupported[i][j] != true) { >+ status = DML_FAIL_PREFETCH_SUPPORT; >+ } else if (locals->TotalVerticalActiveBandwidthSupport[i] != true) { >+ status = DML_FAIL_TOTAL_V_ACTIVE_BW; >+ } else if (locals->VRatioInPrefetchSupported[i][j] != true) { >+ status = DML_FAIL_V_RATIO_PREFETCH; >+ } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) { >+ status = DML_FAIL_PTE_BUFFER_SIZE; >+ } else if (mode_lib->vba.NonsupportedDSCInputBPC != false) { >+ status = DML_FAIL_DSC_INPUT_BPC; >+ } >+ >+ if (status == DML_VALIDATION_OK) { >+ locals->ModeSupport[i][j] = true; >+ } else { >+ locals->ModeSupport[i][j] = false; >+ } >+ locals->ValidationStatus[i] = status; >+ } >+ } >+ { >+ unsigned int MaximumMPCCombine = 0; >+ mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1; >+ for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) { >+ if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) { >+ mode_lib->vba.VoltageLevel = i; >+ if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false >+ || mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible)) { >+ MaximumMPCCombine = 1; >+ } else { >+ MaximumMPCCombine = 0; >+ } >+ break; >+ } >+ } >+ mode_lib->vba.ImmediateFlipSupport = >+ locals->ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; >+ locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; >+ } >+ mode_lib->vba.DISPCLK = locals->RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; >+ mode_lib->vba.maxMpcComb = MaximumMPCCombine; >+ } >+ mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.ReturnBW = locals->ReturnBWPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.FabricAndDRAMBandwidth = locals->FabricAndDRAMBandwidthPerState[mode_lib->vba.VoltageLevel]; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ mode_lib->vba.ODMCombineEnabled[k] = >+ locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k]; >+ } else { >+ mode_lib->vba.ODMCombineEnabled[k] = 0; >+ } >+ mode_lib->vba.DSCEnabled[k] = >+ locals->RequiresDSC[mode_lib->vba.VoltageLevel][k]; >+ mode_lib->vba.OutputBpp[k] = >+ locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k]; >+ } >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h 2019-08-31 15:01:11.867736169 -0500 >@@ -0,0 +1,32 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef _DCN20V2_DISPLAY_MODE_VBA_H_ >+#define _DCN20V2_DISPLAY_MODE_VBA_H_ >+ >+void dml20v2_recalculate(struct display_mode_lib *mode_lib); >+void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 2019-08-31 15:01:11.867736169 -0500 >@@ -0,0 +1,1701 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#include "../display_mode_lib.h" >+#include "../display_mode_vba.h" >+#include "display_rq_dlg_calc_20v2.h" >+ >+// Function: dml20v2_rq_dlg_get_rq_params >+// Calculate requestor related parameters that register definition agnostic >+// (i.e. this layer does try to separate real values from register definition) >+// Input: >+// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.) >+// Output: >+// rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.) >+// >+static void dml20v2_rq_dlg_get_rq_params( >+ struct display_mode_lib *mode_lib, >+ display_rq_params_st * rq_param, >+ const display_pipe_source_params_st pipe_src_param); >+ >+// Function: dml20v2_rq_dlg_get_dlg_params >+// Calculate deadline related parameters >+// >+static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, >+ const display_e2e_pipe_params_st *e2e_pipe_param, >+ const unsigned int num_pipes, >+ const unsigned int pipe_idx, >+ display_dlg_regs_st *disp_dlg_regs, >+ display_ttu_regs_st *disp_ttu_regs, >+ const display_rq_dlg_params_st rq_dlg_param, >+ const display_dlg_sys_params_st dlg_sys_param, >+ const bool cstate_en, >+ const bool pstate_en); >+/* >+ * NOTE: >+ * This file is gcc-parseable HW gospel, coming straight from HW engineers. >+ * >+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd >+ * ways. Unless there is something clearly wrong with it the code should >+ * remain as-is as it provides us with a guarantee from HW that it is correct. >+ */ >+ >+static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, >+ double *refcyc_per_req_delivery_pre_cur, >+ double *refcyc_per_req_delivery_cur, >+ double refclk_freq_in_mhz, >+ double ref_freq_to_pix_freq, >+ double hscale_pixel_rate_l, >+ double hscl_ratio, >+ double vratio_pre_l, >+ double vratio_l, >+ unsigned int cur_width, >+ enum cursor_bpp cur_bpp); >+ >+#include "../dml_inline_defs.h" >+ >+static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) >+{ >+ unsigned int ret_val = 0; >+ >+ if (source_format == dm_444_16) { >+ if (!is_chroma) >+ ret_val = 2; >+ } else if (source_format == dm_444_32) { >+ if (!is_chroma) >+ ret_val = 4; >+ } else if (source_format == dm_444_64) { >+ if (!is_chroma) >+ ret_val = 8; >+ } else if (source_format == dm_420_8) { >+ if (is_chroma) >+ ret_val = 2; >+ else >+ ret_val = 1; >+ } else if (source_format == dm_420_10) { >+ if (is_chroma) >+ ret_val = 4; >+ else >+ ret_val = 2; >+ } else if (source_format == dm_444_8) { >+ ret_val = 1; >+ } >+ return ret_val; >+} >+ >+static bool is_dual_plane(enum source_format_class source_format) >+{ >+ bool ret_val = 0; >+ >+ if ((source_format == dm_420_8) || (source_format == dm_420_10)) >+ ret_val = 1; >+ >+ return ret_val; >+} >+ >+static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, >+ double refclk_freq_in_mhz, >+ double pclk_freq_in_mhz, >+ bool odm_combine, >+ unsigned int recout_width, >+ unsigned int hactive, >+ double vratio, >+ double hscale_pixel_rate, >+ unsigned int delivery_width, >+ unsigned int req_per_swath_ub) >+{ >+ double refcyc_per_delivery = 0.0; >+ >+ if (vratio <= 1.0) { >+ if (odm_combine) >+ refcyc_per_delivery = (double) refclk_freq_in_mhz >+ * dml_min((double) recout_width, (double) hactive / 2.0) >+ / pclk_freq_in_mhz / (double) req_per_swath_ub; >+ else >+ refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width >+ / pclk_freq_in_mhz / (double) req_per_swath_ub; >+ } else { >+ refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width >+ / (double) hscale_pixel_rate / (double) req_per_swath_ub; >+ } >+ >+ dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); >+ dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); >+ dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); >+ dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); >+ >+ return refcyc_per_delivery; >+ >+} >+ >+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) >+{ >+ if (tile_size == dm_256k_tile) >+ return (256 * 1024); >+ else if (tile_size == dm_64k_tile) >+ return (64 * 1024); >+ else >+ return (4 * 1024); >+} >+ >+static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, >+ display_data_rq_regs_st *rq_regs, >+ const display_data_rq_sizing_params_st rq_sizing) >+{ >+ dml_print("DML_DLG: %s: rq_sizing param\n", __func__); >+ print__data_rq_sizing_params_st(mode_lib, rq_sizing); >+ >+ rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; >+ >+ if (rq_sizing.min_chunk_bytes == 0) >+ rq_regs->min_chunk_size = 0; >+ else >+ rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; >+ >+ rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; >+ if (rq_sizing.min_meta_chunk_bytes == 0) >+ rq_regs->min_meta_chunk_size = 0; >+ else >+ rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; >+ >+ rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; >+ rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; >+} >+ >+static void extract_rq_regs(struct display_mode_lib *mode_lib, >+ display_rq_regs_st *rq_regs, >+ const display_rq_params_st rq_param) >+{ >+ unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; >+ unsigned int detile_buf_plane1_addr = 0; >+ >+ extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); >+ >+ rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), >+ 1) - 3; >+ >+ if (rq_param.yuv420) { >+ extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); >+ rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), >+ 1) - 3; >+ } >+ >+ rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); >+ rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); >+ >+ // FIXME: take the max between luma, chroma chunk size? >+ // okay for now, as we are setting chunk_bytes to 8kb anyways >+ if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb >+ rq_regs->drq_expansion_mode = 0; >+ } else { >+ rq_regs->drq_expansion_mode = 2; >+ } >+ rq_regs->prq_expansion_mode = 1; >+ rq_regs->mrq_expansion_mode = 1; >+ rq_regs->crq_expansion_mode = 1; >+ >+ if (rq_param.yuv420) { >+ if ((double) rq_param.misc.rq_l.stored_swath_bytes >+ / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { >+ detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma >+ } else { >+ detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), >+ 256, >+ 0) / 64.0; // 2/3 to chroma >+ } >+ } >+ rq_regs->plane1_base_address = detile_buf_plane1_addr; >+} >+ >+static void handle_det_buf_split(struct display_mode_lib *mode_lib, >+ display_rq_params_st *rq_param, >+ const display_pipe_source_params_st pipe_src_param) >+{ >+ unsigned int total_swath_bytes = 0; >+ unsigned int swath_bytes_l = 0; >+ unsigned int swath_bytes_c = 0; >+ unsigned int full_swath_bytes_packed_l = 0; >+ unsigned int full_swath_bytes_packed_c = 0; >+ bool req128_l = 0; >+ bool req128_c = 0; >+ bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); >+ bool surf_vert = (pipe_src_param.source_scan == dm_vert); >+ unsigned int log2_swath_height_l = 0; >+ unsigned int log2_swath_height_c = 0; >+ unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; >+ >+ full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; >+ full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; >+ >+ if (rq_param->yuv420_10bpc) { >+ full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3, >+ 256, >+ 1) + 256; >+ full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3, >+ 256, >+ 1) + 256; >+ } >+ >+ if (rq_param->yuv420) { >+ total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; >+ >+ if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request >+ req128_l = 0; >+ req128_c = 0; >+ swath_bytes_l = full_swath_bytes_packed_l; >+ swath_bytes_c = full_swath_bytes_packed_c; >+ } else { //128b request (for luma only for yuv420 8bpc) >+ req128_l = 1; >+ req128_c = 0; >+ swath_bytes_l = full_swath_bytes_packed_l / 2; >+ swath_bytes_c = full_swath_bytes_packed_c; >+ } >+ // Note: assumption, the config that pass in will fit into >+ // the detiled buffer. >+ } else { >+ total_swath_bytes = 2 * full_swath_bytes_packed_l; >+ >+ if (total_swath_bytes <= detile_buf_size_in_bytes) >+ req128_l = 0; >+ else >+ req128_l = 1; >+ >+ swath_bytes_l = total_swath_bytes; >+ swath_bytes_c = 0; >+ } >+ rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; >+ rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; >+ >+ if (surf_linear) { >+ log2_swath_height_l = 0; >+ log2_swath_height_c = 0; >+ } else if (!surf_vert) { >+ log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l; >+ log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c; >+ } else { >+ log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l; >+ log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c; >+ } >+ rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; >+ rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; >+ >+ dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); >+ dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); >+ dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", >+ __func__, >+ full_swath_bytes_packed_l); >+ dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", >+ __func__, >+ full_swath_bytes_packed_c); >+} >+ >+static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, >+ display_data_rq_dlg_params_st *rq_dlg_param, >+ display_data_rq_misc_params_st *rq_misc_param, >+ display_data_rq_sizing_params_st *rq_sizing_param, >+ unsigned int vp_width, >+ unsigned int vp_height, >+ unsigned int data_pitch, >+ unsigned int meta_pitch, >+ unsigned int source_format, >+ unsigned int tiling, >+ unsigned int macro_tile_size, >+ unsigned int source_scan, >+ unsigned int is_chroma) >+{ >+ bool surf_linear = (tiling == dm_sw_linear); >+ bool surf_vert = (source_scan == dm_vert); >+ >+ unsigned int bytes_per_element; >+ unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format), >+ false); >+ unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format), >+ true); >+ >+ unsigned int blk256_width = 0; >+ unsigned int blk256_height = 0; >+ >+ unsigned int blk256_width_y = 0; >+ unsigned int blk256_height_y = 0; >+ unsigned int blk256_width_c = 0; >+ unsigned int blk256_height_c = 0; >+ unsigned int log2_bytes_per_element; >+ unsigned int log2_blk256_width; >+ unsigned int log2_blk256_height; >+ unsigned int blk_bytes; >+ unsigned int log2_blk_bytes; >+ unsigned int log2_blk_height; >+ unsigned int log2_blk_width; >+ unsigned int log2_meta_req_bytes; >+ unsigned int log2_meta_req_height; >+ unsigned int log2_meta_req_width; >+ unsigned int meta_req_width; >+ unsigned int meta_req_height; >+ unsigned int log2_meta_row_height; >+ unsigned int meta_row_width_ub; >+ unsigned int log2_meta_chunk_bytes; >+ unsigned int log2_meta_chunk_height; >+ >+ //full sized meta chunk width in unit of data elements >+ unsigned int log2_meta_chunk_width; >+ unsigned int log2_min_meta_chunk_bytes; >+ unsigned int min_meta_chunk_width; >+ unsigned int meta_chunk_width; >+ unsigned int meta_chunk_per_row_int; >+ unsigned int meta_row_remainder; >+ unsigned int meta_chunk_threshold; >+ unsigned int meta_blk_bytes; >+ unsigned int meta_blk_height; >+ unsigned int meta_blk_width; >+ unsigned int meta_surface_bytes; >+ unsigned int vmpg_bytes; >+ unsigned int meta_pte_req_per_frame_ub; >+ unsigned int meta_pte_bytes_per_frame_ub; >+ const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); >+ const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; >+ const unsigned int pde_proc_buffer_size_64k_reqs = >+ mode_lib->ip.pde_proc_buffer_size_64k_reqs; >+ >+ unsigned int log2_vmpg_height = 0; >+ unsigned int log2_vmpg_width = 0; >+ unsigned int log2_dpte_req_height_ptes = 0; >+ unsigned int log2_dpte_req_height = 0; >+ unsigned int log2_dpte_req_width = 0; >+ unsigned int log2_dpte_row_height_linear = 0; >+ unsigned int log2_dpte_row_height = 0; >+ unsigned int log2_dpte_group_width = 0; >+ unsigned int dpte_row_width_ub = 0; >+ unsigned int dpte_req_height = 0; >+ unsigned int dpte_req_width = 0; >+ unsigned int dpte_group_width = 0; >+ unsigned int log2_dpte_group_bytes = 0; >+ unsigned int log2_dpte_group_length = 0; >+ unsigned int pde_buf_entries; >+ bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10); >+ >+ Calculate256BBlockSizes((enum source_format_class)(source_format), >+ (enum dm_swizzle_mode)(tiling), >+ bytes_per_element_y, >+ bytes_per_element_c, >+ &blk256_height_y, >+ &blk256_height_c, >+ &blk256_width_y, >+ &blk256_width_c); >+ >+ if (!is_chroma) { >+ blk256_width = blk256_width_y; >+ blk256_height = blk256_height_y; >+ bytes_per_element = bytes_per_element_y; >+ } else { >+ blk256_width = blk256_width_c; >+ blk256_height = blk256_height_c; >+ bytes_per_element = bytes_per_element_c; >+ } >+ >+ log2_bytes_per_element = dml_log2(bytes_per_element); >+ >+ dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); >+ dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); >+ dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); >+ dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); >+ >+ log2_blk256_width = dml_log2((double) blk256_width); >+ log2_blk256_height = dml_log2((double) blk256_height); >+ blk_bytes = surf_linear ? >+ 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); >+ log2_blk_bytes = dml_log2((double) blk_bytes); >+ log2_blk_height = 0; >+ log2_blk_width = 0; >+ >+ // remember log rule >+ // "+" in log is multiply >+ // "-" in log is divide >+ // "/2" is like square root >+ // blk is vertical biased >+ if (tiling != dm_sw_linear) >+ log2_blk_height = log2_blk256_height >+ + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); >+ else >+ log2_blk_height = 0; // blk height of 1 >+ >+ log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; >+ >+ if (!surf_vert) { >+ rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) >+ + blk256_width; >+ rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; >+ } else { >+ rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1) >+ + blk256_height; >+ rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; >+ } >+ >+ if (!surf_vert) >+ rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height >+ * bytes_per_element; >+ else >+ rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width >+ * bytes_per_element; >+ >+ rq_misc_param->blk256_height = blk256_height; >+ rq_misc_param->blk256_width = blk256_width; >+ >+ // ------- >+ // meta >+ // ------- >+ log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element >+ >+ // each 64b meta request for dcn is 8x8 meta elements and >+ // a meta element covers one 256b block of the the data surface. >+ log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 >+ log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element >+ - log2_meta_req_height; >+ meta_req_width = 1 << log2_meta_req_width; >+ meta_req_height = 1 << log2_meta_req_height; >+ log2_meta_row_height = 0; >+ meta_row_width_ub = 0; >+ >+ // the dimensions of a meta row are meta_row_width x meta_row_height in elements. >+ // calculate upper bound of the meta_row_width >+ if (!surf_vert) { >+ log2_meta_row_height = log2_meta_req_height; >+ meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) >+ + meta_req_width; >+ rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; >+ } else { >+ log2_meta_row_height = log2_meta_req_width; >+ meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) >+ + meta_req_height; >+ rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; >+ } >+ rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; >+ >+ rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; >+ >+ log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); >+ log2_meta_chunk_height = log2_meta_row_height; >+ >+ //full sized meta chunk width in unit of data elements >+ log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element >+ - log2_meta_chunk_height; >+ log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); >+ min_meta_chunk_width = 1 >+ << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element >+ - log2_meta_chunk_height); >+ meta_chunk_width = 1 << log2_meta_chunk_width; >+ meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); >+ meta_row_remainder = meta_row_width_ub % meta_chunk_width; >+ meta_chunk_threshold = 0; >+ meta_blk_bytes = 4096; >+ meta_blk_height = blk256_height * 64; >+ meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; >+ meta_surface_bytes = meta_pitch >+ * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) >+ * bytes_per_element / 256; >+ vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; >+ meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, >+ 8 * vmpg_bytes, >+ 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); >+ meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request >+ rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; >+ >+ dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); >+ dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width); >+ dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); >+ dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", >+ __func__, >+ meta_pte_req_per_frame_ub); >+ dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", >+ __func__, >+ meta_pte_bytes_per_frame_ub); >+ >+ if (!surf_vert) >+ meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; >+ else >+ meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; >+ >+ if (meta_row_remainder <= meta_chunk_threshold) >+ rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; >+ else >+ rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; >+ >+ // ------ >+ // dpte >+ // ------ >+ if (surf_linear) { >+ log2_vmpg_height = 0; // one line high >+ } else { >+ log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; >+ } >+ log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; >+ >+ // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. >+ if (surf_linear) { //one 64B PTE request returns 8 PTEs >+ log2_dpte_req_height_ptes = 0; >+ log2_dpte_req_width = log2_vmpg_width + 3; >+ log2_dpte_req_height = 0; >+ } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size >+ //one 64B req gives 8x1 PTEs for 4KB tile >+ log2_dpte_req_height_ptes = 0; >+ log2_dpte_req_width = log2_blk_width + 3; >+ log2_dpte_req_height = log2_blk_height + 0; >+ } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB >+ //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB >+ log2_dpte_req_height_ptes = 4; >+ log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width >+ log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height >+ } else { //64KB page size and must 64KB tile block >+ //one 64B req gives 8x1 PTEs for 64KB tile >+ log2_dpte_req_height_ptes = 0; >+ log2_dpte_req_width = log2_blk_width + 3; >+ log2_dpte_req_height = log2_blk_height + 0; >+ } >+ >+ // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height >+ // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent >+ // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) >+ //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; >+ //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; >+ dpte_req_height = 1 << log2_dpte_req_height; >+ dpte_req_width = 1 << log2_dpte_req_width; >+ >+ // calculate pitch dpte row buffer can hold >+ // round the result down to a power of two. >+ pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; >+ if (surf_linear) { >+ unsigned int dpte_row_height; >+ >+ log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries >+ / bytes_per_element, >+ dpte_buf_in_pte_reqs >+ * dpte_req_width) >+ / data_pitch), >+ 1); >+ >+ ASSERT(log2_dpte_row_height_linear >= 3); >+ >+ if (log2_dpte_row_height_linear > 7) >+ log2_dpte_row_height_linear = 7; >+ >+ log2_dpte_row_height = log2_dpte_row_height_linear; >+ // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. >+ // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. >+ dpte_row_height = 1 << log2_dpte_row_height; >+ dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, >+ dpte_req_width, >+ 1) + dpte_req_width; >+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; >+ } else { >+ // the upper bound of the dpte_row_width without dependency on viewport position follows. >+ // for tiled mode, row height is the same as req height and row store up to vp size upper bound >+ if (!surf_vert) { >+ log2_dpte_row_height = log2_dpte_req_height; >+ dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) >+ + dpte_req_width; >+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; >+ } else { >+ log2_dpte_row_height = >+ (log2_blk_width < log2_dpte_req_width) ? >+ log2_blk_width : log2_dpte_req_width; >+ dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) >+ + dpte_req_height; >+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; >+ } >+ } >+ if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB >+ rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request >+ else >+ rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request >+ >+ rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; >+ >+ // the dpte_group_bytes is reduced for the specific case of vertical >+ // access of a tile surface that has dpte request of 8x1 ptes. >+ if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group >+ rq_sizing_param->dpte_group_bytes = 512; >+ else >+ //full size >+ rq_sizing_param->dpte_group_bytes = 2048; >+ >+ //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. >+ log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); >+ log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests >+ >+ // full sized data pte group width in elements >+ if (!surf_vert) >+ log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; >+ else >+ log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; >+ >+ //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B >+ if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB >+ log2_dpte_group_width = log2_dpte_group_width - 1; >+ >+ dpte_group_width = 1 << log2_dpte_group_width; >+ >+ // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, >+ // the upper bound for the dpte groups per row is as follows. >+ rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, >+ 1); >+} >+ >+static void get_surf_rq_param(struct display_mode_lib *mode_lib, >+ display_data_rq_sizing_params_st *rq_sizing_param, >+ display_data_rq_dlg_params_st *rq_dlg_param, >+ display_data_rq_misc_params_st *rq_misc_param, >+ const display_pipe_source_params_st pipe_src_param, >+ bool is_chroma) >+{ >+ bool mode_422 = 0; >+ unsigned int vp_width = 0; >+ unsigned int vp_height = 0; >+ unsigned int data_pitch = 0; >+ unsigned int meta_pitch = 0; >+ unsigned int ppe = mode_422 ? 2 : 1; >+ >+ // FIXME check if ppe apply for both luma and chroma in 422 case >+ if (is_chroma) { >+ vp_width = pipe_src_param.viewport_width_c / ppe; >+ vp_height = pipe_src_param.viewport_height_c; >+ data_pitch = pipe_src_param.data_pitch_c; >+ meta_pitch = pipe_src_param.meta_pitch_c; >+ } else { >+ vp_width = pipe_src_param.viewport_width / ppe; >+ vp_height = pipe_src_param.viewport_height; >+ data_pitch = pipe_src_param.data_pitch; >+ meta_pitch = pipe_src_param.meta_pitch; >+ } >+ >+ rq_sizing_param->chunk_bytes = 8192; >+ >+ if (rq_sizing_param->chunk_bytes == 64 * 1024) >+ rq_sizing_param->min_chunk_bytes = 0; >+ else >+ rq_sizing_param->min_chunk_bytes = 1024; >+ >+ rq_sizing_param->meta_chunk_bytes = 2048; >+ rq_sizing_param->min_meta_chunk_bytes = 256; >+ >+ rq_sizing_param->mpte_group_bytes = 2048; >+ >+ get_meta_and_pte_attr(mode_lib, >+ rq_dlg_param, >+ rq_misc_param, >+ rq_sizing_param, >+ vp_width, >+ vp_height, >+ data_pitch, >+ meta_pitch, >+ pipe_src_param.source_format, >+ pipe_src_param.sw_mode, >+ pipe_src_param.macro_tile_size, >+ pipe_src_param.source_scan, >+ is_chroma); >+} >+ >+static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, >+ display_rq_params_st *rq_param, >+ const display_pipe_source_params_st pipe_src_param) >+{ >+ // get param for luma surface >+ rq_param->yuv420 = pipe_src_param.source_format == dm_420_8 >+ || pipe_src_param.source_format == dm_420_10; >+ rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10; >+ >+ get_surf_rq_param(mode_lib, >+ &(rq_param->sizing.rq_l), >+ &(rq_param->dlg.rq_l), >+ &(rq_param->misc.rq_l), >+ pipe_src_param, >+ 0); >+ >+ if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) { >+ // get param for chroma surface >+ get_surf_rq_param(mode_lib, >+ &(rq_param->sizing.rq_c), >+ &(rq_param->dlg.rq_c), >+ &(rq_param->misc.rq_c), >+ pipe_src_param, >+ 1); >+ } >+ >+ // calculate how to split the det buffer space between luma and chroma >+ handle_det_buf_split(mode_lib, rq_param, pipe_src_param); >+ print__rq_params_st(mode_lib, *rq_param); >+} >+ >+void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, >+ display_rq_regs_st *rq_regs, >+ const display_pipe_params_st pipe_param) >+{ >+ display_rq_params_st rq_param = {0}; >+ >+ memset(rq_regs, 0, sizeof(*rq_regs)); >+ dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src); >+ extract_rq_regs(mode_lib, rq_regs, rq_param); >+ >+ print__rq_regs_st(mode_lib, *rq_regs); >+} >+ >+// Note: currently taken in as is. >+// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. >+static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, >+ const display_e2e_pipe_params_st *e2e_pipe_param, >+ const unsigned int num_pipes, >+ const unsigned int pipe_idx, >+ display_dlg_regs_st *disp_dlg_regs, >+ display_ttu_regs_st *disp_ttu_regs, >+ const display_rq_dlg_params_st rq_dlg_param, >+ const display_dlg_sys_params_st dlg_sys_param, >+ const bool cstate_en, >+ const bool pstate_en) >+{ >+ const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; >+ const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; >+ const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; >+ const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; >+ const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; >+ const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; >+ >+ // ------------------------- >+ // Section 1.15.2.1: OTG dependent Params >+ // ------------------------- >+ // Timing >+ unsigned int htotal = dst->htotal; >+// unsigned int hblank_start = dst.hblank_start; // TODO: Remove >+ unsigned int hblank_end = dst->hblank_end; >+ unsigned int vblank_start = dst->vblank_start; >+ unsigned int vblank_end = dst->vblank_end; >+ unsigned int min_vblank = mode_lib->ip.min_vblank_lines; >+ >+ double dppclk_freq_in_mhz = clks->dppclk_mhz; >+ double dispclk_freq_in_mhz = clks->dispclk_mhz; >+ double refclk_freq_in_mhz = clks->refclk_mhz; >+ double pclk_freq_in_mhz = dst->pixel_rate_mhz; >+ bool interlaced = dst->interlaced; >+ >+ double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; >+ >+ double min_dcfclk_mhz; >+ double t_calc_us; >+ double min_ttu_vblank; >+ >+ double min_dst_y_ttu_vblank; >+ unsigned int dlg_vblank_start; >+ bool dual_plane; >+ bool mode_422; >+ unsigned int access_dir; >+ unsigned int vp_height_l; >+ unsigned int vp_width_l; >+ unsigned int vp_height_c; >+ unsigned int vp_width_c; >+ >+ // Scaling >+ unsigned int htaps_l; >+ unsigned int htaps_c; >+ double hratio_l; >+ double hratio_c; >+ double vratio_l; >+ double vratio_c; >+ bool scl_enable; >+ >+ double line_time_in_us; >+ // double vinit_l; >+ // double vinit_c; >+ // double vinit_bot_l; >+ // double vinit_bot_c; >+ >+ // unsigned int swath_height_l; >+ unsigned int swath_width_ub_l; >+ // unsigned int dpte_bytes_per_row_ub_l; >+ unsigned int dpte_groups_per_row_ub_l; >+ // unsigned int meta_pte_bytes_per_frame_ub_l; >+ // unsigned int meta_bytes_per_row_ub_l; >+ >+ // unsigned int swath_height_c; >+ unsigned int swath_width_ub_c; >+ // unsigned int dpte_bytes_per_row_ub_c; >+ unsigned int dpte_groups_per_row_ub_c; >+ >+ unsigned int meta_chunks_per_row_ub_l; >+ unsigned int meta_chunks_per_row_ub_c; >+ unsigned int vupdate_offset; >+ unsigned int vupdate_width; >+ unsigned int vready_offset; >+ >+ unsigned int dppclk_delay_subtotal; >+ unsigned int dispclk_delay_subtotal; >+ unsigned int pixel_rate_delay_subtotal; >+ >+ unsigned int vstartup_start; >+ unsigned int dst_x_after_scaler; >+ unsigned int dst_y_after_scaler; >+ double line_wait; >+ double dst_y_prefetch; >+ double dst_y_per_vm_vblank; >+ double dst_y_per_row_vblank; >+ double dst_y_per_vm_flip; >+ double dst_y_per_row_flip; >+ double min_dst_y_per_vm_vblank; >+ double min_dst_y_per_row_vblank; >+ double lsw; >+ double vratio_pre_l; >+ double vratio_pre_c; >+ unsigned int req_per_swath_ub_l; >+ unsigned int req_per_swath_ub_c; >+ unsigned int meta_row_height_l; >+ unsigned int meta_row_height_c; >+ unsigned int swath_width_pixels_ub_l; >+ unsigned int swath_width_pixels_ub_c; >+ unsigned int scaler_rec_in_width_l; >+ unsigned int scaler_rec_in_width_c; >+ unsigned int dpte_row_height_l; >+ unsigned int dpte_row_height_c; >+ double hscale_pixel_rate_l; >+ double hscale_pixel_rate_c; >+ double min_hratio_fact_l; >+ double min_hratio_fact_c; >+ double refcyc_per_line_delivery_pre_l; >+ double refcyc_per_line_delivery_pre_c; >+ double refcyc_per_line_delivery_l; >+ double refcyc_per_line_delivery_c; >+ >+ double refcyc_per_req_delivery_pre_l; >+ double refcyc_per_req_delivery_pre_c; >+ double refcyc_per_req_delivery_l; >+ double refcyc_per_req_delivery_c; >+ >+ unsigned int full_recout_width; >+ double xfc_transfer_delay; >+ double xfc_precharge_delay; >+ double xfc_remote_surface_flip_latency; >+ double xfc_dst_y_delta_drq_limit; >+ double xfc_prefetch_margin; >+ double refcyc_per_req_delivery_pre_cur0; >+ double refcyc_per_req_delivery_cur0; >+ double refcyc_per_req_delivery_pre_cur1; >+ double refcyc_per_req_delivery_cur1; >+ >+ memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); >+ memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); >+ >+ dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); >+ dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); >+ >+ dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); >+ ASSERT(ref_freq_to_pix_freq < 4.0); >+ >+ disp_dlg_regs->ref_freq_to_pix_freq = >+ (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); >+ disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal >+ * dml_pow(2, 8)); >+ disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits >+ disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end >+ * (double) ref_freq_to_pix_freq); >+ ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); >+ >+ min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; >+ t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); >+ min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; >+ dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; >+ >+ disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start >+ + min_dst_y_ttu_vblank) * dml_pow(2, 2)); >+ ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); >+ >+ dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n", >+ __func__, >+ min_dcfclk_mhz); >+ dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n", >+ __func__, >+ min_ttu_vblank); >+ dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n", >+ __func__, >+ min_dst_y_ttu_vblank); >+ dml_print("DML_DLG: %s: t_calc_us = %3.2f\n", >+ __func__, >+ t_calc_us); >+ dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n", >+ __func__, >+ disp_dlg_regs->min_dst_y_next_start); >+ dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", >+ __func__, >+ ref_freq_to_pix_freq); >+ >+ // ------------------------- >+ // Section 1.15.2.2: Prefetch, Active and TTU >+ // ------------------------- >+ // Prefetch Calc >+ // Source >+// dcc_en = src.dcc; >+ dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); >+ mode_422 = 0; // FIXME >+ access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed >+// bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); >+// bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); >+ vp_height_l = src->viewport_height; >+ vp_width_l = src->viewport_width; >+ vp_height_c = src->viewport_height_c; >+ vp_width_c = src->viewport_width_c; >+ >+ // Scaling >+ htaps_l = taps->htaps; >+ htaps_c = taps->htaps_c; >+ hratio_l = scl->hscl_ratio; >+ hratio_c = scl->hscl_ratio_c; >+ vratio_l = scl->vscl_ratio; >+ vratio_c = scl->vscl_ratio_c; >+ scl_enable = scl->scl_enable; >+ >+ line_time_in_us = (htotal / pclk_freq_in_mhz); >+// vinit_l = scl.vinit; >+// vinit_c = scl.vinit_c; >+// vinit_bot_l = scl.vinit_bot; >+// vinit_bot_c = scl.vinit_bot_c; >+ >+// unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height; >+ swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; >+// unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub; >+ dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; >+// unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub; >+// unsigned int meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub; >+ >+// unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height; >+ swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; >+ // dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub; >+ dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; >+ >+ meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; >+ meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; >+ vupdate_offset = dst->vupdate_offset; >+ vupdate_width = dst->vupdate_width; >+ vready_offset = dst->vready_offset; >+ >+ dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; >+ dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; >+ >+ if (scl_enable) >+ dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; >+ else >+ dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; >+ >+ dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter >+ + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; >+ >+ if (dout->dsc_enable) { >+ double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ dispclk_delay_subtotal += dsc_delay; >+ } >+ >+ pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz >+ + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; >+ >+ vstartup_start = dst->vstartup_start; >+ if (interlaced) { >+ if (vstartup_start / 2.0 >+ - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal >+ <= vblank_end / 2.0) >+ disp_dlg_regs->vready_after_vcount0 = 1; >+ else >+ disp_dlg_regs->vready_after_vcount0 = 0; >+ } else { >+ if (vstartup_start >+ - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal >+ <= vblank_end) >+ disp_dlg_regs->vready_after_vcount0 = 1; >+ else >+ disp_dlg_regs->vready_after_vcount0 = 0; >+ } >+ >+ // TODO: Where is this coming from? >+ if (interlaced) >+ vstartup_start = vstartup_start / 2; >+ >+ // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? >+ if (vstartup_start >= min_vblank) { >+ dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n", >+ __func__, >+ vblank_start, >+ vblank_end); >+ dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", >+ __func__, >+ vstartup_start, >+ min_vblank); >+ min_vblank = vstartup_start + 1; >+ dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", >+ __func__, >+ vstartup_start, >+ min_vblank); >+ } >+ >+ dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); >+ dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", >+ __func__, >+ pixel_rate_delay_subtotal); >+ dml_print("DML_DLG: %s: dst_x_after_scaler = %d\n", >+ __func__, >+ dst_x_after_scaler); >+ dml_print("DML_DLG: %s: dst_y_after_scaler = %d\n", >+ __func__, >+ dst_y_after_scaler); >+ >+ // Lwait >+ line_wait = mode_lib->soc.urgent_latency_us; >+ if (cstate_en) >+ line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); >+ if (pstate_en) >+ line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us >+ + mode_lib->soc.urgent_latency_us, >+ line_wait); >+ line_wait = line_wait / line_time_in_us; >+ >+ dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); >+ >+ dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ min_dst_y_per_vm_vblank = 8.0; >+ min_dst_y_per_row_vblank = 16.0; >+ >+ // magic! >+ if (htotal <= 75) { >+ min_vblank = 300; >+ min_dst_y_per_vm_vblank = 100.0; >+ min_dst_y_per_row_vblank = 100.0; >+ } >+ >+ dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); >+ dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); >+ >+ ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); >+ ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); >+ >+ ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); >+ lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); >+ >+ dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw); >+ >+ vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l); >+ dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); >+ >+ // Active >+ req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; >+ req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; >+ meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; >+ meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; >+ swath_width_pixels_ub_l = 0; >+ swath_width_pixels_ub_c = 0; >+ scaler_rec_in_width_l = 0; >+ scaler_rec_in_width_c = 0; >+ dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; >+ dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; >+ >+ if (mode_422) { >+ swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element >+ swath_width_pixels_ub_c = swath_width_ub_c * 2; >+ } else { >+ swath_width_pixels_ub_l = swath_width_ub_l * 1; >+ swath_width_pixels_ub_c = swath_width_ub_c * 1; >+ } >+ >+ hscale_pixel_rate_l = 0.; >+ hscale_pixel_rate_c = 0.; >+ min_hratio_fact_l = 1.0; >+ min_hratio_fact_c = 1.0; >+ >+ if (htaps_l <= 1) >+ min_hratio_fact_l = 2.0; >+ else if (htaps_l <= 6) { >+ if ((hratio_l * 2.0) > 4.0) >+ min_hratio_fact_l = 4.0; >+ else >+ min_hratio_fact_l = hratio_l * 2.0; >+ } else { >+ if (hratio_l > 4.0) >+ min_hratio_fact_l = 4.0; >+ else >+ min_hratio_fact_l = hratio_l; >+ } >+ >+ hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; >+ >+ if (htaps_c <= 1) >+ min_hratio_fact_c = 2.0; >+ else if (htaps_c <= 6) { >+ if ((hratio_c * 2.0) > 4.0) >+ min_hratio_fact_c = 4.0; >+ else >+ min_hratio_fact_c = hratio_c * 2.0; >+ } else { >+ if (hratio_c > 4.0) >+ min_hratio_fact_c = 4.0; >+ else >+ min_hratio_fact_c = hratio_c; >+ } >+ >+ hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; >+ >+ refcyc_per_line_delivery_pre_l = 0.; >+ refcyc_per_line_delivery_pre_c = 0.; >+ refcyc_per_line_delivery_l = 0.; >+ refcyc_per_line_delivery_c = 0.; >+ >+ refcyc_per_req_delivery_pre_l = 0.; >+ refcyc_per_req_delivery_pre_c = 0.; >+ refcyc_per_req_delivery_l = 0.; >+ refcyc_per_req_delivery_c = 0.; >+ >+ full_recout_width = 0; >+ // In ODM >+ if (src->is_hsplit) { >+ // This "hack" is only allowed (and valid) for MPC combine. In ODM >+ // combine, you MUST specify the full_recout_width...according to Oswin >+ if (dst->full_recout_width == 0 && !dst->odm_combine) { >+ dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", >+ __func__); >+ full_recout_width = dst->recout_width * 2; // assume half split for dcn1 >+ } else >+ full_recout_width = dst->full_recout_width; >+ } else >+ full_recout_width = dst->recout_width; >+ >+ // As of DCN2, mpc_combine and odm_combine are mutually exclusive >+ refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_pre_l, >+ hscale_pixel_rate_l, >+ swath_width_pixels_ub_l, >+ 1); // per line >+ >+ refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_l, >+ hscale_pixel_rate_l, >+ swath_width_pixels_ub_l, >+ 1); // per line >+ >+ dml_print("DML_DLG: %s: full_recout_width = %d\n", >+ __func__, >+ full_recout_width); >+ dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", >+ __func__, >+ hscale_pixel_rate_l); >+ dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", >+ __func__, >+ refcyc_per_line_delivery_pre_l); >+ dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", >+ __func__, >+ refcyc_per_line_delivery_l); >+ >+ if (dual_plane) { >+ refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_pre_c, >+ hscale_pixel_rate_c, >+ swath_width_pixels_ub_c, >+ 1); // per line >+ >+ refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_c, >+ hscale_pixel_rate_c, >+ swath_width_pixels_ub_c, >+ 1); // per line >+ >+ dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", >+ __func__, >+ refcyc_per_line_delivery_pre_c); >+ dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", >+ __func__, >+ refcyc_per_line_delivery_c); >+ } >+ >+ // TTU - Luma / Chroma >+ if (access_dir) { // vertical access >+ scaler_rec_in_width_l = vp_height_l; >+ scaler_rec_in_width_c = vp_height_c; >+ } else { >+ scaler_rec_in_width_l = vp_width_l; >+ scaler_rec_in_width_c = vp_width_c; >+ } >+ >+ refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_pre_l, >+ hscale_pixel_rate_l, >+ scaler_rec_in_width_l, >+ req_per_swath_ub_l); // per req >+ refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_l, >+ hscale_pixel_rate_l, >+ scaler_rec_in_width_l, >+ req_per_swath_ub_l); // per req >+ >+ dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", >+ __func__, >+ refcyc_per_req_delivery_pre_l); >+ dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", >+ __func__, >+ refcyc_per_req_delivery_l); >+ >+ ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); >+ ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); >+ >+ if (dual_plane) { >+ refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_pre_c, >+ hscale_pixel_rate_c, >+ scaler_rec_in_width_c, >+ req_per_swath_ub_c); // per req >+ refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_c, >+ hscale_pixel_rate_c, >+ scaler_rec_in_width_c, >+ req_per_swath_ub_c); // per req >+ >+ dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", >+ __func__, >+ refcyc_per_req_delivery_pre_c); >+ dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", >+ __func__, >+ refcyc_per_req_delivery_c); >+ >+ ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); >+ ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); >+ } >+ >+ // XFC >+ xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ xfc_precharge_delay = get_xfc_precharge_delay(mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency; >+ xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ >+ // TTU - Cursor >+ refcyc_per_req_delivery_pre_cur0 = 0.0; >+ refcyc_per_req_delivery_cur0 = 0.0; >+ if (src->num_cursors > 0) { >+ calculate_ttu_cursor(mode_lib, >+ &refcyc_per_req_delivery_pre_cur0, >+ &refcyc_per_req_delivery_cur0, >+ refclk_freq_in_mhz, >+ ref_freq_to_pix_freq, >+ hscale_pixel_rate_l, >+ scl->hscl_ratio, >+ vratio_pre_l, >+ vratio_l, >+ src->cur0_src_width, >+ (enum cursor_bpp)(src->cur0_bpp)); >+ } >+ >+ refcyc_per_req_delivery_pre_cur1 = 0.0; >+ refcyc_per_req_delivery_cur1 = 0.0; >+ if (src->num_cursors > 1) { >+ calculate_ttu_cursor(mode_lib, >+ &refcyc_per_req_delivery_pre_cur1, >+ &refcyc_per_req_delivery_cur1, >+ refclk_freq_in_mhz, >+ ref_freq_to_pix_freq, >+ hscale_pixel_rate_l, >+ scl->hscl_ratio, >+ vratio_pre_l, >+ vratio_l, >+ src->cur1_src_width, >+ (enum cursor_bpp)(src->cur1_bpp)); >+ } >+ >+ // TTU - Misc >+ // all hard-coded >+ >+ // Assignment to register structures >+ disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line >+ disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk >+ ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); >+ disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); >+ disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); >+ disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); >+ disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); >+ disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); >+ >+ disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); >+ disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); >+ >+ disp_dlg_regs->refcyc_per_pte_group_vblank_l = >+ (unsigned int) (dst_y_per_row_vblank * (double) htotal >+ * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); >+ ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); >+ >+ if (dual_plane) { >+ disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank >+ * (double) htotal * ref_freq_to_pix_freq >+ / (double) dpte_groups_per_row_ub_c); >+ ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c >+ < (unsigned int) dml_pow(2, 13)); >+ } >+ >+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = >+ (unsigned int) (dst_y_per_row_vblank * (double) htotal >+ * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); >+ ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); >+ >+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = >+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now >+ >+ disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal >+ * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; >+ disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal >+ * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; >+ >+ if (dual_plane) { >+ disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip >+ * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; >+ disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip >+ * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; >+ } >+ >+ disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l >+ / (double) vratio_l * dml_pow(2, 2)); >+ ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); >+ >+ if (dual_plane) { >+ disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c >+ / (double) vratio_c * dml_pow(2, 2)); >+ if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { >+ dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", >+ __func__, >+ disp_dlg_regs->dst_y_per_pte_row_nom_c, >+ (unsigned int) dml_pow(2, 17) - 1); >+ } >+ } >+ >+ disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l >+ / (double) vratio_l * dml_pow(2, 2)); >+ ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); >+ >+ disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now >+ >+ disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l >+ / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq >+ / (double) dpte_groups_per_row_ub_l); >+ if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; >+ disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l >+ / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq >+ / (double) meta_chunks_per_row_ub_l); >+ if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; >+ >+ if (dual_plane) { >+ disp_dlg_regs->refcyc_per_pte_group_nom_c = >+ (unsigned int) ((double) dpte_row_height_c / (double) vratio_c >+ * (double) htotal * ref_freq_to_pix_freq >+ / (double) dpte_groups_per_row_ub_c); >+ if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; >+ >+ // TODO: Is this the right calculation? Does htotal need to be halved? >+ disp_dlg_regs->refcyc_per_meta_chunk_nom_c = >+ (unsigned int) ((double) meta_row_height_c / (double) vratio_c >+ * (double) htotal * ref_freq_to_pix_freq >+ / (double) meta_chunks_per_row_ub_c); >+ if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; >+ } >+ >+ disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, >+ 1); >+ disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, >+ 1); >+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); >+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); >+ >+ disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, >+ 1); >+ disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, >+ 1); >+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); >+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); >+ >+ disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; >+ disp_dlg_regs->dst_y_offset_cur0 = 0; >+ disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; >+ disp_dlg_regs->dst_y_offset_cur1 = 0; >+ >+ disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; >+ disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; >+ disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; >+ disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz, >+ 1); >+ >+ // slave has to have this value also set to off >+ if (src->xfc_enable && !src->xfc_slave) >+ disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); >+ else >+ disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off >+ >+ disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = >+ (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = >+ (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 >+ * dml_pow(2, 10)); >+ disp_ttu_regs->qos_level_low_wm = 0; >+ ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); >+ disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal >+ * ref_freq_to_pix_freq); >+ /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/ >+ >+ disp_ttu_regs->qos_level_flip = 14; >+ disp_ttu_regs->qos_level_fixed_l = 8; >+ disp_ttu_regs->qos_level_fixed_c = 8; >+ disp_ttu_regs->qos_level_fixed_cur0 = 8; >+ disp_ttu_regs->qos_ramp_disable_l = 0; >+ disp_ttu_regs->qos_ramp_disable_c = 0; >+ disp_ttu_regs->qos_ramp_disable_cur0 = 0; >+ >+ disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; >+ ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); >+ >+ print__ttu_regs_st(mode_lib, *disp_ttu_regs); >+ print__dlg_regs_st(mode_lib, *disp_dlg_regs); >+} >+ >+void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, >+ display_dlg_regs_st *dlg_regs, >+ display_ttu_regs_st *ttu_regs, >+ display_e2e_pipe_params_st *e2e_pipe_param, >+ const unsigned int num_pipes, >+ const unsigned int pipe_idx, >+ const bool cstate_en, >+ const bool pstate_en, >+ const bool vm_en, >+ const bool ignore_viewport_pos, >+ const bool immediate_flip_support) >+{ >+ display_rq_params_st rq_param = {0}; >+ display_dlg_sys_params_st dlg_sys_param = {0}; >+ >+ // Get watermark and Tex. >+ dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, >+ e2e_pipe_param, >+ num_pipes); >+ dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, >+ e2e_pipe_param, >+ num_pipes); >+ dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, >+ e2e_pipe_param, >+ num_pipes); >+ dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency >+ / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated >+ >+ print__dlg_sys_params_st(mode_lib, dlg_sys_param); >+ >+ // system parameter calculation done >+ >+ dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); >+ dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src); >+ dml20v2_rq_dlg_get_dlg_params(mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx, >+ dlg_regs, >+ ttu_regs, >+ rq_param.dlg, >+ dlg_sys_param, >+ cstate_en, >+ pstate_en); >+ dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); >+} >+ >+static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, >+ double *refcyc_per_req_delivery_pre_cur, >+ double *refcyc_per_req_delivery_cur, >+ double refclk_freq_in_mhz, >+ double ref_freq_to_pix_freq, >+ double hscale_pixel_rate_l, >+ double hscl_ratio, >+ double vratio_pre_l, >+ double vratio_l, >+ unsigned int cur_width, >+ enum cursor_bpp cur_bpp) >+{ >+ unsigned int cur_src_width = cur_width; >+ unsigned int cur_req_size = 0; >+ unsigned int cur_req_width = 0; >+ double cur_width_ub = 0.0; >+ double cur_req_per_width = 0.0; >+ double hactive_cur = 0.0; >+ >+ ASSERT(cur_src_width <= 256); >+ >+ *refcyc_per_req_delivery_pre_cur = 0.0; >+ *refcyc_per_req_delivery_cur = 0.0; >+ if (cur_src_width > 0) { >+ unsigned int cur_bit_per_pixel = 0; >+ >+ if (cur_bpp == dm_cur_2bit) { >+ cur_req_size = 64; // byte >+ cur_bit_per_pixel = 2; >+ } else { // 32bit >+ cur_bit_per_pixel = 32; >+ if (cur_src_width >= 1 && cur_src_width <= 16) >+ cur_req_size = 64; >+ else if (cur_src_width >= 17 && cur_src_width <= 31) >+ cur_req_size = 128; >+ else >+ cur_req_size = 256; >+ } >+ >+ cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); >+ cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) >+ * (double) cur_req_width; >+ cur_req_per_width = cur_width_ub / (double) cur_req_width; >+ hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor >+ >+ if (vratio_pre_l <= 1.0) { >+ *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq >+ / (double) cur_req_per_width; >+ } else { >+ *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz >+ * (double) cur_src_width / hscale_pixel_rate_l >+ / (double) cur_req_per_width; >+ } >+ >+ ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); >+ >+ if (vratio_l <= 1.0) { >+ *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq >+ / (double) cur_req_per_width; >+ } else { >+ *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz >+ * (double) cur_src_width / hscale_pixel_rate_l >+ / (double) cur_req_per_width; >+ } >+ >+ dml_print("DML_DLG: %s: cur_req_width = %d\n", >+ __func__, >+ cur_req_width); >+ dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", >+ __func__, >+ cur_width_ub); >+ dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", >+ __func__, >+ cur_req_per_width); >+ dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", >+ __func__, >+ hactive_cur); >+ dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", >+ __func__, >+ *refcyc_per_req_delivery_pre_cur); >+ dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", >+ __func__, >+ *refcyc_per_req_delivery_cur); >+ >+ ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); >+ } >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h 2019-08-31 15:01:11.867736169 -0500 >@@ -0,0 +1,74 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef __DML20V2_DISPLAY_RQ_DLG_CALC_H__ >+#define __DML20V2_DISPLAY_RQ_DLG_CALC_H__ >+ >+#include "../dml_common_defs.h" >+#include "../display_rq_dlg_helpers.h" >+ >+struct display_mode_lib; >+ >+ >+// Function: dml_rq_dlg_get_rq_reg >+// Main entry point for test to get the register values out of this DML class. >+// This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate >+// and then populate the rq_regs struct >+// Input: >+// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.) >+// Output: >+// rq_regs - struct that holds all the RQ registers field value. >+// See also: <display_rq_regs_st> >+void dml20v2_rq_dlg_get_rq_reg( >+ struct display_mode_lib *mode_lib, >+ display_rq_regs_st *rq_regs, >+ const display_pipe_params_st pipe_param); >+ >+ >+// Function: dml_rq_dlg_get_dlg_reg >+// Calculate and return DLG and TTU register struct given the system setting >+// Output: >+// dlg_regs - output DLG register struct >+// ttu_regs - output DLG TTU register struct >+// Input: >+// e2e_pipe_param - "compacted" array of e2e pipe param struct >+// num_pipes - num of active "pipe" or "route" >+// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg >+// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered. >+// Added for legacy or unrealistic timing tests. >+void dml20v2_rq_dlg_get_dlg_reg( >+ struct display_mode_lib *mode_lib, >+ display_dlg_regs_st *dlg_regs, >+ display_ttu_regs_st *ttu_regs, >+ display_e2e_pipe_params_st *e2e_pipe_param, >+ const unsigned int num_pipes, >+ const unsigned int pipe_idx, >+ const bool cstate_en, >+ const bool pstate_en, >+ const bool vm_en, >+ const bool ignore_viewport_pos, >+ const bool immediate_flip_support); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 2019-08-31 15:01:11.868736169 -0500 >@@ -0,0 +1,6123 @@ >+/* >+ * Copyright 2017 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifdef CONFIG_DRM_AMD_DC_DCN2_0 >+ >+#include "../display_mode_lib.h" >+#include "../dml_inline_defs.h" >+#include "../display_mode_vba.h" >+#include "display_mode_vba_21.h" >+ >+ >+/* >+ * NOTE: >+ * This file is gcc-parsable HW gospel, coming straight from HW engineers. >+ * >+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd >+ * ways. Unless there is something clearly wrong with it the code should >+ * remain as-is as it provides us with a guarantee from HW that it is correct. >+ */ >+ >+typedef unsigned int uint; >+ >+typedef struct { >+ double DPPCLK; >+ double DISPCLK; >+ double PixelClock; >+ double DCFCLKDeepSleep; >+ unsigned int DPPPerPlane; >+ bool ScalerEnabled; >+ enum scan_direction_class SourceScan; >+ unsigned int BlockWidth256BytesY; >+ unsigned int BlockHeight256BytesY; >+ unsigned int BlockWidth256BytesC; >+ unsigned int BlockHeight256BytesC; >+ unsigned int InterlaceEnable; >+ unsigned int NumberOfCursors; >+ unsigned int VBlank; >+ unsigned int HTotal; >+} Pipe; >+ >+typedef struct { >+ bool Enable; >+ unsigned int MaxPageTableLevels; >+ unsigned int CachedPageTableLevels; >+} HostVM; >+ >+#define BPP_INVALID 0 >+#define BPP_BLENDED_PIPE 0xffffffff >+ >+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib); >+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation( >+ struct display_mode_lib *mode_lib); >+static unsigned int dscceComputeDelay( >+ unsigned int bpc, >+ double bpp, >+ unsigned int sliceWidth, >+ unsigned int numSlices, >+ enum output_format_class pixelFormat); >+static unsigned int dscComputeDelay(enum output_format_class pixelFormat); >+// Super monster function with some 45 argument >+static bool CalculatePrefetchSchedule( >+ struct display_mode_lib *mode_lib, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ Pipe *myPipe, >+ unsigned int DSCDelay, >+ double DPPCLKDelaySubtotal, >+ double DPPCLKDelaySCL, >+ double DPPCLKDelaySCLLBOnly, >+ double DPPCLKDelayCNVCFormater, >+ double DPPCLKDelayCNVCCursor, >+ double DISPCLKDelaySubtotal, >+ unsigned int ScalerRecoutWidth, >+ enum output_format_class OutputFormat, >+ unsigned int MaxInterDCNTileRepeaters, >+ unsigned int VStartup, >+ unsigned int MaxVStartup, >+ unsigned int GPUVMPageTableLevels, >+ bool GPUVMEnable, >+ HostVM *myHostVM, >+ bool DynamicMetadataEnable, >+ int DynamicMetadataLinesBeforeActiveRequired, >+ unsigned int DynamicMetadataTransmittedBytes, >+ bool DCCEnable, >+ double UrgentLatency, >+ double UrgentExtraLatency, >+ double TCalc, >+ unsigned int PDEAndMetaPTEBytesFrame, >+ unsigned int MetaRowByte, >+ unsigned int PixelPTEBytesPerRow, >+ double PrefetchSourceLinesY, >+ unsigned int SwathWidthY, >+ double BytePerPixelDETY, >+ double VInitPreFillY, >+ unsigned int MaxNumSwathY, >+ double PrefetchSourceLinesC, >+ double BytePerPixelDETC, >+ double VInitPreFillC, >+ unsigned int MaxNumSwathC, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ double TWait, >+ bool XFCEnabled, >+ double XFCRemoteSurfaceFlipDelay, >+ bool ProgressiveToInterlaceUnitInOPP, >+ double *DSTXAfterScaler, >+ double *DSTYAfterScaler, >+ double *DestinationLinesForPrefetch, >+ double *PrefetchBandwidth, >+ double *DestinationLinesToRequestVMInVBlank, >+ double *DestinationLinesToRequestRowInVBlank, >+ double *VRatioPrefetchY, >+ double *VRatioPrefetchC, >+ double *RequiredPrefetchPixDataBWLuma, >+ double *RequiredPrefetchPixDataBWChroma, >+ unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata, >+ double *Tno_bw, >+ double *prefetch_vmrow_bw, >+ unsigned int *swath_width_luma_ub, >+ unsigned int *swath_width_chroma_ub, >+ unsigned int *VUpdateOffsetPix, >+ double *VUpdateWidthPix, >+ double *VReadyOffsetPix); >+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); >+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed); >+static double CalculateDCCConfiguration( >+ bool DCCEnabled, >+ bool DCCProgrammingAssumesScanDirectionUnknown, >+ unsigned int ViewportWidth, >+ unsigned int ViewportHeight, >+ double DETBufferSize, >+ unsigned int RequestHeight256Byte, >+ unsigned int SwathHeight, >+ enum dm_swizzle_mode TilingFormat, >+ unsigned int BytePerPixel, >+ enum scan_direction_class ScanOrientation, >+ unsigned int *MaxUncompressedBlock, >+ unsigned int *MaxCompressedBlock, >+ unsigned int *Independent64ByteBlock); >+static double CalculatePrefetchSourceLines( >+ struct display_mode_lib *mode_lib, >+ double VRatio, >+ double vtaps, >+ bool Interlace, >+ bool ProgressiveToInterlaceUnitInOPP, >+ unsigned int SwathHeight, >+ unsigned int ViewportYStart, >+ double *VInitPreFill, >+ unsigned int *MaxNumSwath); >+static unsigned int CalculateVMAndRowBytes( >+ struct display_mode_lib *mode_lib, >+ bool DCCEnable, >+ unsigned int BlockHeight256Bytes, >+ unsigned int BlockWidth256Bytes, >+ enum source_format_class SourcePixelFormat, >+ unsigned int SurfaceTiling, >+ unsigned int BytePerPixel, >+ enum scan_direction_class ScanDirection, >+ unsigned int ViewportWidth, >+ unsigned int ViewportHeight, >+ unsigned int SwathWidthY, >+ bool GPUVMEnable, >+ bool HostVMEnable, >+ unsigned int HostVMMaxPageTableLevels, >+ unsigned int HostVMCachedPageTableLevels, >+ unsigned int VMMPageSize, >+ unsigned int PTEBufferSizeInRequests, >+ unsigned int Pitch, >+ unsigned int DCCMetaPitch, >+ unsigned int *MacroTileWidth, >+ unsigned int *MetaRowByte, >+ unsigned int *PixelPTEBytesPerRow, >+ bool *PTEBufferSizeNotExceeded, >+ unsigned int *dpte_row_width_ub, >+ unsigned int *dpte_row_height, >+ unsigned int *MetaRequestWidth, >+ unsigned int *MetaRequestHeight, >+ unsigned int *meta_row_width, >+ unsigned int *meta_row_height, >+ unsigned int *vm_group_bytes, >+ long *dpte_group_bytes, >+ unsigned int *PixelPTEReqWidth, >+ unsigned int *PixelPTEReqHeight, >+ unsigned int *PTERequestSize, >+ unsigned int *DPDE0BytesFrame, >+ unsigned int *MetaPTEBytesFrame); >+ >+static double CalculateTWait( >+ unsigned int PrefetchMode, >+ double DRAMClockChangeLatency, >+ double UrgentLatency, >+ double SREnterPlusExitTime); >+static double CalculateRemoteSurfaceFlipDelay( >+ struct display_mode_lib *mode_lib, >+ double VRatio, >+ double SwathWidth, >+ double Bpp, >+ double LineTime, >+ double XFCTSlvVupdateOffset, >+ double XFCTSlvVupdateWidth, >+ double XFCTSlvVreadyOffset, >+ double XFCXBUFLatencyTolerance, >+ double XFCFillBWOverhead, >+ double XFCSlvChunkSize, >+ double XFCBusTransportTime, >+ double TCalc, >+ double TWait, >+ double *SrcActiveDrainRate, >+ double *TInitXFill, >+ double *TslvChk); >+static void CalculateActiveRowBandwidth( >+ bool GPUVMEnable, >+ enum source_format_class SourcePixelFormat, >+ double VRatio, >+ bool DCCEnable, >+ double LineTime, >+ unsigned int MetaRowByteLuma, >+ unsigned int MetaRowByteChroma, >+ unsigned int meta_row_height_luma, >+ unsigned int meta_row_height_chroma, >+ unsigned int PixelPTEBytesPerRowLuma, >+ unsigned int PixelPTEBytesPerRowChroma, >+ unsigned int dpte_row_height_luma, >+ unsigned int dpte_row_height_chroma, >+ double *meta_row_bw, >+ double *dpte_row_bw); >+static void CalculateFlipSchedule( >+ struct display_mode_lib *mode_lib, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ double UrgentExtraLatency, >+ double UrgentLatency, >+ unsigned int GPUVMMaxPageTableLevels, >+ bool HostVMEnable, >+ unsigned int HostVMMaxPageTableLevels, >+ unsigned int HostVMCachedPageTableLevels, >+ bool GPUVMEnable, >+ double PDEAndMetaPTEBytesPerFrame, >+ double MetaRowBytes, >+ double DPTEBytesPerRow, >+ double BandwidthAvailableForImmediateFlip, >+ unsigned int TotImmediateFlipBytes, >+ enum source_format_class SourcePixelFormat, >+ double LineTime, >+ double VRatio, >+ double Tno_bw, >+ bool DCCEnable, >+ unsigned int dpte_row_height, >+ unsigned int meta_row_height, >+ unsigned int dpte_row_height_chroma, >+ unsigned int meta_row_height_chroma, >+ double *DestinationLinesToRequestVMInImmediateFlip, >+ double *DestinationLinesToRequestRowInImmediateFlip, >+ double *final_flip_bw, >+ bool *ImmediateFlipSupportedForPipe); >+static double CalculateWriteBackDelay( >+ enum source_format_class WritebackPixelFormat, >+ double WritebackHRatio, >+ double WritebackVRatio, >+ unsigned int WritebackLumaHTaps, >+ unsigned int WritebackLumaVTaps, >+ unsigned int WritebackChromaHTaps, >+ unsigned int WritebackChromaVTaps, >+ unsigned int WritebackDestinationWidth); >+static void CalculateWatermarksAndDRAMSpeedChangeSupport( >+ struct display_mode_lib *mode_lib, >+ unsigned int PrefetchMode, >+ unsigned int NumberOfActivePlanes, >+ unsigned int MaxLineBufferLines, >+ unsigned int LineBufferSize, >+ unsigned int DPPOutputBufferPixels, >+ double DETBufferSizeInKByte, >+ unsigned int WritebackInterfaceLumaBufferSize, >+ unsigned int WritebackInterfaceChromaBufferSize, >+ double DCFCLK, >+ double UrgentOutOfOrderReturn, >+ double ReturnBW, >+ bool GPUVMEnable, >+ long dpte_group_bytes[], >+ unsigned int MetaChunkSize, >+ double UrgentLatency, >+ double ExtraLatency, >+ double WritebackLatency, >+ double WritebackChunkSize, >+ double SOCCLK, >+ double DRAMClockChangeLatency, >+ double SRExitTime, >+ double SREnterPlusExitTime, >+ double DCFCLKDeepSleep, >+ int DPPPerPlane[], >+ bool DCCEnable[], >+ double DPPCLK[], >+ unsigned int SwathWidthSingleDPPY[], >+ unsigned int SwathHeightY[], >+ double ReadBandwidthPlaneLuma[], >+ unsigned int SwathHeightC[], >+ double ReadBandwidthPlaneChroma[], >+ unsigned int LBBitPerPixel[], >+ unsigned int SwathWidthY[], >+ double HRatio[], >+ unsigned int vtaps[], >+ unsigned int VTAPsChroma[], >+ double VRatio[], >+ unsigned int HTotal[], >+ double PixelClock[], >+ unsigned int BlendingAndTiming[], >+ double BytePerPixelDETY[], >+ double BytePerPixelDETC[], >+ bool WritebackEnable[], >+ enum source_format_class WritebackPixelFormat[], >+ double WritebackDestinationWidth[], >+ double WritebackDestinationHeight[], >+ double WritebackSourceHeight[], >+ enum clock_change_support *DRAMClockChangeSupport, >+ double *UrgentWatermark, >+ double *WritebackUrgentWatermark, >+ double *DRAMClockChangeWatermark, >+ double *WritebackDRAMClockChangeWatermark, >+ double *StutterExitWatermark, >+ double *StutterEnterPlusExitWatermark, >+ double *MinActiveDRAMClockChangeLatencySupported); >+static void CalculateDCFCLKDeepSleep( >+ struct display_mode_lib *mode_lib, >+ unsigned int NumberOfActivePlanes, >+ double BytePerPixelDETY[], >+ double BytePerPixelDETC[], >+ double VRatio[], >+ unsigned int SwathWidthY[], >+ int DPPPerPlane[], >+ double HRatio[], >+ double PixelClock[], >+ double PSCL_THROUGHPUT[], >+ double PSCL_THROUGHPUT_CHROMA[], >+ double DPPCLK[], >+ double *DCFCLKDeepSleep); >+static void CalculateDETBufferSize( >+ double DETBufferSizeInKByte, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ double *DETBufferSizeY, >+ double *DETBufferSizeC); >+static void CalculateUrgentBurstFactor( >+ unsigned int DETBufferSizeInKByte, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ unsigned int SwathWidthY, >+ double LineTime, >+ double UrgentLatency, >+ double CursorBufferSize, >+ unsigned int CursorWidth, >+ unsigned int CursorBPP, >+ double VRatio, >+ double VRatioPreY, >+ double VRatioPreC, >+ double BytePerPixelInDETY, >+ double BytePerPixelInDETC, >+ double *UrgentBurstFactorCursor, >+ double *UrgentBurstFactorCursorPre, >+ double *UrgentBurstFactorLuma, >+ double *UrgentBurstFactorLumaPre, >+ double *UrgentBurstFactorChroma, >+ double *UrgentBurstFactorChromaPre, >+ unsigned int *NotEnoughUrgentLatencyHiding, >+ unsigned int *NotEnoughUrgentLatencyHidingPre); >+ >+static void CalculatePixelDeliveryTimes( >+ unsigned int NumberOfActivePlanes, >+ double VRatio[], >+ double VRatioPrefetchY[], >+ double VRatioPrefetchC[], >+ unsigned int swath_width_luma_ub[], >+ unsigned int swath_width_chroma_ub[], >+ int DPPPerPlane[], >+ double HRatio[], >+ double PixelClock[], >+ double PSCL_THROUGHPUT[], >+ double PSCL_THROUGHPUT_CHROMA[], >+ double DPPCLK[], >+ double BytePerPixelDETC[], >+ enum scan_direction_class SourceScan[], >+ unsigned int BlockWidth256BytesY[], >+ unsigned int BlockHeight256BytesY[], >+ unsigned int BlockWidth256BytesC[], >+ unsigned int BlockHeight256BytesC[], >+ double DisplayPipeLineDeliveryTimeLuma[], >+ double DisplayPipeLineDeliveryTimeChroma[], >+ double DisplayPipeLineDeliveryTimeLumaPrefetch[], >+ double DisplayPipeLineDeliveryTimeChromaPrefetch[], >+ double DisplayPipeRequestDeliveryTimeLuma[], >+ double DisplayPipeRequestDeliveryTimeChroma[], >+ double DisplayPipeRequestDeliveryTimeLumaPrefetch[], >+ double DisplayPipeRequestDeliveryTimeChromaPrefetch[]); >+ >+static void CalculateMetaAndPTETimes( >+ unsigned int NumberOfActivePlanes, >+ bool GPUVMEnable, >+ unsigned int MetaChunkSize, >+ unsigned int MinMetaChunkSizeBytes, >+ unsigned int GPUVMMaxPageTableLevels, >+ unsigned int HTotal[], >+ double VRatio[], >+ double VRatioPrefetchY[], >+ double VRatioPrefetchC[], >+ double DestinationLinesToRequestRowInVBlank[], >+ double DestinationLinesToRequestRowInImmediateFlip[], >+ double DestinationLinesToRequestVMInVBlank[], >+ double DestinationLinesToRequestVMInImmediateFlip[], >+ bool DCCEnable[], >+ double PixelClock[], >+ double BytePerPixelDETY[], >+ double BytePerPixelDETC[], >+ enum scan_direction_class SourceScan[], >+ unsigned int dpte_row_height[], >+ unsigned int dpte_row_height_chroma[], >+ unsigned int meta_row_width[], >+ unsigned int meta_row_height[], >+ unsigned int meta_req_width[], >+ unsigned int meta_req_height[], >+ long dpte_group_bytes[], >+ unsigned int PTERequestSizeY[], >+ unsigned int PTERequestSizeC[], >+ unsigned int PixelPTEReqWidthY[], >+ unsigned int PixelPTEReqHeightY[], >+ unsigned int PixelPTEReqWidthC[], >+ unsigned int PixelPTEReqHeightC[], >+ unsigned int dpte_row_width_luma_ub[], >+ unsigned int dpte_row_width_chroma_ub[], >+ unsigned int vm_group_bytes[], >+ unsigned int dpde0_bytes_per_frame_ub_l[], >+ unsigned int dpde0_bytes_per_frame_ub_c[], >+ unsigned int meta_pte_bytes_per_frame_ub_l[], >+ unsigned int meta_pte_bytes_per_frame_ub_c[], >+ double DST_Y_PER_PTE_ROW_NOM_L[], >+ double DST_Y_PER_PTE_ROW_NOM_C[], >+ double DST_Y_PER_META_ROW_NOM_L[], >+ double TimePerMetaChunkNominal[], >+ double TimePerMetaChunkVBlank[], >+ double TimePerMetaChunkFlip[], >+ double time_per_pte_group_nom_luma[], >+ double time_per_pte_group_vblank_luma[], >+ double time_per_pte_group_flip_luma[], >+ double time_per_pte_group_nom_chroma[], >+ double time_per_pte_group_vblank_chroma[], >+ double time_per_pte_group_flip_chroma[], >+ double TimePerVMGroupVBlank[], >+ double TimePerVMGroupFlip[], >+ double TimePerVMRequestVBlank[], >+ double TimePerVMRequestFlip[]); >+ >+static double CalculateExtraLatency( >+ double UrgentRoundTripAndOutOfOrderLatency, >+ int TotalNumberOfActiveDPP, >+ int PixelChunkSizeInKByte, >+ int TotalNumberOfDCCActiveDPP, >+ int MetaChunkSize, >+ double ReturnBW, >+ bool GPUVMEnable, >+ bool HostVMEnable, >+ int NumberOfActivePlanes, >+ int NumberOfDPP[], >+ long dpte_group_bytes[], >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ int HostVMMaxPageTableLevels, >+ int HostVMCachedPageTableLevels); >+ >+void dml21_recalculate(struct display_mode_lib *mode_lib) >+{ >+ ModeSupportAndSystemConfiguration(mode_lib); >+ PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib); >+ DisplayPipeConfiguration(mode_lib); >+ DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib); >+} >+ >+static unsigned int dscceComputeDelay( >+ unsigned int bpc, >+ double bpp, >+ unsigned int sliceWidth, >+ unsigned int numSlices, >+ enum output_format_class pixelFormat) >+{ >+ // valid bpc = source bits per component in the set of {8, 10, 12} >+ // valid bpp = increments of 1/16 of a bit >+ // min = 6/7/8 in N420/N422/444, respectively >+ // max = such that compression is 1:1 >+ //valid sliceWidth = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode) >+ //valid numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} >+ //valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420} >+ >+ // fixed value >+ unsigned int rcModelSize = 8192; >+ >+ // N422/N420 operate at 2 pixels per clock >+ unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, S, ix, wx, p, l0, a, ax, l, >+ Delay, pixels; >+ >+ if (pixelFormat == dm_n422 || pixelFormat == dm_420) >+ pixelsPerClock = 2; >+ // #all other modes operate at 1 pixel per clock >+ else >+ pixelsPerClock = 1; >+ >+ //initial transmit delay as per PPS >+ initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); >+ >+ //compute ssm delay >+ if (bpc == 8) >+ D = 81; >+ else if (bpc == 10) >+ D = 89; >+ else >+ D = 113; >+ >+ //divide by pixel per cycle to compute slice width as seen by DSC >+ w = sliceWidth / pixelsPerClock; >+ >+ //422 mode has an additional cycle of delay >+ if (pixelFormat == dm_s422) >+ S = 1; >+ else >+ S = 0; >+ >+ //main calculation for the dscce >+ ix = initalXmitDelay + 45; >+ wx = (w + 2) / 3; >+ p = 3 * wx - w; >+ l0 = ix / w; >+ a = ix + p * l0; >+ ax = (a + 2) / 3 + D + 6 + 1; >+ l = (ax + wx - 1) / wx; >+ if ((ix % w) == 0 && p != 0) >+ lstall = 1; >+ else >+ lstall = 0; >+ Delay = l * wx * (numSlices - 1) + ax + S + lstall + 22; >+ >+ //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels >+ pixels = Delay * 3 * pixelsPerClock; >+ return pixels; >+} >+ >+static unsigned int dscComputeDelay(enum output_format_class pixelFormat) >+{ >+ unsigned int Delay = 0; >+ >+ if (pixelFormat == dm_420) { >+ // sfr >+ Delay = Delay + 2; >+ // dsccif >+ Delay = Delay + 0; >+ // dscc - input deserializer >+ Delay = Delay + 3; >+ // dscc gets pixels every other cycle >+ Delay = Delay + 2; >+ // dscc - input cdc fifo >+ Delay = Delay + 12; >+ // dscc gets pixels every other cycle >+ Delay = Delay + 13; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output cdc fifo >+ Delay = Delay + 7; >+ // dscc gets pixels every other cycle >+ Delay = Delay + 3; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output serializer >+ Delay = Delay + 1; >+ // sft >+ Delay = Delay + 1; >+ } else if (pixelFormat == dm_n422) { >+ // sfr >+ Delay = Delay + 2; >+ // dsccif >+ Delay = Delay + 1; >+ // dscc - input deserializer >+ Delay = Delay + 5; >+ // dscc - input cdc fifo >+ Delay = Delay + 25; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output cdc fifo >+ Delay = Delay + 10; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output serializer >+ Delay = Delay + 1; >+ // sft >+ Delay = Delay + 1; >+ } else { >+ // sfr >+ Delay = Delay + 2; >+ // dsccif >+ Delay = Delay + 0; >+ // dscc - input deserializer >+ Delay = Delay + 3; >+ // dscc - input cdc fifo >+ Delay = Delay + 12; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // dscc - output cdc fifo >+ Delay = Delay + 7; >+ // dscc - output serializer >+ Delay = Delay + 1; >+ // dscc - cdc uncertainty >+ Delay = Delay + 2; >+ // sft >+ Delay = Delay + 1; >+ } >+ >+ return Delay; >+} >+ >+static bool CalculatePrefetchSchedule( >+ struct display_mode_lib *mode_lib, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ Pipe *myPipe, >+ unsigned int DSCDelay, >+ double DPPCLKDelaySubtotal, >+ double DPPCLKDelaySCL, >+ double DPPCLKDelaySCLLBOnly, >+ double DPPCLKDelayCNVCFormater, >+ double DPPCLKDelayCNVCCursor, >+ double DISPCLKDelaySubtotal, >+ unsigned int ScalerRecoutWidth, >+ enum output_format_class OutputFormat, >+ unsigned int MaxInterDCNTileRepeaters, >+ unsigned int VStartup, >+ unsigned int MaxVStartup, >+ unsigned int GPUVMPageTableLevels, >+ bool GPUVMEnable, >+ HostVM *myHostVM, >+ bool DynamicMetadataEnable, >+ int DynamicMetadataLinesBeforeActiveRequired, >+ unsigned int DynamicMetadataTransmittedBytes, >+ bool DCCEnable, >+ double UrgentLatency, >+ double UrgentExtraLatency, >+ double TCalc, >+ unsigned int PDEAndMetaPTEBytesFrame, >+ unsigned int MetaRowByte, >+ unsigned int PixelPTEBytesPerRow, >+ double PrefetchSourceLinesY, >+ unsigned int SwathWidthY, >+ double BytePerPixelDETY, >+ double VInitPreFillY, >+ unsigned int MaxNumSwathY, >+ double PrefetchSourceLinesC, >+ double BytePerPixelDETC, >+ double VInitPreFillC, >+ unsigned int MaxNumSwathC, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ double TWait, >+ bool XFCEnabled, >+ double XFCRemoteSurfaceFlipDelay, >+ bool ProgressiveToInterlaceUnitInOPP, >+ double *DSTXAfterScaler, >+ double *DSTYAfterScaler, >+ double *DestinationLinesForPrefetch, >+ double *PrefetchBandwidth, >+ double *DestinationLinesToRequestVMInVBlank, >+ double *DestinationLinesToRequestRowInVBlank, >+ double *VRatioPrefetchY, >+ double *VRatioPrefetchC, >+ double *RequiredPrefetchPixDataBWLuma, >+ double *RequiredPrefetchPixDataBWChroma, >+ unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata, >+ double *Tno_bw, >+ double *prefetch_vmrow_bw, >+ unsigned int *swath_width_luma_ub, >+ unsigned int *swath_width_chroma_ub, >+ unsigned int *VUpdateOffsetPix, >+ double *VUpdateWidthPix, >+ double *VReadyOffsetPix) >+{ >+ bool MyError = false; >+ unsigned int DPPCycles, DISPCLKCycles; >+ double DSTTotalPixelsAfterScaler, TotalRepeaterDelayTime; >+ double Tdm, LineTime, Tsetup; >+ double dst_y_prefetch_equ; >+ double Tsw_oto; >+ double prefetch_bw_oto; >+ double Tvm_oto; >+ double Tr0_oto; >+ double Tvm_oto_lines; >+ double Tr0_oto_lines; >+ double Tsw_oto_lines; >+ double dst_y_prefetch_oto; >+ double TimeForFetchingMetaPTE = 0; >+ double TimeForFetchingRowInVBlank = 0; >+ double LinesToRequestPrefetchPixelData = 0; >+ double HostVMInefficiencyFactor; >+ unsigned int HostVMDynamicLevels; >+ >+ if (GPUVMEnable == true && myHostVM->Enable == true) { >+ HostVMInefficiencyFactor = >+ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData >+ / PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; >+ HostVMDynamicLevels = myHostVM->MaxPageTableLevels >+ - myHostVM->CachedPageTableLevels; >+ } else { >+ HostVMInefficiencyFactor = 1; >+ HostVMDynamicLevels = 0; >+ } >+ >+ if (myPipe->ScalerEnabled) >+ DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL; >+ else >+ DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly; >+ >+ DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; >+ >+ DISPCLKCycles = DISPCLKDelaySubtotal; >+ >+ if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) >+ return true; >+ >+ *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK >+ + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay; >+ >+ if (myPipe->DPPPerPlane > 1) >+ *DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth; >+ >+ if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP)) >+ *DSTYAfterScaler = 1; >+ else >+ *DSTYAfterScaler = 0; >+ >+ DSTTotalPixelsAfterScaler = ((double) (*DSTYAfterScaler * myPipe->HTotal)) + *DSTXAfterScaler; >+ *DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1); >+ *DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal)); >+ >+ *VUpdateOffsetPix = dml_ceil(myPipe->HTotal / 4.0, 1); >+ TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK); >+ *VUpdateWidthPix = (14.0 / myPipe->DCFCLKDeepSleep + 12.0 / myPipe->DPPCLK + TotalRepeaterDelayTime) >+ * myPipe->PixelClock; >+ >+ *VReadyOffsetPix = dml_max( >+ 150.0 / myPipe->DPPCLK, >+ TotalRepeaterDelayTime + 20.0 / myPipe->DCFCLKDeepSleep + 10.0 / myPipe->DPPCLK) >+ * myPipe->PixelClock; >+ >+ Tsetup = (double) (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / myPipe->PixelClock; >+ >+ LineTime = (double) myPipe->HTotal / myPipe->PixelClock; >+ >+ if (DynamicMetadataEnable) { >+ double Tdmbf, Tdmec, Tdmsks; >+ >+ Tdm = dml_max(0.0, UrgentExtraLatency - TCalc); >+ Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / myPipe->DISPCLK; >+ Tdmec = LineTime; >+ if (DynamicMetadataLinesBeforeActiveRequired == -1) >+ Tdmsks = myPipe->VBlank * LineTime / 2.0; >+ else >+ Tdmsks = DynamicMetadataLinesBeforeActiveRequired * LineTime; >+ if (myPipe->InterlaceEnable && !ProgressiveToInterlaceUnitInOPP) >+ Tdmsks = Tdmsks / 2; >+ if (VStartup * LineTime >+ < Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) { >+ MyError = true; >+ *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (Tsetup + TWait >+ + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime; >+ } else >+ *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = 0.0; >+ } else >+ Tdm = 0; >+ >+ if (GPUVMEnable) { >+ if (GPUVMPageTableLevels >= 3) >+ *Tno_bw = UrgentExtraLatency + UrgentLatency * ((GPUVMPageTableLevels - 2) * (myHostVM->MaxPageTableLevels + 1) - 1); >+ else >+ *Tno_bw = 0; >+ } else if (!DCCEnable) >+ *Tno_bw = LineTime; >+ else >+ *Tno_bw = LineTime / 4; >+ >+ dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime >+ - (Tsetup + Tdm) / LineTime >+ - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal); >+ >+ Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime; >+ >+ if (myPipe->SourceScan == dm_horz) { >+ *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY; >+ *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC; >+ } else { >+ *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY; >+ *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC; >+ } >+ >+ prefetch_bw_oto = (PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) / Tsw_oto; >+ >+ >+ if (GPUVMEnable == true) { >+ Tvm_oto = dml_max(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, >+ dml_max(UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1), >+ LineTime / 4.0)); >+ } else >+ Tvm_oto = LineTime / 4.0; >+ >+ if ((GPUVMEnable == true || DCCEnable == true)) { >+ Tr0_oto = dml_max( >+ (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, >+ dml_max(UrgentLatency * (HostVMDynamicLevels + 1), dml_max(LineTime - Tvm_oto, LineTime / 4))); >+ } else >+ Tr0_oto = (LineTime - Tvm_oto) / 2.0; >+ >+ Tvm_oto_lines = dml_ceil(4 * Tvm_oto / LineTime, 1) / 4.0; >+ Tr0_oto_lines = dml_ceil(4 * Tr0_oto / LineTime, 1) / 4.0; >+ Tsw_oto_lines = dml_ceil(4 * Tsw_oto / LineTime, 1) / 4.0; >+ dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Tsw_oto_lines + 0.75; >+ >+ dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0; >+ >+ if (dst_y_prefetch_oto < dst_y_prefetch_equ) >+ *DestinationLinesForPrefetch = dst_y_prefetch_oto; >+ else >+ *DestinationLinesForPrefetch = dst_y_prefetch_equ; >+ >+ dml_print("DML: VStartup: %d\n", VStartup); >+ dml_print("DML: TCalc: %f\n", TCalc); >+ dml_print("DML: TWait: %f\n", TWait); >+ dml_print("DML: XFCRemoteSurfaceFlipDelay: %f\n", XFCRemoteSurfaceFlipDelay); >+ dml_print("DML: LineTime: %f\n", LineTime); >+ dml_print("DML: Tsetup: %f\n", Tsetup); >+ dml_print("DML: Tdm: %f\n", Tdm); >+ dml_print("DML: DSTYAfterScaler: %f\n", *DSTYAfterScaler); >+ dml_print("DML: DSTXAfterScaler: %f\n", *DSTXAfterScaler); >+ dml_print("DML: HTotal: %d\n", myPipe->HTotal); >+ >+ *PrefetchBandwidth = 0; >+ *DestinationLinesToRequestVMInVBlank = 0; >+ *DestinationLinesToRequestRowInVBlank = 0; >+ *VRatioPrefetchY = 0; >+ *VRatioPrefetchC = 0; >+ *RequiredPrefetchPixDataBWLuma = 0; >+ if (*DestinationLinesForPrefetch > 1) { >+ double PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte >+ + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor >+ + PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) >+ + PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) >+ / (*DestinationLinesForPrefetch * LineTime - *Tno_bw); >+ >+ double PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame * >+ HostVMInefficiencyFactor + PrefetchSourceLinesY * >+ *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + >+ PrefetchSourceLinesC * *swath_width_chroma_ub * >+ dml_ceil(BytePerPixelDETC, 2)) / >+ (*DestinationLinesForPrefetch * LineTime - *Tno_bw - 2 * >+ UrgentLatency * (1 + HostVMDynamicLevels)); >+ >+ double PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow >+ * HostVMInefficiencyFactor + PrefetchSourceLinesY * >+ *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + >+ PrefetchSourceLinesC * *swath_width_chroma_ub * >+ dml_ceil(BytePerPixelDETC, 2)) / >+ (*DestinationLinesForPrefetch * LineTime - >+ UrgentExtraLatency - UrgentLatency * (GPUVMPageTableLevels >+ * (HostVMDynamicLevels + 1) - 1)); >+ >+ double PrefetchBandwidth4 = (PrefetchSourceLinesY * *swath_width_luma_ub * >+ dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * >+ *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) / >+ (*DestinationLinesForPrefetch * LineTime - >+ UrgentExtraLatency - UrgentLatency * (GPUVMPageTableLevels >+ * (HostVMDynamicLevels + 1) - 1) - 2 * UrgentLatency * >+ (1 + HostVMDynamicLevels)); >+ >+ if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (*DestinationLinesForPrefetch - dml_ceil(Tsw_oto_lines, 1) / 4.0 - 0.75) * LineTime - *Tno_bw > 0) { >+ PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / ((*DestinationLinesForPrefetch - dml_ceil(Tsw_oto_lines, 1) / 4.0 - 0.75) * LineTime - *Tno_bw); >+ } >+ if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1 >= UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= UrgentLatency * (1 + HostVMDynamicLevels)) { >+ *PrefetchBandwidth = PrefetchBandwidth1; >+ } else if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2 >= UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < UrgentLatency * (1 + HostVMDynamicLevels)) { >+ *PrefetchBandwidth = PrefetchBandwidth2; >+ } else if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 < UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= UrgentLatency * (1 + HostVMDynamicLevels)) { >+ *PrefetchBandwidth = PrefetchBandwidth3; >+ } else { >+ *PrefetchBandwidth = PrefetchBandwidth4; >+ } >+ >+ if (GPUVMEnable) { >+ TimeForFetchingMetaPTE = dml_max(*Tno_bw + (double) PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / *PrefetchBandwidth, >+ dml_max(UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1), LineTime / 4)); >+ } else { >+// 5/30/2018 - This was an optimization requested from Sy but now NumberOfCursors is no longer a factor >+// so if this needs to be reinstated, then it should be officially done in the VBA code as well. >+// if (mode_lib->NumberOfCursors > 0 || XFCEnabled) >+ TimeForFetchingMetaPTE = LineTime / 4; >+// else >+// TimeForFetchingMetaPTE = 0.0; >+ } >+ >+ if ((GPUVMEnable == true || DCCEnable == true)) { >+ TimeForFetchingRowInVBlank = >+ dml_max( >+ (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) >+ / *PrefetchBandwidth, >+ dml_max( >+ UrgentLatency * (1 + HostVMDynamicLevels), >+ dml_max( >+ (LineTime >+ - TimeForFetchingMetaPTE) / 2.0, >+ LineTime >+ / 4.0))); >+ } else { >+// See note above dated 5/30/2018 >+// if (NumberOfCursors > 0 || XFCEnabled) >+ TimeForFetchingRowInVBlank = (LineTime - TimeForFetchingMetaPTE) / 2.0; >+// else // TODO: Did someone else add this?? >+// TimeForFetchingRowInVBlank = 0.0; >+ } >+ >+ *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0; >+ >+ *DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0; >+ >+ LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch >+// See note above dated 5/30/2018 >+// - ((NumberOfCursors > 0 || GPUVMEnable || DCCEnable) ? >+ - ((GPUVMEnable || DCCEnable) ? >+ (*DestinationLinesToRequestVMInVBlank + 2 * *DestinationLinesToRequestRowInVBlank) : >+ 0.0); // TODO: Did someone else add this?? >+ >+ if (LinesToRequestPrefetchPixelData > 0) { >+ >+ *VRatioPrefetchY = (double) PrefetchSourceLinesY >+ / LinesToRequestPrefetchPixelData; >+ *VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0); >+ if ((SwathHeightY > 4) && (VInitPreFillY > 3)) { >+ if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) { >+ *VRatioPrefetchY = >+ dml_max( >+ (double) PrefetchSourceLinesY >+ / LinesToRequestPrefetchPixelData, >+ (double) MaxNumSwathY >+ * SwathHeightY >+ / (LinesToRequestPrefetchPixelData >+ - (VInitPreFillY >+ - 3.0) >+ / 2.0)); >+ *VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0); >+ } else { >+ MyError = true; >+ *VRatioPrefetchY = 0; >+ } >+ } >+ >+ *VRatioPrefetchC = (double) PrefetchSourceLinesC >+ / LinesToRequestPrefetchPixelData; >+ *VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0); >+ >+ if ((SwathHeightC > 4)) { >+ if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) { >+ *VRatioPrefetchC = >+ dml_max( >+ *VRatioPrefetchC, >+ (double) MaxNumSwathC >+ * SwathHeightC >+ / (LinesToRequestPrefetchPixelData >+ - (VInitPreFillC >+ - 3.0) >+ / 2.0)); >+ *VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0); >+ } else { >+ MyError = true; >+ *VRatioPrefetchC = 0; >+ } >+ } >+ >+ *RequiredPrefetchPixDataBWLuma = myPipe->DPPPerPlane >+ * (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData >+ * dml_ceil(BytePerPixelDETY, 1) >+ * *swath_width_luma_ub / LineTime; >+ *RequiredPrefetchPixDataBWChroma = myPipe->DPPPerPlane >+ * (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData >+ * dml_ceil(BytePerPixelDETC, 2) >+ * *swath_width_chroma_ub / LineTime; >+ } else { >+ MyError = true; >+ *VRatioPrefetchY = 0; >+ *VRatioPrefetchC = 0; >+ *RequiredPrefetchPixDataBWLuma = 0; >+ *RequiredPrefetchPixDataBWChroma = 0; >+ } >+ >+ dml_print("DML: Tvm: %fus\n", TimeForFetchingMetaPTE); >+ dml_print("DML: Tr0: %fus\n", TimeForFetchingRowInVBlank); >+ dml_print("DML: Tsw: %fus\n", (double)(*DestinationLinesForPrefetch) * LineTime - TimeForFetchingMetaPTE - TimeForFetchingRowInVBlank); >+ dml_print("DML: Tpre: %fus\n", (double)(*DestinationLinesForPrefetch) * LineTime); >+ dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow); >+ >+ } else { >+ MyError = true; >+ } >+ >+ { >+ double prefetch_vm_bw; >+ double prefetch_row_bw; >+ >+ if (PDEAndMetaPTEBytesFrame == 0) { >+ prefetch_vm_bw = 0; >+ } else if (*DestinationLinesToRequestVMInVBlank > 0) { >+ prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInVBlank * LineTime); >+ } else { >+ prefetch_vm_bw = 0; >+ MyError = true; >+ } >+ if (MetaRowByte + PixelPTEBytesPerRow == 0) { >+ prefetch_row_bw = 0; >+ } else if (*DestinationLinesToRequestRowInVBlank > 0) { >+ prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInVBlank * LineTime); >+ } else { >+ prefetch_row_bw = 0; >+ MyError = true; >+ } >+ >+ *prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw); >+ } >+ >+ if (MyError) { >+ *PrefetchBandwidth = 0; >+ TimeForFetchingMetaPTE = 0; >+ TimeForFetchingRowInVBlank = 0; >+ *DestinationLinesToRequestVMInVBlank = 0; >+ *DestinationLinesToRequestRowInVBlank = 0; >+ *DestinationLinesForPrefetch = 0; >+ LinesToRequestPrefetchPixelData = 0; >+ *VRatioPrefetchY = 0; >+ *VRatioPrefetchC = 0; >+ *RequiredPrefetchPixDataBWLuma = 0; >+ *RequiredPrefetchPixDataBWChroma = 0; >+ } >+ >+ return MyError; >+} >+ >+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed) >+{ >+ return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1); >+} >+ >+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed) >+{ >+ return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1); >+} >+ >+static double CalculateDCCConfiguration( >+ bool DCCEnabled, >+ bool DCCProgrammingAssumesScanDirectionUnknown, >+ unsigned int ViewportWidth, >+ unsigned int ViewportHeight, >+ double DETBufferSize, >+ unsigned int RequestHeight256Byte, >+ unsigned int SwathHeight, >+ enum dm_swizzle_mode TilingFormat, >+ unsigned int BytePerPixel, >+ enum scan_direction_class ScanOrientation, >+ unsigned int *MaxUncompressedBlock, >+ unsigned int *MaxCompressedBlock, >+ unsigned int *Independent64ByteBlock) >+{ >+ double MaximumDCCCompressionSurface = 0.0; >+ enum { >+ REQ_256Bytes, >+ REQ_128BytesNonContiguous, >+ REQ_128BytesContiguous, >+ REQ_NA >+ } Request = REQ_NA; >+ >+ if (DCCEnabled == true) { >+ if (DCCProgrammingAssumesScanDirectionUnknown == true) { >+ if (DETBufferSize >= RequestHeight256Byte * ViewportWidth * BytePerPixel >+ && DETBufferSize >+ >= 256 / RequestHeight256Byte >+ * ViewportHeight) { >+ Request = REQ_256Bytes; >+ } else if ((DETBufferSize >+ < RequestHeight256Byte * ViewportWidth * BytePerPixel >+ && (BytePerPixel == 2 || BytePerPixel == 4)) >+ || (DETBufferSize >+ < 256 / RequestHeight256Byte >+ * ViewportHeight >+ && BytePerPixel == 8 >+ && (TilingFormat == dm_sw_4kb_d >+ || TilingFormat >+ == dm_sw_4kb_d_x >+ || TilingFormat >+ == dm_sw_var_d >+ || TilingFormat >+ == dm_sw_var_d_x >+ || TilingFormat >+ == dm_sw_64kb_d >+ || TilingFormat >+ == dm_sw_64kb_d_x >+ || TilingFormat >+ == dm_sw_64kb_d_t >+ || TilingFormat >+ == dm_sw_64kb_r_x))) { >+ Request = REQ_128BytesNonContiguous; >+ } else { >+ Request = REQ_128BytesContiguous; >+ } >+ } else { >+ if (BytePerPixel == 1) { >+ if (ScanOrientation == dm_vert || SwathHeight == 16) { >+ Request = REQ_256Bytes; >+ } else { >+ Request = REQ_128BytesContiguous; >+ } >+ } else if (BytePerPixel == 2) { >+ if ((ScanOrientation == dm_vert && SwathHeight == 16) || (ScanOrientation != dm_vert && SwathHeight == 8)) { >+ Request = REQ_256Bytes; >+ } else if (ScanOrientation == dm_vert) { >+ Request = REQ_128BytesContiguous; >+ } else { >+ Request = REQ_128BytesNonContiguous; >+ } >+ } else if (BytePerPixel == 4) { >+ if (SwathHeight == 8) { >+ Request = REQ_256Bytes; >+ } else if (ScanOrientation == dm_vert) { >+ Request = REQ_128BytesContiguous; >+ } else { >+ Request = REQ_128BytesNonContiguous; >+ } >+ } else if (BytePerPixel == 8) { >+ if (TilingFormat == dm_sw_4kb_d || TilingFormat == dm_sw_4kb_d_x >+ || TilingFormat == dm_sw_var_d >+ || TilingFormat == dm_sw_var_d_x >+ || TilingFormat == dm_sw_64kb_d >+ || TilingFormat == dm_sw_64kb_d_x >+ || TilingFormat == dm_sw_64kb_d_t >+ || TilingFormat == dm_sw_64kb_r_x) { >+ if ((ScanOrientation == dm_vert && SwathHeight == 8) >+ || (ScanOrientation != dm_vert >+ && SwathHeight == 4)) { >+ Request = REQ_256Bytes; >+ } else if (ScanOrientation != dm_vert) { >+ Request = REQ_128BytesContiguous; >+ } else { >+ Request = REQ_128BytesNonContiguous; >+ } >+ } else { >+ if (ScanOrientation != dm_vert || SwathHeight == 8) { >+ Request = REQ_256Bytes; >+ } else { >+ Request = REQ_128BytesContiguous; >+ } >+ } >+ } >+ } >+ } else { >+ Request = REQ_NA; >+ } >+ >+ if (Request == REQ_256Bytes) { >+ *MaxUncompressedBlock = 256; >+ *MaxCompressedBlock = 256; >+ *Independent64ByteBlock = false; >+ MaximumDCCCompressionSurface = 4.0; >+ } else if (Request == REQ_128BytesContiguous) { >+ *MaxUncompressedBlock = 128; >+ *MaxCompressedBlock = 128; >+ *Independent64ByteBlock = false; >+ MaximumDCCCompressionSurface = 2.0; >+ } else if (Request == REQ_128BytesNonContiguous) { >+ *MaxUncompressedBlock = 256; >+ *MaxCompressedBlock = 64; >+ *Independent64ByteBlock = true; >+ MaximumDCCCompressionSurface = 4.0; >+ } else { >+ *MaxUncompressedBlock = 0; >+ *MaxCompressedBlock = 0; >+ *Independent64ByteBlock = 0; >+ MaximumDCCCompressionSurface = 0.0; >+ } >+ >+ return MaximumDCCCompressionSurface; >+} >+ >+static double CalculatePrefetchSourceLines( >+ struct display_mode_lib *mode_lib, >+ double VRatio, >+ double vtaps, >+ bool Interlace, >+ bool ProgressiveToInterlaceUnitInOPP, >+ unsigned int SwathHeight, >+ unsigned int ViewportYStart, >+ double *VInitPreFill, >+ unsigned int *MaxNumSwath) >+{ >+ unsigned int MaxPartialSwath; >+ >+ if (ProgressiveToInterlaceUnitInOPP) >+ *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); >+ else >+ *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); >+ >+ if (!mode_lib->vba.IgnoreViewportPositioning) { >+ >+ *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; >+ >+ if (*VInitPreFill > 1.0) >+ MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; >+ else >+ MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) >+ % SwathHeight; >+ MaxPartialSwath = dml_max(1U, MaxPartialSwath); >+ >+ } else { >+ >+ if (ViewportYStart != 0) >+ dml_print( >+ "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); >+ >+ *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); >+ >+ if (*VInitPreFill > 1.0) >+ MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; >+ else >+ MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) >+ % SwathHeight; >+ } >+ >+ return *MaxNumSwath * SwathHeight + MaxPartialSwath; >+} >+ >+static unsigned int CalculateVMAndRowBytes( >+ struct display_mode_lib *mode_lib, >+ bool DCCEnable, >+ unsigned int BlockHeight256Bytes, >+ unsigned int BlockWidth256Bytes, >+ enum source_format_class SourcePixelFormat, >+ unsigned int SurfaceTiling, >+ unsigned int BytePerPixel, >+ enum scan_direction_class ScanDirection, >+ unsigned int ViewportWidth, >+ unsigned int ViewportHeight, >+ unsigned int SwathWidth, >+ bool GPUVMEnable, >+ bool HostVMEnable, >+ unsigned int HostVMMaxPageTableLevels, >+ unsigned int HostVMCachedPageTableLevels, >+ unsigned int VMMPageSize, >+ unsigned int PTEBufferSizeInRequests, >+ unsigned int Pitch, >+ unsigned int DCCMetaPitch, >+ unsigned int *MacroTileWidth, >+ unsigned int *MetaRowByte, >+ unsigned int *PixelPTEBytesPerRow, >+ bool *PTEBufferSizeNotExceeded, >+ unsigned int *dpte_row_width_ub, >+ unsigned int *dpte_row_height, >+ unsigned int *MetaRequestWidth, >+ unsigned int *MetaRequestHeight, >+ unsigned int *meta_row_width, >+ unsigned int *meta_row_height, >+ unsigned int *vm_group_bytes, >+ long *dpte_group_bytes, >+ unsigned int *PixelPTEReqWidth, >+ unsigned int *PixelPTEReqHeight, >+ unsigned int *PTERequestSize, >+ unsigned int *DPDE0BytesFrame, >+ unsigned int *MetaPTEBytesFrame) >+{ >+ unsigned int MPDEBytesFrame; >+ unsigned int DCCMetaSurfaceBytes; >+ unsigned int MacroTileSizeBytes; >+ unsigned int MacroTileHeight; >+ unsigned int ExtraDPDEBytesFrame; >+ unsigned int PDEAndMetaPTEBytesFrame; >+ unsigned int PixelPTEReqHeightPTEs; >+ >+ if (DCCEnable == true) { >+ *MetaRequestHeight = 8 * BlockHeight256Bytes; >+ *MetaRequestWidth = 8 * BlockWidth256Bytes; >+ if (ScanDirection == dm_horz) { >+ *meta_row_height = *MetaRequestHeight; >+ *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) >+ + *MetaRequestWidth; >+ *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; >+ } else { >+ *meta_row_height = *MetaRequestWidth; >+ *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) >+ + *MetaRequestHeight; >+ *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; >+ } >+ if (ScanDirection == dm_horz) { >+ DCCMetaSurfaceBytes = DCCMetaPitch >+ * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) >+ + 64 * BlockHeight256Bytes) * BytePerPixel >+ / 256; >+ } else { >+ DCCMetaSurfaceBytes = DCCMetaPitch >+ * (dml_ceil( >+ (double) ViewportHeight - 1, >+ 64 * BlockHeight256Bytes) >+ + 64 * BlockHeight256Bytes) * BytePerPixel >+ / 256; >+ } >+ if (GPUVMEnable == true) { >+ *MetaPTEBytesFrame = (dml_ceil( >+ (double) (DCCMetaSurfaceBytes - VMMPageSize) >+ / (8 * VMMPageSize), >+ 1) + 1) * 64; >+ MPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 2); >+ } else { >+ *MetaPTEBytesFrame = 0; >+ MPDEBytesFrame = 0; >+ } >+ } else { >+ *MetaPTEBytesFrame = 0; >+ MPDEBytesFrame = 0; >+ *MetaRowByte = 0; >+ } >+ >+ if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_lvp) { >+ MacroTileSizeBytes = 256; >+ MacroTileHeight = BlockHeight256Bytes; >+ } else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x >+ || SurfaceTiling == dm_sw_4kb_d || SurfaceTiling == dm_sw_4kb_d_x) { >+ MacroTileSizeBytes = 4096; >+ MacroTileHeight = 4 * BlockHeight256Bytes; >+ } else if (SurfaceTiling == dm_sw_64kb_s || SurfaceTiling == dm_sw_64kb_s_t >+ || SurfaceTiling == dm_sw_64kb_s_x || SurfaceTiling == dm_sw_64kb_d >+ || SurfaceTiling == dm_sw_64kb_d_t || SurfaceTiling == dm_sw_64kb_d_x >+ || SurfaceTiling == dm_sw_64kb_r_x) { >+ MacroTileSizeBytes = 65536; >+ MacroTileHeight = 16 * BlockHeight256Bytes; >+ } else { >+ MacroTileSizeBytes = 262144; >+ MacroTileHeight = 32 * BlockHeight256Bytes; >+ } >+ *MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight; >+ >+ if (GPUVMEnable == true && (mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) > 2) { >+ if (ScanDirection == dm_horz) { >+ *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); >+ } else { >+ *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); >+ } >+ ExtraDPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 3); >+ } else { >+ *DPDE0BytesFrame = 0; >+ ExtraDPDEBytesFrame = 0; >+ } >+ >+ PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame >+ + ExtraDPDEBytesFrame; >+ >+ if (HostVMEnable == true) { >+ PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * (HostVMMaxPageTableLevels - HostVMCachedPageTableLevels)); >+ } >+ >+ if (GPUVMEnable == true) { >+ double FractionOfPTEReturnDrop; >+ >+ if (SurfaceTiling == dm_sw_linear) { >+ PixelPTEReqHeightPTEs = 1; >+ *PixelPTEReqHeight = 1; >+ *PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel; >+ *PTERequestSize = 64; >+ FractionOfPTEReturnDrop = 0; >+ } else if (MacroTileSizeBytes == 4096) { >+ PixelPTEReqHeightPTEs = 1; >+ *PixelPTEReqHeight = MacroTileHeight; >+ *PixelPTEReqWidth = 8 * *MacroTileWidth; >+ *PTERequestSize = 64; >+ if (ScanDirection == dm_horz) >+ FractionOfPTEReturnDrop = 0; >+ else >+ FractionOfPTEReturnDrop = 7 / 8; >+ } else if (VMMPageSize == 4096 && MacroTileSizeBytes > 4096) { >+ PixelPTEReqHeightPTEs = 16; >+ *PixelPTEReqHeight = 16 * BlockHeight256Bytes; >+ *PixelPTEReqWidth = 16 * BlockWidth256Bytes; >+ *PTERequestSize = 128; >+ FractionOfPTEReturnDrop = 0; >+ } else { >+ PixelPTEReqHeightPTEs = 1; >+ *PixelPTEReqHeight = MacroTileHeight; >+ *PixelPTEReqWidth = 8 * *MacroTileWidth; >+ *PTERequestSize = 64; >+ FractionOfPTEReturnDrop = 0; >+ } >+ >+ if (SurfaceTiling == dm_sw_linear) { >+ *dpte_row_height = dml_min(128, >+ 1 << (unsigned int) dml_floor( >+ dml_log2( >+ (double) PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), >+ 1)); >+ *dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; >+ *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; >+ } else if (ScanDirection == dm_horz) { >+ *dpte_row_height = *PixelPTEReqHeight; >+ *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; >+ *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; >+ } else { >+ *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); >+ *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; >+ *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; >+ } >+ if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) >+ <= 64 * PTEBufferSizeInRequests) { >+ *PTEBufferSizeNotExceeded = true; >+ } else { >+ *PTEBufferSizeNotExceeded = false; >+ } >+ } else { >+ *PixelPTEBytesPerRow = 0; >+ *PTEBufferSizeNotExceeded = true; >+ } >+ dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %d\n", *MetaPTEBytesFrame); >+ >+ if (HostVMEnable == true) { >+ *PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * (HostVMMaxPageTableLevels - HostVMCachedPageTableLevels)); >+ } >+ >+ if (HostVMEnable == true) { >+ *vm_group_bytes = 512; >+ *dpte_group_bytes = 512; >+ } else if (GPUVMEnable == true) { >+ *vm_group_bytes = 2048; >+ if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection != dm_horz) { >+ *dpte_group_bytes = 512; >+ } else { >+ *dpte_group_bytes = 2048; >+ } >+ } else { >+ *vm_group_bytes = 0; >+ *dpte_group_bytes = 0; >+ } >+ >+ return PDEAndMetaPTEBytesFrame; >+} >+ >+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation( >+ struct display_mode_lib *mode_lib) >+{ >+ struct vba_vars_st *locals = &mode_lib->vba; >+ unsigned int j, k; >+ >+ mode_lib->vba.WritebackDISPCLK = 0.0; >+ mode_lib->vba.DISPCLKWithRamping = 0; >+ mode_lib->vba.DISPCLKWithoutRamping = 0; >+ mode_lib->vba.GlobalDPPCLK = 0.0; >+ >+ // DISPCLK and DPPCLK Calculation >+ // >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.WritebackEnable[k]) { >+ mode_lib->vba.WritebackDISPCLK = >+ dml_max( >+ mode_lib->vba.WritebackDISPCLK, >+ CalculateWriteBackDISPCLK( >+ mode_lib->vba.WritebackPixelFormat[k], >+ mode_lib->vba.PixelClock[k], >+ mode_lib->vba.WritebackHRatio[k], >+ mode_lib->vba.WritebackVRatio[k], >+ mode_lib->vba.WritebackLumaHTaps[k], >+ mode_lib->vba.WritebackLumaVTaps[k], >+ mode_lib->vba.WritebackChromaHTaps[k], >+ mode_lib->vba.WritebackChromaVTaps[k], >+ mode_lib->vba.WritebackDestinationWidth[k], >+ mode_lib->vba.HTotal[k], >+ mode_lib->vba.WritebackChromaLineBufferWidth)); >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.HRatio[k] > 1) { >+ locals->PSCL_THROUGHPUT_LUMA[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput >+ * mode_lib->vba.HRatio[k] >+ / dml_ceil( >+ mode_lib->vba.htaps[k] >+ / 6.0, >+ 1)); >+ } else { >+ locals->PSCL_THROUGHPUT_LUMA[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput); >+ } >+ >+ mode_lib->vba.DPPCLKUsingSingleDPPLuma = >+ mode_lib->vba.PixelClock[k] >+ * dml_max( >+ mode_lib->vba.vtaps[k] / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k]), >+ dml_max( >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / locals->PSCL_THROUGHPUT_LUMA[k], >+ 1.0)); >+ >+ if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6) >+ && mode_lib->vba.DPPCLKUsingSingleDPPLuma >+ < 2 * mode_lib->vba.PixelClock[k]) { >+ mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k]; >+ } >+ >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { >+ locals->PSCL_THROUGHPUT_CHROMA[k] = 0.0; >+ locals->DPPCLKUsingSingleDPP[k] = >+ mode_lib->vba.DPPCLKUsingSingleDPPLuma; >+ } else { >+ if (mode_lib->vba.HRatio[k] > 1) { >+ locals->PSCL_THROUGHPUT_CHROMA[k] = >+ dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput >+ * mode_lib->vba.HRatio[k] >+ / 2 >+ / dml_ceil( >+ mode_lib->vba.HTAPsChroma[k] >+ / 6.0, >+ 1.0)); >+ } else { >+ locals->PSCL_THROUGHPUT_CHROMA[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput); >+ } >+ mode_lib->vba.DPPCLKUsingSingleDPPChroma = >+ mode_lib->vba.PixelClock[k] >+ * dml_max( >+ mode_lib->vba.VTAPsChroma[k] >+ / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k] >+ / 2), >+ dml_max( >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / 4 >+ / locals->PSCL_THROUGHPUT_CHROMA[k], >+ 1.0)); >+ >+ if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6) >+ && mode_lib->vba.DPPCLKUsingSingleDPPChroma >+ < 2 * mode_lib->vba.PixelClock[k]) { >+ mode_lib->vba.DPPCLKUsingSingleDPPChroma = 2 >+ * mode_lib->vba.PixelClock[k]; >+ } >+ >+ locals->DPPCLKUsingSingleDPP[k] = dml_max( >+ mode_lib->vba.DPPCLKUsingSingleDPPLuma, >+ mode_lib->vba.DPPCLKUsingSingleDPPChroma); >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.BlendingAndTiming[k] != k) >+ continue; >+ if (mode_lib->vba.ODMCombineEnabled[k]) { >+ mode_lib->vba.DISPCLKWithRamping = >+ dml_max( >+ mode_lib->vba.DISPCLKWithRamping, >+ mode_lib->vba.PixelClock[k] / 2 >+ * (1 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100) >+ * (1 >+ + mode_lib->vba.DISPCLKRampingMargin >+ / 100)); >+ mode_lib->vba.DISPCLKWithoutRamping = >+ dml_max( >+ mode_lib->vba.DISPCLKWithoutRamping, >+ mode_lib->vba.PixelClock[k] / 2 >+ * (1 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100)); >+ } else if (!mode_lib->vba.ODMCombineEnabled[k]) { >+ mode_lib->vba.DISPCLKWithRamping = >+ dml_max( >+ mode_lib->vba.DISPCLKWithRamping, >+ mode_lib->vba.PixelClock[k] >+ * (1 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100) >+ * (1 >+ + mode_lib->vba.DISPCLKRampingMargin >+ / 100)); >+ mode_lib->vba.DISPCLKWithoutRamping = >+ dml_max( >+ mode_lib->vba.DISPCLKWithoutRamping, >+ mode_lib->vba.PixelClock[k] >+ * (1 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100)); >+ } >+ } >+ >+ mode_lib->vba.DISPCLKWithRamping = dml_max( >+ mode_lib->vba.DISPCLKWithRamping, >+ mode_lib->vba.WritebackDISPCLK); >+ mode_lib->vba.DISPCLKWithoutRamping = dml_max( >+ mode_lib->vba.DISPCLKWithoutRamping, >+ mode_lib->vba.WritebackDISPCLK); >+ >+ ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0); >+ mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp( >+ mode_lib->vba.DISPCLKWithRamping, >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp( >+ mode_lib->vba.DISPCLKWithoutRamping, >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ mode_lib->vba.MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown( >+ mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ if (mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity >+ > mode_lib->vba.MaxDispclkRoundedToDFSGranularity) { >+ mode_lib->vba.DISPCLK_calculated = >+ mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity; >+ } else if (mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity >+ > mode_lib->vba.MaxDispclkRoundedToDFSGranularity) { >+ mode_lib->vba.DISPCLK_calculated = mode_lib->vba.MaxDispclkRoundedToDFSGranularity; >+ } else { >+ mode_lib->vba.DISPCLK_calculated = >+ mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity; >+ } >+ DTRACE(" dispclk_mhz (calculated) = %f", mode_lib->vba.DISPCLK_calculated); >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.DPPCLK_calculated[k] = locals->DPPCLKUsingSingleDPP[k] >+ / mode_lib->vba.DPPPerPlane[k] >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100); >+ mode_lib->vba.GlobalDPPCLK = dml_max( >+ mode_lib->vba.GlobalDPPCLK, >+ mode_lib->vba.DPPCLK_calculated[k]); >+ } >+ mode_lib->vba.GlobalDPPCLK = RoundToDFSGranularityUp( >+ mode_lib->vba.GlobalDPPCLK, >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255 >+ * dml_ceil( >+ mode_lib->vba.DPPCLK_calculated[k] * 255 >+ / mode_lib->vba.GlobalDPPCLK, >+ 1); >+ DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]); >+ } >+ >+ // Urgent and B P-State/DRAM Clock Change Watermark >+ DTRACE(" dcfclk_mhz = %f", mode_lib->vba.DCFCLK); >+ DTRACE(" return_bw_to_dcn = %f", mode_lib->vba.ReturnBandwidthToDCN); >+ DTRACE(" return_bus_bw = %f", mode_lib->vba.ReturnBW); >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ bool MainPlaneDoesODMCombine = false; >+ >+ if (mode_lib->vba.SourceScan[k] == dm_horz) >+ locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k]; >+ else >+ locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k]; >+ >+ if (mode_lib->vba.ODMCombineEnabled[k] == true) >+ MainPlaneDoesODMCombine = true; >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) >+ if (mode_lib->vba.BlendingAndTiming[k] == j >+ && mode_lib->vba.ODMCombineEnabled[j] == true) >+ MainPlaneDoesODMCombine = true; >+ >+ if (MainPlaneDoesODMCombine == true) >+ locals->SwathWidthY[k] = dml_min( >+ (double) locals->SwathWidthSingleDPPY[k], >+ dml_round( >+ mode_lib->vba.HActive[k] / 2.0 >+ * mode_lib->vba.HRatio[k])); >+ else >+ locals->SwathWidthY[k] = locals->SwathWidthSingleDPPY[k] >+ / mode_lib->vba.DPPPerPlane[k]; >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { >+ locals->BytePerPixelDETY[k] = 8; >+ locals->BytePerPixelDETC[k] = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { >+ locals->BytePerPixelDETY[k] = 4; >+ locals->BytePerPixelDETC[k] = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) { >+ locals->BytePerPixelDETY[k] = 2; >+ locals->BytePerPixelDETC[k] = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) { >+ locals->BytePerPixelDETY[k] = 1; >+ locals->BytePerPixelDETC[k] = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { >+ locals->BytePerPixelDETY[k] = 1; >+ locals->BytePerPixelDETC[k] = 2; >+ } else { // dm_420_10 >+ locals->BytePerPixelDETY[k] = 4.0 / 3.0; >+ locals->BytePerPixelDETC[k] = 8.0 / 3.0; >+ } >+ } >+ >+ mode_lib->vba.TotalDataReadBandwidth = 0.0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ locals->ReadBandwidthPlaneLuma[k] = locals->SwathWidthSingleDPPY[k] >+ * dml_ceil(locals->BytePerPixelDETY[k], 1) >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) >+ * mode_lib->vba.VRatio[k]; >+ locals->ReadBandwidthPlaneChroma[k] = locals->SwathWidthSingleDPPY[k] >+ / 2 * dml_ceil(locals->BytePerPixelDETC[k], 2) >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) >+ * mode_lib->vba.VRatio[k] / 2; >+ DTRACE( >+ " read_bw[%i] = %fBps", >+ k, >+ locals->ReadBandwidthPlaneLuma[k] >+ + locals->ReadBandwidthPlaneChroma[k]); >+ mode_lib->vba.TotalDataReadBandwidth += locals->ReadBandwidthPlaneLuma[k] >+ + locals->ReadBandwidthPlaneChroma[k]; >+ } >+ >+ // DCFCLK Deep Sleep >+ CalculateDCFCLKDeepSleep( >+ mode_lib, >+ mode_lib->vba.NumberOfActivePlanes, >+ locals->BytePerPixelDETY, >+ locals->BytePerPixelDETC, >+ mode_lib->vba.VRatio, >+ locals->SwathWidthY, >+ mode_lib->vba.DPPPerPlane, >+ mode_lib->vba.HRatio, >+ mode_lib->vba.PixelClock, >+ locals->PSCL_THROUGHPUT_LUMA, >+ locals->PSCL_THROUGHPUT_CHROMA, >+ locals->DPPCLK, >+ &mode_lib->vba.DCFCLKDeepSleep); >+ >+ // DSCCLK >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { >+ locals->DSCCLK_calculated[k] = 0.0; >+ } else { >+ if (mode_lib->vba.OutputFormat[k] == dm_420 >+ || mode_lib->vba.OutputFormat[k] == dm_n422) >+ mode_lib->vba.DSCFormatFactor = 2; >+ else >+ mode_lib->vba.DSCFormatFactor = 1; >+ if (mode_lib->vba.ODMCombineEnabled[k]) >+ locals->DSCCLK_calculated[k] = >+ mode_lib->vba.PixelClockBackEnd[k] / 6 >+ / mode_lib->vba.DSCFormatFactor >+ / (1 >+ - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100); >+ else >+ locals->DSCCLK_calculated[k] = >+ mode_lib->vba.PixelClockBackEnd[k] / 3 >+ / mode_lib->vba.DSCFormatFactor >+ / (1 >+ - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100); >+ } >+ } >+ >+ // DSC Delay >+ // TODO >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ double bpp = mode_lib->vba.OutputBpp[k]; >+ unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; >+ >+ if (mode_lib->vba.DSCEnabled[k] && bpp != 0) { >+ if (!mode_lib->vba.ODMCombineEnabled[k]) { >+ locals->DSCDelay[k] = >+ dscceComputeDelay( >+ mode_lib->vba.DSCInputBitPerComponent[k], >+ bpp, >+ dml_ceil( >+ (double) mode_lib->vba.HActive[k] >+ / mode_lib->vba.NumberOfDSCSlices[k], >+ 1), >+ slices, >+ mode_lib->vba.OutputFormat[k]) >+ + dscComputeDelay( >+ mode_lib->vba.OutputFormat[k]); >+ } else { >+ locals->DSCDelay[k] = >+ 2 >+ * (dscceComputeDelay( >+ mode_lib->vba.DSCInputBitPerComponent[k], >+ bpp, >+ dml_ceil( >+ (double) mode_lib->vba.HActive[k] >+ / mode_lib->vba.NumberOfDSCSlices[k], >+ 1), >+ slices / 2.0, >+ mode_lib->vba.OutputFormat[k]) >+ + dscComputeDelay( >+ mode_lib->vba.OutputFormat[k])); >+ } >+ locals->DSCDelay[k] = locals->DSCDelay[k] >+ * mode_lib->vba.PixelClock[k] >+ / mode_lib->vba.PixelClockBackEnd[k]; >+ } else { >+ locals->DSCDelay[k] = 0; >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) // NumberOfPlanes >+ if (j != k && mode_lib->vba.BlendingAndTiming[k] == j >+ && mode_lib->vba.DSCEnabled[j]) >+ locals->DSCDelay[k] = locals->DSCDelay[j]; >+ >+ // Prefetch >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ unsigned int PDEAndMetaPTEBytesFrameY; >+ unsigned int PixelPTEBytesPerRowY; >+ unsigned int MetaRowByteY; >+ unsigned int MetaRowByteC; >+ unsigned int PDEAndMetaPTEBytesFrameC; >+ unsigned int PixelPTEBytesPerRowC; >+ bool PTEBufferSizeNotExceededY; >+ bool PTEBufferSizeNotExceededC; >+ >+ Calculate256BBlockSizes( >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(locals->BytePerPixelDETY[k], 1), >+ dml_ceil(locals->BytePerPixelDETC[k], 2), >+ &locals->BlockHeight256BytesY[k], >+ &locals->BlockHeight256BytesC[k], >+ &locals->BlockWidth256BytesY[k], >+ &locals->BlockWidth256BytesC[k]); >+ >+ locals->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.vtaps[k], >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ mode_lib->vba.SwathHeightY[k], >+ mode_lib->vba.ViewportYStartY[k], >+ &locals->VInitPreFillY[k], >+ &locals->MaxNumSwathY[k]); >+ >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) { >+ PDEAndMetaPTEBytesFrameC = >+ CalculateVMAndRowBytes( >+ mode_lib, >+ mode_lib->vba.DCCEnable[k], >+ locals->BlockHeight256BytesC[k], >+ locals->BlockWidth256BytesC[k], >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil( >+ locals->BytePerPixelDETC[k], >+ 2), >+ mode_lib->vba.SourceScan[k], >+ mode_lib->vba.ViewportWidth[k] / 2, >+ mode_lib->vba.ViewportHeight[k] / 2, >+ locals->SwathWidthY[k] / 2, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.HostVMEnable, >+ mode_lib->vba.HostVMMaxPageTableLevels, >+ mode_lib->vba.HostVMCachedPageTableLevels, >+ mode_lib->vba.VMMPageSize, >+ mode_lib->vba.PTEBufferSizeInRequestsChroma, >+ mode_lib->vba.PitchC[k], >+ mode_lib->vba.DCCMetaPitchC[k], >+ &locals->MacroTileWidthC[k], >+ &MetaRowByteC, >+ &PixelPTEBytesPerRowC, >+ &PTEBufferSizeNotExceededC, >+ &locals->dpte_row_width_chroma_ub[k], >+ &locals->dpte_row_height_chroma[k], >+ &locals->meta_req_width_chroma[k], >+ &locals->meta_req_height_chroma[k], >+ &locals->meta_row_width_chroma[k], >+ &locals->meta_row_height_chroma[k], >+ &locals->vm_group_bytes_chroma, >+ &locals->dpte_group_bytes_chroma, >+ &locals->PixelPTEReqWidthC[k], >+ &locals->PixelPTEReqHeightC[k], >+ &locals->PTERequestSizeC[k], >+ &locals->dpde0_bytes_per_frame_ub_c[k], >+ &locals->meta_pte_bytes_per_frame_ub_c[k]); >+ >+ locals->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines( >+ mode_lib, >+ mode_lib->vba.VRatio[k] / 2, >+ mode_lib->vba.VTAPsChroma[k], >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ mode_lib->vba.SwathHeightC[k], >+ mode_lib->vba.ViewportYStartC[k], >+ &locals->VInitPreFillC[k], >+ &locals->MaxNumSwathC[k]); >+ } else { >+ PixelPTEBytesPerRowC = 0; >+ PDEAndMetaPTEBytesFrameC = 0; >+ MetaRowByteC = 0; >+ locals->MaxNumSwathC[k] = 0; >+ locals->PrefetchSourceLinesC[k] = 0; >+ locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; >+ } >+ >+ PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes( >+ mode_lib, >+ mode_lib->vba.DCCEnable[k], >+ locals->BlockHeight256BytesY[k], >+ locals->BlockWidth256BytesY[k], >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(locals->BytePerPixelDETY[k], 1), >+ mode_lib->vba.SourceScan[k], >+ mode_lib->vba.ViewportWidth[k], >+ mode_lib->vba.ViewportHeight[k], >+ locals->SwathWidthY[k], >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.HostVMEnable, >+ mode_lib->vba.HostVMMaxPageTableLevels, >+ mode_lib->vba.HostVMCachedPageTableLevels, >+ mode_lib->vba.VMMPageSize, >+ locals->PTEBufferSizeInRequestsForLuma, >+ mode_lib->vba.PitchY[k], >+ mode_lib->vba.DCCMetaPitchY[k], >+ &locals->MacroTileWidthY[k], >+ &MetaRowByteY, >+ &PixelPTEBytesPerRowY, >+ &PTEBufferSizeNotExceededY, >+ &locals->dpte_row_width_luma_ub[k], >+ &locals->dpte_row_height[k], >+ &locals->meta_req_width[k], >+ &locals->meta_req_height[k], >+ &locals->meta_row_width[k], >+ &locals->meta_row_height[k], >+ &locals->vm_group_bytes[k], >+ &locals->dpte_group_bytes[k], >+ &locals->PixelPTEReqWidthY[k], >+ &locals->PixelPTEReqHeightY[k], >+ &locals->PTERequestSizeY[k], >+ &locals->dpde0_bytes_per_frame_ub_l[k], >+ &locals->meta_pte_bytes_per_frame_ub_l[k]); >+ >+ locals->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC; >+ locals->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY >+ + PDEAndMetaPTEBytesFrameC; >+ locals->MetaRowByte[k] = MetaRowByteY + MetaRowByteC; >+ >+ CalculateActiveRowBandwidth( >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ MetaRowByteY, >+ MetaRowByteC, >+ locals->meta_row_height[k], >+ locals->meta_row_height_chroma[k], >+ PixelPTEBytesPerRowY, >+ PixelPTEBytesPerRowC, >+ locals->dpte_row_height[k], >+ locals->dpte_row_height_chroma[k], >+ &locals->meta_row_bw[k], >+ &locals->dpte_row_bw[k]); >+ } >+ >+ mode_lib->vba.TotalDCCActiveDPP = 0; >+ mode_lib->vba.TotalActiveDPP = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP >+ + mode_lib->vba.DPPPerPlane[k]; >+ if (mode_lib->vba.DCCEnable[k]) >+ mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP >+ + mode_lib->vba.DPPPerPlane[k]; >+ } >+ >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannel = dml_max3( >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly); >+ >+ mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency = >+ (mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK >+ + mode_lib->vba.UrgentOutOfOrderReturnPerChannel >+ * mode_lib->vba.NumberOfChannels >+ / mode_lib->vba.ReturnBW; >+ >+ mode_lib->vba.UrgentExtraLatency = CalculateExtraLatency( >+ mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency, >+ mode_lib->vba.TotalActiveDPP, >+ mode_lib->vba.PixelChunkSizeInKByte, >+ mode_lib->vba.TotalDCCActiveDPP, >+ mode_lib->vba.MetaChunkSize, >+ mode_lib->vba.ReturnBW, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.HostVMEnable, >+ mode_lib->vba.NumberOfActivePlanes, >+ mode_lib->vba.DPPPerPlane, >+ locals->dpte_group_bytes, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ mode_lib->vba.HostVMMaxPageTableLevels, >+ mode_lib->vba.HostVMCachedPageTableLevels); >+ >+ >+ mode_lib->vba.TCalc = 24.0 / mode_lib->vba.DCFCLKDeepSleep; >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = >+ mode_lib->vba.WritebackLatency >+ + CalculateWriteBackDelay( >+ mode_lib->vba.WritebackPixelFormat[k], >+ mode_lib->vba.WritebackHRatio[k], >+ mode_lib->vba.WritebackVRatio[k], >+ mode_lib->vba.WritebackLumaHTaps[k], >+ mode_lib->vba.WritebackLumaVTaps[k], >+ mode_lib->vba.WritebackChromaHTaps[k], >+ mode_lib->vba.WritebackChromaVTaps[k], >+ mode_lib->vba.WritebackDestinationWidth[k]) >+ / mode_lib->vba.DISPCLK; >+ } else >+ locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) { >+ if (mode_lib->vba.BlendingAndTiming[j] == k >+ && mode_lib->vba.WritebackEnable[j] == true) { >+ locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = >+ dml_max( >+ locals->WritebackDelay[mode_lib->vba.VoltageLevel][k], >+ mode_lib->vba.WritebackLatency >+ + CalculateWriteBackDelay( >+ mode_lib->vba.WritebackPixelFormat[j], >+ mode_lib->vba.WritebackHRatio[j], >+ mode_lib->vba.WritebackVRatio[j], >+ mode_lib->vba.WritebackLumaHTaps[j], >+ mode_lib->vba.WritebackLumaVTaps[j], >+ mode_lib->vba.WritebackChromaHTaps[j], >+ mode_lib->vba.WritebackChromaVTaps[j], >+ mode_lib->vba.WritebackDestinationWidth[j]) >+ / mode_lib->vba.DISPCLK); >+ } >+ } >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) >+ if (mode_lib->vba.BlendingAndTiming[k] == j) >+ locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = >+ locals->WritebackDelay[mode_lib->vba.VoltageLevel][j]; >+ >+ mode_lib->vba.VStartupLines = 13; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1)); >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) >+ locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]); >+ >+ // We don't really care to iterate between the various prefetch modes >+ //mode_lib->vba.PrefetchERROR = CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &mode_lib->vba.MinPrefetchMode, &mode_lib->vba.MaxPrefetchMode); >+ mode_lib->vba.UrgentLatency = dml_max3(mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.UrgentLatencyPixelMixedWithVMData, mode_lib->vba.UrgentLatencyVMDataOnly); >+ >+ do { >+ double MaxTotalRDBandwidth = 0; >+ double MaxTotalRDBandwidthNoUrgentBurst = 0; >+ bool DestinationLineTimesForPrefetchLessThan2 = false; >+ bool VRatioPrefetchMoreThan4 = false; >+ double TWait = CalculateTWait( >+ mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], >+ mode_lib->vba.DRAMClockChangeLatency, >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.SREnterPlusExitTime); >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ Pipe myPipe; >+ HostVM myHostVM; >+ >+ if (mode_lib->vba.XFCEnabled[k] == true) { >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = >+ CalculateRemoteSurfaceFlipDelay( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ locals->SwathWidthY[k], >+ dml_ceil( >+ locals->BytePerPixelDETY[k], >+ 1), >+ mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.XFCTSlvVupdateOffset, >+ mode_lib->vba.XFCTSlvVupdateWidth, >+ mode_lib->vba.XFCTSlvVreadyOffset, >+ mode_lib->vba.XFCXBUFLatencyTolerance, >+ mode_lib->vba.XFCFillBWOverhead, >+ mode_lib->vba.XFCSlvChunkSize, >+ mode_lib->vba.XFCBusTransportTime, >+ mode_lib->vba.TCalc, >+ TWait, >+ &mode_lib->vba.SrcActiveDrainRate, >+ &mode_lib->vba.TInitXFill, >+ &mode_lib->vba.TslvChk); >+ } else { >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0; >+ } >+ >+ myPipe.DPPCLK = locals->DPPCLK[k]; >+ myPipe.DISPCLK = mode_lib->vba.DISPCLK; >+ myPipe.PixelClock = mode_lib->vba.PixelClock[k]; >+ myPipe.DCFCLKDeepSleep = mode_lib->vba.DCFCLKDeepSleep; >+ myPipe.DPPPerPlane = mode_lib->vba.DPPPerPlane[k]; >+ myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k]; >+ myPipe.SourceScan = mode_lib->vba.SourceScan[k]; >+ myPipe.BlockWidth256BytesY = locals->BlockWidth256BytesY[k]; >+ myPipe.BlockHeight256BytesY = locals->BlockHeight256BytesY[k]; >+ myPipe.BlockWidth256BytesC = locals->BlockWidth256BytesC[k]; >+ myPipe.BlockHeight256BytesC = locals->BlockHeight256BytesC[k]; >+ myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; >+ myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k]; >+ myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]; >+ myPipe.HTotal = mode_lib->vba.HTotal[k]; >+ >+ >+ myHostVM.Enable = mode_lib->vba.HostVMEnable; >+ myHostVM.MaxPageTableLevels = mode_lib->vba.HostVMMaxPageTableLevels; >+ myHostVM.CachedPageTableLevels = mode_lib->vba.HostVMCachedPageTableLevels; >+ >+ mode_lib->vba.ErrorResult[k] = >+ CalculatePrefetchSchedule( >+ mode_lib, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ &myPipe, >+ locals->DSCDelay[k], >+ mode_lib->vba.DPPCLKDelaySubtotal, >+ mode_lib->vba.DPPCLKDelaySCL, >+ mode_lib->vba.DPPCLKDelaySCLLBOnly, >+ mode_lib->vba.DPPCLKDelayCNVCFormater, >+ mode_lib->vba.DPPCLKDelayCNVCCursor, >+ mode_lib->vba.DISPCLKDelaySubtotal, >+ (unsigned int) (locals->SwathWidthY[k] >+ / mode_lib->vba.HRatio[k]), >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.MaxInterDCNTileRepeaters, >+ dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]), >+ locals->MaxVStartupLines[k], >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.GPUVMEnable, >+ &myHostVM, >+ mode_lib->vba.DynamicMetadataEnable[k], >+ mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], >+ mode_lib->vba.DynamicMetadataTransmittedBytes[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.UrgentExtraLatency, >+ mode_lib->vba.TCalc, >+ locals->PDEAndMetaPTEBytesFrame[k], >+ locals->MetaRowByte[k], >+ locals->PixelPTEBytesPerRow[k], >+ locals->PrefetchSourceLinesY[k], >+ locals->SwathWidthY[k], >+ locals->BytePerPixelDETY[k], >+ locals->VInitPreFillY[k], >+ locals->MaxNumSwathY[k], >+ locals->PrefetchSourceLinesC[k], >+ locals->BytePerPixelDETC[k], >+ locals->VInitPreFillC[k], >+ locals->MaxNumSwathC[k], >+ mode_lib->vba.SwathHeightY[k], >+ mode_lib->vba.SwathHeightC[k], >+ TWait, >+ mode_lib->vba.XFCEnabled[k], >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay, >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ &locals->DSTXAfterScaler[k], >+ &locals->DSTYAfterScaler[k], >+ &locals->DestinationLinesForPrefetch[k], >+ &locals->PrefetchBandwidth[k], >+ &locals->DestinationLinesToRequestVMInVBlank[k], >+ &locals->DestinationLinesToRequestRowInVBlank[k], >+ &locals->VRatioPrefetchY[k], >+ &locals->VRatioPrefetchC[k], >+ &locals->RequiredPrefetchPixDataBWLuma[k], >+ &locals->RequiredPrefetchPixDataBWChroma[k], >+ &locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata, >+ &locals->Tno_bw[k], >+ &locals->prefetch_vmrow_bw[k], >+ &locals->swath_width_luma_ub[k], >+ &locals->swath_width_chroma_ub[k], >+ &mode_lib->vba.VUpdateOffsetPix[k], >+ &mode_lib->vba.VUpdateWidthPix[k], >+ &mode_lib->vba.VReadyOffsetPix[k]); >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ locals->VStartup[k] = dml_min( >+ mode_lib->vba.VStartupLines, >+ locals->MaxVStartupLines[k]); >+ if (locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata >+ != 0) { >+ locals->VStartup[k] = >+ locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; >+ } >+ } else { >+ locals->VStartup[k] = >+ dml_min( >+ mode_lib->vba.VStartupLines, >+ locals->MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); >+ } >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ unsigned int m; >+ >+ locals->cursor_bw[k] = 0; >+ locals->cursor_bw_pre[k] = 0; >+ for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { >+ locals->cursor_bw[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; >+ locals->cursor_bw_pre[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPrefetchY[k]; >+ } >+ >+ CalculateUrgentBurstFactor( >+ mode_lib->vba.DETBufferSizeInKByte, >+ mode_lib->vba.SwathHeightY[k], >+ mode_lib->vba.SwathHeightC[k], >+ locals->SwathWidthY[k], >+ mode_lib->vba.HTotal[k] / >+ mode_lib->vba.PixelClock[k], >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.CursorBufferSize, >+ mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1], >+ dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), >+ mode_lib->vba.VRatio[k], >+ locals->VRatioPrefetchY[k], >+ locals->VRatioPrefetchC[k], >+ locals->BytePerPixelDETY[k], >+ locals->BytePerPixelDETC[k], >+ &locals->UrgentBurstFactorCursor[k], >+ &locals->UrgentBurstFactorCursorPre[k], >+ &locals->UrgentBurstFactorLuma[k], >+ &locals->UrgentBurstFactorLumaPre[k], >+ &locals->UrgentBurstFactorChroma[k], >+ &locals->UrgentBurstFactorChromaPre[k], >+ &locals->NotEnoughUrgentLatencyHiding, >+ &locals->NotEnoughUrgentLatencyHidingPre); >+ >+ if (mode_lib->vba.UseUrgentBurstBandwidth == false) { >+ locals->UrgentBurstFactorLuma[k] = 1; >+ locals->UrgentBurstFactorChroma[k] = 1; >+ locals->UrgentBurstFactorCursor[k] = 1; >+ locals->UrgentBurstFactorLumaPre[k] = 1; >+ locals->UrgentBurstFactorChromaPre[k] = 1; >+ locals->UrgentBurstFactorCursorPre[k] = 1; >+ } >+ >+ MaxTotalRDBandwidth = MaxTotalRDBandwidth + >+ dml_max3(locals->prefetch_vmrow_bw[k], >+ locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k] >+ + locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] >+ * locals->UrgentBurstFactorCursor[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k], >+ locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixDataBWChroma[k] >+ * locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); >+ >+ MaxTotalRDBandwidthNoUrgentBurst = MaxTotalRDBandwidthNoUrgentBurst + >+ dml_max3(locals->prefetch_vmrow_bw[k], >+ locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k] >+ + locals->meta_row_bw[k] + locals->dpte_row_bw[k], >+ locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]); >+ >+ if (locals->DestinationLinesForPrefetch[k] < 2) >+ DestinationLineTimesForPrefetchLessThan2 = true; >+ if (locals->VRatioPrefetchY[k] > 4 || locals->VRatioPrefetchC[k] > 4) >+ VRatioPrefetchMoreThan4 = true; >+ } >+ mode_lib->vba.FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / mode_lib->vba.ReturnBW; >+ >+ if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && locals->NotEnoughUrgentLatencyHiding == 0 && locals->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4 >+ && !DestinationLineTimesForPrefetchLessThan2) >+ mode_lib->vba.PrefetchModeSupported = true; >+ else { >+ mode_lib->vba.PrefetchModeSupported = false; >+ dml_print( >+ "DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid\n"); >+ } >+ >+ if (mode_lib->vba.PrefetchModeSupported == true) { >+ mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.ReturnBW; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.BandwidthAvailableForImmediateFlip = >+ mode_lib->vba.BandwidthAvailableForImmediateFlip >+ - dml_max( >+ locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k] >+ + locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k] >+ + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k], >+ locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] + >+ locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k] + >+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); >+ } >+ >+ mode_lib->vba.TotImmediateFlipBytes = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k]; >+ } >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ CalculateFlipSchedule( >+ mode_lib, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ mode_lib->vba.UrgentExtraLatency, >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.HostVMEnable, >+ mode_lib->vba.HostVMMaxPageTableLevels, >+ mode_lib->vba.HostVMCachedPageTableLevels, >+ mode_lib->vba.GPUVMEnable, >+ locals->PDEAndMetaPTEBytesFrame[k], >+ locals->MetaRowByte[k], >+ locals->PixelPTEBytesPerRow[k], >+ mode_lib->vba.BandwidthAvailableForImmediateFlip, >+ mode_lib->vba.TotImmediateFlipBytes, >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.VRatio[k], >+ locals->Tno_bw[k], >+ mode_lib->vba.DCCEnable[k], >+ locals->dpte_row_height[k], >+ locals->meta_row_height[k], >+ locals->dpte_row_height_chroma[k], >+ locals->meta_row_height_chroma[k], >+ &locals->DestinationLinesToRequestVMInImmediateFlip[k], >+ &locals->DestinationLinesToRequestRowInImmediateFlip[k], >+ &locals->final_flip_bw[k], >+ &locals->ImmediateFlipSupportedForPipe[k]); >+ } >+ mode_lib->vba.total_dcn_read_bw_with_flip = 0.0; >+ mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst = 0.0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ mode_lib->vba.total_dcn_read_bw_with_flip = >+ mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3( >+ locals->prefetch_vmrow_bw[k], >+ locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] >+ + locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k], >+ locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] >+ + locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k] >+ + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); >+ mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst = >+ mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst + >+ dml_max3(locals->prefetch_vmrow_bw[k], >+ locals->final_flip_bw[k] + locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k], >+ locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]); >+ >+ } >+ mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip = mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst / mode_lib->vba.ReturnBW; >+ >+ mode_lib->vba.ImmediateFlipSupported = true; >+ if (mode_lib->vba.total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) { >+ mode_lib->vba.ImmediateFlipSupported = false; >+ } >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (locals->ImmediateFlipSupportedForPipe[k] == false) { >+ mode_lib->vba.ImmediateFlipSupported = false; >+ } >+ } >+ } else { >+ mode_lib->vba.ImmediateFlipSupported = false; >+ } >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.ErrorResult[k]) { >+ mode_lib->vba.PrefetchModeSupported = false; >+ dml_print( >+ "DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid\n"); >+ } >+ } >+ >+ mode_lib->vba.VStartupLines = mode_lib->vba.VStartupLines + 1; >+ } while (!((mode_lib->vba.PrefetchModeSupported >+ && ((!mode_lib->vba.ImmediateFlipSupport && !mode_lib->vba.HostVMEnable) >+ || mode_lib->vba.ImmediateFlipSupported)) >+ || locals->MaximumMaxVStartupLines < mode_lib->vba.VStartupLines)); >+ >+ //Watermarks and NB P-State/DRAM Clock Change Support >+ { >+ enum clock_change_support DRAMClockChangeSupport; // dummy >+ CalculateWatermarksAndDRAMSpeedChangeSupport( >+ mode_lib, >+ mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], >+ mode_lib->vba.NumberOfActivePlanes, >+ mode_lib->vba.MaxLineBufferLines, >+ mode_lib->vba.LineBufferSize, >+ mode_lib->vba.DPPOutputBufferPixels, >+ mode_lib->vba.DETBufferSizeInKByte, >+ mode_lib->vba.WritebackInterfaceLumaBufferSize, >+ mode_lib->vba.WritebackInterfaceChromaBufferSize, >+ mode_lib->vba.DCFCLK, >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels, >+ mode_lib->vba.ReturnBW, >+ mode_lib->vba.GPUVMEnable, >+ locals->dpte_group_bytes, >+ mode_lib->vba.MetaChunkSize, >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.UrgentExtraLatency, >+ mode_lib->vba.WritebackLatency, >+ mode_lib->vba.WritebackChunkSize, >+ mode_lib->vba.SOCCLK, >+ mode_lib->vba.DRAMClockChangeLatency, >+ mode_lib->vba.SRExitTime, >+ mode_lib->vba.SREnterPlusExitTime, >+ mode_lib->vba.DCFCLKDeepSleep, >+ mode_lib->vba.DPPPerPlane, >+ mode_lib->vba.DCCEnable, >+ locals->DPPCLK, >+ locals->SwathWidthSingleDPPY, >+ mode_lib->vba.SwathHeightY, >+ locals->ReadBandwidthPlaneLuma, >+ mode_lib->vba.SwathHeightC, >+ locals->ReadBandwidthPlaneChroma, >+ mode_lib->vba.LBBitPerPixel, >+ locals->SwathWidthY, >+ mode_lib->vba.HRatio, >+ mode_lib->vba.vtaps, >+ mode_lib->vba.VTAPsChroma, >+ mode_lib->vba.VRatio, >+ mode_lib->vba.HTotal, >+ mode_lib->vba.PixelClock, >+ mode_lib->vba.BlendingAndTiming, >+ locals->BytePerPixelDETY, >+ locals->BytePerPixelDETC, >+ mode_lib->vba.WritebackEnable, >+ mode_lib->vba.WritebackPixelFormat, >+ mode_lib->vba.WritebackDestinationWidth, >+ mode_lib->vba.WritebackDestinationHeight, >+ mode_lib->vba.WritebackSourceHeight, >+ &DRAMClockChangeSupport, >+ &mode_lib->vba.UrgentWatermark, >+ &mode_lib->vba.WritebackUrgentWatermark, >+ &mode_lib->vba.DRAMClockChangeWatermark, >+ &mode_lib->vba.WritebackDRAMClockChangeWatermark, >+ &mode_lib->vba.StutterExitWatermark, >+ &mode_lib->vba.StutterEnterPlusExitWatermark, >+ &mode_lib->vba.MinActiveDRAMClockChangeLatencySupported); >+ } >+ >+ >+ //Display Pipeline Delivery Time in Prefetch, Groups >+ CalculatePixelDeliveryTimes( >+ mode_lib->vba.NumberOfActivePlanes, >+ mode_lib->vba.VRatio, >+ locals->VRatioPrefetchY, >+ locals->VRatioPrefetchC, >+ locals->swath_width_luma_ub, >+ locals->swath_width_chroma_ub, >+ mode_lib->vba.DPPPerPlane, >+ mode_lib->vba.HRatio, >+ mode_lib->vba.PixelClock, >+ locals->PSCL_THROUGHPUT_LUMA, >+ locals->PSCL_THROUGHPUT_CHROMA, >+ locals->DPPCLK, >+ locals->BytePerPixelDETC, >+ mode_lib->vba.SourceScan, >+ locals->BlockWidth256BytesY, >+ locals->BlockHeight256BytesY, >+ locals->BlockWidth256BytesC, >+ locals->BlockHeight256BytesC, >+ locals->DisplayPipeLineDeliveryTimeLuma, >+ locals->DisplayPipeLineDeliveryTimeChroma, >+ locals->DisplayPipeLineDeliveryTimeLumaPrefetch, >+ locals->DisplayPipeLineDeliveryTimeChromaPrefetch, >+ locals->DisplayPipeRequestDeliveryTimeLuma, >+ locals->DisplayPipeRequestDeliveryTimeChroma, >+ locals->DisplayPipeRequestDeliveryTimeLumaPrefetch, >+ locals->DisplayPipeRequestDeliveryTimeChromaPrefetch); >+ >+ CalculateMetaAndPTETimes( >+ mode_lib->vba.NumberOfActivePlanes, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.MetaChunkSize, >+ mode_lib->vba.MinMetaChunkSizeBytes, >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.HTotal, >+ mode_lib->vba.VRatio, >+ locals->VRatioPrefetchY, >+ locals->VRatioPrefetchC, >+ locals->DestinationLinesToRequestRowInVBlank, >+ locals->DestinationLinesToRequestRowInImmediateFlip, >+ locals->DestinationLinesToRequestVMInVBlank, >+ locals->DestinationLinesToRequestVMInImmediateFlip, >+ mode_lib->vba.DCCEnable, >+ mode_lib->vba.PixelClock, >+ locals->BytePerPixelDETY, >+ locals->BytePerPixelDETC, >+ mode_lib->vba.SourceScan, >+ locals->dpte_row_height, >+ locals->dpte_row_height_chroma, >+ locals->meta_row_width, >+ locals->meta_row_height, >+ locals->meta_req_width, >+ locals->meta_req_height, >+ locals->dpte_group_bytes, >+ locals->PTERequestSizeY, >+ locals->PTERequestSizeC, >+ locals->PixelPTEReqWidthY, >+ locals->PixelPTEReqHeightY, >+ locals->PixelPTEReqWidthC, >+ locals->PixelPTEReqHeightC, >+ locals->dpte_row_width_luma_ub, >+ locals->dpte_row_width_chroma_ub, >+ locals->vm_group_bytes, >+ locals->dpde0_bytes_per_frame_ub_l, >+ locals->dpde0_bytes_per_frame_ub_c, >+ locals->meta_pte_bytes_per_frame_ub_l, >+ locals->meta_pte_bytes_per_frame_ub_c, >+ locals->DST_Y_PER_PTE_ROW_NOM_L, >+ locals->DST_Y_PER_PTE_ROW_NOM_C, >+ locals->DST_Y_PER_META_ROW_NOM_L, >+ locals->TimePerMetaChunkNominal, >+ locals->TimePerMetaChunkVBlank, >+ locals->TimePerMetaChunkFlip, >+ locals->time_per_pte_group_nom_luma, >+ locals->time_per_pte_group_vblank_luma, >+ locals->time_per_pte_group_flip_luma, >+ locals->time_per_pte_group_nom_chroma, >+ locals->time_per_pte_group_vblank_chroma, >+ locals->time_per_pte_group_flip_chroma, >+ locals->TimePerVMGroupVBlank, >+ locals->TimePerVMGroupFlip, >+ locals->TimePerVMRequestVBlank, >+ locals->TimePerVMRequestFlip); >+ >+ >+ // Min TTUVBlank >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) { >+ locals->AllowDRAMClockChangeDuringVBlank[k] = true; >+ locals->AllowDRAMSelfRefreshDuringVBlank[k] = true; >+ locals->MinTTUVBlank[k] = dml_max( >+ mode_lib->vba.DRAMClockChangeWatermark, >+ dml_max( >+ mode_lib->vba.StutterEnterPlusExitWatermark, >+ mode_lib->vba.UrgentWatermark)); >+ } else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) { >+ locals->AllowDRAMClockChangeDuringVBlank[k] = false; >+ locals->AllowDRAMSelfRefreshDuringVBlank[k] = true; >+ locals->MinTTUVBlank[k] = dml_max( >+ mode_lib->vba.StutterEnterPlusExitWatermark, >+ mode_lib->vba.UrgentWatermark); >+ } else { >+ locals->AllowDRAMClockChangeDuringVBlank[k] = false; >+ locals->AllowDRAMSelfRefreshDuringVBlank[k] = false; >+ locals->MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark; >+ } >+ if (!mode_lib->vba.DynamicMetadataEnable[k]) >+ locals->MinTTUVBlank[k] = mode_lib->vba.TCalc >+ + locals->MinTTUVBlank[k]; >+ } >+ >+ // DCC Configuration >+ mode_lib->vba.ActiveDPPs = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ locals->MaximumDCCCompressionYSurface[k] = CalculateDCCConfiguration( >+ mode_lib->vba.DCCEnable[k], >+ false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown, >+ mode_lib->vba.ViewportWidth[k], >+ mode_lib->vba.ViewportHeight[k], >+ mode_lib->vba.DETBufferSizeInKByte * 1024, >+ locals->BlockHeight256BytesY[k], >+ mode_lib->vba.SwathHeightY[k], >+ mode_lib->vba.SurfaceTiling[k], >+ locals->BytePerPixelDETY[k], >+ mode_lib->vba.SourceScan[k], >+ &locals->DCCYMaxUncompressedBlock[k], >+ &locals->DCCYMaxCompressedBlock[k], >+ &locals->DCCYIndependent64ByteBlock[k]); >+ } >+ >+ //XFC Parameters: >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.XFCEnabled[k] == true) { >+ double TWait; >+ >+ locals->XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset; >+ locals->XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth; >+ locals->XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset; >+ TWait = CalculateTWait( >+ mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], >+ mode_lib->vba.DRAMClockChangeLatency, >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.SREnterPlusExitTime); >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = CalculateRemoteSurfaceFlipDelay( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ locals->SwathWidthY[k], >+ dml_ceil(locals->BytePerPixelDETY[k], 1), >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.XFCTSlvVupdateOffset, >+ mode_lib->vba.XFCTSlvVupdateWidth, >+ mode_lib->vba.XFCTSlvVreadyOffset, >+ mode_lib->vba.XFCXBUFLatencyTolerance, >+ mode_lib->vba.XFCFillBWOverhead, >+ mode_lib->vba.XFCSlvChunkSize, >+ mode_lib->vba.XFCBusTransportTime, >+ mode_lib->vba.TCalc, >+ TWait, >+ &mode_lib->vba.SrcActiveDrainRate, >+ &mode_lib->vba.TInitXFill, >+ &mode_lib->vba.TslvChk); >+ locals->XFCRemoteSurfaceFlipLatency[k] = >+ dml_floor( >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay >+ / (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]), >+ 1); >+ locals->XFCTransferDelay[k] = >+ dml_ceil( >+ mode_lib->vba.XFCBusTransportTime >+ / (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]), >+ 1); >+ locals->XFCPrechargeDelay[k] = >+ dml_ceil( >+ (mode_lib->vba.XFCBusTransportTime >+ + mode_lib->vba.TInitXFill >+ + mode_lib->vba.TslvChk) >+ / (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]), >+ 1); >+ mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance >+ * mode_lib->vba.SrcActiveDrainRate; >+ mode_lib->vba.FinalFillMargin = >+ (locals->DestinationLinesToRequestVMInVBlank[k] >+ + locals->DestinationLinesToRequestRowInVBlank[k]) >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k] >+ * mode_lib->vba.SrcActiveDrainRate >+ + mode_lib->vba.XFCFillConstant; >+ mode_lib->vba.FinalFillLevel = mode_lib->vba.XFCRemoteSurfaceFlipDelay >+ * mode_lib->vba.SrcActiveDrainRate >+ + mode_lib->vba.FinalFillMargin; >+ mode_lib->vba.RemainingFillLevel = dml_max( >+ 0.0, >+ mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel); >+ mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel >+ / (mode_lib->vba.SrcActiveDrainRate >+ * mode_lib->vba.XFCFillBWOverhead / 100); >+ locals->XFCPrefetchMargin[k] = >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay >+ + mode_lib->vba.TFinalxFill >+ + (locals->DestinationLinesToRequestVMInVBlank[k] >+ + locals->DestinationLinesToRequestRowInVBlank[k]) >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]; >+ } else { >+ locals->XFCSlaveVUpdateOffset[k] = 0; >+ locals->XFCSlaveVupdateWidth[k] = 0; >+ locals->XFCSlaveVReadyOffset[k] = 0; >+ locals->XFCRemoteSurfaceFlipLatency[k] = 0; >+ locals->XFCPrechargeDelay[k] = 0; >+ locals->XFCTransferDelay[k] = 0; >+ locals->XFCPrefetchMargin[k] = 0; >+ } >+ } >+ >+ // Stutter Efficiency >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ CalculateDETBufferSize( >+ mode_lib->vba.DETBufferSizeInKByte, >+ mode_lib->vba.SwathHeightY[k], >+ mode_lib->vba.SwathHeightC[k], >+ &locals->DETBufferSizeY[k], >+ &locals->DETBufferSizeC[k]); >+ >+ locals->LinesInDETY[k] = locals->DETBufferSizeY[k] >+ / locals->BytePerPixelDETY[k] / locals->SwathWidthY[k]; >+ locals->LinesInDETYRoundedDownToSwath[k] = dml_floor( >+ locals->LinesInDETY[k], >+ mode_lib->vba.SwathHeightY[k]); >+ locals->FullDETBufferingTimeY[k] = >+ locals->LinesInDETYRoundedDownToSwath[k] >+ * (mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) >+ / mode_lib->vba.VRatio[k]; >+ } >+ >+ mode_lib->vba.StutterPeriod = 999999.0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (locals->FullDETBufferingTimeY[k] < mode_lib->vba.StutterPeriod) { >+ mode_lib->vba.StutterPeriod = locals->FullDETBufferingTimeY[k]; >+ mode_lib->vba.FrameTimeForMinFullDETBufferingTime = >+ (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]; >+ locals->BytePerPixelYCriticalPlane = dml_ceil(locals->BytePerPixelDETY[k], 1); >+ locals->SwathWidthYCriticalPlane = locals->SwathWidthY[k]; >+ locals->LinesToFinishSwathTransferStutterCriticalPlane = >+ mode_lib->vba.SwathHeightY[k] - (locals->LinesInDETY[k] - locals->LinesInDETYRoundedDownToSwath[k]); >+ } >+ } >+ >+ mode_lib->vba.AverageReadBandwidth = 0.0; >+ mode_lib->vba.TotalRowReadBandwidth = 0.0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ unsigned int DCCRateLimit; >+ >+ if (mode_lib->vba.DCCEnable[k]) { >+ if (locals->DCCYMaxCompressedBlock[k] == 256) >+ DCCRateLimit = 4; >+ else >+ DCCRateLimit = 2; >+ >+ mode_lib->vba.AverageReadBandwidth = >+ mode_lib->vba.AverageReadBandwidth >+ + (locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k]) / >+ dml_min(mode_lib->vba.DCCRate[k], DCCRateLimit); >+ } else { >+ mode_lib->vba.AverageReadBandwidth = >+ mode_lib->vba.AverageReadBandwidth >+ + locals->ReadBandwidthPlaneLuma[k] >+ + locals->ReadBandwidthPlaneChroma[k]; >+ } >+ mode_lib->vba.TotalRowReadBandwidth = mode_lib->vba.TotalRowReadBandwidth + >+ locals->meta_row_bw[k] + locals->dpte_row_bw[k]; >+ } >+ >+ mode_lib->vba.AverageDCCCompressionRate = mode_lib->vba.TotalDataReadBandwidth / mode_lib->vba.AverageReadBandwidth; >+ >+ mode_lib->vba.PartOfBurstThatFitsInROB = >+ dml_min( >+ mode_lib->vba.StutterPeriod >+ * mode_lib->vba.TotalDataReadBandwidth, >+ mode_lib->vba.ROBBufferSizeInKByte * 1024 >+ * mode_lib->vba.AverageDCCCompressionRate); >+ mode_lib->vba.StutterBurstTime = mode_lib->vba.PartOfBurstThatFitsInROB >+ / mode_lib->vba.AverageDCCCompressionRate / mode_lib->vba.ReturnBW >+ + (mode_lib->vba.StutterPeriod * mode_lib->vba.TotalDataReadBandwidth >+ - mode_lib->vba.PartOfBurstThatFitsInROB) >+ / (mode_lib->vba.DCFCLK * 64) >+ + mode_lib->vba.StutterPeriod * mode_lib->vba.TotalRowReadBandwidth / mode_lib->vba.ReturnBW; >+ mode_lib->vba.StutterBurstTime = dml_max( >+ mode_lib->vba.StutterBurstTime, >+ (locals->LinesToFinishSwathTransferStutterCriticalPlane * locals->BytePerPixelYCriticalPlane * >+ locals->SwathWidthYCriticalPlane / mode_lib->vba.ReturnBW) >+ ); >+ >+ mode_lib->vba.TotalActiveWriteback = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1; >+ } >+ } >+ >+ if (mode_lib->vba.TotalActiveWriteback == 0) { >+ mode_lib->vba.StutterEfficiencyNotIncludingVBlank = (1 >+ - (mode_lib->vba.SRExitTime + mode_lib->vba.StutterBurstTime) >+ / mode_lib->vba.StutterPeriod) * 100; >+ } else { >+ mode_lib->vba.StutterEfficiencyNotIncludingVBlank = 0; >+ } >+ >+ mode_lib->vba.SmallestVBlank = 999999; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) { >+ mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k] >+ - mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]; >+ } else { >+ mode_lib->vba.VBlankTime = 0; >+ } >+ mode_lib->vba.SmallestVBlank = dml_min( >+ mode_lib->vba.SmallestVBlank, >+ mode_lib->vba.VBlankTime); >+ } >+ >+ mode_lib->vba.StutterEfficiency = (mode_lib->vba.StutterEfficiencyNotIncludingVBlank / 100 >+ * (mode_lib->vba.FrameTimeForMinFullDETBufferingTime >+ - mode_lib->vba.SmallestVBlank) >+ + mode_lib->vba.SmallestVBlank) >+ / mode_lib->vba.FrameTimeForMinFullDETBufferingTime * 100; >+} >+ >+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) >+{ >+ // Display Pipe Configuration >+ double BytePerPixDETY; >+ double BytePerPixDETC; >+ double Read256BytesBlockHeightY; >+ double Read256BytesBlockHeightC; >+ double Read256BytesBlockWidthY; >+ double Read256BytesBlockWidthC; >+ double MaximumSwathHeightY; >+ double MaximumSwathHeightC; >+ double MinimumSwathHeightY; >+ double MinimumSwathHeightC; >+ double SwathWidth; >+ double SwathWidthGranularityY; >+ double SwathWidthGranularityC; >+ double RoundedUpMaxSwathSizeBytesY; >+ double RoundedUpMaxSwathSizeBytesC; >+ unsigned int j, k; >+ >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ bool MainPlaneDoesODMCombine = false; >+ >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { >+ BytePerPixDETY = 8; >+ BytePerPixDETC = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { >+ BytePerPixDETY = 4; >+ BytePerPixDETC = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { >+ BytePerPixDETY = 2; >+ BytePerPixDETC = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) { >+ BytePerPixDETY = 1; >+ BytePerPixDETC = 0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { >+ BytePerPixDETY = 1; >+ BytePerPixDETC = 2; >+ } else { >+ BytePerPixDETY = 4.0 / 3.0; >+ BytePerPixDETC = 8.0 / 3.0; >+ } >+ >+ if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ Read256BytesBlockHeightY = 1; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { >+ Read256BytesBlockHeightY = 4; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { >+ Read256BytesBlockHeightY = 8; >+ } else { >+ Read256BytesBlockHeightY = 16; >+ } >+ Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1) >+ / Read256BytesBlockHeightY; >+ Read256BytesBlockHeightC = 0; >+ Read256BytesBlockWidthC = 0; >+ } else { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ Read256BytesBlockHeightY = 1; >+ Read256BytesBlockHeightC = 1; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { >+ Read256BytesBlockHeightY = 16; >+ Read256BytesBlockHeightC = 8; >+ } else { >+ Read256BytesBlockHeightY = 8; >+ Read256BytesBlockHeightC = 8; >+ } >+ Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1) >+ / Read256BytesBlockHeightY; >+ Read256BytesBlockWidthC = 256 / dml_ceil(BytePerPixDETC, 2) >+ / Read256BytesBlockHeightC; >+ } >+ >+ if (mode_lib->vba.SourceScan[k] == dm_horz) { >+ MaximumSwathHeightY = Read256BytesBlockHeightY; >+ MaximumSwathHeightC = Read256BytesBlockHeightC; >+ } else { >+ MaximumSwathHeightY = Read256BytesBlockWidthY; >+ MaximumSwathHeightC = Read256BytesBlockWidthC; >+ } >+ >+ if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear >+ || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ && (mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_4kb_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_4kb_s_x >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s_t >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s_x >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_var_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_var_s_x) >+ && mode_lib->vba.SourceScan[k] == dm_horz)) { >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 >+ && mode_lib->vba.SourceScan[k] != dm_horz) { >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ } else { >+ MinimumSwathHeightY = MaximumSwathHeightY / 2.0; >+ } >+ MinimumSwathHeightC = MaximumSwathHeightC; >+ } else { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ MinimumSwathHeightC = MaximumSwathHeightC; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 >+ && mode_lib->vba.SourceScan[k] == dm_horz) { >+ MinimumSwathHeightY = MaximumSwathHeightY / 2.0; >+ MinimumSwathHeightC = MaximumSwathHeightC; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 >+ && mode_lib->vba.SourceScan[k] == dm_horz) { >+ MinimumSwathHeightC = MaximumSwathHeightC / 2.0; >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ } else { >+ MinimumSwathHeightY = MaximumSwathHeightY; >+ MinimumSwathHeightC = MaximumSwathHeightC; >+ } >+ } >+ >+ if (mode_lib->vba.SourceScan[k] == dm_horz) { >+ SwathWidth = mode_lib->vba.ViewportWidth[k]; >+ } else { >+ SwathWidth = mode_lib->vba.ViewportHeight[k]; >+ } >+ >+ if (mode_lib->vba.ODMCombineEnabled[k] == true) { >+ MainPlaneDoesODMCombine = true; >+ } >+ for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) { >+ if (mode_lib->vba.BlendingAndTiming[k] == j >+ && mode_lib->vba.ODMCombineEnabled[j] == true) { >+ MainPlaneDoesODMCombine = true; >+ } >+ } >+ >+ if (MainPlaneDoesODMCombine == true) { >+ SwathWidth = dml_min( >+ SwathWidth, >+ mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]); >+ } else { >+ SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k]; >+ } >+ >+ SwathWidthGranularityY = 256 / dml_ceil(BytePerPixDETY, 1) / MaximumSwathHeightY; >+ RoundedUpMaxSwathSizeBytesY = (dml_ceil( >+ (double) (SwathWidth - 1), >+ SwathWidthGranularityY) + SwathWidthGranularityY) * BytePerPixDETY >+ * MaximumSwathHeightY; >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { >+ RoundedUpMaxSwathSizeBytesY = dml_ceil(RoundedUpMaxSwathSizeBytesY, 256) >+ + 256; >+ } >+ if (MaximumSwathHeightC > 0) { >+ SwathWidthGranularityC = 256.0 / dml_ceil(BytePerPixDETC, 2) >+ / MaximumSwathHeightC; >+ RoundedUpMaxSwathSizeBytesC = (dml_ceil( >+ (double) (SwathWidth / 2.0 - 1), >+ SwathWidthGranularityC) + SwathWidthGranularityC) >+ * BytePerPixDETC * MaximumSwathHeightC; >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { >+ RoundedUpMaxSwathSizeBytesC = dml_ceil( >+ RoundedUpMaxSwathSizeBytesC, >+ 256) + 256; >+ } >+ } else >+ RoundedUpMaxSwathSizeBytesC = 0.0; >+ >+ if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC >+ <= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) { >+ mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; >+ mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; >+ } else { >+ mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; >+ mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; >+ } >+ >+ CalculateDETBufferSize( >+ mode_lib->vba.DETBufferSizeInKByte, >+ mode_lib->vba.SwathHeightY[k], >+ mode_lib->vba.SwathHeightC[k], >+ &mode_lib->vba.DETBufferSizeY[k], >+ &mode_lib->vba.DETBufferSizeC[k]); >+ } >+} >+ >+static double CalculateTWait( >+ unsigned int PrefetchMode, >+ double DRAMClockChangeLatency, >+ double UrgentLatency, >+ double SREnterPlusExitTime) >+{ >+ if (PrefetchMode == 0) { >+ return dml_max( >+ DRAMClockChangeLatency + UrgentLatency, >+ dml_max(SREnterPlusExitTime, UrgentLatency)); >+ } else if (PrefetchMode == 1) { >+ return dml_max(SREnterPlusExitTime, UrgentLatency); >+ } else { >+ return UrgentLatency; >+ } >+} >+ >+static double CalculateRemoteSurfaceFlipDelay( >+ struct display_mode_lib *mode_lib, >+ double VRatio, >+ double SwathWidth, >+ double Bpp, >+ double LineTime, >+ double XFCTSlvVupdateOffset, >+ double XFCTSlvVupdateWidth, >+ double XFCTSlvVreadyOffset, >+ double XFCXBUFLatencyTolerance, >+ double XFCFillBWOverhead, >+ double XFCSlvChunkSize, >+ double XFCBusTransportTime, >+ double TCalc, >+ double TWait, >+ double *SrcActiveDrainRate, >+ double *TInitXFill, >+ double *TslvChk) >+{ >+ double TSlvSetup, AvgfillRate, result; >+ >+ *SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime; >+ TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth + XFCTSlvVreadyOffset; >+ *TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100); >+ AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100); >+ *TslvChk = XFCSlvChunkSize / AvgfillRate; >+ dml_print( >+ "DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f\n", >+ *SrcActiveDrainRate); >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n", TSlvSetup); >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n", *TInitXFill); >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n", AvgfillRate); >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n", *TslvChk); >+ result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk + *TInitXFill; // TODO: This doesn't seem to match programming guide >+ dml_print("DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f\n", result); >+ return result; >+} >+ >+static double CalculateWriteBackDelay( >+ enum source_format_class WritebackPixelFormat, >+ double WritebackHRatio, >+ double WritebackVRatio, >+ unsigned int WritebackLumaHTaps, >+ unsigned int WritebackLumaVTaps, >+ unsigned int WritebackChromaHTaps, >+ unsigned int WritebackChromaVTaps, >+ unsigned int WritebackDestinationWidth) >+{ >+ double CalculateWriteBackDelay = >+ dml_max( >+ dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio, >+ WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) >+ * dml_ceil( >+ WritebackDestinationWidth >+ / 4.0, >+ 1) >+ + dml_ceil(1.0 / WritebackVRatio, 1) >+ * (dml_ceil( >+ WritebackLumaVTaps >+ / 4.0, >+ 1) + 4)); >+ >+ if (WritebackPixelFormat != dm_444_32) { >+ CalculateWriteBackDelay = >+ dml_max( >+ CalculateWriteBackDelay, >+ dml_max( >+ dml_ceil( >+ WritebackChromaHTaps >+ / 2.0, >+ 1) >+ / (2 >+ * WritebackHRatio), >+ WritebackChromaVTaps >+ * dml_ceil( >+ 1 >+ / (2 >+ * WritebackVRatio), >+ 1) >+ * dml_ceil( >+ WritebackDestinationWidth >+ / 2.0 >+ / 2.0, >+ 1) >+ + dml_ceil( >+ 1 >+ / (2 >+ * WritebackVRatio), >+ 1) >+ * (dml_ceil( >+ WritebackChromaVTaps >+ / 4.0, >+ 1) >+ + 4))); >+ } >+ return CalculateWriteBackDelay; >+} >+ >+static void CalculateActiveRowBandwidth( >+ bool GPUVMEnable, >+ enum source_format_class SourcePixelFormat, >+ double VRatio, >+ bool DCCEnable, >+ double LineTime, >+ unsigned int MetaRowByteLuma, >+ unsigned int MetaRowByteChroma, >+ unsigned int meta_row_height_luma, >+ unsigned int meta_row_height_chroma, >+ unsigned int PixelPTEBytesPerRowLuma, >+ unsigned int PixelPTEBytesPerRowChroma, >+ unsigned int dpte_row_height_luma, >+ unsigned int dpte_row_height_chroma, >+ double *meta_row_bw, >+ double *dpte_row_bw) >+{ >+ if (DCCEnable != true) { >+ *meta_row_bw = 0; >+ } else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) { >+ *meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime) >+ + VRatio / 2 * MetaRowByteChroma >+ / (meta_row_height_chroma * LineTime); >+ } else { >+ *meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime); >+ } >+ >+ if (GPUVMEnable != true) { >+ *dpte_row_bw = 0; >+ } else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) { >+ *dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime) >+ + VRatio / 2 * PixelPTEBytesPerRowChroma >+ / (dpte_row_height_chroma * LineTime); >+ } else { >+ *dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime); >+ } >+} >+ >+static void CalculateFlipSchedule( >+ struct display_mode_lib *mode_lib, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ double UrgentExtraLatency, >+ double UrgentLatency, >+ unsigned int GPUVMMaxPageTableLevels, >+ bool HostVMEnable, >+ unsigned int HostVMMaxPageTableLevels, >+ unsigned int HostVMCachedPageTableLevels, >+ bool GPUVMEnable, >+ double PDEAndMetaPTEBytesPerFrame, >+ double MetaRowBytes, >+ double DPTEBytesPerRow, >+ double BandwidthAvailableForImmediateFlip, >+ unsigned int TotImmediateFlipBytes, >+ enum source_format_class SourcePixelFormat, >+ double LineTime, >+ double VRatio, >+ double Tno_bw, >+ bool DCCEnable, >+ unsigned int dpte_row_height, >+ unsigned int meta_row_height, >+ unsigned int dpte_row_height_chroma, >+ unsigned int meta_row_height_chroma, >+ double *DestinationLinesToRequestVMInImmediateFlip, >+ double *DestinationLinesToRequestRowInImmediateFlip, >+ double *final_flip_bw, >+ bool *ImmediateFlipSupportedForPipe) >+{ >+ double min_row_time = 0.0; >+ unsigned int HostVMDynamicLevels; >+ double TimeForFetchingMetaPTEImmediateFlip; >+ double TimeForFetchingRowInVBlankImmediateFlip; >+ double ImmediateFlipBW; >+ double HostVMInefficiencyFactor; >+ >+ if (GPUVMEnable == true && HostVMEnable == true) { >+ HostVMInefficiencyFactor = >+ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData >+ / PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; >+ HostVMDynamicLevels = HostVMMaxPageTableLevels - HostVMCachedPageTableLevels; >+ } else { >+ HostVMInefficiencyFactor = 1; >+ HostVMDynamicLevels = 0; >+ } >+ >+ ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) >+ * BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes; >+ >+ if (GPUVMEnable == true) { >+ TimeForFetchingMetaPTEImmediateFlip = dml_max3( >+ Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW, >+ UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevels + 1) - 1), >+ LineTime / 4.0); >+ } else { >+ TimeForFetchingMetaPTEImmediateFlip = 0; >+ } >+ >+ *DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0; >+ if ((GPUVMEnable == true || DCCEnable == true)) { >+ TimeForFetchingRowInVBlankImmediateFlip = dml_max3((MetaRowBytes + DPTEBytesPerRow) * HostVMInefficiencyFactor / ImmediateFlipBW, UrgentLatency * (HostVMDynamicLevels + 1), LineTime / 4); >+ } else { >+ TimeForFetchingRowInVBlankImmediateFlip = 0; >+ } >+ >+ *DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0; >+ *final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime), (MetaRowBytes + DPTEBytesPerRow) * HostVMInefficiencyFactor / (*DestinationLinesToRequestRowInImmediateFlip * LineTime)); >+ if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) { >+ if (GPUVMEnable == true && DCCEnable != true) { >+ min_row_time = dml_min( >+ dpte_row_height * LineTime / VRatio, >+ dpte_row_height_chroma * LineTime / (VRatio / 2)); >+ } else if (GPUVMEnable != true && DCCEnable == true) { >+ min_row_time = dml_min( >+ meta_row_height * LineTime / VRatio, >+ meta_row_height_chroma * LineTime / (VRatio / 2)); >+ } else { >+ min_row_time = dml_min4( >+ dpte_row_height * LineTime / VRatio, >+ meta_row_height * LineTime / VRatio, >+ dpte_row_height_chroma * LineTime / (VRatio / 2), >+ meta_row_height_chroma * LineTime / (VRatio / 2)); >+ } >+ } else { >+ if (GPUVMEnable == true && DCCEnable != true) { >+ min_row_time = dpte_row_height * LineTime / VRatio; >+ } else if (GPUVMEnable != true && DCCEnable == true) { >+ min_row_time = meta_row_height * LineTime / VRatio; >+ } else { >+ min_row_time = dml_min( >+ dpte_row_height * LineTime / VRatio, >+ meta_row_height * LineTime / VRatio); >+ } >+ } >+ >+ if (*DestinationLinesToRequestVMInImmediateFlip >= 32 >+ || *DestinationLinesToRequestRowInImmediateFlip >= 16 >+ || TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) { >+ *ImmediateFlipSupportedForPipe = false; >+ } else { >+ *ImmediateFlipSupportedForPipe = true; >+ } >+} >+ >+static unsigned int TruncToValidBPP( >+ double DecimalBPP, >+ double DesiredBPP, >+ bool DSCEnabled, >+ enum output_encoder_class Output, >+ enum output_format_class Format, >+ unsigned int DSCInputBitPerComponent) >+{ >+ if (Output == dm_hdmi) { >+ if (Format == dm_420) { >+ if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18)) >+ return 18; >+ else if (DecimalBPP >= 15 && (DesiredBPP == 0 || DesiredBPP == 15)) >+ return 15; >+ else if (DecimalBPP >= 12 && (DesiredBPP == 0 || DesiredBPP == 12)) >+ return 12; >+ else >+ return BPP_INVALID; >+ } else if (Format == dm_444) { >+ if (DecimalBPP >= 36 && (DesiredBPP == 0 || DesiredBPP == 36)) >+ return 36; >+ else if (DecimalBPP >= 30 && (DesiredBPP == 0 || DesiredBPP == 30)) >+ return 30; >+ else if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24)) >+ return 24; >+ else if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18)) >+ return 18; >+ else >+ return BPP_INVALID; >+ } else { >+ if (DecimalBPP / 1.5 >= 24 && (DesiredBPP == 0 || DesiredBPP == 24)) >+ return 24; >+ else if (DecimalBPP / 1.5 >= 20 && (DesiredBPP == 0 || DesiredBPP == 20)) >+ return 20; >+ else if (DecimalBPP / 1.5 >= 16 && (DesiredBPP == 0 || DesiredBPP == 16)) >+ return 16; >+ else >+ return BPP_INVALID; >+ } >+ } else { >+ if (DSCEnabled) { >+ if (Format == dm_420) { >+ if (DesiredBPP == 0) { >+ if (DecimalBPP < 6) >+ return BPP_INVALID; >+ else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16.0) >+ return 1.5 * DSCInputBitPerComponent - 1.0 / 16.0; >+ else >+ return dml_floor(16 * DecimalBPP, 1) / 16.0; >+ } else { >+ if (DecimalBPP < 6 >+ || DesiredBPP < 6 >+ || DesiredBPP > 1.5 * DSCInputBitPerComponent - 1.0 / 16.0 >+ || DecimalBPP < DesiredBPP) { >+ return BPP_INVALID; >+ } else { >+ return DesiredBPP; >+ } >+ } >+ } else if (Format == dm_n422) { >+ if (DesiredBPP == 0) { >+ if (DecimalBPP < 7) >+ return BPP_INVALID; >+ else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16.0) >+ return 2 * DSCInputBitPerComponent - 1.0 / 16.0; >+ else >+ return dml_floor(16 * DecimalBPP, 1) / 16.0; >+ } else { >+ if (DecimalBPP < 7 >+ || DesiredBPP < 7 >+ || DesiredBPP > 2 * DSCInputBitPerComponent - 1.0 / 16.0 >+ || DecimalBPP < DesiredBPP) { >+ return BPP_INVALID; >+ } else { >+ return DesiredBPP; >+ } >+ } >+ } else { >+ if (DesiredBPP == 0) { >+ if (DecimalBPP < 8) >+ return BPP_INVALID; >+ else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16.0) >+ return 3 * DSCInputBitPerComponent - 1.0 / 16.0; >+ else >+ return dml_floor(16 * DecimalBPP, 1) / 16.0; >+ } else { >+ if (DecimalBPP < 8 >+ || DesiredBPP < 8 >+ || DesiredBPP > 3 * DSCInputBitPerComponent - 1.0 / 16.0 >+ || DecimalBPP < DesiredBPP) { >+ return BPP_INVALID; >+ } else { >+ return DesiredBPP; >+ } >+ } >+ } >+ } else if (Format == dm_420) { >+ if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18)) >+ return 18; >+ else if (DecimalBPP >= 15 && (DesiredBPP == 0 || DesiredBPP == 15)) >+ return 15; >+ else if (DecimalBPP >= 12 && (DesiredBPP == 0 || DesiredBPP == 12)) >+ return 12; >+ else >+ return BPP_INVALID; >+ } else if (Format == dm_s422 || Format == dm_n422) { >+ if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24)) >+ return 24; >+ else if (DecimalBPP >= 20 && (DesiredBPP == 0 || DesiredBPP == 20)) >+ return 20; >+ else if (DecimalBPP >= 16 && (DesiredBPP == 0 || DesiredBPP == 16)) >+ return 16; >+ else >+ return BPP_INVALID; >+ } else { >+ if (DecimalBPP >= 36 && (DesiredBPP == 0 || DesiredBPP == 36)) >+ return 36; >+ else if (DecimalBPP >= 30 && (DesiredBPP == 0 || DesiredBPP == 30)) >+ return 30; >+ else if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24)) >+ return 24; >+ else >+ return BPP_INVALID; >+ } >+ } >+} >+ >+void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) >+{ >+ struct vba_vars_st *locals = &mode_lib->vba; >+ >+ int i; >+ unsigned int j, k, m; >+ >+ /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ >+ >+ /*Scale Ratio, taps Support Check*/ >+ >+ mode_lib->vba.ScaleRatioAndTapsSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.ScalerEnabled[k] == false >+ && ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) >+ || mode_lib->vba.HRatio[k] != 1.0 >+ || mode_lib->vba.htaps[k] != 1.0 >+ || mode_lib->vba.VRatio[k] != 1.0 >+ || mode_lib->vba.vtaps[k] != 1.0)) { >+ mode_lib->vba.ScaleRatioAndTapsSupport = false; >+ } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 >+ || mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0 >+ || (mode_lib->vba.htaps[k] > 1.0 >+ && (mode_lib->vba.htaps[k] % 2) == 1) >+ || mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio >+ || mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio >+ || mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k] >+ || mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k] >+ || (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8 >+ && (mode_lib->vba.HRatio[k] / 2.0 >+ > mode_lib->vba.HTAPsChroma[k] >+ || mode_lib->vba.VRatio[k] / 2.0 >+ > mode_lib->vba.VTAPsChroma[k]))) { >+ mode_lib->vba.ScaleRatioAndTapsSupport = false; >+ } >+ } >+ /*Source Format, Pixel Format and Scan Support Check*/ >+ >+ mode_lib->vba.SourceFormatPixelAndScanSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear >+ && mode_lib->vba.SourceScan[k] != dm_horz) >+ || ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d >+ || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x) >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_64) >+ || (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x >+ && (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8 >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_420_8 >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_420_10)) >+ || (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_gfx7_2d_thin_lvp) >+ && !((mode_lib->vba.SourcePixelFormat[k] >+ == dm_444_64 >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_444_32) >+ && mode_lib->vba.SourceScan[k] >+ == dm_horz >+ && mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp >+ == true >+ && mode_lib->vba.DCCEnable[k] >+ == false)) >+ || (mode_lib->vba.DCCEnable[k] == true >+ && (mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_linear >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_420_8 >+ || mode_lib->vba.SourcePixelFormat[k] >+ == dm_420_10)))) { >+ mode_lib->vba.SourceFormatPixelAndScanSupport = false; >+ } >+ } >+ /*Bandwidth Support Check*/ >+ >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { >+ locals->BytePerPixelInDETY[k] = 8.0; >+ locals->BytePerPixelInDETC[k] = 0.0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { >+ locals->BytePerPixelInDETY[k] = 4.0; >+ locals->BytePerPixelInDETC[k] = 0.0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) { >+ locals->BytePerPixelInDETY[k] = 2.0; >+ locals->BytePerPixelInDETC[k] = 0.0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) { >+ locals->BytePerPixelInDETY[k] = 1.0; >+ locals->BytePerPixelInDETC[k] = 0.0; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { >+ locals->BytePerPixelInDETY[k] = 1.0; >+ locals->BytePerPixelInDETC[k] = 2.0; >+ } else { >+ locals->BytePerPixelInDETY[k] = 4.0 / 3; >+ locals->BytePerPixelInDETC[k] = 8.0 / 3; >+ } >+ if (mode_lib->vba.SourceScan[k] == dm_horz) { >+ locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k]; >+ } else { >+ locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k]; >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0) >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; >+ locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0) >+ / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0; >+ locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k]; >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true >+ && mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { >+ locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) * 4.0; >+ } else if (mode_lib->vba.WritebackEnable[k] == true >+ && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { >+ locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) * 3.0; >+ } else if (mode_lib->vba.WritebackEnable[k] == true) { >+ locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] >+ * mode_lib->vba.WritebackDestinationHeight[k] >+ / (mode_lib->vba.WritebackSourceHeight[k] >+ * mode_lib->vba.HTotal[k] >+ / mode_lib->vba.PixelClock[k]) * 1.5; >+ } else { >+ locals->WriteBandwidth[k] = 0.0; >+ } >+ } >+ mode_lib->vba.DCCEnabledInAnyPlane = false; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.DCCEnable[k] == true) { >+ mode_lib->vba.DCCEnabledInAnyPlane = true; >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->IdealSDPPortBandwidthPerState[i] = dml_min3( >+ mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKPerState[i], >+ mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels >+ * mode_lib->vba.DRAMChannelWidth, >+ mode_lib->vba.FabricClockPerState[i] >+ * mode_lib->vba.FabricDatapathToDCNDataReturn); >+ if (mode_lib->vba.HostVMEnable == false) { >+ locals->ReturnBWPerState[i] = locals->IdealSDPPortBandwidthPerState[i] >+ * mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100.0; >+ } else { >+ locals->ReturnBWPerState[i] = locals->IdealSDPPortBandwidthPerState[i] >+ * mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0; >+ } >+ } >+ /*Writeback Latency support check*/ >+ >+ mode_lib->vba.WritebackLatencySupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { >+ if (locals->WriteBandwidth[k] >+ > (mode_lib->vba.WritebackInterfaceLumaBufferSize >+ + mode_lib->vba.WritebackInterfaceChromaBufferSize) >+ / mode_lib->vba.WritebackLatency) { >+ mode_lib->vba.WritebackLatencySupport = false; >+ } >+ } else { >+ if (locals->WriteBandwidth[k] >+ > 1.5 >+ * dml_min( >+ mode_lib->vba.WritebackInterfaceLumaBufferSize, >+ 2.0 >+ * mode_lib->vba.WritebackInterfaceChromaBufferSize) >+ / mode_lib->vba.WritebackLatency) { >+ mode_lib->vba.WritebackLatencySupport = false; >+ } >+ } >+ } >+ } >+ /*Re-ordering Buffer Support Check*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i] = >+ (mode_lib->vba.RoundTripPingLatencyCycles + 32.0) / mode_lib->vba.DCFCLKPerState[i] >+ + dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly) >+ * mode_lib->vba.NumberOfChannels / locals->ReturnBWPerState[i]; >+ if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024.0 / locals->ReturnBWPerState[i] >+ > locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i]) { >+ locals->ROBSupport[i] = true; >+ } else { >+ locals->ROBSupport[i] = false; >+ } >+ } >+ /*Writeback Mode Support Check*/ >+ >+ mode_lib->vba.TotalNumberOfActiveWriteback = 0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0) >+ mode_lib->vba.ActiveWritebacksPerPlane[k] = 1; >+ mode_lib->vba.TotalNumberOfActiveWriteback = >+ mode_lib->vba.TotalNumberOfActiveWriteback >+ + mode_lib->vba.ActiveWritebacksPerPlane[k]; >+ } >+ } >+ mode_lib->vba.WritebackModeSupport = true; >+ if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback) { >+ mode_lib->vba.WritebackModeSupport = false; >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true >+ && mode_lib->vba.Writeback10bpc420Supported != true >+ && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { >+ mode_lib->vba.WritebackModeSupport = false; >+ } >+ } >+ /*Writeback Scale Ratio and Taps Support Check*/ >+ >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false >+ && (mode_lib->vba.WritebackHRatio[k] != 1.0 >+ || mode_lib->vba.WritebackVRatio[k] != 1.0)) { >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; >+ } >+ if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio >+ || mode_lib->vba.WritebackVRatio[k] >+ > mode_lib->vba.WritebackMaxVSCLRatio >+ || mode_lib->vba.WritebackHRatio[k] >+ < mode_lib->vba.WritebackMinHSCLRatio >+ || mode_lib->vba.WritebackVRatio[k] >+ < mode_lib->vba.WritebackMinVSCLRatio >+ || mode_lib->vba.WritebackLumaHTaps[k] >+ > mode_lib->vba.WritebackMaxHSCLTaps >+ || mode_lib->vba.WritebackLumaVTaps[k] >+ > mode_lib->vba.WritebackMaxVSCLTaps >+ || mode_lib->vba.WritebackHRatio[k] >+ > mode_lib->vba.WritebackLumaHTaps[k] >+ || mode_lib->vba.WritebackVRatio[k] >+ > mode_lib->vba.WritebackLumaVTaps[k] >+ || (mode_lib->vba.WritebackLumaHTaps[k] > 2.0 >+ && ((mode_lib->vba.WritebackLumaHTaps[k] % 2) >+ == 1)) >+ || (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32 >+ && (mode_lib->vba.WritebackChromaHTaps[k] >+ > mode_lib->vba.WritebackMaxHSCLTaps >+ || mode_lib->vba.WritebackChromaVTaps[k] >+ > mode_lib->vba.WritebackMaxVSCLTaps >+ || 2.0 >+ * mode_lib->vba.WritebackHRatio[k] >+ > mode_lib->vba.WritebackChromaHTaps[k] >+ || 2.0 >+ * mode_lib->vba.WritebackVRatio[k] >+ > mode_lib->vba.WritebackChromaVTaps[k] >+ || (mode_lib->vba.WritebackChromaHTaps[k] > 2.0 >+ && ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) { >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; >+ } >+ if (mode_lib->vba.WritebackVRatio[k] < 1.0) { >+ mode_lib->vba.WritebackLumaVExtra = >+ dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0); >+ } else { >+ mode_lib->vba.WritebackLumaVExtra = -1; >+ } >+ if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32 >+ && mode_lib->vba.WritebackLumaVTaps[k] >+ > (mode_lib->vba.WritebackLineBufferLumaBufferSize >+ + mode_lib->vba.WritebackLineBufferChromaBufferSize) >+ / 3.0 >+ / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackLumaVExtra) >+ || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 >+ && mode_lib->vba.WritebackLumaVTaps[k] >+ > mode_lib->vba.WritebackLineBufferLumaBufferSize >+ * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackLumaVExtra) >+ || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 >+ && mode_lib->vba.WritebackLumaVTaps[k] >+ > mode_lib->vba.WritebackLineBufferLumaBufferSize >+ * 8.0 / 10.0 >+ / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackLumaVExtra)) { >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; >+ } >+ if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) { >+ mode_lib->vba.WritebackChromaVExtra = 0.0; >+ } else { >+ mode_lib->vba.WritebackChromaVExtra = -1; >+ } >+ if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 >+ && mode_lib->vba.WritebackChromaVTaps[k] >+ > mode_lib->vba.WritebackLineBufferChromaBufferSize >+ * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackChromaVExtra) >+ || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 >+ && mode_lib->vba.WritebackChromaVTaps[k] >+ > mode_lib->vba.WritebackLineBufferChromaBufferSize >+ * 8.0 / 10.0 >+ / mode_lib->vba.WritebackDestinationWidth[k] >+ - mode_lib->vba.WritebackChromaVExtra)) { >+ mode_lib->vba.WritebackScaleRatioAndTapsSupport = false; >+ } >+ } >+ } >+ /*Maximum DISPCLK/DPPCLK Support check*/ >+ >+ mode_lib->vba.WritebackRequiredDISPCLK = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ mode_lib->vba.WritebackRequiredDISPCLK = >+ dml_max( >+ mode_lib->vba.WritebackRequiredDISPCLK, >+ CalculateWriteBackDISPCLK( >+ mode_lib->vba.WritebackPixelFormat[k], >+ mode_lib->vba.PixelClock[k], >+ mode_lib->vba.WritebackHRatio[k], >+ mode_lib->vba.WritebackVRatio[k], >+ mode_lib->vba.WritebackLumaHTaps[k], >+ mode_lib->vba.WritebackLumaVTaps[k], >+ mode_lib->vba.WritebackChromaHTaps[k], >+ mode_lib->vba.WritebackChromaVTaps[k], >+ mode_lib->vba.WritebackDestinationWidth[k], >+ mode_lib->vba.HTotal[k], >+ mode_lib->vba.WritebackChromaLineBufferWidth)); >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.HRatio[k] > 1.0) { >+ locals->PSCL_FACTOR[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput >+ * mode_lib->vba.HRatio[k] >+ / dml_ceil( >+ mode_lib->vba.htaps[k] >+ / 6.0, >+ 1.0)); >+ } else { >+ locals->PSCL_FACTOR[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput); >+ } >+ if (locals->BytePerPixelInDETC[k] == 0.0) { >+ locals->PSCL_FACTOR_CHROMA[k] = 0.0; >+ locals->MinDPPCLKUsingSingleDPP[k] = >+ mode_lib->vba.PixelClock[k] >+ * dml_max3( >+ mode_lib->vba.vtaps[k] / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k]), >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / locals->PSCL_FACTOR[k], >+ 1.0); >+ if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0) >+ && locals->MinDPPCLKUsingSingleDPP[k] >+ < 2.0 * mode_lib->vba.PixelClock[k]) { >+ locals->MinDPPCLKUsingSingleDPP[k] = 2.0 >+ * mode_lib->vba.PixelClock[k]; >+ } >+ } else { >+ if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) { >+ locals->PSCL_FACTOR_CHROMA[k] = >+ dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput >+ * mode_lib->vba.HRatio[k] >+ / 2.0 >+ / dml_ceil( >+ mode_lib->vba.HTAPsChroma[k] >+ / 6.0, >+ 1.0)); >+ } else { >+ locals->PSCL_FACTOR_CHROMA[k] = dml_min( >+ mode_lib->vba.MaxDCHUBToPSCLThroughput, >+ mode_lib->vba.MaxPSCLToLBThroughput); >+ } >+ locals->MinDPPCLKUsingSingleDPP[k] = >+ mode_lib->vba.PixelClock[k] >+ * dml_max5( >+ mode_lib->vba.vtaps[k] / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k]), >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / locals->PSCL_FACTOR[k], >+ mode_lib->vba.VTAPsChroma[k] >+ / 6.0 >+ * dml_min( >+ 1.0, >+ mode_lib->vba.HRatio[k] >+ / 2.0), >+ mode_lib->vba.HRatio[k] >+ * mode_lib->vba.VRatio[k] >+ / 4.0 >+ / locals->PSCL_FACTOR_CHROMA[k], >+ 1.0); >+ if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0 >+ || mode_lib->vba.HTAPsChroma[k] > 6.0 >+ || mode_lib->vba.VTAPsChroma[k] > 6.0) >+ && locals->MinDPPCLKUsingSingleDPP[k] >+ < 2.0 * mode_lib->vba.PixelClock[k]) { >+ locals->MinDPPCLKUsingSingleDPP[k] = 2.0 >+ * mode_lib->vba.PixelClock[k]; >+ } >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ Calculate256BBlockSizes( >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(locals->BytePerPixelInDETY[k], 1.0), >+ dml_ceil(locals->BytePerPixelInDETC[k], 2.0), >+ &locals->Read256BlockHeightY[k], >+ &locals->Read256BlockHeightC[k], >+ &locals->Read256BlockWidthY[k], >+ &locals->Read256BlockWidthC[k]); >+ if (mode_lib->vba.SourceScan[k] == dm_horz) { >+ locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k]; >+ locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k]; >+ } else { >+ locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k]; >+ locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k]; >+ } >+ if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16 >+ || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear >+ || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 >+ && (mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_4kb_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_4kb_s_x >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s_t >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_64kb_s_x >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_var_s >+ || mode_lib->vba.SurfaceTiling[k] >+ == dm_sw_var_s_x) >+ && mode_lib->vba.SourceScan[k] == dm_horz)) { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; >+ } else { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] >+ / 2.0; >+ } >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; >+ } else { >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 >+ && mode_lib->vba.SourceScan[k] == dm_horz) { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] >+ / 2.0; >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; >+ } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 >+ && mode_lib->vba.SourceScan[k] == dm_horz) { >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k] >+ / 2.0; >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; >+ } else { >+ locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; >+ locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; >+ } >+ } >+ if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { >+ mode_lib->vba.MaximumSwathWidthSupport = 8192.0; >+ } else { >+ mode_lib->vba.MaximumSwathWidthSupport = 5120.0; >+ } >+ mode_lib->vba.MaximumSwathWidthInDETBuffer = >+ dml_min( >+ mode_lib->vba.MaximumSwathWidthSupport, >+ mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0 >+ / (locals->BytePerPixelInDETY[k] >+ * locals->MinSwathHeightY[k] >+ + locals->BytePerPixelInDETC[k] >+ / 2.0 >+ * locals->MinSwathHeightC[k])); >+ if (locals->BytePerPixelInDETC[k] == 0.0) { >+ mode_lib->vba.MaximumSwathWidthInLineBuffer = >+ mode_lib->vba.LineBufferSize >+ * dml_max(mode_lib->vba.HRatio[k], 1.0) >+ / mode_lib->vba.LBBitPerPixel[k] >+ / (mode_lib->vba.vtaps[k] >+ + dml_max( >+ dml_ceil( >+ mode_lib->vba.VRatio[k], >+ 1.0) >+ - 2, >+ 0.0)); >+ } else { >+ mode_lib->vba.MaximumSwathWidthInLineBuffer = >+ dml_min( >+ mode_lib->vba.LineBufferSize >+ * dml_max( >+ mode_lib->vba.HRatio[k], >+ 1.0) >+ / mode_lib->vba.LBBitPerPixel[k] >+ / (mode_lib->vba.vtaps[k] >+ + dml_max( >+ dml_ceil( >+ mode_lib->vba.VRatio[k], >+ 1.0) >+ - 2, >+ 0.0)), >+ 2.0 * mode_lib->vba.LineBufferSize >+ * dml_max( >+ mode_lib->vba.HRatio[k] >+ / 2.0, >+ 1.0) >+ / mode_lib->vba.LBBitPerPixel[k] >+ / (mode_lib->vba.VTAPsChroma[k] >+ + dml_max( >+ dml_ceil( >+ mode_lib->vba.VRatio[k] >+ / 2.0, >+ 1.0) >+ - 2, >+ 0.0))); >+ } >+ locals->MaximumSwathWidth[k] = dml_min( >+ mode_lib->vba.MaximumSwathWidthInDETBuffer, >+ mode_lib->vba.MaximumSwathWidthInLineBuffer); >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown( >+ mode_lib->vba.MaxDispclk[i], >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown( >+ mode_lib->vba.MaxDppclk[i], >+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed); >+ locals->RequiredDISPCLK[i][j] = 0.0; >+ locals->DISPCLK_DPPCLK_Support[i][j] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = >+ mode_lib->vba.PixelClock[k] >+ * (1.0 >+ + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading >+ / 100.0) >+ * (1.0 >+ + mode_lib->vba.DISPCLKRampingMargin >+ / 100.0); >+ if (mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine >= mode_lib->vba.MaxDispclk[i] >+ && i == mode_lib->vba.soc.num_states) >+ mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k] >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ >+ mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1 + mode_lib->vba.DISPCLKRampingMargin / 100.0); >+ if (mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine >= mode_lib->vba.MaxDispclk[i] >+ && i == mode_lib->vba.soc.num_states) >+ mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) { >+ locals->ODMCombineEnablePerState[i][k] = false; >+ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine; >+ } else { >+ locals->ODMCombineEnablePerState[i][k] = true; >+ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; >+ } >+ if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity >+ && locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k] >+ && locals->ODMCombineEnablePerState[i][k] == false) { >+ locals->NoOfDPP[i][j][k] = 1; >+ locals->RequiredDPPCLK[i][j][k] = >+ locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ } else { >+ locals->NoOfDPP[i][j][k] = 2; >+ locals->RequiredDPPCLK[i][j][k] = >+ locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; >+ } >+ locals->RequiredDISPCLK[i][j] = dml_max( >+ locals->RequiredDISPCLK[i][j], >+ mode_lib->vba.PlaneRequiredDISPCLK); >+ if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) >+ > mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity) >+ || (mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) { >+ locals->DISPCLK_DPPCLK_Support[i][j] = false; >+ } >+ } >+ locals->TotalNumberOfActiveDPP[i][j] = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) >+ locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; >+ if (j == 1) { >+ while (locals->TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP >+ && locals->TotalNumberOfActiveDPP[i][j] < 2 * mode_lib->vba.NumberOfActivePlanes) { >+ double BWOfNonSplitPlaneOfMaximumBandwidth; >+ unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth; >+ >+ BWOfNonSplitPlaneOfMaximumBandwidth = 0; >+ NumberOfNonSplitPlaneOfMaximumBandwidth = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) { >+ BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k]; >+ NumberOfNonSplitPlaneOfMaximumBandwidth = k; >+ } >+ } >+ locals->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2; >+ locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = >+ locals->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth] >+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2; >+ locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + 1; >+ } >+ } >+ if (locals->TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP) { >+ locals->RequiredDISPCLK[i][j] = 0.0; >+ locals->DISPCLK_DPPCLK_Support[i][j] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->ODMCombineEnablePerState[i][k] = false; >+ if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) { >+ locals->NoOfDPP[i][j][k] = 1; >+ locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] >+ * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ } else { >+ locals->NoOfDPP[i][j][k] = 2; >+ locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] >+ * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; >+ } >+ if (i != mode_lib->vba.soc.num_states) { >+ mode_lib->vba.PlaneRequiredDISPCLK = >+ mode_lib->vba.PixelClock[k] >+ * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) >+ * (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0); >+ } else { >+ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k] >+ * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); >+ } >+ locals->RequiredDISPCLK[i][j] = dml_max( >+ locals->RequiredDISPCLK[i][j], >+ mode_lib->vba.PlaneRequiredDISPCLK); >+ if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) >+ > mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity >+ || mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) >+ locals->DISPCLK_DPPCLK_Support[i][j] = false; >+ } >+ locals->TotalNumberOfActiveDPP[i][j] = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) >+ locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; >+ } >+ locals->RequiredDISPCLK[i][j] = dml_max( >+ locals->RequiredDISPCLK[i][j], >+ mode_lib->vba.WritebackRequiredDISPCLK); >+ if (mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity >+ < mode_lib->vba.WritebackRequiredDISPCLK) { >+ locals->DISPCLK_DPPCLK_Support[i][j] = false; >+ } >+ } >+ } >+ /*Viewport Size Check*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->ViewportSizeSupport[i] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->ODMCombineEnablePerState[i][k] == true) { >+ if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])) >+ > locals->MaximumSwathWidth[k]) { >+ locals->ViewportSizeSupport[i] = false; >+ } >+ } else { >+ if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) { >+ locals->ViewportSizeSupport[i] = false; >+ } >+ } >+ } >+ } >+ /*Total Available Pipes Support Check*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ if (locals->TotalNumberOfActiveDPP[i][j] <= mode_lib->vba.MaxNumDPP) >+ locals->TotalAvailablePipesSupport[i][j] = true; >+ else >+ locals->TotalAvailablePipesSupport[i][j] = false; >+ } >+ } >+ /*Total Available OTG Support Check*/ >+ >+ mode_lib->vba.TotalNumberOfActiveOTG = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG >+ + 1.0; >+ } >+ } >+ if (mode_lib->vba.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG) { >+ mode_lib->vba.NumberOfOTGSupport = true; >+ } else { >+ mode_lib->vba.NumberOfOTGSupport = false; >+ } >+ /*Display IO and DSC Support Check*/ >+ >+ mode_lib->vba.NonsupportedDSCInputBPC = false; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0 >+ || mode_lib->vba.DSCInputBitPerComponent[k] == 10.0 >+ || mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) { >+ mode_lib->vba.NonsupportedDSCInputBPC = true; >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->RequiresDSC[i][k] = 0; >+ locals->RequiresFEC[i][k] = 0; >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ if (mode_lib->vba.Output[k] == dm_hdmi) { >+ locals->RequiresDSC[i][k] = 0; >+ locals->RequiresFEC[i][k] = 0; >+ locals->OutputBppPerState[i][k] = TruncToValidBPP( >+ dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, >+ mode_lib->vba.ForcedOutputLinkBPP[k], >+ false, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ } else if (mode_lib->vba.Output[k] == dm_dp >+ || mode_lib->vba.Output[k] == dm_edp) { >+ if (mode_lib->vba.Output[k] == dm_edp) { >+ mode_lib->vba.EffectiveFECOverhead = 0.0; >+ } else { >+ mode_lib->vba.EffectiveFECOverhead = >+ mode_lib->vba.FECOverhead; >+ } >+ if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { >+ mode_lib->vba.Outbpp = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ mode_lib->vba.ForcedOutputLinkBPP[k], >+ false, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ mode_lib->vba.OutbppDSC = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ mode_lib->vba.ForcedOutputLinkBPP[k], >+ true, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ if (mode_lib->vba.DSCEnabled[k] == true) { >+ locals->RequiresDSC[i][k] = true; >+ if (mode_lib->vba.Output[k] == dm_dp) { >+ locals->RequiresFEC[i][k] = true; >+ } else { >+ locals->RequiresFEC[i][k] = false; >+ } >+ mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC; >+ } else { >+ locals->RequiresDSC[i][k] = false; >+ locals->RequiresFEC[i][k] = false; >+ } >+ locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; >+ } >+ if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { >+ mode_lib->vba.Outbpp = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ mode_lib->vba.ForcedOutputLinkBPP[k], >+ false, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ mode_lib->vba.OutbppDSC = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ mode_lib->vba.ForcedOutputLinkBPP[k], >+ true, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ if (mode_lib->vba.DSCEnabled[k] == true) { >+ locals->RequiresDSC[i][k] = true; >+ if (mode_lib->vba.Output[k] == dm_dp) { >+ locals->RequiresFEC[i][k] = true; >+ } else { >+ locals->RequiresFEC[i][k] = false; >+ } >+ mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC; >+ } else { >+ locals->RequiresDSC[i][k] = false; >+ locals->RequiresFEC[i][k] = false; >+ } >+ locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; >+ } >+ if (mode_lib->vba.Outbpp == BPP_INVALID >+ && mode_lib->vba.PHYCLKPerState[i] >+ >= 810.0) { >+ mode_lib->vba.Outbpp = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ mode_lib->vba.ForcedOutputLinkBPP[k], >+ false, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ mode_lib->vba.OutbppDSC = TruncToValidBPP( >+ (1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0 >+ * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, >+ mode_lib->vba.ForcedOutputLinkBPP[k], >+ true, >+ mode_lib->vba.Output[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.DSCInputBitPerComponent[k]); >+ if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) { >+ locals->RequiresDSC[i][k] = true; >+ if (mode_lib->vba.Output[k] == dm_dp) { >+ locals->RequiresFEC[i][k] = true; >+ } else { >+ locals->RequiresFEC[i][k] = false; >+ } >+ mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC; >+ } else { >+ locals->RequiresDSC[i][k] = false; >+ locals->RequiresFEC[i][k] = false; >+ } >+ locals->OutputBppPerState[i][k] = >+ mode_lib->vba.Outbpp; >+ } >+ } >+ } else { >+ locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE; >+ } >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->DIOSupport[i] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->OutputBppPerState[i][k] == BPP_INVALID >+ || (mode_lib->vba.OutputFormat[k] == dm_420 >+ && mode_lib->vba.Interlace[k] == true >+ && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { >+ locals->DIOSupport[i] = false; >+ } >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->DSCCLKRequiredMoreThanSupported[i] = false; >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ if ((mode_lib->vba.Output[k] == dm_dp >+ || mode_lib->vba.Output[k] == dm_edp)) { >+ if (mode_lib->vba.OutputFormat[k] == dm_420 >+ || mode_lib->vba.OutputFormat[k] >+ == dm_n422) { >+ mode_lib->vba.DSCFormatFactor = 2; >+ } else { >+ mode_lib->vba.DSCFormatFactor = 1; >+ } >+ if (locals->RequiresDSC[i][k] == true) { >+ if (locals->ODMCombineEnablePerState[i][k] >+ == true) { >+ if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor >+ > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) { >+ locals->DSCCLKRequiredMoreThanSupported[i] = >+ true; >+ } >+ } else { >+ if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor >+ > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) { >+ locals->DSCCLKRequiredMoreThanSupported[i] = >+ true; >+ } >+ } >+ } >+ } >+ } >+ } >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ locals->NotEnoughDSCUnits[i] = false; >+ mode_lib->vba.TotalDSCUnitsRequired = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->RequiresDSC[i][k] == true) { >+ if (locals->ODMCombineEnablePerState[i][k] == true) { >+ mode_lib->vba.TotalDSCUnitsRequired = >+ mode_lib->vba.TotalDSCUnitsRequired + 2.0; >+ } else { >+ mode_lib->vba.TotalDSCUnitsRequired = >+ mode_lib->vba.TotalDSCUnitsRequired + 1.0; >+ } >+ } >+ } >+ if (mode_lib->vba.TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC) { >+ locals->NotEnoughDSCUnits[i] = true; >+ } >+ } >+ /*DSC Delay per state*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.BlendingAndTiming[k] != k) { >+ mode_lib->vba.slices = 0; >+ } else if (locals->RequiresDSC[i][k] == 0 >+ || locals->RequiresDSC[i][k] == false) { >+ mode_lib->vba.slices = 0; >+ } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { >+ mode_lib->vba.slices = dml_ceil( >+ mode_lib->vba.PixelClockBackEnd[k] / 400.0, >+ 4.0); >+ } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { >+ mode_lib->vba.slices = 8.0; >+ } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { >+ mode_lib->vba.slices = 4.0; >+ } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { >+ mode_lib->vba.slices = 2.0; >+ } else { >+ mode_lib->vba.slices = 1.0; >+ } >+ if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE >+ || locals->OutputBppPerState[i][k] == BPP_INVALID) { >+ mode_lib->vba.bpp = 0.0; >+ } else { >+ mode_lib->vba.bpp = locals->OutputBppPerState[i][k]; >+ } >+ if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) { >+ if (locals->ODMCombineEnablePerState[i][k] == false) { >+ locals->DSCDelayPerState[i][k] = >+ dscceComputeDelay( >+ mode_lib->vba.DSCInputBitPerComponent[k], >+ mode_lib->vba.bpp, >+ dml_ceil( >+ mode_lib->vba.HActive[k] >+ / mode_lib->vba.slices, >+ 1.0), >+ mode_lib->vba.slices, >+ mode_lib->vba.OutputFormat[k]) >+ + dscComputeDelay( >+ mode_lib->vba.OutputFormat[k]); >+ } else { >+ locals->DSCDelayPerState[i][k] = >+ 2.0 * (dscceComputeDelay( >+ mode_lib->vba.DSCInputBitPerComponent[k], >+ mode_lib->vba.bpp, >+ dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), >+ mode_lib->vba.slices / 2, >+ mode_lib->vba.OutputFormat[k]) >+ + dscComputeDelay(mode_lib->vba.OutputFormat[k])); >+ } >+ locals->DSCDelayPerState[i][k] = >+ locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k]; >+ } else { >+ locals->DSCDelayPerState[i][k] = 0.0; >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) { >+ for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true) >+ locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m]; >+ } >+ } >+ } >+ } >+ >+ //Prefetch Check >+ for (i = 0; i <= mode_lib->vba.soc.num_states; ++i) { >+ for (j = 0; j <= 1; ++j) { >+ locals->TotalNumberOfDCCActiveDPP[i][j] = 0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.DCCEnable[k] == true) >+ locals->TotalNumberOfDCCActiveDPP[i][j] = locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; >+ } >+ } >+ } >+ >+ mode_lib->vba.UrgentLatency = dml_max3( >+ mode_lib->vba.UrgentLatencyPixelDataOnly, >+ mode_lib->vba.UrgentLatencyPixelMixedWithVMData, >+ mode_lib->vba.UrgentLatencyVMDataOnly); >+ mode_lib->vba.PrefetchERROR = CalculateMinAndMaxPrefetchMode( >+ mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, >+ &mode_lib->vba.MinPrefetchMode, >+ &mode_lib->vba.MaxPrefetchMode); >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k]; >+ locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k]; >+ if (locals->ODMCombineEnablePerState[i][k] == true) { >+ locals->SwathWidthYThisState[k] = >+ dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])); >+ } else { >+ locals->SwathWidthYThisState[k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; >+ } >+ mode_lib->vba.SwathWidthGranularityY = 256.0 >+ / dml_ceil(locals->BytePerPixelInDETY[k], 1.0) >+ / locals->MaxSwathHeightY[k]; >+ mode_lib->vba.RoundedUpMaxSwathSizeBytesY = >+ (dml_ceil(locals->SwathWidthYThisState[k] - 1.0, mode_lib->vba.SwathWidthGranularityY) >+ + mode_lib->vba.SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { >+ mode_lib->vba.RoundedUpMaxSwathSizeBytesY = dml_ceil( >+ mode_lib->vba.RoundedUpMaxSwathSizeBytesY, >+ 256.0) + 256; >+ } >+ if (locals->MaxSwathHeightC[k] > 0.0) { >+ mode_lib->vba.SwathWidthGranularityC = 256.0 / dml_ceil(locals->BytePerPixelInDETC[k], 2.0) / locals->MaxSwathHeightC[k]; >+ mode_lib->vba.RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYThisState[k] / 2.0 - 1.0, mode_lib->vba.SwathWidthGranularityC) >+ + mode_lib->vba.SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k]; >+ if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { >+ mode_lib->vba.RoundedUpMaxSwathSizeBytesC = dml_ceil(mode_lib->vba.RoundedUpMaxSwathSizeBytesC, 256.0) + 256; >+ } >+ } else { >+ mode_lib->vba.RoundedUpMaxSwathSizeBytesC = 0.0; >+ } >+ if (mode_lib->vba.RoundedUpMaxSwathSizeBytesY + mode_lib->vba.RoundedUpMaxSwathSizeBytesC >+ <= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) { >+ locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k]; >+ locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k]; >+ } else { >+ locals->SwathHeightYThisState[k] = >+ locals->MinSwathHeightY[k]; >+ locals->SwathHeightCThisState[k] = >+ locals->MinSwathHeightC[k]; >+ } >+ } >+ >+ CalculateDCFCLKDeepSleep( >+ mode_lib, >+ mode_lib->vba.NumberOfActivePlanes, >+ locals->BytePerPixelInDETY, >+ locals->BytePerPixelInDETC, >+ mode_lib->vba.VRatio, >+ locals->SwathWidthYThisState, >+ locals->NoOfDPPThisState, >+ mode_lib->vba.HRatio, >+ mode_lib->vba.PixelClock, >+ locals->PSCL_FACTOR, >+ locals->PSCL_FACTOR_CHROMA, >+ locals->RequiredDPPCLKThisState, >+ &mode_lib->vba.ProjectedDCFCLKDeepSleep); >+ >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) { >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes( >+ mode_lib, >+ mode_lib->vba.DCCEnable[k], >+ locals->Read256BlockHeightC[k], >+ locals->Read256BlockWidthC[k], >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(locals->BytePerPixelInDETC[k], 2.0), >+ mode_lib->vba.SourceScan[k], >+ mode_lib->vba.ViewportWidth[k] / 2.0, >+ mode_lib->vba.ViewportHeight[k] / 2.0, >+ locals->SwathWidthYThisState[k] / 2.0, >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.HostVMEnable, >+ mode_lib->vba.HostVMMaxPageTableLevels, >+ mode_lib->vba.HostVMCachedPageTableLevels, >+ mode_lib->vba.VMMPageSize, >+ mode_lib->vba.PTEBufferSizeInRequestsChroma, >+ mode_lib->vba.PitchC[k], >+ 0.0, >+ &locals->MacroTileWidthC[k], >+ &mode_lib->vba.MetaRowBytesC, >+ &mode_lib->vba.DPTEBytesPerRowC, >+ &locals->PTEBufferSizeNotExceededC[i][j][k], >+ locals->dpte_row_width_chroma_ub, >+ &locals->dpte_row_height_chroma[k], >+ &locals->meta_req_width_chroma[k], >+ &locals->meta_req_height_chroma[k], >+ &locals->meta_row_width_chroma[k], >+ &locals->meta_row_height_chroma[k], >+ &locals->vm_group_bytes_chroma, >+ &locals->dpte_group_bytes_chroma, >+ locals->PixelPTEReqWidthC, >+ locals->PixelPTEReqHeightC, >+ locals->PTERequestSizeC, >+ locals->dpde0_bytes_per_frame_ub_c, >+ locals->meta_pte_bytes_per_frame_ub_c); >+ locals->PrefetchLinesC[k] = CalculatePrefetchSourceLines( >+ mode_lib, >+ mode_lib->vba.VRatio[k]/2, >+ mode_lib->vba.VTAPsChroma[k], >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ locals->SwathHeightCThisState[k], >+ mode_lib->vba.ViewportYStartC[k], >+ &locals->PrefillC[k], >+ &locals->MaxNumSwC[k]); >+ locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma; >+ } else { >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0; >+ mode_lib->vba.MetaRowBytesC = 0.0; >+ mode_lib->vba.DPTEBytesPerRowC = 0.0; >+ locals->PrefetchLinesC[k] = 0.0; >+ locals->PTEBufferSizeNotExceededC[i][j][k] = true; >+ locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; >+ } >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes( >+ mode_lib, >+ mode_lib->vba.DCCEnable[k], >+ locals->Read256BlockHeightY[k], >+ locals->Read256BlockWidthY[k], >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.SurfaceTiling[k], >+ dml_ceil(locals->BytePerPixelInDETY[k], 1.0), >+ mode_lib->vba.SourceScan[k], >+ mode_lib->vba.ViewportWidth[k], >+ mode_lib->vba.ViewportHeight[k], >+ locals->SwathWidthYThisState[k], >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.HostVMEnable, >+ mode_lib->vba.HostVMMaxPageTableLevels, >+ mode_lib->vba.HostVMCachedPageTableLevels, >+ mode_lib->vba.VMMPageSize, >+ locals->PTEBufferSizeInRequestsForLuma, >+ mode_lib->vba.PitchY[k], >+ mode_lib->vba.DCCMetaPitchY[k], >+ &locals->MacroTileWidthY[k], >+ &mode_lib->vba.MetaRowBytesY, >+ &mode_lib->vba.DPTEBytesPerRowY, >+ &locals->PTEBufferSizeNotExceededY[i][j][k], >+ locals->dpte_row_width_luma_ub, >+ &locals->dpte_row_height[k], >+ &locals->meta_req_width[k], >+ &locals->meta_req_height[k], >+ &locals->meta_row_width[k], >+ &locals->meta_row_height[k], >+ &locals->vm_group_bytes[k], >+ &locals->dpte_group_bytes[k], >+ locals->PixelPTEReqWidthY, >+ locals->PixelPTEReqHeightY, >+ locals->PTERequestSizeY, >+ locals->dpde0_bytes_per_frame_ub_l, >+ locals->meta_pte_bytes_per_frame_ub_l); >+ locals->PrefetchLinesY[k] = CalculatePrefetchSourceLines( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.vtaps[k], >+ mode_lib->vba.Interlace[k], >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ locals->SwathHeightYThisState[k], >+ mode_lib->vba.ViewportYStartY[k], >+ &locals->PrefillY[k], >+ &locals->MaxNumSwY[k]); >+ locals->PDEAndMetaPTEBytesPerFrame[k] = >+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameY + mode_lib->vba.PDEAndMetaPTEBytesPerFrameC; >+ locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC; >+ locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC; >+ >+ CalculateActiveRowBandwidth( >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.VRatio[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.HTotal[k] / >+ mode_lib->vba.PixelClock[k], >+ mode_lib->vba.MetaRowBytesY, >+ mode_lib->vba.MetaRowBytesC, >+ locals->meta_row_height[k], >+ locals->meta_row_height_chroma[k], >+ mode_lib->vba.DPTEBytesPerRowY, >+ mode_lib->vba.DPTEBytesPerRowC, >+ locals->dpte_row_height[k], >+ locals->dpte_row_height_chroma[k], >+ &locals->meta_row_bw[k], >+ &locals->dpte_row_bw[k]); >+ } >+ mode_lib->vba.ExtraLatency = CalculateExtraLatency( >+ locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i], >+ locals->TotalNumberOfActiveDPP[i][j], >+ mode_lib->vba.PixelChunkSizeInKByte, >+ locals->TotalNumberOfDCCActiveDPP[i][j], >+ mode_lib->vba.MetaChunkSize, >+ locals->ReturnBWPerState[i], >+ mode_lib->vba.GPUVMEnable, >+ mode_lib->vba.HostVMEnable, >+ mode_lib->vba.NumberOfActivePlanes, >+ locals->NoOfDPPThisState, >+ locals->dpte_group_bytes, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ mode_lib->vba.HostVMMaxPageTableLevels, >+ mode_lib->vba.HostVMCachedPageTableLevels); >+ >+ mode_lib->vba.TimeCalc = 24.0 / mode_lib->vba.ProjectedDCFCLKDeepSleep; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ if (mode_lib->vba.WritebackEnable[k] == true) { >+ locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency >+ + CalculateWriteBackDelay( >+ mode_lib->vba.WritebackPixelFormat[k], >+ mode_lib->vba.WritebackHRatio[k], >+ mode_lib->vba.WritebackVRatio[k], >+ mode_lib->vba.WritebackLumaHTaps[k], >+ mode_lib->vba.WritebackLumaVTaps[k], >+ mode_lib->vba.WritebackChromaHTaps[k], >+ mode_lib->vba.WritebackChromaVTaps[k], >+ mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; >+ } else { >+ locals->WritebackDelay[i][k] = 0.0; >+ } >+ for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) { >+ if (mode_lib->vba.BlendingAndTiming[m] == k >+ && mode_lib->vba.WritebackEnable[m] >+ == true) { >+ locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k], >+ mode_lib->vba.WritebackLatency + CalculateWriteBackDelay( >+ mode_lib->vba.WritebackPixelFormat[m], >+ mode_lib->vba.WritebackHRatio[m], >+ mode_lib->vba.WritebackVRatio[m], >+ mode_lib->vba.WritebackLumaHTaps[m], >+ mode_lib->vba.WritebackLumaVTaps[m], >+ mode_lib->vba.WritebackChromaHTaps[m], >+ mode_lib->vba.WritebackChromaVTaps[m], >+ mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); >+ } >+ } >+ } >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == m) { >+ locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m]; >+ } >+ } >+ } >+ mode_lib->vba.MaxMaxVStartup = 0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] >+ - dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0)); >+ mode_lib->vba.MaxMaxVStartup = dml_max(mode_lib->vba.MaxMaxVStartup, locals->MaximumVStartup[k]); >+ } >+ >+ mode_lib->vba.NextPrefetchMode = mode_lib->vba.MinPrefetchMode; >+ mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup; >+ do { >+ mode_lib->vba.PrefetchMode[i][j] = mode_lib->vba.NextPrefetchMode; >+ mode_lib->vba.MaxVStartup = mode_lib->vba.NextMaxVStartup; >+ >+ mode_lib->vba.TWait = CalculateTWait( >+ mode_lib->vba.PrefetchMode[i][j], >+ mode_lib->vba.DRAMClockChangeLatency, >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.SREnterPlusExitTime); >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ Pipe myPipe; >+ HostVM myHostVM; >+ >+ if (mode_lib->vba.XFCEnabled[k] == true) { >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = >+ CalculateRemoteSurfaceFlipDelay( >+ mode_lib, >+ mode_lib->vba.VRatio[k], >+ locals->SwathWidthYThisState[k], >+ dml_ceil(locals->BytePerPixelInDETY[k], 1.0), >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.XFCTSlvVupdateOffset, >+ mode_lib->vba.XFCTSlvVupdateWidth, >+ mode_lib->vba.XFCTSlvVreadyOffset, >+ mode_lib->vba.XFCXBUFLatencyTolerance, >+ mode_lib->vba.XFCFillBWOverhead, >+ mode_lib->vba.XFCSlvChunkSize, >+ mode_lib->vba.XFCBusTransportTime, >+ mode_lib->vba.TimeCalc, >+ mode_lib->vba.TWait, >+ &mode_lib->vba.SrcActiveDrainRate, >+ &mode_lib->vba.TInitXFill, >+ &mode_lib->vba.TslvChk); >+ } else { >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0.0; >+ } >+ >+ myPipe.DPPCLK = locals->RequiredDPPCLK[i][j][k]; >+ myPipe.DISPCLK = locals->RequiredDISPCLK[i][j]; >+ myPipe.PixelClock = mode_lib->vba.PixelClock[k]; >+ myPipe.DCFCLKDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep; >+ myPipe.DPPPerPlane = locals->NoOfDPP[i][j][k]; >+ myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k]; >+ myPipe.SourceScan = mode_lib->vba.SourceScan[k]; >+ myPipe.BlockWidth256BytesY = locals->Read256BlockWidthY[k]; >+ myPipe.BlockHeight256BytesY = locals->Read256BlockHeightY[k]; >+ myPipe.BlockWidth256BytesC = locals->Read256BlockWidthC[k]; >+ myPipe.BlockHeight256BytesC = locals->Read256BlockHeightC[k]; >+ myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; >+ myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k]; >+ myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]; >+ myPipe.HTotal = mode_lib->vba.HTotal[k]; >+ >+ >+ myHostVM.Enable = mode_lib->vba.HostVMEnable; >+ myHostVM.MaxPageTableLevels = mode_lib->vba.HostVMMaxPageTableLevels; >+ myHostVM.CachedPageTableLevels = mode_lib->vba.HostVMCachedPageTableLevels; >+ >+ >+ mode_lib->vba.IsErrorResult[i][j][k] = CalculatePrefetchSchedule( >+ mode_lib, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ &myPipe, >+ locals->DSCDelayPerState[i][k], >+ mode_lib->vba.DPPCLKDelaySubtotal, >+ mode_lib->vba.DPPCLKDelaySCL, >+ mode_lib->vba.DPPCLKDelaySCLLBOnly, >+ mode_lib->vba.DPPCLKDelayCNVCFormater, >+ mode_lib->vba.DPPCLKDelayCNVCCursor, >+ mode_lib->vba.DISPCLKDelaySubtotal, >+ locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k], >+ mode_lib->vba.OutputFormat[k], >+ mode_lib->vba.MaxInterDCNTileRepeaters, >+ dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[k]), >+ locals->MaximumVStartup[k], >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.GPUVMEnable, >+ &myHostVM, >+ mode_lib->vba.DynamicMetadataEnable[k], >+ mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], >+ mode_lib->vba.DynamicMetadataTransmittedBytes[k], >+ mode_lib->vba.DCCEnable[k], >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.ExtraLatency, >+ mode_lib->vba.TimeCalc, >+ locals->PDEAndMetaPTEBytesPerFrame[k], >+ locals->MetaRowBytes[k], >+ locals->DPTEBytesPerRow[k], >+ locals->PrefetchLinesY[k], >+ locals->SwathWidthYThisState[k], >+ locals->BytePerPixelInDETY[k], >+ locals->PrefillY[k], >+ locals->MaxNumSwY[k], >+ locals->PrefetchLinesC[k], >+ locals->BytePerPixelInDETC[k], >+ locals->PrefillC[k], >+ locals->MaxNumSwC[k], >+ locals->SwathHeightYThisState[k], >+ locals->SwathHeightCThisState[k], >+ mode_lib->vba.TWait, >+ mode_lib->vba.XFCEnabled[k], >+ mode_lib->vba.XFCRemoteSurfaceFlipDelay, >+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP, >+ &locals->dst_x_after_scaler, >+ &locals->dst_y_after_scaler, >+ &locals->LineTimesForPrefetch[k], >+ &locals->PrefetchBW[k], >+ &locals->LinesForMetaPTE[k], >+ &locals->LinesForMetaAndDPTERow[k], >+ &locals->VRatioPreY[i][j][k], >+ &locals->VRatioPreC[i][j][k], >+ &locals->RequiredPrefetchPixelDataBWLuma[i][j][k], >+ &locals->RequiredPrefetchPixelDataBWChroma[i][j][k], >+ &locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata, >+ &locals->Tno_bw[k], >+ &locals->prefetch_vmrow_bw[k], >+ locals->swath_width_luma_ub, >+ locals->swath_width_chroma_ub, >+ &mode_lib->vba.VUpdateOffsetPix[k], >+ &mode_lib->vba.VUpdateWidthPix[k], >+ &mode_lib->vba.VReadyOffsetPix[k]); >+ } >+ mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0; >+ mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ uint m; >+ >+ locals->cursor_bw[k] = 0; >+ locals->cursor_bw_pre[k] = 0; >+ for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { >+ locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] >+ / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; >+ locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] >+ / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k]; >+ } >+ >+ CalculateUrgentBurstFactor( >+ mode_lib->vba.DETBufferSizeInKByte, >+ locals->SwathHeightYThisState[k], >+ locals->SwathHeightCThisState[k], >+ locals->SwathWidthYThisState[k], >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.CursorBufferSize, >+ mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1], >+ dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), >+ mode_lib->vba.VRatio[k], >+ locals->VRatioPreY[i][j][k], >+ locals->VRatioPreC[i][j][k], >+ locals->BytePerPixelInDETY[k], >+ locals->BytePerPixelInDETC[k], >+ &locals->UrgentBurstFactorCursor[k], >+ &locals->UrgentBurstFactorCursorPre[k], >+ &locals->UrgentBurstFactorLuma[k], >+ &locals->UrgentBurstFactorLumaPre[k], >+ &locals->UrgentBurstFactorChroma[k], >+ &locals->UrgentBurstFactorChromaPre[k], >+ &locals->NotEnoughUrgentLatencyHiding, >+ &locals->NotEnoughUrgentLatencyHidingPre); >+ >+ if (mode_lib->vba.UseUrgentBurstBandwidth == false) { >+ locals->UrgentBurstFactorCursor[k] = 1; >+ locals->UrgentBurstFactorCursorPre[k] = 1; >+ locals->UrgentBurstFactorLuma[k] = 1; >+ locals->UrgentBurstFactorLumaPre[k] = 1; >+ locals->UrgentBurstFactorChroma[k] = 1; >+ locals->UrgentBurstFactorChromaPre[k] = 1; >+ } >+ >+ mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = mode_lib->vba.MaximumReadBandwidthWithoutPrefetch >+ + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k] + locals->ReadBandwidthLuma[k] >+ * locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k] >+ * locals->UrgentBurstFactorChroma[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k]; >+ mode_lib->vba.MaximumReadBandwidthWithPrefetch = mode_lib->vba.MaximumReadBandwidthWithPrefetch >+ + dml_max3(locals->prefetch_vmrow_bw[k], >+ locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k] >+ * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k] >+ + locals->meta_row_bw[k] + locals->dpte_row_bw[k], >+ locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k] >+ + locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k] >+ + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); >+ } >+ locals->BandwidthWithoutPrefetchSupported[i] = true; >+ if (mode_lib->vba.MaximumReadBandwidthWithoutPrefetch > locals->ReturnBWPerState[i] >+ || locals->NotEnoughUrgentLatencyHiding == 1) { >+ locals->BandwidthWithoutPrefetchSupported[i] = false; >+ } >+ >+ locals->PrefetchSupported[i][j] = true; >+ if (mode_lib->vba.MaximumReadBandwidthWithPrefetch > locals->ReturnBWPerState[i] >+ || locals->NotEnoughUrgentLatencyHiding == 1 >+ || locals->NotEnoughUrgentLatencyHidingPre == 1) { >+ locals->PrefetchSupported[i][j] = false; >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->LineTimesForPrefetch[k] < 2.0 >+ || locals->LinesForMetaPTE[k] >= 32.0 >+ || locals->LinesForMetaAndDPTERow[k] >= 16.0 >+ || mode_lib->vba.IsErrorResult[i][j][k] == true) { >+ locals->PrefetchSupported[i][j] = false; >+ } >+ } >+ locals->VRatioInPrefetchSupported[i][j] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->VRatioPreY[i][j][k] > 4.0 >+ || locals->VRatioPreC[i][j][k] > 4.0 >+ || mode_lib->vba.IsErrorResult[i][j][k] == true) { >+ locals->VRatioInPrefetchSupported[i][j] = false; >+ } >+ } >+ mode_lib->vba.AnyLinesForVMOrRowTooLarge = false; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ if (locals->LinesForMetaAndDPTERow[k] >= 16 || locals->LinesForMetaPTE[k] >= 32) { >+ mode_lib->vba.AnyLinesForVMOrRowTooLarge = true; >+ } >+ } >+ >+ if (mode_lib->vba.MaxVStartup <= 13 || mode_lib->vba.AnyLinesForVMOrRowTooLarge == false) { >+ mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup; >+ mode_lib->vba.NextPrefetchMode = mode_lib->vba.NextPrefetchMode + 1; >+ } else { >+ mode_lib->vba.NextMaxVStartup = mode_lib->vba.NextMaxVStartup - 1; >+ } >+ } while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true) >+ && (mode_lib->vba.NextMaxVStartup != mode_lib->vba.MaxMaxVStartup >+ || mode_lib->vba.NextPrefetchMode < mode_lib->vba.MaxPrefetchMode)); >+ >+ if (locals->PrefetchSupported[i][j] == true && locals->VRatioInPrefetchSupported[i][j] == true) { >+ mode_lib->vba.BandwidthAvailableForImmediateFlip = locals->ReturnBWPerState[i]; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.BandwidthAvailableForImmediateFlip >+ - dml_max(locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] >+ + locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] >+ + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k], >+ locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k] >+ + locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k] >+ + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); >+ } >+ mode_lib->vba.TotImmediateFlipBytes = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes >+ + locals->PDEAndMetaPTEBytesPerFrame[k] + locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k]; >+ } >+ >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ CalculateFlipSchedule( >+ mode_lib, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ mode_lib->vba.ExtraLatency, >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.GPUVMMaxPageTableLevels, >+ mode_lib->vba.HostVMEnable, >+ mode_lib->vba.HostVMMaxPageTableLevels, >+ mode_lib->vba.HostVMCachedPageTableLevels, >+ mode_lib->vba.GPUVMEnable, >+ locals->PDEAndMetaPTEBytesPerFrame[k], >+ locals->MetaRowBytes[k], >+ locals->DPTEBytesPerRow[k], >+ mode_lib->vba.BandwidthAvailableForImmediateFlip, >+ mode_lib->vba.TotImmediateFlipBytes, >+ mode_lib->vba.SourcePixelFormat[k], >+ mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], >+ mode_lib->vba.VRatio[k], >+ locals->Tno_bw[k], >+ mode_lib->vba.DCCEnable[k], >+ locals->dpte_row_height[k], >+ locals->meta_row_height[k], >+ locals->dpte_row_height_chroma[k], >+ locals->meta_row_height_chroma[k], >+ &locals->DestinationLinesToRequestVMInImmediateFlip[k], >+ &locals->DestinationLinesToRequestRowInImmediateFlip[k], >+ &locals->final_flip_bw[k], >+ &locals->ImmediateFlipSupportedForPipe[k]); >+ } >+ mode_lib->vba.total_dcn_read_bw_with_flip = 0.0; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.total_dcn_read_bw_with_flip = mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3( >+ locals->prefetch_vmrow_bw[k], >+ locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] >+ + locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] >+ + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k], >+ locals->final_flip_bw[k] + locals->RequiredPrefetchPixelDataBWLuma[i][j][k] >+ * locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixelDataBWChroma[i][j][k] >+ * locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] >+ * locals->UrgentBurstFactorCursorPre[k]); >+ } >+ locals->ImmediateFlipSupportedForState[i][j] = true; >+ if (mode_lib->vba.total_dcn_read_bw_with_flip >+ > locals->ReturnBWPerState[i]) { >+ locals->ImmediateFlipSupportedForState[i][j] = false; >+ } >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->ImmediateFlipSupportedForPipe[k] == false) { >+ locals->ImmediateFlipSupportedForState[i][j] = false; >+ } >+ } >+ } else { >+ locals->ImmediateFlipSupportedForState[i][j] = false; >+ } >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannel = dml_max3( >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly); >+ CalculateWatermarksAndDRAMSpeedChangeSupport( >+ mode_lib, >+ mode_lib->vba.PrefetchMode[i][j], >+ mode_lib->vba.NumberOfActivePlanes, >+ mode_lib->vba.MaxLineBufferLines, >+ mode_lib->vba.LineBufferSize, >+ mode_lib->vba.DPPOutputBufferPixels, >+ mode_lib->vba.DETBufferSizeInKByte, >+ mode_lib->vba.WritebackInterfaceLumaBufferSize, >+ mode_lib->vba.WritebackInterfaceChromaBufferSize, >+ mode_lib->vba.DCFCLKPerState[i], >+ mode_lib->vba.UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels, >+ locals->ReturnBWPerState[i], >+ mode_lib->vba.GPUVMEnable, >+ locals->dpte_group_bytes, >+ mode_lib->vba.MetaChunkSize, >+ mode_lib->vba.UrgentLatency, >+ mode_lib->vba.ExtraLatency, >+ mode_lib->vba.WritebackLatency, >+ mode_lib->vba.WritebackChunkSize, >+ mode_lib->vba.SOCCLKPerState[i], >+ mode_lib->vba.DRAMClockChangeLatency, >+ mode_lib->vba.SRExitTime, >+ mode_lib->vba.SREnterPlusExitTime, >+ mode_lib->vba.ProjectedDCFCLKDeepSleep, >+ locals->NoOfDPPThisState, >+ mode_lib->vba.DCCEnable, >+ locals->RequiredDPPCLKThisState, >+ locals->SwathWidthYSingleDPP, >+ locals->SwathHeightYThisState, >+ locals->ReadBandwidthLuma, >+ locals->SwathHeightCThisState, >+ locals->ReadBandwidthChroma, >+ mode_lib->vba.LBBitPerPixel, >+ locals->SwathWidthYThisState, >+ mode_lib->vba.HRatio, >+ mode_lib->vba.vtaps, >+ mode_lib->vba.VTAPsChroma, >+ mode_lib->vba.VRatio, >+ mode_lib->vba.HTotal, >+ mode_lib->vba.PixelClock, >+ mode_lib->vba.BlendingAndTiming, >+ locals->BytePerPixelInDETY, >+ locals->BytePerPixelInDETC, >+ mode_lib->vba.WritebackEnable, >+ mode_lib->vba.WritebackPixelFormat, >+ mode_lib->vba.WritebackDestinationWidth, >+ mode_lib->vba.WritebackDestinationHeight, >+ mode_lib->vba.WritebackSourceHeight, >+ &locals->DRAMClockChangeSupport[i][j], >+ &mode_lib->vba.UrgentWatermark, >+ &mode_lib->vba.WritebackUrgentWatermark, >+ &mode_lib->vba.DRAMClockChangeWatermark, >+ &mode_lib->vba.WritebackDRAMClockChangeWatermark, >+ &mode_lib->vba.StutterExitWatermark, >+ &mode_lib->vba.StutterEnterPlusExitWatermark, >+ &mode_lib->vba.MinActiveDRAMClockChangeLatencySupported); >+ } >+ } >+ >+ /*Vertical Active BW support*/ >+ { >+ double MaxTotalVActiveRDBandwidth = 0.0; >+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { >+ MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k]; >+ } >+ for (i = 0; i <= mode_lib->vba.soc.num_states; ++i) { >+ locals->MaxTotalVerticalActiveAvailableBandwidth[i] = dml_min( >+ locals->IdealSDPPortBandwidthPerState[i] * >+ mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation >+ / 100.0, mode_lib->vba.DRAMSpeedPerState[i] * >+ mode_lib->vba.NumberOfChannels * >+ mode_lib->vba.DRAMChannelWidth * >+ mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation >+ / 100.0); >+ >+ if (MaxTotalVActiveRDBandwidth <= locals->MaxTotalVerticalActiveAvailableBandwidth[i]) { >+ locals->TotalVerticalActiveBandwidthSupport[i] = true; >+ } else { >+ locals->TotalVerticalActiveBandwidthSupport[i] = false; >+ } >+ } >+ } >+ >+ /*PTE Buffer Size Check*/ >+ >+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { >+ for (j = 0; j < 2; j++) { >+ locals->PTEBufferSizeNotExceeded[i][j] = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (locals->PTEBufferSizeNotExceededY[i][j][k] == false >+ || locals->PTEBufferSizeNotExceededC[i][j][k] == false) { >+ locals->PTEBufferSizeNotExceeded[i][j] = false; >+ } >+ } >+ } >+ } >+ /*Cursor Support Check*/ >+ >+ mode_lib->vba.CursorSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.CursorWidth[k][0] > 0.0) { >+ for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { >+ if (mode_lib->vba.CursorBPP[k][m] == 64 && mode_lib->vba.Cursor64BppSupport == false) { >+ mode_lib->vba.CursorSupport = false; >+ } >+ } >+ } >+ } >+ /*Valid Pitch Check*/ >+ >+ mode_lib->vba.PitchSupport = true; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ locals->AlignedYPitch[k] = dml_ceil( >+ dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]), >+ locals->MacroTileWidthY[k]); >+ if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) { >+ mode_lib->vba.PitchSupport = false; >+ } >+ if (mode_lib->vba.DCCEnable[k] == true) { >+ locals->AlignedDCCMetaPitch[k] = dml_ceil( >+ dml_max( >+ mode_lib->vba.DCCMetaPitchY[k], >+ mode_lib->vba.ViewportWidth[k]), >+ 64.0 * locals->Read256BlockWidthY[k]); >+ } else { >+ locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k]; >+ } >+ if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) { >+ mode_lib->vba.PitchSupport = false; >+ } >+ if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 >+ && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) { >+ locals->AlignedCPitch[k] = dml_ceil( >+ dml_max( >+ mode_lib->vba.PitchC[k], >+ mode_lib->vba.ViewportWidth[k] / 2.0), >+ locals->MacroTileWidthC[k]); >+ } else { >+ locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k]; >+ } >+ if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) { >+ mode_lib->vba.PitchSupport = false; >+ } >+ } >+ /*Mode Support, Voltage State and SOC Configuration*/ >+ >+ for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { >+ for (j = 0; j < 2; j++) { >+ enum dm_validation_status status = DML_VALIDATION_OK; >+ >+ if (mode_lib->vba.ScaleRatioAndTapsSupport != true) { >+ status = DML_FAIL_SCALE_RATIO_TAP; >+ } else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) { >+ status = DML_FAIL_SOURCE_PIXEL_FORMAT; >+ } else if (locals->ViewportSizeSupport[i] != true) { >+ status = DML_FAIL_VIEWPORT_SIZE; >+ } else if (locals->DIOSupport[i] != true) { >+ status = DML_FAIL_DIO_SUPPORT; >+ } else if (locals->NotEnoughDSCUnits[i] != false) { >+ status = DML_FAIL_NOT_ENOUGH_DSC; >+ } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) { >+ status = DML_FAIL_DSC_CLK_REQUIRED; >+ } else if (locals->ROBSupport[i] != true) { >+ status = DML_FAIL_REORDERING_BUFFER; >+ } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) { >+ status = DML_FAIL_DISPCLK_DPPCLK; >+ } else if (locals->TotalAvailablePipesSupport[i][j] != true) { >+ status = DML_FAIL_TOTAL_AVAILABLE_PIPES; >+ } else if (mode_lib->vba.NumberOfOTGSupport != true) { >+ status = DML_FAIL_NUM_OTG; >+ } else if (mode_lib->vba.WritebackModeSupport != true) { >+ status = DML_FAIL_WRITEBACK_MODE; >+ } else if (mode_lib->vba.WritebackLatencySupport != true) { >+ status = DML_FAIL_WRITEBACK_LATENCY; >+ } else if (mode_lib->vba.WritebackScaleRatioAndTapsSupport != true) { >+ status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP; >+ } else if (mode_lib->vba.CursorSupport != true) { >+ status = DML_FAIL_CURSOR_SUPPORT; >+ } else if (mode_lib->vba.PitchSupport != true) { >+ status = DML_FAIL_PITCH_SUPPORT; >+ } else if (locals->TotalVerticalActiveBandwidthSupport[i] != true) { >+ status = DML_FAIL_TOTAL_V_ACTIVE_BW; >+ } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) { >+ status = DML_FAIL_PTE_BUFFER_SIZE; >+ } else if (mode_lib->vba.NonsupportedDSCInputBPC != false) { >+ status = DML_FAIL_DSC_INPUT_BPC; >+ } else if ((mode_lib->vba.HostVMEnable != false >+ && locals->ImmediateFlipSupportedForState[i][j] != true)) { >+ status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP; >+ } else if (locals->PrefetchSupported[i][j] != true) { >+ status = DML_FAIL_PREFETCH_SUPPORT; >+ } else if (locals->VRatioInPrefetchSupported[i][j] != true) { >+ status = DML_FAIL_V_RATIO_PREFETCH; >+ } >+ >+ if (status == DML_VALIDATION_OK) { >+ locals->ModeSupport[i][j] = true; >+ } else { >+ locals->ModeSupport[i][j] = false; >+ } >+ locals->ValidationStatus[i] = status; >+ } >+ } >+ { >+ unsigned int MaximumMPCCombine = 0; >+ mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1; >+ for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) { >+ if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) { >+ mode_lib->vba.VoltageLevel = i; >+ if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false >+ || mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible >+ || (mode_lib->vba.WhenToDoMPCCombine == dm_mpc_reduce_voltage_and_clocks >+ && ((locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive >+ && locals->DRAMClockChangeSupport[i][0] != dm_dram_clock_change_vactive) >+ || (locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank >+ && locals->DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported))))) { >+ MaximumMPCCombine = 1; >+ } else { >+ MaximumMPCCombine = 0; >+ } >+ break; >+ } >+ } >+ mode_lib->vba.ImmediateFlipSupport = >+ locals->ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; >+ locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; >+ } >+ mode_lib->vba.DISPCLK = locals->RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; >+ mode_lib->vba.maxMpcComb = MaximumMPCCombine; >+ } >+ mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; >+ mode_lib->vba.ReturnBW = locals->ReturnBWPerState[mode_lib->vba.VoltageLevel]; >+ for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { >+ if (mode_lib->vba.BlendingAndTiming[k] == k) { >+ mode_lib->vba.ODMCombineEnabled[k] = >+ locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k]; >+ } else { >+ mode_lib->vba.ODMCombineEnabled[k] = 0; >+ } >+ mode_lib->vba.DSCEnabled[k] = >+ locals->RequiresDSC[mode_lib->vba.VoltageLevel][k]; >+ mode_lib->vba.OutputBpp[k] = >+ locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k]; >+ } >+} >+ >+static void CalculateWatermarksAndDRAMSpeedChangeSupport( >+ struct display_mode_lib *mode_lib, >+ unsigned int PrefetchMode, >+ unsigned int NumberOfActivePlanes, >+ unsigned int MaxLineBufferLines, >+ unsigned int LineBufferSize, >+ unsigned int DPPOutputBufferPixels, >+ double DETBufferSizeInKByte, >+ unsigned int WritebackInterfaceLumaBufferSize, >+ unsigned int WritebackInterfaceChromaBufferSize, >+ double DCFCLK, >+ double UrgentOutOfOrderReturn, >+ double ReturnBW, >+ bool GPUVMEnable, >+ long dpte_group_bytes[], >+ unsigned int MetaChunkSize, >+ double UrgentLatency, >+ double ExtraLatency, >+ double WritebackLatency, >+ double WritebackChunkSize, >+ double SOCCLK, >+ double DRAMClockChangeLatency, >+ double SRExitTime, >+ double SREnterPlusExitTime, >+ double DCFCLKDeepSleep, >+ int DPPPerPlane[], >+ bool DCCEnable[], >+ double DPPCLK[], >+ unsigned int SwathWidthSingleDPPY[], >+ unsigned int SwathHeightY[], >+ double ReadBandwidthPlaneLuma[], >+ unsigned int SwathHeightC[], >+ double ReadBandwidthPlaneChroma[], >+ unsigned int LBBitPerPixel[], >+ unsigned int SwathWidthY[], >+ double HRatio[], >+ unsigned int vtaps[], >+ unsigned int VTAPsChroma[], >+ double VRatio[], >+ unsigned int HTotal[], >+ double PixelClock[], >+ unsigned int BlendingAndTiming[], >+ double BytePerPixelDETY[], >+ double BytePerPixelDETC[], >+ bool WritebackEnable[], >+ enum source_format_class WritebackPixelFormat[], >+ double WritebackDestinationWidth[], >+ double WritebackDestinationHeight[], >+ double WritebackSourceHeight[], >+ enum clock_change_support *DRAMClockChangeSupport, >+ double *UrgentWatermark, >+ double *WritebackUrgentWatermark, >+ double *DRAMClockChangeWatermark, >+ double *WritebackDRAMClockChangeWatermark, >+ double *StutterExitWatermark, >+ double *StutterEnterPlusExitWatermark, >+ double *MinActiveDRAMClockChangeLatencySupported) >+{ >+ double EffectiveLBLatencyHidingY; >+ double EffectiveLBLatencyHidingC; >+ double DPPOutputBufferLinesY; >+ double DPPOutputBufferLinesC; >+ double DETBufferSizeY; >+ double DETBufferSizeC; >+ double LinesInDETY[DC__NUM_DPP__MAX]; >+ double LinesInDETC; >+ unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; >+ unsigned int LinesInDETCRoundedDownToSwath; >+ double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; >+ double FullDETBufferingTimeC; >+ double ActiveDRAMClockChangeLatencyMarginY; >+ double ActiveDRAMClockChangeLatencyMarginC; >+ double WritebackDRAMClockChangeLatencyMargin; >+ double PlaneWithMinActiveDRAMClockChangeMargin; >+ double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank; >+ double FullDETBufferingTimeYStutterCriticalPlane = 0; >+ double TimeToFinishSwathTransferStutterCriticalPlane = 0; >+ uint k, j; >+ >+ mode_lib->vba.TotalActiveDPP = 0; >+ mode_lib->vba.TotalDCCActiveDPP = 0; >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k]; >+ if (DCCEnable[k] == true) { >+ mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k]; >+ } >+ } >+ >+ mode_lib->vba.TotalDataReadBandwidth = 0; >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ mode_lib->vba.TotalDataReadBandwidth = mode_lib->vba.TotalDataReadBandwidth >+ + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k]; >+ } >+ >+ *UrgentWatermark = UrgentLatency + ExtraLatency; >+ >+ *DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark; >+ >+ mode_lib->vba.TotalActiveWriteback = 0; >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (WritebackEnable[k] == true) { >+ mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1; >+ } >+ } >+ >+ if (mode_lib->vba.TotalActiveWriteback <= 1) { >+ *WritebackUrgentWatermark = WritebackLatency; >+ } else { >+ *WritebackUrgentWatermark = WritebackLatency >+ + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; >+ } >+ >+ if (mode_lib->vba.TotalActiveWriteback <= 1) { >+ *WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency; >+ } else { >+ *WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency >+ + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; >+ } >+ >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ >+ mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines, >+ dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) >+ - (vtaps[k] - 1); >+ >+ mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines, >+ dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1)) >+ - (VTAPsChroma[k] - 1); >+ >+ EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k] >+ * (HTotal[k] / PixelClock[k]); >+ >+ EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC >+ / (VRatio[k] / 2) * (HTotal[k] / PixelClock[k]); >+ >+ if (SwathWidthY[k] > 2 * DPPOutputBufferPixels) { >+ DPPOutputBufferLinesY = (double) DPPOutputBufferPixels / SwathWidthY[k]; >+ } else if (SwathWidthY[k] > DPPOutputBufferPixels) { >+ DPPOutputBufferLinesY = 0.5; >+ } else { >+ DPPOutputBufferLinesY = 1; >+ } >+ >+ if (SwathWidthY[k] / 2.0 > 2 * DPPOutputBufferPixels) { >+ DPPOutputBufferLinesC = (double) DPPOutputBufferPixels >+ / (SwathWidthY[k] / 2.0); >+ } else if (SwathWidthY[k] / 2.0 > DPPOutputBufferPixels) { >+ DPPOutputBufferLinesC = 0.5; >+ } else { >+ DPPOutputBufferLinesC = 1; >+ } >+ >+ CalculateDETBufferSize( >+ DETBufferSizeInKByte, >+ SwathHeightY[k], >+ SwathHeightC[k], >+ &DETBufferSizeY, >+ &DETBufferSizeC); >+ >+ LinesInDETY[k] = DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; >+ LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); >+ FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] >+ * (HTotal[k] / PixelClock[k]) / VRatio[k]; >+ if (BytePerPixelDETC[k] > 0) { >+ LinesInDETC = DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0); >+ LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); >+ FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath >+ * (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2); >+ } else { >+ LinesInDETC = 0; >+ FullDETBufferingTimeC = 999999; >+ } >+ >+ ActiveDRAMClockChangeLatencyMarginY = HTotal[k] / PixelClock[k] >+ * DPPOutputBufferLinesY + EffectiveLBLatencyHidingY >+ + FullDETBufferingTimeY[k] - *DRAMClockChangeWatermark; >+ >+ if (NumberOfActivePlanes > 1) { >+ ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY >+ - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k]; >+ } >+ >+ if (BytePerPixelDETC[k] > 0) { >+ ActiveDRAMClockChangeLatencyMarginC = HTotal[k] / PixelClock[k] >+ * DPPOutputBufferLinesC + EffectiveLBLatencyHidingC >+ + FullDETBufferingTimeC - *DRAMClockChangeWatermark; >+ if (NumberOfActivePlanes > 1) { >+ ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC >+ - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / (VRatio[k] / 2); >+ } >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( >+ ActiveDRAMClockChangeLatencyMarginY, >+ ActiveDRAMClockChangeLatencyMarginC); >+ } else { >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY; >+ } >+ >+ if (WritebackEnable[k] == true) { >+ if (WritebackPixelFormat[k] == dm_444_32) { >+ WritebackDRAMClockChangeLatencyMargin = (WritebackInterfaceLumaBufferSize >+ + WritebackInterfaceChromaBufferSize) / (WritebackDestinationWidth[k] >+ * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] >+ / PixelClock[k]) * 4) - *WritebackDRAMClockChangeWatermark; >+ } else { >+ WritebackDRAMClockChangeLatencyMargin = dml_min( >+ WritebackInterfaceLumaBufferSize * 8.0 / 10, >+ 2 * WritebackInterfaceChromaBufferSize * 8.0 / 10) / (WritebackDestinationWidth[k] >+ * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k])) >+ - *WritebackDRAMClockChangeWatermark; >+ } >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], >+ WritebackDRAMClockChangeLatencyMargin); >+ } >+ } >+ >+ mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999; >+ PlaneWithMinActiveDRAMClockChangeMargin = 0; >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] >+ < mode_lib->vba.MinActiveDRAMClockChangeMargin) { >+ mode_lib->vba.MinActiveDRAMClockChangeMargin = >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; >+ if (BlendingAndTiming[k] == k) { >+ PlaneWithMinActiveDRAMClockChangeMargin = k; >+ } else { >+ for (j = 0; j < NumberOfActivePlanes; ++j) { >+ if (BlendingAndTiming[k] == j) { >+ PlaneWithMinActiveDRAMClockChangeMargin = j; >+ } >+ } >+ } >+ } >+ } >+ >+ *MinActiveDRAMClockChangeLatencySupported = mode_lib->vba.MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency; >+ >+ SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999; >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) >+ && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) >+ && mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] >+ < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) { >+ SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = >+ mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; >+ } >+ } >+ >+ mode_lib->vba.TotalNumberOfActiveOTG = 0; >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (BlendingAndTiming[k] == k) { >+ mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG + 1; >+ } >+ } >+ >+ if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) { >+ *DRAMClockChangeSupport = dm_dram_clock_change_vactive; >+ } else if (((mode_lib->vba.SynchronizedVBlank == true >+ || mode_lib->vba.TotalNumberOfActiveOTG == 1 >+ || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) >+ && PrefetchMode == 0)) { >+ *DRAMClockChangeSupport = dm_dram_clock_change_vblank; >+ } else { >+ *DRAMClockChangeSupport = dm_dram_clock_change_unsupported; >+ } >+ >+ FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[0]; >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) { >+ TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] >+ - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) >+ * (HTotal[k] / PixelClock[k]) / VRatio[k]; >+ } >+ } >+ >+ *StutterExitWatermark = SRExitTime + mode_lib->vba.LastPixelOfLineExtraWatermark >+ + ExtraLatency + 10 / DCFCLKDeepSleep; >+ *StutterEnterPlusExitWatermark = dml_max( >+ SREnterPlusExitTime + mode_lib->vba.LastPixelOfLineExtraWatermark >+ + ExtraLatency + 10 / DCFCLKDeepSleep, >+ TimeToFinishSwathTransferStutterCriticalPlane); >+ >+} >+ >+static void CalculateDCFCLKDeepSleep( >+ struct display_mode_lib *mode_lib, >+ unsigned int NumberOfActivePlanes, >+ double BytePerPixelDETY[], >+ double BytePerPixelDETC[], >+ double VRatio[], >+ unsigned int SwathWidthY[], >+ int DPPPerPlane[], >+ double HRatio[], >+ double PixelClock[], >+ double PSCL_THROUGHPUT[], >+ double PSCL_THROUGHPUT_CHROMA[], >+ double DPPCLK[], >+ double *DCFCLKDeepSleep) >+{ >+ uint k; >+ double DisplayPipeLineDeliveryTimeLuma; >+ double DisplayPipeLineDeliveryTimeChroma; >+ //double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX]; >+ >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (VRatio[k] <= 1) { >+ DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] >+ / HRatio[k] / PixelClock[k]; >+ } else { >+ DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] >+ / DPPCLK[k]; >+ } >+ if (BytePerPixelDETC[k] == 0) { >+ DisplayPipeLineDeliveryTimeChroma = 0; >+ } else { >+ if (VRatio[k] / 2 <= 1) { >+ DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0 >+ * DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k]; >+ } else { >+ DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0 >+ / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; >+ } >+ } >+ >+ if (BytePerPixelDETC[k] > 0) { >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max( >+ 1.1 * SwathWidthY[k] * dml_ceil(BytePerPixelDETY[k], 1) >+ / 32.0 / DisplayPipeLineDeliveryTimeLuma, >+ 1.1 * SwathWidthY[k] / 2.0 >+ * dml_ceil(BytePerPixelDETC[k], 2) / 32.0 >+ / DisplayPipeLineDeliveryTimeChroma); >+ } else { >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * SwathWidthY[k] >+ * dml_ceil(BytePerPixelDETY[k], 1) / 64.0 >+ / DisplayPipeLineDeliveryTimeLuma; >+ } >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max( >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k], >+ PixelClock[k] / 16); >+ >+ } >+ >+ *DCFCLKDeepSleep = 8; >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ *DCFCLKDeepSleep = dml_max( >+ *DCFCLKDeepSleep, >+ mode_lib->vba.DCFCLKDeepSleepPerPlane[k]); >+ } >+} >+ >+static void CalculateDETBufferSize( >+ double DETBufferSizeInKByte, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ double *DETBufferSizeY, >+ double *DETBufferSizeC) >+{ >+ if (SwathHeightC == 0) { >+ *DETBufferSizeY = DETBufferSizeInKByte * 1024; >+ *DETBufferSizeC = 0; >+ } else if (SwathHeightY <= SwathHeightC) { >+ *DETBufferSizeY = DETBufferSizeInKByte * 1024 / 2; >+ *DETBufferSizeC = DETBufferSizeInKByte * 1024 / 2; >+ } else { >+ *DETBufferSizeY = DETBufferSizeInKByte * 1024 * 2 / 3; >+ *DETBufferSizeC = DETBufferSizeInKByte * 1024 / 3; >+ } >+} >+ >+static void CalculateUrgentBurstFactor( >+ unsigned int DETBufferSizeInKByte, >+ unsigned int SwathHeightY, >+ unsigned int SwathHeightC, >+ unsigned int SwathWidthY, >+ double LineTime, >+ double UrgentLatency, >+ double CursorBufferSize, >+ unsigned int CursorWidth, >+ unsigned int CursorBPP, >+ double VRatio, >+ double VRatioPreY, >+ double VRatioPreC, >+ double BytePerPixelInDETY, >+ double BytePerPixelInDETC, >+ double *UrgentBurstFactorCursor, >+ double *UrgentBurstFactorCursorPre, >+ double *UrgentBurstFactorLuma, >+ double *UrgentBurstFactorLumaPre, >+ double *UrgentBurstFactorChroma, >+ double *UrgentBurstFactorChromaPre, >+ unsigned int *NotEnoughUrgentLatencyHiding, >+ unsigned int *NotEnoughUrgentLatencyHidingPre) >+{ >+ double LinesInDETLuma; >+ double LinesInDETChroma; >+ unsigned int LinesInCursorBuffer; >+ double CursorBufferSizeInTime; >+ double CursorBufferSizeInTimePre; >+ double DETBufferSizeInTimeLuma; >+ double DETBufferSizeInTimeLumaPre; >+ double DETBufferSizeInTimeChroma; >+ double DETBufferSizeInTimeChromaPre; >+ double DETBufferSizeY; >+ double DETBufferSizeC; >+ >+ *NotEnoughUrgentLatencyHiding = 0; >+ *NotEnoughUrgentLatencyHidingPre = 0; >+ >+ if (CursorWidth > 0) { >+ LinesInCursorBuffer = 1 << (unsigned int) dml_floor( >+ dml_log2(CursorBufferSize * 1024.0 / (CursorWidth * CursorBPP / 8.0)), 1.0); >+ CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio; >+ if (CursorBufferSizeInTime - UrgentLatency <= 0) { >+ *NotEnoughUrgentLatencyHiding = 1; >+ *UrgentBurstFactorCursor = 0; >+ } else { >+ *UrgentBurstFactorCursor = CursorBufferSizeInTime >+ / (CursorBufferSizeInTime - UrgentLatency); >+ } >+ if (VRatioPreY > 0) { >+ CursorBufferSizeInTimePre = LinesInCursorBuffer * LineTime / VRatioPreY; >+ if (CursorBufferSizeInTimePre - UrgentLatency <= 0) { >+ *NotEnoughUrgentLatencyHidingPre = 1; >+ *UrgentBurstFactorCursorPre = 0; >+ } else { >+ *UrgentBurstFactorCursorPre = CursorBufferSizeInTimePre >+ / (CursorBufferSizeInTimePre - UrgentLatency); >+ } >+ } else { >+ *UrgentBurstFactorCursorPre = 1; >+ } >+ } >+ >+ CalculateDETBufferSize( >+ DETBufferSizeInKByte, >+ SwathHeightY, >+ SwathHeightC, >+ &DETBufferSizeY, >+ &DETBufferSizeC); >+ >+ LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / SwathWidthY; >+ DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio; >+ if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) { >+ *NotEnoughUrgentLatencyHiding = 1; >+ *UrgentBurstFactorLuma = 0; >+ } else { >+ *UrgentBurstFactorLuma = DETBufferSizeInTimeLuma >+ / (DETBufferSizeInTimeLuma - UrgentLatency); >+ } >+ if (VRatioPreY > 0) { >+ DETBufferSizeInTimeLumaPre = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime >+ / VRatioPreY; >+ if (DETBufferSizeInTimeLumaPre - UrgentLatency <= 0) { >+ *NotEnoughUrgentLatencyHidingPre = 1; >+ *UrgentBurstFactorLumaPre = 0; >+ } else { >+ *UrgentBurstFactorLumaPre = DETBufferSizeInTimeLumaPre >+ / (DETBufferSizeInTimeLumaPre - UrgentLatency); >+ } >+ } else { >+ *UrgentBurstFactorLumaPre = 1; >+ } >+ >+ if (BytePerPixelInDETC > 0) { >+ LinesInDETChroma = DETBufferSizeC / BytePerPixelInDETC / (SwathWidthY / 2); >+ DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime >+ / (VRatio / 2); >+ if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) { >+ *NotEnoughUrgentLatencyHiding = 1; >+ *UrgentBurstFactorChroma = 0; >+ } else { >+ *UrgentBurstFactorChroma = DETBufferSizeInTimeChroma >+ / (DETBufferSizeInTimeChroma - UrgentLatency); >+ } >+ if (VRatioPreC > 0) { >+ DETBufferSizeInTimeChromaPre = dml_floor(LinesInDETChroma, SwathHeightC) >+ * LineTime / VRatioPreC; >+ if (DETBufferSizeInTimeChromaPre - UrgentLatency <= 0) { >+ *NotEnoughUrgentLatencyHidingPre = 1; >+ *UrgentBurstFactorChromaPre = 0; >+ } else { >+ *UrgentBurstFactorChromaPre = DETBufferSizeInTimeChromaPre >+ / (DETBufferSizeInTimeChromaPre - UrgentLatency); >+ } >+ } else { >+ *UrgentBurstFactorChromaPre = 1; >+ } >+ } >+} >+ >+static void CalculatePixelDeliveryTimes( >+ unsigned int NumberOfActivePlanes, >+ double VRatio[], >+ double VRatioPrefetchY[], >+ double VRatioPrefetchC[], >+ unsigned int swath_width_luma_ub[], >+ unsigned int swath_width_chroma_ub[], >+ int DPPPerPlane[], >+ double HRatio[], >+ double PixelClock[], >+ double PSCL_THROUGHPUT[], >+ double PSCL_THROUGHPUT_CHROMA[], >+ double DPPCLK[], >+ double BytePerPixelDETC[], >+ enum scan_direction_class SourceScan[], >+ unsigned int BlockWidth256BytesY[], >+ unsigned int BlockHeight256BytesY[], >+ unsigned int BlockWidth256BytesC[], >+ unsigned int BlockHeight256BytesC[], >+ double DisplayPipeLineDeliveryTimeLuma[], >+ double DisplayPipeLineDeliveryTimeChroma[], >+ double DisplayPipeLineDeliveryTimeLumaPrefetch[], >+ double DisplayPipeLineDeliveryTimeChromaPrefetch[], >+ double DisplayPipeRequestDeliveryTimeLuma[], >+ double DisplayPipeRequestDeliveryTimeChroma[], >+ double DisplayPipeRequestDeliveryTimeLumaPrefetch[], >+ double DisplayPipeRequestDeliveryTimeChromaPrefetch[]) >+{ >+ double req_per_swath_ub; >+ uint k; >+ >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (VRatio[k] <= 1) { >+ DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] >+ / HRatio[k] / PixelClock[k]; >+ } else { >+ DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] >+ / PSCL_THROUGHPUT[k] / DPPCLK[k]; >+ } >+ >+ if (BytePerPixelDETC[k] == 0) { >+ DisplayPipeLineDeliveryTimeChroma[k] = 0; >+ } else { >+ if (VRatio[k] / 2 <= 1) { >+ DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] >+ * DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k]; >+ } else { >+ DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] >+ / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; >+ } >+ } >+ >+ if (VRatioPrefetchY[k] <= 1) { >+ DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] >+ * DPPPerPlane[k] / HRatio[k] / PixelClock[k]; >+ } else { >+ DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] >+ / PSCL_THROUGHPUT[k] / DPPCLK[k]; >+ } >+ >+ if (BytePerPixelDETC[k] == 0) { >+ DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0; >+ } else { >+ if (VRatioPrefetchC[k] <= 1) { >+ DisplayPipeLineDeliveryTimeChromaPrefetch[k] = >+ swath_width_chroma_ub[k] * DPPPerPlane[k] >+ / (HRatio[k] / 2) / PixelClock[k]; >+ } else { >+ DisplayPipeLineDeliveryTimeChromaPrefetch[k] = >+ swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; >+ } >+ } >+ } >+ >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (SourceScan[k] == dm_horz) { >+ req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k]; >+ } else { >+ req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k]; >+ } >+ DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] >+ / req_per_swath_ub; >+ DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = >+ DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub; >+ if (BytePerPixelDETC[k] == 0) { >+ DisplayPipeRequestDeliveryTimeChroma[k] = 0; >+ DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0; >+ } else { >+ if (SourceScan[k] == dm_horz) { >+ req_per_swath_ub = swath_width_chroma_ub[k] >+ / BlockWidth256BytesC[k]; >+ } else { >+ req_per_swath_ub = swath_width_chroma_ub[k] >+ / BlockHeight256BytesC[k]; >+ } >+ DisplayPipeRequestDeliveryTimeChroma[k] = >+ DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub; >+ DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = >+ DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub; >+ } >+ } >+} >+ >+static void CalculateMetaAndPTETimes( >+ unsigned int NumberOfActivePlanes, >+ bool GPUVMEnable, >+ unsigned int MetaChunkSize, >+ unsigned int MinMetaChunkSizeBytes, >+ unsigned int GPUVMMaxPageTableLevels, >+ unsigned int HTotal[], >+ double VRatio[], >+ double VRatioPrefetchY[], >+ double VRatioPrefetchC[], >+ double DestinationLinesToRequestRowInVBlank[], >+ double DestinationLinesToRequestRowInImmediateFlip[], >+ double DestinationLinesToRequestVMInVBlank[], >+ double DestinationLinesToRequestVMInImmediateFlip[], >+ bool DCCEnable[], >+ double PixelClock[], >+ double BytePerPixelDETY[], >+ double BytePerPixelDETC[], >+ enum scan_direction_class SourceScan[], >+ unsigned int dpte_row_height[], >+ unsigned int dpte_row_height_chroma[], >+ unsigned int meta_row_width[], >+ unsigned int meta_row_height[], >+ unsigned int meta_req_width[], >+ unsigned int meta_req_height[], >+ long dpte_group_bytes[], >+ unsigned int PTERequestSizeY[], >+ unsigned int PTERequestSizeC[], >+ unsigned int PixelPTEReqWidthY[], >+ unsigned int PixelPTEReqHeightY[], >+ unsigned int PixelPTEReqWidthC[], >+ unsigned int PixelPTEReqHeightC[], >+ unsigned int dpte_row_width_luma_ub[], >+ unsigned int dpte_row_width_chroma_ub[], >+ unsigned int vm_group_bytes[], >+ unsigned int dpde0_bytes_per_frame_ub_l[], >+ unsigned int dpde0_bytes_per_frame_ub_c[], >+ unsigned int meta_pte_bytes_per_frame_ub_l[], >+ unsigned int meta_pte_bytes_per_frame_ub_c[], >+ double DST_Y_PER_PTE_ROW_NOM_L[], >+ double DST_Y_PER_PTE_ROW_NOM_C[], >+ double DST_Y_PER_META_ROW_NOM_L[], >+ double TimePerMetaChunkNominal[], >+ double TimePerMetaChunkVBlank[], >+ double TimePerMetaChunkFlip[], >+ double time_per_pte_group_nom_luma[], >+ double time_per_pte_group_vblank_luma[], >+ double time_per_pte_group_flip_luma[], >+ double time_per_pte_group_nom_chroma[], >+ double time_per_pte_group_vblank_chroma[], >+ double time_per_pte_group_flip_chroma[], >+ double TimePerVMGroupVBlank[], >+ double TimePerVMGroupFlip[], >+ double TimePerVMRequestVBlank[], >+ double TimePerVMRequestFlip[]) >+{ >+ unsigned int meta_chunk_width; >+ unsigned int min_meta_chunk_width; >+ unsigned int meta_chunk_per_row_int; >+ unsigned int meta_row_remainder; >+ unsigned int meta_chunk_threshold; >+ unsigned int meta_chunks_per_row_ub; >+ unsigned int dpte_group_width_luma; >+ unsigned int dpte_group_width_chroma; >+ unsigned int dpte_groups_per_row_luma_ub; >+ unsigned int dpte_groups_per_row_chroma_ub; >+ unsigned int num_group_per_lower_vm_stage; >+ unsigned int num_req_per_lower_vm_stage; >+ uint k; >+ >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (GPUVMEnable == true) { >+ DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k]; >+ if (BytePerPixelDETC[k] == 0) { >+ DST_Y_PER_PTE_ROW_NOM_C[k] = 0; >+ } else { >+ DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / (VRatio[k] / 2); >+ } >+ } else { >+ DST_Y_PER_PTE_ROW_NOM_L[k] = 0; >+ DST_Y_PER_PTE_ROW_NOM_C[k] = 0; >+ } >+ if (DCCEnable[k] == true) { >+ DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k]; >+ } else { >+ DST_Y_PER_META_ROW_NOM_L[k] = 0; >+ } >+ } >+ >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (DCCEnable[k] == true) { >+ meta_chunk_width = MetaChunkSize * 1024 * 256 >+ / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]; >+ min_meta_chunk_width = MinMetaChunkSizeBytes * 256 >+ / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]; >+ meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width; >+ meta_row_remainder = meta_row_width[k] % meta_chunk_width; >+ if (SourceScan[k] == dm_horz) { >+ meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; >+ } else { >+ meta_chunk_threshold = 2 * min_meta_chunk_width >+ - meta_req_height[k]; >+ } >+ if (meta_row_remainder <= meta_chunk_threshold) { >+ meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; >+ } else { >+ meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; >+ } >+ TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] >+ / PixelClock[k] / meta_chunks_per_row_ub; >+ TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] >+ * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; >+ TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] >+ * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; >+ } else { >+ TimePerMetaChunkNominal[k] = 0; >+ TimePerMetaChunkVBlank[k] = 0; >+ TimePerMetaChunkFlip[k] = 0; >+ } >+ } >+ >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (GPUVMEnable == true) { >+ if (SourceScan[k] == dm_horz) { >+ dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] >+ * PixelPTEReqWidthY[k]; >+ } else { >+ dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] >+ * PixelPTEReqHeightY[k]; >+ } >+ dpte_groups_per_row_luma_ub = dml_ceil( >+ dpte_row_width_luma_ub[k] / dpte_group_width_luma, >+ 1); >+ time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] >+ / PixelClock[k] / dpte_groups_per_row_luma_ub; >+ time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] >+ * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; >+ time_per_pte_group_flip_luma[k] = >+ DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] >+ / PixelClock[k] >+ / dpte_groups_per_row_luma_ub; >+ if (BytePerPixelDETC[k] == 0) { >+ time_per_pte_group_nom_chroma[k] = 0; >+ time_per_pte_group_vblank_chroma[k] = 0; >+ time_per_pte_group_flip_chroma[k] = 0; >+ } else { >+ if (SourceScan[k] == dm_horz) { >+ dpte_group_width_chroma = dpte_group_bytes[k] >+ / PTERequestSizeC[k] * PixelPTEReqWidthC[k]; >+ } else { >+ dpte_group_width_chroma = dpte_group_bytes[k] >+ / PTERequestSizeC[k] >+ * PixelPTEReqHeightC[k]; >+ } >+ dpte_groups_per_row_chroma_ub = dml_ceil( >+ dpte_row_width_chroma_ub[k] >+ / dpte_group_width_chroma, >+ 1); >+ time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] >+ * HTotal[k] / PixelClock[k] >+ / dpte_groups_per_row_chroma_ub; >+ time_per_pte_group_vblank_chroma[k] = >+ DestinationLinesToRequestRowInVBlank[k] * HTotal[k] >+ / PixelClock[k] >+ / dpte_groups_per_row_chroma_ub; >+ time_per_pte_group_flip_chroma[k] = >+ DestinationLinesToRequestRowInImmediateFlip[k] >+ * HTotal[k] / PixelClock[k] >+ / dpte_groups_per_row_chroma_ub; >+ } >+ } else { >+ time_per_pte_group_nom_luma[k] = 0; >+ time_per_pte_group_vblank_luma[k] = 0; >+ time_per_pte_group_flip_luma[k] = 0; >+ time_per_pte_group_nom_chroma[k] = 0; >+ time_per_pte_group_vblank_chroma[k] = 0; >+ time_per_pte_group_flip_chroma[k] = 0; >+ } >+ } >+ >+ for (k = 0; k < NumberOfActivePlanes; ++k) { >+ if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { >+ if (DCCEnable[k] == false) { >+ if (BytePerPixelDETC[k] > 0) { >+ num_group_per_lower_vm_stage = >+ dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) >+ + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); >+ } else { >+ num_group_per_lower_vm_stage = >+ dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); >+ } >+ } else { >+ if (GPUVMMaxPageTableLevels == 1) { >+ if (BytePerPixelDETC[k] > 0) { >+ num_group_per_lower_vm_stage = >+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) >+ + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); >+ } else { >+ num_group_per_lower_vm_stage = >+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); >+ } >+ } else { >+ if (BytePerPixelDETC[k] > 0) { >+ num_group_per_lower_vm_stage = >+ dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) >+ + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) >+ + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) >+ + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); >+ } else { >+ num_group_per_lower_vm_stage = >+ dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) >+ + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); >+ } >+ } >+ } >+ >+ if (DCCEnable[k] == false) { >+ if (BytePerPixelDETC[k] > 0) { >+ num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] >+ / 64 + dpde0_bytes_per_frame_ub_c[k] / 64; >+ } else { >+ num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] >+ / 64; >+ } >+ } else { >+ if (GPUVMMaxPageTableLevels == 1) { >+ if (BytePerPixelDETC[k] > 0) { >+ num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 >+ + meta_pte_bytes_per_frame_ub_c[k] / 64; >+ } else { >+ num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64; >+ } >+ } else { >+ if (BytePerPixelDETC[k] > 0) { >+ num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 >+ + dpde0_bytes_per_frame_ub_c[k] / 64 >+ + meta_pte_bytes_per_frame_ub_l[k] / 64 >+ + meta_pte_bytes_per_frame_ub_c[k] / 64; >+ } else { >+ num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 >+ + meta_pte_bytes_per_frame_ub_l[k] / 64; >+ } >+ } >+ } >+ >+ TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] >+ / PixelClock[k] / num_group_per_lower_vm_stage; >+ TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] >+ * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage; >+ TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] >+ * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage; >+ TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] >+ * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage; >+ >+ if (GPUVMMaxPageTableLevels > 2) { >+ TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2; >+ TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2; >+ TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2; >+ TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2; >+ } >+ >+ } else { >+ TimePerVMGroupVBlank[k] = 0; >+ TimePerVMGroupFlip[k] = 0; >+ TimePerVMRequestVBlank[k] = 0; >+ TimePerVMRequestFlip[k] = 0; >+ } >+ } >+} >+ >+static double CalculateExtraLatency( >+ double UrgentRoundTripAndOutOfOrderLatency, >+ int TotalNumberOfActiveDPP, >+ int PixelChunkSizeInKByte, >+ int TotalNumberOfDCCActiveDPP, >+ int MetaChunkSize, >+ double ReturnBW, >+ bool GPUVMEnable, >+ bool HostVMEnable, >+ int NumberOfActivePlanes, >+ int NumberOfDPP[], >+ long dpte_group_bytes[], >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, >+ double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, >+ int HostVMMaxPageTableLevels, >+ int HostVMCachedPageTableLevels) >+{ >+ double CalculateExtraLatency; >+ double HostVMInefficiencyFactor; >+ int HostVMDynamicLevels; >+ >+ if (GPUVMEnable && HostVMEnable) { >+ HostVMInefficiencyFactor = >+ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData >+ / PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; >+ HostVMDynamicLevels = HostVMMaxPageTableLevels - HostVMCachedPageTableLevels; >+ } else { >+ HostVMInefficiencyFactor = 1; >+ HostVMDynamicLevels = 0; >+ } >+ >+ CalculateExtraLatency = UrgentRoundTripAndOutOfOrderLatency >+ + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte >+ + TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0 >+ / ReturnBW; >+ >+ if (GPUVMEnable) { >+ int k; >+ >+ for (k = 0; k < NumberOfActivePlanes; k++) { >+ CalculateExtraLatency = CalculateExtraLatency >+ + NumberOfDPP[k] * dpte_group_bytes[k] >+ * (1 + 8 * HostVMDynamicLevels) >+ * HostVMInefficiencyFactor / ReturnBW; >+ } >+ } >+ return CalculateExtraLatency; >+} >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h 2019-08-31 15:01:11.868736169 -0500 >@@ -0,0 +1,32 @@ >+/* >+ * Copyright 2017 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef __DML21_DISPLAY_MODE_VBA_H__ >+#define __DML21_DISPLAY_MODE_VBA_H__ >+ >+void dml21_recalculate(struct display_mode_lib *mode_lib); >+void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib); >+ >+#endif /* _DML21_DISPLAY_MODE_VBA_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 2019-08-31 15:01:11.868736169 -0500 >@@ -0,0 +1,1823 @@ >+/* >+ * Copyright 2017 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifdef CONFIG_DRM_AMD_DC_DCN2_0 >+ >+#include "../display_mode_lib.h" >+#include "../display_mode_vba.h" >+#include "../dml_inline_defs.h" >+#include "display_rq_dlg_calc_21.h" >+ >+/* >+ * NOTE: >+ * This file is gcc-parseable HW gospel, coming straight from HW engineers. >+ * >+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd >+ * ways. Unless there is something clearly wrong with it the code should >+ * remain as-is as it provides us with a guarantee from HW that it is correct. >+ */ >+ >+static void calculate_ttu_cursor( >+ struct display_mode_lib *mode_lib, >+ double *refcyc_per_req_delivery_pre_cur, >+ double *refcyc_per_req_delivery_cur, >+ double refclk_freq_in_mhz, >+ double ref_freq_to_pix_freq, >+ double hscale_pixel_rate_l, >+ double hscl_ratio, >+ double vratio_pre_l, >+ double vratio_l, >+ unsigned int cur_width, >+ enum cursor_bpp cur_bpp); >+ >+static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) >+{ >+ unsigned int ret_val = 0; >+ >+ if (source_format == dm_444_16) { >+ if (!is_chroma) >+ ret_val = 2; >+ } else if (source_format == dm_444_32) { >+ if (!is_chroma) >+ ret_val = 4; >+ } else if (source_format == dm_444_64) { >+ if (!is_chroma) >+ ret_val = 8; >+ } else if (source_format == dm_420_8) { >+ if (is_chroma) >+ ret_val = 2; >+ else >+ ret_val = 1; >+ } else if (source_format == dm_420_10) { >+ if (is_chroma) >+ ret_val = 4; >+ else >+ ret_val = 2; >+ } else if (source_format == dm_444_8) { >+ ret_val = 1; >+ } >+ return ret_val; >+} >+ >+static bool is_dual_plane(enum source_format_class source_format) >+{ >+ bool ret_val = 0; >+ >+ if ((source_format == dm_420_8) || (source_format == dm_420_10)) >+ ret_val = 1; >+ >+ return ret_val; >+} >+ >+static double get_refcyc_per_delivery( >+ struct display_mode_lib *mode_lib, >+ double refclk_freq_in_mhz, >+ double pclk_freq_in_mhz, >+ bool odm_combine, >+ unsigned int recout_width, >+ unsigned int hactive, >+ double vratio, >+ double hscale_pixel_rate, >+ unsigned int delivery_width, >+ unsigned int req_per_swath_ub) >+{ >+ double refcyc_per_delivery = 0.0; >+ >+ if (vratio <= 1.0) { >+ if (odm_combine) >+ refcyc_per_delivery = (double) refclk_freq_in_mhz >+ * dml_min((double) recout_width, (double) hactive / 2.0) >+ / pclk_freq_in_mhz / (double) req_per_swath_ub; >+ else >+ refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width >+ / pclk_freq_in_mhz / (double) req_per_swath_ub; >+ } else { >+ refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width >+ / (double) hscale_pixel_rate / (double) req_per_swath_ub; >+ } >+ >+ dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); >+ dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); >+ dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); >+ dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); >+ >+ return refcyc_per_delivery; >+ >+} >+ >+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) >+{ >+ if (tile_size == dm_256k_tile) >+ return (256 * 1024); >+ else if (tile_size == dm_64k_tile) >+ return (64 * 1024); >+ else >+ return (4 * 1024); >+} >+ >+static void extract_rq_sizing_regs( >+ struct display_mode_lib *mode_lib, >+ display_data_rq_regs_st *rq_regs, >+ const display_data_rq_sizing_params_st rq_sizing) >+{ >+ dml_print("DML_DLG: %s: rq_sizing param\n", __func__); >+ print__data_rq_sizing_params_st(mode_lib, rq_sizing); >+ >+ rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; >+ >+ if (rq_sizing.min_chunk_bytes == 0) >+ rq_regs->min_chunk_size = 0; >+ else >+ rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; >+ >+ rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; >+ if (rq_sizing.min_meta_chunk_bytes == 0) >+ rq_regs->min_meta_chunk_size = 0; >+ else >+ rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; >+ >+ rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; >+ rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; >+} >+ >+static void extract_rq_regs( >+ struct display_mode_lib *mode_lib, >+ display_rq_regs_st *rq_regs, >+ const display_rq_params_st rq_param) >+{ >+ unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; >+ unsigned int detile_buf_plane1_addr = 0; >+ >+ extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); >+ >+ rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( >+ dml_log2(rq_param.dlg.rq_l.dpte_row_height), >+ 1) - 3; >+ >+ if (rq_param.yuv420) { >+ extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); >+ rq_regs->rq_regs_c.pte_row_height_linear = dml_floor( >+ dml_log2(rq_param.dlg.rq_c.dpte_row_height), >+ 1) - 3; >+ } >+ >+ rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); >+ rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); >+ >+ // FIXME: take the max between luma, chroma chunk size? >+ // okay for now, as we are setting chunk_bytes to 8kb anyways >+ if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb >+ rq_regs->drq_expansion_mode = 0; >+ } else { >+ rq_regs->drq_expansion_mode = 2; >+ } >+ rq_regs->prq_expansion_mode = 1; >+ rq_regs->mrq_expansion_mode = 1; >+ rq_regs->crq_expansion_mode = 1; >+ >+ if (rq_param.yuv420) { >+ if ((double) rq_param.misc.rq_l.stored_swath_bytes >+ / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { >+ detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma >+ } else { >+ detile_buf_plane1_addr = dml_round_to_multiple( >+ (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), >+ 256, >+ 0) / 64.0; // 2/3 to chroma >+ } >+ } >+ rq_regs->plane1_base_address = detile_buf_plane1_addr; >+} >+ >+static void handle_det_buf_split( >+ struct display_mode_lib *mode_lib, >+ display_rq_params_st *rq_param, >+ const display_pipe_source_params_st pipe_src_param) >+{ >+ unsigned int total_swath_bytes = 0; >+ unsigned int swath_bytes_l = 0; >+ unsigned int swath_bytes_c = 0; >+ unsigned int full_swath_bytes_packed_l = 0; >+ unsigned int full_swath_bytes_packed_c = 0; >+ bool req128_l = 0; >+ bool req128_c = 0; >+ bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); >+ bool surf_vert = (pipe_src_param.source_scan == dm_vert); >+ unsigned int log2_swath_height_l = 0; >+ unsigned int log2_swath_height_c = 0; >+ unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; >+ >+ full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; >+ full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; >+ >+ if (rq_param->yuv420_10bpc) { >+ full_swath_bytes_packed_l = dml_round_to_multiple( >+ rq_param->misc.rq_l.full_swath_bytes * 2 / 3, >+ 256, >+ 1) + 256; >+ full_swath_bytes_packed_c = dml_round_to_multiple( >+ rq_param->misc.rq_c.full_swath_bytes * 2 / 3, >+ 256, >+ 1) + 256; >+ } >+ >+ if (rq_param->yuv420) { >+ total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; >+ >+ if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request >+ req128_l = 0; >+ req128_c = 0; >+ swath_bytes_l = full_swath_bytes_packed_l; >+ swath_bytes_c = full_swath_bytes_packed_c; >+ } else { //128b request (for luma only for yuv420 8bpc) >+ req128_l = 1; >+ req128_c = 0; >+ swath_bytes_l = full_swath_bytes_packed_l / 2; >+ swath_bytes_c = full_swath_bytes_packed_c; >+ } >+ // Note: assumption, the config that pass in will fit into >+ // the detiled buffer. >+ } else { >+ total_swath_bytes = 2 * full_swath_bytes_packed_l; >+ >+ if (total_swath_bytes <= detile_buf_size_in_bytes) >+ req128_l = 0; >+ else >+ req128_l = 1; >+ >+ swath_bytes_l = total_swath_bytes; >+ swath_bytes_c = 0; >+ } >+ rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; >+ rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; >+ >+ if (surf_linear) { >+ log2_swath_height_l = 0; >+ log2_swath_height_c = 0; >+ } else if (!surf_vert) { >+ log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l; >+ log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c; >+ } else { >+ log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l; >+ log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c; >+ } >+ rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; >+ rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; >+ >+ dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); >+ dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); >+ dml_print( >+ "DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", >+ __func__, >+ full_swath_bytes_packed_l); >+ dml_print( >+ "DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", >+ __func__, >+ full_swath_bytes_packed_c); >+} >+ >+static void get_meta_and_pte_attr( >+ struct display_mode_lib *mode_lib, >+ display_data_rq_dlg_params_st *rq_dlg_param, >+ display_data_rq_misc_params_st *rq_misc_param, >+ display_data_rq_sizing_params_st *rq_sizing_param, >+ unsigned int vp_width, >+ unsigned int vp_height, >+ unsigned int data_pitch, >+ unsigned int meta_pitch, >+ unsigned int source_format, >+ unsigned int tiling, >+ unsigned int macro_tile_size, >+ unsigned int source_scan, >+ unsigned int hostvm_enable, >+ unsigned int is_chroma) >+{ >+ bool surf_linear = (tiling == dm_sw_linear); >+ bool surf_vert = (source_scan == dm_vert); >+ >+ unsigned int bytes_per_element; >+ unsigned int bytes_per_element_y = get_bytes_per_element( >+ (enum source_format_class) (source_format), >+ false); >+ unsigned int bytes_per_element_c = get_bytes_per_element( >+ (enum source_format_class) (source_format), >+ true); >+ >+ unsigned int blk256_width = 0; >+ unsigned int blk256_height = 0; >+ >+ unsigned int blk256_width_y = 0; >+ unsigned int blk256_height_y = 0; >+ unsigned int blk256_width_c = 0; >+ unsigned int blk256_height_c = 0; >+ unsigned int log2_bytes_per_element; >+ unsigned int log2_blk256_width; >+ unsigned int log2_blk256_height; >+ unsigned int blk_bytes; >+ unsigned int log2_blk_bytes; >+ unsigned int log2_blk_height; >+ unsigned int log2_blk_width; >+ unsigned int log2_meta_req_bytes; >+ unsigned int log2_meta_req_height; >+ unsigned int log2_meta_req_width; >+ unsigned int meta_req_width; >+ unsigned int meta_req_height; >+ unsigned int log2_meta_row_height; >+ unsigned int meta_row_width_ub; >+ unsigned int log2_meta_chunk_bytes; >+ unsigned int log2_meta_chunk_height; >+ >+ //full sized meta chunk width in unit of data elements >+ unsigned int log2_meta_chunk_width; >+ unsigned int log2_min_meta_chunk_bytes; >+ unsigned int min_meta_chunk_width; >+ unsigned int meta_chunk_width; >+ unsigned int meta_chunk_per_row_int; >+ unsigned int meta_row_remainder; >+ unsigned int meta_chunk_threshold; >+ unsigned int meta_blk_bytes; >+ unsigned int meta_blk_height; >+ unsigned int meta_blk_width; >+ unsigned int meta_surface_bytes; >+ unsigned int vmpg_bytes; >+ unsigned int meta_pte_req_per_frame_ub; >+ unsigned int meta_pte_bytes_per_frame_ub; >+ const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); >+ const unsigned int dpte_buf_in_pte_reqs = >+ mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma; >+ const unsigned int pde_proc_buffer_size_64k_reqs = >+ mode_lib->ip.pde_proc_buffer_size_64k_reqs; >+ >+ unsigned int log2_vmpg_height = 0; >+ unsigned int log2_vmpg_width = 0; >+ unsigned int log2_dpte_req_height_ptes = 0; >+ unsigned int log2_dpte_req_height = 0; >+ unsigned int log2_dpte_req_width = 0; >+ unsigned int log2_dpte_row_height_linear = 0; >+ unsigned int log2_dpte_row_height = 0; >+ unsigned int log2_dpte_group_width = 0; >+ unsigned int dpte_row_width_ub = 0; >+ unsigned int dpte_req_height = 0; >+ unsigned int dpte_req_width = 0; >+ unsigned int dpte_group_width = 0; >+ unsigned int log2_dpte_group_bytes = 0; >+ unsigned int log2_dpte_group_length = 0; >+ unsigned int pde_buf_entries; >+ bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10); >+ >+ Calculate256BBlockSizes( >+ (enum source_format_class) (source_format), >+ (enum dm_swizzle_mode) (tiling), >+ bytes_per_element_y, >+ bytes_per_element_c, >+ &blk256_height_y, >+ &blk256_height_c, >+ &blk256_width_y, >+ &blk256_width_c); >+ >+ if (!is_chroma) { >+ blk256_width = blk256_width_y; >+ blk256_height = blk256_height_y; >+ bytes_per_element = bytes_per_element_y; >+ } else { >+ blk256_width = blk256_width_c; >+ blk256_height = blk256_height_c; >+ bytes_per_element = bytes_per_element_c; >+ } >+ >+ log2_bytes_per_element = dml_log2(bytes_per_element); >+ >+ dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); >+ dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); >+ dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); >+ dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); >+ >+ log2_blk256_width = dml_log2((double) blk256_width); >+ log2_blk256_height = dml_log2((double) blk256_height); >+ blk_bytes = surf_linear ? >+ 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); >+ log2_blk_bytes = dml_log2((double) blk_bytes); >+ log2_blk_height = 0; >+ log2_blk_width = 0; >+ >+ // remember log rule >+ // "+" in log is multiply >+ // "-" in log is divide >+ // "/2" is like square root >+ // blk is vertical biased >+ if (tiling != dm_sw_linear) >+ log2_blk_height = log2_blk256_height >+ + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); >+ else >+ log2_blk_height = 0; // blk height of 1 >+ >+ log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; >+ >+ if (!surf_vert) { >+ rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) >+ + blk256_width; >+ rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; >+ } else { >+ rq_dlg_param->swath_width_ub = dml_round_to_multiple( >+ vp_height - 1, >+ blk256_height, >+ 1) + blk256_height; >+ rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; >+ } >+ >+ if (!surf_vert) >+ rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height >+ * bytes_per_element; >+ else >+ rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width >+ * bytes_per_element; >+ >+ rq_misc_param->blk256_height = blk256_height; >+ rq_misc_param->blk256_width = blk256_width; >+ >+ // ------- >+ // meta >+ // ------- >+ log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element >+ >+ // each 64b meta request for dcn is 8x8 meta elements and >+ // a meta element covers one 256b block of the the data surface. >+ log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 >+ log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element >+ - log2_meta_req_height; >+ meta_req_width = 1 << log2_meta_req_width; >+ meta_req_height = 1 << log2_meta_req_height; >+ log2_meta_row_height = 0; >+ meta_row_width_ub = 0; >+ >+ // the dimensions of a meta row are meta_row_width x meta_row_height in elements. >+ // calculate upper bound of the meta_row_width >+ if (!surf_vert) { >+ log2_meta_row_height = log2_meta_req_height; >+ meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) >+ + meta_req_width; >+ rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; >+ } else { >+ log2_meta_row_height = log2_meta_req_width; >+ meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) >+ + meta_req_height; >+ rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; >+ } >+ rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; >+ >+ rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; >+ >+ log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); >+ log2_meta_chunk_height = log2_meta_row_height; >+ >+ //full sized meta chunk width in unit of data elements >+ log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element >+ - log2_meta_chunk_height; >+ log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); >+ min_meta_chunk_width = 1 >+ << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element >+ - log2_meta_chunk_height); >+ meta_chunk_width = 1 << log2_meta_chunk_width; >+ meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); >+ meta_row_remainder = meta_row_width_ub % meta_chunk_width; >+ meta_chunk_threshold = 0; >+ meta_blk_bytes = 4096; >+ meta_blk_height = blk256_height * 64; >+ meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; >+ meta_surface_bytes = meta_pitch >+ * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) >+ + meta_blk_height) * bytes_per_element / 256; >+ vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; >+ meta_pte_req_per_frame_ub = (dml_round_to_multiple( >+ meta_surface_bytes - vmpg_bytes, >+ 8 * vmpg_bytes, >+ 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); >+ meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request >+ rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; >+ >+ dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); >+ dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width); >+ dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); >+ dml_print( >+ "DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", >+ __func__, >+ meta_pte_req_per_frame_ub); >+ dml_print( >+ "DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", >+ __func__, >+ meta_pte_bytes_per_frame_ub); >+ >+ if (!surf_vert) >+ meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; >+ else >+ meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; >+ >+ if (meta_row_remainder <= meta_chunk_threshold) >+ rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; >+ else >+ rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; >+ >+ // ------ >+ // dpte >+ // ------ >+ if (surf_linear) { >+ log2_vmpg_height = 0; // one line high >+ } else { >+ log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; >+ } >+ log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; >+ >+ // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. >+ if (surf_linear) { //one 64B PTE request returns 8 PTEs >+ log2_dpte_req_height_ptes = 0; >+ log2_dpte_req_width = log2_vmpg_width + 3; >+ log2_dpte_req_height = 0; >+ } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size >+ //one 64B req gives 8x1 PTEs for 4KB tile >+ log2_dpte_req_height_ptes = 0; >+ log2_dpte_req_width = log2_blk_width + 3; >+ log2_dpte_req_height = log2_blk_height + 0; >+ } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB >+ //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB >+ log2_dpte_req_height_ptes = 4; >+ log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width >+ log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height >+ } else { //64KB page size and must 64KB tile block >+ //one 64B req gives 8x1 PTEs for 64KB tile >+ log2_dpte_req_height_ptes = 0; >+ log2_dpte_req_width = log2_blk_width + 3; >+ log2_dpte_req_height = log2_blk_height + 0; >+ } >+ >+ // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height >+ // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent >+ // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) >+ //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; >+ //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; >+ dpte_req_height = 1 << log2_dpte_req_height; >+ dpte_req_width = 1 << log2_dpte_req_width; >+ >+ // calculate pitch dpte row buffer can hold >+ // round the result down to a power of two. >+ pde_buf_entries = >+ yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; >+ if (surf_linear) { >+ unsigned int dpte_row_height; >+ >+ log2_dpte_row_height_linear = dml_floor( >+ dml_log2( >+ dml_min( >+ 64 * 1024 * pde_buf_entries >+ / bytes_per_element, >+ dpte_buf_in_pte_reqs >+ * dpte_req_width) >+ / data_pitch), >+ 1); >+ >+ ASSERT(log2_dpte_row_height_linear >= 3); >+ >+ if (log2_dpte_row_height_linear > 7) >+ log2_dpte_row_height_linear = 7; >+ >+ log2_dpte_row_height = log2_dpte_row_height_linear; >+ // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. >+ // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. >+ dpte_row_height = 1 << log2_dpte_row_height; >+ dpte_row_width_ub = dml_round_to_multiple( >+ data_pitch * dpte_row_height - 1, >+ dpte_req_width, >+ 1) + dpte_req_width; >+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; >+ } else { >+ // the upper bound of the dpte_row_width without dependency on viewport position follows. >+ // for tiled mode, row height is the same as req height and row store up to vp size upper bound >+ if (!surf_vert) { >+ log2_dpte_row_height = log2_dpte_req_height; >+ dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) >+ + dpte_req_width; >+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; >+ } else { >+ log2_dpte_row_height = >+ (log2_blk_width < log2_dpte_req_width) ? >+ log2_blk_width : log2_dpte_req_width; >+ dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) >+ + dpte_req_height; >+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; >+ } >+ } >+ if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB >+ rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request >+ else >+ rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request >+ >+ rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; >+ >+ // the dpte_group_bytes is reduced for the specific case of vertical >+ // access of a tile surface that has dpte request of 8x1 ptes. >+ >+ if (hostvm_enable) >+ rq_sizing_param->dpte_group_bytes = 512; >+ else { >+ if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group >+ rq_sizing_param->dpte_group_bytes = 512; >+ else >+ //full size >+ rq_sizing_param->dpte_group_bytes = 2048; >+ } >+ >+ //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. >+ log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); >+ log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests >+ >+ // full sized data pte group width in elements >+ if (!surf_vert) >+ log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; >+ else >+ log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; >+ >+ //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B >+ if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB >+ log2_dpte_group_width = log2_dpte_group_width - 1; >+ >+ dpte_group_width = 1 << log2_dpte_group_width; >+ >+ // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, >+ // the upper bound for the dpte groups per row is as follows. >+ rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( >+ (double) dpte_row_width_ub / dpte_group_width, >+ 1); >+} >+ >+static void get_surf_rq_param( >+ struct display_mode_lib *mode_lib, >+ display_data_rq_sizing_params_st *rq_sizing_param, >+ display_data_rq_dlg_params_st *rq_dlg_param, >+ display_data_rq_misc_params_st *rq_misc_param, >+ const display_pipe_params_st pipe_param, >+ bool is_chroma) >+{ >+ bool mode_422 = 0; >+ unsigned int vp_width = 0; >+ unsigned int vp_height = 0; >+ unsigned int data_pitch = 0; >+ unsigned int meta_pitch = 0; >+ unsigned int ppe = mode_422 ? 2 : 1; >+ >+ // FIXME check if ppe apply for both luma and chroma in 422 case >+ if (is_chroma) { >+ vp_width = pipe_param.src.viewport_width_c / ppe; >+ vp_height = pipe_param.src.viewport_height_c; >+ data_pitch = pipe_param.src.data_pitch_c; >+ meta_pitch = pipe_param.src.meta_pitch_c; >+ } else { >+ vp_width = pipe_param.src.viewport_width / ppe; >+ vp_height = pipe_param.src.viewport_height; >+ data_pitch = pipe_param.src.data_pitch; >+ meta_pitch = pipe_param.src.meta_pitch; >+ } >+ >+ if (pipe_param.dest.odm_combine) { >+ unsigned int access_dir; >+ unsigned int full_src_vp_width; >+ unsigned int hactive_half; >+ unsigned int src_hactive_half; >+ access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed >+ hactive_half = pipe_param.dest.hactive / 2; >+ if (is_chroma) { >+ full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width; >+ src_hactive_half = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half; >+ } else { >+ full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width; >+ src_hactive_half = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half; >+ } >+ >+ if (access_dir == 0) { >+ vp_width = dml_min(full_src_vp_width, src_hactive_half); >+ dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); >+ } else { >+ vp_height = dml_min(full_src_vp_width, src_hactive_half); >+ dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); >+ >+ } >+ dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width); >+ dml_print("DML_DLG: %s: hactive_half = %d\n", __func__, hactive_half); >+ dml_print("DML_DLG: %s: src_hactive_half = %d\n", __func__, src_hactive_half); >+ } >+ rq_sizing_param->chunk_bytes = 8192; >+ >+ if (rq_sizing_param->chunk_bytes == 64 * 1024) >+ rq_sizing_param->min_chunk_bytes = 0; >+ else >+ rq_sizing_param->min_chunk_bytes = 1024; >+ >+ rq_sizing_param->meta_chunk_bytes = 2048; >+ rq_sizing_param->min_meta_chunk_bytes = 256; >+ >+ if (pipe_param.src.hostvm) >+ rq_sizing_param->mpte_group_bytes = 512; >+ else >+ rq_sizing_param->mpte_group_bytes = 2048; >+ >+ get_meta_and_pte_attr( >+ mode_lib, >+ rq_dlg_param, >+ rq_misc_param, >+ rq_sizing_param, >+ vp_width, >+ vp_height, >+ data_pitch, >+ meta_pitch, >+ pipe_param.src.source_format, >+ pipe_param.src.sw_mode, >+ pipe_param.src.macro_tile_size, >+ pipe_param.src.source_scan, >+ pipe_param.src.hostvm, >+ is_chroma); >+} >+ >+static void dml_rq_dlg_get_rq_params( >+ struct display_mode_lib *mode_lib, >+ display_rq_params_st *rq_param, >+ const display_pipe_params_st pipe_param) >+{ >+ // get param for luma surface >+ rq_param->yuv420 = pipe_param.src.source_format == dm_420_8 >+ || pipe_param.src.source_format == dm_420_10; >+ rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10; >+ >+ get_surf_rq_param( >+ mode_lib, >+ &(rq_param->sizing.rq_l), >+ &(rq_param->dlg.rq_l), >+ &(rq_param->misc.rq_l), >+ pipe_param, >+ 0); >+ >+ if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) { >+ // get param for chroma surface >+ get_surf_rq_param( >+ mode_lib, >+ &(rq_param->sizing.rq_c), >+ &(rq_param->dlg.rq_c), >+ &(rq_param->misc.rq_c), >+ pipe_param, >+ 1); >+ } >+ >+ // calculate how to split the det buffer space between luma and chroma >+ handle_det_buf_split(mode_lib, rq_param, pipe_param.src); >+ print__rq_params_st(mode_lib, *rq_param); >+} >+ >+void dml21_rq_dlg_get_rq_reg( >+ struct display_mode_lib *mode_lib, >+ display_rq_regs_st *rq_regs, >+ const display_pipe_params_st pipe_param) >+{ >+ display_rq_params_st rq_param = {0}; >+ >+ memset(rq_regs, 0, sizeof(*rq_regs)); >+ dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); >+ extract_rq_regs(mode_lib, rq_regs, rq_param); >+ >+ print__rq_regs_st(mode_lib, *rq_regs); >+} >+ >+// Note: currently taken in as is. >+// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. >+static void dml_rq_dlg_get_dlg_params( >+ struct display_mode_lib *mode_lib, >+ const display_e2e_pipe_params_st *e2e_pipe_param, >+ const unsigned int num_pipes, >+ const unsigned int pipe_idx, >+ display_dlg_regs_st *disp_dlg_regs, >+ display_ttu_regs_st *disp_ttu_regs, >+ const display_rq_dlg_params_st rq_dlg_param, >+ const display_dlg_sys_params_st dlg_sys_param, >+ const bool cstate_en, >+ const bool pstate_en) >+{ >+ const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; >+ const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; >+ const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; >+ const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; >+ const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; >+ const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; >+ >+ // ------------------------- >+ // Section 1.15.2.1: OTG dependent Params >+ // ------------------------- >+ // Timing >+ unsigned int htotal = dst->htotal; >+ // unsigned int hblank_start = dst.hblank_start; // TODO: Remove >+ unsigned int hblank_end = dst->hblank_end; >+ unsigned int vblank_start = dst->vblank_start; >+ unsigned int vblank_end = dst->vblank_end; >+ unsigned int min_vblank = mode_lib->ip.min_vblank_lines; >+ >+ double dppclk_freq_in_mhz = clks->dppclk_mhz; >+ double dispclk_freq_in_mhz = clks->dispclk_mhz; >+ double refclk_freq_in_mhz = clks->refclk_mhz; >+ double pclk_freq_in_mhz = dst->pixel_rate_mhz; >+ bool interlaced = dst->interlaced; >+ >+ double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; >+ >+ double min_dcfclk_mhz; >+ double t_calc_us; >+ double min_ttu_vblank; >+ >+ double min_dst_y_ttu_vblank; >+ unsigned int dlg_vblank_start; >+ bool dual_plane; >+ bool mode_422; >+ unsigned int access_dir; >+ unsigned int vp_height_l; >+ unsigned int vp_width_l; >+ unsigned int vp_height_c; >+ unsigned int vp_width_c; >+ >+ // Scaling >+ unsigned int htaps_l; >+ unsigned int htaps_c; >+ double hratio_l; >+ double hratio_c; >+ double vratio_l; >+ double vratio_c; >+ bool scl_enable; >+ >+ double line_time_in_us; >+ // double vinit_l; >+ // double vinit_c; >+ // double vinit_bot_l; >+ // double vinit_bot_c; >+ >+ // unsigned int swath_height_l; >+ unsigned int swath_width_ub_l; >+ // unsigned int dpte_bytes_per_row_ub_l; >+ unsigned int dpte_groups_per_row_ub_l; >+ // unsigned int meta_pte_bytes_per_frame_ub_l; >+ // unsigned int meta_bytes_per_row_ub_l; >+ >+ // unsigned int swath_height_c; >+ unsigned int swath_width_ub_c; >+ // unsigned int dpte_bytes_per_row_ub_c; >+ unsigned int dpte_groups_per_row_ub_c; >+ >+ unsigned int meta_chunks_per_row_ub_l; >+ unsigned int meta_chunks_per_row_ub_c; >+ unsigned int vupdate_offset; >+ unsigned int vupdate_width; >+ unsigned int vready_offset; >+ >+ unsigned int dppclk_delay_subtotal; >+ unsigned int dispclk_delay_subtotal; >+ unsigned int pixel_rate_delay_subtotal; >+ >+ unsigned int vstartup_start; >+ unsigned int dst_x_after_scaler; >+ unsigned int dst_y_after_scaler; >+ double line_wait; >+ double dst_y_prefetch; >+ double dst_y_per_vm_vblank; >+ double dst_y_per_row_vblank; >+ double dst_y_per_vm_flip; >+ double dst_y_per_row_flip; >+ double max_dst_y_per_vm_vblank; >+ double max_dst_y_per_row_vblank; >+ double lsw; >+ double vratio_pre_l; >+ double vratio_pre_c; >+ unsigned int req_per_swath_ub_l; >+ unsigned int req_per_swath_ub_c; >+ unsigned int meta_row_height_l; >+ unsigned int meta_row_height_c; >+ unsigned int swath_width_pixels_ub_l; >+ unsigned int swath_width_pixels_ub_c; >+ unsigned int scaler_rec_in_width_l; >+ unsigned int scaler_rec_in_width_c; >+ unsigned int dpte_row_height_l; >+ unsigned int dpte_row_height_c; >+ double hscale_pixel_rate_l; >+ double hscale_pixel_rate_c; >+ double min_hratio_fact_l; >+ double min_hratio_fact_c; >+ double refcyc_per_line_delivery_pre_l; >+ double refcyc_per_line_delivery_pre_c; >+ double refcyc_per_line_delivery_l; >+ double refcyc_per_line_delivery_c; >+ >+ double refcyc_per_req_delivery_pre_l; >+ double refcyc_per_req_delivery_pre_c; >+ double refcyc_per_req_delivery_l; >+ double refcyc_per_req_delivery_c; >+ >+ unsigned int full_recout_width; >+ double xfc_transfer_delay; >+ double xfc_precharge_delay; >+ double xfc_remote_surface_flip_latency; >+ double xfc_dst_y_delta_drq_limit; >+ double xfc_prefetch_margin; >+ double refcyc_per_req_delivery_pre_cur0; >+ double refcyc_per_req_delivery_cur0; >+ double refcyc_per_req_delivery_pre_cur1; >+ double refcyc_per_req_delivery_cur1; >+ >+ memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); >+ memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); >+ >+ dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); >+ dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); >+ >+ dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); >+ dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); >+ ASSERT(ref_freq_to_pix_freq < 4.0); >+ >+ disp_dlg_regs->ref_freq_to_pix_freq = >+ (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); >+ disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal >+ * dml_pow(2, 8)); >+ disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits >+ disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end >+ * (double) ref_freq_to_pix_freq); >+ ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); >+ >+ min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; >+ t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); >+ min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; >+ dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; >+ >+ disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); >+ ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); >+ >+ dml_print( >+ "DML_DLG: %s: min_dcfclk_mhz = %3.2f\n", >+ __func__, >+ min_dcfclk_mhz); >+ dml_print( >+ "DML_DLG: %s: min_ttu_vblank = %3.2f\n", >+ __func__, >+ min_ttu_vblank); >+ dml_print( >+ "DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n", >+ __func__, >+ min_dst_y_ttu_vblank); >+ dml_print( >+ "DML_DLG: %s: t_calc_us = %3.2f\n", >+ __func__, >+ t_calc_us); >+ dml_print( >+ "DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n", >+ __func__, >+ disp_dlg_regs->min_dst_y_next_start); >+ dml_print( >+ "DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", >+ __func__, >+ ref_freq_to_pix_freq); >+ >+ // ------------------------- >+ // Section 1.15.2.2: Prefetch, Active and TTU >+ // ------------------------- >+ // Prefetch Calc >+ // Source >+ // dcc_en = src.dcc; >+ dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); >+ mode_422 = 0; // FIXME >+ access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed >+ // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); >+ // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); >+ vp_height_l = src->viewport_height; >+ vp_width_l = src->viewport_width; >+ vp_height_c = src->viewport_height_c; >+ vp_width_c = src->viewport_width_c; >+ >+ // Scaling >+ htaps_l = taps->htaps; >+ htaps_c = taps->htaps_c; >+ hratio_l = scl->hscl_ratio; >+ hratio_c = scl->hscl_ratio_c; >+ vratio_l = scl->vscl_ratio; >+ vratio_c = scl->vscl_ratio_c; >+ scl_enable = scl->scl_enable; >+ >+ line_time_in_us = (htotal / pclk_freq_in_mhz); >+ swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; >+ dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; >+ swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; >+ dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; >+ >+ meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; >+ meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; >+ vupdate_offset = dst->vupdate_offset; >+ vupdate_width = dst->vupdate_width; >+ vready_offset = dst->vready_offset; >+ >+ dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; >+ dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; >+ >+ if (scl_enable) >+ dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; >+ else >+ dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; >+ >+ dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter >+ + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; >+ >+ if (dout->dsc_enable) { >+ double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ dispclk_delay_subtotal += dsc_delay; >+ } >+ >+ pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz >+ + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; >+ >+ vstartup_start = dst->vstartup_start; >+ if (interlaced) { >+ if (vstartup_start / 2.0 >+ - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal >+ <= vblank_end / 2.0) >+ disp_dlg_regs->vready_after_vcount0 = 1; >+ else >+ disp_dlg_regs->vready_after_vcount0 = 0; >+ } else { >+ if (vstartup_start >+ - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal >+ <= vblank_end) >+ disp_dlg_regs->vready_after_vcount0 = 1; >+ else >+ disp_dlg_regs->vready_after_vcount0 = 0; >+ } >+ >+ // TODO: Where is this coming from? >+ if (interlaced) >+ vstartup_start = vstartup_start / 2; >+ >+ // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? >+ if (vstartup_start >= min_vblank) { >+ dml_print( >+ "WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n", >+ __func__, >+ vblank_start, >+ vblank_end); >+ dml_print( >+ "WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", >+ __func__, >+ vstartup_start, >+ min_vblank); >+ min_vblank = vstartup_start + 1; >+ dml_print( >+ "WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", >+ __func__, >+ vstartup_start, >+ min_vblank); >+ } >+ >+ dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); >+ dml_print( >+ "DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", >+ __func__, >+ pixel_rate_delay_subtotal); >+ dml_print( >+ "DML_DLG: %s: dst_x_after_scaler = %d\n", >+ __func__, >+ dst_x_after_scaler); >+ dml_print( >+ "DML_DLG: %s: dst_y_after_scaler = %d\n", >+ __func__, >+ dst_y_after_scaler); >+ >+ // Lwait >+ // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? >+ line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us; >+ if (cstate_en) >+ line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); >+ if (pstate_en) >+ line_wait = dml_max( >+ mode_lib->soc.dram_clock_change_latency_us >+ + mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? >+ line_wait); >+ line_wait = line_wait / line_time_in_us; >+ >+ dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); >+ >+ dst_y_per_vm_vblank = get_dst_y_per_vm_vblank( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ dst_y_per_row_vblank = get_dst_y_per_row_vblank( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ max_dst_y_per_vm_vblank = 32.0; >+ max_dst_y_per_row_vblank = 16.0; >+ >+ // magic! >+ if (htotal <= 75) { >+ min_vblank = 300; >+ max_dst_y_per_vm_vblank = 100.0; >+ max_dst_y_per_row_vblank = 100.0; >+ } >+ >+ dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip); >+ dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip); >+ dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); >+ dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); >+ >+ ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); >+ ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); >+ >+ ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); >+ lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); >+ >+ dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw); >+ >+ vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ >+ dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l); >+ dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); >+ >+ // Active >+ req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; >+ req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; >+ meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; >+ meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; >+ swath_width_pixels_ub_l = 0; >+ swath_width_pixels_ub_c = 0; >+ scaler_rec_in_width_l = 0; >+ scaler_rec_in_width_c = 0; >+ dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; >+ dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; >+ >+ if (mode_422) { >+ swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element >+ swath_width_pixels_ub_c = swath_width_ub_c * 2; >+ } else { >+ swath_width_pixels_ub_l = swath_width_ub_l * 1; >+ swath_width_pixels_ub_c = swath_width_ub_c * 1; >+ } >+ >+ hscale_pixel_rate_l = 0.; >+ hscale_pixel_rate_c = 0.; >+ min_hratio_fact_l = 1.0; >+ min_hratio_fact_c = 1.0; >+ >+ if (htaps_l <= 1) >+ min_hratio_fact_l = 2.0; >+ else if (htaps_l <= 6) { >+ if ((hratio_l * 2.0) > 4.0) >+ min_hratio_fact_l = 4.0; >+ else >+ min_hratio_fact_l = hratio_l * 2.0; >+ } else { >+ if (hratio_l > 4.0) >+ min_hratio_fact_l = 4.0; >+ else >+ min_hratio_fact_l = hratio_l; >+ } >+ >+ hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; >+ >+ if (htaps_c <= 1) >+ min_hratio_fact_c = 2.0; >+ else if (htaps_c <= 6) { >+ if ((hratio_c * 2.0) > 4.0) >+ min_hratio_fact_c = 4.0; >+ else >+ min_hratio_fact_c = hratio_c * 2.0; >+ } else { >+ if (hratio_c > 4.0) >+ min_hratio_fact_c = 4.0; >+ else >+ min_hratio_fact_c = hratio_c; >+ } >+ >+ hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; >+ >+ refcyc_per_line_delivery_pre_l = 0.; >+ refcyc_per_line_delivery_pre_c = 0.; >+ refcyc_per_line_delivery_l = 0.; >+ refcyc_per_line_delivery_c = 0.; >+ >+ refcyc_per_req_delivery_pre_l = 0.; >+ refcyc_per_req_delivery_pre_c = 0.; >+ refcyc_per_req_delivery_l = 0.; >+ refcyc_per_req_delivery_c = 0.; >+ >+ full_recout_width = 0; >+ // In ODM >+ if (src->is_hsplit) { >+ // This "hack" is only allowed (and valid) for MPC combine. In ODM >+ // combine, you MUST specify the full_recout_width...according to Oswin >+ if (dst->full_recout_width == 0 && !dst->odm_combine) { >+ dml_print( >+ "DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", >+ __func__); >+ full_recout_width = dst->recout_width * 2; // assume half split for dcn1 >+ } else >+ full_recout_width = dst->full_recout_width; >+ } else >+ full_recout_width = dst->recout_width; >+ >+ // As of DCN2, mpc_combine and odm_combine are mutually exclusive >+ refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( >+ mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_pre_l, >+ hscale_pixel_rate_l, >+ swath_width_pixels_ub_l, >+ 1); // per line >+ >+ refcyc_per_line_delivery_l = get_refcyc_per_delivery( >+ mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_l, >+ hscale_pixel_rate_l, >+ swath_width_pixels_ub_l, >+ 1); // per line >+ >+ dml_print("DML_DLG: %s: full_recout_width = %d\n", __func__, full_recout_width); >+ dml_print( >+ "DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", >+ __func__, >+ hscale_pixel_rate_l); >+ dml_print( >+ "DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", >+ __func__, >+ refcyc_per_line_delivery_pre_l); >+ dml_print( >+ "DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", >+ __func__, >+ refcyc_per_line_delivery_l); >+ >+ if (dual_plane) { >+ refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery( >+ mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_pre_c, >+ hscale_pixel_rate_c, >+ swath_width_pixels_ub_c, >+ 1); // per line >+ >+ refcyc_per_line_delivery_c = get_refcyc_per_delivery( >+ mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_c, >+ hscale_pixel_rate_c, >+ swath_width_pixels_ub_c, >+ 1); // per line >+ >+ dml_print( >+ "DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", >+ __func__, >+ refcyc_per_line_delivery_pre_c); >+ dml_print( >+ "DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", >+ __func__, >+ refcyc_per_line_delivery_c); >+ } >+ >+ // TTU - Luma / Chroma >+ if (access_dir) { // vertical access >+ scaler_rec_in_width_l = vp_height_l; >+ scaler_rec_in_width_c = vp_height_c; >+ } else { >+ scaler_rec_in_width_l = vp_width_l; >+ scaler_rec_in_width_c = vp_width_c; >+ } >+ >+ refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery( >+ mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_pre_l, >+ hscale_pixel_rate_l, >+ scaler_rec_in_width_l, >+ req_per_swath_ub_l); // per req >+ refcyc_per_req_delivery_l = get_refcyc_per_delivery( >+ mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_l, >+ hscale_pixel_rate_l, >+ scaler_rec_in_width_l, >+ req_per_swath_ub_l); // per req >+ >+ dml_print( >+ "DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", >+ __func__, >+ refcyc_per_req_delivery_pre_l); >+ dml_print( >+ "DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", >+ __func__, >+ refcyc_per_req_delivery_l); >+ >+ ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); >+ ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); >+ >+ if (dual_plane) { >+ refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery( >+ mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_pre_c, >+ hscale_pixel_rate_c, >+ scaler_rec_in_width_c, >+ req_per_swath_ub_c); // per req >+ refcyc_per_req_delivery_c = get_refcyc_per_delivery( >+ mode_lib, >+ refclk_freq_in_mhz, >+ pclk_freq_in_mhz, >+ dst->odm_combine, >+ full_recout_width, >+ dst->hactive, >+ vratio_c, >+ hscale_pixel_rate_c, >+ scaler_rec_in_width_c, >+ req_per_swath_ub_c); // per req >+ >+ dml_print( >+ "DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", >+ __func__, >+ refcyc_per_req_delivery_pre_c); >+ dml_print( >+ "DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", >+ __func__, >+ refcyc_per_req_delivery_c); >+ >+ ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); >+ ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); >+ } >+ >+ // XFC >+ xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); >+ xfc_precharge_delay = get_xfc_precharge_delay( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency; >+ xfc_prefetch_margin = get_xfc_prefetch_margin( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx); >+ >+ // TTU - Cursor >+ refcyc_per_req_delivery_pre_cur0 = 0.0; >+ refcyc_per_req_delivery_cur0 = 0.0; >+ if (src->num_cursors > 0) { >+ calculate_ttu_cursor( >+ mode_lib, >+ &refcyc_per_req_delivery_pre_cur0, >+ &refcyc_per_req_delivery_cur0, >+ refclk_freq_in_mhz, >+ ref_freq_to_pix_freq, >+ hscale_pixel_rate_l, >+ scl->hscl_ratio, >+ vratio_pre_l, >+ vratio_l, >+ src->cur0_src_width, >+ (enum cursor_bpp) (src->cur0_bpp)); >+ } >+ >+ refcyc_per_req_delivery_pre_cur1 = 0.0; >+ refcyc_per_req_delivery_cur1 = 0.0; >+ if (src->num_cursors > 1) { >+ calculate_ttu_cursor( >+ mode_lib, >+ &refcyc_per_req_delivery_pre_cur1, >+ &refcyc_per_req_delivery_cur1, >+ refclk_freq_in_mhz, >+ ref_freq_to_pix_freq, >+ hscale_pixel_rate_l, >+ scl->hscl_ratio, >+ vratio_pre_l, >+ vratio_l, >+ src->cur1_src_width, >+ (enum cursor_bpp) (src->cur1_bpp)); >+ } >+ >+ // TTU - Misc >+ // all hard-coded >+ >+ // Assignment to register structures >+ disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line >+ disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk >+ ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); >+ disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); >+ disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); >+ disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); >+ disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); >+ disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); >+ >+ disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); >+ disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); >+ >+ dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank); >+ dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank); >+ dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip); >+ dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip); >+ >+ disp_dlg_regs->refcyc_per_pte_group_vblank_l = >+ (unsigned int) (dst_y_per_row_vblank * (double) htotal >+ * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); >+ ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); >+ >+ if (dual_plane) { >+ disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank >+ * (double) htotal * ref_freq_to_pix_freq >+ / (double) dpte_groups_per_row_ub_c); >+ ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c >+ < (unsigned int)dml_pow(2, 13)); >+ } >+ >+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = >+ (unsigned int) (dst_y_per_row_vblank * (double) htotal >+ * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); >+ ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); >+ >+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = >+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now >+ >+ disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal >+ * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; >+ disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal >+ * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; >+ >+ if (dual_plane) { >+ disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip >+ * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; >+ disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip >+ * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; >+ } >+ >+ disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; >+ disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; >+ disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;; >+ disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;; >+ >+ // Clamp to max for now >+ if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; >+ >+ if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; >+ >+ if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; >+ >+ if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; >+ disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l >+ / (double) vratio_l * dml_pow(2, 2)); >+ ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); >+ >+ if (dual_plane) { >+ disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c >+ / (double) vratio_c * dml_pow(2, 2)); >+ if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { >+ dml_print( >+ "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", >+ __func__, >+ disp_dlg_regs->dst_y_per_pte_row_nom_c, >+ (unsigned int)dml_pow(2, 17) - 1); >+ } >+ } >+ >+ disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l >+ / (double) vratio_l * dml_pow(2, 2)); >+ ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); >+ >+ disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now >+ >+ dml_print( >+ "DML: Trow: %fus\n", >+ line_time_in_us * (double)dpte_row_height_l / (double)vratio_l); >+ >+ disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l >+ / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq >+ / (double) dpte_groups_per_row_ub_l); >+ if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; >+ disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l >+ / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq >+ / (double) meta_chunks_per_row_ub_l); >+ if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; >+ >+ if (dual_plane) { >+ disp_dlg_regs->refcyc_per_pte_group_nom_c = >+ (unsigned int) ((double) dpte_row_height_c / (double) vratio_c >+ * (double) htotal * ref_freq_to_pix_freq >+ / (double) dpte_groups_per_row_ub_c); >+ if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; >+ >+ // TODO: Is this the right calculation? Does htotal need to be halved? >+ disp_dlg_regs->refcyc_per_meta_chunk_nom_c = >+ (unsigned int) ((double) meta_row_height_c / (double) vratio_c >+ * (double) htotal * ref_freq_to_pix_freq >+ / (double) meta_chunks_per_row_ub_c); >+ if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) >+ disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; >+ } >+ >+ disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( >+ refcyc_per_line_delivery_pre_l, 1); >+ disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor( >+ refcyc_per_line_delivery_l, 1); >+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); >+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); >+ >+ disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor( >+ refcyc_per_line_delivery_pre_c, 1); >+ disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor( >+ refcyc_per_line_delivery_c, 1); >+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); >+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); >+ >+ disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; >+ disp_dlg_regs->dst_y_offset_cur0 = 0; >+ disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; >+ disp_dlg_regs->dst_y_offset_cur1 = 0; >+ >+ disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; >+ disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; >+ disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; >+ disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil( >+ xfc_prefetch_margin * refclk_freq_in_mhz, 1); >+ >+ // slave has to have this value also set to off >+ if (src->xfc_enable && !src->xfc_slave) >+ disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); >+ else >+ disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off >+ >+ disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = >+ (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 >+ * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = >+ (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); >+ disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 >+ * dml_pow(2, 10)); >+ disp_ttu_regs->qos_level_low_wm = 0; >+ ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); >+ disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal >+ * ref_freq_to_pix_freq); >+ ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); >+ >+ disp_ttu_regs->qos_level_flip = 14; >+ disp_ttu_regs->qos_level_fixed_l = 8; >+ disp_ttu_regs->qos_level_fixed_c = 8; >+ disp_ttu_regs->qos_level_fixed_cur0 = 8; >+ disp_ttu_regs->qos_ramp_disable_l = 0; >+ disp_ttu_regs->qos_ramp_disable_c = 0; >+ disp_ttu_regs->qos_ramp_disable_cur0 = 0; >+ >+ disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; >+ ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); >+ >+ print__ttu_regs_st(mode_lib, *disp_ttu_regs); >+ print__dlg_regs_st(mode_lib, *disp_dlg_regs); >+} >+ >+void dml21_rq_dlg_get_dlg_reg( >+ struct display_mode_lib *mode_lib, >+ display_dlg_regs_st *dlg_regs, >+ display_ttu_regs_st *ttu_regs, >+ display_e2e_pipe_params_st *e2e_pipe_param, >+ const unsigned int num_pipes, >+ const unsigned int pipe_idx, >+ const bool cstate_en, >+ const bool pstate_en, >+ const bool vm_en, >+ const bool ignore_viewport_pos, >+ const bool immediate_flip_support) >+{ >+ display_rq_params_st rq_param = {0}; >+ display_dlg_sys_params_st dlg_sys_param = {0}; >+ >+ // Get watermark and Tex. >+ dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes); >+ dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); >+ dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes); >+ dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes); >+ dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency >+ / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated >+ >+ print__dlg_sys_params_st(mode_lib, dlg_sys_param); >+ >+ // system parameter calculation done >+ >+ dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); >+ dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe); >+ dml_rq_dlg_get_dlg_params( >+ mode_lib, >+ e2e_pipe_param, >+ num_pipes, >+ pipe_idx, >+ dlg_regs, >+ ttu_regs, >+ rq_param.dlg, >+ dlg_sys_param, >+ cstate_en, >+ pstate_en); >+ dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); >+} >+ >+void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param) >+{ >+ memset(arb_param, 0, sizeof(*arb_param)); >+ arb_param->max_req_outstanding = 256; >+ arb_param->min_req_outstanding = 68; >+ arb_param->sat_level_us = 60; >+} >+ >+static void calculate_ttu_cursor( >+ struct display_mode_lib *mode_lib, >+ double *refcyc_per_req_delivery_pre_cur, >+ double *refcyc_per_req_delivery_cur, >+ double refclk_freq_in_mhz, >+ double ref_freq_to_pix_freq, >+ double hscale_pixel_rate_l, >+ double hscl_ratio, >+ double vratio_pre_l, >+ double vratio_l, >+ unsigned int cur_width, >+ enum cursor_bpp cur_bpp) >+{ >+ unsigned int cur_src_width = cur_width; >+ unsigned int cur_req_size = 0; >+ unsigned int cur_req_width = 0; >+ double cur_width_ub = 0.0; >+ double cur_req_per_width = 0.0; >+ double hactive_cur = 0.0; >+ >+ ASSERT(cur_src_width <= 256); >+ >+ *refcyc_per_req_delivery_pre_cur = 0.0; >+ *refcyc_per_req_delivery_cur = 0.0; >+ if (cur_src_width > 0) { >+ unsigned int cur_bit_per_pixel = 0; >+ >+ if (cur_bpp == dm_cur_2bit) { >+ cur_req_size = 64; // byte >+ cur_bit_per_pixel = 2; >+ } else { // 32bit >+ cur_bit_per_pixel = 32; >+ if (cur_src_width >= 1 && cur_src_width <= 16) >+ cur_req_size = 64; >+ else if (cur_src_width >= 17 && cur_src_width <= 31) >+ cur_req_size = 128; >+ else >+ cur_req_size = 256; >+ } >+ >+ cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); >+ cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) >+ * (double) cur_req_width; >+ cur_req_per_width = cur_width_ub / (double) cur_req_width; >+ hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor >+ >+ if (vratio_pre_l <= 1.0) { >+ *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq >+ / (double) cur_req_per_width; >+ } else { >+ *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz >+ * (double) cur_src_width / hscale_pixel_rate_l >+ / (double) cur_req_per_width; >+ } >+ >+ ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); >+ >+ if (vratio_l <= 1.0) { >+ *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq >+ / (double) cur_req_per_width; >+ } else { >+ *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz >+ * (double) cur_src_width / hscale_pixel_rate_l >+ / (double) cur_req_per_width; >+ } >+ >+ dml_print( >+ "DML_DLG: %s: cur_req_width = %d\n", >+ __func__, >+ cur_req_width); >+ dml_print( >+ "DML_DLG: %s: cur_width_ub = %3.2f\n", >+ __func__, >+ cur_width_ub); >+ dml_print( >+ "DML_DLG: %s: cur_req_per_width = %3.2f\n", >+ __func__, >+ cur_req_per_width); >+ dml_print( >+ "DML_DLG: %s: hactive_cur = %3.2f\n", >+ __func__, >+ hactive_cur); >+ dml_print( >+ "DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", >+ __func__, >+ *refcyc_per_req_delivery_pre_cur); >+ dml_print( >+ "DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", >+ __func__, >+ *refcyc_per_req_delivery_cur); >+ >+ ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); >+ } >+} >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h 2019-08-31 15:01:11.868736169 -0500 >@@ -0,0 +1,73 @@ >+/* >+ * Copyright 2017 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef __DML21_DISPLAY_RQ_DLG_CALC_H__ >+#define __DML21_DISPLAY_RQ_DLG_CALC_H__ >+ >+#include "../dml_common_defs.h" >+#include "../display_rq_dlg_helpers.h" >+ >+struct display_mode_lib; >+ >+ >+// Function: dml_rq_dlg_get_rq_reg >+// Main entry point for test to get the register values out of this DML class. >+// This function calls <get_rq_param> and <extract_rq_regs> functions to calculate >+// and then populate the rq_regs struct >+// Input: >+// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.) >+// Output: >+// rq_regs - struct that holds all the RQ registers field value. >+// See also: <display_rq_regs_st> >+void dml21_rq_dlg_get_rq_reg( >+ struct display_mode_lib *mode_lib, >+ display_rq_regs_st *rq_regs, >+ const display_pipe_params_st pipe_param); >+ >+// Function: dml_rq_dlg_get_dlg_reg >+// Calculate and return DLG and TTU register struct given the system setting >+// Output: >+// dlg_regs - output DLG register struct >+// ttu_regs - output DLG TTU register struct >+// Input: >+// e2e_pipe_param - "compacted" array of e2e pipe param struct >+// num_pipes - num of active "pipe" or "route" >+// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg >+// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered. >+// Added for legacy or unrealistic timing tests. >+void dml21_rq_dlg_get_dlg_reg( >+ struct display_mode_lib *mode_lib, >+ display_dlg_regs_st *dlg_regs, >+ display_ttu_regs_st *ttu_regs, >+ display_e2e_pipe_params_st *e2e_pipe_param, >+ const unsigned int num_pipes, >+ const unsigned int pipe_idx, >+ const bool cstate_en, >+ const bool pstate_en, >+ const bool vm_en, >+ const bool ignore_viewport_pos, >+ const bool immediate_flip_support); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h 2019-08-31 15:01:11.868736169 -0500 >@@ -37,11 +37,14 @@ > dm_444_64 = 2, > dm_420_8 = 3, > dm_420_10 = 4, >- dm_422_8 = 5, >- dm_422_10 = 6, >- dm_444_8 = 7, >+ dm_420_12 = 5, >+ dm_422_8 = 6, >+ dm_422_10 = 7, >+ dm_444_8 = 8, > dm_mono_8 = dm_444_8, >- dm_mono_16 = dm_444_16 >+ dm_mono_16 = dm_444_16, >+ dm_rgbe = 9, >+ dm_rgbe_alpha = 10, > }; > enum output_bpc_class { > dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4 >@@ -83,7 +86,7 @@ > dm_sw_var_d_x = 30, > dm_sw_64kb_r_x, > dm_sw_gfx7_2d_thin_lvp, >- dm_sw_gfx7_2d_thin_gl >+ dm_sw_gfx7_2d_thin_gl, > }; > enum lb_depth { > dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4, >@@ -112,7 +115,8 @@ > enum mpc_combine_affinity { > dm_mpc_always_when_possible, > dm_mpc_reduce_voltage, >- dm_mpc_reduce_voltage_and_clocks >+ dm_mpc_reduce_voltage_and_clocks, >+ dm_mpc_never > }; > > enum self_refresh_affinity { >@@ -157,4 +161,10 @@ > dm_whole_buffer_for_single_stream_interleave, > }; > >+enum odm_combine_mode { >+ dm_odm_combine_mode_disabled, >+ dm_odm_combine_mode_2to1, >+ dm_odm_combine_mode_4to1, >+}; >+ > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c 2019-08-31 15:01:11.868736169 -0500 >@@ -28,6 +28,12 @@ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #include "dcn20/display_mode_vba_20.h" > #include "dcn20/display_rq_dlg_calc_20.h" >+#include "dcn20/display_mode_vba_20v2.h" >+#include "dcn20/display_rq_dlg_calc_20v2.h" >+#endif >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+#include "dcn21/display_mode_vba_21.h" >+#include "dcn21/display_rq_dlg_calc_21.h" > #endif > > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) >@@ -37,6 +43,22 @@ > .rq_dlg_get_dlg_reg = dml20_rq_dlg_get_dlg_reg, > .rq_dlg_get_rq_reg = dml20_rq_dlg_get_rq_reg > }; >+ >+const struct dml_funcs dml20v2_funcs = { >+ .validate = dml20v2_ModeSupportAndSystemConfigurationFull, >+ .recalculate = dml20v2_recalculate, >+ .rq_dlg_get_dlg_reg = dml20v2_rq_dlg_get_dlg_reg, >+ .rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg >+}; >+#endif >+ >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+const struct dml_funcs dml21_funcs = { >+ .validate = dml21_ModeSupportAndSystemConfigurationFull, >+ .recalculate = dml21_recalculate, >+ .rq_dlg_get_dlg_reg = dml21_rq_dlg_get_dlg_reg, >+ .rq_dlg_get_rq_reg = dml21_rq_dlg_get_rq_reg >+}; > #endif > > void dml_init_instance(struct display_mode_lib *lib, >@@ -52,7 +74,16 @@ > case DML_PROJECT_NAVI10: > lib->funcs = dml20_funcs; > break; >+ case DML_PROJECT_NAVI10v2: >+ lib->funcs = dml20v2_funcs; >+ break; > #endif >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+ case DML_PROJECT_DCN21: >+ lib->funcs = dml21_funcs; >+ break; >+#endif >+ > default: > break; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h 2019-08-31 15:01:11.868736169 -0500 >@@ -36,6 +36,10 @@ > DML_PROJECT_RAVEN1, > #ifdef CONFIG_DRM_AMD_DC_DCN2_0 > DML_PROJECT_NAVI10, >+ DML_PROJECT_NAVI10v2, >+#endif >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+ DML_PROJECT_DCN21, > #endif > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 2019-08-31 15:01:11.868736169 -0500 >@@ -100,6 +100,7 @@ > unsigned int vmm_page_size_bytes; > unsigned int hostvm_min_page_size_bytes; > double dram_clock_change_latency_us; >+ double dummy_pstate_latency_us; > double writeback_dram_clock_change_latency_us; > unsigned int return_bus_width_bytes; > unsigned int voltage_override; >@@ -108,6 +109,9 @@ > int use_urgent_burst_bw; > unsigned int num_states; > struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES]; >+ bool do_urgent_latency_adjustment; >+ double urgent_latency_adjustment_fabric_clock_component_us; >+ double urgent_latency_adjustment_fabric_clock_reference_mhz; > }; > > struct _vcs_dpi_ip_params_st { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 2019-08-31 15:01:11.868736169 -0500 >@@ -262,6 +262,13 @@ > //mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mhz; > mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz; > } >+ >+ mode_lib->vba.DoUrgentLatencyAdjustment = >+ soc->do_urgent_latency_adjustment; >+ mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent = >+ soc->urgent_latency_adjustment_fabric_clock_component_us; >+ mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference = >+ soc->urgent_latency_adjustment_fabric_clock_reference_mhz; > } > > static void fetch_ip_params(struct display_mode_lib *mode_lib) >@@ -385,8 +392,10 @@ > src->viewport_y_c; > mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch; > mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height; >+ mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width; > mode_lib->vba.PitchC[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch_c; > mode_lib->vba.SurfaceHeightC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_c; >+ mode_lib->vba.SurfaceWidthC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width_c; > mode_lib->vba.DCCMetaPitchY[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch; > mode_lib->vba.DCCMetaPitchC[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch_c; > mode_lib->vba.HRatio[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio; >@@ -457,6 +466,10 @@ > dout->wb.wb_dst_width; > mode_lib->vba.WritebackDestinationHeight[mode_lib->vba.NumberOfActivePlanes] = > dout->wb.wb_dst_height; >+ mode_lib->vba.WritebackHRatio[mode_lib->vba.NumberOfActivePlanes] = >+ dout->wb.wb_hratio; >+ mode_lib->vba.WritebackVRatio[mode_lib->vba.NumberOfActivePlanes] = >+ dout->wb.wb_vratio; > mode_lib->vba.WritebackPixelFormat[mode_lib->vba.NumberOfActivePlanes] = > (enum source_format_class) (dout->wb.wb_pixel_format); > mode_lib->vba.WritebackHTaps[mode_lib->vba.NumberOfActivePlanes] = >@@ -568,6 +581,7 @@ > if (src->is_hsplit) { > for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) { > display_pipe_source_params_st *src_k = &pipes[k].pipe.src; >+ display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest; > > if (src_k->is_hsplit && !visited[k] > && src->hsplit_grp == src_k->hsplit_grp) { >@@ -575,12 +589,15 @@ > mode_lib->vba.NumberOfActivePlanes; > mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes]++; > if (mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] >- == dm_horz) >+ == dm_horz) { > mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] += > src_k->viewport_width; >- else >+ mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] += >+ dst_k->recout_width; >+ } else { > mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] += > src_k->viewport_height; >+ } > > visited[k] = true; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 2019-08-31 15:01:11.869736169 -0500 >@@ -290,6 +290,7 @@ > double PixelClock[DC__NUM_DPP__MAX]; > double PixelClockBackEnd[DC__NUM_DPP__MAX]; > bool DCCEnable[DC__NUM_DPP__MAX]; >+ bool FECEnable[DC__NUM_DPP__MAX]; > unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX]; > unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX]; > enum scan_direction_class SourceScan[DC__NUM_DPP__MAX]; >@@ -317,6 +318,7 @@ > double DCCRate[DC__NUM_DPP__MAX]; > double AverageDCCCompressionRate; > bool ODMCombineEnabled[DC__NUM_DPP__MAX]; >+ enum odm_combine_mode ODMCombineTypeEnabled[DC__NUM_DPP__MAX]; > double OutputBpp[DC__NUM_DPP__MAX]; > bool DSCEnabled[DC__NUM_DPP__MAX]; > unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX]; >@@ -395,6 +397,7 @@ > double FabricClockPerState[DC__VOLTAGE_STATES + 1]; > double SOCCLKPerState[DC__VOLTAGE_STATES + 1]; > double PHYCLKPerState[DC__VOLTAGE_STATES + 1]; >+ double DTBCLKPerState[DC__VOLTAGE_STATES + 1]; > double MaxDppclk[DC__VOLTAGE_STATES + 1]; > double MaxDSCCLK[DC__VOLTAGE_STATES + 1]; > double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1]; >@@ -488,6 +491,7 @@ > unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; > int NoOfDPPThisState[DC__NUM_DPP__MAX]; > bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; >+ enum odm_combine_mode ODMCombineTypeEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX]; > unsigned int SwathWidthYThisState[DC__NUM_DPP__MAX]; > unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX]; > unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX]; >@@ -513,6 +517,7 @@ > bool DIOSupport[DC__VOLTAGE_STATES + 1]; > bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1]; > bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1]; >+ bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1]; > double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1]; > bool ROBSupport[DC__VOLTAGE_STATES + 1]; > bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2]; >@@ -605,6 +610,7 @@ > double MaximumSwathWidthLuma[DC__NUM_DPP__MAX]; > double MaximumSwathWidthChroma[DC__NUM_DPP__MAX]; > bool odm_combine_dummy[DC__NUM_DPP__MAX]; >+ enum odm_combine_mode odm_combine_mode_dummy[DC__NUM_DPP__MAX]; > double dummy1[DC__NUM_DPP__MAX]; > double dummy2[DC__NUM_DPP__MAX]; > double dummy3[DC__NUM_DPP__MAX]; >@@ -625,6 +631,11 @@ > unsigned int dummyinteger10; > unsigned int dummyinteger11; > unsigned int dummyinteger12; >+ unsigned int dummyintegerarr1[DC__NUM_DPP__MAX]; >+ unsigned int dummyintegerarr2[DC__NUM_DPP__MAX]; >+ unsigned int dummyintegerarr3[DC__NUM_DPP__MAX]; >+ unsigned int dummyintegerarr4[DC__NUM_DPP__MAX]; >+ long dummylongarr1[DC__NUM_DPP__MAX]; > bool dummysinglestring; > bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; > double PlaneRequiredDISPCLKWithODMCombine2To1; >@@ -633,6 +644,7 @@ > bool LinkDSCEnable; > bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1]; > bool ODMCombineEnableThisState[DC__NUM_DPP__MAX]; >+ enum odm_combine_mode ODMCombineEnableTypeThisState[DC__NUM_DPP__MAX]; > unsigned int SwathWidthCThisState[DC__NUM_DPP__MAX]; > bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; > double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX]; >@@ -641,6 +653,7 @@ > unsigned int NotEnoughUrgentLatencyHiding; > unsigned int NotEnoughUrgentLatencyHidingPre; > long PTEBufferSizeInRequestsForLuma; >+ long PTEBufferSizeInRequestsForChroma; > > // Missing from VBA > long dpte_group_bytes_chroma; >@@ -787,6 +800,9 @@ > unsigned int PDEProcessingBufIn64KBReqs; > > double MaxTotalVActiveRDBandwidth; >+ bool DoUrgentLatencyAdjustment; >+ double UrgentLatencyAdjustmentFabricClockComponent; >+ double UrgentLatencyAdjustmentFabricClockReference; > double MinUrgentLatencySupportUs; > double MinFullDETBufferingTime; > double AverageReadBandwidthGBytePerSecond; >@@ -801,6 +817,8 @@ > bool ModeIsSupported; > bool ODMCombine4To1Supported; > >+ unsigned int SurfaceWidthY[DC__NUM_DPP__MAX]; >+ unsigned int SurfaceWidthC[DC__NUM_DPP__MAX]; > unsigned int SurfaceHeightY[DC__NUM_DPP__MAX]; > unsigned int SurfaceHeightC[DC__NUM_DPP__MAX]; > unsigned int WritebackHTaps[DC__NUM_DPP__MAX]; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/Makefile 2019-08-31 15:01:11.867736169 -0500 >@@ -32,12 +32,22 @@ > > dml_ccflags := -mhard-float -msse $(cc_stack_align) > >+ifdef CONFIG_CC_IS_CLANG >+dml_ccflags += -msse2 >+endif >+ > CFLAGS_display_mode_lib.o := $(dml_ccflags) > > ifdef CONFIG_DRM_AMD_DC_DCN2_0 > CFLAGS_display_mode_vba.o := $(dml_ccflags) > CFLAGS_display_mode_vba_20.o := $(dml_ccflags) > CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags) >+CFLAGS_display_mode_vba_20v2.o := $(dml_ccflags) >+CFLAGS_display_rq_dlg_calc_20v2.o := $(dml_ccflags) >+endif >+ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+CFLAGS_display_mode_vba_21.o := $(dml_ccflags) >+CFLAGS_display_rq_dlg_calc_21.o := $(dml_ccflags) > endif > ifdef CONFIG_DRM_AMD_DCN3AG > CFLAGS_display_mode_vba_3ag.o := $(dml_ccflags) >@@ -51,7 +61,12 @@ > > ifdef CONFIG_DRM_AMD_DC_DCN2_0 > DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o >+DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o > endif >+ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o >+endif >+ > > AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML)) > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 2019-08-31 15:01:11.867736169 -0500 >@@ -44,6 +44,9 @@ > #ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0 > PP_SMU_VER_NV, > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ PP_SMU_VER_RN, >+#endif > > PP_SMU_VER_MAX > }; >@@ -246,6 +249,47 @@ > }; > #endif > >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ >+#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8 >+#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 4 >+#define PP_SMU_NUM_FCLK_DPM_LEVELS 4 >+#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4 >+ >+struct dpm_clock { >+ uint32_t Freq; // In MHz >+ uint32_t Vol; // Millivolts with 2 fractional bits >+}; >+ >+ >+/* this is a copy of the structure defined in smuxx_driver_if.h*/ >+struct dpm_clocks { >+ struct dpm_clock DcfClocks[PP_SMU_NUM_DCFCLK_DPM_LEVELS]; >+ struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS]; >+ struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS]; >+ struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS]; >+}; >+ >+ >+struct pp_smu_funcs_rn { >+ struct pp_smu pp_smu; >+ >+ /* >+ * reader and writer WM's are sent together as part of one table >+ * >+ * PPSMC_MSG_SetDriverDramAddrHigh >+ * PPSMC_MSG_SetDriverDramAddrLow >+ * PPSMC_MSG_TransferTableDram2Smu >+ * >+ */ >+ enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp, >+ struct pp_smu_wm_range_sets *ranges); >+ >+ enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp, >+ struct dpm_clocks *clock_table); >+}; >+#endif >+ > struct pp_smu_funcs { > struct pp_smu ctx; > union { >@@ -253,6 +297,9 @@ > #ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0 > struct pp_smu_funcs_nv nv_funcs; > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ struct pp_smu_funcs_rn rn_funcs; >+#endif > > }; > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dm_services.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dm_services.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dm_services.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dm_services.h 2019-08-31 15:01:11.867736169 -0500 >@@ -151,6 +151,7 @@ > unsigned int delay_between_poll_us, unsigned int time_out_num_tries, > const char *func_name, int line); > >+unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...); > > /* These macros need to be used with soc15 registers in order to retrieve > * the actual offset. >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 2019-08-31 15:01:11.869736169 -0500 >@@ -28,6 +28,23 @@ > #include "dsc.h" > #include <drm/drm_dp_helper.h> > >+struct dc_dsc_policy { >+ bool use_min_slices_h; >+ int max_slices_h; // Maximum available if 0 >+ int min_sice_height; // Must not be less than 8 >+ int max_target_bpp; >+ int min_target_bpp; // Minimum target bits per pixel >+}; >+ >+const struct dc_dsc_policy dsc_policy = { >+ .use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock >+ .max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode) >+ .min_sice_height = 108, // DSC Policy: Use slice height recommended by VESA DSC Spreadsheet user guide >+ .max_target_bpp = 16, >+ .min_target_bpp = 8, >+}; >+ >+ > /* This module's internal functions */ > > static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size) >@@ -241,14 +258,6 @@ > return true; > } > >-struct dc_dsc_policy { >- bool use_min_slices_h; >- int max_slices_h; // Maximum available if 0 >- int num_slices_v; >- int max_target_bpp; >- int min_target_bpp; // Minimum target bits per pixel >-}; >- > static inline uint32_t dsc_div_by_10_round_up(uint32_t value) > { > return (value + 9) / 10; >@@ -270,19 +279,6 @@ > return dsc_target_bpp_x16; > } > >-const struct dc_dsc_policy dsc_policy = { >- .use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock >- .max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode) >- /* DSC Policy: Number of vertical slices set to 2 for no particular reason. >- * Seems small enough to not affect the quality too much, while still providing some error >- * propagation control (which may also help debugging). >- */ >- .num_slices_v = 16, >- .max_target_bpp = 16, >- .min_target_bpp = 8, >-}; >- >- > /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clock > * and uncompressed bandwidth. > */ >@@ -528,8 +524,8 @@ > int sink_per_slice_throughput_mps; > int branch_max_throughput_mps = 0; > bool is_dsc_possible = false; >- int num_slices_v; > int pic_height; >+ int slice_height; > > memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); > >@@ -615,7 +611,7 @@ > if (!is_dsc_possible) > goto done; > >- // DSC slicing >+ // Slice width (i.e. number of slices per line) > max_slices_h = get_max_dsc_slices(dsc_common_caps.slice_caps); > > while (max_slices_h > 0) { >@@ -678,29 +674,26 @@ > dsc_cfg->num_slices_h = num_slices_h; > slice_width = pic_width / num_slices_h; > >- // Vertical number of slices: start from policy and pick the first one that height is divisible by. >+ is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width; >+ if (!is_dsc_possible) >+ goto done; >+ >+ // Slice height (i.e. number of slices per column): start with policy and pick the first one that height is divisible by. > // For 4:2:0 make sure the slice height is divisible by 2 as well. >- num_slices_v = dsc_policy.num_slices_v; >- if (num_slices_v < 1) >- num_slices_v = 1; >- >- while (num_slices_v >= 1) { >- if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) { >- int slice_height = pic_height / num_slices_v; >- if (pic_height % num_slices_v == 0 && slice_height % 2 == 0) >- break; >- } else if (pic_height % num_slices_v == 0) >- break; >+ slice_height = min(dsc_policy.min_sice_height, pic_height); > >- num_slices_v--; >- } >+ while (slice_height < pic_height && (pic_height % slice_height != 0 || >+ (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0))) >+ slice_height++; > >- dsc_cfg->num_slices_v = num_slices_v; >+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) // For the case when pic_height < dsc_policy.min_sice_height >+ is_dsc_possible = (slice_height % 2 == 0); > >- is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width; > if (!is_dsc_possible) > goto done; > >+ dsc_cfg->num_slices_v = pic_height/slice_height; >+ > // Final decission: can we do DSC or not? > if (is_dsc_possible) { > // Fill out the rest of DSC settings >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c 1969-12-31 18:00:00.000000000 -0600 >@@ -1,388 +0,0 @@ >-// SPDX-License-Identifier: MIT >-/* >- * Copyright © 2018 Intel Corp >- * >- * Author: >- * Manasi Navare <manasi.d.navare@intel.com> >- */ >- >-/* DC versions of linux includes */ >-#include <include/drm_dsc_dc.h> >- >-#define EXPORT_SYMBOL(symbol) /* nothing */ >-#define BUILD_BUG_ON(cond) /* nothing */ >-#define DIV_ROUND_UP(a, b) (((b) + (a) - 1) / (b)) >-#define ERANGE -1 >-#define DRM_DEBUG_KMS(msg) /* nothing */ >-#define cpu_to_be16(__x) little_to_big(__x) >- >-static unsigned short little_to_big(int data) >-{ >- /* Swap lower and upper byte. DMCU uses big endian format. */ >- return (0xff & (data >> 8)) + ((data & 0xff) << 8); >-} >- >-/* >- * Everything below this comment was copied directly from drm_dsc.c. >- * Only the functions needed in DC are included. >- * Please keep this file synced with upstream. >- */ >- >-/** >- * DOC: dsc helpers >- * >- * These functions contain some common logic and helpers to deal with VESA >- * Display Stream Compression standard required for DSC on Display Port/eDP or >- * MIPI display interfaces. >- */ >- >-/** >- * drm_dsc_pps_payload_pack() - Populates the DSC PPS >- * >- * @pps_payload: >- * Bitwise struct for DSC Picture Parameter Set. This is defined >- * by &struct drm_dsc_picture_parameter_set >- * @dsc_cfg: >- * DSC Configuration data filled by driver as defined by >- * &struct drm_dsc_config >- * >- * DSC source device sends a picture parameter set (PPS) containing the >- * information required by the sink to decode the compressed frame. Driver >- * populates the DSC PPS struct using the DSC configuration parameters in >- * the order expected by the DSC Display Sink device. For the DSC, the sink >- * device expects the PPS payload in big endian format for fields >- * that span more than 1 byte. >- */ >-void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, >- const struct drm_dsc_config *dsc_cfg) >-{ >- int i; >- >- /* Protect against someone accidently changing struct size */ >- BUILD_BUG_ON(sizeof(*pps_payload) != >- DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); >- >- memset(pps_payload, 0, sizeof(*pps_payload)); >- >- /* PPS 0 */ >- pps_payload->dsc_version = >- dsc_cfg->dsc_version_minor | >- dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; >- >- /* PPS 1, 2 is 0 */ >- >- /* PPS 3 */ >- pps_payload->pps_3 = >- dsc_cfg->line_buf_depth | >- dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; >- >- /* PPS 4 */ >- pps_payload->pps_4 = >- ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> >- DSC_PPS_MSB_SHIFT) | >- dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | >- dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | >- dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | >- dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; >- >- /* PPS 5 */ >- pps_payload->bits_per_pixel_low = >- (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); >- >- /* >- * The DSC panel expects the PPS packet to have big endian format >- * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert >- * to big endian format. If format is little endian, it will swap >- * bytes to convert to Big endian else keep it unchanged. >- */ >- >- /* PPS 6, 7 */ >- pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); >- >- /* PPS 8, 9 */ >- pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); >- >- /* PPS 10, 11 */ >- pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); >- >- /* PPS 12, 13 */ >- pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); >- >- /* PPS 14, 15 */ >- pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); >- >- /* PPS 16 */ >- pps_payload->initial_xmit_delay_high = >- ((dsc_cfg->initial_xmit_delay & >- DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> >- DSC_PPS_MSB_SHIFT); >- >- /* PPS 17 */ >- pps_payload->initial_xmit_delay_low = >- (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); >- >- /* PPS 18, 19 */ >- pps_payload->initial_dec_delay = >- cpu_to_be16(dsc_cfg->initial_dec_delay); >- >- /* PPS 20 is 0 */ >- >- /* PPS 21 */ >- pps_payload->initial_scale_value = >- dsc_cfg->initial_scale_value; >- >- /* PPS 22, 23 */ >- pps_payload->scale_increment_interval = >- cpu_to_be16(dsc_cfg->scale_increment_interval); >- >- /* PPS 24 */ >- pps_payload->scale_decrement_interval_high = >- ((dsc_cfg->scale_decrement_interval & >- DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> >- DSC_PPS_MSB_SHIFT); >- >- /* PPS 25 */ >- pps_payload->scale_decrement_interval_low = >- (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); >- >- /* PPS 26[7:0], PPS 27[7:5] RESERVED */ >- >- /* PPS 27 */ >- pps_payload->first_line_bpg_offset = >- dsc_cfg->first_line_bpg_offset; >- >- /* PPS 28, 29 */ >- pps_payload->nfl_bpg_offset = >- cpu_to_be16(dsc_cfg->nfl_bpg_offset); >- >- /* PPS 30, 31 */ >- pps_payload->slice_bpg_offset = >- cpu_to_be16(dsc_cfg->slice_bpg_offset); >- >- /* PPS 32, 33 */ >- pps_payload->initial_offset = >- cpu_to_be16(dsc_cfg->initial_offset); >- >- /* PPS 34, 35 */ >- pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); >- >- /* PPS 36 */ >- pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; >- >- /* PPS 37 */ >- pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; >- >- /* PPS 38, 39 */ >- pps_payload->rc_model_size = >- cpu_to_be16(DSC_RC_MODEL_SIZE_CONST); >- >- /* PPS 40 */ >- pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; >- >- /* PPS 41 */ >- pps_payload->rc_quant_incr_limit0 = >- dsc_cfg->rc_quant_incr_limit0; >- >- /* PPS 42 */ >- pps_payload->rc_quant_incr_limit1 = >- dsc_cfg->rc_quant_incr_limit1; >- >- /* PPS 43 */ >- pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | >- DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; >- >- /* PPS 44 - 57 */ >- for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) >- pps_payload->rc_buf_thresh[i] = >- dsc_cfg->rc_buf_thresh[i]; >- >- /* PPS 58 - 87 */ >- /* >- * For DSC sink programming the RC Range parameter fields >- * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] >- */ >- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { >- pps_payload->rc_range_parameters[i] = >- ((dsc_cfg->rc_range_params[i].range_min_qp << >- DSC_PPS_RC_RANGE_MINQP_SHIFT) | >- (dsc_cfg->rc_range_params[i].range_max_qp << >- DSC_PPS_RC_RANGE_MAXQP_SHIFT) | >- (dsc_cfg->rc_range_params[i].range_bpg_offset)); >- pps_payload->rc_range_parameters[i] = >- cpu_to_be16(pps_payload->rc_range_parameters[i]); >- } >- >- /* PPS 88 */ >- pps_payload->native_422_420 = dsc_cfg->native_422 | >- dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; >- >- /* PPS 89 */ >- pps_payload->second_line_bpg_offset = >- dsc_cfg->second_line_bpg_offset; >- >- /* PPS 90, 91 */ >- pps_payload->nsl_bpg_offset = >- cpu_to_be16(dsc_cfg->nsl_bpg_offset); >- >- /* PPS 92, 93 */ >- pps_payload->second_line_offset_adj = >- cpu_to_be16(dsc_cfg->second_line_offset_adj); >- >- /* PPS 94 - 127 are O */ >-} >-EXPORT_SYMBOL(drm_dsc_pps_payload_pack); >- >-/** >- * drm_dsc_compute_rc_parameters() - Write rate control >- * parameters to the dsc configuration defined in >- * &struct drm_dsc_config in accordance with the DSC 1.2 >- * specification. Some configuration fields must be present >- * beforehand. >- * >- * @vdsc_cfg: >- * DSC Configuration data partially filled by driver >- */ >-int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) >-{ >- unsigned long groups_per_line = 0; >- unsigned long groups_total = 0; >- unsigned long num_extra_mux_bits = 0; >- unsigned long slice_bits = 0; >- unsigned long hrd_delay = 0; >- unsigned long final_scale = 0; >- unsigned long rbs_min = 0; >- >- if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { >- /* Number of groups used to code each line of a slice */ >- groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, >- DSC_RC_PIXELS_PER_GROUP); >- >- /* chunksize in Bytes */ >- vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * >- vdsc_cfg->bits_per_pixel, >- (8 * 16)); >- } else { >- /* Number of groups used to code each line of a slice */ >- groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, >- DSC_RC_PIXELS_PER_GROUP); >- >- /* chunksize in Bytes */ >- vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * >- vdsc_cfg->bits_per_pixel, >- (8 * 16)); >- } >- >- if (vdsc_cfg->convert_rgb) >- num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + >- (4 * vdsc_cfg->bits_per_component + 4) >- - 2); >- else if (vdsc_cfg->native_422) >- num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + >- (4 * vdsc_cfg->bits_per_component + 4) + >- 3 * (4 * vdsc_cfg->bits_per_component) - 2; >- else >- num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + >- (4 * vdsc_cfg->bits_per_component + 4) + >- 2 * (4 * vdsc_cfg->bits_per_component) - 2; >- /* Number of bits in one Slice */ >- slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; >- >- while ((num_extra_mux_bits > 0) && >- ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) >- num_extra_mux_bits--; >- >- if (groups_per_line < vdsc_cfg->initial_scale_value - 8) >- vdsc_cfg->initial_scale_value = groups_per_line + 8; >- >- /* scale_decrement_interval calculation according to DSC spec 1.11 */ >- if (vdsc_cfg->initial_scale_value > 8) >- vdsc_cfg->scale_decrement_interval = groups_per_line / >- (vdsc_cfg->initial_scale_value - 8); >- else >- vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; >- >- vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - >- (vdsc_cfg->initial_xmit_delay * >- vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; >- >- if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { >- DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); >- return -ERANGE; >- } >- >- final_scale = (vdsc_cfg->rc_model_size * 8) / >- (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); >- if (vdsc_cfg->slice_height > 1) >- /* >- * NflBpgOffset is 16 bit value with 11 fractional bits >- * hence we multiply by 2^11 for preserving the >- * fractional part >- */ >- vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), >- (vdsc_cfg->slice_height - 1)); >- else >- vdsc_cfg->nfl_bpg_offset = 0; >- >- /* 2^16 - 1 */ >- if (vdsc_cfg->nfl_bpg_offset > 65535) { >- DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n"); >- return -ERANGE; >- } >- >- /* Number of groups used to code the entire slice */ >- groups_total = groups_per_line * vdsc_cfg->slice_height; >- >- /* slice_bpg_offset is 16 bit value with 11 fractional bits */ >- vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - >- vdsc_cfg->initial_offset + >- num_extra_mux_bits) << 11), >- groups_total); >- >- if (final_scale > 9) { >- /* >- * ScaleIncrementInterval = >- * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) >- * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, >- * we need divide by 2^11 from pstDscCfg values >- */ >- vdsc_cfg->scale_increment_interval = >- (vdsc_cfg->final_offset * (1 << 11)) / >- ((vdsc_cfg->nfl_bpg_offset + >- vdsc_cfg->slice_bpg_offset) * >- (final_scale - 9)); >- } else { >- /* >- * If finalScaleValue is less than or equal to 9, a value of 0 should >- * be used to disable the scale increment at the end of the slice >- */ >- vdsc_cfg->scale_increment_interval = 0; >- } >- >- if (vdsc_cfg->scale_increment_interval > 65535) { >- DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n"); >- return -ERANGE; >- } >- >- /* >- * DSC spec mentions that bits_per_pixel specifies the target >- * bits/pixel (bpp) rate that is used by the encoder, >- * in steps of 1/16 of a bit per pixel >- */ >- rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + >- DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * >- vdsc_cfg->bits_per_pixel, 16) + >- groups_per_line * vdsc_cfg->first_line_bpg_offset; >- >- hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); >- vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; >- vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; >- >- /* As per DSC spec v1.2a recommendation: */ >- if (vdsc_cfg->native_420) >- vdsc_cfg->second_line_offset_adj = 512; >- else >- vdsc_cfg->second_line_offset_adj = 0; >- >- return 0; >-} >-EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/Makefile 2019-08-31 15:01:11.869736169 -0500 >@@ -9,6 +9,10 @@ > > dsc_ccflags := -mhard-float -msse $(cc_stack_align) > >+ifdef CONFIG_CC_IS_CLANG >+dsc_ccflags += -msse2 >+endif >+ > CFLAGS_rc_calc.o := $(dsc_ccflags) > CFLAGS_rc_calc_dpi.o := $(dsc_ccflags) > CFLAGS_codec_main_amd.o := $(dsc_ccflags) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 2019-08-31 15:01:11.869736169 -0500 >@@ -24,9 +24,15 @@ > */ > > #include "dm_services.h" >+ > #include "include/gpio_types.h" > #include "../hw_factory.h" > >+#include "../hw_gpio.h" >+#include "../hw_ddc.h" >+#include "../hw_hpd.h" >+#include "../hw_generic.h" >+ > #include "hw_factory_dce110.h" > > #include "dce/dce_11_0_d.h" >@@ -143,12 +149,12 @@ > } > > static const struct hw_factory_funcs funcs = { >- .create_ddc_data = dal_hw_ddc_create, >- .create_ddc_clock = dal_hw_ddc_create, >- .create_generic = NULL, >- .create_hpd = dal_hw_hpd_create, >- .create_sync = NULL, >- .create_gsl = NULL, >+ .init_ddc_data = dal_hw_ddc_init, >+ .init_generic = NULL, >+ .init_hpd = dal_hw_hpd_init, >+ .get_ddc_pin = dal_hw_ddc_get_pin, >+ .get_hpd_pin = dal_hw_hpd_get_pin, >+ .get_generic_pin = NULL, > .define_hpd_registers = define_hpd_registers, > .define_ddc_registers = define_ddc_registers > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 2019-08-31 15:01:11.869736169 -0500 >@@ -27,10 +27,10 @@ > #include "include/gpio_types.h" > #include "../hw_factory.h" > >- > #include "../hw_gpio.h" > #include "../hw_ddc.h" > #include "../hw_hpd.h" >+#include "../hw_generic.h" > > #include "hw_factory_dce120.h" > >@@ -164,12 +164,12 @@ > > /* fucntion table */ > static const struct hw_factory_funcs funcs = { >- .create_ddc_data = dal_hw_ddc_create, >- .create_ddc_clock = dal_hw_ddc_create, >- .create_generic = NULL, >- .create_hpd = dal_hw_hpd_create, >- .create_sync = NULL, >- .create_gsl = NULL, >+ .init_ddc_data = dal_hw_ddc_init, >+ .init_generic = NULL, >+ .init_hpd = dal_hw_hpd_init, >+ .get_ddc_pin = dal_hw_ddc_get_pin, >+ .get_hpd_pin = dal_hw_hpd_get_pin, >+ .get_generic_pin = NULL, > .define_hpd_registers = define_hpd_registers, > .define_ddc_registers = define_ddc_registers > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 2019-08-31 15:01:11.869736169 -0500 >@@ -32,10 +32,12 @@ > #include "../hw_gpio.h" > #include "../hw_ddc.h" > #include "../hw_hpd.h" >+#include "../hw_generic.h" > > #include "dce/dce_8_0_d.h" > #include "dce/dce_8_0_sh_mask.h" > >+ > #define REG(reg_name)\ > mm ## reg_name > >@@ -147,12 +149,12 @@ > } > > static const struct hw_factory_funcs funcs = { >- .create_ddc_data = dal_hw_ddc_create, >- .create_ddc_clock = dal_hw_ddc_create, >- .create_generic = NULL, >- .create_hpd = dal_hw_hpd_create, >- .create_sync = NULL, >- .create_gsl = NULL, >+ .init_ddc_data = dal_hw_ddc_init, >+ .init_generic = NULL, >+ .init_hpd = dal_hw_hpd_init, >+ .get_ddc_pin = dal_hw_ddc_get_pin, >+ .get_hpd_pin = dal_hw_hpd_get_pin, >+ .get_generic_pin = NULL, > .define_hpd_registers = define_hpd_registers, > .define_ddc_registers = define_ddc_registers > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 2019-08-31 15:01:11.869736169 -0500 >@@ -31,6 +31,7 @@ > #include "../hw_gpio.h" > #include "../hw_ddc.h" > #include "../hw_hpd.h" >+#include "../hw_generic.h" > > #include "hw_factory_dcn10.h" > >@@ -121,6 +122,42 @@ > DDC_MASK_SH_LIST(_MASK) > }; > >+#include "../generic_regs.h" >+ >+/* set field name */ >+#define SF_GENERIC(reg_name, field_name, post_fix)\ >+ .field_name = reg_name ## __ ## field_name ## post_fix >+ >+#define generic_regs(id) \ >+{\ >+ GENERIC_REG_LIST(id)\ >+} >+ >+static const struct generic_registers generic_regs[] = { >+ generic_regs(A), >+ generic_regs(B), >+}; >+ >+static const struct generic_sh_mask generic_shift[] = { >+ GENERIC_MASK_SH_LIST(__SHIFT, A), >+ GENERIC_MASK_SH_LIST(__SHIFT, B), >+}; >+ >+static const struct generic_sh_mask generic_mask[] = { >+ GENERIC_MASK_SH_LIST(_MASK, A), >+ GENERIC_MASK_SH_LIST(_MASK, B), >+}; >+ >+static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) >+{ >+ struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin); >+ >+ generic->regs = &generic_regs[en]; >+ generic->shifts = &generic_shift[en]; >+ generic->masks = &generic_mask[en]; >+ generic->base.regs = &generic_regs[en].gpio; >+} >+ > static void define_ddc_registers( > struct hw_gpio_pin *pin, > uint32_t en) >@@ -159,14 +196,15 @@ > > /* fucntion table */ > static const struct hw_factory_funcs funcs = { >- .create_ddc_data = dal_hw_ddc_create, >- .create_ddc_clock = dal_hw_ddc_create, >- .create_generic = NULL, >- .create_hpd = dal_hw_hpd_create, >- .create_sync = NULL, >- .create_gsl = NULL, >+ .init_ddc_data = dal_hw_ddc_init, >+ .init_generic = dal_hw_generic_init, >+ .init_hpd = dal_hw_hpd_init, >+ .get_ddc_pin = dal_hw_ddc_get_pin, >+ .get_hpd_pin = dal_hw_hpd_get_pin, >+ .get_generic_pin = dal_hw_generic_get_pin, > .define_hpd_registers = define_hpd_registers, >- .define_ddc_registers = define_ddc_registers >+ .define_ddc_registers = define_ddc_registers, >+ .define_generic_registers = define_generic_registers > }; > /* > * dal_hw_factory_dcn10_init >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c 2019-08-31 15:01:11.869736169 -0500 >@@ -31,6 +31,7 @@ > #include "../hw_gpio.h" > #include "../hw_ddc.h" > #include "../hw_hpd.h" >+#include "../hw_generic.h" > > #include "hw_factory_dcn20.h" > >@@ -138,6 +139,32 @@ > DDC_MASK_SH_LIST_DCN2(_MASK, 6) > }; > >+#include "../generic_regs.h" >+ >+/* set field name */ >+#define SF_GENERIC(reg_name, field_name, post_fix)\ >+ .field_name = reg_name ## __ ## field_name ## post_fix >+ >+#define generic_regs(id) \ >+{\ >+ GENERIC_REG_LIST(id)\ >+} >+ >+static const struct generic_registers generic_regs[] = { >+ generic_regs(A), >+ generic_regs(B), >+}; >+ >+static const struct generic_sh_mask generic_shift[] = { >+ GENERIC_MASK_SH_LIST(__SHIFT, A), >+ GENERIC_MASK_SH_LIST(__SHIFT, B), >+}; >+ >+static const struct generic_sh_mask generic_mask[] = { >+ GENERIC_MASK_SH_LIST(_MASK, A), >+ GENERIC_MASK_SH_LIST(_MASK, B), >+}; >+ > static void define_ddc_registers( > struct hw_gpio_pin *pin, > uint32_t en) >@@ -173,17 +200,27 @@ > hpd->base.regs = &hpd_regs[en].gpio; > } > >+static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) >+{ >+ struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin); >+ >+ generic->regs = &generic_regs[en]; >+ generic->shifts = &generic_shift[en]; >+ generic->masks = &generic_mask[en]; >+ generic->base.regs = &generic_regs[en].gpio; >+} > > /* fucntion table */ > static const struct hw_factory_funcs funcs = { >- .create_ddc_data = dal_hw_ddc_create, >- .create_ddc_clock = dal_hw_ddc_create, >- .create_generic = NULL, >- .create_hpd = dal_hw_hpd_create, >- .create_sync = NULL, >- .create_gsl = NULL, >+ .init_ddc_data = dal_hw_ddc_init, >+ .init_generic = dal_hw_generic_init, >+ .init_hpd = dal_hw_hpd_init, >+ .get_ddc_pin = dal_hw_ddc_get_pin, >+ .get_hpd_pin = dal_hw_hpd_get_pin, >+ .get_generic_pin = dal_hw_generic_get_pin, > .define_hpd_registers = define_hpd_registers, >- .define_ddc_registers = define_ddc_registers >+ .define_ddc_registers = define_ddc_registers, >+ .define_generic_registers = define_generic_registers, > }; > /* > * dal_hw_factory_dcn10_init >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c 2019-08-31 15:01:11.869736169 -0500 >@@ -71,7 +71,7 @@ > { > switch (offset) { > /* GENERIC */ >- case REG(DC_GENERICA): >+ case REG(DC_GPIO_GENERIC_A): > *id = GPIO_ID_GENERIC; > switch (mask) { > case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK: >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c 2019-08-31 15:01:11.869736169 -0500 >@@ -0,0 +1,210 @@ >+/* >+ * Copyright 2013-15 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+#if defined(CONFIG_DRM_AMD_DC_DCN2_0) >+#include "dm_services.h" >+#include "include/gpio_types.h" >+#include "../hw_factory.h" >+ >+ >+#include "../hw_gpio.h" >+#include "../hw_ddc.h" >+#include "../hw_hpd.h" >+#include "../hw_generic.h" >+ >+#include "hw_factory_dcn21.h" >+ >+ >+#include "dcn/dcn_2_1_0_offset.h" >+#include "dcn/dcn_2_1_0_sh_mask.h" >+#include "renoir_ip_offset.h" >+ >+ >+#include "reg_helper.h" >+#include "../hpd_regs.h" >+/* begin ********************* >+ * macros to expend register list macro defined in HW object header file */ >+ >+/* DCN */ >+#define block HPD >+#define reg_num 0 >+ >+#undef BASE_INNER >+#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg >+ >+#define BASE(seg) BASE_INNER(seg) >+ >+ >+ >+#define REG(reg_name)\ >+ BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name >+ >+#define SF_HPD(reg_name, field_name, post_fix)\ >+ .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix >+ >+#define REGI(reg_name, block, id)\ >+ BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ >+ mm ## block ## id ## _ ## reg_name >+ >+#define SF(reg_name, field_name, post_fix)\ >+ .field_name = reg_name ## __ ## field_name ## post_fix >+ >+/* macros to expend register list macro defined in HW object header file >+ * end *********************/ >+ >+ >+ >+#define hpd_regs(id) \ >+{\ >+ HPD_REG_LIST(id)\ >+} >+ >+static const struct hpd_registers hpd_regs[] = { >+ hpd_regs(0), >+ hpd_regs(1), >+ hpd_regs(2), >+ hpd_regs(3), >+ hpd_regs(4), >+}; >+ >+static const struct hpd_sh_mask hpd_shift = { >+ HPD_MASK_SH_LIST(__SHIFT) >+}; >+ >+static const struct hpd_sh_mask hpd_mask = { >+ HPD_MASK_SH_LIST(_MASK) >+}; >+ >+#include "../ddc_regs.h" >+ >+ /* set field name */ >+#define SF_DDC(reg_name, field_name, post_fix)\ >+ .field_name = reg_name ## __ ## field_name ## post_fix >+ >+static const struct ddc_registers ddc_data_regs_dcn[] = { >+ ddc_data_regs_dcn2(1), >+ ddc_data_regs_dcn2(2), >+ ddc_data_regs_dcn2(3), >+ ddc_data_regs_dcn2(4), >+ ddc_data_regs_dcn2(5), >+}; >+ >+static const struct ddc_registers ddc_clk_regs_dcn[] = { >+ ddc_clk_regs_dcn2(1), >+ ddc_clk_regs_dcn2(2), >+ ddc_clk_regs_dcn2(3), >+ ddc_clk_regs_dcn2(4), >+ ddc_clk_regs_dcn2(5), >+}; >+ >+static const struct ddc_sh_mask ddc_shift[] = { >+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), >+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), >+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), >+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), >+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), >+ DDC_MASK_SH_LIST_DCN2(__SHIFT, 6) >+}; >+ >+static const struct ddc_sh_mask ddc_mask[] = { >+ DDC_MASK_SH_LIST_DCN2(_MASK, 1), >+ DDC_MASK_SH_LIST_DCN2(_MASK, 2), >+ DDC_MASK_SH_LIST_DCN2(_MASK, 3), >+ DDC_MASK_SH_LIST_DCN2(_MASK, 4), >+ DDC_MASK_SH_LIST_DCN2(_MASK, 5), >+ DDC_MASK_SH_LIST_DCN2(_MASK, 6) >+}; >+ >+static void define_ddc_registers( >+ struct hw_gpio_pin *pin, >+ uint32_t en) >+{ >+ struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); >+ >+ switch (pin->id) { >+ case GPIO_ID_DDC_DATA: >+ ddc->regs = &ddc_data_regs_dcn[en]; >+ ddc->base.regs = &ddc_data_regs_dcn[en].gpio; >+ break; >+ case GPIO_ID_DDC_CLOCK: >+ ddc->regs = &ddc_clk_regs_dcn[en]; >+ ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; >+ break; >+ default: >+ ASSERT_CRITICAL(false); >+ return; >+ } >+ >+ ddc->shifts = &ddc_shift[en]; >+ ddc->masks = &ddc_mask[en]; >+ >+} >+ >+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) >+{ >+ struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); >+ >+ hpd->regs = &hpd_regs[en]; >+ hpd->shifts = &hpd_shift; >+ hpd->masks = &hpd_mask; >+ hpd->base.regs = &hpd_regs[en].gpio; >+} >+ >+ >+/* fucntion table */ >+static const struct hw_factory_funcs funcs = { >+ .init_ddc_data = dal_hw_ddc_init, >+ .init_generic = dal_hw_generic_init, >+ .init_hpd = dal_hw_hpd_init, >+ .get_ddc_pin = dal_hw_ddc_get_pin, >+ .get_hpd_pin = dal_hw_hpd_get_pin, >+ .get_generic_pin = dal_hw_generic_get_pin, >+ .define_hpd_registers = define_hpd_registers, >+ .define_ddc_registers = define_ddc_registers >+}; >+/* >+ * dal_hw_factory_dcn10_init >+ * >+ * @brief >+ * Initialize HW factory function pointers and pin info >+ * >+ * @param >+ * struct hw_factory *factory - [out] struct of function pointers >+ */ >+void dal_hw_factory_dcn21_init(struct hw_factory *factory) >+{ >+ /*TODO check ASIC CAPs*/ >+ factory->number_of_pins[GPIO_ID_DDC_DATA] = 8; >+ factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8; >+ factory->number_of_pins[GPIO_ID_GENERIC] = 4; >+ factory->number_of_pins[GPIO_ID_HPD] = 6; >+ factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; >+ factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; >+ factory->number_of_pins[GPIO_ID_SYNC] = 0; >+ factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/ >+ >+ factory->funcs = &funcs; >+} >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h 2019-08-31 15:01:11.869736169 -0500 >@@ -0,0 +1,33 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#ifndef __DAL_HW_FACTORY_DCN21_H__ >+#define __DAL_HW_FACTORY_DCN21_H__ >+ >+/* Initialize HW factory function pointers and pin info */ >+void dal_hw_factory_dcn21_init(struct hw_factory *factory); >+ >+#endif /* __DAL_HW_FACTORY_DCN20_H__ */ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c 2019-08-31 15:01:11.869736169 -0500 >@@ -0,0 +1,386 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+/* >+ * Pre-requisites: headers required by header of this unit >+ */ >+#if defined(CONFIG_DRM_AMD_DC_DCN2_0) >+#include "hw_translate_dcn21.h" >+ >+#include "dm_services.h" >+#include "include/gpio_types.h" >+#include "../hw_translate.h" >+ >+#include "dcn/dcn_2_1_0_offset.h" >+#include "dcn/dcn_2_1_0_sh_mask.h" >+#include "renoir_ip_offset.h" >+ >+ >+ >+ >+/* begin ********************* >+ * macros to expend register list macro defined in HW object header file */ >+ >+/* DCN */ >+#define block HPD >+#define reg_num 0 >+ >+#undef BASE_INNER >+#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg >+ >+#define BASE(seg) BASE_INNER(seg) >+ >+#undef REG >+#define REG(reg_name)\ >+ BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name >+#define SF_HPD(reg_name, field_name, post_fix)\ >+ .field_name = reg_name ## __ ## field_name ## post_fix >+ >+ >+/* macros to expend register list macro defined in HW object header file >+ * end *********************/ >+ >+ >+static bool offset_to_id( >+ uint32_t offset, >+ uint32_t mask, >+ enum gpio_id *id, >+ uint32_t *en) >+{ >+ switch (offset) { >+ /* GENERIC */ >+ case REG(DC_GENERICA): >+ *id = GPIO_ID_GENERIC; >+ switch (mask) { >+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK: >+ *en = GPIO_GENERIC_A; >+ return true; >+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK: >+ *en = GPIO_GENERIC_B; >+ return true; >+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK: >+ *en = GPIO_GENERIC_C; >+ return true; >+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK: >+ *en = GPIO_GENERIC_D; >+ return true; >+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK: >+ *en = GPIO_GENERIC_E; >+ return true; >+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK: >+ *en = GPIO_GENERIC_F; >+ return true; >+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK: >+ *en = GPIO_GENERIC_G; >+ return true; >+ default: >+ ASSERT_CRITICAL(false); >+#ifdef PALLADIUM_SUPPORTED >+ *en = GPIO_DDC_LINE_DDC1; >+ return true; >+#endif >+ return false; >+ } >+ break; >+ /* HPD */ >+ case REG(DC_GPIO_HPD_A): >+ *id = GPIO_ID_HPD; >+ switch (mask) { >+ case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK: >+ *en = GPIO_HPD_1; >+ return true; >+ case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK: >+ *en = GPIO_HPD_2; >+ return true; >+ case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK: >+ *en = GPIO_HPD_3; >+ return true; >+ case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK: >+ *en = GPIO_HPD_4; >+ return true; >+ case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK: >+ *en = GPIO_HPD_5; >+ return true; >+ case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK: >+ *en = GPIO_HPD_6; >+ return true; >+ default: >+ ASSERT_CRITICAL(false); >+ return false; >+ } >+ break; >+ /* REG(DC_GPIO_GENLK_MASK */ >+ case REG(DC_GPIO_GENLK_A): >+ *id = GPIO_ID_GSL; >+ switch (mask) { >+ case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK: >+ *en = GPIO_GSL_GENLOCK_CLOCK; >+ return true; >+ case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK: >+ *en = GPIO_GSL_GENLOCK_VSYNC; >+ return true; >+ case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK: >+ *en = GPIO_GSL_SWAPLOCK_A; >+ return true; >+ case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK: >+ *en = GPIO_GSL_SWAPLOCK_B; >+ return true; >+ default: >+ ASSERT_CRITICAL(false); >+ return false; >+ } >+ break; >+ /* DDC */ >+ /* we don't care about the GPIO_ID for DDC >+ * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK >+ * directly in the create method */ >+ case REG(DC_GPIO_DDC1_A): >+ *en = GPIO_DDC_LINE_DDC1; >+ return true; >+ case REG(DC_GPIO_DDC2_A): >+ *en = GPIO_DDC_LINE_DDC2; >+ return true; >+ case REG(DC_GPIO_DDC3_A): >+ *en = GPIO_DDC_LINE_DDC3; >+ return true; >+ case REG(DC_GPIO_DDC4_A): >+ *en = GPIO_DDC_LINE_DDC4; >+ return true; >+ case REG(DC_GPIO_DDC5_A): >+ *en = GPIO_DDC_LINE_DDC5; >+ return true; >+ case REG(DC_GPIO_DDCVGA_A): >+ *en = GPIO_DDC_LINE_DDC_VGA; >+ return true; >+ >+// case REG(DC_GPIO_I2CPAD_A): not exit >+// case REG(DC_GPIO_PWRSEQ_A): >+// case REG(DC_GPIO_PAD_STRENGTH_1): >+// case REG(DC_GPIO_PAD_STRENGTH_2): >+// case REG(DC_GPIO_DEBUG): >+ /* UNEXPECTED */ >+ default: >+// case REG(DC_GPIO_SYNCA_A): not exist >+#ifdef PALLADIUM_SUPPORTED >+ *id = GPIO_ID_HPD; >+ *en = GPIO_DDC_LINE_DDC1; >+ return true; >+#endif >+ ASSERT_CRITICAL(false); >+ return false; >+ } >+} >+ >+static bool id_to_offset( >+ enum gpio_id id, >+ uint32_t en, >+ struct gpio_pin_info *info) >+{ >+ bool result = true; >+ >+ switch (id) { >+ case GPIO_ID_DDC_DATA: >+ info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK; >+ switch (en) { >+ case GPIO_DDC_LINE_DDC1: >+ info->offset = REG(DC_GPIO_DDC1_A); >+ break; >+ case GPIO_DDC_LINE_DDC2: >+ info->offset = REG(DC_GPIO_DDC2_A); >+ break; >+ case GPIO_DDC_LINE_DDC3: >+ info->offset = REG(DC_GPIO_DDC3_A); >+ break; >+ case GPIO_DDC_LINE_DDC4: >+ info->offset = REG(DC_GPIO_DDC4_A); >+ break; >+ case GPIO_DDC_LINE_DDC5: >+ info->offset = REG(DC_GPIO_DDC5_A); >+ break; >+ case GPIO_DDC_LINE_DDC_VGA: >+ info->offset = REG(DC_GPIO_DDCVGA_A); >+ break; >+ case GPIO_DDC_LINE_I2C_PAD: >+ default: >+ ASSERT_CRITICAL(false); >+ result = false; >+ } >+ break; >+ case GPIO_ID_DDC_CLOCK: >+ info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK; >+ switch (en) { >+ case GPIO_DDC_LINE_DDC1: >+ info->offset = REG(DC_GPIO_DDC1_A); >+ break; >+ case GPIO_DDC_LINE_DDC2: >+ info->offset = REG(DC_GPIO_DDC2_A); >+ break; >+ case GPIO_DDC_LINE_DDC3: >+ info->offset = REG(DC_GPIO_DDC3_A); >+ break; >+ case GPIO_DDC_LINE_DDC4: >+ info->offset = REG(DC_GPIO_DDC4_A); >+ break; >+ case GPIO_DDC_LINE_DDC5: >+ info->offset = REG(DC_GPIO_DDC5_A); >+ break; >+ case GPIO_DDC_LINE_DDC_VGA: >+ info->offset = REG(DC_GPIO_DDCVGA_A); >+ break; >+ case GPIO_DDC_LINE_I2C_PAD: >+ default: >+ ASSERT_CRITICAL(false); >+ result = false; >+ } >+ break; >+ case GPIO_ID_GENERIC: >+ info->offset = REG(DC_GPIO_GENERIC_A); >+ switch (en) { >+ case GPIO_GENERIC_A: >+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; >+ break; >+ case GPIO_GENERIC_B: >+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; >+ break; >+ case GPIO_GENERIC_C: >+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; >+ break; >+ case GPIO_GENERIC_D: >+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; >+ break; >+ case GPIO_GENERIC_E: >+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; >+ break; >+ case GPIO_GENERIC_F: >+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; >+ break; >+ case GPIO_GENERIC_G: >+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; >+ break; >+ default: >+ ASSERT_CRITICAL(false); >+ result = false; >+ } >+ break; >+ case GPIO_ID_HPD: >+ info->offset = REG(DC_GPIO_HPD_A); >+ switch (en) { >+ case GPIO_HPD_1: >+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; >+ break; >+ case GPIO_HPD_2: >+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; >+ break; >+ case GPIO_HPD_3: >+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; >+ break; >+ case GPIO_HPD_4: >+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; >+ break; >+ case GPIO_HPD_5: >+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; >+ break; >+ case GPIO_HPD_6: >+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; >+ break; >+ default: >+ ASSERT_CRITICAL(false); >+#ifdef PALLADIUM_SUPPORTED >+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; >+ result = true; >+#endif >+ result = false; >+ } >+ break; >+ case GPIO_ID_GSL: >+ switch (en) { >+ case GPIO_GSL_GENLOCK_CLOCK: >+ /*not implmented*/ >+ ASSERT_CRITICAL(false); >+ result = false; >+ break; >+ case GPIO_GSL_GENLOCK_VSYNC: >+ /*not implmented*/ >+ ASSERT_CRITICAL(false); >+ result = false; >+ break; >+ case GPIO_GSL_SWAPLOCK_A: >+ /*not implmented*/ >+ ASSERT_CRITICAL(false); >+ result = false; >+ break; >+ case GPIO_GSL_SWAPLOCK_B: >+ /*not implmented*/ >+ ASSERT_CRITICAL(false); >+ result = false; >+ >+ break; >+ default: >+ ASSERT_CRITICAL(false); >+ result = false; >+ } >+ break; >+ case GPIO_ID_SYNC: >+ case GPIO_ID_VIP_PAD: >+ default: >+ ASSERT_CRITICAL(false); >+ result = false; >+ } >+ >+ if (result) { >+ info->offset_y = info->offset + 2; >+ info->offset_en = info->offset + 1; >+ info->offset_mask = info->offset - 1; >+ >+ info->mask_y = info->mask; >+ info->mask_en = info->mask; >+ info->mask_mask = info->mask; >+ } >+ >+ return result; >+} >+ >+/* function table */ >+static const struct hw_translate_funcs funcs = { >+ .offset_to_id = offset_to_id, >+ .id_to_offset = id_to_offset, >+}; >+ >+/* >+ * dal_hw_translate_dcn10_init >+ * >+ * @brief >+ * Initialize Hw translate function pointers. >+ * >+ * @param >+ * struct hw_translate *tr - [out] struct of function pointers >+ * >+ */ >+void dal_hw_translate_dcn21_init(struct hw_translate *tr) >+{ >+ tr->funcs = &funcs; >+} >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h 2019-08-31 15:01:11.869736169 -0500 >@@ -0,0 +1,35 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#ifndef __DAL_HW_TRANSLATE_DCN21_H__ >+#define __DAL_HW_TRANSLATE_DCN21_H__ >+ >+struct hw_translate; >+ >+/* Initialize Hw translate function pointers */ >+void dal_hw_translate_dcn21_init(struct hw_translate *tr); >+ >+#endif /* __DAL_HW_TRANSLATE_DCN21_H__ */ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c 2019-08-31 15:01:11.869736169 -0500 >@@ -38,15 +38,13 @@ > #include "../hw_gpio.h" > #include "../hw_ddc.h" > #include "../hw_hpd.h" >+#include "../hw_generic.h" > > /* function table */ > static const struct hw_factory_funcs funcs = { >- .create_ddc_data = NULL, >- .create_ddc_clock = NULL, >- .create_generic = NULL, >- .create_hpd = NULL, >- .create_sync = NULL, >- .create_gsl = NULL, >+ .init_ddc_data = NULL, >+ .init_generic = NULL, >+ .init_hpd = NULL, > }; > > void dal_hw_factory_diag_fpga_init(struct hw_factory *factory) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h 2019-08-31 15:01:11.869736169 -0500 >@@ -0,0 +1,66 @@ >+/* >+ * Copyright 2012-16 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_ >+#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_ >+ >+#include "gpio_regs.h" >+ >+#define GENERIC_GPIO_REG_LIST_ENTRY(type, cd, id) \ >+ .type ## _reg = REG(DC_GPIO_GENERIC_## type),\ >+ .type ## _mask = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\ >+ .type ## _shift = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## __SHIFT >+ >+#define GENERIC_GPIO_REG_LIST(id) \ >+ {\ >+ GENERIC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\ >+ GENERIC_GPIO_REG_LIST_ENTRY(A, cd, id),\ >+ GENERIC_GPIO_REG_LIST_ENTRY(EN, cd, id),\ >+ GENERIC_GPIO_REG_LIST_ENTRY(Y, cd, id)\ >+ } >+ >+#define GENERIC_REG_LIST(id) \ >+ GENERIC_GPIO_REG_LIST(id), \ >+ .mux = REG(DC_GENERIC ## id),\ >+ >+#define GENERIC_MASK_SH_LIST(mask_sh, cd) \ >+ {(DC_GENERIC ## cd ##__GENERIC ## cd ##_EN## mask_sh),\ >+ (DC_GENERIC ## cd ##__GENERIC ## cd ##_SEL## mask_sh)} >+ >+struct generic_registers { >+ struct gpio_registers gpio; >+ uint32_t mux; >+}; >+ >+struct generic_sh_mask { >+ /* enable */ >+ uint32_t GENERIC_EN; >+ /* select */ >+ uint32_t GENERIC_SEL; >+ >+}; >+ >+ >+#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c 2019-08-31 15:01:11.869736169 -0500 >@@ -67,10 +67,14 @@ > return GPIO_RESULT_ALREADY_OPENED; > } > >+ // No action if allocation failed during gpio construct >+ if (!gpio->hw_container.ddc) { >+ ASSERT_CRITICAL(false); >+ return GPIO_RESULT_NON_SPECIFIC_ERROR; >+ } > gpio->mode = mode; > >- return dal_gpio_service_open( >- gpio->service, gpio->id, gpio->en, mode, &gpio->pin); >+ return dal_gpio_service_open(gpio); > } > > enum gpio_result dal_gpio_get_value( >@@ -231,6 +235,21 @@ > return gpio->output_state; > } > >+struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio) >+{ >+ return gpio->hw_container.ddc; >+} >+ >+struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio) >+{ >+ return gpio->hw_container.hpd; >+} >+ >+struct hw_generic *dal_gpio_get_generic(struct gpio *gpio) >+{ >+ return gpio->hw_container.generic; >+} >+ > void dal_gpio_close( > struct gpio *gpio) > { >@@ -267,6 +286,30 @@ > gpio->mode = GPIO_MODE_UNKNOWN; > gpio->output_state = output_state; > >+ //initialize hw_container union based on id >+ switch (gpio->id) { >+ case GPIO_ID_DDC_DATA: >+ gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); >+ break; >+ case GPIO_ID_DDC_CLOCK: >+ gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); >+ break; >+ case GPIO_ID_GENERIC: >+ gpio->service->factory.funcs->init_generic(&gpio->hw_container.generic, service->ctx, id, en); >+ break; >+ case GPIO_ID_HPD: >+ gpio->service->factory.funcs->init_hpd(&gpio->hw_container.hpd, service->ctx, id, en); >+ break; >+ // TODO: currently gpio for sync and gsl does not get created, might need it later >+ case GPIO_ID_SYNC: >+ break; >+ case GPIO_ID_GSL: >+ break; >+ default: >+ ASSERT_CRITICAL(false); >+ gpio->pin = NULL; >+ } >+ > return gpio; > } > >@@ -280,6 +323,33 @@ > > dal_gpio_close(*gpio); > >+ switch ((*gpio)->id) { >+ case GPIO_ID_DDC_DATA: >+ kfree((*gpio)->hw_container.ddc); >+ (*gpio)->hw_container.ddc = NULL; >+ break; >+ case GPIO_ID_DDC_CLOCK: >+ //TODO: might want to change it to init_ddc_clock >+ kfree((*gpio)->hw_container.ddc); >+ (*gpio)->hw_container.ddc = NULL; >+ break; >+ case GPIO_ID_GENERIC: >+ kfree((*gpio)->hw_container.generic); >+ (*gpio)->hw_container.generic = NULL; >+ break; >+ case GPIO_ID_HPD: >+ kfree((*gpio)->hw_container.hpd); >+ (*gpio)->hw_container.hpd = NULL; >+ break; >+ // TODO: currently gpio for sync and gsl does not get created, might need it later >+ case GPIO_ID_SYNC: >+ break; >+ case GPIO_ID_GSL: >+ break; >+ default: >+ break; >+ } >+ > kfree(*gpio); > > *gpio = NULL; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c 2019-08-31 15:01:11.870736169 -0500 >@@ -141,6 +141,58 @@ > return dal_gpio_create_irq(service, id, en); > } > >+struct gpio *dal_gpio_service_create_generic_mux( >+ struct gpio_service *service, >+ uint32_t offset, >+ uint32_t mask) >+{ >+ enum gpio_id id; >+ uint32_t en; >+ struct gpio *generic; >+ >+ if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) { >+ ASSERT_CRITICAL(false); >+ return NULL; >+ } >+ >+ generic = dal_gpio_create( >+ service, id, en, GPIO_PIN_OUTPUT_STATE_DEFAULT); >+ >+ return generic; >+} >+ >+void dal_gpio_destroy_generic_mux( >+ struct gpio **mux) >+{ >+ if (!mux || !*mux) { >+ ASSERT_CRITICAL(false); >+ return; >+ } >+ >+ dal_gpio_close(*mux); >+ dal_gpio_destroy(mux); >+ kfree(*mux); >+ >+ *mux = NULL; >+} >+ >+struct gpio_pin_info dal_gpio_get_generic_pin_info( >+ struct gpio_service *service, >+ enum gpio_id id, >+ uint32_t en) >+{ >+ struct gpio_pin_info pin; >+ >+ if (service->translate.funcs->id_to_offset) { >+ service->translate.funcs->id_to_offset(id, en, &pin); >+ } else { >+ pin.mask = 0xFFFFFFFF; >+ pin.offset = 0xFFFFFFFF; >+ } >+ >+ return pin; >+} >+ > void dal_gpio_service_destroy( > struct gpio_service **ptr) > { >@@ -165,6 +217,21 @@ > *ptr = NULL; > } > >+enum gpio_result dal_mux_setup_config( >+ struct gpio *mux, >+ struct gpio_generic_mux_config *config) >+{ >+ struct gpio_config_data config_data; >+ >+ if (!config) >+ return GPIO_RESULT_INVALID_DATA; >+ >+ config_data.config.generic_mux = *config; >+ config_data.type = GPIO_CONFIG_TYPE_GENERIC_MUX; >+ >+ return dal_gpio_set_config(mux, &config_data); >+} >+ > /* > * @brief > * Private API. >@@ -223,13 +290,15 @@ > } > > enum gpio_result dal_gpio_service_open( >- struct gpio_service *service, >- enum gpio_id id, >- uint32_t en, >- enum gpio_mode mode, >- struct hw_gpio_pin **ptr) >+ struct gpio *gpio) > { >- struct hw_gpio_pin *pin; >+ struct gpio_service *service = gpio->service; >+ enum gpio_id id = gpio->id; >+ uint32_t en = gpio->en; >+ enum gpio_mode mode = gpio->mode; >+ >+ struct hw_gpio_pin **pin = &gpio->pin; >+ > > if (!service->busyness[id]) { > ASSERT_CRITICAL(false); >@@ -243,50 +312,43 @@ > > switch (id) { > case GPIO_ID_DDC_DATA: >- pin = service->factory.funcs->create_ddc_data( >- service->ctx, id, en); >- service->factory.funcs->define_ddc_registers(pin, en); >+ *pin = service->factory.funcs->get_ddc_pin(gpio); >+ service->factory.funcs->define_ddc_registers(*pin, en); > break; > case GPIO_ID_DDC_CLOCK: >- pin = service->factory.funcs->create_ddc_clock( >- service->ctx, id, en); >- service->factory.funcs->define_ddc_registers(pin, en); >+ *pin = service->factory.funcs->get_ddc_pin(gpio); >+ service->factory.funcs->define_ddc_registers(*pin, en); > break; > case GPIO_ID_GENERIC: >- pin = service->factory.funcs->create_generic( >- service->ctx, id, en); >+ *pin = service->factory.funcs->get_generic_pin(gpio); >+ service->factory.funcs->define_generic_registers(*pin, en); > break; > case GPIO_ID_HPD: >- pin = service->factory.funcs->create_hpd( >- service->ctx, id, en); >- service->factory.funcs->define_hpd_registers(pin, en); >+ *pin = service->factory.funcs->get_hpd_pin(gpio); >+ service->factory.funcs->define_hpd_registers(*pin, en); > break; >+ >+ //TODO: gsl and sync support? create_sync and create_gsl are NULL > case GPIO_ID_SYNC: >- pin = service->factory.funcs->create_sync( >- service->ctx, id, en); >- break; > case GPIO_ID_GSL: >- pin = service->factory.funcs->create_gsl( >- service->ctx, id, en); > break; > default: > ASSERT_CRITICAL(false); > return GPIO_RESULT_NON_SPECIFIC_ERROR; > } > >- if (!pin) { >+ if (!*pin) { > ASSERT_CRITICAL(false); > return GPIO_RESULT_NON_SPECIFIC_ERROR; > } > >- if (!pin->funcs->open(pin, mode)) { >+ if (!(*pin)->funcs->open(*pin, mode)) { > ASSERT_CRITICAL(false); >- dal_gpio_service_close(service, &pin); >+ dal_gpio_service_close(service, pin); > return GPIO_RESULT_OPEN_FAILED; > } > > set_pin_busy(service, id, en); >- *ptr = pin; > return GPIO_RESULT_OK; > } > >@@ -308,11 +370,10 @@ > > pin->funcs->close(pin); > >- pin->funcs->destroy(ptr); >+ *ptr = NULL; > } > } > >- > enum dc_irq_source dal_irq_get_source( > const struct gpio *irq) > { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h 2019-08-31 15:01:11.870736169 -0500 >@@ -42,11 +42,7 @@ > }; > > enum gpio_result dal_gpio_service_open( >- struct gpio_service *service, >- enum gpio_id id, >- uint32_t en, >- enum gpio_mode mode, >- struct hw_gpio_pin **ptr); >+ struct gpio *gpio); > > void dal_gpio_service_close( > struct gpio_service *service, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 2019-08-31 15:01:11.870736169 -0500 >@@ -28,6 +28,7 @@ > > #include "dm_services.h" > >+#include "include/gpio_interface.h" > #include "include/gpio_types.h" > #include "hw_gpio.h" > #include "hw_ddc.h" >@@ -45,6 +46,8 @@ > #define REG(reg)\ > (ddc->regs->reg) > >+struct gpio; >+ > static void destruct( > struct hw_ddc *pin) > { >@@ -227,24 +230,29 @@ > ddc->base.base.funcs = &funcs; > } > >-struct hw_gpio_pin *dal_hw_ddc_create( >+void dal_hw_ddc_init( >+ struct hw_ddc **hw_ddc, > struct dc_context *ctx, > enum gpio_id id, > uint32_t en) > { >- struct hw_ddc *pin; >- > if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { > ASSERT_CRITICAL(false); >- return NULL; >+ *hw_ddc = NULL; > } > >- pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); >- if (!pin) { >+ *hw_ddc = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); >+ if (!*hw_ddc) { > ASSERT_CRITICAL(false); >- return NULL; >+ return; > } > >- construct(pin, id, en, ctx); >- return &pin->base.base; >+ construct(*hw_ddc, id, en, ctx); >+} >+ >+struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio) >+{ >+ struct hw_ddc *hw_ddc = dal_gpio_get_ddc(gpio); >+ >+ return &hw_ddc->base.base; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h 2019-08-31 15:01:11.870736169 -0500 >@@ -38,9 +38,12 @@ > #define HW_DDC_FROM_BASE(hw_gpio) \ > container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_ddc, base) > >-struct hw_gpio_pin *dal_hw_ddc_create( >+void dal_hw_ddc_init( >+ struct hw_ddc **hw_ddc, > struct dc_context *ctx, > enum gpio_id id, > uint32_t en); > >+struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio); >+ > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c 2019-08-31 15:01:11.870736169 -0500 >@@ -51,6 +51,9 @@ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #include "dcn20/hw_factory_dcn20.h" > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#include "dcn21/hw_factory_dcn21.h" >+#endif > > #include "diagnostics/hw_factory_diag.h" > >@@ -99,6 +102,11 @@ > dal_hw_factory_dcn20_init(factory); > return true; > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ case DCN_VERSION_2_1: >+ dal_hw_factory_dcn21_init(factory); >+ return true; >+#endif > > default: > ASSERT_CRITICAL(false); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h 2019-08-31 15:01:11.870736169 -0500 >@@ -28,41 +28,44 @@ > > struct hw_gpio_pin; > struct hw_hpd; >+struct hw_ddc; >+struct hw_generic; >+struct gpio; > > struct hw_factory { > uint32_t number_of_pins[GPIO_ID_COUNT]; > > const struct hw_factory_funcs { >- struct hw_gpio_pin *(*create_ddc_data)( >- struct dc_context *ctx, >- enum gpio_id id, >- uint32_t en); >- struct hw_gpio_pin *(*create_ddc_clock)( >- struct dc_context *ctx, >- enum gpio_id id, >- uint32_t en); >- struct hw_gpio_pin *(*create_generic)( >- struct dc_context *ctx, >- enum gpio_id id, >- uint32_t en); >- struct hw_gpio_pin *(*create_hpd)( >- struct dc_context *ctx, >- enum gpio_id id, >- uint32_t en); >- struct hw_gpio_pin *(*create_sync)( >- struct dc_context *ctx, >- enum gpio_id id, >- uint32_t en); >- struct hw_gpio_pin *(*create_gsl)( >- struct dc_context *ctx, >- enum gpio_id id, >- uint32_t en); >+ void (*init_ddc_data)( >+ struct hw_ddc **hw_ddc, >+ struct dc_context *ctx, >+ enum gpio_id id, >+ uint32_t en); >+ void (*init_generic)( >+ struct hw_generic **hw_generic, >+ struct dc_context *ctx, >+ enum gpio_id id, >+ uint32_t en); >+ void (*init_hpd)( >+ struct hw_hpd **hw_hpd, >+ struct dc_context *ctx, >+ enum gpio_id id, >+ uint32_t en); >+ struct hw_gpio_pin *(*get_hpd_pin)( >+ struct gpio *gpio); >+ struct hw_gpio_pin *(*get_ddc_pin)( >+ struct gpio *gpio); >+ struct hw_gpio_pin *(*get_generic_pin)( >+ struct gpio *gpio); > void (*define_hpd_registers)( > struct hw_gpio_pin *pin, > uint32_t en); > void (*define_ddc_registers)( > struct hw_gpio_pin *pin, > uint32_t en); >+ void (*define_generic_registers)( >+ struct hw_gpio_pin *pin, >+ uint32_t en); > } *funcs; > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c 2019-08-31 15:01:11.870736169 -0500 >@@ -0,0 +1,138 @@ >+/* >+ * Copyright 2012-15 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#include <linux/slab.h> >+ >+#include "dm_services.h" >+ >+#include "include/gpio_interface.h" >+#include "include/gpio_types.h" >+#include "hw_gpio.h" >+#include "hw_generic.h" >+ >+#include "reg_helper.h" >+#include "generic_regs.h" >+ >+#undef FN >+#define FN(reg_name, field_name) \ >+ generic->shifts->field_name, generic->masks->field_name >+ >+#define CTX \ >+ generic->base.base.ctx >+#define REG(reg)\ >+ (generic->regs->reg) >+ >+struct gpio; >+ >+static void dal_hw_generic_construct( >+ struct hw_generic *pin, >+ enum gpio_id id, >+ uint32_t en, >+ struct dc_context *ctx) >+{ >+ dal_hw_gpio_construct(&pin->base, id, en, ctx); >+} >+ >+static void dal_hw_generic_destruct( >+ struct hw_generic *pin) >+{ >+ dal_hw_gpio_destruct(&pin->base); >+} >+ >+static void destroy( >+ struct hw_gpio_pin **ptr) >+{ >+ struct hw_generic *generic = HW_GENERIC_FROM_BASE(*ptr); >+ >+ dal_hw_generic_destruct(generic); >+ >+ kfree(generic); >+ >+ *ptr = NULL; >+} >+ >+static enum gpio_result set_config( >+ struct hw_gpio_pin *ptr, >+ const struct gpio_config_data *config_data) >+{ >+ struct hw_generic *generic = HW_GENERIC_FROM_BASE(ptr); >+ >+ if (!config_data) >+ return GPIO_RESULT_INVALID_DATA; >+ >+ REG_UPDATE_2(mux, >+ GENERIC_EN, config_data->config.generic_mux.enable_output_from_mux, >+ GENERIC_SEL, config_data->config.generic_mux.mux_select); >+ >+ return GPIO_RESULT_OK; >+} >+ >+static const struct hw_gpio_pin_funcs funcs = { >+ .destroy = destroy, >+ .open = dal_hw_gpio_open, >+ .get_value = dal_hw_gpio_get_value, >+ .set_value = dal_hw_gpio_set_value, >+ .set_config = set_config, >+ .change_mode = dal_hw_gpio_change_mode, >+ .close = dal_hw_gpio_close, >+}; >+ >+static void construct( >+ struct hw_generic *generic, >+ enum gpio_id id, >+ uint32_t en, >+ struct dc_context *ctx) >+{ >+ dal_hw_generic_construct(generic, id, en, ctx); >+ generic->base.base.funcs = &funcs; >+} >+ >+void dal_hw_generic_init( >+ struct hw_generic **hw_generic, >+ struct dc_context *ctx, >+ enum gpio_id id, >+ uint32_t en) >+{ >+ if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { >+ ASSERT_CRITICAL(false); >+ *hw_generic = NULL; >+ } >+ >+ *hw_generic = kzalloc(sizeof(struct hw_generic), GFP_KERNEL); >+ if (!*hw_generic) { >+ ASSERT_CRITICAL(false); >+ return; >+ } >+ >+ construct(*hw_generic, id, en, ctx); >+} >+ >+ >+struct hw_gpio_pin *dal_hw_generic_get_pin(struct gpio *gpio) >+{ >+ struct hw_generic *hw_generic = dal_gpio_get_generic(gpio); >+ >+ return &hw_generic->base.base; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h 2019-08-31 15:01:11.870736169 -0500 >@@ -0,0 +1,50 @@ >+/* >+ * Copyright 2012-15 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef __DAL_HW_generic_H__ >+#define __DAL_HW_generic_H__ >+ >+#include "generic_regs.h" >+#include "hw_gpio.h" >+ >+struct hw_generic { >+ struct hw_gpio base; >+ const struct generic_registers *regs; >+ const struct generic_sh_mask *shifts; >+ const struct generic_sh_mask *masks; >+}; >+ >+#define HW_GENERIC_FROM_BASE(hw_gpio) \ >+ container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_generic, base) >+ >+void dal_hw_generic_init( >+ struct hw_generic **hw_generic, >+ struct dc_context *ctx, >+ enum gpio_id id, >+ uint32_t en); >+ >+struct hw_gpio_pin *dal_hw_generic_get_pin(struct gpio *gpio); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c 2019-08-31 15:01:11.870736169 -0500 >@@ -27,6 +27,7 @@ > > #include "dm_services.h" > >+#include "include/gpio_interface.h" > #include "include/gpio_types.h" > #include "hw_gpio.h" > #include "hw_hpd.h" >@@ -43,6 +44,8 @@ > #define REG(reg)\ > (hpd->regs->reg) > >+struct gpio; >+ > static void dal_hw_hpd_construct( > struct hw_hpd *pin, > enum gpio_id id, >@@ -136,29 +139,29 @@ > hpd->base.base.funcs = &funcs; > } > >-struct hw_gpio_pin *dal_hw_hpd_create( >+void dal_hw_hpd_init( >+ struct hw_hpd **hw_hpd, > struct dc_context *ctx, > enum gpio_id id, > uint32_t en) > { >- struct hw_hpd *hpd; >- >- if (id != GPIO_ID_HPD) { >+ if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { > ASSERT_CRITICAL(false); >- return NULL; >+ *hw_hpd = NULL; > } > >- if ((en < GPIO_HPD_MIN) || (en > GPIO_HPD_MAX)) { >+ *hw_hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL); >+ if (!*hw_hpd) { > ASSERT_CRITICAL(false); >- return NULL; >+ return; > } > >- hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL); >- if (!hpd) { >- ASSERT_CRITICAL(false); >- return NULL; >- } >+ construct(*hw_hpd, id, en, ctx); >+} >+ >+struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio) >+{ >+ struct hw_hpd *hw_hpd = dal_gpio_get_hpd(gpio); > >- construct(hpd, id, en, ctx); >- return &hpd->base.base; >+ return &hw_hpd->base.base; > } >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h 2019-08-31 15:01:11.870736169 -0500 >@@ -38,9 +38,12 @@ > #define HW_HPD_FROM_BASE(hw_gpio) \ > container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_hpd, base) > >-struct hw_gpio_pin *dal_hw_hpd_create( >+void dal_hw_hpd_init( >+ struct hw_hpd **hw_hpd, > struct dc_context *ctx, > enum gpio_id id, > uint32_t en); > >+struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio); >+ > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c 2019-08-31 15:01:11.870736169 -0500 >@@ -49,6 +49,9 @@ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #include "dcn20/hw_translate_dcn20.h" > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#include "dcn21/hw_translate_dcn21.h" >+#endif > > #include "diagnostics/hw_translate_diag.h" > >@@ -94,6 +97,11 @@ > dal_hw_translate_dcn20_init(translate); > return true; > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ case DCN_VERSION_2_1: >+ dal_hw_translate_dcn21_init(translate); >+ return true; >+#endif > > default: > BREAK_TO_DEBUGGER(); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/Makefile 2019-08-31 15:01:11.869736169 -0500 >@@ -24,7 +24,7 @@ > # It provides the control and status of HW GPIO pins. > > GPIO = gpio_base.o gpio_service.o hw_factory.o \ >- hw_gpio.o hw_hpd.o hw_ddc.o hw_translate.o >+ hw_gpio.o hw_hpd.o hw_ddc.o hw_generic.o hw_translate.o > > AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO)) > >@@ -80,6 +80,13 @@ > AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN20) > endif > >+ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+GPIO_DCN21 = hw_translate_dcn21.o hw_factory_dcn21.o >+ >+AMD_DAL_GPIO_DCN21 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn21/,$(GPIO_DCN21)) >+ >+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN21) >+endif > ############################################################################### > # Diagnostics on FPGA > ############################################################################### >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/core_status.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/core_status.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/core_status.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/core_status.h 2019-08-31 15:01:11.870736169 -0500 >@@ -48,6 +48,9 @@ > DC_NO_DSC_RESOURCE = 17, > #endif > DC_FAIL_UNSUPPORTED_1 = 18, >+ DC_FAIL_CLK_EXCEED_MAX = 21, >+ DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/ >+ DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/ > > DC_ERROR_UNEXPECTED = -1 > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/core_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/core_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/core_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/core_types.h 2019-08-31 15:01:11.870736169 -0500 >@@ -63,11 +63,6 @@ > TODO: remove it when DC is complete. */ > }; > >-enum { >- FREE_ACQUIRED_RESOURCE = 0, >- KEEP_ACQUIRED_RESOURCE = 1, >-}; >- > struct dc_link *link_create(const struct link_init_data *init_params); > void link_destroy(struct dc_link **link); > >@@ -82,7 +77,7 @@ > struct dc_state *state, > struct pipe_ctx *pipe_ctx); > >-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option); >+void core_link_disable_stream(struct pipe_ctx *pipe_ctx); > > void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); > /********** DAL Core*********************/ >@@ -92,6 +87,9 @@ > struct resource_pool; > struct dc_state; > struct resource_context; >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+struct clk_bw_params; >+#endif > > struct resource_funcs { > void (*destroy)(struct resource_pool **pool); >@@ -147,6 +145,11 @@ > display_e2e_pipe_params_st *pipes, > int pipe_cnt); > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ void (*update_bw_bounding_box)( >+ struct dc *dc, >+ struct clk_bw_params *bw_params); >+#endif > > }; > >@@ -228,14 +231,12 @@ > > struct dcn_fe_bandwidth { > int dppclk_khz; >- > }; > > struct stream_resource { > struct output_pixel_processor *opp; > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > struct display_stream_compressor *dsc; >- int dscclk_khz; > #endif > struct timing_generator *tg; > struct stream_encoder *stream_enc; >@@ -299,6 +300,8 @@ > > struct pipe_ctx *top_pipe; > struct pipe_ctx *bottom_pipe; >+ struct pipe_ctx *next_odm_pipe; >+ struct pipe_ctx *prev_odm_pipe; > > #ifdef CONFIG_DRM_AMD_DC_DCN1_0 > struct _vcs_dpi_display_dlg_regs_st dlg_regs; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h 2019-08-31 15:01:11.870736169 -0500 >@@ -38,6 +38,11 @@ > struct dc_link_settings *known_limit_link_setting, > int *fail_count); > >+bool dp_verify_link_cap_with_retries( >+ struct dc_link *link, >+ struct dc_link_settings *known_limit_link_setting, >+ int attempts); >+ > bool dp_validate_mode_timing( > struct dc_link *link, > const struct dc_crtc_timing *timing); >@@ -62,10 +67,15 @@ > > void dp_enable_mst_on_sink(struct dc_link *link, bool enable); > >+enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); >+void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode); >+ > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > void dp_set_fec_ready(struct dc_link *link, bool ready); > void dp_set_fec_enable(struct dc_link *link, bool enable); > bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable); >+bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable); >+void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable); > bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx); > #endif > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 2019-08-31 15:01:11.870736169 -0500 >@@ -28,6 +28,131 @@ > > #include "dc.h" > >+#define DCN_MINIMUM_DISPCLK_Khz 100000 >+#define DCN_MINIMUM_DPPCLK_Khz 100000 >+ >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+/* Constants */ >+#define DDR4_DRAM_WIDTH 64 >+#define WM_A 0 >+#define WM_B 1 >+#define WM_C 2 >+#define WM_D 3 >+#define WM_SET_COUNT 4 >+#endif >+ >+#define DCN_MINIMUM_DISPCLK_Khz 100000 >+#define DCN_MINIMUM_DPPCLK_Khz 100000 >+ >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+/* Will these bw structures be ASIC specific? */ >+ >+#define MAX_NUM_DPM_LVL 4 >+#define WM_SET_COUNT 4 >+ >+ >+struct clk_limit_table_entry { >+ unsigned int voltage; /* milivolts withh 2 fractional bits */ >+ unsigned int dcfclk_mhz; >+ unsigned int fclk_mhz; >+ unsigned int memclk_mhz; >+ unsigned int socclk_mhz; >+}; >+ >+/* This table is contiguous */ >+struct clk_limit_table { >+ struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; >+ unsigned int num_entries; >+}; >+ >+struct wm_range_table_entry { >+ unsigned int wm_inst; >+ unsigned int wm_type; >+ double pstate_latency_us; >+ bool valid; >+}; >+ >+ >+struct clk_log_info { >+ bool enabled; >+ char *pBuf; >+ unsigned int bufSize; >+ unsigned int *sum_chars_printed; >+}; >+ >+struct clk_state_registers_and_bypass { >+ uint32_t dcfclk; >+ uint32_t dcf_deep_sleep_divider; >+ uint32_t dcf_deep_sleep_allow; >+ uint32_t dprefclk; >+ uint32_t dispclk; >+ uint32_t dppclk; >+ >+ uint32_t dppclk_bypass; >+ uint32_t dcfclk_bypass; >+ uint32_t dprefclk_bypass; >+ uint32_t dispclk_bypass; >+}; >+ >+struct rv1_clk_internal { >+ uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk >+ uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider >+ uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow >+ uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk >+ uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk >+ >+ uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass >+ uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass >+ uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass >+}; >+ >+struct rn_clk_internal { >+ uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk >+ uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk >+ uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk >+ uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk >+ uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider >+ uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow >+ >+ uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass >+ uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass >+ uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass >+ uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass >+ >+}; >+ >+/* For dtn logging and debugging */ >+struct clk_state_registers { >+ uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk >+ uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider >+ uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow >+ uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk >+ uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk >+}; >+ >+/* TODO: combine this with the above */ >+struct clk_bypass { >+ uint32_t dcfclk_bypass; >+ uint32_t dispclk_pypass; >+ uint32_t dprefclk_bypass; >+}; >+/* >+ * This table is not contiguous, can have holes, each >+ * entry correspond to one set of WM. For example if >+ * we have 2 DPM and LPDDR, we will WM set A, B and >+ * D occupied, C will be emptry. >+ */ >+struct wm_table { >+ struct wm_range_table_entry entries[WM_SET_COUNT]; >+}; >+ >+struct clk_bw_params { >+ unsigned int vram_type; >+ unsigned int num_channels; >+ struct clk_limit_table clk_table; >+ struct wm_table wm_table; >+}; >+#endif > /* Public interfaces */ > > struct clk_states { >@@ -51,6 +176,10 @@ > void (*init_clocks)(struct clk_mgr *clk_mgr); > > void (*enable_pme_wa) (struct clk_mgr *clk_mgr); >+ void (*get_clock)(struct clk_mgr *clk_mgr, >+ struct dc_state *context, >+ enum dc_clock_type clock_type, >+ struct dc_clock_config *clock_cfg); > }; > > struct clk_mgr { >@@ -58,6 +187,9 @@ > struct clk_mgr_funcs *funcs; > struct dc_clocks clks; > int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes >+#ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+ struct clk_bw_params *bw_params; >+#endif > }; > > /* forward declarations */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h 2019-08-31 15:01:11.870736169 -0500 >@@ -64,6 +64,8 @@ > *************************************************************************************** > */ > >+/* Macros */ >+ > #define TO_CLK_MGR_INTERNAL(clk_mgr)\ > container_of(clk_mgr, struct clk_mgr_internal, base) > >@@ -189,6 +191,7 @@ > > struct clk_mgr_internal { > struct clk_mgr base; >+ int smu_ver; > struct pp_smu_funcs *pp_smu; > struct clk_mgr_internal_funcs *funcs; > >@@ -213,6 +216,8 @@ > bool dfs_bypass_enabled; > /* True if the DFS-bypass feature is enabled and active. */ > bool dfs_bypass_active; >+ >+ uint32_t dfs_ref_freq_khz; > /* > * Cache the display clock returned by VBIOS if DFS-bypass is enabled. > * This is basically "Crystal Frequency In KHz" (XTALIN) frequency >@@ -276,8 +281,14 @@ > > static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support) > { >- // Whenever we are transitioning pstate support, we always want to notify prior to committing state >- return (calc_support != cur_support) ? !safe_to_lower : false; >+ if (cur_support != calc_support) { >+ if (calc_support == true && safe_to_lower) >+ return true; >+ else if (calc_support == false && !safe_to_lower) >+ return true; >+ } >+ >+ return false; > } > > int clk_mgr_helper_get_active_display_cnt( >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h 2019-08-31 15:01:11.870736169 -0500 >@@ -38,7 +38,8 @@ > struct dccg_funcs { > void (*update_dpp_dto)(struct dccg *dccg, > int dpp_inst, >- int req_dppclk); >+ int req_dppclk, >+ bool reduce_divider_only); > void (*get_dccg_ref_freq)(struct dccg *dccg, > unsigned int xtalin_freq_inKhz, > unsigned int *dccg_ref_freq_inKhz); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 2019-08-31 15:01:11.870736169 -0500 >@@ -80,6 +80,8 @@ > uint64_t page_table_end_addr; > uint64_t page_table_base_addr; > } gart_config; >+ >+ uint64_t page_table_default_page_addr; > }; > > struct dcn_hubbub_virt_addr_config { >@@ -141,6 +143,10 @@ > struct dcn_watermark_set *watermarks, > unsigned int refclk_mhz, > bool safe_to_lower); >+ >+ bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub); >+ void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow); >+ > }; > > struct hubbub { >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h 2019-08-31 15:01:11.870736169 -0500 >@@ -42,6 +42,7 @@ > > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > struct pwl_params shaper_params; >+ bool cm_bypass_mode; > #endif > }; > >@@ -200,7 +201,7 @@ > > void (*set_cursor_attributes)( > struct dpp *dpp_base, >- enum dc_cursor_color_format color_format); >+ struct dc_cursor_attributes *cursor_attributes); > > void (*set_cursor_position)( > struct dpp *dpp_base, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h 2019-08-31 15:01:11.870736169 -0500 >@@ -92,7 +92,9 @@ > void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); > bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); > void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, >- struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps); >+ struct dsc_optc_config *dsc_optc_cfg); >+ bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, >+ uint8_t *dsc_packed_pps); > void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe); > void (*dsc_disable)(struct display_stream_compressor *dsc); > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 2019-08-31 15:01:11.870736169 -0500 >@@ -45,22 +45,10 @@ > dwb_src_scl = 0, /* for DCE7x/9x, DCN won't support. */ > dwb_src_blnd, /* for DCE7x/9x */ > dwb_src_fmt, /* for DCE7x/9x */ >-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) > dwb_src_otg0 = 0x100, /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */ > dwb_src_otg1, /* for DCN1.x/DCN2.x */ > dwb_src_otg2, /* for DCN1.x/DCN2.x */ > dwb_src_otg3, /* for DCN1.x/DCN2.x */ >-#else >- dwb_src_otg0 = 0x100, /* for DCN1.x, register: mmDWB_SOURCE_SELECT */ >- dwb_src_otg1, /* for DCN1.x */ >- dwb_src_otg2, /* for DCN1.x */ >- dwb_src_otg3, /* for DCN1.x */ >-#endif >- dwb_src_mpc0 = 0x200, /* for DCN2, register: mmMPC_DWB0_MUX, mmMPC_DWB1_MUX, mmMPC_DWB2_MUX */ >- dwb_src_mpc1, /* for DCN2 */ >- dwb_src_mpc2, /* for DCN2 */ >- dwb_src_mpc3, /* for DCN2 */ >- dwb_src_mpc4, /* for DCN2 */ > }; > > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h 2019-08-31 15:01:11.870736169 -0500 >@@ -28,12 +28,22 @@ > > #include "gpio_types.h" > >+ >+union gpio_hw_container { >+ struct hw_ddc *ddc; >+ struct hw_generic *generic; >+ struct hw_hpd *hpd; >+}; >+ > struct gpio { > struct gpio_service *service; > struct hw_gpio_pin *pin; > enum gpio_id id; > uint32_t en; >+ >+ union gpio_hw_container hw_container; > enum gpio_mode mode; >+ > /* when GPIO comes from VBIOS, it has defined output state */ > enum gpio_pin_output_state output_state; > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h 2019-08-31 15:01:11.871736169 -0500 >@@ -47,6 +47,11 @@ > CURSOR_LINE_PER_CHUNK_16 > }; > >+enum hubp_ind_block_size { >+ hubp_ind_block_unconstrained = 0, >+ hubp_ind_block_64b, >+}; >+ > struct hubp { > const struct hubp_funcs *funcs; > struct dc_context *ctx; >@@ -74,7 +79,8 @@ > struct _vcs_dpi_display_ttu_regs_st *ttu_regs); > > void (*dcc_control)(struct hubp *hubp, bool enable, >- bool independent_64b_blks); >+ enum hubp_ind_block_size blk_size); >+ > void (*mem_program_viewport)( > struct hubp *hubp, > const struct rect *viewport, >@@ -103,7 +109,7 @@ > struct hubp *hubp, > enum surface_pixel_format format, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > enum dc_rotation_angle rotation, > struct dc_plane_dcc_param *dcc, > bool horizontal_mirror, >@@ -111,9 +117,6 @@ > > bool (*hubp_is_flip_pending)(struct hubp *hubp); > >- void (*hubp_update_dchub)(struct hubp *hubp, >- struct dchub_init_data *dh_data); >- > void (*set_blank)(struct hubp *hubp, bool blank); > void (*set_hubp_blank_en)(struct hubp *hubp, bool blank); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h 2019-08-31 15:01:11.871736169 -0500 >@@ -183,6 +183,9 @@ > > bool (*fec_is_active)(struct link_encoder *enc); > #endif >+ bool (*is_in_alt_mode) (struct link_encoder *enc); >+ enum signal_type (*get_dig_mode)( >+ struct link_encoder *enc); > }; > > #endif /* LINK_ENCODER_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h 2019-08-31 15:01:11.871736169 -0500 >@@ -40,6 +40,10 @@ > struct dcn_watermarks { > uint32_t pte_meta_urgent_ns; > uint32_t urgent_ns; >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ uint32_t frac_urg_bw_nom; >+ uint32_t frac_urg_bw_flip; >+#endif > struct cstate_pstate_watermarks_st cstate_pstate; > }; > >@@ -149,7 +153,7 @@ > struct mem_input *mem_input, > enum surface_pixel_format format, > union dc_tiling_info *tiling_info, >- union plane_size *plane_size, >+ struct plane_size *plane_size, > enum dc_rotation_angle rotation, > struct dc_plane_dcc_param *dcc, > bool horizontal_mirror); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h 2019-08-31 15:01:11.871736169 -0500 >@@ -128,6 +128,7 @@ > struct mpcc mpcc_array[MAX_MPCC]; > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > struct pwl_params blender_params; >+ bool cm_bypass_mode; > #endif > }; > >@@ -198,6 +199,9 @@ > * Return: void > */ > void (*mpc_init)(struct mpc *mpc); >+ void (*mpc_init_single_inst)( >+ struct mpc *mpc, >+ unsigned int mpcc_id); > > /* > * Update the blending configuration for a specified MPCC. >@@ -250,6 +254,10 @@ > struct mpc *mpc, > int mpcc_id, > const struct pwl_params *params); >+ void (*power_on_mpc_mem_pwr)( >+ struct mpc *mpc, >+ int mpcc_id, >+ bool power_on); > #endif > > }; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 2019-08-31 15:01:11.871736169 -0500 >@@ -316,11 +316,6 @@ > bool (*dpg_is_blanked)( > struct output_pixel_processor *opp); > >- void (*opp_convert_pti)( >- struct output_pixel_processor *opp, >- bool enable, >- bool polarity); >- > void (*opp_dpg_set_blank_color)( > struct output_pixel_processor *opp, > const struct tg_color *color); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h 2019-08-31 15:01:11.871736169 -0500 >@@ -91,7 +91,7 @@ > struct dc_link_settings link_settings; > struct dc_crtc_timing timing; > #ifdef CONFIG_DRM_AMD_DC_DCN2_0 >- bool odm; >+ int opp_cnt; > #endif > }; > >@@ -122,9 +122,6 @@ > #endif > > struct stream_encoder_funcs { >- #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >- void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s); >- #endif > void (*dp_set_stream_attribute)( > struct stream_encoder *enc, > struct dc_crtc_timing *crtc_timing, >@@ -211,14 +208,25 @@ > struct stream_encoder *enc, > int tg_inst); > >+ void (*hdmi_reset_stream_attribute)( >+ struct stream_encoder *enc); >+ >+ unsigned int (*dig_source_otg)( >+ struct stream_encoder *enc); >+ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT >+ void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s); >+ > void (*dp_set_dsc_config)( > struct stream_encoder *enc, > enum optc_dsc_mode dsc_mode, > uint32_t dsc_bytes_per_pixel, >- uint32_t dsc_slice_width, >- uint8_t *dsc_packed_pps); >+ uint32_t dsc_slice_width); >+ >+ void (*dp_set_dsc_pps_info_packet)(struct stream_encoder *enc, >+ bool enable, >+ uint8_t *dsc_packed_pps); > #endif > > void (*set_dynamic_metadata)(struct stream_encoder *enc, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 2019-08-31 15:01:11.871736169 -0500 >@@ -59,6 +59,8 @@ > struct drr_params { > uint32_t vertical_total_min; > uint32_t vertical_total_max; >+ uint32_t vertical_total_mid; >+ uint32_t vertical_total_mid_frame_num; > bool immediate_flip; > }; > >@@ -96,6 +98,11 @@ > INTERSECT_WINDOW_NOT_A_NOT_B, > }; > >+enum h_timing_div_mode { >+ H_TIMING_NO_DIV, >+ H_TIMING_DIV_BY2, >+}; >+ > struct crc_params { > /* Regions used to calculate CRC*/ > uint16_t windowa_x_start; >@@ -184,10 +191,8 @@ > bool (*did_triggered_reset_occur)(struct timing_generator *tg); > void (*setup_global_swap_lock)(struct timing_generator *tg, > const struct dcp_gsl_params *gsl_params); >- void (*setup_global_lock)(struct timing_generator *tg); > void (*unlock)(struct timing_generator *tg); > void (*lock)(struct timing_generator *tg); >- void (*lock_global)(struct timing_generator *tg); > void (*lock_doublebuffer_disable)(struct timing_generator *tg); > void (*lock_doublebuffer_enable)(struct timing_generator *tg); > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) >@@ -267,9 +272,9 @@ > uint32_t dsc_bytes_per_pixel, > uint32_t dsc_slice_width); > #endif >- void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing); >- void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id, >- int mpcc_hactive, enum dc_pixel_encoding pixel_encoding); >+ void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); >+ void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, >+ struct dc_crtc_timing *timing); > void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); > void (*set_gsl_source_select)(struct timing_generator *optc, > int group_idx, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 2019-08-31 15:01:11.871736169 -0500 >@@ -48,6 +48,7 @@ > bool DEGVIDCN10_253; > bool false_optc_underflow; > bool DEGVIDCN10_254; >+ bool DEGVIDCN21; > }; > > struct hwseq_wa_state { >@@ -78,6 +79,8 @@ > struct dc_phy_addr_space_config; > struct dc_virtual_addr_space_config; > #endif >+struct hubp; >+struct dpp; > > struct hw_sequencer_funcs { > >@@ -194,8 +197,7 @@ > > void (*enable_stream)(struct pipe_ctx *pipe_ctx); > >- void (*disable_stream)(struct pipe_ctx *pipe_ctx, >- int option); >+ void (*disable_stream)(struct pipe_ctx *pipe_ctx); > > void (*unblank_stream)(struct pipe_ctx *pipe_ctx, > struct dc_link_settings *link_settings); >@@ -204,7 +206,7 @@ > > void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); > >- void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx, int option); >+ void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); > > void (*pipe_control_lock)( > struct dc *dc, >@@ -231,11 +233,13 @@ > bool (*update_bandwidth)( > struct dc *dc, > struct dc_state *context); >+ void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); > bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); > #endif > > void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, >- int vmin, int vmax); >+ unsigned int vmin, unsigned int vmax, >+ unsigned int vmid, unsigned int vmid_frame_number); > > void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, > struct crtc_position *position); >@@ -279,6 +283,36 @@ > void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx); > bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); > >+ void (*init_blank)(struct dc *dc, struct timing_generator *tg); >+ void (*disable_vga)(struct dce_hwseq *hws); >+ void (*bios_golden_init)(struct dc *dc); >+ void (*plane_atomic_power_down)(struct dc *dc, >+ struct dpp *dpp, >+ struct hubp *hubp); >+ >+ void (*plane_atomic_disable)( >+ struct dc *dc, struct pipe_ctx *pipe_ctx); >+ >+ void (*enable_power_gating_plane)( >+ struct dce_hwseq *hws, >+ bool enable); >+ >+ void (*dpp_pg_control)( >+ struct dce_hwseq *hws, >+ unsigned int dpp_inst, >+ bool power_on); >+ >+ void (*hubp_pg_control)( >+ struct dce_hwseq *hws, >+ unsigned int hubp_inst, >+ bool power_on); >+ >+ void (*dsc_pg_control)( >+ struct dce_hwseq *hws, >+ unsigned int dsc_inst, >+ bool power_on); >+ >+ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); > void (*program_all_writeback_pipes_in_tree)( >@@ -294,6 +328,15 @@ > void (*disable_writeback)(struct dc *dc, > unsigned int dwb_pipe_inst); > #endif >+ enum dc_status (*set_clock)(struct dc *dc, >+ enum dc_clock_type clock_type, >+ uint32_t clk_khz, >+ uint32_t stepping); >+ >+ void (*get_clock)(struct dc *dc, >+ enum dc_clock_type clock_type, >+ struct dc_clock_config *clock_cfg); >+ > }; > > void color_space_to_black_color( >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h 2019-08-31 15:01:11.871736169 -0500 >@@ -60,7 +60,7 @@ > > bool dp_set_hw_training_pattern( > struct dc_link *link, >- enum hw_dp_training_pattern pattern); >+ enum dc_dp_training_pattern pattern); > > void dp_set_hw_lane_settings( > struct dc_link *link, >@@ -72,8 +72,6 @@ > uint8_t *custom_pattern, > uint32_t custom_pattern_size); > >-enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); >- > void dp_retrain_link_dp_test(struct dc_link *link, > struct dc_link_settings *link_setting, > bool skip_video_pattern); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/resource.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/resource.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/resource.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/resource.h 2019-08-31 15:01:11.871736169 -0500 >@@ -179,7 +179,4 @@ > > unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format); > >-struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx); >-bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx); >- > #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 2019-08-31 15:01:11.871736169 -0500 >@@ -167,6 +167,11 @@ > .ack = NULL > }; > >+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { >+ .set = NULL, >+ .ack = NULL >+}; >+ > #undef BASE_INNER > #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg > >@@ -221,12 +226,15 @@ > .funcs = &pflip_irq_info_funcs\ > } > >-#define vupdate_int_entry(reg_num)\ >+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic >+ * of DCE's DC_IRQ_SOURCE_VUPDATEx. >+ */ >+#define vupdate_no_lock_int_entry(reg_num)\ > [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ > IRQ_REG_ENTRY(OTG, reg_num,\ >- OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\ >- OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\ >- .funcs = &vblank_irq_info_funcs\ >+ OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ >+ OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ >+ .funcs = &vupdate_no_lock_irq_info_funcs\ > } > > #define vblank_int_entry(reg_num)\ >@@ -333,12 +341,12 @@ > dc_underflow_int_entry(6), > [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), > [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), >- vupdate_int_entry(0), >- vupdate_int_entry(1), >- vupdate_int_entry(2), >- vupdate_int_entry(3), >- vupdate_int_entry(4), >- vupdate_int_entry(5), >+ vupdate_no_lock_int_entry(0), >+ vupdate_no_lock_int_entry(1), >+ vupdate_no_lock_int_entry(2), >+ vupdate_no_lock_int_entry(3), >+ vupdate_no_lock_int_entry(4), >+ vupdate_no_lock_int_entry(5), > vblank_int_entry(0), > vblank_int_entry(1), > vblank_int_entry(2), >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c 2019-08-31 15:01:11.871736169 -0500 >@@ -0,0 +1,374 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#include <linux/slab.h> >+ >+#include "dm_services.h" >+ >+#include "include/logger_interface.h" >+ >+#include "../dce110/irq_service_dce110.h" >+ >+#include "dcn/dcn_2_1_0_offset.h" >+#include "dcn/dcn_2_1_0_sh_mask.h" >+#include "renoir_ip_offset.h" >+ >+ >+#include "irq_service_dcn21.h" >+ >+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" >+ >+enum dc_irq_source to_dal_irq_source_dcn21( >+ struct irq_service *irq_service, >+ uint32_t src_id, >+ uint32_t ext_id) >+{ >+ switch (src_id) { >+ case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: >+ return DC_IRQ_SOURCE_VBLANK1; >+ case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: >+ return DC_IRQ_SOURCE_VBLANK2; >+ case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: >+ return DC_IRQ_SOURCE_VBLANK3; >+ case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: >+ return DC_IRQ_SOURCE_VBLANK4; >+ case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: >+ return DC_IRQ_SOURCE_VBLANK5; >+ case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: >+ return DC_IRQ_SOURCE_VBLANK6; >+ case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: >+ return DC_IRQ_SOURCE_PFLIP1; >+ case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: >+ return DC_IRQ_SOURCE_PFLIP2; >+ case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: >+ return DC_IRQ_SOURCE_PFLIP3; >+ case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: >+ return DC_IRQ_SOURCE_PFLIP4; >+ case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: >+ return DC_IRQ_SOURCE_PFLIP5; >+ case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: >+ return DC_IRQ_SOURCE_PFLIP6; >+ case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: >+ return DC_IRQ_SOURCE_VUPDATE1; >+ case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: >+ return DC_IRQ_SOURCE_VUPDATE2; >+ case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: >+ return DC_IRQ_SOURCE_VUPDATE3; >+ case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: >+ return DC_IRQ_SOURCE_VUPDATE4; >+ case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: >+ return DC_IRQ_SOURCE_VUPDATE5; >+ case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: >+ return DC_IRQ_SOURCE_VUPDATE6; >+ >+ case DCN_1_0__SRCID__DC_HPD1_INT: >+ /* generic src_id for all HPD and HPDRX interrupts */ >+ switch (ext_id) { >+ case DCN_1_0__CTXID__DC_HPD1_INT: >+ return DC_IRQ_SOURCE_HPD1; >+ case DCN_1_0__CTXID__DC_HPD2_INT: >+ return DC_IRQ_SOURCE_HPD2; >+ case DCN_1_0__CTXID__DC_HPD3_INT: >+ return DC_IRQ_SOURCE_HPD3; >+ case DCN_1_0__CTXID__DC_HPD4_INT: >+ return DC_IRQ_SOURCE_HPD4; >+ case DCN_1_0__CTXID__DC_HPD5_INT: >+ return DC_IRQ_SOURCE_HPD5; >+ case DCN_1_0__CTXID__DC_HPD6_INT: >+ return DC_IRQ_SOURCE_HPD6; >+ case DCN_1_0__CTXID__DC_HPD1_RX_INT: >+ return DC_IRQ_SOURCE_HPD1RX; >+ case DCN_1_0__CTXID__DC_HPD2_RX_INT: >+ return DC_IRQ_SOURCE_HPD2RX; >+ case DCN_1_0__CTXID__DC_HPD3_RX_INT: >+ return DC_IRQ_SOURCE_HPD3RX; >+ case DCN_1_0__CTXID__DC_HPD4_RX_INT: >+ return DC_IRQ_SOURCE_HPD4RX; >+ case DCN_1_0__CTXID__DC_HPD5_RX_INT: >+ return DC_IRQ_SOURCE_HPD5RX; >+ case DCN_1_0__CTXID__DC_HPD6_RX_INT: >+ return DC_IRQ_SOURCE_HPD6RX; >+ default: >+ return DC_IRQ_SOURCE_INVALID; >+ } >+ break; >+ >+ default: >+ break; >+ } >+ return DC_IRQ_SOURCE_INVALID; >+} >+ >+static bool hpd_ack( >+ struct irq_service *irq_service, >+ const struct irq_source_info *info) >+{ >+ uint32_t addr = info->status_reg; >+ uint32_t value = dm_read_reg(irq_service->ctx, addr); >+ uint32_t current_status = >+ get_reg_field_value( >+ value, >+ HPD0_DC_HPD_INT_STATUS, >+ DC_HPD_SENSE_DELAYED); >+ >+ dal_irq_service_ack_generic(irq_service, info); >+ >+ value = dm_read_reg(irq_service->ctx, info->enable_reg); >+ >+ set_reg_field_value( >+ value, >+ current_status ? 0 : 1, >+ HPD0_DC_HPD_INT_CONTROL, >+ DC_HPD_INT_POLARITY); >+ >+ dm_write_reg(irq_service->ctx, info->enable_reg, value); >+ >+ return true; >+} >+ >+static const struct irq_source_info_funcs hpd_irq_info_funcs = { >+ .set = NULL, >+ .ack = hpd_ack >+}; >+ >+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { >+ .set = NULL, >+ .ack = NULL >+}; >+ >+static const struct irq_source_info_funcs pflip_irq_info_funcs = { >+ .set = NULL, >+ .ack = NULL >+}; >+ >+static const struct irq_source_info_funcs vblank_irq_info_funcs = { >+ .set = NULL, >+ .ack = NULL >+}; >+ >+#undef BASE_INNER >+#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg >+ >+/* compile time expand base address. */ >+#define BASE(seg) \ >+ BASE_INNER(seg) >+ >+ >+#define SRI(reg_name, block, id)\ >+ BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ >+ mm ## block ## id ## _ ## reg_name >+ >+ >+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ >+ .enable_reg = SRI(reg1, block, reg_num),\ >+ .enable_mask = \ >+ block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ >+ .enable_value = {\ >+ block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ >+ ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ >+ },\ >+ .ack_reg = SRI(reg2, block, reg_num),\ >+ .ack_mask = \ >+ block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ >+ .ack_value = \ >+ block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ >+ >+ >+ >+#define hpd_int_entry(reg_num)\ >+ [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ >+ IRQ_REG_ENTRY(HPD, reg_num,\ >+ DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ >+ DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ >+ .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ >+ .funcs = &hpd_irq_info_funcs\ >+ } >+ >+#define hpd_rx_int_entry(reg_num)\ >+ [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ >+ IRQ_REG_ENTRY(HPD, reg_num,\ >+ DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ >+ DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ >+ .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ >+ .funcs = &hpd_rx_irq_info_funcs\ >+ } >+#define pflip_int_entry(reg_num)\ >+ [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ >+ IRQ_REG_ENTRY(HUBPREQ, reg_num,\ >+ DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ >+ DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ >+ .funcs = &pflip_irq_info_funcs\ >+ } >+ >+#define vupdate_int_entry(reg_num)\ >+ [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ >+ IRQ_REG_ENTRY(OTG, reg_num,\ >+ OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\ >+ OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\ >+ .funcs = &vblank_irq_info_funcs\ >+ } >+ >+#define vblank_int_entry(reg_num)\ >+ [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ >+ IRQ_REG_ENTRY(OTG, reg_num,\ >+ OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ >+ OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ >+ .funcs = &vblank_irq_info_funcs\ >+ } >+ >+#define dummy_irq_entry() \ >+ {\ >+ .funcs = &dummy_irq_info_funcs\ >+ } >+ >+#define i2c_int_entry(reg_num) \ >+ [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() >+ >+#define dp_sink_int_entry(reg_num) \ >+ [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() >+ >+#define gpio_pad_int_entry(reg_num) \ >+ [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() >+ >+#define dc_underflow_int_entry(reg_num) \ >+ [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() >+ >+static const struct irq_source_info_funcs dummy_irq_info_funcs = { >+ .set = dal_irq_service_dummy_set, >+ .ack = dal_irq_service_dummy_ack >+}; >+ >+static const struct irq_source_info >+irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = { >+ [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), >+ hpd_int_entry(0), >+ hpd_int_entry(1), >+ hpd_int_entry(2), >+ hpd_int_entry(3), >+ hpd_int_entry(4), >+ hpd_rx_int_entry(0), >+ hpd_rx_int_entry(1), >+ hpd_rx_int_entry(2), >+ hpd_rx_int_entry(3), >+ hpd_rx_int_entry(4), >+ i2c_int_entry(1), >+ i2c_int_entry(2), >+ i2c_int_entry(3), >+ i2c_int_entry(4), >+ i2c_int_entry(5), >+ i2c_int_entry(6), >+ dp_sink_int_entry(1), >+ dp_sink_int_entry(2), >+ dp_sink_int_entry(3), >+ dp_sink_int_entry(4), >+ dp_sink_int_entry(5), >+ dp_sink_int_entry(6), >+ [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), >+ pflip_int_entry(0), >+ pflip_int_entry(1), >+ pflip_int_entry(2), >+ pflip_int_entry(3), >+ [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), >+ [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), >+ [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), >+ gpio_pad_int_entry(0), >+ gpio_pad_int_entry(1), >+ gpio_pad_int_entry(2), >+ gpio_pad_int_entry(3), >+ gpio_pad_int_entry(4), >+ gpio_pad_int_entry(5), >+ gpio_pad_int_entry(6), >+ gpio_pad_int_entry(7), >+ gpio_pad_int_entry(8), >+ gpio_pad_int_entry(9), >+ gpio_pad_int_entry(10), >+ gpio_pad_int_entry(11), >+ gpio_pad_int_entry(12), >+ gpio_pad_int_entry(13), >+ gpio_pad_int_entry(14), >+ gpio_pad_int_entry(15), >+ gpio_pad_int_entry(16), >+ gpio_pad_int_entry(17), >+ gpio_pad_int_entry(18), >+ gpio_pad_int_entry(19), >+ gpio_pad_int_entry(20), >+ gpio_pad_int_entry(21), >+ gpio_pad_int_entry(22), >+ gpio_pad_int_entry(23), >+ gpio_pad_int_entry(24), >+ gpio_pad_int_entry(25), >+ gpio_pad_int_entry(26), >+ gpio_pad_int_entry(27), >+ gpio_pad_int_entry(28), >+ gpio_pad_int_entry(29), >+ gpio_pad_int_entry(30), >+ dc_underflow_int_entry(1), >+ dc_underflow_int_entry(2), >+ dc_underflow_int_entry(3), >+ dc_underflow_int_entry(4), >+ dc_underflow_int_entry(5), >+ dc_underflow_int_entry(6), >+ [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), >+ [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), >+ vupdate_int_entry(0), >+ vupdate_int_entry(1), >+ vupdate_int_entry(2), >+ vupdate_int_entry(3), >+ vupdate_int_entry(4), >+ vupdate_int_entry(5), >+ vblank_int_entry(0), >+ vblank_int_entry(1), >+ vblank_int_entry(2), >+ vblank_int_entry(3), >+ vblank_int_entry(4), >+ vblank_int_entry(5), >+}; >+ >+static const struct irq_service_funcs irq_service_funcs_dcn21 = { >+ .to_dal_irq_source = to_dal_irq_source_dcn21 >+}; >+ >+static void construct( >+ struct irq_service *irq_service, >+ struct irq_service_init_data *init_data) >+{ >+ dal_irq_service_construct(irq_service, init_data); >+ >+ irq_service->info = irq_source_info_dcn21; >+ irq_service->funcs = &irq_service_funcs_dcn21; >+} >+ >+struct irq_service *dal_irq_service_dcn21_create( >+ struct irq_service_init_data *init_data) >+{ >+ struct irq_service *irq_service = kzalloc(sizeof(*irq_service), >+ GFP_KERNEL); >+ >+ if (!irq_service) >+ return NULL; >+ >+ construct(irq_service, init_data); >+ return irq_service; >+} >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h 2019-08-31 15:01:11.871736169 -0500 >@@ -0,0 +1,34 @@ >+/* >+ * Copyright 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included in >+ * all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >+ * OTHER DEALINGS IN THE SOFTWARE. >+ * >+ * Authors: AMD >+ * >+ */ >+ >+#ifndef __DAL_IRQ_SERVICE_DCN21_H__ >+#define __DAL_IRQ_SERVICE_DCN21_H__ >+ >+#include "../irq_service.h" >+ >+struct irq_service *dal_irq_service_dcn21_create( >+ struct irq_service_init_data *init_data); >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/Makefile 2019-08-31 15:01:11.871736169 -0500 >@@ -77,3 +77,13 @@ > > AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN2) > endif >+############################################################################### >+# DCN 21 >+############################################################################### >+ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+IRQ_DCN21 = irq_service_dcn21.o >+ >+AMD_DAL_IRQ_DCN21= $(addprefix $(AMDDALPATH)/dc/irq/dcn21/,$(IRQ_DCN21)) >+ >+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN21) >+endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/Makefile >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/Makefile 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/Makefile 2019-08-31 15:01:11.855736168 -0500 >@@ -37,6 +37,9 @@ > ifdef CONFIG_DRM_AMD_DC_DCN1_0 > DC_LIBS += dcn10 dml > endif >+ifdef CONFIG_DRM_AMD_DC_DCN2_1 >+DC_LIBS += dcn21 >+endif > > DC_LIBS += dce120 > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c 2019-08-31 15:01:11.871736169 -0500 >@@ -77,6 +77,10 @@ > struct stream_encoder *enc, > bool mute) {} > >+static void virtual_stream_encoder_reset_hdmi_stream_attribute( >+ struct stream_encoder *enc) >+{} >+ > #ifdef CONFIG_DRM_AMD_DC_DCN2_0 > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > static void virtual_enc_dp_set_odm_combine( >@@ -116,6 +120,7 @@ > > .audio_mute_control = virtual_audio_mute_control, > .set_avmute = virtual_stream_encoder_set_avmute, >+ .hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute, > }; > > bool virtual_stream_encoder_construct( >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/audio_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/audio_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/audio_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/audio_types.h 2019-08-31 15:01:11.871736169 -0500 >@@ -38,8 +38,8 @@ > uint32_t h_active; > uint32_t v_active; > uint32_t pixel_repetition; >- uint32_t requested_pixel_clock; /* in KHz */ >- uint32_t calculated_pixel_clock; /* in KHz */ >+ uint32_t requested_pixel_clock_100Hz; /* in 100Hz */ >+ uint32_t calculated_pixel_clock_100Hz; /* in 100Hz */ > uint32_t refresh_rate; > enum dc_color_depth color_depth; > bool interlaced; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/dal_asic_id.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/dal_asic_id.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/dal_asic_id.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/dal_asic_id.h 2019-08-31 15:01:11.871736169 -0500 >@@ -151,6 +151,21 @@ > > #define FAMILY_NV 143 /* DCN 2*/ > >+enum { >+ NV_NAVI10_P_A0 = 1, >+ NV_NAVI12_P_A0 = 10, >+ NV_NAVI14_M_A0 = 20, >+ NV_UNKNOWN = 0xFF >+}; >+ >+#define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0) >+#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0)) >+#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) >+#endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+#define RENOIR_A0 0x91 >+#define DEVICE_ID_RENOIR_1636 0x1636 // Renoir >+#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < 0xFF)) > #endif > > /* >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/dal_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/dal_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/dal_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/dal_types.h 2019-08-31 15:01:11.871736169 -0500 >@@ -49,6 +49,9 @@ > #if defined(CONFIG_DRM_AMD_DC_DCN2_0) > DCN_VERSION_2_0, > #endif >+#if defined(CONFIG_DRM_AMD_DC_DCN2_1) >+ DCN_VERSION_2_1, >+#endif > DCN_VERSION_MAX > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/ddc_service_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/ddc_service_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/ddc_service_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/ddc_service_types.h 2019-08-31 15:01:11.871736169 -0500 >@@ -25,10 +25,12 @@ > #ifndef __DAL_DDC_SERVICE_TYPES_H__ > #define __DAL_DDC_SERVICE_TYPES_H__ > >-#define DP_BRANCH_DEVICE_ID_1 0x0010FA >-#define DP_BRANCH_DEVICE_ID_2 0x0022B9 >-#define DP_BRANCH_DEVICE_ID_3 0x00001A >-#define DP_BRANCH_DEVICE_ID_4 0x0080e1 >+/* 0010FA dongles (ST Micro) external converter chip id */ >+#define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA >+/* 0022B9 external converter chip id */ >+#define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9 >+#define DP_BRANCH_DEVICE_ID_00001A 0x00001A >+#define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1 > > enum ddc_result { > DDC_RESULT_UNKNOWN = 0, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/gpio_interface.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/gpio_interface.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/gpio_interface.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/gpio_interface.h 2019-08-31 15:01:11.872736169 -0500 >@@ -93,8 +93,17 @@ > enum gpio_pin_output_state dal_gpio_get_output_state( > const struct gpio *gpio); > >+struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio); >+ >+struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio); >+ >+struct hw_generic *dal_gpio_get_generic(struct gpio *gpio); >+ > /* Close the handle */ > void dal_gpio_close( > struct gpio *gpio); > >+ >+ >+ > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/gpio_service_interface.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/gpio_service_interface.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/gpio_service_interface.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/gpio_service_interface.h 2019-08-31 15:01:11.872736169 -0500 >@@ -51,13 +51,29 @@ > uint32_t offset, > uint32_t mask); > >+struct gpio *dal_gpio_service_create_generic_mux( >+ struct gpio_service *service, >+ uint32_t offset, >+ uint32_t mask); >+ >+void dal_gpio_destroy_generic_mux( >+ struct gpio **mux); >+ >+enum gpio_result dal_mux_setup_config( >+ struct gpio *mux, >+ struct gpio_generic_mux_config *config); >+ >+struct gpio_pin_info dal_gpio_get_generic_pin_info( >+ struct gpio_service *service, >+ enum gpio_id id, >+ uint32_t en); >+ > struct ddc *dal_gpio_create_ddc( > struct gpio_service *service, > uint32_t offset, > uint32_t mask, > struct gpio_ddc_hw_info *info); > >- > void dal_gpio_destroy_ddc( > struct ddc **ddc); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/link_service_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/link_service_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/link_service_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/link_service_types.h 2019-08-31 15:01:11.872736169 -0500 >@@ -71,14 +71,17 @@ > struct link_training_settings { > struct dc_link_settings link_settings; > struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; >- bool allow_invalid_msa_timing_param; >-}; > >-enum hw_dp_training_pattern { >- HW_DP_TRAINING_PATTERN_1 = 0, >- HW_DP_TRAINING_PATTERN_2, >- HW_DP_TRAINING_PATTERN_3, >- HW_DP_TRAINING_PATTERN_4 >+ enum dc_voltage_swing *voltage_swing; >+ enum dc_pre_emphasis *pre_emphasis; >+ enum dc_post_cursor2 *post_cursor2; >+ >+ uint16_t cr_pattern_time; >+ uint16_t eq_pattern_time; >+ enum dc_dp_training_pattern pattern_for_eq; >+ >+ bool enhanced_framing; >+ bool allow_invalid_msa_timing_param; > }; > > /*TODO: Move this enum test harness*/ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/logger_interface.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/logger_interface.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/logger_interface.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/logger_interface.h 2019-08-31 15:01:11.872736169 -0500 >@@ -155,4 +155,6 @@ > > #define DISPLAY_STATS_END(entry) (void)(entry) > >+#define LOG_GAMMA_WRITE(msg, ...) >+ > #endif /* __DAL_LOGGER_INTERFACE_H__ */ >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/logger_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/logger_types.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/logger_types.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/logger_types.h 2019-08-31 15:01:11.872736169 -0500 >@@ -63,6 +63,9 @@ > #define DC_LOG_IF_TRACE(...) pr_debug("[IF_TRACE]:"__VA_ARGS__) > #define DC_LOG_PERF_TRACE(...) DRM_DEBUG_KMS(__VA_ARGS__) > #define DC_LOG_RETIMER_REDRIVER(...) DRM_DEBUG_KMS(__VA_ARGS__) >+#define DC_LOG_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__) >+#define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__) >+#define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__) > #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT > #define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__) > #endif >@@ -117,6 +120,10 @@ > LOG_DSC, > #endif > LOG_DWB, >+ LOG_GAMMA_DEBUG, >+ LOG_MAX_HW_POINTS, >+ LOG_ALL_TF_CHANNELS, >+ LOG_SAMPLE_1DLUT, > LOG_SECTION_TOTAL_COUNT > }; > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/Kconfig linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/Kconfig >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/Kconfig 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/Kconfig 2019-08-31 15:01:11.854736168 -0500 >@@ -26,6 +26,14 @@ > Choose this option if you want to have > Navi support for display engine > >+config DRM_AMD_DC_DCN2_1 >+ bool "DCN 2.1 family" >+ depends on DRM_AMD_DC && X86 >+ depends on DRM_AMD_DC_DCN2_0 >+ help >+ Choose this option if you want to have >+ Renoir support for display engine >+ > config DRM_AMD_DC_DSC_SUPPORT > bool "DSC support" > default y >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/color/color_gamma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/color/color_gamma.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 2019-08-31 15:01:11.872736169 -0500 >@@ -30,7 +30,6 @@ > #include "opp.h" > #include "color_gamma.h" > >- > #define NUM_PTS_IN_REGION 16 > #define NUM_REGIONS 32 > #define MAX_HW_POINTS (NUM_PTS_IN_REGION*NUM_REGIONS) >@@ -40,6 +39,33 @@ > static struct fixed31_32 pq_table[MAX_HW_POINTS + 2]; > static struct fixed31_32 de_pq_table[MAX_HW_POINTS + 2]; > >+// these are helpers for calculations to reduce stack usage >+// do not depend on these being preserved across calls >+static struct fixed31_32 scratch_1; >+static struct fixed31_32 scratch_2; >+static struct translate_from_linear_space_args scratch_gamma_args; >+ >+/* Helper to optimize gamma calculation, only use in translate_from_linear, in >+ * particular the dc_fixpt_pow function which is very expensive >+ * The idea is that our regions for X points are exponential and currently they all use >+ * the same number of points (NUM_PTS_IN_REGION) and in each region every point >+ * is exactly 2x the one at the same index in the previous region. In other words >+ * X[i] = 2 * X[i-NUM_PTS_IN_REGION] for i>=16 >+ * The other fact is that (2x)^gamma = 2^gamma * x^gamma >+ * So we compute and save x^gamma for the first 16 regions, and for every next region >+ * just multiply with 2^gamma which can be computed once, and save the result so we >+ * recursively compute all the values. >+ */ >+static struct fixed31_32 pow_buffer[NUM_PTS_IN_REGION]; >+static struct fixed31_32 gamma_of_2; // 2^gamma >+int pow_buffer_ptr = -1; >+ /*sRGB 709 2.2 2.4 P3*/ >+static const int32_t gamma_numerator01[] = { 31308, 180000, 0, 0, 0}; >+static const int32_t gamma_numerator02[] = { 12920, 4500, 0, 0, 0}; >+static const int32_t gamma_numerator03[] = { 55, 99, 0, 0, 0}; >+static const int32_t gamma_numerator04[] = { 55, 99, 0, 0, 0}; >+static const int32_t gamma_numerator05[] = { 2400, 2200, 2200, 2400, 2600}; >+ > static bool pq_initialized; /* = false; */ > static bool de_pq_initialized; /* = false; */ > >@@ -71,6 +97,18 @@ > } > } > >+void log_x_points_distribution(struct dal_logger *logger) >+{ >+ int i = 0; >+ >+ if (logger != NULL) { >+ LOG_GAMMA_WRITE("Log X Distribution\n"); >+ >+ for (i = 0; i < MAX_HW_POINTS; i++) >+ LOG_GAMMA_WRITE("%llu\n", coordinates_x[i].x.value); >+ } >+} >+ > static void compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y) > { > /* consts for PQ gamma formula. */ >@@ -135,59 +173,68 @@ > > } > >+ > /*de gamma, none linear to linear*/ >-static void compute_hlg_oetf(struct fixed31_32 in_x, bool is_light0_12, struct fixed31_32 *out_y) >+static void compute_hlg_eotf(struct fixed31_32 in_x, >+ struct fixed31_32 *out_y, >+ uint32_t sdr_white_level, uint32_t max_luminance_nits) > { > struct fixed31_32 a; > struct fixed31_32 b; > struct fixed31_32 c; > struct fixed31_32 threshold; >- struct fixed31_32 reference_white_level; >+ struct fixed31_32 x; > >+ struct fixed31_32 scaling_factor = >+ dc_fixpt_from_fraction(max_luminance_nits, sdr_white_level); > a = dc_fixpt_from_fraction(17883277, 100000000); >- if (is_light0_12) { >- /*light 0-12*/ >- b = dc_fixpt_from_fraction(28466892, 100000000); >- c = dc_fixpt_from_fraction(55991073, 100000000); >- threshold = dc_fixpt_one; >- reference_white_level = dc_fixpt_half; >+ b = dc_fixpt_from_fraction(28466892, 100000000); >+ c = dc_fixpt_from_fraction(55991073, 100000000); >+ threshold = dc_fixpt_from_fraction(1, 2); >+ >+ if (dc_fixpt_lt(in_x, threshold)) { >+ x = dc_fixpt_mul(in_x, in_x); >+ x = dc_fixpt_div_int(x, 3); > } else { >- /*light 0-1*/ >- b = dc_fixpt_from_fraction(2372241, 100000000); >- c = dc_fixpt_add(dc_fixpt_one, dc_fixpt_from_fraction(429347, 100000000)); >- threshold = dc_fixpt_from_fraction(1, 12); >- reference_white_level = dc_fixpt_pow(dc_fixpt_from_fraction(3, 1), dc_fixpt_half); >+ x = dc_fixpt_sub(in_x, c); >+ x = dc_fixpt_div(x, a); >+ x = dc_fixpt_exp(x); >+ x = dc_fixpt_add(x, b); >+ x = dc_fixpt_div_int(x, 12); > } >- if (dc_fixpt_lt(threshold, in_x)) >- *out_y = dc_fixpt_add(c, dc_fixpt_mul(a, dc_fixpt_log(dc_fixpt_sub(in_x, b)))); >- else >- *out_y = dc_fixpt_mul(dc_fixpt_pow(in_x, dc_fixpt_half), reference_white_level); >+ *out_y = dc_fixpt_mul(x, scaling_factor); >+ > } > > /*re gamma, linear to none linear*/ >-static void compute_hlg_eotf(struct fixed31_32 in_x, bool is_light0_12, struct fixed31_32 *out_y) >+static void compute_hlg_oetf(struct fixed31_32 in_x, struct fixed31_32 *out_y, >+ uint32_t sdr_white_level, uint32_t max_luminance_nits) > { > struct fixed31_32 a; > struct fixed31_32 b; > struct fixed31_32 c; >- struct fixed31_32 reference_white_level; >+ struct fixed31_32 threshold; >+ struct fixed31_32 x; > >+ struct fixed31_32 scaling_factor = >+ dc_fixpt_from_fraction(sdr_white_level, max_luminance_nits); > a = dc_fixpt_from_fraction(17883277, 100000000); >- if (is_light0_12) { >- /*light 0-12*/ >- b = dc_fixpt_from_fraction(28466892, 100000000); >- c = dc_fixpt_from_fraction(55991073, 100000000); >- reference_white_level = dc_fixpt_from_fraction(4, 1); >+ b = dc_fixpt_from_fraction(28466892, 100000000); >+ c = dc_fixpt_from_fraction(55991073, 100000000); >+ threshold = dc_fixpt_from_fraction(1, 12); >+ x = dc_fixpt_mul(in_x, scaling_factor); >+ >+ >+ if (dc_fixpt_lt(x, threshold)) { >+ x = dc_fixpt_mul(x, dc_fixpt_from_fraction(3, 1)); >+ *out_y = dc_fixpt_pow(x, dc_fixpt_half); > } else { >- /*light 0-1*/ >- b = dc_fixpt_from_fraction(2372241, 100000000); >- c = dc_fixpt_add(dc_fixpt_one, dc_fixpt_from_fraction(429347, 100000000)); >- reference_white_level = dc_fixpt_from_fraction(1, 3); >+ x = dc_fixpt_mul(x, dc_fixpt_from_fraction(12, 1)); >+ x = dc_fixpt_sub(x, b); >+ x = dc_fixpt_log(x); >+ x = dc_fixpt_mul(a, x); >+ *out_y = dc_fixpt_add(x, c); > } >- if (dc_fixpt_lt(dc_fixpt_half, in_x)) >- *out_y = dc_fixpt_add(dc_fixpt_exp(dc_fixpt_div(dc_fixpt_sub(in_x, c), a)), b); >- else >- *out_y = dc_fixpt_mul(dc_fixpt_pow(in_x, dc_fixpt_from_fraction(2, 1)), reference_white_level); > } > > >@@ -243,93 +290,101 @@ > struct fixed31_32 divider3; > }; > >-enum gamma_type_index { >- gamma_type_index_2_4, >- gamma_type_index_2_2, >- gamma_type_index_2_2_flat >-}; > >-static void build_coefficients(struct gamma_coefficients *coefficients, enum gamma_type_index type) >+static bool build_coefficients(struct gamma_coefficients *coefficients, enum dc_transfer_func_predefined type) > { >- static const int32_t numerator01[] = { 31308, 180000, 0}; >- static const int32_t numerator02[] = { 12920, 4500, 0}; >- static const int32_t numerator03[] = { 55, 99, 0}; >- static const int32_t numerator04[] = { 55, 99, 0}; >- static const int32_t numerator05[] = { 2400, 2200, 2200}; > > uint32_t i = 0; > uint32_t index = 0; >+ bool ret = true; > >- if (type == gamma_type_index_2_2) >+ if (type == TRANSFER_FUNCTION_SRGB) >+ index = 0; >+ else if (type == TRANSFER_FUNCTION_BT709) > index = 1; >- else if (type == gamma_type_index_2_2_flat) >+ else if (type == TRANSFER_FUNCTION_GAMMA22) > index = 2; >+ else if (type == TRANSFER_FUNCTION_GAMMA24) >+ index = 3; >+ else if (type == TRANSFER_FUNCTION_GAMMA26) >+ index = 4; >+ else { >+ ret = false; >+ goto release; >+ } > > do { > coefficients->a0[i] = dc_fixpt_from_fraction( >- numerator01[index], 10000000); >+ gamma_numerator01[index], 10000000); > coefficients->a1[i] = dc_fixpt_from_fraction( >- numerator02[index], 1000); >+ gamma_numerator02[index], 1000); > coefficients->a2[i] = dc_fixpt_from_fraction( >- numerator03[index], 1000); >+ gamma_numerator03[index], 1000); > coefficients->a3[i] = dc_fixpt_from_fraction( >- numerator04[index], 1000); >+ gamma_numerator04[index], 1000); > coefficients->user_gamma[i] = dc_fixpt_from_fraction( >- numerator05[index], 1000); >+ gamma_numerator05[index], 1000); > > ++i; > } while (i != ARRAY_SIZE(coefficients->a0)); >+release: >+ return ret; > } > > static struct fixed31_32 translate_from_linear_space( >- struct fixed31_32 arg, >- struct fixed31_32 a0, >- struct fixed31_32 a1, >- struct fixed31_32 a2, >- struct fixed31_32 a3, >- struct fixed31_32 gamma) >+ struct translate_from_linear_space_args *args) > { > const struct fixed31_32 one = dc_fixpt_from_int(1); > >- if (dc_fixpt_lt(one, arg)) >+ if (dc_fixpt_le(one, args->arg)) > return one; > >- if (dc_fixpt_le(arg, dc_fixpt_neg(a0))) >- return dc_fixpt_sub( >- a2, >- dc_fixpt_mul( >- dc_fixpt_add( >- one, >- a3), >- dc_fixpt_pow( >- dc_fixpt_neg(arg), >- dc_fixpt_recip(gamma)))); >- else if (dc_fixpt_le(a0, arg)) >- return dc_fixpt_sub( >- dc_fixpt_mul( >- dc_fixpt_add( >- one, >- a3), >- dc_fixpt_pow( >- arg, >- dc_fixpt_recip(gamma))), >- a2); >+ if (dc_fixpt_le(args->arg, dc_fixpt_neg(args->a0))) { >+ scratch_1 = dc_fixpt_add(one, args->a3); >+ scratch_2 = dc_fixpt_pow( >+ dc_fixpt_neg(args->arg), >+ dc_fixpt_recip(args->gamma)); >+ scratch_1 = dc_fixpt_mul(scratch_1, scratch_2); >+ scratch_1 = dc_fixpt_sub(args->a2, scratch_1); >+ >+ return scratch_1; >+ } else if (dc_fixpt_le(args->a0, args->arg)) { >+ if (pow_buffer_ptr == 0) { >+ gamma_of_2 = dc_fixpt_pow(dc_fixpt_from_int(2), >+ dc_fixpt_recip(args->gamma)); >+ } >+ scratch_1 = dc_fixpt_add(one, args->a3); >+ if (pow_buffer_ptr < 16) >+ scratch_2 = dc_fixpt_pow(args->arg, >+ dc_fixpt_recip(args->gamma)); >+ else >+ scratch_2 = dc_fixpt_mul(gamma_of_2, >+ pow_buffer[pow_buffer_ptr%16]); >+ >+ pow_buffer[pow_buffer_ptr%16] = scratch_2; >+ pow_buffer_ptr++; >+ >+ scratch_1 = dc_fixpt_mul(scratch_1, scratch_2); >+ scratch_1 = dc_fixpt_sub(scratch_1, args->a2); >+ >+ return scratch_1; >+ } > else >- return dc_fixpt_mul( >- arg, >- a1); >+ return dc_fixpt_mul(args->arg, args->a1); > } > > static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg) > { > struct fixed31_32 gamma = dc_fixpt_from_fraction(22, 10); > >- return translate_from_linear_space(arg, >- dc_fixpt_zero, >- dc_fixpt_zero, >- dc_fixpt_zero, >- dc_fixpt_zero, >- gamma); >+ scratch_gamma_args.arg = arg; >+ scratch_gamma_args.a0 = dc_fixpt_zero; >+ scratch_gamma_args.a1 = dc_fixpt_zero; >+ scratch_gamma_args.a2 = dc_fixpt_zero; >+ scratch_gamma_args.a3 = dc_fixpt_zero; >+ scratch_gamma_args.gamma = gamma; >+ >+ return translate_from_linear_space(&scratch_gamma_args); > } > > static struct fixed31_32 translate_to_linear_space( >@@ -365,18 +420,19 @@ > return linear; > } > >-static inline struct fixed31_32 translate_from_linear_space_ex( >+static struct fixed31_32 translate_from_linear_space_ex( > struct fixed31_32 arg, > struct gamma_coefficients *coeff, > uint32_t color_index) > { >- return translate_from_linear_space( >- arg, >- coeff->a0[color_index], >- coeff->a1[color_index], >- coeff->a2[color_index], >- coeff->a3[color_index], >- coeff->user_gamma[color_index]); >+ scratch_gamma_args.arg = arg; >+ scratch_gamma_args.a0 = coeff->a0[color_index]; >+ scratch_gamma_args.a1 = coeff->a1[color_index]; >+ scratch_gamma_args.a2 = coeff->a2[color_index]; >+ scratch_gamma_args.a3 = coeff->a3[color_index]; >+ scratch_gamma_args.gamma = coeff->user_gamma[color_index]; >+ >+ return translate_from_linear_space(&scratch_gamma_args); > } > > >@@ -709,30 +765,42 @@ > } > } > >-static void build_regamma(struct pwl_float_data_ex *rgb_regamma, >+static bool build_regamma(struct pwl_float_data_ex *rgb_regamma, > uint32_t hw_points_num, >- const struct hw_x_point *coordinate_x, enum gamma_type_index type) >+ const struct hw_x_point *coordinate_x, enum dc_transfer_func_predefined type) > { > uint32_t i; >+ bool ret = false; > >- struct gamma_coefficients coeff; >+ struct gamma_coefficients *coeff; > struct pwl_float_data_ex *rgb = rgb_regamma; > const struct hw_x_point *coord_x = coordinate_x; > >- build_coefficients(&coeff, type); >+ coeff = kvzalloc(sizeof(*coeff), GFP_KERNEL); >+ if (!coeff) >+ goto release; > >- i = 0; >+ if (!build_coefficients(coeff, type)) >+ goto release; > >- while (i != hw_points_num + 1) { >+ memset(pow_buffer, 0, NUM_PTS_IN_REGION * sizeof(struct fixed31_32)); >+ pow_buffer_ptr = 0; // see variable definition for more info >+ i = 0; >+ while (i <= hw_points_num) { > /*TODO use y vs r,g,b*/ > rgb->r = translate_from_linear_space_ex( >- coord_x->x, &coeff, 0); >+ coord_x->x, coeff, 0); > rgb->g = rgb->r; > rgb->b = rgb->r; > ++coord_x; > ++rgb; > ++i; > } >+ pow_buffer_ptr = -1; // reset back to no optimize >+ ret = true; >+release: >+ kfree(coeff); >+ return ret; > } > > static void hermite_spline_eetf(struct fixed31_32 input_x, >@@ -862,6 +930,8 @@ > else > max_content = max_display; > >+ if (!use_eetf) >+ pow_buffer_ptr = 0; // see var definition for more info > rgb += 32; // first 32 points have problems with fixed point, too small > coord_x += 32; > for (i = 32; i <= hw_points_num; i++) { >@@ -900,19 +970,23 @@ > ++coord_x; > ++rgb; > } >+ pow_buffer_ptr = -1; > > return true; > } > >-static void build_degamma(struct pwl_float_data_ex *curve, >+static bool build_degamma(struct pwl_float_data_ex *curve, > uint32_t hw_points_num, >- const struct hw_x_point *coordinate_x, enum gamma_type_index type) >+ const struct hw_x_point *coordinate_x, enum dc_transfer_func_predefined type) > { > uint32_t i; > struct gamma_coefficients coeff; > uint32_t begin_index, end_index; >+ bool ret = false; >+ >+ if (!build_coefficients(&coeff, type)) >+ goto release; > >- build_coefficients(&coeff, type); > i = 0; > > /* X points is 2^-25 to 2^7 >@@ -941,11 +1015,19 @@ > curve[i].b = dc_fixpt_one; > i++; > } >+ ret = true; >+release: >+ return ret; > } > >+ >+ >+ >+ > static void build_hlg_degamma(struct pwl_float_data_ex *degamma, > uint32_t hw_points_num, >- const struct hw_x_point *coordinate_x, bool is_light0_12) >+ const struct hw_x_point *coordinate_x, >+ uint32_t sdr_white_level, uint32_t max_luminance_nits) > { > uint32_t i; > >@@ -953,9 +1035,9 @@ > const struct hw_x_point *coord_x = coordinate_x; > > i = 0; >- >+ //check when i == 434 > while (i != hw_points_num + 1) { >- compute_hlg_oetf(coord_x->x, is_light0_12, &rgb->r); >+ compute_hlg_eotf(coord_x->x, &rgb->r, sdr_white_level, max_luminance_nits); > rgb->g = rgb->r; > rgb->b = rgb->r; > ++coord_x; >@@ -964,9 +1046,11 @@ > } > } > >+ > static void build_hlg_regamma(struct pwl_float_data_ex *regamma, > uint32_t hw_points_num, >- const struct hw_x_point *coordinate_x, bool is_light0_12) >+ const struct hw_x_point *coordinate_x, >+ uint32_t sdr_white_level, uint32_t max_luminance_nits) > { > uint32_t i; > >@@ -975,8 +1059,9 @@ > > i = 0; > >+ //when i == 471 > while (i != hw_points_num + 1) { >- compute_hlg_eotf(coord_x->x, is_light0_12, &rgb->r); >+ compute_hlg_oetf(coord_x->x, &rgb->r, sdr_white_level, max_luminance_nits); > rgb->g = rgb->r; > rgb->b = rgb->r; > ++coord_x; >@@ -1572,14 +1657,15 @@ > output_tf->tf == TRANSFER_FUNCTION_SRGB) { > if (ramp == NULL) > return true; >- if ((ramp->is_logical_identity) || >+ if ((ramp->is_identity && ramp->type != GAMMA_CS_TFM_1D) || > (!mapUserRamp && ramp->type == GAMMA_RGB_256)) > return true; > } > > output_tf->type = TF_TYPE_DISTRIBUTED_POINTS; > >- if (ramp && (mapUserRamp || ramp->type != GAMMA_RGB_256)) { >+ if (ramp && ramp->type != GAMMA_CS_TFM_1D && >+ (mapUserRamp || ramp->type != GAMMA_RGB_256)) { > rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS, > sizeof(*rgb_user), > GFP_KERNEL); >@@ -1634,6 +1720,12 @@ > MAX_HW_POINTS, > coordinates_x, > fs_params); >+ } else if (tf == TRANSFER_FUNCTION_HLG) { >+ build_freesync_hdr(rgb_regamma, >+ MAX_HW_POINTS, >+ coordinates_x, >+ fs_params); >+ > } else { > tf_pts->end_exponent = 0; > tf_pts->x_point_at_y1_red = 1; >@@ -1642,9 +1734,7 @@ > > build_regamma(rgb_regamma, > MAX_HW_POINTS, >- coordinates_x, tf == TRANSFER_FUNCTION_SRGB ? gamma_type_index_2_4 : >- tf == TRANSFER_FUNCTION_GAMMA22 ? >- gamma_type_index_2_2_flat : gamma_type_index_2_2); >+ coordinates_x, tf); > } > map_regamma_hw_to_x_user(ramp, coeff, rgb_user, > coordinates_x, axis_x, rgb_regamma, >@@ -1845,13 +1935,19 @@ > MAX_HW_POINTS, > coordinates_x); > else if (tf == TRANSFER_FUNCTION_SRGB || >- tf == TRANSFER_FUNCTION_BT709) >+ tf == TRANSFER_FUNCTION_BT709 || >+ tf == TRANSFER_FUNCTION_GAMMA22 || >+ tf == TRANSFER_FUNCTION_GAMMA24 || >+ tf == TRANSFER_FUNCTION_GAMMA26) > build_degamma(curve, > MAX_HW_POINTS, > coordinates_x, >- tf == TRANSFER_FUNCTION_SRGB ? >- gamma_type_index_2_4 : tf == TRANSFER_FUNCTION_GAMMA22 ? >- gamma_type_index_2_2_flat : gamma_type_index_2_2); >+ tf); >+ else if (tf == TRANSFER_FUNCTION_HLG) >+ build_hlg_degamma(curve, >+ MAX_HW_POINTS, >+ coordinates_x, >+ 80, 1000); > else if (tf == TRANSFER_FUNCTION_LINEAR) { > // just copy coordinates_x into curve > i = 0; >@@ -1938,7 +2034,10 @@ > > kvfree(rgb_regamma); > } else if (trans == TRANSFER_FUNCTION_SRGB || >- trans == TRANSFER_FUNCTION_BT709) { >+ trans == TRANSFER_FUNCTION_BT709 || >+ trans == TRANSFER_FUNCTION_GAMMA22 || >+ trans == TRANSFER_FUNCTION_GAMMA24 || >+ trans == TRANSFER_FUNCTION_GAMMA26) { > rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS, > sizeof(*rgb_regamma), > GFP_KERNEL); >@@ -1952,9 +2051,7 @@ > build_regamma(rgb_regamma, > MAX_HW_POINTS, > coordinates_x, >- trans == TRANSFER_FUNCTION_SRGB ? >- gamma_type_index_2_4 : trans == TRANSFER_FUNCTION_GAMMA22 ? >- gamma_type_index_2_2_flat : gamma_type_index_2_2); >+ trans); > for (i = 0; i <= MAX_HW_POINTS ; i++) { > points->red[i] = rgb_regamma[i].r; > points->green[i] = rgb_regamma[i].g; >@@ -1963,18 +2060,21 @@ > ret = true; > > kvfree(rgb_regamma); >- } else if (trans == TRANSFER_FUNCTION_HLG || >- trans == TRANSFER_FUNCTION_HLG12) { >+ } else if (trans == TRANSFER_FUNCTION_HLG) { > rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS, > sizeof(*rgb_regamma), > GFP_KERNEL); > if (!rgb_regamma) > goto rgb_regamma_alloc_fail; >+ points->end_exponent = 4; >+ points->x_point_at_y1_red = 12; >+ points->x_point_at_y1_green = 12; >+ points->x_point_at_y1_blue = 12; > > build_hlg_regamma(rgb_regamma, > MAX_HW_POINTS, > coordinates_x, >- trans == TRANSFER_FUNCTION_HLG12 ? true:false); >+ 80, 1000); > for (i = 0; i <= MAX_HW_POINTS ; i++) { > points->red[i] = rgb_regamma[i].r; > points->green[i] = rgb_regamma[i].g; >@@ -2024,8 +2124,10 @@ > > kvfree(rgb_degamma); > } else if (trans == TRANSFER_FUNCTION_SRGB || >- trans == TRANSFER_FUNCTION_BT709 || >- trans == TRANSFER_FUNCTION_GAMMA22) { >+ trans == TRANSFER_FUNCTION_BT709 || >+ trans == TRANSFER_FUNCTION_GAMMA22 || >+ trans == TRANSFER_FUNCTION_GAMMA24 || >+ trans == TRANSFER_FUNCTION_GAMMA26) { > rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS, > sizeof(*rgb_degamma), > GFP_KERNEL); >@@ -2035,9 +2137,7 @@ > build_degamma(rgb_degamma, > MAX_HW_POINTS, > coordinates_x, >- trans == TRANSFER_FUNCTION_SRGB ? >- gamma_type_index_2_4 : trans == TRANSFER_FUNCTION_GAMMA22 ? >- gamma_type_index_2_2_flat : gamma_type_index_2_2); >+ trans); > for (i = 0; i <= MAX_HW_POINTS ; i++) { > points->red[i] = rgb_degamma[i].r; > points->green[i] = rgb_degamma[i].g; >@@ -2046,8 +2146,7 @@ > ret = true; > > kvfree(rgb_degamma); >- } else if (trans == TRANSFER_FUNCTION_HLG || >- trans == TRANSFER_FUNCTION_HLG12) { >+ } else if (trans == TRANSFER_FUNCTION_HLG) { > rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS, > sizeof(*rgb_degamma), > GFP_KERNEL); >@@ -2057,7 +2156,7 @@ > build_hlg_degamma(rgb_degamma, > MAX_HW_POINTS, > coordinates_x, >- trans == TRANSFER_FUNCTION_HLG12 ? true:false); >+ 80, 1000); > for (i = 0; i <= MAX_HW_POINTS ; i++) { > points->red[i] = rgb_degamma[i].r; > points->green[i] = rgb_degamma[i].g; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/color/color_gamma.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/color/color_gamma.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/color/color_gamma.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/color/color_gamma.h 2019-08-31 15:01:11.872736169 -0500 >@@ -82,7 +82,17 @@ > unsigned int skip_tm; // skip tm > }; > >+struct translate_from_linear_space_args { >+ struct fixed31_32 arg; >+ struct fixed31_32 a0; >+ struct fixed31_32 a1; >+ struct fixed31_32 a2; >+ struct fixed31_32 a3; >+ struct fixed31_32 gamma; >+}; >+ > void setup_x_points_distribution(void); >+void log_x_points_distribution(struct dal_logger *logger); > void precompute_pq(void); > void precompute_de_pq(void); > >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/freesync/freesync.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/freesync/freesync.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 2019-08-31 15:01:11.872736169 -0500 >@@ -52,93 +52,6 @@ > struct dc *dc; > }; > >-void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int value) >-{ >- unsigned int shift = 0; >- >- if (!mask || !dest) >- return; >- >- while (!((mask >> shift) & 1)) >- shift++; >- >- //reset >- *dest = *dest & ~mask; >- //set >- //dont let value span past mask >- value = value & (mask >> shift); >- //insert value >- *dest = *dest | (value << shift); >-} >- >-// VTEM Byte Offset >-#define VRR_VTEM_PB0 0 >-#define VRR_VTEM_PB1 1 >-#define VRR_VTEM_PB2 2 >-#define VRR_VTEM_PB3 3 >-#define VRR_VTEM_PB4 4 >-#define VRR_VTEM_PB5 5 >-#define VRR_VTEM_PB6 6 >- >-#define VRR_VTEM_MD0 7 >-#define VRR_VTEM_MD1 8 >-#define VRR_VTEM_MD2 9 >-#define VRR_VTEM_MD3 10 >- >- >-// VTEM Byte Masks >-//PB0 >-#define MASK__VRR_VTEM_PB0__RESERVED0 0x01 >-#define MASK__VRR_VTEM_PB0__SYNC 0x02 >-#define MASK__VRR_VTEM_PB0__VFR 0x04 >-#define MASK__VRR_VTEM_PB0__AFR 0x08 >-#define MASK__VRR_VTEM_PB0__DS_TYPE 0x30 >- //0: Periodic pseudo-static EM Data Set >- //1: Periodic dynamic EM Data Set >- //2: Unique EM Data Set >- //3: Reserved >-#define MASK__VRR_VTEM_PB0__END 0x40 >-#define MASK__VRR_VTEM_PB0__NEW 0x80 >- >-//PB1 >-#define MASK__VRR_VTEM_PB1__RESERVED1 0xFF >- >-//PB2 >-#define MASK__VRR_VTEM_PB2__ORGANIZATION_ID 0xFF >- //0: This is a Vendor Specific EM Data Set >- //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean) >- //2: This EM Data Set is defined by CTA-861-G >- //3: This EM Data Set is defined by VESA >-//PB3 >-#define MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB 0xFF >-//PB4 >-#define MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB 0xFF >-//PB5 >-#define MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF >-//PB6 >-#define MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF >- >- >- >-//PB7-27 (20 bytes): >-//PB7 = MD0 >-#define MASK__VRR_VTEM_MD0__VRR_EN 0x01 >-#define MASK__VRR_VTEM_MD0__M_CONST 0x02 >-#define MASK__VRR_VTEM_MD0__RESERVED2 0x0C >-#define MASK__VRR_VTEM_MD0__FVA_FACTOR_M1 0xF0 >- >-//MD1 >-#define MASK__VRR_VTEM_MD1__BASE_VFRONT 0xFF >- >-//MD2 >-#define MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98 0x03 >-#define MASK__VRR_VTEM_MD2__RB 0x04 >-#define MASK__VRR_VTEM_MD2__RESERVED3 0xF8 >- >-//MD3 >-#define MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07 0xFF >- >- > #define MOD_FREESYNC_TO_CORE(mod_freesync)\ > container_of(mod_freesync, struct core_freesync, public) > >@@ -435,6 +348,12 @@ > /* Either we've calculated the number of frames to insert, > * or we need to insert min duration frames > */ >+ if (last_render_time_in_us / frames_to_insert < >+ in_out_vrr->min_duration_in_us){ >+ frames_to_insert -= (frames_to_insert > 1) ? >+ 1 : 0; >+ } >+ > if (frames_to_insert > 0) > inserted_frame_duration_in_us = last_render_time_in_us / > frames_to_insert; >@@ -568,22 +487,64 @@ > return false; > } > >-static void build_vrr_infopacket_header_vtem(enum signal_type signal, >+static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr, >+ struct dc_info_packet *infopacket) >+{ >+ /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ >+ infopacket->sb[1] = 0x1A; >+ >+ /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ >+ infopacket->sb[2] = 0x00; >+ >+ /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ >+ infopacket->sb[3] = 0x00; >+ >+ /* PB4 = Reserved */ >+ >+ /* PB5 = Reserved */ >+ >+ /* PB6 = [Bits 7:3 = Reserved] */ >+ >+ /* PB6 = [Bit 0 = FreeSync Supported] */ >+ if (vrr->state != VRR_STATE_UNSUPPORTED) >+ infopacket->sb[6] |= 0x01; >+ >+ /* PB6 = [Bit 1 = FreeSync Enabled] */ >+ if (vrr->state != VRR_STATE_DISABLED && >+ vrr->state != VRR_STATE_UNSUPPORTED) >+ infopacket->sb[6] |= 0x02; >+ >+ /* PB6 = [Bit 2 = FreeSync Active] */ >+ if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || >+ vrr->state == VRR_STATE_ACTIVE_FIXED) >+ infopacket->sb[6] |= 0x04; >+ >+ /* PB7 = FreeSync Minimum refresh rate (Hz) */ >+ infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000); >+ >+ /* PB8 = FreeSync Maximum refresh rate (Hz) >+ * Note: We should never go above the field rate of the mode timing set. >+ */ >+ infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000); >+ >+ >+ //FreeSync HDR >+ infopacket->sb[9] = 0; >+ infopacket->sb[10] = 0; >+} >+ >+static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf, > struct dc_info_packet *infopacket) > { >- // HEADER >+ if (app_tf != TRANSFER_FUNC_UNKNOWN) { >+ infopacket->valid = true; > >- // HB0, HB1, HB2 indicates PacketType VTEMPacket >- infopacket->hb0 = 0x7F; >- infopacket->hb1 = 0xC0; >- infopacket->hb2 = 0x00; //sequence_index >- >- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB0], MASK__VRR_VTEM_PB0__VFR, 1); >- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB2], MASK__VRR_VTEM_PB2__ORGANIZATION_ID, 1); >- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB3], MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB, 0); >- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB4], MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB, 1); >- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB5], MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB, 0); >- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB6], MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB, 4); >+ infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active] >+ >+ if (app_tf == TRANSFER_FUNC_GAMMA_22) { >+ infopacket->sb[9] |= 0x04; // PB6 = [Bit 2 = Gamma 2.2 EOTF Active] >+ } >+ } > } > > static void build_vrr_infopacket_header_v1(enum signal_type signal, >@@ -684,105 +645,6 @@ > } > } > >-static void build_vrr_vtem_infopacket_data(const struct dc_stream_state *stream, >- const struct mod_vrr_params *vrr, >- struct dc_info_packet *infopacket) >-{ >- unsigned int fieldRateInHz; >- >- if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || >- vrr->state == VRR_STATE_ACTIVE_FIXED) { >- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD0], MASK__VRR_VTEM_MD0__VRR_EN, 1); >- } else { >- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD0], MASK__VRR_VTEM_MD0__VRR_EN, 0); >- } >- >- if (!stream->timing.vic) { >- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD1], MASK__VRR_VTEM_MD1__BASE_VFRONT, >- stream->timing.v_front_porch); >- >- >- /* TODO: In dal2, we check mode flags for a reduced blanking timing. >- * Need a way to relay that information to this function. >- * if("ReducedBlanking") >- * { >- * setFieldWithMask(&infopacket->sb[VRR_VTEM_MD2], MASK__VRR_VTEM_MD2__RB, 1; >- * } >- */ >- >- //TODO: DAL2 does FixPoint and rounding. Here we might need to account for that >- fieldRateInHz = (stream->timing.pix_clk_100hz * 100)/ >- (stream->timing.h_total * stream->timing.v_total); >- >- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD2], MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98, >- fieldRateInHz >> 8); >- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD3], MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07, >- fieldRateInHz); >- >- } >- infopacket->valid = true; >-} >- >-static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr, >- struct dc_info_packet *infopacket) >-{ >- /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ >- infopacket->sb[1] = 0x1A; >- >- /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ >- infopacket->sb[2] = 0x00; >- >- /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ >- infopacket->sb[3] = 0x00; >- >- /* PB4 = Reserved */ >- >- /* PB5 = Reserved */ >- >- /* PB6 = [Bits 7:3 = Reserved] */ >- >- /* PB6 = [Bit 0 = FreeSync Supported] */ >- if (vrr->state != VRR_STATE_UNSUPPORTED) >- infopacket->sb[6] |= 0x01; >- >- /* PB6 = [Bit 1 = FreeSync Enabled] */ >- if (vrr->state != VRR_STATE_DISABLED && >- vrr->state != VRR_STATE_UNSUPPORTED) >- infopacket->sb[6] |= 0x02; >- >- /* PB6 = [Bit 2 = FreeSync Active] */ >- if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || >- vrr->state == VRR_STATE_ACTIVE_FIXED) >- infopacket->sb[6] |= 0x04; >- >- /* PB7 = FreeSync Minimum refresh rate (Hz) */ >- infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000); >- >- /* PB8 = FreeSync Maximum refresh rate (Hz) >- * Note: We should never go above the field rate of the mode timing set. >- */ >- infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000); >- >- >- //FreeSync HDR >- infopacket->sb[9] = 0; >- infopacket->sb[10] = 0; >-} >- >-static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf, >- struct dc_info_packet *infopacket) >-{ >- if (app_tf != TRANSFER_FUNC_UNKNOWN) { >- infopacket->valid = true; >- >- infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active] >- >- if (app_tf == TRANSFER_FUNC_GAMMA_22) { >- infopacket->sb[9] |= 0x04; // PB6 = [Bit 2 = Gamma 2.2 EOTF Active] >- } >- } >-} >- > static void build_vrr_infopacket_checksum(unsigned int *payload_size, > struct dc_info_packet *infopacket) > { >@@ -835,21 +697,6 @@ > infopacket->valid = true; > } > >-static void build_vrr_infopacket_vtem(const struct dc_stream_state *stream, >- const struct mod_vrr_params *vrr, >- struct dc_info_packet *infopacket) >-{ >- //VTEM info packet for HdmiVrr >- >- memset(infopacket, 0, sizeof(struct dc_info_packet)); >- >- //VTEM Packet is structured differently >- build_vrr_infopacket_header_vtem(stream->signal, infopacket); >- build_vrr_vtem_infopacket_data(stream, vrr, infopacket); >- >- infopacket->valid = true; >-} >- > void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, > const struct dc_stream_state *stream, > const struct mod_vrr_params *vrr, >@@ -862,16 +709,13 @@ > * Check if Freesync is supported. Return if false. If true, > * set the corresponding bit in the info packet > */ >- if (!vrr->supported || (!vrr->send_info_frame && packet_type != PACKET_TYPE_VTEM)) >+ if (!vrr->supported || (!vrr->send_info_frame)) > return; > > switch (packet_type) { > case PACKET_TYPE_FS2: > build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket); > break; >- case PACKET_TYPE_VTEM: >- build_vrr_infopacket_vtem(stream, vrr, infopacket); >- break; > case PACKET_TYPE_VRR: > case PACKET_TYPE_FS1: > default: >@@ -887,8 +731,8 @@ > struct core_freesync *core_freesync = NULL; > unsigned long long nominal_field_rate_in_uhz = 0; > unsigned int refresh_range = 0; >- unsigned int min_refresh_in_uhz = 0; >- unsigned int max_refresh_in_uhz = 0; >+ unsigned long long min_refresh_in_uhz = 0; >+ unsigned long long max_refresh_in_uhz = 0; > > if (mod_freesync == NULL) > return; >@@ -915,7 +759,7 @@ > min_refresh_in_uhz = nominal_field_rate_in_uhz; > > if (!vrr_settings_require_update(core_freesync, >- in_config, min_refresh_in_uhz, max_refresh_in_uhz, >+ in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz, > in_out_vrr)) > return; > >@@ -931,15 +775,15 @@ > return; > > } else { >- in_out_vrr->min_refresh_in_uhz = min_refresh_in_uhz; >+ in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz; > in_out_vrr->max_duration_in_us = > calc_duration_in_us_from_refresh_in_uhz( >- min_refresh_in_uhz); >+ (unsigned int)min_refresh_in_uhz); > >- in_out_vrr->max_refresh_in_uhz = max_refresh_in_uhz; >+ in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz; > in_out_vrr->min_duration_in_us = > calc_duration_in_us_from_refresh_in_uhz( >- max_refresh_in_uhz); >+ (unsigned int)max_refresh_in_uhz); > > refresh_range = in_out_vrr->max_refresh_in_uhz - > in_out_vrr->min_refresh_in_uhz; >@@ -950,17 +794,18 @@ > in_out_vrr->fixed.ramping_active = in_config->ramping; > > in_out_vrr->btr.btr_enabled = in_config->btr; >+ > if (in_out_vrr->max_refresh_in_uhz < > 2 * in_out_vrr->min_refresh_in_uhz) > in_out_vrr->btr.btr_enabled = false; >+ > in_out_vrr->btr.btr_active = false; > in_out_vrr->btr.inserted_duration_in_us = 0; > in_out_vrr->btr.frames_to_insert = 0; > in_out_vrr->btr.frame_counter = 0; > in_out_vrr->btr.mid_point_in_us = >- in_out_vrr->min_duration_in_us + >- (in_out_vrr->max_duration_in_us - >- in_out_vrr->min_duration_in_us) / 2; >+ (in_out_vrr->min_duration_in_us + >+ in_out_vrr->max_duration_in_us) / 2; > > if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) { > in_out_vrr->adjust.v_total_min = stream->timing.v_total; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h 2019-08-31 15:01:11.872736169 -0500 >@@ -173,4 +173,6 @@ > uint32_t min_refresh_request_in_uhz, > uint32_t max_refresh_request_in_uhz); > >+ >+ > #endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h 2019-08-31 15:01:11.872736169 -0500 >@@ -27,10 +27,10 @@ > #define MOD_INFO_PACKET_H_ > > #include "mod_shared.h" >- > //Forward Declarations > struct dc_stream_state; > struct dc_info_packet; >+struct mod_vrr_params; > > void mod_build_vsc_infopacket(const struct dc_stream_state *stream, > struct dc_info_packet *info_packet); >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c 2019-08-31 15:01:11.872736169 -0500 >@@ -27,9 +27,78 @@ > #include "core_types.h" > #include "dc_types.h" > #include "mod_shared.h" >+#include "mod_freesync.h" >+#include "dc.h" > > #define HDMI_INFOFRAME_TYPE_VENDOR 0x81 > >+// VTEM Byte Offset >+#define VTEM_PB0 0 >+#define VTEM_PB1 1 >+#define VTEM_PB2 2 >+#define VTEM_PB3 3 >+#define VTEM_PB4 4 >+#define VTEM_PB5 5 >+#define VTEM_PB6 6 >+ >+#define VTEM_MD0 7 >+#define VTEM_MD1 8 >+#define VTEM_MD2 9 >+#define VTEM_MD3 10 >+ >+ >+// VTEM Byte Masks >+//PB0 >+#define MASK_VTEM_PB0__RESERVED0 0x01 >+#define MASK_VTEM_PB0__SYNC 0x02 >+#define MASK_VTEM_PB0__VFR 0x04 >+#define MASK_VTEM_PB0__AFR 0x08 >+#define MASK_VTEM_PB0__DS_TYPE 0x30 >+ //0: Periodic pseudo-static EM Data Set >+ //1: Periodic dynamic EM Data Set >+ //2: Unique EM Data Set >+ //3: Reserved >+#define MASK_VTEM_PB0__END 0x40 >+#define MASK_VTEM_PB0__NEW 0x80 >+ >+//PB1 >+#define MASK_VTEM_PB1__RESERVED1 0xFF >+ >+//PB2 >+#define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF >+ //0: This is a Vendor Specific EM Data Set >+ //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean) >+ //2: This EM Data Set is defined by CTA-861-G >+ //3: This EM Data Set is defined by VESA >+//PB3 >+#define MASK_VTEM_PB3__DATA_SET_TAG_MSB 0xFF >+//PB4 >+#define MASK_VTEM_PB4__DATA_SET_TAG_LSB 0xFF >+//PB5 >+#define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF >+//PB6 >+#define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF >+ >+ >+ >+//PB7-27 (20 bytes): >+//PB7 = MD0 >+#define MASK_VTEM_MD0__VRR_EN 0x01 >+#define MASK_VTEM_MD0__M_CONST 0x02 >+#define MASK_VTEM_MD0__RESERVED2 0x0C >+#define MASK_VTEM_MD0__FVA_FACTOR_M1 0xF0 >+ >+//MD1 >+#define MASK_VTEM_MD1__BASE_VFRONT 0xFF >+ >+//MD2 >+#define MASK_VTEM_MD2__BASE_REFRESH_RATE_98 0x03 >+#define MASK_VTEM_MD2__RB 0x04 >+#define MASK_VTEM_MD2__RESERVED3 0xF8 >+ >+//MD3 >+#define MASK_VTEM_MD3__BASE_REFRESH_RATE_07 0xFF >+ > enum ColorimetryRGBDP { > ColorimetryRGB_DP_sRGB = 0, > ColorimetryRGB_DP_AdobeRGB = 3, >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/power/power_helpers.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/power/power_helpers.c >--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 2019-08-31 15:01:11.872736169 -0500 >@@ -66,6 +66,39 @@ > { 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */ > }; > >+struct abm_parameters { >+ unsigned char min_reduction; >+ unsigned char max_reduction; >+ unsigned char bright_pos_gain; >+ unsigned char dark_pos_gain; >+ unsigned char brightness_gain; >+ unsigned char contrast_factor; >+ unsigned char deviation_gain; >+ unsigned char min_knee; >+ unsigned char max_knee; >+}; >+ >+static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = { >+// min_red max_red bright_pos dark_pos brightness_gain contrast deviation min_knee max_knee >+ {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xE0}, >+ {0xff, 0x85, 0x20, 0x00, 0xff, 0x90, 0xa8, 0x40, 0xE0}, >+ {0xff, 0x40, 0x20, 0x00, 0xff, 0x90, 0x68, 0x40, 0xE0}, >+ {0x82, 0x4d, 0x20, 0x00, 0x00, 0x90, 0xb3, 0x70, 0x70}, >+}; >+ >+static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = { >+// min_red max_red bright_pos dark_pos brightness_gain contrast deviation min_knee max_knee >+ {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xa8, 0xb3, 0x70, 0x70}, >+ {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xa8, 0xb3, 0x70, 0x70}, >+ {0x99, 0x65, 0x20, 0x00, 0x00, 0xa8, 0xb3, 0x70, 0x70}, >+ {0x82, 0x4d, 0x20, 0x00, 0x00, 0xa8, 0xb3, 0x70, 0x70}, >+}; >+ >+static const struct abm_parameters * const abm_settings[] = { >+ abm_settings_config0, >+ abm_settings_config1, >+}; >+ > #define NUM_AMBI_LEVEL 5 > #define NUM_AGGR_LEVEL 4 > #define NUM_POWER_FN_SEGS 8 >@@ -131,11 +164,13 @@ > uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ > uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ > uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ >- uint8_t hybridFactor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */ >- uint8_t contrastFactor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */ >+ uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */ >+ uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */ > uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */ > uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */ >- uint8_t pad[29]; /* 0x63 U0.8 */ >+ uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */ >+ uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */ >+ uint8_t pad[21]; /* 0x6b U0.8 */ > > /* parameters for crgb conversion */ > uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ >@@ -501,15 +536,72 @@ > ram_table->dark_pos_gain[4][2] = 0x00; > ram_table->dark_pos_gain[4][3] = 0x00; > >- ram_table->hybridFactor[0] = 0xff; >- ram_table->hybridFactor[1] = 0xff; >- ram_table->hybridFactor[2] = 0xff; >- ram_table->hybridFactor[3] = 0xc0; >- >- ram_table->contrastFactor[0] = 0x99; >- ram_table->contrastFactor[1] = 0x99; >- ram_table->contrastFactor[2] = 0x90; >- ram_table->contrastFactor[3] = 0x80; >+ ram_table->hybrid_factor[0] = 0xff; >+ ram_table->hybrid_factor[1] = 0xff; >+ ram_table->hybrid_factor[2] = 0xff; >+ ram_table->hybrid_factor[3] = 0xc0; >+ >+ ram_table->contrast_factor[0] = 0x99; >+ ram_table->contrast_factor[1] = 0x99; >+ ram_table->contrast_factor[2] = 0x90; >+ ram_table->contrast_factor[3] = 0x80; >+ >+ ram_table->iir_curve[0] = 0x65; >+ ram_table->iir_curve[1] = 0x65; >+ ram_table->iir_curve[2] = 0x65; >+ ram_table->iir_curve[3] = 0x65; >+ ram_table->iir_curve[4] = 0x65; >+ >+ //Gamma 2.2 >+ ram_table->crgb_thresh[0] = cpu_to_be16(0x127c); >+ ram_table->crgb_thresh[1] = cpu_to_be16(0x151b); >+ ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5); >+ ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56); >+ ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83); >+ ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72); >+ ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0); >+ ram_table->crgb_thresh[7] = cpu_to_be16(0x232b); >+ ram_table->crgb_offset[0] = cpu_to_be16(0x2999); >+ ram_table->crgb_offset[1] = cpu_to_be16(0x3999); >+ ram_table->crgb_offset[2] = cpu_to_be16(0x4666); >+ ram_table->crgb_offset[3] = cpu_to_be16(0x5999); >+ ram_table->crgb_offset[4] = cpu_to_be16(0x6333); >+ ram_table->crgb_offset[5] = cpu_to_be16(0x7800); >+ ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); >+ ram_table->crgb_offset[7] = cpu_to_be16(0xa000); >+ ram_table->crgb_slope[0] = cpu_to_be16(0x3609); >+ ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa); >+ ram_table->crgb_slope[2] = cpu_to_be16(0x27ea); >+ ram_table->crgb_slope[3] = cpu_to_be16(0x235d); >+ ram_table->crgb_slope[4] = cpu_to_be16(0x2042); >+ ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3); >+ ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a); >+ ram_table->crgb_slope[7] = cpu_to_be16(0x1910); >+ >+ fill_backlight_transform_table_v_2_2( >+ params, ram_table); >+} >+ >+void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params) >+{ >+ unsigned int i, j; >+ unsigned int set = params.set; >+ >+ ram_table->flags = 0x0; >+ for (i = 0; i < NUM_AGGR_LEVEL; i++) { >+ ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain; >+ ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor; >+ ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain; >+ ram_table->min_knee[i] = abm_settings[set][i].min_knee; >+ ram_table->max_knee[i] = abm_settings[set][i].max_knee; >+ >+ for (j = 0; j < NUM_AMBI_LEVEL; j++) { >+ ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction; >+ ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction; >+ ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain; >+ ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain; >+ } >+ } > > ram_table->iir_curve[0] = 0x65; > ram_table->iir_curve[1] = 0x65; >@@ -561,7 +653,12 @@ > > memset(&ram_table, 0, sizeof(ram_table)); > >- if (dmcu->dmcu_version.abm_version == 0x22) { >+ if (dmcu->dmcu_version.abm_version == 0x23) { >+ fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params); >+ >+ result = dmcu->funcs->load_iram( >+ dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); >+ } else if (dmcu->dmcu_version.abm_version == 0x22) { > fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params); > > result = dmcu->funcs->load_iram( >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/amd_shared.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/amd_shared.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/include/amd_shared.h 2019-08-25 14:01:23.000000000 -0500 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/amd_shared.h 2019-08-31 15:01:11.872736169 -0500 >@@ -142,6 +142,7 @@ > > enum DC_FEATURE_MASK { > DC_FBC_MASK = 0x1, >+ DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2, > }; > > enum amd_dpm_forced_level; >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/arct_ip_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/arct_ip_offset.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/include/arct_ip_offset.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/arct_ip_offset.h 2019-08-31 15:01:11.873736170 -0500 >@@ -0,0 +1,1650 @@ >+/* >+ * Copyright (C) 2018 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included >+ * in all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN >+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN >+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. >+ */ >+#ifndef _arct_ip_offset_HEADER >+#define _arct_ip_offset_HEADER >+ >+#define MAX_INSTANCE 8 >+#define MAX_SEGMENT 6 >+ >+ >+struct IP_BASE_INSTANCE >+{ >+ unsigned int segment[MAX_SEGMENT]; >+}; >+ >+struct IP_BASE >+{ >+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; >+}; >+ >+ >+static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } }, >+ { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } }, >+ { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } }, >+ { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } }, >+ { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } }, >+ { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } }, >+ { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } }, >+ { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } }, >+ { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } }, >+ { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } }, >+ { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } }, >+ { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } }, >+ { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } }, >+ { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } }; >+static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } }, >+ { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } }, >+ { { 0, 0, 0, 0, 0, 0 } } } }; >+ >+ >+ >+#define ATHUB_BASE__INST0_SEG0 0x00000C20 >+#define ATHUB_BASE__INST0_SEG1 0x00012460 >+#define ATHUB_BASE__INST0_SEG2 0x00408C00 >+#define ATHUB_BASE__INST0_SEG3 0 >+#define ATHUB_BASE__INST0_SEG4 0 >+#define ATHUB_BASE__INST0_SEG5 0 >+ >+#define ATHUB_BASE__INST1_SEG0 0 >+#define ATHUB_BASE__INST1_SEG1 0 >+#define ATHUB_BASE__INST1_SEG2 0 >+#define ATHUB_BASE__INST1_SEG3 0 >+#define ATHUB_BASE__INST1_SEG4 0 >+#define ATHUB_BASE__INST1_SEG5 0 >+ >+#define ATHUB_BASE__INST2_SEG0 0 >+#define ATHUB_BASE__INST2_SEG1 0 >+#define ATHUB_BASE__INST2_SEG2 0 >+#define ATHUB_BASE__INST2_SEG3 0 >+#define ATHUB_BASE__INST2_SEG4 0 >+#define ATHUB_BASE__INST2_SEG5 0 >+ >+#define ATHUB_BASE__INST3_SEG0 0 >+#define ATHUB_BASE__INST3_SEG1 0 >+#define ATHUB_BASE__INST3_SEG2 0 >+#define ATHUB_BASE__INST3_SEG3 0 >+#define ATHUB_BASE__INST3_SEG4 0 >+#define ATHUB_BASE__INST3_SEG5 0 >+ >+#define ATHUB_BASE__INST4_SEG0 0 >+#define ATHUB_BASE__INST4_SEG1 0 >+#define ATHUB_BASE__INST4_SEG2 0 >+#define ATHUB_BASE__INST4_SEG3 0 >+#define ATHUB_BASE__INST4_SEG4 0 >+#define ATHUB_BASE__INST4_SEG5 0 >+ >+#define ATHUB_BASE__INST5_SEG0 0 >+#define ATHUB_BASE__INST5_SEG1 0 >+#define ATHUB_BASE__INST5_SEG2 0 >+#define ATHUB_BASE__INST5_SEG3 0 >+#define ATHUB_BASE__INST5_SEG4 0 >+#define ATHUB_BASE__INST5_SEG5 0 >+ >+#define ATHUB_BASE__INST6_SEG0 0 >+#define ATHUB_BASE__INST6_SEG1 0 >+#define ATHUB_BASE__INST6_SEG2 0 >+#define ATHUB_BASE__INST6_SEG3 0 >+#define ATHUB_BASE__INST6_SEG4 0 >+#define ATHUB_BASE__INST6_SEG5 0 >+ >+#define ATHUB_BASE__INST7_SEG0 0 >+#define ATHUB_BASE__INST7_SEG1 0 >+#define ATHUB_BASE__INST7_SEG2 0 >+#define ATHUB_BASE__INST7_SEG3 0 >+#define ATHUB_BASE__INST7_SEG4 0 >+#define ATHUB_BASE__INST7_SEG5 0 >+ >+#define CLK_BASE__INST0_SEG0 0x000120C0 >+#define CLK_BASE__INST0_SEG1 0x00016C00 >+#define CLK_BASE__INST0_SEG2 0x00401800 >+#define CLK_BASE__INST0_SEG3 0 >+#define CLK_BASE__INST0_SEG4 0 >+#define CLK_BASE__INST0_SEG5 0 >+ >+#define CLK_BASE__INST1_SEG0 0x000120E0 >+#define CLK_BASE__INST1_SEG1 0x00016E00 >+#define CLK_BASE__INST1_SEG2 0x00401C00 >+#define CLK_BASE__INST1_SEG3 0 >+#define CLK_BASE__INST1_SEG4 0 >+#define CLK_BASE__INST1_SEG5 0 >+ >+#define CLK_BASE__INST2_SEG0 0x00012100 >+#define CLK_BASE__INST2_SEG1 0x00017000 >+#define CLK_BASE__INST2_SEG2 0x00402000 >+#define CLK_BASE__INST2_SEG3 0 >+#define CLK_BASE__INST2_SEG4 0 >+#define CLK_BASE__INST2_SEG5 0 >+ >+#define CLK_BASE__INST3_SEG0 0x00012120 >+#define CLK_BASE__INST3_SEG1 0x00017200 >+#define CLK_BASE__INST3_SEG2 0x00402400 >+#define CLK_BASE__INST3_SEG3 0 >+#define CLK_BASE__INST3_SEG4 0 >+#define CLK_BASE__INST3_SEG5 0 >+ >+#define CLK_BASE__INST4_SEG0 0x000136C0 >+#define CLK_BASE__INST4_SEG1 0x0001B000 >+#define CLK_BASE__INST4_SEG2 0x0042D800 >+#define CLK_BASE__INST4_SEG3 0 >+#define CLK_BASE__INST4_SEG4 0 >+#define CLK_BASE__INST4_SEG5 0 >+ >+#define CLK_BASE__INST5_SEG0 0x00013720 >+#define CLK_BASE__INST5_SEG1 0x0001B200 >+#define CLK_BASE__INST5_SEG2 0x0042E400 >+#define CLK_BASE__INST5_SEG3 0 >+#define CLK_BASE__INST5_SEG4 0 >+#define CLK_BASE__INST5_SEG5 0 >+ >+#define CLK_BASE__INST6_SEG0 0x000125E0 >+#define CLK_BASE__INST6_SEG1 0x00017E00 >+#define CLK_BASE__INST6_SEG2 0x0040BC00 >+#define CLK_BASE__INST6_SEG3 0 >+#define CLK_BASE__INST6_SEG4 0 >+#define CLK_BASE__INST6_SEG5 0 >+ >+#define CLK_BASE__INST7_SEG0 0 >+#define CLK_BASE__INST7_SEG1 0 >+#define CLK_BASE__INST7_SEG2 0 >+#define CLK_BASE__INST7_SEG3 0 >+#define CLK_BASE__INST7_SEG4 0 >+#define CLK_BASE__INST7_SEG5 0 >+ >+#define DF_BASE__INST0_SEG0 0x00007000 >+#define DF_BASE__INST0_SEG1 0x000125C0 >+#define DF_BASE__INST0_SEG2 0x0040B800 >+#define DF_BASE__INST0_SEG3 0 >+#define DF_BASE__INST0_SEG4 0 >+#define DF_BASE__INST0_SEG5 0 >+ >+#define DF_BASE__INST1_SEG0 0 >+#define DF_BASE__INST1_SEG1 0 >+#define DF_BASE__INST1_SEG2 0 >+#define DF_BASE__INST1_SEG3 0 >+#define DF_BASE__INST1_SEG4 0 >+#define DF_BASE__INST1_SEG5 0 >+ >+#define DF_BASE__INST2_SEG0 0 >+#define DF_BASE__INST2_SEG1 0 >+#define DF_BASE__INST2_SEG2 0 >+#define DF_BASE__INST2_SEG3 0 >+#define DF_BASE__INST2_SEG4 0 >+#define DF_BASE__INST2_SEG5 0 >+ >+#define DF_BASE__INST3_SEG0 0 >+#define DF_BASE__INST3_SEG1 0 >+#define DF_BASE__INST3_SEG2 0 >+#define DF_BASE__INST3_SEG3 0 >+#define DF_BASE__INST3_SEG4 0 >+#define DF_BASE__INST3_SEG5 0 >+ >+#define DF_BASE__INST4_SEG0 0 >+#define DF_BASE__INST4_SEG1 0 >+#define DF_BASE__INST4_SEG2 0 >+#define DF_BASE__INST4_SEG3 0 >+#define DF_BASE__INST4_SEG4 0 >+#define DF_BASE__INST4_SEG5 0 >+ >+#define DF_BASE__INST5_SEG0 0 >+#define DF_BASE__INST5_SEG1 0 >+#define DF_BASE__INST5_SEG2 0 >+#define DF_BASE__INST5_SEG3 0 >+#define DF_BASE__INST5_SEG4 0 >+#define DF_BASE__INST5_SEG5 0 >+ >+#define DF_BASE__INST6_SEG0 0 >+#define DF_BASE__INST6_SEG1 0 >+#define DF_BASE__INST6_SEG2 0 >+#define DF_BASE__INST6_SEG3 0 >+#define DF_BASE__INST6_SEG4 0 >+#define DF_BASE__INST6_SEG5 0 >+ >+#define DF_BASE__INST7_SEG0 0 >+#define DF_BASE__INST7_SEG1 0 >+#define DF_BASE__INST7_SEG2 0 >+#define DF_BASE__INST7_SEG3 0 >+#define DF_BASE__INST7_SEG4 0 >+#define DF_BASE__INST7_SEG5 0 >+ >+#define FUSE_BASE__INST0_SEG0 0x000120A0 >+#define FUSE_BASE__INST0_SEG1 0x00017400 >+#define FUSE_BASE__INST0_SEG2 0x00401400 >+#define FUSE_BASE__INST0_SEG3 0 >+#define FUSE_BASE__INST0_SEG4 0 >+#define FUSE_BASE__INST0_SEG5 0 >+ >+#define FUSE_BASE__INST1_SEG0 0 >+#define FUSE_BASE__INST1_SEG1 0 >+#define FUSE_BASE__INST1_SEG2 0 >+#define FUSE_BASE__INST1_SEG3 0 >+#define FUSE_BASE__INST1_SEG4 0 >+#define FUSE_BASE__INST1_SEG5 0 >+ >+#define FUSE_BASE__INST2_SEG0 0 >+#define FUSE_BASE__INST2_SEG1 0 >+#define FUSE_BASE__INST2_SEG2 0 >+#define FUSE_BASE__INST2_SEG3 0 >+#define FUSE_BASE__INST2_SEG4 0 >+#define FUSE_BASE__INST2_SEG5 0 >+ >+#define FUSE_BASE__INST3_SEG0 0 >+#define FUSE_BASE__INST3_SEG1 0 >+#define FUSE_BASE__INST3_SEG2 0 >+#define FUSE_BASE__INST3_SEG3 0 >+#define FUSE_BASE__INST3_SEG4 0 >+#define FUSE_BASE__INST3_SEG5 0 >+ >+#define FUSE_BASE__INST4_SEG0 0 >+#define FUSE_BASE__INST4_SEG1 0 >+#define FUSE_BASE__INST4_SEG2 0 >+#define FUSE_BASE__INST4_SEG3 0 >+#define FUSE_BASE__INST4_SEG4 0 >+#define FUSE_BASE__INST4_SEG5 0 >+ >+#define FUSE_BASE__INST5_SEG0 0 >+#define FUSE_BASE__INST5_SEG1 0 >+#define FUSE_BASE__INST5_SEG2 0 >+#define FUSE_BASE__INST5_SEG3 0 >+#define FUSE_BASE__INST5_SEG4 0 >+#define FUSE_BASE__INST5_SEG5 0 >+ >+#define FUSE_BASE__INST6_SEG0 0 >+#define FUSE_BASE__INST6_SEG1 0 >+#define FUSE_BASE__INST6_SEG2 0 >+#define FUSE_BASE__INST6_SEG3 0 >+#define FUSE_BASE__INST6_SEG4 0 >+#define FUSE_BASE__INST6_SEG5 0 >+ >+#define FUSE_BASE__INST7_SEG0 0 >+#define FUSE_BASE__INST7_SEG1 0 >+#define FUSE_BASE__INST7_SEG2 0 >+#define FUSE_BASE__INST7_SEG3 0 >+#define FUSE_BASE__INST7_SEG4 0 >+#define FUSE_BASE__INST7_SEG5 0 >+ >+#define GC_BASE__INST0_SEG0 0x00002000 >+#define GC_BASE__INST0_SEG1 0x0000A000 >+#define GC_BASE__INST0_SEG2 0x00012160 >+#define GC_BASE__INST0_SEG3 0x00402C00 >+#define GC_BASE__INST0_SEG4 0 >+#define GC_BASE__INST0_SEG5 0 >+ >+#define GC_BASE__INST1_SEG0 0 >+#define GC_BASE__INST1_SEG1 0 >+#define GC_BASE__INST1_SEG2 0 >+#define GC_BASE__INST1_SEG3 0 >+#define GC_BASE__INST1_SEG4 0 >+#define GC_BASE__INST1_SEG5 0 >+ >+#define GC_BASE__INST2_SEG0 0 >+#define GC_BASE__INST2_SEG1 0 >+#define GC_BASE__INST2_SEG2 0 >+#define GC_BASE__INST2_SEG3 0 >+#define GC_BASE__INST2_SEG4 0 >+#define GC_BASE__INST2_SEG5 0 >+ >+#define GC_BASE__INST3_SEG0 0 >+#define GC_BASE__INST3_SEG1 0 >+#define GC_BASE__INST3_SEG2 0 >+#define GC_BASE__INST3_SEG3 0 >+#define GC_BASE__INST3_SEG4 0 >+#define GC_BASE__INST3_SEG5 0 >+ >+#define GC_BASE__INST4_SEG0 0 >+#define GC_BASE__INST4_SEG1 0 >+#define GC_BASE__INST4_SEG2 0 >+#define GC_BASE__INST4_SEG3 0 >+#define GC_BASE__INST4_SEG4 0 >+#define GC_BASE__INST4_SEG5 0 >+ >+#define GC_BASE__INST5_SEG0 0 >+#define GC_BASE__INST5_SEG1 0 >+#define GC_BASE__INST5_SEG2 0 >+#define GC_BASE__INST5_SEG3 0 >+#define GC_BASE__INST5_SEG4 0 >+#define GC_BASE__INST5_SEG5 0 >+ >+#define GC_BASE__INST6_SEG0 0 >+#define GC_BASE__INST6_SEG1 0 >+#define GC_BASE__INST6_SEG2 0 >+#define GC_BASE__INST6_SEG3 0 >+#define GC_BASE__INST6_SEG4 0 >+#define GC_BASE__INST6_SEG5 0 >+ >+#define GC_BASE__INST7_SEG0 0 >+#define GC_BASE__INST7_SEG1 0 >+#define GC_BASE__INST7_SEG2 0 >+#define GC_BASE__INST7_SEG3 0 >+#define GC_BASE__INST7_SEG4 0 >+#define GC_BASE__INST7_SEG5 0 >+ >+#define HDP_BASE__INST0_SEG0 0x00000F20 >+#define HDP_BASE__INST0_SEG1 0x00012520 >+#define HDP_BASE__INST0_SEG2 0x0040A400 >+#define HDP_BASE__INST0_SEG3 0 >+#define HDP_BASE__INST0_SEG4 0 >+#define HDP_BASE__INST0_SEG5 0 >+ >+#define HDP_BASE__INST1_SEG0 0 >+#define HDP_BASE__INST1_SEG1 0 >+#define HDP_BASE__INST1_SEG2 0 >+#define HDP_BASE__INST1_SEG3 0 >+#define HDP_BASE__INST1_SEG4 0 >+#define HDP_BASE__INST1_SEG5 0 >+ >+#define HDP_BASE__INST2_SEG0 0 >+#define HDP_BASE__INST2_SEG1 0 >+#define HDP_BASE__INST2_SEG2 0 >+#define HDP_BASE__INST2_SEG3 0 >+#define HDP_BASE__INST2_SEG4 0 >+#define HDP_BASE__INST2_SEG5 0 >+ >+#define HDP_BASE__INST3_SEG0 0 >+#define HDP_BASE__INST3_SEG1 0 >+#define HDP_BASE__INST3_SEG2 0 >+#define HDP_BASE__INST3_SEG3 0 >+#define HDP_BASE__INST3_SEG4 0 >+#define HDP_BASE__INST3_SEG5 0 >+ >+#define HDP_BASE__INST4_SEG0 0 >+#define HDP_BASE__INST4_SEG1 0 >+#define HDP_BASE__INST4_SEG2 0 >+#define HDP_BASE__INST4_SEG3 0 >+#define HDP_BASE__INST4_SEG4 0 >+#define HDP_BASE__INST4_SEG5 0 >+ >+#define HDP_BASE__INST5_SEG0 0 >+#define HDP_BASE__INST5_SEG1 0 >+#define HDP_BASE__INST5_SEG2 0 >+#define HDP_BASE__INST5_SEG3 0 >+#define HDP_BASE__INST5_SEG4 0 >+#define HDP_BASE__INST5_SEG5 0 >+ >+#define HDP_BASE__INST6_SEG0 0 >+#define HDP_BASE__INST6_SEG1 0 >+#define HDP_BASE__INST6_SEG2 0 >+#define HDP_BASE__INST6_SEG3 0 >+#define HDP_BASE__INST6_SEG4 0 >+#define HDP_BASE__INST6_SEG5 0 >+ >+#define HDP_BASE__INST7_SEG0 0 >+#define HDP_BASE__INST7_SEG1 0 >+#define HDP_BASE__INST7_SEG2 0 >+#define HDP_BASE__INST7_SEG3 0 >+#define HDP_BASE__INST7_SEG4 0 >+#define HDP_BASE__INST7_SEG5 0 >+ >+#define MMHUB_BASE__INST0_SEG0 0x00012440 >+#define MMHUB_BASE__INST0_SEG1 0x0001A000 >+#define MMHUB_BASE__INST0_SEG2 0x00408800 >+#define MMHUB_BASE__INST0_SEG3 0 >+#define MMHUB_BASE__INST0_SEG4 0 >+#define MMHUB_BASE__INST0_SEG5 0 >+ >+#define MMHUB_BASE__INST1_SEG0 0 >+#define MMHUB_BASE__INST1_SEG1 0 >+#define MMHUB_BASE__INST1_SEG2 0 >+#define MMHUB_BASE__INST1_SEG3 0 >+#define MMHUB_BASE__INST1_SEG4 0 >+#define MMHUB_BASE__INST1_SEG5 0 >+ >+#define MMHUB_BASE__INST2_SEG0 0 >+#define MMHUB_BASE__INST2_SEG1 0 >+#define MMHUB_BASE__INST2_SEG2 0 >+#define MMHUB_BASE__INST2_SEG3 0 >+#define MMHUB_BASE__INST2_SEG4 0 >+#define MMHUB_BASE__INST2_SEG5 0 >+ >+#define MMHUB_BASE__INST3_SEG0 0 >+#define MMHUB_BASE__INST3_SEG1 0 >+#define MMHUB_BASE__INST3_SEG2 0 >+#define MMHUB_BASE__INST3_SEG3 0 >+#define MMHUB_BASE__INST3_SEG4 0 >+#define MMHUB_BASE__INST3_SEG5 0 >+ >+#define MMHUB_BASE__INST4_SEG0 0 >+#define MMHUB_BASE__INST4_SEG1 0 >+#define MMHUB_BASE__INST4_SEG2 0 >+#define MMHUB_BASE__INST4_SEG3 0 >+#define MMHUB_BASE__INST4_SEG4 0 >+#define MMHUB_BASE__INST4_SEG5 0 >+ >+#define MMHUB_BASE__INST5_SEG0 0 >+#define MMHUB_BASE__INST5_SEG1 0 >+#define MMHUB_BASE__INST5_SEG2 0 >+#define MMHUB_BASE__INST5_SEG3 0 >+#define MMHUB_BASE__INST5_SEG4 0 >+#define MMHUB_BASE__INST5_SEG5 0 >+ >+#define MMHUB_BASE__INST6_SEG0 0 >+#define MMHUB_BASE__INST6_SEG1 0 >+#define MMHUB_BASE__INST6_SEG2 0 >+#define MMHUB_BASE__INST6_SEG3 0 >+#define MMHUB_BASE__INST6_SEG4 0 >+#define MMHUB_BASE__INST6_SEG5 0 >+ >+#define MMHUB_BASE__INST7_SEG0 0 >+#define MMHUB_BASE__INST7_SEG1 0 >+#define MMHUB_BASE__INST7_SEG2 0 >+#define MMHUB_BASE__INST7_SEG3 0 >+#define MMHUB_BASE__INST7_SEG4 0 >+#define MMHUB_BASE__INST7_SEG5 0 >+ >+#define MP0_BASE__INST0_SEG0 0x00013FE0 >+#define MP0_BASE__INST0_SEG1 0x00016000 >+#define MP0_BASE__INST0_SEG2 0x0043FC00 >+#define MP0_BASE__INST0_SEG3 0x00DC0000 >+#define MP0_BASE__INST0_SEG4 0x00E00000 >+#define MP0_BASE__INST0_SEG5 0x00E40000 >+ >+#define MP0_BASE__INST1_SEG0 0 >+#define MP0_BASE__INST1_SEG1 0 >+#define MP0_BASE__INST1_SEG2 0 >+#define MP0_BASE__INST1_SEG3 0 >+#define MP0_BASE__INST1_SEG4 0 >+#define MP0_BASE__INST1_SEG5 0 >+ >+#define MP0_BASE__INST2_SEG0 0 >+#define MP0_BASE__INST2_SEG1 0 >+#define MP0_BASE__INST2_SEG2 0 >+#define MP0_BASE__INST2_SEG3 0 >+#define MP0_BASE__INST2_SEG4 0 >+#define MP0_BASE__INST2_SEG5 0 >+ >+#define MP0_BASE__INST3_SEG0 0 >+#define MP0_BASE__INST3_SEG1 0 >+#define MP0_BASE__INST3_SEG2 0 >+#define MP0_BASE__INST3_SEG3 0 >+#define MP0_BASE__INST3_SEG4 0 >+#define MP0_BASE__INST3_SEG5 0 >+ >+#define MP0_BASE__INST4_SEG0 0 >+#define MP0_BASE__INST4_SEG1 0 >+#define MP0_BASE__INST4_SEG2 0 >+#define MP0_BASE__INST4_SEG3 0 >+#define MP0_BASE__INST4_SEG4 0 >+#define MP0_BASE__INST4_SEG5 0 >+ >+#define MP0_BASE__INST5_SEG0 0 >+#define MP0_BASE__INST5_SEG1 0 >+#define MP0_BASE__INST5_SEG2 0 >+#define MP0_BASE__INST5_SEG3 0 >+#define MP0_BASE__INST5_SEG4 0 >+#define MP0_BASE__INST5_SEG5 0 >+ >+#define MP0_BASE__INST6_SEG0 0 >+#define MP0_BASE__INST6_SEG1 0 >+#define MP0_BASE__INST6_SEG2 0 >+#define MP0_BASE__INST6_SEG3 0 >+#define MP0_BASE__INST6_SEG4 0 >+#define MP0_BASE__INST6_SEG5 0 >+ >+#define MP0_BASE__INST7_SEG0 0 >+#define MP0_BASE__INST7_SEG1 0 >+#define MP0_BASE__INST7_SEG2 0 >+#define MP0_BASE__INST7_SEG3 0 >+#define MP0_BASE__INST7_SEG4 0 >+#define MP0_BASE__INST7_SEG5 0 >+ >+#define MP1_BASE__INST0_SEG0 0x00012020 >+#define MP1_BASE__INST0_SEG1 0x00016200 >+#define MP1_BASE__INST0_SEG2 0x00400400 >+#define MP1_BASE__INST0_SEG3 0x00E80000 >+#define MP1_BASE__INST0_SEG4 0x00EC0000 >+#define MP1_BASE__INST0_SEG5 0x00F00000 >+ >+#define MP1_BASE__INST1_SEG0 0 >+#define MP1_BASE__INST1_SEG1 0 >+#define MP1_BASE__INST1_SEG2 0 >+#define MP1_BASE__INST1_SEG3 0 >+#define MP1_BASE__INST1_SEG4 0 >+#define MP1_BASE__INST1_SEG5 0 >+ >+#define MP1_BASE__INST2_SEG0 0 >+#define MP1_BASE__INST2_SEG1 0 >+#define MP1_BASE__INST2_SEG2 0 >+#define MP1_BASE__INST2_SEG3 0 >+#define MP1_BASE__INST2_SEG4 0 >+#define MP1_BASE__INST2_SEG5 0 >+ >+#define MP1_BASE__INST3_SEG0 0 >+#define MP1_BASE__INST3_SEG1 0 >+#define MP1_BASE__INST3_SEG2 0 >+#define MP1_BASE__INST3_SEG3 0 >+#define MP1_BASE__INST3_SEG4 0 >+#define MP1_BASE__INST3_SEG5 0 >+ >+#define MP1_BASE__INST4_SEG0 0 >+#define MP1_BASE__INST4_SEG1 0 >+#define MP1_BASE__INST4_SEG2 0 >+#define MP1_BASE__INST4_SEG3 0 >+#define MP1_BASE__INST4_SEG4 0 >+#define MP1_BASE__INST4_SEG5 0 >+ >+#define MP1_BASE__INST5_SEG0 0 >+#define MP1_BASE__INST5_SEG1 0 >+#define MP1_BASE__INST5_SEG2 0 >+#define MP1_BASE__INST5_SEG3 0 >+#define MP1_BASE__INST5_SEG4 0 >+#define MP1_BASE__INST5_SEG5 0 >+ >+#define MP1_BASE__INST6_SEG0 0 >+#define MP1_BASE__INST6_SEG1 0 >+#define MP1_BASE__INST6_SEG2 0 >+#define MP1_BASE__INST6_SEG3 0 >+#define MP1_BASE__INST6_SEG4 0 >+#define MP1_BASE__INST6_SEG5 0 >+ >+#define MP1_BASE__INST7_SEG0 0 >+#define MP1_BASE__INST7_SEG1 0 >+#define MP1_BASE__INST7_SEG2 0 >+#define MP1_BASE__INST7_SEG3 0 >+#define MP1_BASE__INST7_SEG4 0 >+#define MP1_BASE__INST7_SEG5 0 >+ >+#define NBIF0_BASE__INST0_SEG0 0x00000000 >+#define NBIF0_BASE__INST0_SEG1 0x00000014 >+#define NBIF0_BASE__INST0_SEG2 0x00000D20 >+#define NBIF0_BASE__INST0_SEG3 0x00010400 >+#define NBIF0_BASE__INST0_SEG4 0x00012D80 >+#define NBIF0_BASE__INST0_SEG5 0x0041B000 >+ >+#define NBIF0_BASE__INST1_SEG0 0 >+#define NBIF0_BASE__INST1_SEG1 0 >+#define NBIF0_BASE__INST1_SEG2 0 >+#define NBIF0_BASE__INST1_SEG3 0 >+#define NBIF0_BASE__INST1_SEG4 0 >+#define NBIF0_BASE__INST1_SEG5 0 >+ >+#define NBIF0_BASE__INST2_SEG0 0 >+#define NBIF0_BASE__INST2_SEG1 0 >+#define NBIF0_BASE__INST2_SEG2 0 >+#define NBIF0_BASE__INST2_SEG3 0 >+#define NBIF0_BASE__INST2_SEG4 0 >+#define NBIF0_BASE__INST2_SEG5 0 >+ >+#define NBIF0_BASE__INST3_SEG0 0 >+#define NBIF0_BASE__INST3_SEG1 0 >+#define NBIF0_BASE__INST3_SEG2 0 >+#define NBIF0_BASE__INST3_SEG3 0 >+#define NBIF0_BASE__INST3_SEG4 0 >+#define NBIF0_BASE__INST3_SEG5 0 >+ >+#define NBIF0_BASE__INST4_SEG0 0 >+#define NBIF0_BASE__INST4_SEG1 0 >+#define NBIF0_BASE__INST4_SEG2 0 >+#define NBIF0_BASE__INST4_SEG3 0 >+#define NBIF0_BASE__INST4_SEG4 0 >+#define NBIF0_BASE__INST4_SEG5 0 >+ >+#define NBIF0_BASE__INST5_SEG0 0 >+#define NBIF0_BASE__INST5_SEG1 0 >+#define NBIF0_BASE__INST5_SEG2 0 >+#define NBIF0_BASE__INST5_SEG3 0 >+#define NBIF0_BASE__INST5_SEG4 0 >+#define NBIF0_BASE__INST5_SEG5 0 >+ >+#define NBIF0_BASE__INST6_SEG0 0 >+#define NBIF0_BASE__INST6_SEG1 0 >+#define NBIF0_BASE__INST6_SEG2 0 >+#define NBIF0_BASE__INST6_SEG3 0 >+#define NBIF0_BASE__INST6_SEG4 0 >+#define NBIF0_BASE__INST6_SEG5 0 >+ >+#define NBIF0_BASE__INST7_SEG0 0 >+#define NBIF0_BASE__INST7_SEG1 0 >+#define NBIF0_BASE__INST7_SEG2 0 >+#define NBIF0_BASE__INST7_SEG3 0 >+#define NBIF0_BASE__INST7_SEG4 0 >+#define NBIF0_BASE__INST7_SEG5 0 >+ >+#define OSSSYS_BASE__INST0_SEG0 0x000010A0 >+#define OSSSYS_BASE__INST0_SEG1 0x00012500 >+#define OSSSYS_BASE__INST0_SEG2 0x0040A000 >+#define OSSSYS_BASE__INST0_SEG3 0 >+#define OSSSYS_BASE__INST0_SEG4 0 >+#define OSSSYS_BASE__INST0_SEG5 0 >+ >+#define OSSSYS_BASE__INST1_SEG0 0 >+#define OSSSYS_BASE__INST1_SEG1 0 >+#define OSSSYS_BASE__INST1_SEG2 0 >+#define OSSSYS_BASE__INST1_SEG3 0 >+#define OSSSYS_BASE__INST1_SEG4 0 >+#define OSSSYS_BASE__INST1_SEG5 0 >+ >+#define OSSSYS_BASE__INST2_SEG0 0 >+#define OSSSYS_BASE__INST2_SEG1 0 >+#define OSSSYS_BASE__INST2_SEG2 0 >+#define OSSSYS_BASE__INST2_SEG3 0 >+#define OSSSYS_BASE__INST2_SEG4 0 >+#define OSSSYS_BASE__INST2_SEG5 0 >+ >+#define OSSSYS_BASE__INST3_SEG0 0 >+#define OSSSYS_BASE__INST3_SEG1 0 >+#define OSSSYS_BASE__INST3_SEG2 0 >+#define OSSSYS_BASE__INST3_SEG3 0 >+#define OSSSYS_BASE__INST3_SEG4 0 >+#define OSSSYS_BASE__INST3_SEG5 0 >+ >+#define OSSSYS_BASE__INST4_SEG0 0 >+#define OSSSYS_BASE__INST4_SEG1 0 >+#define OSSSYS_BASE__INST4_SEG2 0 >+#define OSSSYS_BASE__INST4_SEG3 0 >+#define OSSSYS_BASE__INST4_SEG4 0 >+#define OSSSYS_BASE__INST4_SEG5 0 >+ >+#define OSSSYS_BASE__INST5_SEG0 0 >+#define OSSSYS_BASE__INST5_SEG1 0 >+#define OSSSYS_BASE__INST5_SEG2 0 >+#define OSSSYS_BASE__INST5_SEG3 0 >+#define OSSSYS_BASE__INST5_SEG4 0 >+#define OSSSYS_BASE__INST5_SEG5 0 >+ >+#define OSSSYS_BASE__INST6_SEG0 0 >+#define OSSSYS_BASE__INST6_SEG1 0 >+#define OSSSYS_BASE__INST6_SEG2 0 >+#define OSSSYS_BASE__INST6_SEG3 0 >+#define OSSSYS_BASE__INST6_SEG4 0 >+#define OSSSYS_BASE__INST6_SEG5 0 >+ >+#define OSSSYS_BASE__INST7_SEG0 0 >+#define OSSSYS_BASE__INST7_SEG1 0 >+#define OSSSYS_BASE__INST7_SEG2 0 >+#define OSSSYS_BASE__INST7_SEG3 0 >+#define OSSSYS_BASE__INST7_SEG4 0 >+#define OSSSYS_BASE__INST7_SEG5 0 >+ >+#define PCIE0_BASE__INST0_SEG0 0x000128C0 >+#define PCIE0_BASE__INST0_SEG1 0x00411800 >+#define PCIE0_BASE__INST0_SEG2 0x04440000 >+#define PCIE0_BASE__INST0_SEG3 0 >+#define PCIE0_BASE__INST0_SEG4 0 >+#define PCIE0_BASE__INST0_SEG5 0 >+ >+#define PCIE0_BASE__INST1_SEG0 0 >+#define PCIE0_BASE__INST1_SEG1 0 >+#define PCIE0_BASE__INST1_SEG2 0 >+#define PCIE0_BASE__INST1_SEG3 0 >+#define PCIE0_BASE__INST1_SEG4 0 >+#define PCIE0_BASE__INST1_SEG5 0 >+ >+#define PCIE0_BASE__INST2_SEG0 0 >+#define PCIE0_BASE__INST2_SEG1 0 >+#define PCIE0_BASE__INST2_SEG2 0 >+#define PCIE0_BASE__INST2_SEG3 0 >+#define PCIE0_BASE__INST2_SEG4 0 >+#define PCIE0_BASE__INST2_SEG5 0 >+ >+#define PCIE0_BASE__INST3_SEG0 0 >+#define PCIE0_BASE__INST3_SEG1 0 >+#define PCIE0_BASE__INST3_SEG2 0 >+#define PCIE0_BASE__INST3_SEG3 0 >+#define PCIE0_BASE__INST3_SEG4 0 >+#define PCIE0_BASE__INST3_SEG5 0 >+ >+#define PCIE0_BASE__INST4_SEG0 0 >+#define PCIE0_BASE__INST4_SEG1 0 >+#define PCIE0_BASE__INST4_SEG2 0 >+#define PCIE0_BASE__INST4_SEG3 0 >+#define PCIE0_BASE__INST4_SEG4 0 >+#define PCIE0_BASE__INST4_SEG5 0 >+ >+#define PCIE0_BASE__INST5_SEG0 0 >+#define PCIE0_BASE__INST5_SEG1 0 >+#define PCIE0_BASE__INST5_SEG2 0 >+#define PCIE0_BASE__INST5_SEG3 0 >+#define PCIE0_BASE__INST5_SEG4 0 >+#define PCIE0_BASE__INST5_SEG5 0 >+ >+#define PCIE0_BASE__INST6_SEG0 0 >+#define PCIE0_BASE__INST6_SEG1 0 >+#define PCIE0_BASE__INST6_SEG2 0 >+#define PCIE0_BASE__INST6_SEG3 0 >+#define PCIE0_BASE__INST6_SEG4 0 >+#define PCIE0_BASE__INST6_SEG5 0 >+ >+#define PCIE0_BASE__INST7_SEG0 0 >+#define PCIE0_BASE__INST7_SEG1 0 >+#define PCIE0_BASE__INST7_SEG2 0 >+#define PCIE0_BASE__INST7_SEG3 0 >+#define PCIE0_BASE__INST7_SEG4 0 >+#define PCIE0_BASE__INST7_SEG5 0 >+ >+#define SDMA0_BASE__INST0_SEG0 0x00001260 >+#define SDMA0_BASE__INST0_SEG1 0x00012540 >+#define SDMA0_BASE__INST0_SEG2 0x0040A800 >+#define SDMA0_BASE__INST0_SEG3 0 >+#define SDMA0_BASE__INST0_SEG4 0 >+#define SDMA0_BASE__INST0_SEG5 0 >+ >+#define SDMA0_BASE__INST1_SEG0 0 >+#define SDMA0_BASE__INST1_SEG1 0 >+#define SDMA0_BASE__INST1_SEG2 0 >+#define SDMA0_BASE__INST1_SEG3 0 >+#define SDMA0_BASE__INST1_SEG4 0 >+#define SDMA0_BASE__INST1_SEG5 0 >+ >+#define SDMA0_BASE__INST2_SEG0 0 >+#define SDMA0_BASE__INST2_SEG1 0 >+#define SDMA0_BASE__INST2_SEG2 0 >+#define SDMA0_BASE__INST2_SEG3 0 >+#define SDMA0_BASE__INST2_SEG4 0 >+#define SDMA0_BASE__INST2_SEG5 0 >+ >+#define SDMA0_BASE__INST3_SEG0 0 >+#define SDMA0_BASE__INST3_SEG1 0 >+#define SDMA0_BASE__INST3_SEG2 0 >+#define SDMA0_BASE__INST3_SEG3 0 >+#define SDMA0_BASE__INST3_SEG4 0 >+#define SDMA0_BASE__INST3_SEG5 0 >+ >+#define SDMA0_BASE__INST4_SEG0 0 >+#define SDMA0_BASE__INST4_SEG1 0 >+#define SDMA0_BASE__INST4_SEG2 0 >+#define SDMA0_BASE__INST4_SEG3 0 >+#define SDMA0_BASE__INST4_SEG4 0 >+#define SDMA0_BASE__INST4_SEG5 0 >+ >+#define SDMA0_BASE__INST5_SEG0 0 >+#define SDMA0_BASE__INST5_SEG1 0 >+#define SDMA0_BASE__INST5_SEG2 0 >+#define SDMA0_BASE__INST5_SEG3 0 >+#define SDMA0_BASE__INST5_SEG4 0 >+#define SDMA0_BASE__INST5_SEG5 0 >+ >+#define SDMA0_BASE__INST6_SEG0 0 >+#define SDMA0_BASE__INST6_SEG1 0 >+#define SDMA0_BASE__INST6_SEG2 0 >+#define SDMA0_BASE__INST6_SEG3 0 >+#define SDMA0_BASE__INST6_SEG4 0 >+#define SDMA0_BASE__INST6_SEG5 0 >+ >+#define SDMA1_BASE__INST0_SEG0 0x00001860 >+#define SDMA1_BASE__INST0_SEG1 0x00012560 >+#define SDMA1_BASE__INST0_SEG2 0x0040AC00 >+#define SDMA1_BASE__INST0_SEG3 0 >+#define SDMA1_BASE__INST0_SEG4 0 >+#define SDMA1_BASE__INST0_SEG5 0 >+ >+#define SDMA1_BASE__INST1_SEG0 0 >+#define SDMA1_BASE__INST1_SEG1 0 >+#define SDMA1_BASE__INST1_SEG2 0 >+#define SDMA1_BASE__INST1_SEG3 0 >+#define SDMA1_BASE__INST1_SEG4 0 >+#define SDMA1_BASE__INST1_SEG5 0 >+ >+#define SDMA1_BASE__INST2_SEG0 0 >+#define SDMA1_BASE__INST2_SEG1 0 >+#define SDMA1_BASE__INST2_SEG2 0 >+#define SDMA1_BASE__INST2_SEG3 0 >+#define SDMA1_BASE__INST2_SEG4 0 >+#define SDMA1_BASE__INST2_SEG5 0 >+ >+#define SDMA1_BASE__INST3_SEG0 0 >+#define SDMA1_BASE__INST3_SEG1 0 >+#define SDMA1_BASE__INST3_SEG2 0 >+#define SDMA1_BASE__INST3_SEG3 0 >+#define SDMA1_BASE__INST3_SEG4 0 >+#define SDMA1_BASE__INST3_SEG5 0 >+ >+#define SDMA1_BASE__INST4_SEG0 0 >+#define SDMA1_BASE__INST4_SEG1 0 >+#define SDMA1_BASE__INST4_SEG2 0 >+#define SDMA1_BASE__INST4_SEG3 0 >+#define SDMA1_BASE__INST4_SEG4 0 >+#define SDMA1_BASE__INST4_SEG5 0 >+ >+#define SDMA1_BASE__INST5_SEG0 0 >+#define SDMA1_BASE__INST5_SEG1 0 >+#define SDMA1_BASE__INST5_SEG2 0 >+#define SDMA1_BASE__INST5_SEG3 0 >+#define SDMA1_BASE__INST5_SEG4 0 >+#define SDMA1_BASE__INST5_SEG5 0 >+ >+ >+#define SDMA1_BASE__INST6_SEG0 0 >+#define SDMA1_BASE__INST6_SEG1 0 >+#define SDMA1_BASE__INST6_SEG2 0 >+#define SDMA1_BASE__INST6_SEG3 0 >+#define SDMA1_BASE__INST6_SEG4 0 >+#define SDMA1_BASE__INST6_SEG5 0 >+ >+ >+#define SDMA2_BASE__INST0_SEG0 0x00013760 >+#define SDMA2_BASE__INST0_SEG1 0x0001E000 >+#define SDMA2_BASE__INST0_SEG2 0x0042EC00 >+#define SDMA2_BASE__INST0_SEG3 0 >+#define SDMA2_BASE__INST0_SEG4 0 >+#define SDMA2_BASE__INST0_SEG5 0 >+ >+ >+#define SDMA2_BASE__INST1_SEG0 0 >+#define SDMA2_BASE__INST1_SEG1 0 >+#define SDMA2_BASE__INST1_SEG2 0 >+#define SDMA2_BASE__INST1_SEG3 0 >+#define SDMA2_BASE__INST1_SEG4 0 >+#define SDMA2_BASE__INST1_SEG5 0 >+ >+#define SDMA2_BASE__INST2_SEG0 0 >+#define SDMA2_BASE__INST2_SEG1 0 >+#define SDMA2_BASE__INST2_SEG2 0 >+#define SDMA2_BASE__INST2_SEG3 0 >+#define SDMA2_BASE__INST2_SEG4 0 >+#define SDMA2_BASE__INST2_SEG5 0 >+ >+#define SDMA2_BASE__INST3_SEG0 0 >+#define SDMA2_BASE__INST3_SEG1 0 >+#define SDMA2_BASE__INST3_SEG2 0 >+#define SDMA2_BASE__INST3_SEG3 0 >+#define SDMA2_BASE__INST3_SEG4 0 >+#define SDMA2_BASE__INST3_SEG5 0 >+ >+#define SDMA2_BASE__INST4_SEG0 0 >+#define SDMA2_BASE__INST4_SEG1 0 >+#define SDMA2_BASE__INST4_SEG2 0 >+#define SDMA2_BASE__INST4_SEG3 0 >+#define SDMA2_BASE__INST4_SEG4 0 >+#define SDMA2_BASE__INST4_SEG5 0 >+ >+#define SDMA2_BASE__INST5_SEG0 0 >+#define SDMA2_BASE__INST5_SEG1 0 >+#define SDMA2_BASE__INST5_SEG2 0 >+#define SDMA2_BASE__INST5_SEG3 0 >+#define SDMA2_BASE__INST5_SEG4 0 >+#define SDMA2_BASE__INST5_SEG5 0 >+ >+#define SDMA2_BASE__INST6_SEG0 0 >+#define SDMA2_BASE__INST6_SEG1 0 >+#define SDMA2_BASE__INST6_SEG2 0 >+#define SDMA2_BASE__INST6_SEG3 0 >+#define SDMA2_BASE__INST6_SEG4 0 >+#define SDMA2_BASE__INST6_SEG5 0 >+ >+#define SDMA3_BASE__INST0_SEG0 0x00013780 >+#define SDMA3_BASE__INST0_SEG1 0x0001E400 >+#define SDMA3_BASE__INST0_SEG2 0x0042F000 >+#define SDMA3_BASE__INST0_SEG3 0 >+#define SDMA3_BASE__INST0_SEG4 0 >+#define SDMA3_BASE__INST0_SEG5 0 >+ >+#define SDMA3_BASE__INST1_SEG0 0 >+#define SDMA3_BASE__INST1_SEG1 0 >+#define SDMA3_BASE__INST1_SEG2 0 >+#define SDMA3_BASE__INST1_SEG3 0 >+#define SDMA3_BASE__INST1_SEG4 0 >+#define SDMA3_BASE__INST1_SEG5 0 >+ >+#define SDMA3_BASE__INST2_SEG0 0 >+#define SDMA3_BASE__INST2_SEG1 0 >+#define SDMA3_BASE__INST2_SEG2 0 >+#define SDMA3_BASE__INST2_SEG3 0 >+#define SDMA3_BASE__INST2_SEG4 0 >+#define SDMA3_BASE__INST2_SEG5 0 >+ >+#define SDMA3_BASE__INST3_SEG0 0 >+#define SDMA3_BASE__INST3_SEG1 0 >+#define SDMA3_BASE__INST3_SEG2 0 >+#define SDMA3_BASE__INST3_SEG3 0 >+#define SDMA3_BASE__INST3_SEG4 0 >+#define SDMA3_BASE__INST3_SEG5 0 >+ >+#define SDMA3_BASE__INST4_SEG0 0 >+#define SDMA3_BASE__INST4_SEG1 0 >+#define SDMA3_BASE__INST4_SEG2 0 >+#define SDMA3_BASE__INST4_SEG3 0 >+#define SDMA3_BASE__INST4_SEG4 0 >+#define SDMA3_BASE__INST4_SEG5 0 >+ >+#define SDMA3_BASE__INST5_SEG0 0 >+#define SDMA3_BASE__INST5_SEG1 0 >+#define SDMA3_BASE__INST5_SEG2 0 >+#define SDMA3_BASE__INST5_SEG3 0 >+#define SDMA3_BASE__INST5_SEG4 0 >+#define SDMA3_BASE__INST5_SEG5 0 >+ >+#define SDMA3_BASE__INST6_SEG0 0 >+#define SDMA3_BASE__INST6_SEG1 0 >+#define SDMA3_BASE__INST6_SEG2 0 >+#define SDMA3_BASE__INST6_SEG3 0 >+#define SDMA3_BASE__INST6_SEG4 0 >+#define SDMA3_BASE__INST6_SEG5 0 >+ >+#define SDMA4_BASE__INST0_SEG0 0x000137A0 >+#define SDMA4_BASE__INST0_SEG1 0x0001E800 >+#define SDMA4_BASE__INST0_SEG2 0x0042F400 >+#define SDMA4_BASE__INST0_SEG3 0 >+#define SDMA4_BASE__INST0_SEG4 0 >+#define SDMA4_BASE__INST0_SEG5 0 >+ >+#define SDMA4_BASE__INST1_SEG0 0 >+#define SDMA4_BASE__INST1_SEG1 0 >+#define SDMA4_BASE__INST1_SEG2 0 >+#define SDMA4_BASE__INST1_SEG3 0 >+#define SDMA4_BASE__INST1_SEG4 0 >+#define SDMA4_BASE__INST1_SEG5 0 >+ >+#define SDMA4_BASE__INST2_SEG0 0 >+#define SDMA4_BASE__INST2_SEG1 0 >+#define SDMA4_BASE__INST2_SEG2 0 >+#define SDMA4_BASE__INST2_SEG3 0 >+#define SDMA4_BASE__INST2_SEG4 0 >+#define SDMA4_BASE__INST2_SEG5 0 >+ >+#define SDMA4_BASE__INST3_SEG0 0 >+#define SDMA4_BASE__INST3_SEG1 0 >+#define SDMA4_BASE__INST3_SEG2 0 >+#define SDMA4_BASE__INST3_SEG3 0 >+#define SDMA4_BASE__INST3_SEG4 0 >+#define SDMA4_BASE__INST3_SEG5 0 >+ >+#define SDMA4_BASE__INST4_SEG0 0 >+#define SDMA4_BASE__INST4_SEG1 0 >+#define SDMA4_BASE__INST4_SEG2 0 >+#define SDMA4_BASE__INST4_SEG3 0 >+#define SDMA4_BASE__INST4_SEG4 0 >+#define SDMA4_BASE__INST4_SEG5 0 >+ >+#define SDMA4_BASE__INST5_SEG0 0 >+#define SDMA4_BASE__INST5_SEG1 0 >+#define SDMA4_BASE__INST5_SEG2 0 >+#define SDMA4_BASE__INST5_SEG3 0 >+#define SDMA4_BASE__INST5_SEG4 0 >+#define SDMA4_BASE__INST5_SEG5 0 >+ >+#define SDMA4_BASE__INST6_SEG0 0 >+#define SDMA4_BASE__INST6_SEG1 0 >+#define SDMA4_BASE__INST6_SEG2 0 >+#define SDMA4_BASE__INST6_SEG3 0 >+#define SDMA4_BASE__INST6_SEG4 0 >+#define SDMA4_BASE__INST6_SEG5 0 >+ >+#define SDMA5_BASE__INST0_SEG0 0x000137C0 >+#define SDMA5_BASE__INST0_SEG1 0x0001EC00 >+#define SDMA5_BASE__INST0_SEG2 0x0042F800 >+#define SDMA5_BASE__INST0_SEG3 0 >+#define SDMA5_BASE__INST0_SEG4 0 >+#define SDMA5_BASE__INST0_SEG5 0 >+ >+#define SDMA5_BASE__INST1_SEG0 0 >+#define SDMA5_BASE__INST1_SEG1 0 >+#define SDMA5_BASE__INST1_SEG2 0 >+#define SDMA5_BASE__INST1_SEG3 0 >+#define SDMA5_BASE__INST1_SEG4 0 >+#define SDMA5_BASE__INST1_SEG5 0 >+ >+#define SDMA5_BASE__INST2_SEG0 0 >+#define SDMA5_BASE__INST2_SEG1 0 >+#define SDMA5_BASE__INST2_SEG2 0 >+#define SDMA5_BASE__INST2_SEG3 0 >+#define SDMA5_BASE__INST2_SEG4 0 >+#define SDMA5_BASE__INST2_SEG5 0 >+ >+#define SDMA5_BASE__INST3_SEG0 0 >+#define SDMA5_BASE__INST3_SEG1 0 >+#define SDMA5_BASE__INST3_SEG2 0 >+#define SDMA5_BASE__INST3_SEG3 0 >+#define SDMA5_BASE__INST3_SEG4 0 >+#define SDMA5_BASE__INST3_SEG5 0 >+ >+#define SDMA5_BASE__INST4_SEG0 0 >+#define SDMA5_BASE__INST4_SEG1 0 >+#define SDMA5_BASE__INST4_SEG2 0 >+#define SDMA5_BASE__INST4_SEG3 0 >+#define SDMA5_BASE__INST4_SEG4 0 >+#define SDMA5_BASE__INST4_SEG5 0 >+ >+#define SDMA5_BASE__INST5_SEG0 0 >+#define SDMA5_BASE__INST5_SEG1 0 >+#define SDMA5_BASE__INST5_SEG2 0 >+#define SDMA5_BASE__INST5_SEG3 0 >+#define SDMA5_BASE__INST5_SEG4 0 >+#define SDMA5_BASE__INST5_SEG5 0 >+ >+#define SDMA5_BASE__INST6_SEG0 0 >+#define SDMA5_BASE__INST6_SEG1 0 >+#define SDMA5_BASE__INST6_SEG2 0 >+#define SDMA5_BASE__INST6_SEG3 0 >+#define SDMA5_BASE__INST6_SEG4 0 >+#define SDMA5_BASE__INST6_SEG5 0 >+ >+#define SDMA6_BASE__INST0_SEG0 0x000137E0 >+#define SDMA6_BASE__INST0_SEG1 0x0001F000 >+#define SDMA6_BASE__INST0_SEG2 0x0042FC00 >+#define SDMA6_BASE__INST0_SEG3 0 >+#define SDMA6_BASE__INST0_SEG4 0 >+#define SDMA6_BASE__INST0_SEG5 0 >+ >+#define SDMA6_BASE__INST1_SEG0 0 >+#define SDMA6_BASE__INST1_SEG1 0 >+#define SDMA6_BASE__INST1_SEG2 0 >+#define SDMA6_BASE__INST1_SEG3 0 >+#define SDMA6_BASE__INST1_SEG4 0 >+#define SDMA6_BASE__INST1_SEG5 0 >+ >+#define SDMA6_BASE__INST2_SEG0 0 >+#define SDMA6_BASE__INST2_SEG1 0 >+#define SDMA6_BASE__INST2_SEG2 0 >+#define SDMA6_BASE__INST2_SEG3 0 >+#define SDMA6_BASE__INST2_SEG4 0 >+#define SDMA6_BASE__INST2_SEG5 0 >+ >+#define SDMA6_BASE__INST3_SEG0 0 >+#define SDMA6_BASE__INST3_SEG1 0 >+#define SDMA6_BASE__INST3_SEG2 0 >+#define SDMA6_BASE__INST3_SEG3 0 >+#define SDMA6_BASE__INST3_SEG4 0 >+#define SDMA6_BASE__INST3_SEG5 0 >+ >+#define SDMA6_BASE__INST4_SEG0 0 >+#define SDMA6_BASE__INST4_SEG1 0 >+#define SDMA6_BASE__INST4_SEG2 0 >+#define SDMA6_BASE__INST4_SEG3 0 >+#define SDMA6_BASE__INST4_SEG4 0 >+#define SDMA6_BASE__INST4_SEG5 0 >+ >+#define SDMA6_BASE__INST5_SEG0 0 >+#define SDMA6_BASE__INST5_SEG1 0 >+#define SDMA6_BASE__INST5_SEG2 0 >+#define SDMA6_BASE__INST5_SEG3 0 >+#define SDMA6_BASE__INST5_SEG4 0 >+#define SDMA6_BASE__INST5_SEG5 0 >+ >+#define SDMA6_BASE__INST6_SEG0 0 >+#define SDMA6_BASE__INST6_SEG1 0 >+#define SDMA6_BASE__INST6_SEG2 0 >+#define SDMA6_BASE__INST6_SEG3 0 >+#define SDMA6_BASE__INST6_SEG4 0 >+#define SDMA6_BASE__INST6_SEG5 0 >+ >+#define SDMA7_BASE__INST0_SEG0 0x00013800 >+#define SDMA7_BASE__INST0_SEG1 0x0001F400 >+#define SDMA7_BASE__INST0_SEG2 0x00430000 >+#define SDMA7_BASE__INST0_SEG3 0 >+#define SDMA7_BASE__INST0_SEG4 0 >+#define SDMA7_BASE__INST0_SEG5 0 >+ >+#define SDMA7_BASE__INST1_SEG0 0 >+#define SDMA7_BASE__INST1_SEG1 0 >+#define SDMA7_BASE__INST1_SEG2 0 >+#define SDMA7_BASE__INST1_SEG3 0 >+#define SDMA7_BASE__INST1_SEG4 0 >+#define SDMA7_BASE__INST1_SEG5 0 >+ >+#define SDMA7_BASE__INST2_SEG0 0 >+#define SDMA7_BASE__INST2_SEG1 0 >+#define SDMA7_BASE__INST2_SEG2 0 >+#define SDMA7_BASE__INST2_SEG3 0 >+#define SDMA7_BASE__INST2_SEG4 0 >+#define SDMA7_BASE__INST2_SEG5 0 >+ >+#define SDMA7_BASE__INST3_SEG0 0 >+#define SDMA7_BASE__INST3_SEG1 0 >+#define SDMA7_BASE__INST3_SEG2 0 >+#define SDMA7_BASE__INST3_SEG3 0 >+#define SDMA7_BASE__INST3_SEG4 0 >+#define SDMA7_BASE__INST3_SEG5 0 >+ >+#define SDMA7_BASE__INST4_SEG0 0 >+#define SDMA7_BASE__INST4_SEG1 0 >+#define SDMA7_BASE__INST4_SEG2 0 >+#define SDMA7_BASE__INST4_SEG3 0 >+#define SDMA7_BASE__INST4_SEG4 0 >+#define SDMA7_BASE__INST4_SEG5 0 >+ >+#define SDMA7_BASE__INST5_SEG0 0 >+#define SDMA7_BASE__INST5_SEG1 0 >+#define SDMA7_BASE__INST5_SEG2 0 >+#define SDMA7_BASE__INST5_SEG3 0 >+#define SDMA7_BASE__INST5_SEG4 0 >+#define SDMA7_BASE__INST5_SEG5 0 >+ >+#define SDMA7_BASE__INST6_SEG0 0 >+#define SDMA7_BASE__INST6_SEG1 0 >+#define SDMA7_BASE__INST6_SEG2 0 >+#define SDMA7_BASE__INST6_SEG3 0 >+#define SDMA7_BASE__INST6_SEG4 0 >+#define SDMA7_BASE__INST6_SEG5 0 >+ >+#define SMUIO_BASE__INST0_SEG0 0x00012080 >+#define SMUIO_BASE__INST0_SEG1 0x00016800 >+#define SMUIO_BASE__INST0_SEG2 0x00016A00 >+#define SMUIO_BASE__INST0_SEG3 0x00401000 >+#define SMUIO_BASE__INST0_SEG4 0x00440000 >+#define SMUIO_BASE__INST0_SEG5 0 >+ >+#define SMUIO_BASE__INST1_SEG0 0 >+#define SMUIO_BASE__INST1_SEG1 0 >+#define SMUIO_BASE__INST1_SEG2 0 >+#define SMUIO_BASE__INST1_SEG3 0 >+#define SMUIO_BASE__INST1_SEG4 0 >+#define SMUIO_BASE__INST1_SEG5 0 >+ >+#define SMUIO_BASE__INST2_SEG0 0 >+#define SMUIO_BASE__INST2_SEG1 0 >+#define SMUIO_BASE__INST2_SEG2 0 >+#define SMUIO_BASE__INST2_SEG3 0 >+#define SMUIO_BASE__INST2_SEG4 0 >+#define SMUIO_BASE__INST2_SEG5 0 >+ >+#define SMUIO_BASE__INST3_SEG0 0 >+#define SMUIO_BASE__INST3_SEG1 0 >+#define SMUIO_BASE__INST3_SEG2 0 >+#define SMUIO_BASE__INST3_SEG3 0 >+#define SMUIO_BASE__INST3_SEG4 0 >+#define SMUIO_BASE__INST3_SEG5 0 >+ >+#define SMUIO_BASE__INST4_SEG0 0 >+#define SMUIO_BASE__INST4_SEG1 0 >+#define SMUIO_BASE__INST4_SEG2 0 >+#define SMUIO_BASE__INST4_SEG3 0 >+#define SMUIO_BASE__INST4_SEG4 0 >+#define SMUIO_BASE__INST4_SEG5 0 >+ >+#define SMUIO_BASE__INST5_SEG0 0 >+#define SMUIO_BASE__INST5_SEG1 0 >+#define SMUIO_BASE__INST5_SEG2 0 >+#define SMUIO_BASE__INST5_SEG3 0 >+#define SMUIO_BASE__INST5_SEG4 0 >+#define SMUIO_BASE__INST5_SEG5 0 >+ >+#define SMUIO_BASE__INST6_SEG0 0 >+#define SMUIO_BASE__INST6_SEG1 0 >+#define SMUIO_BASE__INST6_SEG2 0 >+#define SMUIO_BASE__INST6_SEG3 0 >+#define SMUIO_BASE__INST6_SEG4 0 >+#define SMUIO_BASE__INST6_SEG5 0 >+ >+#define SMUIO_BASE__INST7_SEG0 0 >+#define SMUIO_BASE__INST7_SEG1 0 >+#define SMUIO_BASE__INST7_SEG2 0 >+#define SMUIO_BASE__INST7_SEG3 0 >+#define SMUIO_BASE__INST7_SEG4 0 >+#define SMUIO_BASE__INST7_SEG5 0 >+ >+#define THM_BASE__INST0_SEG0 0x00012060 >+#define THM_BASE__INST0_SEG1 0x00016600 >+#define THM_BASE__INST0_SEG2 0x00400C00 >+#define THM_BASE__INST0_SEG3 0 >+#define THM_BASE__INST0_SEG4 0 >+#define THM_BASE__INST0_SEG5 0 >+ >+#define THM_BASE__INST1_SEG0 0 >+#define THM_BASE__INST1_SEG1 0 >+#define THM_BASE__INST1_SEG2 0 >+#define THM_BASE__INST1_SEG3 0 >+#define THM_BASE__INST1_SEG4 0 >+#define THM_BASE__INST1_SEG5 0 >+ >+#define THM_BASE__INST2_SEG0 0 >+#define THM_BASE__INST2_SEG1 0 >+#define THM_BASE__INST2_SEG2 0 >+#define THM_BASE__INST2_SEG3 0 >+#define THM_BASE__INST2_SEG4 0 >+#define THM_BASE__INST2_SEG5 0 >+ >+#define THM_BASE__INST3_SEG0 0 >+#define THM_BASE__INST3_SEG1 0 >+#define THM_BASE__INST3_SEG2 0 >+#define THM_BASE__INST3_SEG3 0 >+#define THM_BASE__INST3_SEG4 0 >+#define THM_BASE__INST3_SEG5 0 >+ >+#define THM_BASE__INST4_SEG0 0 >+#define THM_BASE__INST4_SEG1 0 >+#define THM_BASE__INST4_SEG2 0 >+#define THM_BASE__INST4_SEG3 0 >+#define THM_BASE__INST4_SEG4 0 >+#define THM_BASE__INST4_SEG5 0 >+ >+#define THM_BASE__INST5_SEG0 0 >+#define THM_BASE__INST5_SEG1 0 >+#define THM_BASE__INST5_SEG2 0 >+#define THM_BASE__INST5_SEG3 0 >+#define THM_BASE__INST5_SEG4 0 >+#define THM_BASE__INST5_SEG5 0 >+ >+#define THM_BASE__INST6_SEG0 0 >+#define THM_BASE__INST6_SEG1 0 >+#define THM_BASE__INST6_SEG2 0 >+#define THM_BASE__INST6_SEG3 0 >+#define THM_BASE__INST6_SEG4 0 >+#define THM_BASE__INST6_SEG5 0 >+ >+#define THM_BASE__INST7_SEG0 0 >+#define THM_BASE__INST7_SEG1 0 >+#define THM_BASE__INST7_SEG2 0 >+#define THM_BASE__INST7_SEG3 0 >+#define THM_BASE__INST7_SEG4 0 >+#define THM_BASE__INST7_SEG5 0 >+ >+#define UMC_BASE__INST0_SEG0 0x000132C0 >+#define UMC_BASE__INST0_SEG1 0x00014000 >+#define UMC_BASE__INST0_SEG2 0x00425800 >+#define UMC_BASE__INST0_SEG3 0 >+#define UMC_BASE__INST0_SEG4 0 >+#define UMC_BASE__INST0_SEG5 0 >+ >+#define UMC_BASE__INST1_SEG0 0x000132E0 >+#define UMC_BASE__INST1_SEG1 0x00054000 >+#define UMC_BASE__INST1_SEG2 0x00425C00 >+#define UMC_BASE__INST1_SEG3 0 >+#define UMC_BASE__INST1_SEG4 0 >+#define UMC_BASE__INST1_SEG5 0 >+ >+#define UMC_BASE__INST2_SEG0 0x00013300 >+#define UMC_BASE__INST2_SEG1 0x00094000 >+#define UMC_BASE__INST2_SEG2 0x00426000 >+#define UMC_BASE__INST2_SEG3 0 >+#define UMC_BASE__INST2_SEG4 0 >+#define UMC_BASE__INST2_SEG5 0 >+ >+#define UMC_BASE__INST3_SEG0 0x00013320 >+#define UMC_BASE__INST3_SEG1 0x000D4000 >+#define UMC_BASE__INST3_SEG2 0x00426400 >+#define UMC_BASE__INST3_SEG3 0 >+#define UMC_BASE__INST3_SEG4 0 >+#define UMC_BASE__INST3_SEG5 0 >+ >+#define UMC_BASE__INST4_SEG0 0x00013340 >+#define UMC_BASE__INST4_SEG1 0x00114000 >+#define UMC_BASE__INST4_SEG2 0x00426800 >+#define UMC_BASE__INST4_SEG3 0 >+#define UMC_BASE__INST4_SEG4 0 >+#define UMC_BASE__INST4_SEG5 0 >+ >+#define UMC_BASE__INST5_SEG0 0x00013360 >+#define UMC_BASE__INST5_SEG1 0x00154000 >+#define UMC_BASE__INST5_SEG2 0x00426C00 >+#define UMC_BASE__INST5_SEG3 0 >+#define UMC_BASE__INST5_SEG4 0 >+#define UMC_BASE__INST5_SEG5 0 >+ >+#define UMC_BASE__INST6_SEG0 0x00013380 >+#define UMC_BASE__INST6_SEG1 0x00194000 >+#define UMC_BASE__INST6_SEG2 0x00427000 >+#define UMC_BASE__INST6_SEG3 0 >+#define UMC_BASE__INST6_SEG4 0 >+#define UMC_BASE__INST6_SEG5 0 >+ >+#define UMC_BASE__INST7_SEG0 0x000133A0 >+#define UMC_BASE__INST7_SEG1 0x001D4000 >+#define UMC_BASE__INST7_SEG2 0x00427400 >+#define UMC_BASE__INST7_SEG3 0 >+#define UMC_BASE__INST7_SEG4 0 >+#define UMC_BASE__INST7_SEG5 0 >+ >+#define UVD_BASE__INST0_SEG0 0x00007800 >+#define UVD_BASE__INST0_SEG1 0x00007E00 >+#define UVD_BASE__INST0_SEG2 0x00012180 >+#define UVD_BASE__INST0_SEG3 0x00403000 >+#define UVD_BASE__INST0_SEG4 0 >+#define UVD_BASE__INST0_SEG5 0 >+ >+#define UVD_BASE__INST1_SEG0 0x00007A00 >+#define UVD_BASE__INST1_SEG1 0x00009000 >+#define UVD_BASE__INST1_SEG2 0x000136E0 >+#define UVD_BASE__INST1_SEG3 0x0042DC00 >+#define UVD_BASE__INST1_SEG4 0 >+#define UVD_BASE__INST1_SEG5 0 >+ >+#define UVD_BASE__INST2_SEG0 0 >+#define UVD_BASE__INST2_SEG1 0 >+#define UVD_BASE__INST2_SEG2 0 >+#define UVD_BASE__INST2_SEG3 0 >+#define UVD_BASE__INST2_SEG4 0 >+#define UVD_BASE__INST2_SEG5 0 >+ >+#define UVD_BASE__INST3_SEG0 0 >+#define UVD_BASE__INST3_SEG1 0 >+#define UVD_BASE__INST3_SEG2 0 >+#define UVD_BASE__INST3_SEG3 0 >+#define UVD_BASE__INST3_SEG4 0 >+#define UVD_BASE__INST3_SEG5 0 >+ >+#define UVD_BASE__INST4_SEG0 0 >+#define UVD_BASE__INST4_SEG1 0 >+#define UVD_BASE__INST4_SEG2 0 >+#define UVD_BASE__INST4_SEG3 0 >+#define UVD_BASE__INST4_SEG4 0 >+#define UVD_BASE__INST4_SEG5 0 >+ >+#define UVD_BASE__INST5_SEG0 0 >+#define UVD_BASE__INST5_SEG1 0 >+#define UVD_BASE__INST5_SEG2 0 >+#define UVD_BASE__INST5_SEG3 0 >+#define UVD_BASE__INST5_SEG4 0 >+#define UVD_BASE__INST5_SEG5 0 >+ >+#define UVD_BASE__INST6_SEG0 0 >+#define UVD_BASE__INST6_SEG1 0 >+#define UVD_BASE__INST6_SEG2 0 >+#define UVD_BASE__INST6_SEG3 0 >+#define UVD_BASE__INST6_SEG4 0 >+#define UVD_BASE__INST6_SEG5 0 >+ >+#define UVD_BASE__INST7_SEG0 0 >+#define UVD_BASE__INST7_SEG1 0 >+#define UVD_BASE__INST7_SEG2 0 >+#define UVD_BASE__INST7_SEG3 0 >+#define UVD_BASE__INST7_SEG4 0 >+#define UVD_BASE__INST7_SEG5 0 >+ >+#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 >+#define DBGU_IO_BASE__INST0_SEG1 0x000125A0 >+#define DBGU_IO_BASE__INST0_SEG2 0x0040B400 >+#define DBGU_IO_BASE__INST0_SEG3 0 >+#define DBGU_IO_BASE__INST0_SEG4 0 >+#define DBGU_IO_BASE__INST0_SEG5 0 >+ >+#define DBGU_IO_BASE__INST1_SEG0 0 >+#define DBGU_IO_BASE__INST1_SEG1 0 >+#define DBGU_IO_BASE__INST1_SEG2 0 >+#define DBGU_IO_BASE__INST1_SEG3 0 >+#define DBGU_IO_BASE__INST1_SEG4 0 >+#define DBGU_IO_BASE__INST1_SEG5 0 >+ >+#define DBGU_IO_BASE__INST2_SEG0 0 >+#define DBGU_IO_BASE__INST2_SEG1 0 >+#define DBGU_IO_BASE__INST2_SEG2 0 >+#define DBGU_IO_BASE__INST2_SEG3 0 >+#define DBGU_IO_BASE__INST2_SEG4 0 >+#define DBGU_IO_BASE__INST2_SEG5 0 >+ >+#define DBGU_IO_BASE__INST3_SEG0 0 >+#define DBGU_IO_BASE__INST3_SEG1 0 >+#define DBGU_IO_BASE__INST3_SEG2 0 >+#define DBGU_IO_BASE__INST3_SEG3 0 >+#define DBGU_IO_BASE__INST3_SEG4 0 >+#define DBGU_IO_BASE__INST3_SEG5 0 >+ >+#define DBGU_IO_BASE__INST4_SEG0 0 >+#define DBGU_IO_BASE__INST4_SEG1 0 >+#define DBGU_IO_BASE__INST4_SEG2 0 >+#define DBGU_IO_BASE__INST4_SEG3 0 >+#define DBGU_IO_BASE__INST4_SEG4 0 >+#define DBGU_IO_BASE__INST4_SEG5 0 >+ >+#define DBGU_IO_BASE__INST5_SEG0 0 >+#define DBGU_IO_BASE__INST5_SEG1 0 >+#define DBGU_IO_BASE__INST5_SEG2 0 >+#define DBGU_IO_BASE__INST5_SEG3 0 >+#define DBGU_IO_BASE__INST5_SEG4 0 >+#define DBGU_IO_BASE__INST5_SEG5 0 >+ >+#define DBGU_IO_BASE__INST6_SEG0 0 >+#define DBGU_IO_BASE__INST6_SEG1 0 >+#define DBGU_IO_BASE__INST6_SEG2 0 >+#define DBGU_IO_BASE__INST6_SEG3 0 >+#define DBGU_IO_BASE__INST6_SEG4 0 >+#define DBGU_IO_BASE__INST6_SEG5 0 >+ >+#define DBGU_IO_BASE__INST7_SEG0 0 >+#define DBGU_IO_BASE__INST7_SEG1 0 >+#define DBGU_IO_BASE__INST7_SEG2 0 >+#define DBGU_IO_BASE__INST7_SEG3 0 >+#define DBGU_IO_BASE__INST7_SEG4 0 >+#define DBGU_IO_BASE__INST7_SEG5 0 >+ >+#define RSMU_BASE__INST0_SEG0 0x00012000 >+#define RSMU_BASE__INST0_SEG1 0 >+#define RSMU_BASE__INST0_SEG2 0 >+#define RSMU_BASE__INST0_SEG3 0 >+#define RSMU_BASE__INST0_SEG4 0 >+#define RSMU_BASE__INST0_SEG5 0 >+ >+#define RSMU_BASE__INST1_SEG0 0 >+#define RSMU_BASE__INST1_SEG1 0 >+#define RSMU_BASE__INST1_SEG2 0 >+#define RSMU_BASE__INST1_SEG3 0 >+#define RSMU_BASE__INST1_SEG4 0 >+#define RSMU_BASE__INST1_SEG5 0 >+ >+#define RSMU_BASE__INST2_SEG0 0 >+#define RSMU_BASE__INST2_SEG1 0 >+#define RSMU_BASE__INST2_SEG2 0 >+#define RSMU_BASE__INST2_SEG3 0 >+#define RSMU_BASE__INST2_SEG4 0 >+#define RSMU_BASE__INST2_SEG5 0 >+ >+#define RSMU_BASE__INST3_SEG0 0 >+#define RSMU_BASE__INST3_SEG1 0 >+#define RSMU_BASE__INST3_SEG2 0 >+#define RSMU_BASE__INST3_SEG3 0 >+#define RSMU_BASE__INST3_SEG4 0 >+#define RSMU_BASE__INST3_SEG5 0 >+ >+#define RSMU_BASE__INST4_SEG0 0 >+#define RSMU_BASE__INST4_SEG1 0 >+#define RSMU_BASE__INST4_SEG2 0 >+#define RSMU_BASE__INST4_SEG3 0 >+#define RSMU_BASE__INST4_SEG4 0 >+#define RSMU_BASE__INST4_SEG5 0 >+ >+#define RSMU_BASE__INST5_SEG0 0 >+#define RSMU_BASE__INST5_SEG1 0 >+#define RSMU_BASE__INST5_SEG2 0 >+#define RSMU_BASE__INST5_SEG3 0 >+#define RSMU_BASE__INST5_SEG4 0 >+#define RSMU_BASE__INST5_SEG5 0 >+ >+#define RSMU_BASE__INST6_SEG0 0 >+#define RSMU_BASE__INST6_SEG1 0 >+#define RSMU_BASE__INST6_SEG2 0 >+#define RSMU_BASE__INST6_SEG3 0 >+#define RSMU_BASE__INST6_SEG4 0 >+#define RSMU_BASE__INST6_SEG5 0 >+ >+#define RSMU_BASE__INST7_SEG0 0 >+#define RSMU_BASE__INST7_SEG1 0 >+#define RSMU_BASE__INST7_SEG2 0 >+#define RSMU_BASE__INST7_SEG3 0 >+#define RSMU_BASE__INST7_SEG4 0 >+#define RSMU_BASE__INST7_SEG5 0 >+ >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h 2019-08-31 15:01:11.873736170 -0500 >@@ -0,0 +1,56 @@ >+/* >+ * Copyright (C) 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included >+ * in all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN >+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN >+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. >+ */ >+#ifndef _clk_10_0_2_OFFSET_HEADER >+#define _clk_10_0_2_OFFSET_HEADER >+ >+ >+ >+// addressBlock: clk_clk1_0_SmuClkDec >+// base address: 0x5b800 >+#define mmCLK1_CLK_PLL_REQ 0x000f >+#define mmCLK1_CLK_PLL_REQ_BASE_IDX 1 >+#define mmCLK1_CLK0_BYPASS_CNTL 0x0049 >+#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX 1 >+#define mmCLK1_CLK1_BYPASS_CNTL 0x0053 >+#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX 1 >+#define mmCLK1_CLK2_BYPASS_CNTL 0x005d >+#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX 1 >+#define mmCLK1_CLK2_STATUS 0x005e >+#define mmCLK1_CLK2_STATUS_BASE_IDX 1 >+#define mmCLK1_CLK3_DFS_CNTL 0x005f >+#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX 1 >+#define mmCLK1_CLK3_DS_CNTL 0x0060 >+#define mmCLK1_CLK3_DS_CNTL_BASE_IDX 1 >+#define mmCLK1_CLK3_ALLOW_DS 0x0061 >+#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX 1 >+#define mmCLK1_CLK3_BYPASS_CNTL 0x0067 >+#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX 1 >+#define mmCLK1_CLK0_CURRENT_CNT 0x008a >+#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX 1 >+#define mmCLK1_CLK1_CURRENT_CNT 0x008b >+#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX 1 >+#define mmCLK1_CLK2_CURRENT_CNT 0x008c >+#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX 1 >+#define mmCLK1_CLK3_CURRENT_CNT 0x008d >+#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX 1 >+ >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h 2019-08-31 15:01:11.873736170 -0500 >@@ -0,0 +1,73 @@ >+/* >+ * Copyright (C) 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included >+ * in all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN >+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN >+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. >+ */ >+#ifndef _clk_10_0_2_SH_MASK_HEADER >+#define _clk_10_0_2_SH_MASK_HEADER >+ >+ >+// addressBlock: clk_clk1_0_SmuClkDec >+//CLK1_CLK_PLL_REQ >+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 >+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc >+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 >+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL >+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L >+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L >+//CLK1_CLK0_BYPASS_CNTL >+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0 >+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10 >+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L >+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK 0x000F0000L >+//CLK1_CLK1_BYPASS_CNTL >+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0 >+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10 >+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L >+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK 0x000F0000L >+//CLK1_CLK2_BYPASS_CNTL >+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 >+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 >+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L >+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L >+//CLK1_CLK3_DS_CNTL >+#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0 >+#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x00000007L >+//CLK1_CLK3_ALLOW_DS >+#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT 0x0 >+#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK 0x00000001L >+//CLK1_CLK3_BYPASS_CNTL >+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0 >+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10 >+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L >+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK 0x000F0000L >+//CLK1_CLK0_CURRENT_CNT >+#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 >+#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL >+//CLK1_CLK1_CURRENT_CNT >+#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 >+#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL >+//CLK1_CLK2_CURRENT_CNT >+#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 >+#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL >+//CLK1_CLK3_CURRENT_CNT >+#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 >+#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL >+ >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h 2019-08-31 15:01:11.876736170 -0500 >@@ -0,0 +1,13862 @@ >+/* >+ * Copyright (C) 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included >+ * in all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN >+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN >+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. >+ */ >+#ifndef _dcn_2_1_0_OFFSET_HEADER >+#define _dcn_2_1_0_OFFSET_HEADER >+ >+ >+ >+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] >+// base address: 0x48 >+#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 >+#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 >+#define mmVGA_MEM_READ_PAGE_ADDR 0x0001 >+#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 >+ >+ >+// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] >+// base address: 0x3b4 >+#define mmCRTC8_IDX 0x002d >+#define mmCRTC8_IDX_BASE_IDX 1 >+#define mmCRTC8_DATA 0x002d >+#define mmCRTC8_DATA_BASE_IDX 1 >+#define mmGENFC_WT 0x002e >+#define mmGENFC_WT_BASE_IDX 1 >+#define mmGENS1 0x002e >+#define mmGENS1_BASE_IDX 1 >+#define mmATTRDW 0x0030 >+#define mmATTRDW_BASE_IDX 1 >+#define mmATTRX 0x0030 >+#define mmATTRX_BASE_IDX 1 >+#define mmATTRDR 0x0030 >+#define mmATTRDR_BASE_IDX 1 >+#define mmGENMO_WT 0x0030 >+#define mmGENMO_WT_BASE_IDX 1 >+#define mmGENS0 0x0030 >+#define mmGENS0_BASE_IDX 1 >+#define mmGENENB 0x0030 >+#define mmGENENB_BASE_IDX 1 >+#define mmSEQ8_IDX 0x0031 >+#define mmSEQ8_IDX_BASE_IDX 1 >+#define mmSEQ8_DATA 0x0031 >+#define mmSEQ8_DATA_BASE_IDX 1 >+#define mmDAC_MASK 0x0031 >+#define mmDAC_MASK_BASE_IDX 1 >+#define mmDAC_R_INDEX 0x0031 >+#define mmDAC_R_INDEX_BASE_IDX 1 >+#define mmDAC_W_INDEX 0x0032 >+#define mmDAC_W_INDEX_BASE_IDX 1 >+#define mmDAC_DATA 0x0032 >+#define mmDAC_DATA_BASE_IDX 1 >+#define mmGENFC_RD 0x0032 >+#define mmGENFC_RD_BASE_IDX 1 >+#define mmGENMO_RD 0x0033 >+#define mmGENMO_RD_BASE_IDX 1 >+#define mmGRPH8_IDX 0x0033 >+#define mmGRPH8_IDX_BASE_IDX 1 >+#define mmGRPH8_DATA 0x0033 >+#define mmGRPH8_DATA_BASE_IDX 1 >+#define mmCRTC8_IDX_1 0x0035 >+#define mmCRTC8_IDX_1_BASE_IDX 1 >+#define mmCRTC8_DATA_1 0x0035 >+#define mmCRTC8_DATA_1_BASE_IDX 1 >+#define mmGENFC_WT_1 0x0036 >+#define mmGENFC_WT_1_BASE_IDX 1 >+#define mmGENS1_1 0x0036 >+#define mmGENS1_1_BASE_IDX 1 >+ >+ >+// addressBlock: dce_dc_mmhubbub_vga_dispdec >+// base address: 0x0 >+#define mmVGA_RENDER_CONTROL 0x0000 >+#define mmVGA_RENDER_CONTROL_BASE_IDX 1 >+#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 >+#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 >+#define mmVGA_MODE_CONTROL 0x0002 >+#define mmVGA_MODE_CONTROL_BASE_IDX 1 >+#define mmVGA_SURFACE_PITCH_SELECT 0x0003 >+#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 >+#define mmVGA_MEMORY_BASE_ADDRESS 0x0004 >+#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 >+#define mmVGA_TEST_DEBUG_INDEX 0x0005 >+#define mmVGA_TEST_DEBUG_INDEX_BASE_IDX 1 >+#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 >+#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 >+#define mmVGA_TEST_DEBUG_DATA 0x0007 >+#define mmVGA_TEST_DEBUG_DATA_BASE_IDX 1 >+#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 >+#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 >+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 >+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 >+#define mmVGA_HDP_CONTROL 0x000a >+#define mmVGA_HDP_CONTROL_BASE_IDX 1 >+#define mmVGA_CACHE_CONTROL 0x000b >+#define mmVGA_CACHE_CONTROL_BASE_IDX 1 >+#define mmD1VGA_CONTROL 0x000c >+#define mmD1VGA_CONTROL_BASE_IDX 1 >+#define mmVGA_SECURITY_LEVEL 0x000d >+#define mmVGA_SECURITY_LEVEL_BASE_IDX 1 >+#define mmD2VGA_CONTROL 0x000e >+#define mmD2VGA_CONTROL_BASE_IDX 1 >+#define mmVGA_HW_DEBUG 0x000f >+#define mmVGA_HW_DEBUG_BASE_IDX 1 >+#define mmVGA_STATUS 0x0010 >+#define mmVGA_STATUS_BASE_IDX 1 >+#define mmVGA_INTERRUPT_CONTROL 0x0011 >+#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 >+#define mmVGA_STATUS_CLEAR 0x0012 >+#define mmVGA_STATUS_CLEAR_BASE_IDX 1 >+#define mmVGA_INTERRUPT_STATUS 0x0013 >+#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 >+#define mmVGA_MAIN_CONTROL 0x0014 >+#define mmVGA_MAIN_CONTROL_BASE_IDX 1 >+#define mmVGA_TEST_CONTROL 0x0015 >+#define mmVGA_TEST_CONTROL_BASE_IDX 1 >+#define mmVGA_DEBUG_READBACK_INDEX 0x0016 >+#define mmVGA_DEBUG_READBACK_INDEX_BASE_IDX 1 >+#define mmVGA_DEBUG_READBACK_DATA 0x0017 >+#define mmVGA_DEBUG_READBACK_DATA_BASE_IDX 1 >+#define mmVGA_QOS_CTRL 0x0018 >+#define mmVGA_QOS_CTRL_BASE_IDX 1 >+#define mmD3VGA_CONTROL 0x0038 >+#define mmD3VGA_CONTROL_BASE_IDX 1 >+#define mmD4VGA_CONTROL 0x0039 >+#define mmD4VGA_CONTROL_BASE_IDX 1 >+#define mmD5VGA_CONTROL 0x003a >+#define mmD5VGA_CONTROL_BASE_IDX 1 >+#define mmD6VGA_CONTROL 0x003b >+#define mmD6VGA_CONTROL_BASE_IDX 1 >+#define mmVGA_SOURCE_SELECT 0x003c >+#define mmVGA_SOURCE_SELECT_BASE_IDX 1 >+ >+ >+// addressBlock: dce_dc_dccg_dccg_dispdec >+// base address: 0x0 >+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 >+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 >+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 >+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 >+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 >+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 >+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 >+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 >+#define mmDP_DTO_DBUF_EN 0x0044 >+#define mmDP_DTO_DBUF_EN_BASE_IDX 1 >+#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 >+#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 >+#define mmREFCLK_CNTL 0x0049 >+#define mmREFCLK_CNTL_BASE_IDX 1 >+#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b >+#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 >+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c >+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 >+#define mmDCCG_PERFMON_CNTL2 0x004e >+#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 >+#define mmDCCG_DS_DTO_INCR 0x0053 >+#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 >+#define mmDCCG_DS_DTO_MODULO 0x0054 >+#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 >+#define mmDCCG_DS_CNTL 0x0055 >+#define mmDCCG_DS_CNTL_BASE_IDX 1 >+#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 >+#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 >+#define mmDPREFCLK_CNTL 0x0058 >+#define mmDPREFCLK_CNTL_BASE_IDX 1 >+#define mmDCE_VERSION 0x005e >+#define mmDCE_VERSION_BASE_IDX 1 >+#define mmDCCG_GTC_CNTL 0x0060 >+#define mmDCCG_GTC_CNTL_BASE_IDX 1 >+#define mmDCCG_GTC_DTO_INCR 0x0061 >+#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 >+#define mmDCCG_GTC_DTO_MODULO 0x0062 >+#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 >+#define mmDCCG_GTC_CURRENT 0x0063 >+#define mmDCCG_GTC_CURRENT_BASE_IDX 1 >+#define mmDSCCLK0_DTO_PARAM 0x006c >+#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1 >+#define mmDSCCLK1_DTO_PARAM 0x006d >+#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1 >+#define mmDSCCLK2_DTO_PARAM 0x006e >+#define mmDSCCLK2_DTO_PARAM_BASE_IDX 1 >+#define mmMILLISECOND_TIME_BASE_DIV 0x0070 >+#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 >+#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 >+#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 >+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 >+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 >+#define mmDCCG_PERFMON_CNTL 0x0073 >+#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 >+#define mmDCCG_GATE_DISABLE_CNTL 0x0074 >+#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 >+#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 >+#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 >+#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 >+#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 >+#define mmDCCG_CAC_STATUS 0x0077 >+#define mmDCCG_CAC_STATUS_BASE_IDX 1 >+#define mmMICROSECOND_TIME_BASE_DIV 0x007b >+#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 >+#define mmDCCG_GATE_DISABLE_CNTL2 0x007c >+#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 >+#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d >+#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 >+#define mmDCCG_DISP_CNTL_REG 0x007f >+#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 >+#define mmOTG0_PIXEL_RATE_CNTL 0x0080 >+#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 >+#define mmDP_DTO0_PHASE 0x0081 >+#define mmDP_DTO0_PHASE_BASE_IDX 1 >+#define mmDP_DTO0_MODULO 0x0082 >+#define mmDP_DTO0_MODULO_BASE_IDX 1 >+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 >+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 >+#define mmOTG1_PIXEL_RATE_CNTL 0x0084 >+#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 >+#define mmDP_DTO1_PHASE 0x0085 >+#define mmDP_DTO1_PHASE_BASE_IDX 1 >+#define mmDP_DTO1_MODULO 0x0086 >+#define mmDP_DTO1_MODULO_BASE_IDX 1 >+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 >+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 >+#define mmOTG2_PIXEL_RATE_CNTL 0x0088 >+#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 >+#define mmDP_DTO2_PHASE 0x0089 >+#define mmDP_DTO2_PHASE_BASE_IDX 1 >+#define mmDP_DTO2_MODULO 0x008a >+#define mmDP_DTO2_MODULO_BASE_IDX 1 >+#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b >+#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 >+#define mmOTG3_PIXEL_RATE_CNTL 0x008c >+#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 >+#define mmDP_DTO3_PHASE 0x008d >+#define mmDP_DTO3_PHASE_BASE_IDX 1 >+#define mmDP_DTO3_MODULO 0x008e >+#define mmDP_DTO3_MODULO_BASE_IDX 1 >+#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f >+#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 >+#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 >+#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 >+#define mmDPPCLK0_DTO_PARAM 0x0099 >+#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1 >+#define mmDPPCLK1_DTO_PARAM 0x009a >+#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1 >+#define mmDPPCLK2_DTO_PARAM 0x009b >+#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1 >+#define mmDPPCLK3_DTO_PARAM 0x009c >+#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1 >+#define mmDCCG_CAC_STATUS2 0x009f >+#define mmDCCG_CAC_STATUS2_BASE_IDX 1 >+#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 >+#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 >+#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 >+#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 >+#define mmSYMCLKC_CLOCK_ENABLE 0x00a2 >+#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 >+#define mmSYMCLKD_CLOCK_ENABLE 0x00a3 >+#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 >+#define mmSYMCLKE_CLOCK_ENABLE 0x00a4 >+#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 >+#define mmDCCG_SOFT_RESET 0x00a6 >+#define mmDCCG_SOFT_RESET_BASE_IDX 1 >+#define mmDSCCLK_DTO_CTRL 0x00a7 >+#define mmDSCCLK_DTO_CTRL_BASE_IDX 1 >+#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab >+#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 >+#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac >+#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 >+#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad >+#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 >+#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae >+#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 >+#define mmDCCG_AUDIO_DTO1_MODULE 0x00af >+#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 >+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 >+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 >+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 >+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 >+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 >+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 >+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 >+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 >+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 >+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 >+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 >+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 >+#define mmDPPCLK_DTO_CTRL 0x00b6 >+#define mmDPPCLK_DTO_CTRL_BASE_IDX 1 >+#define mmDCCG_VSYNC_CNT_CTRL 0x00b8 >+#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 >+#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 >+#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 >+#define mmFORCE_SYMCLK_DISABLE 0x00ba >+#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1 >+#define mmDCCG_TEST_CLK_SEL 0x00be >+#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1 >+ >+ >+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec >+// base address: 0x0 >+#define mmDENTIST_DISPCLK_CNTL 0x0064 >+#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 >+ >+ >+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec >+// base address: 0x0 >+#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 >+#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 >+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 >+#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON0_PERFMON_CNTL 0x0003 >+#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 >+#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 >+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 >+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON0_PERFMON_HI 0x0007 >+#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON0_PERFMON_LOW 0x0008 >+#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec >+// base address: 0x30 >+#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c >+#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d >+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e >+#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON1_PERFMON_CNTL 0x000f >+#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010 >+#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 >+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 >+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON1_PERFMON_HI 0x0013 >+#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON1_PERFMON_LOW 0x0014 >+#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dccg_dccg_pll_dispdec >+// base address: 0x0 >+#define mmPLL_MACRO_CNTL_RESERVED0 0x0018 >+#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED1 0x0019 >+#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED2 0x001a >+#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED3 0x001b >+#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED4 0x001c >+#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED5 0x001d >+#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED6 0x001e >+#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED7 0x001f >+#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED8 0x0020 >+#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED9 0x0021 >+#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED10 0x0022 >+#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED11 0x0023 >+#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED12 0x0024 >+#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED13 0x0025 >+#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED14 0x0026 >+#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED15 0x0027 >+#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED16 0x0028 >+#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED17 0x0029 >+#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED18 0x002a >+#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED19 0x002b >+#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED20 0x002c >+#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED21 0x002d >+#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED22 0x002e >+#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED23 0x002f >+#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED24 0x0030 >+#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED25 0x0031 >+#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED26 0x0032 >+#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED27 0x0033 >+#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED28 0x0034 >+#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED29 0x0035 >+#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED30 0x0036 >+#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED31 0x0037 >+#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED32 0x0038 >+#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED33 0x0039 >+#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED34 0x003a >+#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED35 0x003b >+#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED36 0x003c >+#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED37 0x003d >+#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED38 0x003e >+#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED39 0x003f >+#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED40 0x0040 >+#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2 >+#define mmPLL_MACRO_CNTL_RESERVED41 0x0041 >+#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dmu_rbbmif_dispdec >+// base address: 0x0 >+#define mmRBBMIF_TIMEOUT 0x005b >+#define mmRBBMIF_TIMEOUT_BASE_IDX 2 >+#define mmRBBMIF_STATUS 0x005c >+#define mmRBBMIF_STATUS_BASE_IDX 2 >+#define mmRBBMIF_STATUS_2 0x005d >+#define mmRBBMIF_STATUS_2_BASE_IDX 2 >+#define mmRBBMIF_INT_STATUS 0x005e >+#define mmRBBMIF_INT_STATUS_BASE_IDX 2 >+#define mmRBBMIF_TIMEOUT_DIS 0x005f >+#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 >+#define mmRBBMIF_TIMEOUT_DIS_2 0x0060 >+#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 >+#define mmRBBMIF_STATUS_FLAG 0x0061 >+#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dmu_dc_pg_dispdec >+// base address: 0x0 >+#define mmDOMAIN0_PG_CONFIG 0x0080 >+#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN0_PG_STATUS 0x0081 >+#define mmDOMAIN0_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN1_PG_CONFIG 0x0082 >+#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN1_PG_STATUS 0x0083 >+#define mmDOMAIN1_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN2_PG_CONFIG 0x0084 >+#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN2_PG_STATUS 0x0085 >+#define mmDOMAIN2_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN3_PG_CONFIG 0x0086 >+#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN3_PG_STATUS 0x0087 >+#define mmDOMAIN3_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN4_PG_CONFIG 0x0088 >+#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN4_PG_STATUS 0x0089 >+#define mmDOMAIN4_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN5_PG_CONFIG 0x008a >+#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN5_PG_STATUS 0x008b >+#define mmDOMAIN5_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN6_PG_CONFIG 0x008c >+#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN6_PG_STATUS 0x008d >+#define mmDOMAIN6_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN7_PG_CONFIG 0x008e >+#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN7_PG_STATUS 0x008f >+#define mmDOMAIN7_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN16_PG_CONFIG 0x00a1 >+#define mmDOMAIN16_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN16_PG_STATUS 0x00a2 >+#define mmDOMAIN16_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN17_PG_CONFIG 0x00a3 >+#define mmDOMAIN17_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN17_PG_STATUS 0x00a4 >+#define mmDOMAIN17_PG_STATUS_BASE_IDX 2 >+#define mmDOMAIN18_PG_CONFIG 0x00a5 >+#define mmDOMAIN18_PG_CONFIG_BASE_IDX 2 >+#define mmDOMAIN18_PG_STATUS 0x00a6 >+#define mmDOMAIN18_PG_STATUS_BASE_IDX 2 >+#define mmDCPG_INTERRUPT_STATUS 0x00ad >+#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDCPG_INTERRUPT_STATUS_2 0x00ae >+#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 >+#define mmDCPG_INTERRUPT_CONTROL_1 0x00af >+#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 >+#define mmDCPG_INTERRUPT_CONTROL_2 0x00b0 >+#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 >+#define mmDCPG_INTERRUPT_CONTROL_3 0x00b1 >+#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 >+#define mmDC_IP_REQUEST_CNTL 0x00b2 >+#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec >+// base address: 0x2f8 >+#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be >+#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf >+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 >+#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1 >+#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2 >+#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 >+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 >+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON2_PERFMON_HI 0x00c5 >+#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON2_PERFMON_LOW 0x00c6 >+#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dmu_dmu_misc_dispdec >+// base address: 0x0 >+#define mmCC_DC_PIPE_DIS 0x00ca >+#define mmCC_DC_PIPE_DIS_BASE_IDX 2 >+#define mmDMU_CLK_CNTL 0x00cb >+#define mmDMU_CLK_CNTL_BASE_IDX 2 >+#define mmDMU_MEM_PWR_CNTL 0x00cc >+#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 >+#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd >+#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 >+#define mmSMU_INTERRUPT_CONTROL 0x00ce >+#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6 >+#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dmu_dmcu_dispdec >+// base address: 0x0 >+#define mmDMCU_CTRL 0x00da >+#define mmDMCU_CTRL_BASE_IDX 2 >+#define mmDMCU_STATUS 0x00db >+#define mmDMCU_STATUS_BASE_IDX 2 >+#define mmDMCU_PC_START_ADDR 0x00dc >+#define mmDMCU_PC_START_ADDR_BASE_IDX 2 >+#define mmDMCU_FW_START_ADDR 0x00dd >+#define mmDMCU_FW_START_ADDR_BASE_IDX 2 >+#define mmDMCU_FW_END_ADDR 0x00de >+#define mmDMCU_FW_END_ADDR_BASE_IDX 2 >+#define mmDMCU_FW_ISR_START_ADDR 0x00df >+#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 >+#define mmDMCU_FW_CS_HI 0x00e0 >+#define mmDMCU_FW_CS_HI_BASE_IDX 2 >+#define mmDMCU_FW_CS_LO 0x00e1 >+#define mmDMCU_FW_CS_LO_BASE_IDX 2 >+#define mmDMCU_RAM_ACCESS_CTRL 0x00e2 >+#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 >+#define mmDMCU_ERAM_WR_CTRL 0x00e3 >+#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 >+#define mmDMCU_ERAM_WR_DATA 0x00e4 >+#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 >+#define mmDMCU_ERAM_RD_CTRL 0x00e5 >+#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 >+#define mmDMCU_ERAM_RD_DATA 0x00e6 >+#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 >+#define mmDMCU_IRAM_WR_CTRL 0x00e7 >+#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 >+#define mmDMCU_IRAM_WR_DATA 0x00e8 >+#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 >+#define mmDMCU_IRAM_RD_CTRL 0x00e9 >+#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 >+#define mmDMCU_IRAM_RD_DATA 0x00ea >+#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 >+#define mmDMCU_EVENT_TRIGGER 0x00eb >+#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 >+#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec >+#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 >+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed >+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_STATUS 0x00ee >+#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_STATUS_1 0x00ef >+#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 >+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 >+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 >+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 >+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 >+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 >+#define mmDC_DMCU_SCRATCH 0x00f5 >+#define mmDC_DMCU_SCRATCH_BASE_IDX 2 >+#define mmDMCU_INT_CNT 0x00f6 >+#define mmDMCU_INT_CNT_BASE_IDX 2 >+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 >+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 >+#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8 >+#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 >+#define mmMASTER_COMM_DATA_REG1 0x00f9 >+#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 >+#define mmMASTER_COMM_DATA_REG2 0x00fa >+#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 >+#define mmMASTER_COMM_DATA_REG3 0x00fb >+#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 >+#define mmMASTER_COMM_CMD_REG 0x00fc >+#define mmMASTER_COMM_CMD_REG_BASE_IDX 2 >+#define mmMASTER_COMM_CNTL_REG 0x00fd >+#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 >+#define mmSLAVE_COMM_DATA_REG1 0x00fe >+#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 >+#define mmSLAVE_COMM_DATA_REG2 0x00ff >+#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 >+#define mmSLAVE_COMM_DATA_REG3 0x0100 >+#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 >+#define mmSLAVE_COMM_CMD_REG 0x0101 >+#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 >+#define mmSLAVE_COMM_CNTL_REG 0x0102 >+#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 >+#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 >+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 >+#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 >+#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 >+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 >+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 >+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 >+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 >+#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a >+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b >+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 >+#define mmDMCU_INT_CNT_CONTINUE 0x011c >+#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d >+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_STATUS_2 0x011e >+#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 >+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f >+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dmu_ihc_dispdec >+// base address: 0x0 >+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 >+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 >+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 >+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 >+#define mmDC_GPU_TIMER_READ 0x0128 >+#define mmDC_GPU_TIMER_READ_BASE_IDX 2 >+#define mmDC_GPU_TIMER_READ_CNTL 0x0129 >+#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS 0x012a >+#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b >+#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c >+#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d >+#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e >+#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f >+#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a >+#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b >+#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c >+#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d >+#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e >+#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f >+#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 >+#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 >+#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 >+#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 >+#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 >+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 >+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 >+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 >+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 >+#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 >+#define mmDCCG_INTERRUPT_DEST 0x0147 >+#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDMU_INTERRUPT_DEST 0x0148 >+#define mmDMU_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDCPG_INTERRUPT_DEST 0x0149 >+#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDCPG_INTERRUPT_DEST2 0x014a >+#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2 >+#define mmMMHUBBUB_INTERRUPT_DEST 0x014b >+#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 >+#define mmWB_INTERRUPT_DEST 0x014c >+#define mmWB_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDCHUB_INTERRUPT_DEST 0x014d >+#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x014e >+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDCHUB_INTERRUPT_DEST2 0x014f >+#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2 >+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0150 >+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 >+#define mmMPC_INTERRUPT_DEST 0x0151 >+#define mmMPC_INTERRUPT_DEST_BASE_IDX 2 >+#define mmOPP_INTERRUPT_DEST 0x0152 >+#define mmOPP_INTERRUPT_DEST_BASE_IDX 2 >+#define mmOPTC_INTERRUPT_DEST 0x0153 >+#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2 >+#define mmOTG0_INTERRUPT_DEST 0x0154 >+#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2 >+#define mmOTG1_INTERRUPT_DEST 0x0155 >+#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2 >+#define mmOTG2_INTERRUPT_DEST 0x0156 >+#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2 >+#define mmOTG3_INTERRUPT_DEST 0x0157 >+#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2 >+#define mmOTG4_INTERRUPT_DEST 0x0158 >+#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2 >+#define mmOTG5_INTERRUPT_DEST 0x0159 >+#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDIG_INTERRUPT_DEST 0x015a >+#define mmDIG_INTERRUPT_DEST_BASE_IDX 2 >+#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015b >+#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDIO_INTERRUPT_DEST 0x015d >+#define mmDIO_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDCIO_INTERRUPT_DEST 0x015e >+#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2 >+#define mmHPD_INTERRUPT_DEST 0x015f >+#define mmHPD_INTERRUPT_DEST_BASE_IDX 2 >+#define mmAZ_INTERRUPT_DEST 0x0160 >+#define mmAZ_INTERRUPT_DEST_BASE_IDX 2 >+#define mmAUX_INTERRUPT_DEST 0x0161 >+#define mmAUX_INTERRUPT_DEST_BASE_IDX 2 >+#define mmDSC_INTERRUPT_DEST 0x0162 >+#define mmDSC_INTERRUPT_DEST_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec >+// base address: 0x0 >+#define mmWB_ENABLE 0x01da >+#define mmWB_ENABLE_BASE_IDX 2 >+#define mmWB_EC_CONFIG 0x01db >+#define mmWB_EC_CONFIG_BASE_IDX 2 >+#define mmCNV_MODE 0x01dc >+#define mmCNV_MODE_BASE_IDX 2 >+#define mmCNV_WINDOW_START 0x01dd >+#define mmCNV_WINDOW_START_BASE_IDX 2 >+#define mmCNV_WINDOW_SIZE 0x01de >+#define mmCNV_WINDOW_SIZE_BASE_IDX 2 >+#define mmCNV_UPDATE 0x01df >+#define mmCNV_UPDATE_BASE_IDX 2 >+#define mmCNV_SOURCE_SIZE 0x01e0 >+#define mmCNV_SOURCE_SIZE_BASE_IDX 2 >+#define mmCNV_TEST_CNTL 0x01ee >+#define mmCNV_TEST_CNTL_BASE_IDX 2 >+#define mmCNV_TEST_CRC_RED 0x01ef >+#define mmCNV_TEST_CRC_RED_BASE_IDX 2 >+#define mmCNV_TEST_CRC_GREEN 0x01f0 >+#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2 >+#define mmCNV_TEST_CRC_BLUE 0x01f1 >+#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2 >+#define mmWB_DEBUG_CTRL 0x01f2 >+#define mmWB_DEBUG_CTRL_BASE_IDX 2 >+#define mmWB_DBG_MODE 0x01f3 >+#define mmWB_DBG_MODE_BASE_IDX 2 >+#define mmWB_HW_DEBUG 0x01f4 >+#define mmWB_HW_DEBUG_BASE_IDX 2 >+#define mmWB_SOFT_RESET 0x01f5 >+#define mmWB_SOFT_RESET_BASE_IDX 2 >+#define mmWB_WARM_UP_MODE_CTL1 0x01f6 >+#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2 >+#define mmWB_WARM_UP_MODE_CTL2 0x01f7 >+#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2 >+#define mmCNV_TEST_DEBUG_INDEX 0x01f8 >+#define mmCNV_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmCNV_TEST_DEBUG_DATA 0x01f9 >+#define mmCNV_TEST_DEBUG_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec >+// base address: 0x0 >+#define mmWBSCL_COEF_RAM_SELECT 0x020a >+#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2 >+#define mmWBSCL_COEF_RAM_TAP_DATA 0x020b >+#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 >+#define mmWBSCL_MODE 0x020c >+#define mmWBSCL_MODE_BASE_IDX 2 >+#define mmWBSCL_TAP_CONTROL 0x020d >+#define mmWBSCL_TAP_CONTROL_BASE_IDX 2 >+#define mmWBSCL_DEST_SIZE 0x020e >+#define mmWBSCL_DEST_SIZE_BASE_IDX 2 >+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x020f >+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210 >+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 >+#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0211 >+#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 >+#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x0212 >+#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x0213 >+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 >+#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x0214 >+#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 >+#define mmWBSCL_ROUND_OFFSET 0x0215 >+#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2 >+#define mmWBSCL_OVERFLOW_STATUS 0x0216 >+#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2 >+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0217 >+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 >+#define mmWBSCL_TEST_CNTL 0x0218 >+#define mmWBSCL_TEST_CNTL_BASE_IDX 2 >+#define mmWBSCL_TEST_CRC_RED 0x0219 >+#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2 >+#define mmWBSCL_TEST_CRC_GREEN 0x021a >+#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2 >+#define mmWBSCL_TEST_CRC_BLUE 0x021b >+#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2 >+#define mmWBSCL_BACKPRESSURE_CNT_EN 0x021c >+#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 >+#define mmWB_MCIF_BACKPRESSURE_CNT 0x021d >+#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 >+#define mmWBSCL_CLAMP_Y_RGB 0x021e >+#define mmWBSCL_CLAMP_Y_RGB_BASE_IDX 2 >+#define mmWBSCL_CLAMP_CBCR 0x021f >+#define mmWBSCL_CLAMP_CBCR_BASE_IDX 2 >+#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0220 >+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 >+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR 0x0221 >+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR_BASE_IDX 2 >+#define mmWBSCL_DEBUG 0x0222 >+#define mmWBSCL_DEBUG_BASE_IDX 2 >+#define mmWBSCL_TEST_DEBUG_INDEX 0x0223 >+#define mmWBSCL_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmWBSCL_TEST_DEBUG_DATA 0x0224 >+#define mmWBSCL_TEST_DEBUG_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec >+// base address: 0x8e8 >+#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a >+#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b >+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c >+#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON3_PERFMON_CNTL 0x023d >+#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON3_PERFMON_CNTL2 0x023e >+#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f >+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240 >+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON3_PERFMON_HI 0x0241 >+#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON3_PERFMON_LOW 0x0242 >+#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec >+// base address: 0x0 >+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2 >+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3 >+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4 >+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5 >+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba >+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb >+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc >+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd >+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be >+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf >+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x02c0 >+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x02c1 >+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2 >+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3 >+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4 >+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5 >+#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6 >+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7 >+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8 >+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9 >+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL 0x02da >+#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db >+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc >+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x02dd >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH 0x02de >+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x02df >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH 0x02e0 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x02e1 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH 0x02e2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x02e3 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH 0x02e4 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION 0x02e5 >+#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION 0x02e6 >+#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION 0x02e7 >+#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION 0x02e8 >+#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec >+// base address: 0x100 >+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2 >+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3 >+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4 >+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5 >+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa >+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb >+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc >+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd >+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe >+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff >+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x0300 >+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x0301 >+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312 >+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313 >+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314 >+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315 >+#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316 >+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317 >+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318 >+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319 >+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b >+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c >+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x031d >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH 0x031e >+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x031f >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH 0x0320 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x0321 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH 0x0322 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x0323 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH 0x0324 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION 0x0325 >+#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION 0x0326 >+#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION 0x0327 >+#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION 0x0328 >+#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec >+// base address: 0x0 >+#define mmWBIF0_MISC_CTRL 0x0333 >+#define mmWBIF0_MISC_CTRL_BASE_IDX 2 >+#define mmWBIF0_SMU_WM_CONTROL 0x0334 >+#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2 >+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 >+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 >+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 >+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 >+#define mmVGA_SRC_SPLIT_CNTL 0x033f >+#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 >+#define mmMMHUBBUB_MEM_PWR_STATUS 0x0340 >+#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmMMHUBBUB_MEM_PWR_CNTL 0x0341 >+#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 >+#define mmMMHUBBUB_CLOCK_CNTL 0x0342 >+#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 >+#define mmMMHUBBUB_SOFT_RESET 0x0343 >+#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 >+#define mmDMU_IF_ERR_STATUS 0x0347 >+#define mmDMU_IF_ERR_STATUS_BASE_IDX 2 >+#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0348 >+#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec >+// base address: 0x0 >+#define mmMCIF_CONTROL 0x034a >+#define mmMCIF_CONTROL_BASE_IDX 2 >+#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b >+#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 >+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e >+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 >+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f >+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 >+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 >+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec >+// base address: 0xd48 >+#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 >+#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 >+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0354 >+#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON4_PERFMON_CNTL 0x0355 >+#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON4_PERFMON_CNTL2 0x0356 >+#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 >+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 >+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON4_PERFMON_HI 0x0359 >+#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON4_PERFMON_LOW 0x035a >+#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream0_dispdec >+// base address: 0x0 >+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e >+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f >+#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream1_dispdec >+// base address: 0x8 >+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 >+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 >+#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream2_dispdec >+// base address: 0x10 >+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 >+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 >+#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream3_dispdec >+// base address: 0x18 >+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 >+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 >+#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream4_dispdec >+// base address: 0x20 >+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 >+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 >+#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream5_dispdec >+// base address: 0x28 >+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 >+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 >+#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream6_dispdec >+// base address: 0x30 >+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a >+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b >+#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream7_dispdec >+// base address: 0x38 >+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c >+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d >+#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_az_misc_dispdec >+// base address: 0x0 >+#define mmAZ_CLOCK_CNTL 0x0372 >+#define mmAZ_CLOCK_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec >+// base address: 0xde8 >+#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x037a >+#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b >+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x037c >+#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON5_PERFMON_CNTL 0x037d >+#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON5_PERFMON_CNTL2 0x037e >+#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f >+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 >+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON5_PERFMON_HI 0x0381 >+#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON5_PERFMON_LOW 0x0382 >+#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec >+// base address: 0x0 >+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 >+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 >+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec >+// base address: 0x18 >+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c >+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d >+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec >+// base address: 0x30 >+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 >+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 >+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec >+// base address: 0x48 >+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 >+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 >+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec >+// base address: 0x60 >+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e >+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f >+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec >+// base address: 0x78 >+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 >+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 >+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec >+// base address: 0x90 >+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa >+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab >+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec >+// base address: 0xa8 >+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 >+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 >+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0controller_dispdec >+// base address: 0x0 >+#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 >+#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 >+#define mmAZALIA_AUDIO_DTO 0x03c3 >+#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 >+#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 >+#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 >+#define mmAZALIA_SOCCLK_CONTROL 0x03c5 >+#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 >+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 >+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 >+#define mmAZALIA_DATA_DMA_CONTROL 0x03c7 >+#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 >+#define mmAZALIA_BDL_DMA_CONTROL 0x03c8 >+#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 >+#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 >+#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 >+#define mmAZALIA_CORB_DMA_CONTROL 0x03ca >+#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 >+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 >+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 >+#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 >+#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 >+#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 >+#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 >+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 >+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 >+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 >+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 >+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 >+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 >+#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da >+#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db >+#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc >+#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd >+#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de >+#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df >+#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 >+#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 >+#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 >+#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 >+#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 >+#define mmAZALIA_CRC0_CONTROL0 0x03e3 >+#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 >+#define mmAZALIA_CRC0_CONTROL1 0x03e4 >+#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 >+#define mmAZALIA_CRC0_CONTROL2 0x03e5 >+#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 >+#define mmAZALIA_CRC0_CONTROL3 0x03e6 >+#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 >+#define mmAZALIA_CRC0_RESULT 0x03e7 >+#define mmAZALIA_CRC0_RESULT_BASE_IDX 2 >+#define mmAZALIA_CRC1_CONTROL0 0x03e8 >+#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 >+#define mmAZALIA_CRC1_CONTROL1 0x03e9 >+#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 >+#define mmAZALIA_CRC1_CONTROL2 0x03ea >+#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 >+#define mmAZALIA_CRC1_CONTROL3 0x03eb >+#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 >+#define mmAZALIA_CRC1_RESULT 0x03ec >+#define mmAZALIA_CRC1_RESULT_BASE_IDX 2 >+#define mmAZALIA_MEM_PWR_CTRL 0x03ee >+#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmAZALIA_MEM_PWR_STATUS 0x03ef >+#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0root_dispdec >+// base address: 0x0 >+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 >+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 >+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 >+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 >+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a >+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b >+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c >+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d >+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e >+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f >+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 >+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 >+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 >+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 >+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 >+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 >+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 >+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a >+#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 >+#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b >+#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 >+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c >+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 >+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d >+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream8_dispdec >+// base address: 0x320 >+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 >+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 >+#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream9_dispdec >+// base address: 0x328 >+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 >+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 >+#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream10_dispdec >+// base address: 0x330 >+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a >+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b >+#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream11_dispdec >+// base address: 0x338 >+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c >+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d >+#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream12_dispdec >+// base address: 0x340 >+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e >+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f >+#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream13_dispdec >+// base address: 0x348 >+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 >+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 >+#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream14_dispdec >+// base address: 0x350 >+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 >+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 >+#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0stream15_dispdec >+// base address: 0x358 >+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 >+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 >+#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 >+#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec >+// base address: 0x0 >+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a >+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b >+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec >+// base address: 0x10 >+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e >+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f >+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec >+// base address: 0x20 >+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 >+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 >+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec >+// base address: 0x30 >+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 >+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 >+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec >+// base address: 0x40 >+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a >+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b >+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec >+// base address: 0x50 >+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e >+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f >+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec >+// base address: 0x60 >+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 >+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 >+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec >+// base address: 0x70 >+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 >+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 >+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 >+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec >+// base address: 0x0 >+#define mmDCHUBBUB_SDPIF_CFG0 0x048f >+#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 >+#define mmVM_REQUEST_PHYSICAL 0x0490 >+#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2 >+#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 >+#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 >+#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 >+#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 >+#define mmDCN_VM_FB_LOCATION_BASE 0x0493 >+#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 >+#define mmDCN_VM_FB_LOCATION_TOP 0x0494 >+#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 >+#define mmDCN_VM_FB_OFFSET 0x0495 >+#define mmDCN_VM_FB_OFFSET_BASE_IDX 2 >+#define mmDCN_VM_AGP_BOT 0x0496 >+#define mmDCN_VM_AGP_BOT_BASE_IDX 2 >+#define mmDCN_VM_AGP_TOP 0x0497 >+#define mmDCN_VM_AGP_TOP_BASE_IDX 2 >+#define mmDCN_VM_AGP_BASE 0x0498 >+#define mmDCN_VM_AGP_BASE_BASE_IDX 2 >+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499 >+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 >+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a >+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 >+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b >+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 >+#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8 >+#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 >+#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x04b9 >+#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 >+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba >+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb >+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmDCHUBBUB_SDPIF_CFG1 0x04bf >+#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 >+#define mmDCHUBBUB_SDPIF_CFG2 0x04c0 >+#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec >+// base address: 0x0 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf >+#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da >+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db >+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc >+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd >+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de >+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df >+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef >+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0 >+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmDCHUBBUB_CRC_CTRL 0x04f1 >+#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 >+#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2 >+#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 >+#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3 >+#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 >+#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4 >+#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 >+#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5 >+#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dchubbub_hubbub_dispdec >+// base address: 0x0 >+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 >+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 >+#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 >+#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 >+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 >+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a >+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b >+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c >+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d >+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e >+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f >+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 >+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 >+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 >+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 >+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514 >+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 >+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 >+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 >+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 >+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 >+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a >+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b >+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c >+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d >+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e >+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 >+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f >+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 >+#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 >+#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 >+#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 >+#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 >+#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 >+#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 >+#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 >+#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 >+#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 >+#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 >+#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 >+#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 >+#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 >+#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 >+#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 >+#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 >+#define mmVTG0_CONTROL 0x0528 >+#define mmVTG0_CONTROL_BASE_IDX 2 >+#define mmVTG1_CONTROL 0x0529 >+#define mmVTG1_CONTROL_BASE_IDX 2 >+#define mmVTG2_CONTROL 0x052a >+#define mmVTG2_CONTROL_BASE_IDX 2 >+#define mmVTG3_CONTROL 0x052b >+#define mmVTG3_CONTROL_BASE_IDX 2 >+#define mmDCHUBBUB_SOFT_RESET 0x052e >+#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 >+#define mmDCHUBBUB_CLOCK_CNTL 0x052f >+#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 >+#define mmDCFCLK_CNTL 0x0530 >+#define mmDCFCLK_CNTL_BASE_IDX 2 >+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 >+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 >+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 >+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 >+#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 >+#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 >+#define mmDCHUBBUB_CTRL_STATUS 0x0534 >+#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2 >+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a >+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 >+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b >+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 >+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c >+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d >+#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e >+#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546 >+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 >+#define mmDCHUBBUB_ARB_HOSTVM_CNTL 0x0547 >+#define mmDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 >+#define mmFMON_CTRL 0x0548 >+#define mmFMON_CTRL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec >+// base address: 0x1534 >+#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x054d >+#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e >+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x054f >+#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON6_PERFMON_CNTL 0x0550 >+#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON6_PERFMON_CNTL2 0x0551 >+#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 >+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 >+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON6_PERFMON_HI 0x0554 >+#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON6_PERFMON_LOW 0x0555 >+#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec >+// base address: 0x0 >+#define mmDCN_VM_CONTEXT0_CNTL 0x0559 >+#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f >+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT1_CNTL 0x0560 >+#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 >+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT2_CNTL 0x0567 >+#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d >+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT3_CNTL 0x056e >+#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 >+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT4_CNTL 0x0575 >+#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b >+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT5_CNTL 0x057c >+#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 >+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT6_CNTL 0x0583 >+#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 >+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT7_CNTL 0x058a >+#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 >+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT8_CNTL 0x0591 >+#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 >+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT9_CNTL 0x0598 >+#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e >+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT10_CNTL 0x059f >+#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 >+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT11_CNTL 0x05a6 >+#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac >+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT12_CNTL 0x05ad >+#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 >+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT13_CNTL 0x05b4 >+#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba >+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT14_CNTL 0x05bb >+#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 >+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT15_CNTL 0x05c2 >+#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 >+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 >+#define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9 >+#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 >+#define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca >+#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 >+#define mmDCN_VM_FAULT_CNTL 0x05cb >+#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2 >+#define mmDCN_VM_FAULT_STATUS 0x05cc >+#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2 >+#define mmDCN_VM_FAULT_ADDR_MSB 0x05cd >+#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 >+#define mmDCN_VM_FAULT_ADDR_LSB 0x05ce >+#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec >+// base address: 0x0 >+#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 >+#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 >+#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6 >+#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 >+#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7 >+#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 >+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 >+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 >+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea >+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 >+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb >+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 >+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec >+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 >+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed >+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 >+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee >+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 >+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef >+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 >+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 >+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 >+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 >+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 >+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 >+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 >+#define mmHUBP0_DCHUBP_CNTL 0x05f3 >+#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 >+#define mmHUBP0_HUBP_CLK_CNTL 0x05f4 >+#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 >+#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 >+#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 >+#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6 >+#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 >+#define mmHUBP0_HUBPREQ_DEBUG 0x05f7 >+#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 >+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb >+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 >+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc >+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec >+// base address: 0x0 >+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 >+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 >+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 >+#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609 >+#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a >+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b >+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c >+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d >+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e >+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f >+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 >+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 >+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 >+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 >+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 >+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 >+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 >+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 >+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 >+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 >+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a >+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b >+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c >+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 >+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 >+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 >+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 >+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 >+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 >+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 >+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 >+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 >+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x062c >+#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062d >+#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062e >+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062f >+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0630 >+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0631 >+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0632 >+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0633 >+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0634 >+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0635 >+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0636 >+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0637 >+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0638 >+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 >+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0645 >+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 >+#define mmHUBPREQ0_BLANK_OFFSET_0 0x0646 >+#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 >+#define mmHUBPREQ0_BLANK_OFFSET_1 0x0647 >+#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 >+#define mmHUBPREQ0_DST_DIMENSIONS 0x0648 >+#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 >+#define mmHUBPREQ0_DST_AFTER_SCALER 0x0649 >+#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 >+#define mmHUBPREQ0_PREFETCH_SETTINGS 0x064a >+#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 >+#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x064b >+#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064c >+#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064d >+#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064e >+#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064f >+#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x0650 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x0651 >+#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0652 >+#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0653 >+#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0654 >+#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0655 >+#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0656 >+#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0657 >+#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0658 >+#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0659 >+#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ0_NOM_PARAMETERS_6 0x065a >+#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 >+#define mmHUBPREQ0_NOM_PARAMETERS_7 0x065b >+#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 >+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065c >+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 >+#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065d >+#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 >+#define mmHUBPREQ0_CURSOR_SETTINGS 0x065e >+#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 >+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065f >+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 >+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0660 >+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 >+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0661 >+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0662 >+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0665 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0666 >+#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 >+#define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0667 >+#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0668 >+#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0669 >+#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ0_FLIP_PARAMETERS_6 0x066a >+#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec >+// base address: 0x0 >+#define mmHUBPRET0_HUBPRET_CONTROL 0x066c >+#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d >+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e >+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f >+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 >+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671 >+#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672 >+#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673 >+#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 >+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 >+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 >+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec >+// base address: 0x0 >+#define mmCURSOR0_0_CURSOR_CONTROL 0x0678 >+#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 >+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a >+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_SIZE 0x067b >+#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_POSITION 0x067c >+#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d >+#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e >+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f >+#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 >+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 >+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 >+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 >+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 >+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 >+#define mmCURSOR0_0_DMDATA_CNTL 0x0684 >+#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 >+#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685 >+#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 >+#define mmCURSOR0_0_DMDATA_STATUS 0x0686 >+#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 >+#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687 >+#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 >+#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688 >+#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x1a74 >+#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x069d >+#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e >+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x069f >+#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON7_PERFMON_CNTL 0x06a0 >+#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON7_PERFMON_CNTL2 0x06a1 >+#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 >+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 >+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON7_PERFMON_HI 0x06a4 >+#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON7_PERFMON_LOW 0x06a5 >+#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec >+// base address: 0x370 >+#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 >+#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 >+#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2 >+#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 >+#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3 >+#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 >+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 >+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 >+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 >+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 >+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 >+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 >+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 >+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 >+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 >+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 >+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca >+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 >+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb >+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 >+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc >+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 >+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd >+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 >+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce >+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 >+#define mmHUBP1_DCHUBP_CNTL 0x06cf >+#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 >+#define mmHUBP1_HUBP_CLK_CNTL 0x06d0 >+#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 >+#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 >+#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 >+#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2 >+#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 >+#define mmHUBP1_HUBPREQ_DEBUG 0x06d3 >+#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 >+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 >+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 >+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 >+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec >+// base address: 0x370 >+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 >+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 >+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 >+#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5 >+#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 >+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 >+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 >+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 >+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea >+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb >+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec >+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed >+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee >+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef >+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 >+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 >+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 >+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 >+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 >+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 >+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 >+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 >+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc >+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd >+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe >+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff >+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 >+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 >+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 >+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 >+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 >+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0708 >+#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0709 >+#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x070a >+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x070b >+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x070c >+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070d >+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070e >+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070f >+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0710 >+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0711 >+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0712 >+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0713 >+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0714 >+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 >+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0721 >+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 >+#define mmHUBPREQ1_BLANK_OFFSET_0 0x0722 >+#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 >+#define mmHUBPREQ1_BLANK_OFFSET_1 0x0723 >+#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 >+#define mmHUBPREQ1_DST_DIMENSIONS 0x0724 >+#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 >+#define mmHUBPREQ1_DST_AFTER_SCALER 0x0725 >+#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 >+#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0726 >+#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 >+#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0727 >+#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0728 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0729 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x072a >+#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x072b >+#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072c >+#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072d >+#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072e >+#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072f >+#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ1_NOM_PARAMETERS_0 0x0730 >+#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ1_NOM_PARAMETERS_1 0x0731 >+#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0732 >+#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0733 >+#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0734 >+#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0735 >+#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0736 >+#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 >+#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0737 >+#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 >+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0738 >+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 >+#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0739 >+#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 >+#define mmHUBPREQ1_CURSOR_SETTINGS 0x073a >+#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 >+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x073b >+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 >+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073c >+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 >+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073d >+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073e >+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x0741 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0742 >+#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 >+#define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0743 >+#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0744 >+#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0745 >+#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0746 >+#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec >+// base address: 0x370 >+#define mmHUBPRET1_HUBPRET_CONTROL 0x0748 >+#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 >+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a >+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b >+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c >+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d >+#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e >+#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f >+#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 >+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 >+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 >+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec >+// base address: 0x370 >+#define mmCURSOR0_1_CURSOR_CONTROL 0x0754 >+#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 >+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 >+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_SIZE 0x0757 >+#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_POSITION 0x0758 >+#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759 >+#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a >+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b >+#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c >+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d >+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e >+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 >+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f >+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 >+#define mmCURSOR0_1_DMDATA_CNTL 0x0760 >+#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 >+#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761 >+#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 >+#define mmCURSOR0_1_DMDATA_STATUS 0x0762 >+#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 >+#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763 >+#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 >+#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764 >+#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x1de4 >+#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 >+#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a >+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x077b >+#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON8_PERFMON_CNTL 0x077c >+#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON8_PERFMON_CNTL2 0x077d >+#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e >+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f >+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON8_PERFMON_HI 0x0780 >+#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON8_PERFMON_LOW 0x0781 >+#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec >+// base address: 0x6e0 >+#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d >+#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 >+#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e >+#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 >+#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f >+#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 >+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 >+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 >+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 >+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 >+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 >+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 >+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 >+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 >+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 >+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 >+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 >+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 >+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 >+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 >+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 >+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 >+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 >+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 >+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa >+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 >+#define mmHUBP2_DCHUBP_CNTL 0x07ab >+#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2 >+#define mmHUBP2_HUBP_CLK_CNTL 0x07ac >+#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 >+#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad >+#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 >+#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae >+#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 >+#define mmHUBP2_HUBPREQ_DEBUG 0x07af >+#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 >+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 >+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 >+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 >+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec >+// base address: 0x6e0 >+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf >+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 >+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 >+#define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1 >+#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 >+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 >+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 >+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 >+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 >+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 >+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 >+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca >+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb >+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc >+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd >+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce >+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf >+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 >+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 >+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 >+#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 >+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 >+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 >+#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 >+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da >+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db >+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc >+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd >+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de >+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df >+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 >+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e4 >+#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e5 >+#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e6 >+#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e7 >+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e8 >+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e9 >+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07ea >+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07eb >+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07ec >+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ed >+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ee >+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ef >+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07f0 >+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 >+#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fd >+#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 >+#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fe >+#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 >+#define mmHUBPREQ2_BLANK_OFFSET_1 0x07ff >+#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 >+#define mmHUBPREQ2_DST_DIMENSIONS 0x0800 >+#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 >+#define mmHUBPREQ2_DST_AFTER_SCALER 0x0801 >+#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 >+#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0802 >+#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 >+#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0803 >+#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0804 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0805 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0806 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0807 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0808 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0809 >+#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ2_FLIP_PARAMETERS_1 0x080a >+#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x080b >+#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ2_NOM_PARAMETERS_0 0x080c >+#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ2_NOM_PARAMETERS_1 0x080d >+#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ2_NOM_PARAMETERS_2 0x080e >+#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ2_NOM_PARAMETERS_3 0x080f >+#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ2_NOM_PARAMETERS_4 0x0810 >+#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ2_NOM_PARAMETERS_5 0x0811 >+#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0812 >+#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 >+#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0813 >+#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 >+#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0814 >+#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 >+#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0815 >+#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 >+#define mmHUBPREQ2_CURSOR_SETTINGS 0x0816 >+#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 >+#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0817 >+#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 >+#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0818 >+#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 >+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0819 >+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x081a >+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_5 0x081d >+#define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ2_VBLANK_PARAMETERS_6 0x081e >+#define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 >+#define mmHUBPREQ2_FLIP_PARAMETERS_3 0x081f >+#define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ2_FLIP_PARAMETERS_4 0x0820 >+#define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ2_FLIP_PARAMETERS_5 0x0821 >+#define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ2_FLIP_PARAMETERS_6 0x0822 >+#define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec >+// base address: 0x6e0 >+#define mmHUBPRET2_HUBPRET_CONTROL 0x0824 >+#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 >+#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 >+#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 >+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 >+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829 >+#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a >+#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b >+#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c >+#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 >+#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d >+#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec >+// base address: 0x6e0 >+#define mmCURSOR0_2_CURSOR_CONTROL 0x0830 >+#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 >+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 >+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_SIZE 0x0833 >+#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_POSITION 0x0834 >+#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835 >+#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 >+#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837 >+#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 >+#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 >+#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a >+#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 >+#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b >+#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 >+#define mmCURSOR0_2_DMDATA_CNTL 0x083c >+#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 >+#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d >+#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 >+#define mmCURSOR0_2_DMDATA_STATUS 0x083e >+#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 >+#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f >+#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 >+#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840 >+#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x2154 >+#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 >+#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 >+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0857 >+#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON9_PERFMON_CNTL 0x0858 >+#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON9_PERFMON_CNTL2 0x0859 >+#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a >+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b >+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON9_PERFMON_HI 0x085c >+#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON9_PERFMON_LOW 0x085d >+#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec >+// base address: 0xa50 >+#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879 >+#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 >+#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a >+#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 >+#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b >+#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 >+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d >+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 >+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e >+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 >+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f >+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 >+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 >+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 >+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 >+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 >+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 >+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 >+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 >+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 >+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 >+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 >+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 >+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 >+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 >+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 >+#define mmHUBP3_DCHUBP_CNTL 0x0887 >+#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2 >+#define mmHUBP3_HUBP_CLK_CNTL 0x0888 >+#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 >+#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889 >+#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 >+#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a >+#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 >+#define mmHUBP3_HUBPREQ_DEBUG 0x088b >+#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 >+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f >+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 >+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 >+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec >+// base address: 0xa50 >+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b >+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c >+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 >+#define mmHUBPREQ3_VMID_SETTINGS_0 0x089d >+#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e >+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f >+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 >+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 >+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 >+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 >+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 >+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 >+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 >+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 >+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 >+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa >+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab >+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac >+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad >+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae >+#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af >+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 >+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 >+#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 >+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 >+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 >+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 >+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 >+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba >+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb >+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc >+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08c0 >+#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08c1 >+#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08c2 >+#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c3 >+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c4 >+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c5 >+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c6 >+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c7 >+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c8 >+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c9 >+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08ca >+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08cb >+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08cc >+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 >+#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d9 >+#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 >+#define mmHUBPREQ3_BLANK_OFFSET_0 0x08da >+#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 >+#define mmHUBPREQ3_BLANK_OFFSET_1 0x08db >+#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 >+#define mmHUBPREQ3_DST_DIMENSIONS 0x08dc >+#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 >+#define mmHUBPREQ3_DST_AFTER_SCALER 0x08dd >+#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 >+#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08de >+#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 >+#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08df >+#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08e0 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08e1 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e2 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e3 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e4 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e5 >+#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e6 >+#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e7 >+#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e8 >+#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 >+#define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e9 >+#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 >+#define mmHUBPREQ3_NOM_PARAMETERS_2 0x08ea >+#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 >+#define mmHUBPREQ3_NOM_PARAMETERS_3 0x08eb >+#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ec >+#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08ed >+#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ee >+#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 >+#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ef >+#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 >+#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08f0 >+#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 >+#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08f1 >+#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 >+#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f2 >+#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 >+#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f3 >+#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 >+#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f4 >+#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 >+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f5 >+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f6 >+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_5 0x08f9 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ3_VBLANK_PARAMETERS_6 0x08fa >+#define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 >+#define mmHUBPREQ3_FLIP_PARAMETERS_3 0x08fb >+#define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 >+#define mmHUBPREQ3_FLIP_PARAMETERS_4 0x08fc >+#define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 >+#define mmHUBPREQ3_FLIP_PARAMETERS_5 0x08fd >+#define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 >+#define mmHUBPREQ3_FLIP_PARAMETERS_6 0x08fe >+#define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec >+// base address: 0xa50 >+#define mmHUBPRET3_HUBPRET_CONTROL 0x0900 >+#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 >+#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 >+#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 >+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 >+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905 >+#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906 >+#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907 >+#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 >+#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 >+#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 >+#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec >+// base address: 0xa50 >+#define mmCURSOR0_3_CURSOR_CONTROL 0x090c >+#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d >+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e >+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_SIZE 0x090f >+#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_POSITION 0x0910 >+#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911 >+#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 >+#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913 >+#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 >+#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 >+#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 >+#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 >+#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 >+#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 >+#define mmCURSOR0_3_DMDATA_CNTL 0x0918 >+#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 >+#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919 >+#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 >+#define mmCURSOR0_3_DMDATA_STATUS 0x091a >+#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 >+#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b >+#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 >+#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c >+#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x24c4 >+#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 >+#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 >+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0933 >+#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON10_PERFMON_CNTL 0x0934 >+#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON10_PERFMON_CNTL2 0x0935 >+#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 >+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 >+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON10_PERFMON_HI 0x0938 >+#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON10_PERFMON_LOW 0x0939 >+#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec >+// base address: 0x0 >+#define mmDPP_TOP0_DPP_CONTROL 0x0cc5 >+#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 >+#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6 >+#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 >+#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 >+#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 >+#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 >+#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 >+#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9 >+#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 >+#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca >+#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec >+// base address: 0x0 >+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf >+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 >+#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0 >+#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 >+#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 >+#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 >+#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 >+#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 >+#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 >+#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 >+#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 >+#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 >+#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 >+#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 >+#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 >+#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 >+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 >+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 >+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 >+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 >+#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 >+#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 >+#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda >+#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 >+#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb >+#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 >+#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd >+#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec >+// base address: 0x0 >+#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0ce0 >+#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 >+#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0ce1 >+#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 >+#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0ce2 >+#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 >+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0ce3 >+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec >+// base address: 0x0 >+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cea >+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 >+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0ceb >+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 >+#define mmDSCL0_SCL_MODE 0x0cec >+#define mmDSCL0_SCL_MODE_BASE_IDX 2 >+#define mmDSCL0_SCL_TAP_CONTROL 0x0ced >+#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 >+#define mmDSCL0_DSCL_CONTROL 0x0cee >+#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 >+#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cef >+#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 >+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cf0 >+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 >+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0cf1 >+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0cf2 >+#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 >+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0cf3 >+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 >+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0cf4 >+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 >+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0cf5 >+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0cf6 >+#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 >+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0cf7 >+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 >+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0cf8 >+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 >+#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0cf9 >+#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 >+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0cfa >+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 >+#define mmDSCL0_SCL_BLACK_OFFSET 0x0cfb >+#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2 >+#define mmDSCL0_DSCL_UPDATE 0x0cfc >+#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 >+#define mmDSCL0_DSCL_AUTOCAL 0x0cfd >+#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 >+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0cfe >+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 >+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0cff >+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 >+#define mmDSCL0_OTG_H_BLANK 0x0d00 >+#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 >+#define mmDSCL0_OTG_V_BLANK 0x0d01 >+#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 >+#define mmDSCL0_RECOUT_START 0x0d02 >+#define mmDSCL0_RECOUT_START_BASE_IDX 2 >+#define mmDSCL0_RECOUT_SIZE 0x0d03 >+#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 >+#define mmDSCL0_MPC_SIZE 0x0d04 >+#define mmDSCL0_MPC_SIZE_BASE_IDX 2 >+#define mmDSCL0_LB_DATA_FORMAT 0x0d05 >+#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 >+#define mmDSCL0_LB_MEMORY_CTRL 0x0d06 >+#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 >+#define mmDSCL0_LB_V_COUNTER 0x0d07 >+#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 >+#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d08 >+#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d09 >+#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmDSCL0_OBUF_CONTROL 0x0d0a >+#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 >+#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d0b >+#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec >+// base address: 0x0 >+#define mmCM0_CM_CONTROL 0x0d1a >+#define mmCM0_CM_CONTROL_BASE_IDX 2 >+#define mmCM0_CM_ICSC_CONTROL 0x0d1b >+#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2 >+#define mmCM0_CM_ICSC_C11_C12 0x0d1c >+#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2 >+#define mmCM0_CM_ICSC_C13_C14 0x0d1d >+#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2 >+#define mmCM0_CM_ICSC_C21_C22 0x0d1e >+#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2 >+#define mmCM0_CM_ICSC_C23_C24 0x0d1f >+#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2 >+#define mmCM0_CM_ICSC_C31_C32 0x0d20 >+#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2 >+#define mmCM0_CM_ICSC_C33_C34 0x0d21 >+#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2 >+#define mmCM0_CM_ICSC_B_C11_C12 0x0d22 >+#define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX 2 >+#define mmCM0_CM_ICSC_B_C13_C14 0x0d23 >+#define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX 2 >+#define mmCM0_CM_ICSC_B_C21_C22 0x0d24 >+#define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX 2 >+#define mmCM0_CM_ICSC_B_C23_C24 0x0d25 >+#define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX 2 >+#define mmCM0_CM_ICSC_B_C31_C32 0x0d26 >+#define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX 2 >+#define mmCM0_CM_ICSC_B_C33_C34 0x0d27 >+#define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d28 >+#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d29 >+#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d2a >+#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d2b >+#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d2c >+#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d2d >+#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d2e >+#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d2f >+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d30 >+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d31 >+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d32 >+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d33 >+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 >+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d34 >+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 >+#define mmCM0_CM_BIAS_CR_R 0x0d35 >+#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2 >+#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d36 >+#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_CONTROL 0x0d37 >+#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2 >+#define mmCM0_CM_DGAM_LUT_INDEX 0x0d38 >+#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2 >+#define mmCM0_CM_DGAM_LUT_DATA 0x0d39 >+#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2 >+#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0d3a >+#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0d3b >+#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0d3c >+#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0d3d >+#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0d3e >+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0d3f >+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0d40 >+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0d41 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0d42 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0d43 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0d44 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0d45 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0d46 >+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0d47 >+#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0d48 >+#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0d49 >+#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0d4a >+#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0d4b >+#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0d4c >+#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0d4d >+#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0d4e >+#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0d4f >+#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0d50 >+#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0d51 >+#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0d52 >+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0d53 >+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0d54 >+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0d55 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0d56 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0d57 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0d58 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0d59 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0d5a >+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0d5b >+#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0d5c >+#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0d5d >+#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0d5e >+#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0d5f >+#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0d60 >+#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0d61 >+#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0d62 >+#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_CONTROL 0x0d63 >+#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d64 >+#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d65 >+#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0d66 >+#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d67 >+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d68 >+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d69 >+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0d6a >+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0d6b >+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0d6c >+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d6d >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d6e >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d6f >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d70 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d71 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d72 >+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d73 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d74 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d75 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0d76 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0d77 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0d78 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0d79 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0d7a >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0d7b >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0d7c >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0d7d >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0d7e >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0d7f >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0d80 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0d81 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0d82 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0d83 >+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0d84 >+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0d85 >+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0d86 >+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0d87 >+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0d88 >+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0d89 >+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0d8a >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0d8b >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0d8c >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0d8d >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0d8e >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0d8f >+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0d90 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0d91 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0d92 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0d93 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0d94 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0d95 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0d96 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0d97 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0d98 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0d99 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0d9a >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0d9b >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0d9c >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0d9d >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0d9e >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0d9f >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0da0 >+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 >+#define mmCM0_CM_HDR_MULT_COEF 0x0da1 >+#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 >+#define mmCM0_CM_MEM_PWR_CTRL 0x0da2 >+#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmCM0_CM_MEM_PWR_STATUS 0x0da3 >+#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmCM0_CM_DEALPHA 0x0da5 >+#define mmCM0_CM_DEALPHA_BASE_IDX 2 >+#define mmCM0_CM_COEF_FORMAT 0x0da6 >+#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_CONTROL 0x0da7 >+#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_OFFSET_R 0x0da8 >+#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_OFFSET_G 0x0da9 >+#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_OFFSET_B 0x0daa >+#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_SCALE_R 0x0dab >+#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_SCALE_G_B 0x0dac >+#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_LUT_INDEX 0x0dad >+#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_LUT_DATA 0x0dae >+#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0daf >+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0db0 >+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0db1 >+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0db2 >+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0db3 >+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0db4 >+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0db5 >+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0db6 >+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0db7 >+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0db8 >+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0db9 >+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dba >+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0dbb >+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dbc >+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0dbd >+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dbe >+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0dbf >+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0dc0 >+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0dc1 >+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0dc2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0dc3 >+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0dc4 >+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0dc5 >+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0dc6 >+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0dc7 >+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0dc8 >+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0dc9 >+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dca >+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dcb >+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dcc >+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dcd >+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dce >+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dcf >+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0dd0 >+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0dd1 >+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0dd2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0dd3 >+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0dd4 >+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0dd5 >+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0dd6 >+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0dd7 >+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0dd8 >+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0dd9 >+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0dda >+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0ddb >+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0ddc >+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0ddd >+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 >+#define mmCM0_CM_MEM_PWR_CTRL2 0x0dde >+#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 >+#define mmCM0_CM_MEM_PWR_STATUS2 0x0ddf >+#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_MODE 0x0de0 >+#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_INDEX 0x0de1 >+#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_DATA 0x0de2 >+#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_DATA_30BIT 0x0de3 >+#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0de4 >+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0de5 >+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0de6 >+#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0de7 >+#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 >+#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0de8 >+#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 >+#define mmCM0_CM_TEST_DEBUG_INDEX 0x0de9 >+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmCM0_CM_TEST_DEBUG_DATA 0x0dea >+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x3890 >+#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 >+#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 >+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 >+#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON11_PERFMON_CNTL 0x0e27 >+#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON11_PERFMON_CNTL2 0x0e28 >+#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 >+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a >+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON11_PERFMON_HI 0x0e2b >+#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON11_PERFMON_LOW 0x0e2c >+#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec >+// base address: 0x5ac >+#define mmDPP_TOP1_DPP_CONTROL 0x0e30 >+#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 >+#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31 >+#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 >+#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 >+#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 >+#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 >+#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 >+#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34 >+#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 >+#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35 >+#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec >+// base address: 0x5ac >+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a >+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 >+#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b >+#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 >+#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c >+#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 >+#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d >+#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 >+#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e >+#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 >+#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f >+#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 >+#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 >+#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 >+#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 >+#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 >+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 >+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 >+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 >+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 >+#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44 >+#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 >+#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 >+#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 >+#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 >+#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 >+#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 >+#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec >+// base address: 0x5ac >+#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e4b >+#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 >+#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e4c >+#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 >+#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e4d >+#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 >+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e4e >+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec >+// base address: 0x5ac >+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e55 >+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 >+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e56 >+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 >+#define mmDSCL1_SCL_MODE 0x0e57 >+#define mmDSCL1_SCL_MODE_BASE_IDX 2 >+#define mmDSCL1_SCL_TAP_CONTROL 0x0e58 >+#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 >+#define mmDSCL1_DSCL_CONTROL 0x0e59 >+#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 >+#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e5a >+#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 >+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e5b >+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 >+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e5c >+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e5d >+#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 >+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e5e >+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 >+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e5f >+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 >+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e60 >+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e61 >+#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 >+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e62 >+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 >+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e63 >+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 >+#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e64 >+#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 >+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e65 >+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 >+#define mmDSCL1_SCL_BLACK_OFFSET 0x0e66 >+#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2 >+#define mmDSCL1_DSCL_UPDATE 0x0e67 >+#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 >+#define mmDSCL1_DSCL_AUTOCAL 0x0e68 >+#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 >+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e69 >+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 >+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e6a >+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 >+#define mmDSCL1_OTG_H_BLANK 0x0e6b >+#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 >+#define mmDSCL1_OTG_V_BLANK 0x0e6c >+#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 >+#define mmDSCL1_RECOUT_START 0x0e6d >+#define mmDSCL1_RECOUT_START_BASE_IDX 2 >+#define mmDSCL1_RECOUT_SIZE 0x0e6e >+#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 >+#define mmDSCL1_MPC_SIZE 0x0e6f >+#define mmDSCL1_MPC_SIZE_BASE_IDX 2 >+#define mmDSCL1_LB_DATA_FORMAT 0x0e70 >+#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 >+#define mmDSCL1_LB_MEMORY_CTRL 0x0e71 >+#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 >+#define mmDSCL1_LB_V_COUNTER 0x0e72 >+#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 >+#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e73 >+#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e74 >+#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmDSCL1_OBUF_CONTROL 0x0e75 >+#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 >+#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e76 >+#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec >+// base address: 0x5ac >+#define mmCM1_CM_CONTROL 0x0e85 >+#define mmCM1_CM_CONTROL_BASE_IDX 2 >+#define mmCM1_CM_ICSC_CONTROL 0x0e86 >+#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2 >+#define mmCM1_CM_ICSC_C11_C12 0x0e87 >+#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2 >+#define mmCM1_CM_ICSC_C13_C14 0x0e88 >+#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2 >+#define mmCM1_CM_ICSC_C21_C22 0x0e89 >+#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2 >+#define mmCM1_CM_ICSC_C23_C24 0x0e8a >+#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2 >+#define mmCM1_CM_ICSC_C31_C32 0x0e8b >+#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2 >+#define mmCM1_CM_ICSC_C33_C34 0x0e8c >+#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2 >+#define mmCM1_CM_ICSC_B_C11_C12 0x0e8d >+#define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX 2 >+#define mmCM1_CM_ICSC_B_C13_C14 0x0e8e >+#define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX 2 >+#define mmCM1_CM_ICSC_B_C21_C22 0x0e8f >+#define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX 2 >+#define mmCM1_CM_ICSC_B_C23_C24 0x0e90 >+#define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX 2 >+#define mmCM1_CM_ICSC_B_C31_C32 0x0e91 >+#define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX 2 >+#define mmCM1_CM_ICSC_B_C33_C34 0x0e92 >+#define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e93 >+#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e94 >+#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e95 >+#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e96 >+#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e97 >+#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e98 >+#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e99 >+#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0e9a >+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0e9b >+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0e9c >+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0e9d >+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0e9e >+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 >+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0e9f >+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 >+#define mmCM1_CM_BIAS_CR_R 0x0ea0 >+#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2 >+#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea1 >+#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_CONTROL 0x0ea2 >+#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2 >+#define mmCM1_CM_DGAM_LUT_INDEX 0x0ea3 >+#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2 >+#define mmCM1_CM_DGAM_LUT_DATA 0x0ea4 >+#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2 >+#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ea5 >+#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0ea6 >+#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0ea7 >+#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0ea8 >+#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0ea9 >+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eaa >+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab >+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0eac >+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0ead >+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0eae >+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0eaf >+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0eb0 >+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0eb1 >+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0eb2 >+#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0eb3 >+#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0eb4 >+#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0eb5 >+#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0eb6 >+#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0eb7 >+#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0eb8 >+#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0eb9 >+#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0eba >+#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0ebb >+#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0ebc >+#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0ebd >+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0ebe >+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0ebf >+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0ec0 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0ec1 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0ec2 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0ec3 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0ec4 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0ec5 >+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0ec6 >+#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0ec7 >+#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0ec8 >+#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0ec9 >+#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0eca >+#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0ecb >+#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0ecc >+#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0ecd >+#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_CONTROL 0x0ece >+#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ecf >+#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ed0 >+#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0ed1 >+#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ed2 >+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ed3 >+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ed4 >+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0ed5 >+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0ed6 >+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0ed7 >+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0ed8 >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0ed9 >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0eda >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0edb >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0edc >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0edd >+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0ede >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0edf >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0ee0 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0ee1 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0ee2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0ee3 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0ee4 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0ee5 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0ee6 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0ee7 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0ee8 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0ee9 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0eea >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0eeb >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0eec >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0eed >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0eee >+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0eef >+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0ef0 >+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0ef1 >+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0ef2 >+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0ef3 >+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0ef4 >+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0ef5 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0ef6 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0ef7 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0ef8 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0ef9 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0efa >+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0efb >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0efc >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0efd >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0efe >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0eff >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f00 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f01 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f02 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f03 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f04 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f05 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f06 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f07 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f08 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f09 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f0a >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f0b >+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 >+#define mmCM1_CM_HDR_MULT_COEF 0x0f0c >+#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 >+#define mmCM1_CM_MEM_PWR_CTRL 0x0f0d >+#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmCM1_CM_MEM_PWR_STATUS 0x0f0e >+#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmCM1_CM_DEALPHA 0x0f10 >+#define mmCM1_CM_DEALPHA_BASE_IDX 2 >+#define mmCM1_CM_COEF_FORMAT 0x0f11 >+#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_CONTROL 0x0f12 >+#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_OFFSET_R 0x0f13 >+#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_OFFSET_G 0x0f14 >+#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_OFFSET_B 0x0f15 >+#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_SCALE_R 0x0f16 >+#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f17 >+#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f18 >+#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_LUT_DATA 0x0f19 >+#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f1a >+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f1b >+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f1c >+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f1d >+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f1e >+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f1f >+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f20 >+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f21 >+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f22 >+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f23 >+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f24 >+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f25 >+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f26 >+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f27 >+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f28 >+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f29 >+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f2a >+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f2b >+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f2c >+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f2d >+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f2e >+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f2f >+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f30 >+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f31 >+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f32 >+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f33 >+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f34 >+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f35 >+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f36 >+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f37 >+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f38 >+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f39 >+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f3a >+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f3b >+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f3c >+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f3d >+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f3e >+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f3f >+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f40 >+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f41 >+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f42 >+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f43 >+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f44 >+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f45 >+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f46 >+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f47 >+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f48 >+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 >+#define mmCM1_CM_MEM_PWR_CTRL2 0x0f49 >+#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 >+#define mmCM1_CM_MEM_PWR_STATUS2 0x0f4a >+#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_MODE 0x0f4b >+#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_INDEX 0x0f4c >+#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_DATA 0x0f4d >+#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f4e >+#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f4f >+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f50 >+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f51 >+#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f52 >+#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 >+#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f53 >+#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 >+#define mmCM1_CM_TEST_DEBUG_INDEX 0x0f54 >+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmCM1_CM_TEST_DEBUG_DATA 0x0f55 >+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x3e3c >+#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f >+#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 >+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 >+#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON12_PERFMON_CNTL 0x0f92 >+#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON12_PERFMON_CNTL2 0x0f93 >+#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 >+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 >+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON12_PERFMON_HI 0x0f96 >+#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON12_PERFMON_LOW 0x0f97 >+#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec >+// base address: 0xb58 >+#define mmDPP_TOP2_DPP_CONTROL 0x0f9b >+#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2 >+#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c >+#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 >+#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d >+#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 >+#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e >+#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 >+#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f >+#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 >+#define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0 >+#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec >+// base address: 0xb58 >+#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 >+#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 >+#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6 >+#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 >+#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 >+#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 >+#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 >+#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 >+#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 >+#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 >+#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa >+#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 >+#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab >+#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 >+#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac >+#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 >+#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad >+#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 >+#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae >+#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 >+#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf >+#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 >+#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 >+#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 >+#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 >+#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 >+#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 >+#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec >+// base address: 0xb58 >+#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fb6 >+#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 >+#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fb7 >+#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 >+#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fb8 >+#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 >+#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fb9 >+#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec >+// base address: 0xb58 >+#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fc0 >+#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 >+#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fc1 >+#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 >+#define mmDSCL2_SCL_MODE 0x0fc2 >+#define mmDSCL2_SCL_MODE_BASE_IDX 2 >+#define mmDSCL2_SCL_TAP_CONTROL 0x0fc3 >+#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 >+#define mmDSCL2_DSCL_CONTROL 0x0fc4 >+#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2 >+#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fc5 >+#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 >+#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fc6 >+#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 >+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fc7 >+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fc8 >+#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 >+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fc9 >+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 >+#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fca >+#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 >+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fcb >+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fcc >+#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 >+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fcd >+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 >+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fce >+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 >+#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fcf >+#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 >+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fd0 >+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 >+#define mmDSCL2_SCL_BLACK_OFFSET 0x0fd1 >+#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2 >+#define mmDSCL2_DSCL_UPDATE 0x0fd2 >+#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2 >+#define mmDSCL2_DSCL_AUTOCAL 0x0fd3 >+#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2 >+#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fd4 >+#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 >+#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fd5 >+#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 >+#define mmDSCL2_OTG_H_BLANK 0x0fd6 >+#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2 >+#define mmDSCL2_OTG_V_BLANK 0x0fd7 >+#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2 >+#define mmDSCL2_RECOUT_START 0x0fd8 >+#define mmDSCL2_RECOUT_START_BASE_IDX 2 >+#define mmDSCL2_RECOUT_SIZE 0x0fd9 >+#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2 >+#define mmDSCL2_MPC_SIZE 0x0fda >+#define mmDSCL2_MPC_SIZE_BASE_IDX 2 >+#define mmDSCL2_LB_DATA_FORMAT 0x0fdb >+#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2 >+#define mmDSCL2_LB_MEMORY_CTRL 0x0fdc >+#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 >+#define mmDSCL2_LB_V_COUNTER 0x0fdd >+#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2 >+#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fde >+#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fdf >+#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmDSCL2_OBUF_CONTROL 0x0fe0 >+#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2 >+#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0fe1 >+#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec >+// base address: 0xb58 >+#define mmCM2_CM_CONTROL 0x0ff0 >+#define mmCM2_CM_CONTROL_BASE_IDX 2 >+#define mmCM2_CM_ICSC_CONTROL 0x0ff1 >+#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2 >+#define mmCM2_CM_ICSC_C11_C12 0x0ff2 >+#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2 >+#define mmCM2_CM_ICSC_C13_C14 0x0ff3 >+#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2 >+#define mmCM2_CM_ICSC_C21_C22 0x0ff4 >+#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2 >+#define mmCM2_CM_ICSC_C23_C24 0x0ff5 >+#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2 >+#define mmCM2_CM_ICSC_C31_C32 0x0ff6 >+#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2 >+#define mmCM2_CM_ICSC_C33_C34 0x0ff7 >+#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2 >+#define mmCM2_CM_ICSC_B_C11_C12 0x0ff8 >+#define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX 2 >+#define mmCM2_CM_ICSC_B_C13_C14 0x0ff9 >+#define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX 2 >+#define mmCM2_CM_ICSC_B_C21_C22 0x0ffa >+#define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX 2 >+#define mmCM2_CM_ICSC_B_C23_C24 0x0ffb >+#define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX 2 >+#define mmCM2_CM_ICSC_B_C31_C32 0x0ffc >+#define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX 2 >+#define mmCM2_CM_ICSC_B_C33_C34 0x0ffd >+#define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ffe >+#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0fff >+#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1000 >+#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1001 >+#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1002 >+#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1003 >+#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x1004 >+#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x1005 >+#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x1006 >+#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x1007 >+#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x1008 >+#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x1009 >+#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 >+#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x100a >+#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 >+#define mmCM2_CM_BIAS_CR_R 0x100b >+#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2 >+#define mmCM2_CM_BIAS_Y_G_CB_B 0x100c >+#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_CONTROL 0x100d >+#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2 >+#define mmCM2_CM_DGAM_LUT_INDEX 0x100e >+#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2 >+#define mmCM2_CM_DGAM_LUT_DATA 0x100f >+#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2 >+#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x1010 >+#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x1011 >+#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x1012 >+#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x1013 >+#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1014 >+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1015 >+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1016 >+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x1017 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x1018 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x1019 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x101a >+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x101b >+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x101c >+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x101d >+#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x101e >+#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x101f >+#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x1020 >+#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x1021 >+#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x1022 >+#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x1023 >+#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x1024 >+#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x1025 >+#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x1026 >+#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x1027 >+#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1028 >+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1029 >+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102a >+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x102b >+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x102c >+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x102d >+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x102e >+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x102f >+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x1030 >+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x1031 >+#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x1032 >+#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x1033 >+#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x1034 >+#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x1035 >+#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x1036 >+#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x1037 >+#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x1038 >+#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_CONTROL 0x1039 >+#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x103a >+#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_LUT_DATA 0x103b >+#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x103c >+#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x103d >+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x103e >+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x103f >+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x1040 >+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x1041 >+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x1042 >+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1043 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1044 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1045 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1046 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1047 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1048 >+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1049 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x104a >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x104b >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x104c >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x104d >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x104e >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x104f >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x1050 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x1051 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x1052 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x1053 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x1054 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x1055 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1056 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1057 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1058 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1059 >+#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x105a >+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x105b >+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x105c >+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x105d >+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x105e >+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x105f >+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1060 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1061 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1062 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1063 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1064 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1065 >+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1066 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1067 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1068 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1069 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x106a >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x106b >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x106c >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x106d >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x106e >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x106f >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x1070 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x1071 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x1072 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x1073 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x1074 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x1075 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x1076 >+#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 >+#define mmCM2_CM_HDR_MULT_COEF 0x1077 >+#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2 >+#define mmCM2_CM_MEM_PWR_CTRL 0x1078 >+#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmCM2_CM_MEM_PWR_STATUS 0x1079 >+#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmCM2_CM_DEALPHA 0x107b >+#define mmCM2_CM_DEALPHA_BASE_IDX 2 >+#define mmCM2_CM_COEF_FORMAT 0x107c >+#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_CONTROL 0x107d >+#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_OFFSET_R 0x107e >+#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_OFFSET_G 0x107f >+#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_OFFSET_B 0x1080 >+#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_SCALE_R 0x1081 >+#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_SCALE_G_B 0x1082 >+#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_LUT_INDEX 0x1083 >+#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_LUT_DATA 0x1084 >+#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x1085 >+#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x1086 >+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x1087 >+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x1088 >+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x1089 >+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x108a >+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x108b >+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x108c >+#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x108d >+#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x108e >+#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x108f >+#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x1090 >+#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x1091 >+#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x1092 >+#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x1093 >+#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x1094 >+#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x1095 >+#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x1096 >+#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x1097 >+#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x1098 >+#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x1099 >+#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x109a >+#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x109b >+#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x109c >+#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x109d >+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x109e >+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x109f >+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10a0 >+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10a1 >+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10a2 >+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10a3 >+#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10a4 >+#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10a5 >+#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10a6 >+#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10a7 >+#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10a8 >+#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10a9 >+#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10aa >+#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10ab >+#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10ac >+#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10ad >+#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10ae >+#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10af >+#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10b0 >+#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10b1 >+#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10b2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10b3 >+#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 >+#define mmCM2_CM_MEM_PWR_CTRL2 0x10b4 >+#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 >+#define mmCM2_CM_MEM_PWR_STATUS2 0x10b5 >+#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_MODE 0x10b6 >+#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_INDEX 0x10b7 >+#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_DATA 0x10b8 >+#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_DATA_30BIT 0x10b9 >+#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ba >+#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10bb >+#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10bc >+#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10bd >+#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 >+#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10be >+#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 >+#define mmCM2_CM_TEST_DEBUG_INDEX 0x10bf >+#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmCM2_CM_TEST_DEBUG_DATA 0x10c0 >+#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x43e8 >+#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa >+#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb >+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x10fc >+#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON13_PERFMON_CNTL 0x10fd >+#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON13_PERFMON_CNTL2 0x10fe >+#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff >+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 >+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON13_PERFMON_HI 0x1101 >+#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON13_PERFMON_LOW 0x1102 >+#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec >+// base address: 0x1104 >+#define mmDPP_TOP3_DPP_CONTROL 0x1106 >+#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2 >+#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107 >+#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 >+#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 >+#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 >+#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 >+#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 >+#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a >+#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 >+#define mmDPP_TOP3_HOST_READ_CONTROL 0x110b >+#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec >+// base address: 0x1104 >+#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 >+#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 >+#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111 >+#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 >+#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 >+#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 >+#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 >+#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 >+#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 >+#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 >+#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 >+#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 >+#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 >+#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 >+#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 >+#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 >+#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 >+#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 >+#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 >+#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 >+#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a >+#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 >+#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b >+#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 >+#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c >+#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 >+#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e >+#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec >+// base address: 0x1104 >+#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1121 >+#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 >+#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1122 >+#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 >+#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1123 >+#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 >+#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1124 >+#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec >+// base address: 0x1104 >+#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x112b >+#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 >+#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x112c >+#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 >+#define mmDSCL3_SCL_MODE 0x112d >+#define mmDSCL3_SCL_MODE_BASE_IDX 2 >+#define mmDSCL3_SCL_TAP_CONTROL 0x112e >+#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 >+#define mmDSCL3_DSCL_CONTROL 0x112f >+#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2 >+#define mmDSCL3_DSCL_2TAP_CONTROL 0x1130 >+#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 >+#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1131 >+#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 >+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1132 >+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1133 >+#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 >+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1134 >+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 >+#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1135 >+#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 >+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1136 >+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 >+#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1137 >+#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 >+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1138 >+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 >+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1139 >+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 >+#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x113a >+#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 >+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x113b >+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 >+#define mmDSCL3_SCL_BLACK_OFFSET 0x113c >+#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2 >+#define mmDSCL3_DSCL_UPDATE 0x113d >+#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2 >+#define mmDSCL3_DSCL_AUTOCAL 0x113e >+#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2 >+#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x113f >+#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 >+#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1140 >+#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 >+#define mmDSCL3_OTG_H_BLANK 0x1141 >+#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2 >+#define mmDSCL3_OTG_V_BLANK 0x1142 >+#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2 >+#define mmDSCL3_RECOUT_START 0x1143 >+#define mmDSCL3_RECOUT_START_BASE_IDX 2 >+#define mmDSCL3_RECOUT_SIZE 0x1144 >+#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2 >+#define mmDSCL3_MPC_SIZE 0x1145 >+#define mmDSCL3_MPC_SIZE_BASE_IDX 2 >+#define mmDSCL3_LB_DATA_FORMAT 0x1146 >+#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2 >+#define mmDSCL3_LB_MEMORY_CTRL 0x1147 >+#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 >+#define mmDSCL3_LB_V_COUNTER 0x1148 >+#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2 >+#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1149 >+#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x114a >+#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmDSCL3_OBUF_CONTROL 0x114b >+#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2 >+#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x114c >+#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec >+// base address: 0x1104 >+#define mmCM3_CM_CONTROL 0x115b >+#define mmCM3_CM_CONTROL_BASE_IDX 2 >+#define mmCM3_CM_ICSC_CONTROL 0x115c >+#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2 >+#define mmCM3_CM_ICSC_C11_C12 0x115d >+#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2 >+#define mmCM3_CM_ICSC_C13_C14 0x115e >+#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2 >+#define mmCM3_CM_ICSC_C21_C22 0x115f >+#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2 >+#define mmCM3_CM_ICSC_C23_C24 0x1160 >+#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2 >+#define mmCM3_CM_ICSC_C31_C32 0x1161 >+#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2 >+#define mmCM3_CM_ICSC_C33_C34 0x1162 >+#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2 >+#define mmCM3_CM_ICSC_B_C11_C12 0x1163 >+#define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX 2 >+#define mmCM3_CM_ICSC_B_C13_C14 0x1164 >+#define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX 2 >+#define mmCM3_CM_ICSC_B_C21_C22 0x1165 >+#define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX 2 >+#define mmCM3_CM_ICSC_B_C23_C24 0x1166 >+#define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX 2 >+#define mmCM3_CM_ICSC_B_C31_C32 0x1167 >+#define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX 2 >+#define mmCM3_CM_ICSC_B_C33_C34 0x1168 >+#define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1169 >+#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x116a >+#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x116b >+#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x116c >+#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x116d >+#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x116e >+#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x116f >+#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1170 >+#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1171 >+#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1172 >+#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1173 >+#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x1174 >+#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 >+#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x1175 >+#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 >+#define mmCM3_CM_BIAS_CR_R 0x1176 >+#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2 >+#define mmCM3_CM_BIAS_Y_G_CB_B 0x1177 >+#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_CONTROL 0x1178 >+#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2 >+#define mmCM3_CM_DGAM_LUT_INDEX 0x1179 >+#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2 >+#define mmCM3_CM_DGAM_LUT_DATA 0x117a >+#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2 >+#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x117b >+#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x117c >+#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x117d >+#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x117e >+#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x117f >+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1180 >+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1181 >+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x1182 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x1183 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x1184 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x1185 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1186 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1187 >+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1188 >+#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1189 >+#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x118a >+#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x118b >+#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x118c >+#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x118d >+#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x118e >+#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x118f >+#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x1190 >+#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x1191 >+#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x1192 >+#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1193 >+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1194 >+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x1195 >+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1196 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1197 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1198 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1199 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x119a >+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x119b >+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x119c >+#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x119d >+#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x119e >+#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x119f >+#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x11a0 >+#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x11a1 >+#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x11a2 >+#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x11a3 >+#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_CONTROL 0x11a4 >+#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11a5 >+#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11a6 >+#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x11a7 >+#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11a8 >+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11a9 >+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11aa >+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x11ab >+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x11ac >+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x11ad >+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11ae >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11af >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11b0 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11b1 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11b2 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11b3 >+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11b4 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11b5 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11b6 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11b7 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11b8 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11b9 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11ba >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11bb >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11bc >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11bd >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11be >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11bf >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11c0 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11c1 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11c2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11c3 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11c4 >+#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11c5 >+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11c6 >+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11c7 >+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x11c8 >+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x11c9 >+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x11ca >+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11cb >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11cc >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11cd >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11ce >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11cf >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11d0 >+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x11d1 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x11d2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x11d3 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x11d4 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x11d5 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x11d6 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x11d7 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x11d8 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x11d9 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x11da >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x11db >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x11dc >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x11dd >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x11de >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x11df >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x11e0 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x11e1 >+#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 >+#define mmCM3_CM_HDR_MULT_COEF 0x11e2 >+#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2 >+#define mmCM3_CM_MEM_PWR_CTRL 0x11e3 >+#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmCM3_CM_MEM_PWR_STATUS 0x11e4 >+#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmCM3_CM_DEALPHA 0x11e6 >+#define mmCM3_CM_DEALPHA_BASE_IDX 2 >+#define mmCM3_CM_COEF_FORMAT 0x11e7 >+#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_CONTROL 0x11e8 >+#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_OFFSET_R 0x11e9 >+#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_OFFSET_G 0x11ea >+#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_OFFSET_B 0x11eb >+#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_SCALE_R 0x11ec >+#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_SCALE_G_B 0x11ed >+#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_LUT_INDEX 0x11ee >+#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_LUT_DATA 0x11ef >+#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x11f0 >+#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x11f1 >+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x11f2 >+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x11f3 >+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x11f4 >+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x11f5 >+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x11f6 >+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x11f7 >+#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x11f8 >+#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x11f9 >+#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x11fa >+#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x11fb >+#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x11fc >+#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x11fd >+#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x11fe >+#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x11ff >+#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1200 >+#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1201 >+#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1202 >+#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1203 >+#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1204 >+#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1205 >+#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1206 >+#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1207 >+#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1208 >+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1209 >+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x120a >+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x120b >+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x120c >+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x120d >+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x120e >+#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x120f >+#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1210 >+#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1211 >+#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1212 >+#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1213 >+#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1214 >+#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1215 >+#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1216 >+#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1217 >+#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1218 >+#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1219 >+#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x121a >+#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x121b >+#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x121c >+#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x121d >+#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x121e >+#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 >+#define mmCM3_CM_MEM_PWR_CTRL2 0x121f >+#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 >+#define mmCM3_CM_MEM_PWR_STATUS2 0x1220 >+#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_MODE 0x1221 >+#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_INDEX 0x1222 >+#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_DATA 0x1223 >+#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_DATA_30BIT 0x1224 >+#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1225 >+#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1226 >+#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1227 >+#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1228 >+#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 >+#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1229 >+#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 >+#define mmCM3_CM_TEST_DEBUG_INDEX 0x122a >+#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmCM3_CM_TEST_DEBUG_DATA 0x122b >+#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x4994 >+#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 >+#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 >+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x1267 >+#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON14_PERFMON_CNTL 0x1268 >+#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON14_PERFMON_CNTL2 0x1269 >+#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a >+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b >+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON14_PERFMON_HI 0x126c >+#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON14_PERFMON_LOW 0x126d >+#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc0_dispdec >+// base address: 0x0 >+#define mmMPCC0_MPCC_TOP_SEL 0x1271 >+#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2 >+#define mmMPCC0_MPCC_BOT_SEL 0x1272 >+#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2 >+#define mmMPCC0_MPCC_OPP_ID 0x1273 >+#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2 >+#define mmMPCC0_MPCC_CONTROL 0x1274 >+#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2 >+#define mmMPCC0_MPCC_SM_CONTROL 0x1275 >+#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2 >+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1276 >+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 >+#define mmMPCC0_MPCC_TOP_GAIN 0x1277 >+#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 2 >+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x1278 >+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 >+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x1279 >+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 >+#define mmMPCC0_MPCC_BG_R_CR 0x127a >+#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2 >+#define mmMPCC0_MPCC_BG_G_Y 0x127b >+#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2 >+#define mmMPCC0_MPCC_BG_B_CB 0x127c >+#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2 >+#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x127d >+#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmMPCC0_MPCC_STALL_STATUS 0x127e >+#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2 >+#define mmMPCC0_MPCC_STATUS 0x127f >+#define mmMPCC0_MPCC_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc1_dispdec >+// base address: 0x6c >+#define mmMPCC1_MPCC_TOP_SEL 0x128c >+#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2 >+#define mmMPCC1_MPCC_BOT_SEL 0x128d >+#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2 >+#define mmMPCC1_MPCC_OPP_ID 0x128e >+#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2 >+#define mmMPCC1_MPCC_CONTROL 0x128f >+#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2 >+#define mmMPCC1_MPCC_SM_CONTROL 0x1290 >+#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2 >+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1291 >+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 >+#define mmMPCC1_MPCC_TOP_GAIN 0x1292 >+#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 2 >+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x1293 >+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 >+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x1294 >+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 >+#define mmMPCC1_MPCC_BG_R_CR 0x1295 >+#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2 >+#define mmMPCC1_MPCC_BG_G_Y 0x1296 >+#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2 >+#define mmMPCC1_MPCC_BG_B_CB 0x1297 >+#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2 >+#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x1298 >+#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmMPCC1_MPCC_STALL_STATUS 0x1299 >+#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2 >+#define mmMPCC1_MPCC_STATUS 0x129a >+#define mmMPCC1_MPCC_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc2_dispdec >+// base address: 0xd8 >+#define mmMPCC2_MPCC_TOP_SEL 0x12a7 >+#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2 >+#define mmMPCC2_MPCC_BOT_SEL 0x12a8 >+#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2 >+#define mmMPCC2_MPCC_OPP_ID 0x12a9 >+#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2 >+#define mmMPCC2_MPCC_CONTROL 0x12aa >+#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2 >+#define mmMPCC2_MPCC_SM_CONTROL 0x12ab >+#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2 >+#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x12ac >+#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 >+#define mmMPCC2_MPCC_TOP_GAIN 0x12ad >+#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 2 >+#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x12ae >+#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 >+#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x12af >+#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 >+#define mmMPCC2_MPCC_BG_R_CR 0x12b0 >+#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2 >+#define mmMPCC2_MPCC_BG_G_Y 0x12b1 >+#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2 >+#define mmMPCC2_MPCC_BG_B_CB 0x12b2 >+#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2 >+#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x12b3 >+#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmMPCC2_MPCC_STALL_STATUS 0x12b4 >+#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2 >+#define mmMPCC2_MPCC_STATUS 0x12b5 >+#define mmMPCC2_MPCC_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc3_dispdec >+// base address: 0x144 >+#define mmMPCC3_MPCC_TOP_SEL 0x12c2 >+#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2 >+#define mmMPCC3_MPCC_BOT_SEL 0x12c3 >+#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2 >+#define mmMPCC3_MPCC_OPP_ID 0x12c4 >+#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2 >+#define mmMPCC3_MPCC_CONTROL 0x12c5 >+#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2 >+#define mmMPCC3_MPCC_SM_CONTROL 0x12c6 >+#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2 >+#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x12c7 >+#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 >+#define mmMPCC3_MPCC_TOP_GAIN 0x12c8 >+#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 2 >+#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x12c9 >+#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 >+#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x12ca >+#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 >+#define mmMPCC3_MPCC_BG_R_CR 0x12cb >+#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2 >+#define mmMPCC3_MPCC_BG_G_Y 0x12cc >+#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2 >+#define mmMPCC3_MPCC_BG_B_CB 0x12cd >+#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2 >+#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x12ce >+#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmMPCC3_MPCC_STALL_STATUS 0x12cf >+#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2 >+#define mmMPCC3_MPCC_STATUS 0x12d0 >+#define mmMPCC3_MPCC_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc4_dispdec >+// base address: 0x1b0 >+#define mmMPCC4_MPCC_TOP_SEL 0x12dd >+#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 2 >+#define mmMPCC4_MPCC_BOT_SEL 0x12de >+#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 2 >+#define mmMPCC4_MPCC_OPP_ID 0x12df >+#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 2 >+#define mmMPCC4_MPCC_CONTROL 0x12e0 >+#define mmMPCC4_MPCC_CONTROL_BASE_IDX 2 >+#define mmMPCC4_MPCC_SM_CONTROL 0x12e1 >+#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 2 >+#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x12e2 >+#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 >+#define mmMPCC4_MPCC_TOP_GAIN 0x12e3 >+#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 2 >+#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x12e4 >+#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 >+#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x12e5 >+#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 >+#define mmMPCC4_MPCC_BG_R_CR 0x12e6 >+#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 2 >+#define mmMPCC4_MPCC_BG_G_Y 0x12e7 >+#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 2 >+#define mmMPCC4_MPCC_BG_B_CB 0x12e8 >+#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 2 >+#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x12e9 >+#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmMPCC4_MPCC_STALL_STATUS 0x12ea >+#define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX 2 >+#define mmMPCC4_MPCC_STATUS 0x12eb >+#define mmMPCC4_MPCC_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc5_dispdec >+// base address: 0x21c >+#define mmMPCC5_MPCC_TOP_SEL 0x12f8 >+#define mmMPCC5_MPCC_TOP_SEL_BASE_IDX 2 >+#define mmMPCC5_MPCC_BOT_SEL 0x12f9 >+#define mmMPCC5_MPCC_BOT_SEL_BASE_IDX 2 >+#define mmMPCC5_MPCC_OPP_ID 0x12fa >+#define mmMPCC5_MPCC_OPP_ID_BASE_IDX 2 >+#define mmMPCC5_MPCC_CONTROL 0x12fb >+#define mmMPCC5_MPCC_CONTROL_BASE_IDX 2 >+#define mmMPCC5_MPCC_SM_CONTROL 0x12fc >+#define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX 2 >+#define mmMPCC5_MPCC_UPDATE_LOCK_SEL 0x12fd >+#define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 >+#define mmMPCC5_MPCC_TOP_GAIN 0x12fe >+#define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX 2 >+#define mmMPCC5_MPCC_BOT_GAIN_INSIDE 0x12ff >+#define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 >+#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE 0x1300 >+#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 >+#define mmMPCC5_MPCC_BG_R_CR 0x1301 >+#define mmMPCC5_MPCC_BG_R_CR_BASE_IDX 2 >+#define mmMPCC5_MPCC_BG_G_Y 0x1302 >+#define mmMPCC5_MPCC_BG_G_Y_BASE_IDX 2 >+#define mmMPCC5_MPCC_BG_B_CB 0x1303 >+#define mmMPCC5_MPCC_BG_B_CB_BASE_IDX 2 >+#define mmMPCC5_MPCC_MEM_PWR_CTRL 0x1304 >+#define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmMPCC5_MPCC_STALL_STATUS 0x1305 >+#define mmMPCC5_MPCC_STALL_STATUS_BASE_IDX 2 >+#define mmMPCC5_MPCC_STATUS 0x1306 >+#define mmMPCC5_MPCC_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc6_dispdec >+// base address: 0x288 >+#define mmMPCC6_MPCC_TOP_SEL 0x1313 >+#define mmMPCC6_MPCC_TOP_SEL_BASE_IDX 2 >+#define mmMPCC6_MPCC_BOT_SEL 0x1314 >+#define mmMPCC6_MPCC_BOT_SEL_BASE_IDX 2 >+#define mmMPCC6_MPCC_OPP_ID 0x1315 >+#define mmMPCC6_MPCC_OPP_ID_BASE_IDX 2 >+#define mmMPCC6_MPCC_CONTROL 0x1316 >+#define mmMPCC6_MPCC_CONTROL_BASE_IDX 2 >+#define mmMPCC6_MPCC_SM_CONTROL 0x1317 >+#define mmMPCC6_MPCC_SM_CONTROL_BASE_IDX 2 >+#define mmMPCC6_MPCC_UPDATE_LOCK_SEL 0x1318 >+#define mmMPCC6_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 >+#define mmMPCC6_MPCC_TOP_GAIN 0x1319 >+#define mmMPCC6_MPCC_TOP_GAIN_BASE_IDX 2 >+#define mmMPCC6_MPCC_BOT_GAIN_INSIDE 0x131a >+#define mmMPCC6_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 >+#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE 0x131b >+#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 >+#define mmMPCC6_MPCC_BG_R_CR 0x131c >+#define mmMPCC6_MPCC_BG_R_CR_BASE_IDX 2 >+#define mmMPCC6_MPCC_BG_G_Y 0x131d >+#define mmMPCC6_MPCC_BG_G_Y_BASE_IDX 2 >+#define mmMPCC6_MPCC_BG_B_CB 0x131e >+#define mmMPCC6_MPCC_BG_B_CB_BASE_IDX 2 >+#define mmMPCC6_MPCC_MEM_PWR_CTRL 0x131f >+#define mmMPCC6_MPCC_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmMPCC6_MPCC_STALL_STATUS 0x1320 >+#define mmMPCC6_MPCC_STALL_STATUS_BASE_IDX 2 >+#define mmMPCC6_MPCC_STATUS 0x1321 >+#define mmMPCC6_MPCC_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc7_dispdec >+// base address: 0x2f4 >+#define mmMPCC7_MPCC_TOP_SEL 0x132e >+#define mmMPCC7_MPCC_TOP_SEL_BASE_IDX 2 >+#define mmMPCC7_MPCC_BOT_SEL 0x132f >+#define mmMPCC7_MPCC_BOT_SEL_BASE_IDX 2 >+#define mmMPCC7_MPCC_OPP_ID 0x1330 >+#define mmMPCC7_MPCC_OPP_ID_BASE_IDX 2 >+#define mmMPCC7_MPCC_CONTROL 0x1331 >+#define mmMPCC7_MPCC_CONTROL_BASE_IDX 2 >+#define mmMPCC7_MPCC_SM_CONTROL 0x1332 >+#define mmMPCC7_MPCC_SM_CONTROL_BASE_IDX 2 >+#define mmMPCC7_MPCC_UPDATE_LOCK_SEL 0x1333 >+#define mmMPCC7_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 >+#define mmMPCC7_MPCC_TOP_GAIN 0x1334 >+#define mmMPCC7_MPCC_TOP_GAIN_BASE_IDX 2 >+#define mmMPCC7_MPCC_BOT_GAIN_INSIDE 0x1335 >+#define mmMPCC7_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 >+#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE 0x1336 >+#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 >+#define mmMPCC7_MPCC_BG_R_CR 0x1337 >+#define mmMPCC7_MPCC_BG_R_CR_BASE_IDX 2 >+#define mmMPCC7_MPCC_BG_G_Y 0x1338 >+#define mmMPCC7_MPCC_BG_G_Y_BASE_IDX 2 >+#define mmMPCC7_MPCC_BG_B_CB 0x1339 >+#define mmMPCC7_MPCC_BG_B_CB_BASE_IDX 2 >+#define mmMPCC7_MPCC_MEM_PWR_CTRL 0x133a >+#define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmMPCC7_MPCC_STALL_STATUS 0x133b >+#define mmMPCC7_MPCC_STALL_STATUS_BASE_IDX 2 >+#define mmMPCC7_MPCC_STATUS 0x133c >+#define mmMPCC7_MPCC_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec >+// base address: 0x0 >+#define mmMPC_CLOCK_CONTROL 0x1349 >+#define mmMPC_CLOCK_CONTROL_BASE_IDX 2 >+#define mmMPC_SOFT_RESET 0x134a >+#define mmMPC_SOFT_RESET_BASE_IDX 2 >+#define mmMPC_CRC_CTRL 0x134b >+#define mmMPC_CRC_CTRL_BASE_IDX 2 >+#define mmMPC_CRC_SEL_CONTROL 0x134c >+#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2 >+#define mmMPC_CRC_RESULT_AR 0x134d >+#define mmMPC_CRC_RESULT_AR_BASE_IDX 2 >+#define mmMPC_CRC_RESULT_GB 0x134e >+#define mmMPC_CRC_RESULT_GB_BASE_IDX 2 >+#define mmMPC_CRC_RESULT_C 0x134f >+#define mmMPC_CRC_RESULT_C_BASE_IDX 2 >+#define mmMPC_PERFMON_EVENT_CTRL 0x1352 >+#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2 >+#define mmMPC_BYPASS_BG_AR 0x1353 >+#define mmMPC_BYPASS_BG_AR_BASE_IDX 2 >+#define mmMPC_BYPASS_BG_GB 0x1354 >+#define mmMPC_BYPASS_BG_GB_BASE_IDX 2 >+#define mmMPC_STALL_GRACE_WINDOW 0x1355 >+#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2 >+#define mmMPC_HOST_READ_CONTROL 0x1356 >+#define mmMPC_HOST_READ_CONTROL_BASE_IDX 2 >+#define mmMPC_PENDING_TAKEN_STATUS_REG1 0x1357 >+#define mmMPC_PENDING_TAKEN_STATUS_REG1_BASE_IDX 2 >+#define mmMPC_PENDING_TAKEN_STATUS_REG3 0x1359 >+#define mmMPC_PENDING_TAKEN_STATUS_REG3_BASE_IDX 2 >+#define mmMPC_UPDATE_ACK_REG5 0x135b >+#define mmMPC_UPDATE_ACK_REG5_BASE_IDX 2 >+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x135d >+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 2 >+#define mmADR_CFG_VUPDATE_LOCK_SET0 0x135e >+#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2 >+#define mmADR_VUPDATE_LOCK_SET0 0x135f >+#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2 >+#define mmCFG_VUPDATE_LOCK_SET0 0x1360 >+#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 2 >+#define mmCUR_VUPDATE_LOCK_SET0 0x1361 >+#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 2 >+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x1362 >+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 2 >+#define mmADR_CFG_VUPDATE_LOCK_SET1 0x1363 >+#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2 >+#define mmADR_VUPDATE_LOCK_SET1 0x1364 >+#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2 >+#define mmCFG_VUPDATE_LOCK_SET1 0x1365 >+#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 2 >+#define mmCUR_VUPDATE_LOCK_SET1 0x1366 >+#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 2 >+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x1367 >+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 2 >+#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1368 >+#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2 >+#define mmADR_VUPDATE_LOCK_SET2 0x1369 >+#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2 >+#define mmCFG_VUPDATE_LOCK_SET2 0x136a >+#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 2 >+#define mmCUR_VUPDATE_LOCK_SET2 0x136b >+#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 2 >+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x136c >+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 2 >+#define mmADR_CFG_VUPDATE_LOCK_SET3 0x136d >+#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2 >+#define mmADR_VUPDATE_LOCK_SET3 0x136e >+#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2 >+#define mmCFG_VUPDATE_LOCK_SET3 0x136f >+#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 2 >+#define mmCUR_VUPDATE_LOCK_SET3 0x1370 >+#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 2 >+#define mmMPC_OUT0_MUX 0x1385 >+#define mmMPC_OUT0_MUX_BASE_IDX 2 >+#define mmMPC_OUT0_DENORM_CONTROL 0x1386 >+#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 2 >+#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x1387 >+#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 2 >+#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x1388 >+#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 2 >+#define mmMPC_OUT1_MUX 0x1389 >+#define mmMPC_OUT1_MUX_BASE_IDX 2 >+#define mmMPC_OUT1_DENORM_CONTROL 0x138a >+#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 2 >+#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x138b >+#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 2 >+#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x138c >+#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 2 >+#define mmMPC_OUT2_MUX 0x138d >+#define mmMPC_OUT2_MUX_BASE_IDX 2 >+#define mmMPC_OUT2_DENORM_CONTROL 0x138e >+#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 2 >+#define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x138f >+#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 2 >+#define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x1390 >+#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 2 >+#define mmMPC_OUT3_MUX 0x1391 >+#define mmMPC_OUT3_MUX_BASE_IDX 2 >+#define mmMPC_OUT3_DENORM_CONTROL 0x1392 >+#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 2 >+#define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x1393 >+#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 2 >+#define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x1394 >+#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec >+// base address: 0x0 >+#define mmMPCC_OGAM0_MPCC_OGAM_MODE 0x13ae >+#define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x13af >+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x13b0 >+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL 0x13b1 >+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x13b2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x13b3 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x13b4 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13b5 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13b6 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13b7 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x13b8 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x13b9 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x13ba >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x13bb >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x13bc >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x13bd >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x13be >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x13bf >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x13c0 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x13c1 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x13c2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x13c3 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x13c4 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x13c5 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x13c6 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x13c7 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x13c8 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x13c9 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x13ca >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x13cb >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x13cc >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x13cd >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x13ce >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x13cf >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x13d0 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x13d1 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x13d2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x13d3 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x13d4 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x13d5 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x13d6 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x13d7 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x13d8 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x13d9 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x13da >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x13db >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x13dc >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x13dd >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x13de >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x13df >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x13e0 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x13e1 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x13e2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x13e3 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x13e4 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x13e5 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x13e6 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x13e7 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x13e8 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x13e9 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x13ea >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x13eb >+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec >+// base address: 0x104 >+#define mmMPCC_OGAM1_MPCC_OGAM_MODE 0x13ef >+#define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x13f0 >+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x13f1 >+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL 0x13f2 >+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x13f3 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x13f4 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x13f5 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13f6 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13f7 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13f8 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x13f9 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x13fa >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x13fb >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x13fc >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x13fd >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x13fe >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x13ff >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x1400 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x1401 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x1402 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x1403 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x1404 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x1405 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x1406 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x1407 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x1408 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x1409 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x140a >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x140b >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x140c >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x140d >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x140e >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x140f >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x1410 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x1411 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x1412 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1413 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1414 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1415 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x1416 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x1417 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x1418 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x1419 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x141a >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x141b >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x141c >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x141d >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x141e >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x141f >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x1420 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x1421 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x1422 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x1423 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x1424 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x1425 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x1426 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x1427 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x1428 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x1429 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x142a >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x142b >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x142c >+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec >+// base address: 0x208 >+#define mmMPCC_OGAM2_MPCC_OGAM_MODE 0x1430 >+#define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x1431 >+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x1432 >+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL 0x1433 >+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x1434 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x1435 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x1436 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1437 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1438 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x1439 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x143a >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x143b >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x143c >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x143d >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x143e >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x143f >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x1440 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x1441 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x1442 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x1443 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x1444 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x1445 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x1446 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x1447 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x1448 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x1449 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x144a >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x144b >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x144c >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x144d >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x144e >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x144f >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x1450 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x1451 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x1452 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x1453 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1454 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1455 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1456 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x1457 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x1458 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x1459 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x145a >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x145b >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x145c >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x145d >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x145e >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x145f >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x1460 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x1461 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x1462 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x1463 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x1464 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x1465 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x1466 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x1467 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x1468 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x1469 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x146a >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x146b >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x146c >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x146d >+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec >+// base address: 0x30c >+#define mmMPCC_OGAM3_MPCC_OGAM_MODE 0x1471 >+#define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x1472 >+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x1473 >+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL 0x1474 >+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x1475 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x1476 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x1477 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1478 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1479 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x147a >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x147b >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x147c >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x147d >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x147e >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x147f >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x1480 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x1481 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x1482 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x1483 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x1484 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x1485 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x1486 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x1487 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x1488 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x1489 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x148a >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x148b >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x148c >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x148d >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x148e >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x148f >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x1490 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x1491 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x1492 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x1493 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x1494 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1495 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1496 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1497 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x1498 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x1499 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x149a >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x149b >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x149c >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x149d >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x149e >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x149f >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x14a0 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x14a1 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x14a2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x14a3 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x14a4 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x14a5 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x14a6 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x14a7 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x14a8 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x14a9 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x14aa >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x14ab >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x14ac >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x14ad >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x14ae >+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec >+// base address: 0x410 >+#define mmMPCC_OGAM4_MPCC_OGAM_MODE 0x14b2 >+#define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x14b3 >+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x14b4 >+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL 0x14b5 >+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x14b6 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x14b7 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x14b8 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14b9 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14ba >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14bb >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x14bc >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x14bd >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x14be >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x14bf >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x14c0 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x14c1 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x14c2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x14c3 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x14c4 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x14c5 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x14c6 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x14c7 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x14c8 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x14c9 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x14ca >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x14cb >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x14cc >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x14cd >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x14ce >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x14cf >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x14d0 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x14d1 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x14d2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x14d3 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x14d4 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x14d5 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x14d6 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x14d7 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x14d8 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x14d9 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x14da >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x14db >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x14dc >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x14dd >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x14de >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x14df >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x14e0 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x14e1 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x14e2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x14e3 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x14e4 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x14e5 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x14e6 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x14e7 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x14e8 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x14e9 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x14ea >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x14eb >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x14ec >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x14ed >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x14ee >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x14ef >+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec >+// base address: 0x514 >+#define mmMPCC_OGAM5_MPCC_OGAM_MODE 0x14f3 >+#define mmMPCC_OGAM5_MPCC_OGAM_MODE_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX 0x14f4 >+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA 0x14f5 >+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL 0x14f6 >+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B 0x14f7 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G 0x14f8 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R 0x14f9 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14fa >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14fb >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14fc >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B 0x14fd >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B 0x14fe >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G 0x14ff >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G 0x1500 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R 0x1501 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R 0x1502 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 0x1503 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 0x1504 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 0x1505 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 0x1506 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 0x1507 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 0x1508 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 0x1509 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 0x150a >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 0x150b >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 0x150c >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 0x150d >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 0x150e >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 0x150f >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 0x1510 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 0x1511 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 0x1512 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 0x1513 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B 0x1514 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G 0x1515 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R 0x1516 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1517 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1518 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1519 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B 0x151a >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B 0x151b >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G 0x151c >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G 0x151d >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R 0x151e >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R 0x151f >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 0x1520 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 0x1521 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 0x1522 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 0x1523 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 0x1524 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 0x1525 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 0x1526 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 0x1527 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 0x1528 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 0x1529 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 0x152a >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 0x152b >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 0x152c >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 0x152d >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 0x152e >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 0x152f >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 0x1530 >+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec >+// base address: 0x618 >+#define mmMPCC_OGAM6_MPCC_OGAM_MODE 0x1534 >+#define mmMPCC_OGAM6_MPCC_OGAM_MODE_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX 0x1535 >+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA 0x1536 >+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL 0x1537 >+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B 0x1538 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G 0x1539 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R 0x153a >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x153b >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x153c >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x153d >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B 0x153e >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B 0x153f >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G 0x1540 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G 0x1541 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R 0x1542 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R 0x1543 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1 0x1544 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3 0x1545 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5 0x1546 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7 0x1547 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9 0x1548 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11 0x1549 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13 0x154a >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15 0x154b >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17 0x154c >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19 0x154d >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21 0x154e >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23 0x154f >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25 0x1550 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27 0x1551 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29 0x1552 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31 0x1553 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33 0x1554 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B 0x1555 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G 0x1556 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R 0x1557 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1558 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1559 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x155a >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B 0x155b >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B 0x155c >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G 0x155d >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G 0x155e >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R 0x155f >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R 0x1560 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1 0x1561 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3 0x1562 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5 0x1563 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7 0x1564 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9 0x1565 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11 0x1566 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13 0x1567 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15 0x1568 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17 0x1569 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19 0x156a >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21 0x156b >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23 0x156c >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25 0x156d >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27 0x156e >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29 0x156f >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31 0x1570 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33 0x1571 >+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec >+// base address: 0x71c >+#define mmMPCC_OGAM7_MPCC_OGAM_MODE 0x1575 >+#define mmMPCC_OGAM7_MPCC_OGAM_MODE_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX 0x1576 >+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA 0x1577 >+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL 0x1578 >+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B 0x1579 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G 0x157a >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R 0x157b >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x157c >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x157d >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x157e >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B 0x157f >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B 0x1580 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G 0x1581 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G 0x1582 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R 0x1583 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R 0x1584 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1 0x1585 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3 0x1586 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5 0x1587 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7 0x1588 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9 0x1589 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11 0x158a >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13 0x158b >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15 0x158c >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17 0x158d >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19 0x158e >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21 0x158f >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23 0x1590 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25 0x1591 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27 0x1592 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29 0x1593 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31 0x1594 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33 0x1595 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B 0x1596 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G 0x1597 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R 0x1598 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1599 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x159a >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x159b >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B 0x159c >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B 0x159d >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G 0x159e >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G 0x159f >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R 0x15a0 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R 0x15a1 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1 0x15a2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3 0x15a3 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5 0x15a4 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7 0x15a5 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9 0x15a6 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11 0x15a7 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13 0x15a8 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15 0x15a9 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17 0x15aa >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19 0x15ab >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21 0x15ac >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23 0x15ad >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25 0x15ae >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27 0x15af >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29 0x15b0 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31 0x15b1 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33 0x15b2 >+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec >+// base address: 0x0 >+#define mmMPC_OUT_CSC_COEF_FORMAT 0x15b6 >+#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_MODE 0x15b7 >+#define mmMPC_OUT0_CSC_MODE_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C11_C12_A 0x15b8 >+#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C13_C14_A 0x15b9 >+#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C21_C22_A 0x15ba >+#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C23_C24_A 0x15bb >+#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C31_C32_A 0x15bc >+#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C33_C34_A 0x15bd >+#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C11_C12_B 0x15be >+#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C13_C14_B 0x15bf >+#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C21_C22_B 0x15c0 >+#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C23_C24_B 0x15c1 >+#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C31_C32_B 0x15c2 >+#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 2 >+#define mmMPC_OUT0_CSC_C33_C34_B 0x15c3 >+#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_MODE 0x15c4 >+#define mmMPC_OUT1_CSC_MODE_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C11_C12_A 0x15c5 >+#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C13_C14_A 0x15c6 >+#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C21_C22_A 0x15c7 >+#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C23_C24_A 0x15c8 >+#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C31_C32_A 0x15c9 >+#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C33_C34_A 0x15ca >+#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C11_C12_B 0x15cb >+#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C13_C14_B 0x15cc >+#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C21_C22_B 0x15cd >+#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C23_C24_B 0x15ce >+#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C31_C32_B 0x15cf >+#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 2 >+#define mmMPC_OUT1_CSC_C33_C34_B 0x15d0 >+#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_MODE 0x15d1 >+#define mmMPC_OUT2_CSC_MODE_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C11_C12_A 0x15d2 >+#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C13_C14_A 0x15d3 >+#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C21_C22_A 0x15d4 >+#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C23_C24_A 0x15d5 >+#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C31_C32_A 0x15d6 >+#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C33_C34_A 0x15d7 >+#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C11_C12_B 0x15d8 >+#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C13_C14_B 0x15d9 >+#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C21_C22_B 0x15da >+#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C23_C24_B 0x15db >+#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C31_C32_B 0x15dc >+#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 2 >+#define mmMPC_OUT2_CSC_C33_C34_B 0x15dd >+#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_MODE 0x15de >+#define mmMPC_OUT3_CSC_MODE_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C11_C12_A 0x15df >+#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C13_C14_A 0x15e0 >+#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C21_C22_A 0x15e1 >+#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C23_C24_A 0x15e2 >+#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C31_C32_A 0x15e3 >+#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C33_C34_A 0x15e4 >+#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C11_C12_B 0x15e5 >+#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C13_C14_B 0x15e6 >+#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C21_C22_B 0x15e7 >+#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C23_C24_B 0x15e8 >+#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C31_C32_B 0x15e9 >+#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 2 >+#define mmMPC_OUT3_CSC_C33_C34_B 0x15ea >+#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec >+// base address: 0x5964 >+#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x1659 >+#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x165a >+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x165b >+#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON15_PERFMON_CNTL 0x165c >+#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON15_PERFMON_CNTL2 0x165d >+#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x165e >+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x165f >+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON15_PERFMON_HI 0x1660 >+#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON15_PERFMON_LOW 0x1661 >+#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_abm0_dispdec >+// base address: 0x0 >+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0 >+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2 >+#define mmBL1_PWM_USER_LEVEL 0x17b1 >+#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2 >+#define mmBL1_PWM_TARGET_ABM_LEVEL 0x17b2 >+#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2 >+#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x17b3 >+#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2 >+#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x17b4 >+#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2 >+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5 >+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2 >+#define mmBL1_PWM_ABM_CNTL 0x17b6 >+#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2 >+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7 >+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2 >+#define mmBL1_PWM_GRP2_REG_LOCK 0x17b8 >+#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2 >+#define mmDC_ABM1_CNTL 0x17b9 >+#define mmDC_ABM1_CNTL_BASE_IDX 2 >+#define mmDC_ABM1_IPCSC_COEFF_SEL 0x17ba >+#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2 >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2 >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2 >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2 >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x17be >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2 >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf >+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2 >+#define mmDC_ABM1_ACE_THRES_12 0x17c0 >+#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2 >+#define mmDC_ABM1_ACE_THRES_34 0x17c1 >+#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2 >+#define mmDC_ABM1_ACE_CNTL_MISC 0x17c2 >+#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2 >+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4 >+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2 >+#define mmDC_ABM1_HG_MISC_CTRL 0x17c5 >+#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2 >+#define mmDC_ABM1_LS_SUM_OF_LUMA 0x17c6 >+#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2 >+#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x17c7 >+#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2 >+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8 >+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2 >+#define mmDC_ABM1_LS_PIXEL_COUNT 0x17c9 >+#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2 >+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca >+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2 >+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb >+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2 >+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc >+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2 >+#define mmDC_ABM1_HG_SAMPLE_RATE 0x17cd >+#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2 >+#define mmDC_ABM1_LS_SAMPLE_RATE 0x17ce >+#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2 >+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf >+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2 >+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0 >+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2 >+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1 >+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2 >+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2 >+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2 >+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3 >+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_1 0x17d4 >+#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_2 0x17d5 >+#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_3 0x17d6 >+#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_4 0x17d7 >+#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_5 0x17d8 >+#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_6 0x17d9 >+#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_7 0x17da >+#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_8 0x17db >+#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_9 0x17dc >+#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_10 0x17dd >+#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_11 0x17de >+#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_12 0x17df >+#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_13 0x17e0 >+#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_14 0x17e1 >+#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_15 0x17e2 >+#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_16 0x17e3 >+#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_17 0x17e4 >+#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_18 0x17e5 >+#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_19 0x17e6 >+#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_20 0x17e7 >+#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_21 0x17e8 >+#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_22 0x17e9 >+#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_23 0x17ea >+#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2 >+#define mmDC_ABM1_HG_RESULT_24 0x17eb >+#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2 >+#define mmDC_ABM1_BL_MASTER_LOCK 0x17ec >+#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_fmt0_dispdec >+// base address: 0x0 >+#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c >+#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 >+#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d >+#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 >+#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e >+#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 >+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f >+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 >+#define mmFMT0_FMT_CONTROL 0x1840 >+#define mmFMT0_FMT_CONTROL_BASE_IDX 2 >+#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 >+#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 >+#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 >+#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 >+#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 >+#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 >+#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 >+#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 >+#define mmFMT0_FMT_CLAMP_CNTL 0x1845 >+#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 >+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 >+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 >+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 >+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 >+#define mmFMT0_FMT_422_CONTROL 0x1849 >+#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dpg0_dispdec >+// base address: 0x0 >+#define mmDPG0_DPG_CONTROL 0x1854 >+#define mmDPG0_DPG_CONTROL_BASE_IDX 2 >+#define mmDPG0_DPG_RAMP_CONTROL 0x1855 >+#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 >+#define mmDPG0_DPG_DIMENSIONS 0x1856 >+#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2 >+#define mmDPG0_DPG_COLOUR_R_CR 0x1857 >+#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 >+#define mmDPG0_DPG_COLOUR_G_Y 0x1858 >+#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 >+#define mmDPG0_DPG_COLOUR_B_CB 0x1859 >+#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 >+#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a >+#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 >+#define mmDPG0_DPG_STATUS 0x185b >+#define mmDPG0_DPG_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_oppbuf0_dispdec >+// base address: 0x0 >+#define mmOPPBUF0_OPPBUF_CONTROL 0x1884 >+#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 >+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 >+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 >+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 >+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 >+#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889 >+#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe0_dispdec >+// base address: 0x0 >+#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c >+#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec >+// base address: 0x0 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 >+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_fmt1_dispdec >+// base address: 0x168 >+#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 >+#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 >+#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 >+#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 >+#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 >+#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 >+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 >+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 >+#define mmFMT1_FMT_CONTROL 0x189a >+#define mmFMT1_FMT_CONTROL_BASE_IDX 2 >+#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b >+#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 >+#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c >+#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 >+#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d >+#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 >+#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e >+#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 >+#define mmFMT1_FMT_CLAMP_CNTL 0x189f >+#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 >+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 >+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 >+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 >+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 >+#define mmFMT1_FMT_422_CONTROL 0x18a3 >+#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dpg1_dispdec >+// base address: 0x168 >+#define mmDPG1_DPG_CONTROL 0x18ae >+#define mmDPG1_DPG_CONTROL_BASE_IDX 2 >+#define mmDPG1_DPG_RAMP_CONTROL 0x18af >+#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 >+#define mmDPG1_DPG_DIMENSIONS 0x18b0 >+#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2 >+#define mmDPG1_DPG_COLOUR_R_CR 0x18b1 >+#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 >+#define mmDPG1_DPG_COLOUR_G_Y 0x18b2 >+#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 >+#define mmDPG1_DPG_COLOUR_B_CB 0x18b3 >+#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 >+#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4 >+#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 >+#define mmDPG1_DPG_STATUS 0x18b5 >+#define mmDPG1_DPG_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_oppbuf1_dispdec >+// base address: 0x168 >+#define mmOPPBUF1_OPPBUF_CONTROL 0x18de >+#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 >+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df >+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 >+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 >+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 >+#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3 >+#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe1_dispdec >+// base address: 0x168 >+#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 >+#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec >+// base address: 0x168 >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef >+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_fmt2_dispdec >+// base address: 0x2d0 >+#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 >+#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 >+#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 >+#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 >+#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 >+#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 >+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 >+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 >+#define mmFMT2_FMT_CONTROL 0x18f4 >+#define mmFMT2_FMT_CONTROL_BASE_IDX 2 >+#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 >+#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 >+#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 >+#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 >+#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 >+#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 >+#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 >+#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 >+#define mmFMT2_FMT_CLAMP_CNTL 0x18f9 >+#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 >+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa >+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 >+#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb >+#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 >+#define mmFMT2_FMT_422_CONTROL 0x18fd >+#define mmFMT2_FMT_422_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dpg2_dispdec >+// base address: 0x2d0 >+#define mmDPG2_DPG_CONTROL 0x1908 >+#define mmDPG2_DPG_CONTROL_BASE_IDX 2 >+#define mmDPG2_DPG_RAMP_CONTROL 0x1909 >+#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 >+#define mmDPG2_DPG_DIMENSIONS 0x190a >+#define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2 >+#define mmDPG2_DPG_COLOUR_R_CR 0x190b >+#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 >+#define mmDPG2_DPG_COLOUR_G_Y 0x190c >+#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 >+#define mmDPG2_DPG_COLOUR_B_CB 0x190d >+#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 >+#define mmDPG2_DPG_OFFSET_SEGMENT 0x190e >+#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 >+#define mmDPG2_DPG_STATUS 0x190f >+#define mmDPG2_DPG_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_oppbuf2_dispdec >+// base address: 0x2d0 >+#define mmOPPBUF2_OPPBUF_CONTROL 0x1938 >+#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 >+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 >+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 >+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a >+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 >+#define mmOPPBUF2_OPPBUF_CONTROL1 0x193d >+#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe2_dispdec >+// base address: 0x2d0 >+#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 >+#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec >+// base address: 0x2d0 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 >+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_fmt3_dispdec >+// base address: 0x438 >+#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a >+#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 >+#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b >+#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 >+#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c >+#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 >+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d >+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 >+#define mmFMT3_FMT_CONTROL 0x194e >+#define mmFMT3_FMT_CONTROL_BASE_IDX 2 >+#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f >+#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 >+#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950 >+#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 >+#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951 >+#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 >+#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952 >+#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 >+#define mmFMT3_FMT_CLAMP_CNTL 0x1953 >+#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 >+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 >+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 >+#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 >+#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 >+#define mmFMT3_FMT_422_CONTROL 0x1957 >+#define mmFMT3_FMT_422_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dpg3_dispdec >+// base address: 0x438 >+#define mmDPG3_DPG_CONTROL 0x1962 >+#define mmDPG3_DPG_CONTROL_BASE_IDX 2 >+#define mmDPG3_DPG_RAMP_CONTROL 0x1963 >+#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 >+#define mmDPG3_DPG_DIMENSIONS 0x1964 >+#define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2 >+#define mmDPG3_DPG_COLOUR_R_CR 0x1965 >+#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 >+#define mmDPG3_DPG_COLOUR_G_Y 0x1966 >+#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 >+#define mmDPG3_DPG_COLOUR_B_CB 0x1967 >+#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 >+#define mmDPG3_DPG_OFFSET_SEGMENT 0x1968 >+#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 >+#define mmDPG3_DPG_STATUS 0x1969 >+#define mmDPG3_DPG_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_oppbuf3_dispdec >+// base address: 0x438 >+#define mmOPPBUF3_OPPBUF_CONTROL 0x1992 >+#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 >+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 >+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 >+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 >+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 >+#define mmOPPBUF3_OPPBUF_CONTROL1 0x1997 >+#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe3_dispdec >+// base address: 0x438 >+#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a >+#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec >+// base address: 0x438 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 >+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_fmt4_dispdec >+// base address: 0x5a0 >+#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4 >+#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 >+#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5 >+#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 >+#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6 >+#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 >+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7 >+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 >+#define mmFMT4_FMT_CONTROL 0x19a8 >+#define mmFMT4_FMT_CONTROL_BASE_IDX 2 >+#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9 >+#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 >+#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa >+#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 >+#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab >+#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 >+#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac >+#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 >+#define mmFMT4_FMT_CLAMP_CNTL 0x19ad >+#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2 >+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae >+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 >+#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af >+#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 >+#define mmFMT4_FMT_422_CONTROL 0x19b1 >+#define mmFMT4_FMT_422_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dpg4_dispdec >+// base address: 0x5a0 >+#define mmDPG4_DPG_CONTROL 0x19bc >+#define mmDPG4_DPG_CONTROL_BASE_IDX 2 >+#define mmDPG4_DPG_RAMP_CONTROL 0x19bd >+#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2 >+#define mmDPG4_DPG_DIMENSIONS 0x19be >+#define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2 >+#define mmDPG4_DPG_COLOUR_R_CR 0x19bf >+#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2 >+#define mmDPG4_DPG_COLOUR_G_Y 0x19c0 >+#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2 >+#define mmDPG4_DPG_COLOUR_B_CB 0x19c1 >+#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2 >+#define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2 >+#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2 >+#define mmDPG4_DPG_STATUS 0x19c3 >+#define mmDPG4_DPG_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_oppbuf4_dispdec >+// base address: 0x5a0 >+#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec >+#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2 >+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed >+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 >+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee >+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 >+#define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1 >+#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe4_dispdec >+// base address: 0x5a0 >+#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4 >+#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec >+// base address: 0x5a0 >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9 >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2 >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd >+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_fmt5_dispdec >+// base address: 0x708 >+#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe >+#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 >+#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff >+#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 >+#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00 >+#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 >+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01 >+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 >+#define mmFMT5_FMT_CONTROL 0x1a02 >+#define mmFMT5_FMT_CONTROL_BASE_IDX 2 >+#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03 >+#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 >+#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04 >+#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 >+#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05 >+#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 >+#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06 >+#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 >+#define mmFMT5_FMT_CLAMP_CNTL 0x1a07 >+#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2 >+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a08 >+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 >+#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a09 >+#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 >+#define mmFMT5_FMT_422_CONTROL 0x1a0b >+#define mmFMT5_FMT_422_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dpg5_dispdec >+// base address: 0x708 >+#define mmDPG5_DPG_CONTROL 0x1a16 >+#define mmDPG5_DPG_CONTROL_BASE_IDX 2 >+#define mmDPG5_DPG_RAMP_CONTROL 0x1a17 >+#define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX 2 >+#define mmDPG5_DPG_DIMENSIONS 0x1a18 >+#define mmDPG5_DPG_DIMENSIONS_BASE_IDX 2 >+#define mmDPG5_DPG_COLOUR_R_CR 0x1a19 >+#define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX 2 >+#define mmDPG5_DPG_COLOUR_G_Y 0x1a1a >+#define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX 2 >+#define mmDPG5_DPG_COLOUR_B_CB 0x1a1b >+#define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX 2 >+#define mmDPG5_DPG_OFFSET_SEGMENT 0x1a1c >+#define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX 2 >+#define mmDPG5_DPG_STATUS 0x1a1d >+#define mmDPG5_DPG_STATUS_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_oppbuf5_dispdec >+// base address: 0x708 >+#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46 >+#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2 >+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47 >+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 >+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48 >+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 >+#define mmOPPBUF5_OPPBUF_CONTROL1 0x1a4b >+#define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe5_dispdec >+// base address: 0x708 >+#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e >+#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec >+// base address: 0x708 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57 >+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_top_dispdec >+// base address: 0x0 >+#define mmOPP_TOP_CLK_CONTROL 0x1a5e >+#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dscrm0_dispdec >+// base address: 0x0 >+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 >+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dscrm1_dispdec >+// base address: 0x4 >+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 >+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dscrm2_dispdec >+// base address: 0x8 >+#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 >+#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dscrm3_dispdec >+// base address: 0xc >+#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 >+#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dscrm4_dispdec >+// base address: 0x10 >+#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68 >+#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_dscrm5_dispdec >+// base address: 0x14 >+#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG 0x1a69 >+#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec >+// base address: 0x6af8 >+#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe >+#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf >+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 >+#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON16_PERFMON_CNTL 0x1ac1 >+#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON16_PERFMON_CNTL2 0x1ac2 >+#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 >+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 >+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON16_PERFMON_HI 0x1ac5 >+#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON16_PERFMON_LOW 0x1ac6 >+#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_odm0_dispdec >+// base address: 0x0 >+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca >+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 >+#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb >+#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 >+#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc >+#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 >+#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd >+#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace >+#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 >+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf >+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 >+#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0 >+#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 >+#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 >+#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_odm1_dispdec >+// base address: 0x40 >+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada >+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 >+#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb >+#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 >+#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc >+#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 >+#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add >+#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade >+#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 >+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf >+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 >+#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0 >+#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 >+#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 >+#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_odm2_dispdec >+// base address: 0x80 >+#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea >+#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 >+#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb >+#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 >+#define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec >+#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 >+#define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed >+#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmODM2_OPTC_WIDTH_CONTROL 0x1aee >+#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 >+#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef >+#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 >+#define mmODM2_OPTC_MEMORY_CONFIG 0x1af0 >+#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 >+#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 >+#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_odm3_dispdec >+// base address: 0xc0 >+#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa >+#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 >+#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb >+#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 >+#define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc >+#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 >+#define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd >+#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmODM3_OPTC_WIDTH_CONTROL 0x1afe >+#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 >+#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff >+#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 >+#define mmODM3_OPTC_MEMORY_CONFIG 0x1b00 >+#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 >+#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 >+#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_odm4_dispdec >+// base address: 0x100 >+#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a >+#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 >+#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b >+#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 >+#define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c >+#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 >+#define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d >+#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e >+#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2 >+#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f >+#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 >+#define mmODM4_OPTC_MEMORY_CONFIG 0x1b10 >+#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2 >+#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11 >+#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_odm5_dispdec >+// base address: 0x140 >+#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a >+#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 >+#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b >+#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 >+#define mmODM5_OPTC_DATA_FORMAT_CONTROL 0x1b1c >+#define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 >+#define mmODM5_OPTC_BYTES_PER_PIXEL 0x1b1d >+#define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmODM5_OPTC_WIDTH_CONTROL 0x1b1e >+#define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX 2 >+#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1f >+#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 >+#define mmODM5_OPTC_MEMORY_CONFIG 0x1b20 >+#define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX 2 >+#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b21 >+#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_otg0_dispdec >+// base address: 0x0 >+#define mmOTG0_OTG_H_TOTAL 0x1b2a >+#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 >+#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b >+#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 >+#define mmOTG0_OTG_H_SYNC_A 0x1b2c >+#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 >+#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d >+#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e >+#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 >+#define mmOTG0_OTG_V_TOTAL 0x1b2f >+#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 >+#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 >+#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 >+#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 >+#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 >+#define mmOTG0_OTG_V_TOTAL_MID 0x1b32 >+#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 >+#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 >+#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 >+#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 >+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_V_BLANK_START_END 0x1b36 >+#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 >+#define mmOTG0_OTG_V_SYNC_A 0x1b37 >+#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 >+#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 >+#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG0_OTG_TRIGA_CNTL 0x1b39 >+#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 >+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a >+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b >+#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 >+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c >+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d >+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 >+#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e >+#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f >+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 >+#define mmOTG0_OTG_CONTROL 0x1b41 >+#define mmOTG0_OTG_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_BLANK_CONTROL 0x1b42 >+#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43 >+#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 >+#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 >+#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 >+#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 >+#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 >+#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 >+#define mmOTG0_OTG_STATUS 0x1b49 >+#define mmOTG0_OTG_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_STATUS_POSITION 0x1b4a >+#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 >+#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b >+#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 >+#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c >+#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 >+#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d >+#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 >+#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e >+#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 >+#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f >+#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_COUNT_RESET 0x1b50 >+#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 >+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 >+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 >+#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 >+#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_STEREO_STATUS 0x1b53 >+#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_STEREO_CONTROL 0x1b54 >+#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 >+#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 >+#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 >+#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 >+#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 >+#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 >+#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 >+#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a >+#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b >+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_MASTER_EN 0x1b5c >+#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 >+#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e >+#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 >+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f >+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 >+#define mmOTG0_OTG_BLACK_COLOR 0x1b60 >+#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2 >+#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b61 >+#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 >+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC_CNTL 0x1b68 >+#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC_CNTL2 0x1b69 >+#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2 >+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a >+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b >+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c >+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d >+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e >+#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 >+#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f >+#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 >+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 >+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 >+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 >+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 >+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74 >+#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 >+#define mmOTG0_OTG_CRC1_DATA_B 0x1b75 >+#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 >+#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76 >+#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 >+#define mmOTG0_OTG_CRC2_DATA_B 0x1b77 >+#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 >+#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78 >+#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 >+#define mmOTG0_OTG_CRC3_DATA_B 0x1b79 >+#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 >+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a >+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 >+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b >+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 >+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 >+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 >+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84 >+#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 >+#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 >+#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 >+#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86 >+#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87 >+#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 >+#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88 >+#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 >+#define mmOTG0_OTG_VREADY_PARAM 0x1b89 >+#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 >+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a >+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b >+#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG0_OTG_GSL_CONTROL 0x1b8c >+#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d >+#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 >+#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e >+#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 >+#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f >+#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 >+#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90 >+#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 >+#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91 >+#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 >+#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92 >+#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 >+#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93 >+#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 >+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94 >+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95 >+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b96 >+#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_DRR_CONTROL 0x1b97 >+#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_REQUEST_CONTROL 0x1b98 >+#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 >+#define mmOTG0_OTG_DSC_START_POSITION 0x1b99 >+#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 >+#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9a >+#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 >+#define mmOTG0_OTG_SPARE_REGISTER 0x1b9c >+#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_otg1_dispdec >+// base address: 0x200 >+#define mmOTG1_OTG_H_TOTAL 0x1baa >+#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 >+#define mmOTG1_OTG_H_BLANK_START_END 0x1bab >+#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 >+#define mmOTG1_OTG_H_SYNC_A 0x1bac >+#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 >+#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad >+#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae >+#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 >+#define mmOTG1_OTG_V_TOTAL 0x1baf >+#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 >+#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 >+#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 >+#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 >+#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 >+#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 >+#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 >+#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 >+#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 >+#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 >+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 >+#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 >+#define mmOTG1_OTG_V_SYNC_A 0x1bb7 >+#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 >+#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 >+#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 >+#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 >+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba >+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb >+#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 >+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc >+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd >+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 >+#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe >+#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf >+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 >+#define mmOTG1_OTG_CONTROL 0x1bc1 >+#define mmOTG1_OTG_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 >+#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3 >+#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 >+#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 >+#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 >+#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 >+#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 >+#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 >+#define mmOTG1_OTG_STATUS 0x1bc9 >+#define mmOTG1_OTG_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_STATUS_POSITION 0x1bca >+#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 >+#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb >+#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 >+#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc >+#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 >+#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd >+#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 >+#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce >+#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 >+#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf >+#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_COUNT_RESET 0x1bd0 >+#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 >+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 >+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 >+#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 >+#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_STEREO_STATUS 0x1bd3 >+#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 >+#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 >+#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 >+#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 >+#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 >+#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 >+#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 >+#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 >+#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_UPDATE_LOCK 0x1bda >+#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb >+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_MASTER_EN 0x1bdc >+#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 >+#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde >+#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 >+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf >+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 >+#define mmOTG1_OTG_BLACK_COLOR 0x1be0 >+#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2 >+#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be1 >+#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 >+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC_CNTL 0x1be8 >+#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC_CNTL2 0x1be9 >+#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2 >+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea >+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb >+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec >+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed >+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee >+#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 >+#define mmOTG1_OTG_CRC0_DATA_B 0x1bef >+#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 >+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 >+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 >+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 >+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 >+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4 >+#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 >+#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5 >+#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 >+#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6 >+#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 >+#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7 >+#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 >+#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8 >+#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 >+#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9 >+#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 >+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa >+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 >+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb >+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 >+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 >+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 >+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04 >+#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 >+#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 >+#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 >+#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06 >+#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07 >+#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 >+#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08 >+#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 >+#define mmOTG1_OTG_VREADY_PARAM 0x1c09 >+#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 >+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a >+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b >+#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG1_OTG_GSL_CONTROL 0x1c0c >+#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d >+#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 >+#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e >+#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 >+#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f >+#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 >+#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10 >+#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 >+#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11 >+#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 >+#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12 >+#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 >+#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13 >+#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 >+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14 >+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15 >+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c16 >+#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_DRR_CONTROL 0x1c17 >+#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_REQUEST_CONTROL 0x1c18 >+#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 >+#define mmOTG1_OTG_DSC_START_POSITION 0x1c19 >+#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 >+#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1a >+#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 >+#define mmOTG1_OTG_SPARE_REGISTER 0x1c1c >+#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_otg2_dispdec >+// base address: 0x400 >+#define mmOTG2_OTG_H_TOTAL 0x1c2a >+#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2 >+#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b >+#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 >+#define mmOTG2_OTG_H_SYNC_A 0x1c2c >+#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2 >+#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d >+#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e >+#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 >+#define mmOTG2_OTG_V_TOTAL 0x1c2f >+#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2 >+#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30 >+#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 >+#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31 >+#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 >+#define mmOTG2_OTG_V_TOTAL_MID 0x1c32 >+#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 >+#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33 >+#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 >+#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 >+#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_V_BLANK_START_END 0x1c36 >+#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 >+#define mmOTG2_OTG_V_SYNC_A 0x1c37 >+#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2 >+#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38 >+#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG2_OTG_TRIGA_CNTL 0x1c39 >+#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 >+#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a >+#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b >+#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 >+#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c >+#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d >+#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 >+#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e >+#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f >+#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 >+#define mmOTG2_OTG_CONTROL 0x1c41 >+#define mmOTG2_OTG_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_BLANK_CONTROL 0x1c42 >+#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43 >+#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44 >+#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45 >+#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 >+#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 >+#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 >+#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 >+#define mmOTG2_OTG_STATUS 0x1c49 >+#define mmOTG2_OTG_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_STATUS_POSITION 0x1c4a >+#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2 >+#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b >+#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 >+#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c >+#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 >+#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d >+#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 >+#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e >+#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 >+#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f >+#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_COUNT_RESET 0x1c50 >+#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2 >+#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 >+#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 >+#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 >+#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_STEREO_STATUS 0x1c53 >+#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_STEREO_CONTROL 0x1c54 >+#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55 >+#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 >+#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57 >+#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 >+#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58 >+#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 >+#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59 >+#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a >+#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b >+#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_MASTER_EN 0x1c5c >+#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2 >+#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e >+#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2 >+#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f >+#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 >+#define mmOTG2_OTG_BLACK_COLOR 0x1c60 >+#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2 >+#define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c61 >+#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 >+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC_CNTL 0x1c68 >+#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC_CNTL2 0x1c69 >+#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2 >+#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a >+#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b >+#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c >+#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d >+#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e >+#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 >+#define mmOTG2_OTG_CRC0_DATA_B 0x1c6f >+#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 >+#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 >+#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 >+#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 >+#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 >+#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_CRC1_DATA_RG 0x1c74 >+#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 >+#define mmOTG2_OTG_CRC1_DATA_B 0x1c75 >+#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 >+#define mmOTG2_OTG_CRC2_DATA_RG 0x1c76 >+#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 >+#define mmOTG2_OTG_CRC2_DATA_B 0x1c77 >+#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 >+#define mmOTG2_OTG_CRC3_DATA_RG 0x1c78 >+#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 >+#define mmOTG2_OTG_CRC3_DATA_B 0x1c79 >+#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 >+#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a >+#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 >+#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b >+#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 >+#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 >+#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 >+#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84 >+#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 >+#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 >+#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 >+#define mmOTG2_OTG_CLOCK_CONTROL 0x1c86 >+#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87 >+#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 >+#define mmOTG2_OTG_VUPDATE_PARAM 0x1c88 >+#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 >+#define mmOTG2_OTG_VREADY_PARAM 0x1c89 >+#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2 >+#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a >+#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b >+#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG2_OTG_GSL_CONTROL 0x1c8c >+#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d >+#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 >+#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e >+#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 >+#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f >+#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 >+#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90 >+#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 >+#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91 >+#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 >+#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92 >+#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 >+#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93 >+#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 >+#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94 >+#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95 >+#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c96 >+#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_DRR_CONTROL 0x1c97 >+#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_REQUEST_CONTROL 0x1c98 >+#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 >+#define mmOTG2_OTG_DSC_START_POSITION 0x1c99 >+#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 >+#define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9a >+#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 >+#define mmOTG2_OTG_SPARE_REGISTER 0x1c9c >+#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_otg3_dispdec >+// base address: 0x600 >+#define mmOTG3_OTG_H_TOTAL 0x1caa >+#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2 >+#define mmOTG3_OTG_H_BLANK_START_END 0x1cab >+#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 >+#define mmOTG3_OTG_H_SYNC_A 0x1cac >+#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2 >+#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad >+#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae >+#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 >+#define mmOTG3_OTG_V_TOTAL 0x1caf >+#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2 >+#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0 >+#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 >+#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1 >+#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 >+#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2 >+#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 >+#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 >+#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 >+#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 >+#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6 >+#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 >+#define mmOTG3_OTG_V_SYNC_A 0x1cb7 >+#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2 >+#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 >+#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9 >+#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 >+#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba >+#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb >+#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 >+#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc >+#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd >+#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 >+#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe >+#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf >+#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 >+#define mmOTG3_OTG_CONTROL 0x1cc1 >+#define mmOTG3_OTG_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2 >+#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3 >+#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4 >+#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5 >+#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 >+#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 >+#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 >+#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 >+#define mmOTG3_OTG_STATUS 0x1cc9 >+#define mmOTG3_OTG_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_STATUS_POSITION 0x1cca >+#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2 >+#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb >+#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 >+#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc >+#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 >+#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd >+#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 >+#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce >+#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 >+#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf >+#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_COUNT_RESET 0x1cd0 >+#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2 >+#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 >+#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 >+#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 >+#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_STEREO_STATUS 0x1cd3 >+#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4 >+#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 >+#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 >+#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 >+#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 >+#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 >+#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 >+#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 >+#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_UPDATE_LOCK 0x1cda >+#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb >+#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_MASTER_EN 0x1cdc >+#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2 >+#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde >+#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2 >+#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf >+#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 >+#define mmOTG3_OTG_BLACK_COLOR 0x1ce0 >+#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2 >+#define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce1 >+#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 >+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC_CNTL 0x1ce8 >+#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC_CNTL2 0x1ce9 >+#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2 >+#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea >+#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb >+#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec >+#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced >+#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC0_DATA_RG 0x1cee >+#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 >+#define mmOTG3_OTG_CRC0_DATA_B 0x1cef >+#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 >+#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 >+#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 >+#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 >+#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 >+#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4 >+#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 >+#define mmOTG3_OTG_CRC1_DATA_B 0x1cf5 >+#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 >+#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6 >+#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 >+#define mmOTG3_OTG_CRC2_DATA_B 0x1cf7 >+#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 >+#define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8 >+#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 >+#define mmOTG3_OTG_CRC3_DATA_B 0x1cf9 >+#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 >+#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa >+#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 >+#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb >+#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 >+#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 >+#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 >+#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04 >+#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 >+#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 >+#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 >+#define mmOTG3_OTG_CLOCK_CONTROL 0x1d06 >+#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07 >+#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 >+#define mmOTG3_OTG_VUPDATE_PARAM 0x1d08 >+#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 >+#define mmOTG3_OTG_VREADY_PARAM 0x1d09 >+#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2 >+#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a >+#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b >+#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG3_OTG_GSL_CONTROL 0x1d0c >+#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d >+#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 >+#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e >+#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 >+#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f >+#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 >+#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10 >+#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 >+#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11 >+#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 >+#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12 >+#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 >+#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13 >+#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 >+#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14 >+#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15 >+#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d16 >+#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_DRR_CONTROL 0x1d17 >+#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_REQUEST_CONTROL 0x1d18 >+#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 >+#define mmOTG3_OTG_DSC_START_POSITION 0x1d19 >+#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 >+#define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1a >+#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 >+#define mmOTG3_OTG_SPARE_REGISTER 0x1d1c >+#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_otg4_dispdec >+// base address: 0x800 >+#define mmOTG4_OTG_H_TOTAL 0x1d2a >+#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2 >+#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b >+#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2 >+#define mmOTG4_OTG_H_SYNC_A 0x1d2c >+#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2 >+#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d >+#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e >+#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2 >+#define mmOTG4_OTG_V_TOTAL 0x1d2f >+#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2 >+#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30 >+#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2 >+#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31 >+#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2 >+#define mmOTG4_OTG_V_TOTAL_MID 0x1d32 >+#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2 >+#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33 >+#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34 >+#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35 >+#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_V_BLANK_START_END 0x1d36 >+#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2 >+#define mmOTG4_OTG_V_SYNC_A 0x1d37 >+#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2 >+#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38 >+#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG4_OTG_TRIGA_CNTL 0x1d39 >+#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2 >+#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a >+#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b >+#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2 >+#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c >+#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d >+#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 >+#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e >+#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f >+#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 >+#define mmOTG4_OTG_CONTROL 0x1d41 >+#define mmOTG4_OTG_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_BLANK_CONTROL 0x1d42 >+#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43 >+#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44 >+#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45 >+#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47 >+#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 >+#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48 >+#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 >+#define mmOTG4_OTG_STATUS 0x1d49 >+#define mmOTG4_OTG_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_STATUS_POSITION 0x1d4a >+#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2 >+#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b >+#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2 >+#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c >+#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 >+#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d >+#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2 >+#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e >+#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2 >+#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f >+#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_COUNT_RESET 0x1d50 >+#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2 >+#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51 >+#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 >+#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52 >+#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_STEREO_STATUS 0x1d53 >+#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_STEREO_CONTROL 0x1d54 >+#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55 >+#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56 >+#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57 >+#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2 >+#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58 >+#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2 >+#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59 >+#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a >+#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b >+#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_MASTER_EN 0x1d5c >+#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2 >+#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e >+#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2 >+#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f >+#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 >+#define mmOTG4_OTG_BLACK_COLOR 0x1d60 >+#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2 >+#define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d61 >+#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67 >+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC_CNTL 0x1d68 >+#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC_CNTL2 0x1d69 >+#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2 >+#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a >+#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b >+#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c >+#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d >+#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e >+#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2 >+#define mmOTG4_OTG_CRC0_DATA_B 0x1d6f >+#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2 >+#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70 >+#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71 >+#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72 >+#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73 >+#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_CRC1_DATA_RG 0x1d74 >+#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2 >+#define mmOTG4_OTG_CRC1_DATA_B 0x1d75 >+#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2 >+#define mmOTG4_OTG_CRC2_DATA_RG 0x1d76 >+#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2 >+#define mmOTG4_OTG_CRC2_DATA_B 0x1d77 >+#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2 >+#define mmOTG4_OTG_CRC3_DATA_RG 0x1d78 >+#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2 >+#define mmOTG4_OTG_CRC3_DATA_B 0x1d79 >+#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2 >+#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a >+#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 >+#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b >+#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 >+#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82 >+#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83 >+#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84 >+#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2 >+#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85 >+#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 >+#define mmOTG4_OTG_CLOCK_CONTROL 0x1d86 >+#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87 >+#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2 >+#define mmOTG4_OTG_VUPDATE_PARAM 0x1d88 >+#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2 >+#define mmOTG4_OTG_VREADY_PARAM 0x1d89 >+#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2 >+#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a >+#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b >+#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG4_OTG_GSL_CONTROL 0x1d8c >+#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d >+#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2 >+#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e >+#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2 >+#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f >+#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 >+#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90 >+#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2 >+#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91 >+#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2 >+#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92 >+#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2 >+#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93 >+#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2 >+#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d94 >+#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d95 >+#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d96 >+#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_DRR_CONTROL 0x1d97 >+#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_REQUEST_CONTROL 0x1d98 >+#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2 >+#define mmOTG4_OTG_DSC_START_POSITION 0x1d99 >+#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2 >+#define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1d9a >+#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 >+#define mmOTG4_OTG_SPARE_REGISTER 0x1d9c >+#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_otg5_dispdec >+// base address: 0xa00 >+#define mmOTG5_OTG_H_TOTAL 0x1daa >+#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2 >+#define mmOTG5_OTG_H_BLANK_START_END 0x1dab >+#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2 >+#define mmOTG5_OTG_H_SYNC_A 0x1dac >+#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2 >+#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad >+#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae >+#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2 >+#define mmOTG5_OTG_V_TOTAL 0x1daf >+#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2 >+#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0 >+#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2 >+#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1 >+#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2 >+#define mmOTG5_OTG_V_TOTAL_MID 0x1db2 >+#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2 >+#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3 >+#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4 >+#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5 >+#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_V_BLANK_START_END 0x1db6 >+#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2 >+#define mmOTG5_OTG_V_SYNC_A 0x1db7 >+#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2 >+#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8 >+#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2 >+#define mmOTG5_OTG_TRIGA_CNTL 0x1db9 >+#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2 >+#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba >+#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb >+#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2 >+#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc >+#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 >+#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd >+#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 >+#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe >+#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf >+#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 >+#define mmOTG5_OTG_CONTROL 0x1dc1 >+#define mmOTG5_OTG_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2 >+#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3 >+#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4 >+#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5 >+#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7 >+#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 >+#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8 >+#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 >+#define mmOTG5_OTG_STATUS 0x1dc9 >+#define mmOTG5_OTG_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_STATUS_POSITION 0x1dca >+#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2 >+#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb >+#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2 >+#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc >+#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 >+#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd >+#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2 >+#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce >+#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2 >+#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf >+#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_COUNT_RESET 0x1dd0 >+#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2 >+#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1 >+#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 >+#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2 >+#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_STEREO_STATUS 0x1dd3 >+#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4 >+#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5 >+#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6 >+#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7 >+#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2 >+#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8 >+#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2 >+#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 >+#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_UPDATE_LOCK 0x1dda >+#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb >+#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_MASTER_EN 0x1ddc >+#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2 >+#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1dde >+#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2 >+#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1ddf >+#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 >+#define mmOTG5_OTG_BLACK_COLOR 0x1de0 >+#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2 >+#define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de1 >+#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de2 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de3 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de4 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de5 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de6 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1de7 >+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC_CNTL 0x1de8 >+#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC_CNTL2 0x1de9 >+#define mmOTG5_OTG_CRC_CNTL2_BASE_IDX 2 >+#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dea >+#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1deb >+#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dec >+#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ded >+#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC0_DATA_RG 0x1dee >+#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2 >+#define mmOTG5_OTG_CRC0_DATA_B 0x1def >+#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2 >+#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df0 >+#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df1 >+#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df2 >+#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df3 >+#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_CRC1_DATA_RG 0x1df4 >+#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2 >+#define mmOTG5_OTG_CRC1_DATA_B 0x1df5 >+#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2 >+#define mmOTG5_OTG_CRC2_DATA_RG 0x1df6 >+#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2 >+#define mmOTG5_OTG_CRC2_DATA_B 0x1df7 >+#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2 >+#define mmOTG5_OTG_CRC3_DATA_RG 0x1df8 >+#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2 >+#define mmOTG5_OTG_CRC3_DATA_B 0x1df9 >+#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2 >+#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfa >+#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 >+#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfb >+#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 >+#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e02 >+#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e03 >+#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e04 >+#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2 >+#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e05 >+#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 >+#define mmOTG5_OTG_CLOCK_CONTROL 0x1e06 >+#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e07 >+#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2 >+#define mmOTG5_OTG_VUPDATE_PARAM 0x1e08 >+#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2 >+#define mmOTG5_OTG_VREADY_PARAM 0x1e09 >+#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2 >+#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0a >+#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0b >+#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 >+#define mmOTG5_OTG_GSL_CONTROL 0x1e0c >+#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0d >+#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2 >+#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e0e >+#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2 >+#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e0f >+#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 >+#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e10 >+#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2 >+#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e11 >+#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2 >+#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e12 >+#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2 >+#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e13 >+#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2 >+#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e14 >+#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e15 >+#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e16 >+#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_DRR_CONTROL 0x1e17 >+#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_REQUEST_CONTROL 0x1e18 >+#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2 >+#define mmOTG5_OTG_DSC_START_POSITION 0x1e19 >+#define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX 2 >+#define mmOTG5_OTG_PIPE_UPDATE_STATUS 0x1e1a >+#define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 >+#define mmOTG5_OTG_SPARE_REGISTER 0x1e1c >+#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_optc_misc_dispdec >+// base address: 0x0 >+#define mmDWB_SOURCE_SELECT 0x1e2a >+#define mmDWB_SOURCE_SELECT_BASE_IDX 2 >+#define mmGSL_SOURCE_SELECT 0x1e2b >+#define mmGSL_SOURCE_SELECT_BASE_IDX 2 >+#define mmOPTC_CLOCK_CONTROL 0x1e2c >+#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 >+#define mmODM_MEM_PWR_CTRL 0x1e2d >+#define mmODM_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmODM_MEM_PWR_CTRL2 0x1e2e >+#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2 >+#define mmODM_MEM_PWR_CTRL3 0x1e2f >+#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2 >+#define mmODM_MEM_PWR_STATUS 0x1e30 >+#define mmODM_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmOPTC_MISC_SPARE_REGISTER 0x1e31 >+#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec >+// base address: 0x79a8 >+#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a >+#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b >+#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c >+#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON17_PERFMON_CNTL 0x1e6d >+#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON17_PERFMON_CNTL2 0x1e6e >+#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f >+#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 >+#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON17_PERFMON_HI 0x1e71 >+#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON17_PERFMON_LOW 0x1e72 >+#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dout_i2c_dispdec >+// base address: 0x0 >+#define mmDC_I2C_CONTROL 0x1e98 >+#define mmDC_I2C_CONTROL_BASE_IDX 2 >+#define mmDC_I2C_ARBITRATION 0x1e99 >+#define mmDC_I2C_ARBITRATION_BASE_IDX 2 >+#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a >+#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmDC_I2C_SW_STATUS 0x1e9b >+#define mmDC_I2C_SW_STATUS_BASE_IDX 2 >+#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c >+#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 >+#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d >+#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 >+#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e >+#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 >+#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f >+#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 >+#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0 >+#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 >+#define mmDC_I2C_DDC1_SPEED 0x1ea2 >+#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 >+#define mmDC_I2C_DDC1_SETUP 0x1ea3 >+#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 >+#define mmDC_I2C_DDC2_SPEED 0x1ea4 >+#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 >+#define mmDC_I2C_DDC2_SETUP 0x1ea5 >+#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 >+#define mmDC_I2C_DDC3_SPEED 0x1ea6 >+#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2 >+#define mmDC_I2C_DDC3_SETUP 0x1ea7 >+#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2 >+#define mmDC_I2C_DDC4_SPEED 0x1ea8 >+#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2 >+#define mmDC_I2C_DDC4_SETUP 0x1ea9 >+#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2 >+#define mmDC_I2C_DDC5_SPEED 0x1eaa >+#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2 >+#define mmDC_I2C_DDC5_SETUP 0x1eab >+#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2 >+#define mmDC_I2C_TRANSACTION0 0x1eae >+#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 >+#define mmDC_I2C_TRANSACTION1 0x1eaf >+#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 >+#define mmDC_I2C_TRANSACTION2 0x1eb0 >+#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 >+#define mmDC_I2C_TRANSACTION3 0x1eb1 >+#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 >+#define mmDC_I2C_DATA 0x1eb2 >+#define mmDC_I2C_DATA_BASE_IDX 2 >+#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 >+#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 >+#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 >+#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dio_misc_dispdec >+// base address: 0x0 >+#define mmDIO_SCRATCH0 0x1eca >+#define mmDIO_SCRATCH0_BASE_IDX 2 >+#define mmDIO_SCRATCH1 0x1ecb >+#define mmDIO_SCRATCH1_BASE_IDX 2 >+#define mmDIO_SCRATCH2 0x1ecc >+#define mmDIO_SCRATCH2_BASE_IDX 2 >+#define mmDIO_SCRATCH3 0x1ecd >+#define mmDIO_SCRATCH3_BASE_IDX 2 >+#define mmDIO_SCRATCH4 0x1ece >+#define mmDIO_SCRATCH4_BASE_IDX 2 >+#define mmDIO_SCRATCH5 0x1ecf >+#define mmDIO_SCRATCH5_BASE_IDX 2 >+#define mmDIO_SCRATCH6 0x1ed0 >+#define mmDIO_SCRATCH6_BASE_IDX 2 >+#define mmDIO_SCRATCH7 0x1ed1 >+#define mmDIO_SCRATCH7_BASE_IDX 2 >+#define mmDCE_VCE_CONTROL 0x1ed2 >+#define mmDCE_VCE_CONTROL_BASE_IDX 2 >+#define mmDIO_MEM_PWR_STATUS 0x1edd >+#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 >+#define mmDIO_MEM_PWR_CTRL 0x1ede >+#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 >+#define mmDIO_MEM_PWR_CTRL2 0x1edf >+#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 >+#define mmDIO_CLK_CNTL 0x1ee0 >+#define mmDIO_CLK_CNTL_BASE_IDX 2 >+#define mmDIO_MEM_PWR_CTRL3 0x1ee1 >+#define mmDIO_MEM_PWR_CTRL3_BASE_IDX 2 >+#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 >+#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 >+#define mmDIG_SOFT_RESET 0x1eee >+#define mmDIG_SOFT_RESET_BASE_IDX 2 >+#define mmDIO_MEM_PWR_STATUS1 0x1ef0 >+#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2 >+#define mmDIO_CLK_CNTL2 0x1ef2 >+#define mmDIO_CLK_CNTL2_BASE_IDX 2 >+#define mmDIO_CLK_CNTL3 0x1ef3 >+#define mmDIO_CLK_CNTL3_BASE_IDX 2 >+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff >+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 >+#define mmDIO_PSP_INTERRUPT_STATUS 0x1f00 >+#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01 >+#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 >+#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 >+#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 >+#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 >+#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_hpd0_dispdec >+// base address: 0x0 >+#define mmHPD0_DC_HPD_INT_STATUS 0x1f14 >+#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 >+#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 >+#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 >+#define mmHPD0_DC_HPD_CONTROL 0x1f16 >+#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 >+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 >+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 >+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 >+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_hpd1_dispdec >+// base address: 0x20 >+#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c >+#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 >+#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d >+#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 >+#define mmHPD1_DC_HPD_CONTROL 0x1f1e >+#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 >+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f >+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 >+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 >+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_hpd2_dispdec >+// base address: 0x40 >+#define mmHPD2_DC_HPD_INT_STATUS 0x1f24 >+#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 >+#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25 >+#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 >+#define mmHPD2_DC_HPD_CONTROL 0x1f26 >+#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2 >+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 >+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 >+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 >+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_hpd3_dispdec >+// base address: 0x60 >+#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c >+#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 >+#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d >+#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 >+#define mmHPD3_DC_HPD_CONTROL 0x1f2e >+#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2 >+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f >+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 >+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 >+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_hpd4_dispdec >+// base address: 0x80 >+#define mmHPD4_DC_HPD_INT_STATUS 0x1f34 >+#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 >+#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35 >+#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 >+#define mmHPD4_DC_HPD_CONTROL 0x1f36 >+#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2 >+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 >+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 >+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 >+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec >+// base address: 0x7d10 >+#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 >+#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 >+#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 >+#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON18_PERFMON_CNTL 0x1f47 >+#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON18_PERFMON_CNTL2 0x1f48 >+#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 >+#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a >+#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON18_PERFMON_HI 0x1f4b >+#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON18_PERFMON_LOW 0x1f4c >+#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp_aux0_dispdec >+// base address: 0x0 >+#define mmDP_AUX0_AUX_CONTROL 0x1f50 >+#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 >+#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 >+#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 >+#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 >+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 >+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmDP_AUX0_AUX_SW_STATUS 0x1f54 >+#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 >+#define mmDP_AUX0_AUX_LS_STATUS 0x1f55 >+#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 >+#define mmDP_AUX0_AUX_SW_DATA 0x1f56 >+#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 >+#define mmDP_AUX0_AUX_LS_DATA 0x1f57 >+#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 >+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 >+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 >+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 >+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a >+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 >+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b >+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 >+#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c >+#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 >+#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d >+#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 >+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e >+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 >+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f >+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 >+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 >+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 >+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 >+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 >+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 >+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp_aux1_dispdec >+// base address: 0x70 >+#define mmDP_AUX1_AUX_CONTROL 0x1f6c >+#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d >+#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 >+#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e >+#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 >+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f >+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmDP_AUX1_AUX_SW_STATUS 0x1f70 >+#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 >+#define mmDP_AUX1_AUX_LS_STATUS 0x1f71 >+#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 >+#define mmDP_AUX1_AUX_SW_DATA 0x1f72 >+#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 >+#define mmDP_AUX1_AUX_LS_DATA 0x1f73 >+#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 >+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 >+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 >+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 >+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 >+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 >+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 >+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 >+#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 >+#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 >+#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 >+#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 >+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a >+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 >+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b >+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 >+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c >+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 >+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d >+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 >+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 >+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp_aux2_dispdec >+// base address: 0xe0 >+#define mmDP_AUX2_AUX_CONTROL 0x1f88 >+#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89 >+#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 >+#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a >+#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 >+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b >+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c >+#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 >+#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d >+#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 >+#define mmDP_AUX2_AUX_SW_DATA 0x1f8e >+#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2 >+#define mmDP_AUX2_AUX_LS_DATA 0x1f8f >+#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2 >+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 >+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 >+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 >+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 >+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 >+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 >+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 >+#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 >+#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 >+#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 >+#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 >+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 >+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 >+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 >+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 >+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 >+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 >+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 >+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 >+#define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e >+#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp_aux3_dispdec >+// base address: 0x150 >+#define mmDP_AUX3_AUX_CONTROL 0x1fa4 >+#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5 >+#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 >+#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6 >+#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 >+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 >+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8 >+#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 >+#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9 >+#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 >+#define mmDP_AUX3_AUX_SW_DATA 0x1faa >+#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2 >+#define mmDP_AUX3_AUX_LS_DATA 0x1fab >+#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2 >+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac >+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 >+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad >+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae >+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 >+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf >+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 >+#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 >+#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 >+#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 >+#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 >+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 >+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 >+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 >+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 >+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 >+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 >+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 >+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 >+#define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba >+#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp_aux4_dispdec >+// base address: 0x1c0 >+#define mmDP_AUX4_AUX_CONTROL 0x1fc0 >+#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1 >+#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 >+#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2 >+#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 >+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 >+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 >+#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4 >+#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 >+#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5 >+#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 >+#define mmDP_AUX4_AUX_SW_DATA 0x1fc6 >+#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2 >+#define mmDP_AUX4_AUX_LS_DATA 0x1fc7 >+#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2 >+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 >+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 >+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 >+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 >+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca >+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 >+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb >+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 >+#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc >+#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 >+#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd >+#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 >+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce >+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 >+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf >+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 >+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 >+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 >+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 >+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 >+#define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 >+#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dig0_dispdec >+// base address: 0x0 >+#define mmDIG0_DIG_FE_CNTL 0x2068 >+#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 >+#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069 >+#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 >+#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a >+#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 >+#define mmDIG0_DIG_CLOCK_PATTERN 0x206b >+#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 >+#define mmDIG0_DIG_TEST_PATTERN 0x206c >+#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 >+#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d >+#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 >+#define mmDIG0_DIG_FIFO_STATUS 0x206e >+#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 >+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x206f >+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x2070 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 >+#define mmDIG0_HDMI_CONTROL 0x2071 >+#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 >+#define mmDIG0_HDMI_STATUS 0x2072 >+#define mmDIG0_HDMI_STATUS_BASE_IDX 2 >+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073 >+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074 >+#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075 >+#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076 >+#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077 >+#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 >+#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079 >+#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDIG0_HDMI_GC 0x207b >+#define mmDIG0_HDMI_GC_BASE_IDX 2 >+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c >+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC1_0 0x207d >+#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC1_1 0x207e >+#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC1_2 0x207f >+#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC1_3 0x2080 >+#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC1_4 0x2081 >+#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC2_0 0x2082 >+#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC2_1 0x2083 >+#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC2_2 0x2084 >+#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2 >+#define mmDIG0_AFMT_ISRC2_3 0x2085 >+#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 >+#define mmDIG0_HDMI_DB_CONTROL 0x2088 >+#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 >+#define mmDIG0_DME_CONTROL 0x2089 >+#define mmDIG0_DME_CONTROL_BASE_IDX 2 >+#define mmDIG0_AFMT_MPEG_INFO0 0x208a >+#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2 >+#define mmDIG0_AFMT_MPEG_INFO1 0x208b >+#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_HDR 0x208c >+#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_0 0x208d >+#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_1 0x208e >+#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_2 0x208f >+#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_3 0x2090 >+#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_4 0x2091 >+#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_5 0x2092 >+#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_6 0x2093 >+#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2 >+#define mmDIG0_AFMT_GENERIC_7 0x2094 >+#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_32_0 0x2096 >+#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_32_1 0x2097 >+#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_44_0 0x2098 >+#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_44_1 0x2099 >+#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_48_0 0x209a >+#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_48_1 0x209b >+#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_STATUS_0 0x209c >+#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 >+#define mmDIG0_HDMI_ACR_STATUS_1 0x209d >+#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 >+#define mmDIG0_AFMT_AUDIO_INFO0 0x209e >+#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2 >+#define mmDIG0_AFMT_AUDIO_INFO1 0x209f >+#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2 >+#define mmDIG0_AFMT_60958_0 0x20a0 >+#define mmDIG0_AFMT_60958_0_BASE_IDX 2 >+#define mmDIG0_AFMT_60958_1 0x20a1 >+#define mmDIG0_AFMT_60958_1_BASE_IDX 2 >+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2 >+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 >+#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3 >+#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2 >+#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4 >+#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2 >+#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5 >+#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2 >+#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6 >+#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2 >+#define mmDIG0_AFMT_60958_2 0x20a7 >+#define mmDIG0_AFMT_60958_2_BASE_IDX 2 >+#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8 >+#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 >+#define mmDIG0_AFMT_STATUS 0x20a9 >+#define mmDIG0_AFMT_STATUS_BASE_IDX 2 >+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa >+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab >+#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac >+#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad >+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 >+#define mmDIG0_DIG_BE_CNTL 0x20af >+#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 >+#define mmDIG0_DIG_BE_EN_CNTL 0x20b0 >+#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 >+#define mmDIG0_TMDS_CNTL 0x20d3 >+#define mmDIG0_TMDS_CNTL_BASE_IDX 2 >+#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4 >+#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 >+#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5 >+#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 >+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6 >+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 >+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7 >+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 >+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8 >+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 >+#define mmDIG0_TMDS_CTL_BITS 0x20da >+#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 >+#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db >+#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 >+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20dc >+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 >+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd >+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 >+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de >+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 >+#define mmDIG0_DIG_VERSION 0x20e0 >+#define mmDIG0_DIG_VERSION_BASE_IDX 2 >+#define mmDIG0_DIG_LANE_ENABLE 0x20e1 >+#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 >+#define mmDIG0_AFMT_CNTL 0x20e6 >+#define mmDIG0_AFMT_CNTL_BASE_IDX 2 >+#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7 >+#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20f6 >+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 >+#define mmDIG0_FORCE_DIG_DISABLE 0x20f7 >+#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp0_dispdec >+// base address: 0x0 >+#define mmDP0_DP_LINK_CNTL 0x2108 >+#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 >+#define mmDP0_DP_PIXEL_FORMAT 0x2109 >+#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 >+#define mmDP0_DP_MSA_COLORIMETRY 0x210a >+#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 >+#define mmDP0_DP_CONFIG 0x210b >+#define mmDP0_DP_CONFIG_BASE_IDX 2 >+#define mmDP0_DP_VID_STREAM_CNTL 0x210c >+#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 >+#define mmDP0_DP_STEER_FIFO 0x210d >+#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 >+#define mmDP0_DP_MSA_MISC 0x210e >+#define mmDP0_DP_MSA_MISC_BASE_IDX 2 >+#define mmDP0_DP_VID_TIMING 0x2110 >+#define mmDP0_DP_VID_TIMING_BASE_IDX 2 >+#define mmDP0_DP_VID_N 0x2111 >+#define mmDP0_DP_VID_N_BASE_IDX 2 >+#define mmDP0_DP_VID_M 0x2112 >+#define mmDP0_DP_VID_M_BASE_IDX 2 >+#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 >+#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 >+#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 >+#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 >+#define mmDP0_DP_VID_MSA_VBID 0x2115 >+#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 >+#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 >+#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_CNTL 0x2117 >+#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 >+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_SYM0 0x2119 >+#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 >+#define mmDP0_DP_DPHY_SYM1 0x211a >+#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 >+#define mmDP0_DP_DPHY_SYM2 0x211b >+#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 >+#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c >+#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d >+#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e >+#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_CRC_EN 0x211f >+#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 >+#define mmDP0_DP_DPHY_CRC_CNTL 0x2120 >+#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_CRC_RESULT 0x2121 >+#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 >+#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 >+#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 >+#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 >+#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 >+#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 >+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 >+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 >+#define mmDP0_DP_SEC_CNTL 0x212b >+#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 >+#define mmDP0_DP_SEC_CNTL1 0x212c >+#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 >+#define mmDP0_DP_SEC_FRAMING1 0x212d >+#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 >+#define mmDP0_DP_SEC_FRAMING2 0x212e >+#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 >+#define mmDP0_DP_SEC_FRAMING3 0x212f >+#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 >+#define mmDP0_DP_SEC_FRAMING4 0x2130 >+#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 >+#define mmDP0_DP_SEC_AUD_N 0x2131 >+#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 >+#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 >+#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 >+#define mmDP0_DP_SEC_AUD_M 0x2133 >+#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 >+#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 >+#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 >+#define mmDP0_DP_SEC_TIMESTAMP 0x2135 >+#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 >+#define mmDP0_DP_SEC_PACKET_CNTL 0x2136 >+#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 >+#define mmDP0_DP_MSE_RATE_CNTL 0x2137 >+#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 >+#define mmDP0_DP_MSE_RATE_UPDATE 0x2139 >+#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 >+#define mmDP0_DP_MSE_SAT0 0x213a >+#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 >+#define mmDP0_DP_MSE_SAT1 0x213b >+#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 >+#define mmDP0_DP_MSE_SAT2 0x213c >+#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 >+#define mmDP0_DP_MSE_SAT_UPDATE 0x213d >+#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 >+#define mmDP0_DP_MSE_LINK_TIMING 0x213e >+#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 >+#define mmDP0_DP_MSE_MISC_CNTL 0x213f >+#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 >+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 >+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 >+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 >+#define mmDP0_DP_MSE_SAT0_STATUS 0x2147 >+#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 >+#define mmDP0_DP_MSE_SAT1_STATUS 0x2148 >+#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 >+#define mmDP0_DP_MSE_SAT2_STATUS 0x2149 >+#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 >+#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c >+#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 >+#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d >+#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 >+#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e >+#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 >+#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f >+#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 >+#define mmDP0_DP_MSO_CNTL 0x2150 >+#define mmDP0_DP_MSO_CNTL_BASE_IDX 2 >+#define mmDP0_DP_MSO_CNTL1 0x2151 >+#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2 >+#define mmDP0_DP_DSC_CNTL 0x2152 >+#define mmDP0_DP_DSC_CNTL_BASE_IDX 2 >+#define mmDP0_DP_SEC_CNTL2 0x2153 >+#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 >+#define mmDP0_DP_SEC_CNTL3 0x2154 >+#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 >+#define mmDP0_DP_SEC_CNTL4 0x2155 >+#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 >+#define mmDP0_DP_SEC_CNTL5 0x2156 >+#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 >+#define mmDP0_DP_SEC_CNTL6 0x2157 >+#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 >+#define mmDP0_DP_SEC_CNTL7 0x2158 >+#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 >+#define mmDP0_DP_DB_CNTL 0x2159 >+#define mmDP0_DP_DB_CNTL_BASE_IDX 2 >+#define mmDP0_DP_MSA_VBID_MISC 0x215a >+#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 >+#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b >+#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 >+#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c >+#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmDP0_DP_ALPM_CNTL 0x215d >+#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dig1_dispdec >+// base address: 0x400 >+#define mmDIG1_DIG_FE_CNTL 0x2168 >+#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 >+#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169 >+#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 >+#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a >+#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 >+#define mmDIG1_DIG_CLOCK_PATTERN 0x216b >+#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 >+#define mmDIG1_DIG_TEST_PATTERN 0x216c >+#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 >+#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d >+#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 >+#define mmDIG1_DIG_FIFO_STATUS 0x216e >+#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 >+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x216f >+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x2170 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 >+#define mmDIG1_HDMI_CONTROL 0x2171 >+#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 >+#define mmDIG1_HDMI_STATUS 0x2172 >+#define mmDIG1_HDMI_STATUS_BASE_IDX 2 >+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173 >+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174 >+#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175 >+#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176 >+#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177 >+#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 >+#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179 >+#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDIG1_HDMI_GC 0x217b >+#define mmDIG1_HDMI_GC_BASE_IDX 2 >+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c >+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC1_0 0x217d >+#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC1_1 0x217e >+#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC1_2 0x217f >+#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC1_3 0x2180 >+#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC1_4 0x2181 >+#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC2_0 0x2182 >+#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC2_1 0x2183 >+#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC2_2 0x2184 >+#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2 >+#define mmDIG1_AFMT_ISRC2_3 0x2185 >+#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 >+#define mmDIG1_HDMI_DB_CONTROL 0x2188 >+#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 >+#define mmDIG1_DME_CONTROL 0x2189 >+#define mmDIG1_DME_CONTROL_BASE_IDX 2 >+#define mmDIG1_AFMT_MPEG_INFO0 0x218a >+#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2 >+#define mmDIG1_AFMT_MPEG_INFO1 0x218b >+#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_HDR 0x218c >+#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_0 0x218d >+#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_1 0x218e >+#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_2 0x218f >+#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_3 0x2190 >+#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_4 0x2191 >+#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_5 0x2192 >+#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_6 0x2193 >+#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2 >+#define mmDIG1_AFMT_GENERIC_7 0x2194 >+#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_32_0 0x2196 >+#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_32_1 0x2197 >+#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_44_0 0x2198 >+#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_44_1 0x2199 >+#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_48_0 0x219a >+#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_48_1 0x219b >+#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_STATUS_0 0x219c >+#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 >+#define mmDIG1_HDMI_ACR_STATUS_1 0x219d >+#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 >+#define mmDIG1_AFMT_AUDIO_INFO0 0x219e >+#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2 >+#define mmDIG1_AFMT_AUDIO_INFO1 0x219f >+#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2 >+#define mmDIG1_AFMT_60958_0 0x21a0 >+#define mmDIG1_AFMT_60958_0_BASE_IDX 2 >+#define mmDIG1_AFMT_60958_1 0x21a1 >+#define mmDIG1_AFMT_60958_1_BASE_IDX 2 >+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2 >+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 >+#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3 >+#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2 >+#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4 >+#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2 >+#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5 >+#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2 >+#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6 >+#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2 >+#define mmDIG1_AFMT_60958_2 0x21a7 >+#define mmDIG1_AFMT_60958_2_BASE_IDX 2 >+#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8 >+#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 >+#define mmDIG1_AFMT_STATUS 0x21a9 >+#define mmDIG1_AFMT_STATUS_BASE_IDX 2 >+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa >+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab >+#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac >+#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad >+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 >+#define mmDIG1_DIG_BE_CNTL 0x21af >+#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 >+#define mmDIG1_DIG_BE_EN_CNTL 0x21b0 >+#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 >+#define mmDIG1_TMDS_CNTL 0x21d3 >+#define mmDIG1_TMDS_CNTL_BASE_IDX 2 >+#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4 >+#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 >+#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5 >+#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 >+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6 >+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 >+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7 >+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 >+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8 >+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 >+#define mmDIG1_TMDS_CTL_BITS 0x21da >+#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 >+#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db >+#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 >+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21dc >+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 >+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd >+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 >+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de >+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 >+#define mmDIG1_DIG_VERSION 0x21e0 >+#define mmDIG1_DIG_VERSION_BASE_IDX 2 >+#define mmDIG1_DIG_LANE_ENABLE 0x21e1 >+#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 >+#define mmDIG1_AFMT_CNTL 0x21e6 >+#define mmDIG1_AFMT_CNTL_BASE_IDX 2 >+#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7 >+#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21f6 >+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 >+#define mmDIG1_FORCE_DIG_DISABLE 0x21f7 >+#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp1_dispdec >+// base address: 0x400 >+#define mmDP1_DP_LINK_CNTL 0x2208 >+#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 >+#define mmDP1_DP_PIXEL_FORMAT 0x2209 >+#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 >+#define mmDP1_DP_MSA_COLORIMETRY 0x220a >+#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 >+#define mmDP1_DP_CONFIG 0x220b >+#define mmDP1_DP_CONFIG_BASE_IDX 2 >+#define mmDP1_DP_VID_STREAM_CNTL 0x220c >+#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 >+#define mmDP1_DP_STEER_FIFO 0x220d >+#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 >+#define mmDP1_DP_MSA_MISC 0x220e >+#define mmDP1_DP_MSA_MISC_BASE_IDX 2 >+#define mmDP1_DP_VID_TIMING 0x2210 >+#define mmDP1_DP_VID_TIMING_BASE_IDX 2 >+#define mmDP1_DP_VID_N 0x2211 >+#define mmDP1_DP_VID_N_BASE_IDX 2 >+#define mmDP1_DP_VID_M 0x2212 >+#define mmDP1_DP_VID_M_BASE_IDX 2 >+#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 >+#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 >+#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 >+#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 >+#define mmDP1_DP_VID_MSA_VBID 0x2215 >+#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 >+#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 >+#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_CNTL 0x2217 >+#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 >+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_SYM0 0x2219 >+#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 >+#define mmDP1_DP_DPHY_SYM1 0x221a >+#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 >+#define mmDP1_DP_DPHY_SYM2 0x221b >+#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 >+#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c >+#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d >+#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e >+#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_CRC_EN 0x221f >+#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 >+#define mmDP1_DP_DPHY_CRC_CNTL 0x2220 >+#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_CRC_RESULT 0x2221 >+#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 >+#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 >+#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 >+#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 >+#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 >+#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 >+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 >+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 >+#define mmDP1_DP_SEC_CNTL 0x222b >+#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 >+#define mmDP1_DP_SEC_CNTL1 0x222c >+#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 >+#define mmDP1_DP_SEC_FRAMING1 0x222d >+#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 >+#define mmDP1_DP_SEC_FRAMING2 0x222e >+#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 >+#define mmDP1_DP_SEC_FRAMING3 0x222f >+#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 >+#define mmDP1_DP_SEC_FRAMING4 0x2230 >+#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 >+#define mmDP1_DP_SEC_AUD_N 0x2231 >+#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 >+#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 >+#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 >+#define mmDP1_DP_SEC_AUD_M 0x2233 >+#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 >+#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 >+#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 >+#define mmDP1_DP_SEC_TIMESTAMP 0x2235 >+#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 >+#define mmDP1_DP_SEC_PACKET_CNTL 0x2236 >+#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 >+#define mmDP1_DP_MSE_RATE_CNTL 0x2237 >+#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 >+#define mmDP1_DP_MSE_RATE_UPDATE 0x2239 >+#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 >+#define mmDP1_DP_MSE_SAT0 0x223a >+#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 >+#define mmDP1_DP_MSE_SAT1 0x223b >+#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 >+#define mmDP1_DP_MSE_SAT2 0x223c >+#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 >+#define mmDP1_DP_MSE_SAT_UPDATE 0x223d >+#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 >+#define mmDP1_DP_MSE_LINK_TIMING 0x223e >+#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 >+#define mmDP1_DP_MSE_MISC_CNTL 0x223f >+#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 >+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 >+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 >+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 >+#define mmDP1_DP_MSE_SAT0_STATUS 0x2247 >+#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 >+#define mmDP1_DP_MSE_SAT1_STATUS 0x2248 >+#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 >+#define mmDP1_DP_MSE_SAT2_STATUS 0x2249 >+#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 >+#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c >+#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 >+#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d >+#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 >+#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e >+#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 >+#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f >+#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 >+#define mmDP1_DP_MSO_CNTL 0x2250 >+#define mmDP1_DP_MSO_CNTL_BASE_IDX 2 >+#define mmDP1_DP_MSO_CNTL1 0x2251 >+#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2 >+#define mmDP1_DP_DSC_CNTL 0x2252 >+#define mmDP1_DP_DSC_CNTL_BASE_IDX 2 >+#define mmDP1_DP_SEC_CNTL2 0x2253 >+#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 >+#define mmDP1_DP_SEC_CNTL3 0x2254 >+#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 >+#define mmDP1_DP_SEC_CNTL4 0x2255 >+#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 >+#define mmDP1_DP_SEC_CNTL5 0x2256 >+#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 >+#define mmDP1_DP_SEC_CNTL6 0x2257 >+#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 >+#define mmDP1_DP_SEC_CNTL7 0x2258 >+#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 >+#define mmDP1_DP_DB_CNTL 0x2259 >+#define mmDP1_DP_DB_CNTL_BASE_IDX 2 >+#define mmDP1_DP_MSA_VBID_MISC 0x225a >+#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 >+#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b >+#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 >+#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c >+#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmDP1_DP_ALPM_CNTL 0x225d >+#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dig2_dispdec >+// base address: 0x800 >+#define mmDIG2_DIG_FE_CNTL 0x2268 >+#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2 >+#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269 >+#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 >+#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a >+#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 >+#define mmDIG2_DIG_CLOCK_PATTERN 0x226b >+#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 >+#define mmDIG2_DIG_TEST_PATTERN 0x226c >+#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2 >+#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d >+#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 >+#define mmDIG2_DIG_FIFO_STATUS 0x226e >+#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2 >+#define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x226f >+#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x2270 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 >+#define mmDIG2_HDMI_CONTROL 0x2271 >+#define mmDIG2_HDMI_CONTROL_BASE_IDX 2 >+#define mmDIG2_HDMI_STATUS 0x2272 >+#define mmDIG2_HDMI_STATUS_BASE_IDX 2 >+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273 >+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274 >+#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275 >+#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276 >+#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277 >+#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 >+#define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279 >+#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDIG2_HDMI_GC 0x227b >+#define mmDIG2_HDMI_GC_BASE_IDX 2 >+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c >+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC1_0 0x227d >+#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC1_1 0x227e >+#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC1_2 0x227f >+#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC1_3 0x2280 >+#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC1_4 0x2281 >+#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC2_0 0x2282 >+#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC2_1 0x2283 >+#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC2_2 0x2284 >+#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2 >+#define mmDIG2_AFMT_ISRC2_3 0x2285 >+#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 >+#define mmDIG2_HDMI_DB_CONTROL 0x2288 >+#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2 >+#define mmDIG2_DME_CONTROL 0x2289 >+#define mmDIG2_DME_CONTROL_BASE_IDX 2 >+#define mmDIG2_AFMT_MPEG_INFO0 0x228a >+#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2 >+#define mmDIG2_AFMT_MPEG_INFO1 0x228b >+#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_HDR 0x228c >+#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_0 0x228d >+#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_1 0x228e >+#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_2 0x228f >+#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_3 0x2290 >+#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_4 0x2291 >+#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_5 0x2292 >+#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_6 0x2293 >+#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2 >+#define mmDIG2_AFMT_GENERIC_7 0x2294 >+#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_32_0 0x2296 >+#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_32_1 0x2297 >+#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_44_0 0x2298 >+#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_44_1 0x2299 >+#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_48_0 0x229a >+#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_48_1 0x229b >+#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_STATUS_0 0x229c >+#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 >+#define mmDIG2_HDMI_ACR_STATUS_1 0x229d >+#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 >+#define mmDIG2_AFMT_AUDIO_INFO0 0x229e >+#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2 >+#define mmDIG2_AFMT_AUDIO_INFO1 0x229f >+#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2 >+#define mmDIG2_AFMT_60958_0 0x22a0 >+#define mmDIG2_AFMT_60958_0_BASE_IDX 2 >+#define mmDIG2_AFMT_60958_1 0x22a1 >+#define mmDIG2_AFMT_60958_1_BASE_IDX 2 >+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2 >+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 >+#define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3 >+#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2 >+#define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4 >+#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2 >+#define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5 >+#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2 >+#define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6 >+#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2 >+#define mmDIG2_AFMT_60958_2 0x22a7 >+#define mmDIG2_AFMT_60958_2_BASE_IDX 2 >+#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8 >+#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 >+#define mmDIG2_AFMT_STATUS 0x22a9 >+#define mmDIG2_AFMT_STATUS_BASE_IDX 2 >+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa >+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab >+#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac >+#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad >+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 >+#define mmDIG2_DIG_BE_CNTL 0x22af >+#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2 >+#define mmDIG2_DIG_BE_EN_CNTL 0x22b0 >+#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 >+#define mmDIG2_TMDS_CNTL 0x22d3 >+#define mmDIG2_TMDS_CNTL_BASE_IDX 2 >+#define mmDIG2_TMDS_CONTROL_CHAR 0x22d4 >+#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 >+#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5 >+#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 >+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6 >+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 >+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7 >+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 >+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8 >+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 >+#define mmDIG2_TMDS_CTL_BITS 0x22da >+#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2 >+#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db >+#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 >+#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22dc >+#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 >+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd >+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 >+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de >+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 >+#define mmDIG2_DIG_VERSION 0x22e0 >+#define mmDIG2_DIG_VERSION_BASE_IDX 2 >+#define mmDIG2_DIG_LANE_ENABLE 0x22e1 >+#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2 >+#define mmDIG2_AFMT_CNTL 0x22e6 >+#define mmDIG2_AFMT_CNTL_BASE_IDX 2 >+#define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7 >+#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22f6 >+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 >+#define mmDIG2_FORCE_DIG_DISABLE 0x22f7 >+#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp2_dispdec >+// base address: 0x800 >+#define mmDP2_DP_LINK_CNTL 0x2308 >+#define mmDP2_DP_LINK_CNTL_BASE_IDX 2 >+#define mmDP2_DP_PIXEL_FORMAT 0x2309 >+#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2 >+#define mmDP2_DP_MSA_COLORIMETRY 0x230a >+#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 >+#define mmDP2_DP_CONFIG 0x230b >+#define mmDP2_DP_CONFIG_BASE_IDX 2 >+#define mmDP2_DP_VID_STREAM_CNTL 0x230c >+#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 >+#define mmDP2_DP_STEER_FIFO 0x230d >+#define mmDP2_DP_STEER_FIFO_BASE_IDX 2 >+#define mmDP2_DP_MSA_MISC 0x230e >+#define mmDP2_DP_MSA_MISC_BASE_IDX 2 >+#define mmDP2_DP_VID_TIMING 0x2310 >+#define mmDP2_DP_VID_TIMING_BASE_IDX 2 >+#define mmDP2_DP_VID_N 0x2311 >+#define mmDP2_DP_VID_N_BASE_IDX 2 >+#define mmDP2_DP_VID_M 0x2312 >+#define mmDP2_DP_VID_M_BASE_IDX 2 >+#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313 >+#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 >+#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314 >+#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 >+#define mmDP2_DP_VID_MSA_VBID 0x2315 >+#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2 >+#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316 >+#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_CNTL 0x2317 >+#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 >+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_SYM0 0x2319 >+#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2 >+#define mmDP2_DP_DPHY_SYM1 0x231a >+#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2 >+#define mmDP2_DP_DPHY_SYM2 0x231b >+#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2 >+#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c >+#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d >+#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e >+#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_CRC_EN 0x231f >+#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2 >+#define mmDP2_DP_DPHY_CRC_CNTL 0x2320 >+#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_CRC_RESULT 0x2321 >+#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 >+#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322 >+#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323 >+#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 >+#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324 >+#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 >+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 >+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 >+#define mmDP2_DP_SEC_CNTL 0x232b >+#define mmDP2_DP_SEC_CNTL_BASE_IDX 2 >+#define mmDP2_DP_SEC_CNTL1 0x232c >+#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2 >+#define mmDP2_DP_SEC_FRAMING1 0x232d >+#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2 >+#define mmDP2_DP_SEC_FRAMING2 0x232e >+#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2 >+#define mmDP2_DP_SEC_FRAMING3 0x232f >+#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2 >+#define mmDP2_DP_SEC_FRAMING4 0x2330 >+#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2 >+#define mmDP2_DP_SEC_AUD_N 0x2331 >+#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2 >+#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332 >+#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 >+#define mmDP2_DP_SEC_AUD_M 0x2333 >+#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2 >+#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334 >+#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 >+#define mmDP2_DP_SEC_TIMESTAMP 0x2335 >+#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 >+#define mmDP2_DP_SEC_PACKET_CNTL 0x2336 >+#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 >+#define mmDP2_DP_MSE_RATE_CNTL 0x2337 >+#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 >+#define mmDP2_DP_MSE_RATE_UPDATE 0x2339 >+#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 >+#define mmDP2_DP_MSE_SAT0 0x233a >+#define mmDP2_DP_MSE_SAT0_BASE_IDX 2 >+#define mmDP2_DP_MSE_SAT1 0x233b >+#define mmDP2_DP_MSE_SAT1_BASE_IDX 2 >+#define mmDP2_DP_MSE_SAT2 0x233c >+#define mmDP2_DP_MSE_SAT2_BASE_IDX 2 >+#define mmDP2_DP_MSE_SAT_UPDATE 0x233d >+#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 >+#define mmDP2_DP_MSE_LINK_TIMING 0x233e >+#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 >+#define mmDP2_DP_MSE_MISC_CNTL 0x233f >+#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 >+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 >+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 >+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 >+#define mmDP2_DP_MSE_SAT0_STATUS 0x2347 >+#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 >+#define mmDP2_DP_MSE_SAT1_STATUS 0x2348 >+#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 >+#define mmDP2_DP_MSE_SAT2_STATUS 0x2349 >+#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 >+#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c >+#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 >+#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d >+#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 >+#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e >+#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 >+#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f >+#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 >+#define mmDP2_DP_MSO_CNTL 0x2350 >+#define mmDP2_DP_MSO_CNTL_BASE_IDX 2 >+#define mmDP2_DP_MSO_CNTL1 0x2351 >+#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2 >+#define mmDP2_DP_DSC_CNTL 0x2352 >+#define mmDP2_DP_DSC_CNTL_BASE_IDX 2 >+#define mmDP2_DP_SEC_CNTL2 0x2353 >+#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2 >+#define mmDP2_DP_SEC_CNTL3 0x2354 >+#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2 >+#define mmDP2_DP_SEC_CNTL4 0x2355 >+#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2 >+#define mmDP2_DP_SEC_CNTL5 0x2356 >+#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2 >+#define mmDP2_DP_SEC_CNTL6 0x2357 >+#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2 >+#define mmDP2_DP_SEC_CNTL7 0x2358 >+#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2 >+#define mmDP2_DP_DB_CNTL 0x2359 >+#define mmDP2_DP_DB_CNTL_BASE_IDX 2 >+#define mmDP2_DP_MSA_VBID_MISC 0x235a >+#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2 >+#define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b >+#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 >+#define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c >+#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmDP2_DP_ALPM_CNTL 0x235d >+#define mmDP2_DP_ALPM_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dig3_dispdec >+// base address: 0xc00 >+#define mmDIG3_DIG_FE_CNTL 0x2368 >+#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2 >+#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369 >+#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 >+#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a >+#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 >+#define mmDIG3_DIG_CLOCK_PATTERN 0x236b >+#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 >+#define mmDIG3_DIG_TEST_PATTERN 0x236c >+#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2 >+#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d >+#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 >+#define mmDIG3_DIG_FIFO_STATUS 0x236e >+#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2 >+#define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x236f >+#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2370 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 >+#define mmDIG3_HDMI_CONTROL 0x2371 >+#define mmDIG3_HDMI_CONTROL_BASE_IDX 2 >+#define mmDIG3_HDMI_STATUS 0x2372 >+#define mmDIG3_HDMI_STATUS_BASE_IDX 2 >+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373 >+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374 >+#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375 >+#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376 >+#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377 >+#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 >+#define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379 >+#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDIG3_HDMI_GC 0x237b >+#define mmDIG3_HDMI_GC_BASE_IDX 2 >+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c >+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC1_0 0x237d >+#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC1_1 0x237e >+#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC1_2 0x237f >+#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC1_3 0x2380 >+#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC1_4 0x2381 >+#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC2_0 0x2382 >+#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC2_1 0x2383 >+#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC2_2 0x2384 >+#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2 >+#define mmDIG3_AFMT_ISRC2_3 0x2385 >+#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 >+#define mmDIG3_HDMI_DB_CONTROL 0x2388 >+#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2 >+#define mmDIG3_DME_CONTROL 0x2389 >+#define mmDIG3_DME_CONTROL_BASE_IDX 2 >+#define mmDIG3_AFMT_MPEG_INFO0 0x238a >+#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2 >+#define mmDIG3_AFMT_MPEG_INFO1 0x238b >+#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_HDR 0x238c >+#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_0 0x238d >+#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_1 0x238e >+#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_2 0x238f >+#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_3 0x2390 >+#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_4 0x2391 >+#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_5 0x2392 >+#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_6 0x2393 >+#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2 >+#define mmDIG3_AFMT_GENERIC_7 0x2394 >+#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_32_0 0x2396 >+#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_32_1 0x2397 >+#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_44_0 0x2398 >+#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_44_1 0x2399 >+#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_48_0 0x239a >+#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_48_1 0x239b >+#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_STATUS_0 0x239c >+#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 >+#define mmDIG3_HDMI_ACR_STATUS_1 0x239d >+#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 >+#define mmDIG3_AFMT_AUDIO_INFO0 0x239e >+#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2 >+#define mmDIG3_AFMT_AUDIO_INFO1 0x239f >+#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2 >+#define mmDIG3_AFMT_60958_0 0x23a0 >+#define mmDIG3_AFMT_60958_0_BASE_IDX 2 >+#define mmDIG3_AFMT_60958_1 0x23a1 >+#define mmDIG3_AFMT_60958_1_BASE_IDX 2 >+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2 >+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 >+#define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3 >+#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2 >+#define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4 >+#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2 >+#define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5 >+#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2 >+#define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6 >+#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2 >+#define mmDIG3_AFMT_60958_2 0x23a7 >+#define mmDIG3_AFMT_60958_2_BASE_IDX 2 >+#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8 >+#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 >+#define mmDIG3_AFMT_STATUS 0x23a9 >+#define mmDIG3_AFMT_STATUS_BASE_IDX 2 >+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa >+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab >+#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac >+#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad >+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 >+#define mmDIG3_DIG_BE_CNTL 0x23af >+#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2 >+#define mmDIG3_DIG_BE_EN_CNTL 0x23b0 >+#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 >+#define mmDIG3_TMDS_CNTL 0x23d3 >+#define mmDIG3_TMDS_CNTL_BASE_IDX 2 >+#define mmDIG3_TMDS_CONTROL_CHAR 0x23d4 >+#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 >+#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5 >+#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 >+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6 >+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 >+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7 >+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 >+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8 >+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 >+#define mmDIG3_TMDS_CTL_BITS 0x23da >+#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2 >+#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db >+#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 >+#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23dc >+#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 >+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd >+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 >+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de >+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 >+#define mmDIG3_DIG_VERSION 0x23e0 >+#define mmDIG3_DIG_VERSION_BASE_IDX 2 >+#define mmDIG3_DIG_LANE_ENABLE 0x23e1 >+#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2 >+#define mmDIG3_AFMT_CNTL 0x23e6 >+#define mmDIG3_AFMT_CNTL_BASE_IDX 2 >+#define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7 >+#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x23f6 >+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 >+#define mmDIG3_FORCE_DIG_DISABLE 0x23f7 >+#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp3_dispdec >+// base address: 0xc00 >+#define mmDP3_DP_LINK_CNTL 0x2408 >+#define mmDP3_DP_LINK_CNTL_BASE_IDX 2 >+#define mmDP3_DP_PIXEL_FORMAT 0x2409 >+#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2 >+#define mmDP3_DP_MSA_COLORIMETRY 0x240a >+#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 >+#define mmDP3_DP_CONFIG 0x240b >+#define mmDP3_DP_CONFIG_BASE_IDX 2 >+#define mmDP3_DP_VID_STREAM_CNTL 0x240c >+#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 >+#define mmDP3_DP_STEER_FIFO 0x240d >+#define mmDP3_DP_STEER_FIFO_BASE_IDX 2 >+#define mmDP3_DP_MSA_MISC 0x240e >+#define mmDP3_DP_MSA_MISC_BASE_IDX 2 >+#define mmDP3_DP_VID_TIMING 0x2410 >+#define mmDP3_DP_VID_TIMING_BASE_IDX 2 >+#define mmDP3_DP_VID_N 0x2411 >+#define mmDP3_DP_VID_N_BASE_IDX 2 >+#define mmDP3_DP_VID_M 0x2412 >+#define mmDP3_DP_VID_M_BASE_IDX 2 >+#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413 >+#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 >+#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414 >+#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 >+#define mmDP3_DP_VID_MSA_VBID 0x2415 >+#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2 >+#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416 >+#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_CNTL 0x2417 >+#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 >+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_SYM0 0x2419 >+#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2 >+#define mmDP3_DP_DPHY_SYM1 0x241a >+#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2 >+#define mmDP3_DP_DPHY_SYM2 0x241b >+#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2 >+#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c >+#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d >+#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e >+#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_CRC_EN 0x241f >+#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2 >+#define mmDP3_DP_DPHY_CRC_CNTL 0x2420 >+#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_CRC_RESULT 0x2421 >+#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 >+#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422 >+#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423 >+#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 >+#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424 >+#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 >+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 >+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 >+#define mmDP3_DP_SEC_CNTL 0x242b >+#define mmDP3_DP_SEC_CNTL_BASE_IDX 2 >+#define mmDP3_DP_SEC_CNTL1 0x242c >+#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2 >+#define mmDP3_DP_SEC_FRAMING1 0x242d >+#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2 >+#define mmDP3_DP_SEC_FRAMING2 0x242e >+#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2 >+#define mmDP3_DP_SEC_FRAMING3 0x242f >+#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2 >+#define mmDP3_DP_SEC_FRAMING4 0x2430 >+#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2 >+#define mmDP3_DP_SEC_AUD_N 0x2431 >+#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2 >+#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432 >+#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 >+#define mmDP3_DP_SEC_AUD_M 0x2433 >+#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2 >+#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434 >+#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 >+#define mmDP3_DP_SEC_TIMESTAMP 0x2435 >+#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 >+#define mmDP3_DP_SEC_PACKET_CNTL 0x2436 >+#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 >+#define mmDP3_DP_MSE_RATE_CNTL 0x2437 >+#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 >+#define mmDP3_DP_MSE_RATE_UPDATE 0x2439 >+#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 >+#define mmDP3_DP_MSE_SAT0 0x243a >+#define mmDP3_DP_MSE_SAT0_BASE_IDX 2 >+#define mmDP3_DP_MSE_SAT1 0x243b >+#define mmDP3_DP_MSE_SAT1_BASE_IDX 2 >+#define mmDP3_DP_MSE_SAT2 0x243c >+#define mmDP3_DP_MSE_SAT2_BASE_IDX 2 >+#define mmDP3_DP_MSE_SAT_UPDATE 0x243d >+#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 >+#define mmDP3_DP_MSE_LINK_TIMING 0x243e >+#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 >+#define mmDP3_DP_MSE_MISC_CNTL 0x243f >+#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 >+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 >+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 >+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 >+#define mmDP3_DP_MSE_SAT0_STATUS 0x2447 >+#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 >+#define mmDP3_DP_MSE_SAT1_STATUS 0x2448 >+#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 >+#define mmDP3_DP_MSE_SAT2_STATUS 0x2449 >+#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 >+#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c >+#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 >+#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d >+#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 >+#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e >+#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 >+#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f >+#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 >+#define mmDP3_DP_MSO_CNTL 0x2450 >+#define mmDP3_DP_MSO_CNTL_BASE_IDX 2 >+#define mmDP3_DP_MSO_CNTL1 0x2451 >+#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2 >+#define mmDP3_DP_DSC_CNTL 0x2452 >+#define mmDP3_DP_DSC_CNTL_BASE_IDX 2 >+#define mmDP3_DP_SEC_CNTL2 0x2453 >+#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2 >+#define mmDP3_DP_SEC_CNTL3 0x2454 >+#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2 >+#define mmDP3_DP_SEC_CNTL4 0x2455 >+#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2 >+#define mmDP3_DP_SEC_CNTL5 0x2456 >+#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2 >+#define mmDP3_DP_SEC_CNTL6 0x2457 >+#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2 >+#define mmDP3_DP_SEC_CNTL7 0x2458 >+#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2 >+#define mmDP3_DP_DB_CNTL 0x2459 >+#define mmDP3_DP_DB_CNTL_BASE_IDX 2 >+#define mmDP3_DP_MSA_VBID_MISC 0x245a >+#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2 >+#define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b >+#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 >+#define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c >+#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmDP3_DP_ALPM_CNTL 0x245d >+#define mmDP3_DP_ALPM_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dig4_dispdec >+// base address: 0x1000 >+#define mmDIG4_DIG_FE_CNTL 0x2468 >+#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2 >+#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469 >+#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 >+#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a >+#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 >+#define mmDIG4_DIG_CLOCK_PATTERN 0x246b >+#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 >+#define mmDIG4_DIG_TEST_PATTERN 0x246c >+#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2 >+#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d >+#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 >+#define mmDIG4_DIG_FIFO_STATUS 0x246e >+#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2 >+#define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x246f >+#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x2470 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 >+#define mmDIG4_HDMI_CONTROL 0x2471 >+#define mmDIG4_HDMI_CONTROL_BASE_IDX 2 >+#define mmDIG4_HDMI_STATUS 0x2472 >+#define mmDIG4_HDMI_STATUS_BASE_IDX 2 >+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473 >+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474 >+#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475 >+#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476 >+#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477 >+#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 >+#define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479 >+#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDIG4_HDMI_GC 0x247b >+#define mmDIG4_HDMI_GC_BASE_IDX 2 >+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c >+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC1_0 0x247d >+#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC1_1 0x247e >+#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC1_2 0x247f >+#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC1_3 0x2480 >+#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC1_4 0x2481 >+#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC2_0 0x2482 >+#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC2_1 0x2483 >+#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC2_2 0x2484 >+#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2 >+#define mmDIG4_AFMT_ISRC2_3 0x2485 >+#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 >+#define mmDIG4_HDMI_DB_CONTROL 0x2488 >+#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2 >+#define mmDIG4_DME_CONTROL 0x2489 >+#define mmDIG4_DME_CONTROL_BASE_IDX 2 >+#define mmDIG4_AFMT_MPEG_INFO0 0x248a >+#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2 >+#define mmDIG4_AFMT_MPEG_INFO1 0x248b >+#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_HDR 0x248c >+#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_0 0x248d >+#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_1 0x248e >+#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_2 0x248f >+#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_3 0x2490 >+#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_4 0x2491 >+#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_5 0x2492 >+#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_6 0x2493 >+#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2 >+#define mmDIG4_AFMT_GENERIC_7 0x2494 >+#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_32_0 0x2496 >+#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_32_1 0x2497 >+#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_44_0 0x2498 >+#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_44_1 0x2499 >+#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_48_0 0x249a >+#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_48_1 0x249b >+#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_STATUS_0 0x249c >+#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 >+#define mmDIG4_HDMI_ACR_STATUS_1 0x249d >+#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 >+#define mmDIG4_AFMT_AUDIO_INFO0 0x249e >+#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2 >+#define mmDIG4_AFMT_AUDIO_INFO1 0x249f >+#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2 >+#define mmDIG4_AFMT_60958_0 0x24a0 >+#define mmDIG4_AFMT_60958_0_BASE_IDX 2 >+#define mmDIG4_AFMT_60958_1 0x24a1 >+#define mmDIG4_AFMT_60958_1_BASE_IDX 2 >+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2 >+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 >+#define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3 >+#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2 >+#define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4 >+#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2 >+#define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5 >+#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2 >+#define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6 >+#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2 >+#define mmDIG4_AFMT_60958_2 0x24a7 >+#define mmDIG4_AFMT_60958_2_BASE_IDX 2 >+#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8 >+#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 >+#define mmDIG4_AFMT_STATUS 0x24a9 >+#define mmDIG4_AFMT_STATUS_BASE_IDX 2 >+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa >+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab >+#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 >+#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac >+#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 >+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad >+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 >+#define mmDIG4_DIG_BE_CNTL 0x24af >+#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2 >+#define mmDIG4_DIG_BE_EN_CNTL 0x24b0 >+#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 >+#define mmDIG4_TMDS_CNTL 0x24d3 >+#define mmDIG4_TMDS_CNTL_BASE_IDX 2 >+#define mmDIG4_TMDS_CONTROL_CHAR 0x24d4 >+#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 >+#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5 >+#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 >+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6 >+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 >+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7 >+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 >+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8 >+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 >+#define mmDIG4_TMDS_CTL_BITS 0x24da >+#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2 >+#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db >+#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 >+#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24dc >+#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 >+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd >+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 >+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de >+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 >+#define mmDIG4_DIG_VERSION 0x24e0 >+#define mmDIG4_DIG_VERSION_BASE_IDX 2 >+#define mmDIG4_DIG_LANE_ENABLE 0x24e1 >+#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2 >+#define mmDIG4_AFMT_CNTL 0x24e6 >+#define mmDIG4_AFMT_CNTL_BASE_IDX 2 >+#define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7 >+#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x24f6 >+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 >+#define mmDIG4_FORCE_DIG_DISABLE 0x24f7 >+#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dio_dp4_dispdec >+// base address: 0x1000 >+#define mmDP4_DP_LINK_CNTL 0x2508 >+#define mmDP4_DP_LINK_CNTL_BASE_IDX 2 >+#define mmDP4_DP_PIXEL_FORMAT 0x2509 >+#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2 >+#define mmDP4_DP_MSA_COLORIMETRY 0x250a >+#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 >+#define mmDP4_DP_CONFIG 0x250b >+#define mmDP4_DP_CONFIG_BASE_IDX 2 >+#define mmDP4_DP_VID_STREAM_CNTL 0x250c >+#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 >+#define mmDP4_DP_STEER_FIFO 0x250d >+#define mmDP4_DP_STEER_FIFO_BASE_IDX 2 >+#define mmDP4_DP_MSA_MISC 0x250e >+#define mmDP4_DP_MSA_MISC_BASE_IDX 2 >+#define mmDP4_DP_VID_TIMING 0x2510 >+#define mmDP4_DP_VID_TIMING_BASE_IDX 2 >+#define mmDP4_DP_VID_N 0x2511 >+#define mmDP4_DP_VID_N_BASE_IDX 2 >+#define mmDP4_DP_VID_M 0x2512 >+#define mmDP4_DP_VID_M_BASE_IDX 2 >+#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513 >+#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 >+#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514 >+#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 >+#define mmDP4_DP_VID_MSA_VBID 0x2515 >+#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2 >+#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516 >+#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_CNTL 0x2517 >+#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 >+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_SYM0 0x2519 >+#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2 >+#define mmDP4_DP_DPHY_SYM1 0x251a >+#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2 >+#define mmDP4_DP_DPHY_SYM2 0x251b >+#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2 >+#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c >+#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d >+#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e >+#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_CRC_EN 0x251f >+#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2 >+#define mmDP4_DP_DPHY_CRC_CNTL 0x2520 >+#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_CRC_RESULT 0x2521 >+#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 >+#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522 >+#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523 >+#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 >+#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524 >+#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 >+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 >+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 >+#define mmDP4_DP_SEC_CNTL 0x252b >+#define mmDP4_DP_SEC_CNTL_BASE_IDX 2 >+#define mmDP4_DP_SEC_CNTL1 0x252c >+#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2 >+#define mmDP4_DP_SEC_FRAMING1 0x252d >+#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2 >+#define mmDP4_DP_SEC_FRAMING2 0x252e >+#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2 >+#define mmDP4_DP_SEC_FRAMING3 0x252f >+#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2 >+#define mmDP4_DP_SEC_FRAMING4 0x2530 >+#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2 >+#define mmDP4_DP_SEC_AUD_N 0x2531 >+#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2 >+#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532 >+#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 >+#define mmDP4_DP_SEC_AUD_M 0x2533 >+#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2 >+#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534 >+#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 >+#define mmDP4_DP_SEC_TIMESTAMP 0x2535 >+#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 >+#define mmDP4_DP_SEC_PACKET_CNTL 0x2536 >+#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 >+#define mmDP4_DP_MSE_RATE_CNTL 0x2537 >+#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 >+#define mmDP4_DP_MSE_RATE_UPDATE 0x2539 >+#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 >+#define mmDP4_DP_MSE_SAT0 0x253a >+#define mmDP4_DP_MSE_SAT0_BASE_IDX 2 >+#define mmDP4_DP_MSE_SAT1 0x253b >+#define mmDP4_DP_MSE_SAT1_BASE_IDX 2 >+#define mmDP4_DP_MSE_SAT2 0x253c >+#define mmDP4_DP_MSE_SAT2_BASE_IDX 2 >+#define mmDP4_DP_MSE_SAT_UPDATE 0x253d >+#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 >+#define mmDP4_DP_MSE_LINK_TIMING 0x253e >+#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 >+#define mmDP4_DP_MSE_MISC_CNTL 0x253f >+#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 >+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 >+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 >+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 >+#define mmDP4_DP_MSE_SAT0_STATUS 0x2547 >+#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 >+#define mmDP4_DP_MSE_SAT1_STATUS 0x2548 >+#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 >+#define mmDP4_DP_MSE_SAT2_STATUS 0x2549 >+#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 >+#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c >+#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 >+#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d >+#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 >+#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e >+#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 >+#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f >+#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 >+#define mmDP4_DP_MSO_CNTL 0x2550 >+#define mmDP4_DP_MSO_CNTL_BASE_IDX 2 >+#define mmDP4_DP_MSO_CNTL1 0x2551 >+#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2 >+#define mmDP4_DP_DSC_CNTL 0x2552 >+#define mmDP4_DP_DSC_CNTL_BASE_IDX 2 >+#define mmDP4_DP_SEC_CNTL2 0x2553 >+#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2 >+#define mmDP4_DP_SEC_CNTL3 0x2554 >+#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2 >+#define mmDP4_DP_SEC_CNTL4 0x2555 >+#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2 >+#define mmDP4_DP_SEC_CNTL5 0x2556 >+#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2 >+#define mmDP4_DP_SEC_CNTL6 0x2557 >+#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2 >+#define mmDP4_DP_SEC_CNTL7 0x2558 >+#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2 >+#define mmDP4_DP_DB_CNTL 0x2559 >+#define mmDP4_DP_DB_CNTL_BASE_IDX 2 >+#define mmDP4_DP_MSA_VBID_MISC 0x255a >+#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2 >+#define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b >+#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 >+#define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c >+#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 >+#define mmDP4_DP_ALPM_CNTL 0x255d >+#define mmDP4_DP_ALPM_CNTL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcio_dcio_dispdec >+// base address: 0x0 >+#define mmDC_GENERICA 0x2868 >+#define mmDC_GENERICA_BASE_IDX 2 >+#define mmDC_GENERICB 0x2869 >+#define mmDC_GENERICB_BASE_IDX 2 >+#define mmDC_REF_CLK_CNTL 0x286b >+#define mmDC_REF_CLK_CNTL_BASE_IDX 2 >+#define mmUNIPHYA_LINK_CNTL 0x286d >+#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 >+#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e >+#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 >+#define mmUNIPHYB_LINK_CNTL 0x286f >+#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 >+#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 >+#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 >+#define mmUNIPHYC_LINK_CNTL 0x2871 >+#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2 >+#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 >+#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 >+#define mmUNIPHYD_LINK_CNTL 0x2873 >+#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2 >+#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 >+#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 >+#define mmUNIPHYE_LINK_CNTL 0x2875 >+#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2 >+#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 >+#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 >+#define mmDCIO_WRCMD_DELAY 0x287e >+#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 >+#define mmDC_PINSTRAPS 0x2880 >+#define mmDC_PINSTRAPS_BASE_IDX 2 >+#define mmLVTMA_PWRSEQ_CNTL 0x2883 >+#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 >+#define mmLVTMA_PWRSEQ_STATE 0x2884 >+#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 >+#define mmLVTMA_PWRSEQ_REF_DIV 0x2885 >+#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 >+#define mmLVTMA_PWRSEQ_DELAY1 0x2886 >+#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 >+#define mmLVTMA_PWRSEQ_DELAY2 0x2887 >+#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 >+#define mmBL_PWM_CNTL 0x2888 >+#define mmBL_PWM_CNTL_BASE_IDX 2 >+#define mmBL_PWM_CNTL2 0x2889 >+#define mmBL_PWM_CNTL2_BASE_IDX 2 >+#define mmBL_PWM_PERIOD_CNTL 0x288a >+#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 >+#define mmBL_PWM_GRP1_REG_LOCK 0x288b >+#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 >+#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c >+#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 >+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d >+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 >+#define mmDCIO_CLOCK_CNTL 0x2895 >+#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 >+#define mmDCIO_SOFT_RESET 0x289e >+#define mmDCIO_SOFT_RESET_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dcio_dcio_chip_dispdec >+// base address: 0x0 >+#define mmDC_GPIO_GENERIC_MASK 0x28c8 >+#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 >+#define mmDC_GPIO_GENERIC_A 0x28c9 >+#define mmDC_GPIO_GENERIC_A_BASE_IDX 2 >+#define mmDC_GPIO_GENERIC_EN 0x28ca >+#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 >+#define mmDC_GPIO_GENERIC_Y 0x28cb >+#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 >+#define mmDC_GPIO_DDC1_MASK 0x28d0 >+#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 >+#define mmDC_GPIO_DDC1_A 0x28d1 >+#define mmDC_GPIO_DDC1_A_BASE_IDX 2 >+#define mmDC_GPIO_DDC1_EN 0x28d2 >+#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 >+#define mmDC_GPIO_DDC1_Y 0x28d3 >+#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 >+#define mmDC_GPIO_DDC2_MASK 0x28d4 >+#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 >+#define mmDC_GPIO_DDC2_A 0x28d5 >+#define mmDC_GPIO_DDC2_A_BASE_IDX 2 >+#define mmDC_GPIO_DDC2_EN 0x28d6 >+#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 >+#define mmDC_GPIO_DDC2_Y 0x28d7 >+#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 >+#define mmDC_GPIO_DDC3_MASK 0x28d8 >+#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2 >+#define mmDC_GPIO_DDC3_A 0x28d9 >+#define mmDC_GPIO_DDC3_A_BASE_IDX 2 >+#define mmDC_GPIO_DDC3_EN 0x28da >+#define mmDC_GPIO_DDC3_EN_BASE_IDX 2 >+#define mmDC_GPIO_DDC3_Y 0x28db >+#define mmDC_GPIO_DDC3_Y_BASE_IDX 2 >+#define mmDC_GPIO_DDC4_MASK 0x28dc >+#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2 >+#define mmDC_GPIO_DDC4_A 0x28dd >+#define mmDC_GPIO_DDC4_A_BASE_IDX 2 >+#define mmDC_GPIO_DDC4_EN 0x28de >+#define mmDC_GPIO_DDC4_EN_BASE_IDX 2 >+#define mmDC_GPIO_DDC4_Y 0x28df >+#define mmDC_GPIO_DDC4_Y_BASE_IDX 2 >+#define mmDC_GPIO_DDC5_MASK 0x28e0 >+#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2 >+#define mmDC_GPIO_DDC5_A 0x28e1 >+#define mmDC_GPIO_DDC5_A_BASE_IDX 2 >+#define mmDC_GPIO_DDC5_EN 0x28e2 >+#define mmDC_GPIO_DDC5_EN_BASE_IDX 2 >+#define mmDC_GPIO_DDC5_Y 0x28e3 >+#define mmDC_GPIO_DDC5_Y_BASE_IDX 2 >+#define mmDC_GPIO_DDCVGA_MASK 0x28e8 >+#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 >+#define mmDC_GPIO_DDCVGA_A 0x28e9 >+#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 >+#define mmDC_GPIO_DDCVGA_EN 0x28ea >+#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 >+#define mmDC_GPIO_DDCVGA_Y 0x28eb >+#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 >+#define mmDC_GPIO_GENLK_MASK 0x28f0 >+#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 >+#define mmDC_GPIO_GENLK_A 0x28f1 >+#define mmDC_GPIO_GENLK_A_BASE_IDX 2 >+#define mmDC_GPIO_GENLK_EN 0x28f2 >+#define mmDC_GPIO_GENLK_EN_BASE_IDX 2 >+#define mmDC_GPIO_GENLK_Y 0x28f3 >+#define mmDC_GPIO_GENLK_Y_BASE_IDX 2 >+#define mmDC_GPIO_HPD_MASK 0x28f4 >+#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 >+#define mmDC_GPIO_HPD_A 0x28f5 >+#define mmDC_GPIO_HPD_A_BASE_IDX 2 >+#define mmDC_GPIO_HPD_EN 0x28f6 >+#define mmDC_GPIO_HPD_EN_BASE_IDX 2 >+#define mmDC_GPIO_HPD_Y 0x28f7 >+#define mmDC_GPIO_HPD_Y_BASE_IDX 2 >+#define mmDC_GPIO_PWRSEQ_MASK 0x28f8 >+#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 >+#define mmDC_GPIO_PWRSEQ_A 0x28f9 >+#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 >+#define mmDC_GPIO_PWRSEQ_EN 0x28fa >+#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 >+#define mmDC_GPIO_PWRSEQ_Y 0x28fb >+#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 >+#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc >+#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 >+#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd >+#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 >+#define mmPHY_AUX_CNTL 0x28ff >+#define mmPHY_AUX_CNTL_BASE_IDX 2 >+#define mmDC_GPIO_TX12_EN 0x2915 >+#define mmDC_GPIO_TX12_EN_BASE_IDX 2 >+#define mmDC_GPIO_AUX_CTRL_0 0x2916 >+#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 >+#define mmDC_GPIO_AUX_CTRL_1 0x2917 >+#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 >+#define mmDC_GPIO_AUX_CTRL_2 0x2918 >+#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 >+#define mmDC_GPIO_RXEN 0x2919 >+#define mmDC_GPIO_RXEN_BASE_IDX 2 >+#define mmDC_GPIO_PULLUPEN 0x291a >+#define mmDC_GPIO_PULLUPEN_BASE_IDX 2 >+#define mmDC_GPIO_AUX_CTRL_3 0x291b >+#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 >+#define mmDC_GPIO_AUX_CTRL_4 0x291c >+#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 >+#define mmDC_GPIO_AUX_CTRL_5 0x291d >+#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 >+#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e >+#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 >+ >+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec >+// base address: 0x0 >+#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000 >+#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 >+#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 >+#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec >+// base address: 0x0 >+#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005 >+#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 >+#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006 >+#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec >+// base address: 0x0 >+#define mmDSCC0_DSCC_CONFIG0 0x300a >+#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2 >+#define mmDSCC0_DSCC_CONFIG1 0x300b >+#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2 >+#define mmDSCC0_DSCC_STATUS 0x300c >+#define mmDSCC0_DSCC_STATUS_BASE_IDX 2 >+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d >+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e >+#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f >+#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010 >+#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011 >+#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012 >+#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013 >+#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014 >+#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015 >+#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016 >+#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017 >+#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018 >+#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019 >+#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a >+#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b >+#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c >+#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d >+#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e >+#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f >+#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020 >+#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021 >+#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022 >+#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023 >+#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 >+#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024 >+#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 >+#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 >+#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 >+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 >+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 >+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 >+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 >+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a >+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b >+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c >+#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 >+#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d >+#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 >+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e >+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f >+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 >+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 >+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 >+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 >+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 >+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 >+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a >+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+// base address: 0xc140 >+#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 >+#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 >+#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x3052 >+#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON19_PERFMON_CNTL 0x3053 >+#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON19_PERFMON_CNTL2 0x3054 >+#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 >+#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 >+#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON19_PERFMON_HI 0x3057 >+#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON19_PERFMON_LOW 0x3058 >+#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec >+// base address: 0x170 >+#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c >+#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 >+#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d >+#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec >+// base address: 0x170 >+#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061 >+#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 >+#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062 >+#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec >+// base address: 0x170 >+#define mmDSCC1_DSCC_CONFIG0 0x3066 >+#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2 >+#define mmDSCC1_DSCC_CONFIG1 0x3067 >+#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2 >+#define mmDSCC1_DSCC_STATUS 0x3068 >+#define mmDSCC1_DSCC_STATUS_BASE_IDX 2 >+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 >+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a >+#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b >+#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c >+#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d >+#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e >+#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f >+#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070 >+#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071 >+#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072 >+#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073 >+#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074 >+#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075 >+#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076 >+#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077 >+#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078 >+#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079 >+#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a >+#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b >+#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c >+#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d >+#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e >+#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f >+#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 >+#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080 >+#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 >+#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 >+#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 >+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 >+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 >+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 >+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 >+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 >+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 >+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 >+#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 >+#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 >+#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 >+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a >+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b >+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c >+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d >+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e >+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f >+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 >+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 >+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 >+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+// base address: 0xc2b0 >+#define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac >+#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad >+#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON20_PERFCOUNTER_STATE 0x30ae >+#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON20_PERFMON_CNTL 0x30af >+#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON20_PERFMON_CNTL2 0x30b0 >+#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 >+#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 >+#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON20_PERFMON_HI 0x30b3 >+#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON20_PERFMON_LOW 0x30b4 >+#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec >+// base address: 0x2e0 >+#define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8 >+#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 >+#define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 >+#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec >+// base address: 0x2e0 >+#define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd >+#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 >+#define mmDSCCIF2_DSCCIF_CONFIG1 0x30be >+#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec >+// base address: 0x2e0 >+#define mmDSCC2_DSCC_CONFIG0 0x30c2 >+#define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2 >+#define mmDSCC2_DSCC_CONFIG1 0x30c3 >+#define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2 >+#define mmDSCC2_DSCC_STATUS 0x30c4 >+#define mmDSCC2_DSCC_STATUS_BASE_IDX 2 >+#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 >+#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6 >+#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7 >+#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8 >+#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9 >+#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca >+#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb >+#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc >+#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd >+#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce >+#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf >+#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0 >+#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1 >+#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2 >+#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3 >+#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4 >+#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5 >+#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6 >+#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7 >+#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8 >+#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9 >+#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG20 0x30da >+#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG21 0x30db >+#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 >+#define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc >+#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 >+#define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd >+#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 >+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de >+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df >+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 >+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 >+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 >+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 >+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 >+#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 >+#define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 >+#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 >+#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 >+#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 >+#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 >+#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 >+#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea >+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb >+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec >+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed >+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 >+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+// base address: 0xc420 >+#define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 >+#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 >+#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON21_PERFCOUNTER_STATE 0x310a >+#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON21_PERFMON_CNTL 0x310b >+#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON21_PERFMON_CNTL2 0x310c >+#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d >+#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e >+#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON21_PERFMON_HI 0x310f >+#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON21_PERFMON_LOW 0x3110 >+#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec >+// base address: 0x450 >+#define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114 >+#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 >+#define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 >+#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec >+// base address: 0x450 >+#define mmDSCCIF3_DSCCIF_CONFIG0 0x3119 >+#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 >+#define mmDSCCIF3_DSCCIF_CONFIG1 0x311a >+#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec >+// base address: 0x450 >+#define mmDSCC3_DSCC_CONFIG0 0x311e >+#define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2 >+#define mmDSCC3_DSCC_CONFIG1 0x311f >+#define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2 >+#define mmDSCC3_DSCC_STATUS 0x3120 >+#define mmDSCC3_DSCC_STATUS_BASE_IDX 2 >+#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 >+#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG0 0x3122 >+#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG1 0x3123 >+#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG2 0x3124 >+#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG3 0x3125 >+#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG4 0x3126 >+#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG5 0x3127 >+#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG6 0x3128 >+#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG7 0x3129 >+#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG8 0x312a >+#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG9 0x312b >+#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG10 0x312c >+#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG11 0x312d >+#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG12 0x312e >+#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG13 0x312f >+#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG14 0x3130 >+#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG15 0x3131 >+#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG16 0x3132 >+#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG17 0x3133 >+#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG18 0x3134 >+#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG19 0x3135 >+#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG20 0x3136 >+#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG21 0x3137 >+#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 >+#define mmDSCC3_DSCC_PPS_CONFIG22 0x3138 >+#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 >+#define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 >+#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 >+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a >+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b >+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c >+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d >+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e >+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f >+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 >+#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 >+#define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 >+#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 >+#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 >+#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 >+#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 >+#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 >+#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 >+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 >+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 >+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 >+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e >+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 >+ >+// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+// base address: 0xc590 >+#define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x3164 >+#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x3165 >+#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON22_PERFCOUNTER_STATE 0x3166 >+#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON22_PERFMON_CNTL 0x3167 >+#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON22_PERFMON_CNTL2 0x3168 >+#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x3169 >+#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x316a >+#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON22_PERFMON_HI 0x316b >+#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON22_PERFMON_LOW 0x316c >+#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec >+// base address: 0x5c0 >+#define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170 >+#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2 >+#define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171 >+#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec >+// base address: 0x5c0 >+#define mmDSCCIF4_DSCCIF_CONFIG0 0x3175 >+#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2 >+#define mmDSCCIF4_DSCCIF_CONFIG1 0x3176 >+#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec >+// base address: 0x5c0 >+#define mmDSCC4_DSCC_CONFIG0 0x317a >+#define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2 >+#define mmDSCC4_DSCC_CONFIG1 0x317b >+#define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2 >+#define mmDSCC4_DSCC_STATUS 0x317c >+#define mmDSCC4_DSCC_STATUS_BASE_IDX 2 >+#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d >+#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG0 0x317e >+#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG1 0x317f >+#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG2 0x3180 >+#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG3 0x3181 >+#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG4 0x3182 >+#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG5 0x3183 >+#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG6 0x3184 >+#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG7 0x3185 >+#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG8 0x3186 >+#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG9 0x3187 >+#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG10 0x3188 >+#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG11 0x3189 >+#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG12 0x318a >+#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG13 0x318b >+#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG14 0x318c >+#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG15 0x318d >+#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG16 0x318e >+#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG17 0x318f >+#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG18 0x3190 >+#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG19 0x3191 >+#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG20 0x3192 >+#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG21 0x3193 >+#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2 >+#define mmDSCC4_DSCC_PPS_CONFIG22 0x3194 >+#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2 >+#define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195 >+#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 >+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196 >+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197 >+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198 >+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199 >+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a >+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b >+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c >+#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 >+#define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d >+#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 >+#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e >+#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f >+#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0 >+#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1 >+#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2 >+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3 >+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4 >+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5 >+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE 0x31aa >+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 >+ >+// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+// base address: 0xc700 >+#define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x31c0 >+#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x31c1 >+#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON23_PERFCOUNTER_STATE 0x31c2 >+#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON23_PERFMON_CNTL 0x31c3 >+#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON23_PERFMON_CNTL2 0x31c4 >+#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x31c5 >+#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x31c6 >+#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON23_PERFMON_HI 0x31c7 >+#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON23_PERFMON_LOW 0x31c8 >+#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec >+// base address: 0x730 >+#define mmDSC_TOP5_DSC_TOP_CONTROL 0x31cc >+#define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX 2 >+#define mmDSC_TOP5_DSC_DEBUG_CONTROL 0x31cd >+#define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec >+// base address: 0x730 >+#define mmDSCCIF5_DSCCIF_CONFIG0 0x31d1 >+#define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX 2 >+#define mmDSCCIF5_DSCCIF_CONFIG1 0x31d2 >+#define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec >+// base address: 0x730 >+#define mmDSCC5_DSCC_CONFIG0 0x31d6 >+#define mmDSCC5_DSCC_CONFIG0_BASE_IDX 2 >+#define mmDSCC5_DSCC_CONFIG1 0x31d7 >+#define mmDSCC5_DSCC_CONFIG1_BASE_IDX 2 >+#define mmDSCC5_DSCC_STATUS 0x31d8 >+#define mmDSCC5_DSCC_STATUS_BASE_IDX 2 >+#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS 0x31d9 >+#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG0 0x31da >+#define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG1 0x31db >+#define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG2 0x31dc >+#define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG3 0x31dd >+#define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG4 0x31de >+#define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG5 0x31df >+#define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG6 0x31e0 >+#define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG7 0x31e1 >+#define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG8 0x31e2 >+#define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG9 0x31e3 >+#define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG10 0x31e4 >+#define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG11 0x31e5 >+#define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG12 0x31e6 >+#define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG13 0x31e7 >+#define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG14 0x31e8 >+#define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG15 0x31e9 >+#define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG16 0x31ea >+#define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG17 0x31eb >+#define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG18 0x31ec >+#define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG19 0x31ed >+#define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG20 0x31ee >+#define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG21 0x31ef >+#define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX 2 >+#define mmDSCC5_DSCC_PPS_CONFIG22 0x31f0 >+#define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX 2 >+#define mmDSCC5_DSCC_MEM_POWER_CONTROL 0x31f1 >+#define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 >+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER 0x31f2 >+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER 0x31f3 >+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER 0x31f4 >+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER 0x31f5 >+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER 0x31f6 >+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 >+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER 0x31f7 >+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 >+#define mmDSCC5_DSCC_MAX_ABS_ERROR0 0x31f8 >+#define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 >+#define mmDSCC5_DSCC_MAX_ABS_ERROR1 0x31f9 >+#define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 >+#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x31fa >+#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x31fb >+#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31fc >+#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31fd >+#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31fe >+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31ff >+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3200 >+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201 >+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 >+#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE 0x3206 >+#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+// base address: 0xc870 >+#define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x321c >+#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x321d >+#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON24_PERFCOUNTER_STATE 0x321e >+#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2 >+#define mmDC_PERFMON24_PERFMON_CNTL 0x321f >+#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2 >+#define mmDC_PERFMON24_PERFMON_CNTL2 0x3220 >+#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2 >+#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x3221 >+#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 >+#define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x3222 >+#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2 >+#define mmDC_PERFMON24_PERFMON_HI 0x3223 >+#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2 >+#define mmDC_PERFMON24_PERFMON_LOW 0x3224 >+#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dmu_dmcub_dispdec >+// base address: 0x0 >+#define mmDMCUB_REGION0_OFFSET 0x3238 >+#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION0_OFFSET_HIGH 0x3239 >+#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION1_OFFSET 0x323a >+#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION1_OFFSET_HIGH 0x323b >+#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION2_OFFSET 0x323c >+#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION2_OFFSET_HIGH 0x323d >+#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION4_OFFSET 0x3240 >+#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION4_OFFSET_HIGH 0x3241 >+#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION5_OFFSET 0x3242 >+#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION5_OFFSET_HIGH 0x3243 >+#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION6_OFFSET 0x3244 >+#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION6_OFFSET_HIGH 0x3245 >+#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION7_OFFSET 0x3246 >+#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION7_OFFSET_HIGH 0x3247 >+#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION0_TOP_ADDRESS 0x3248 >+#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION1_TOP_ADDRESS 0x3249 >+#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION2_TOP_ADDRESS 0x324a >+#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION4_TOP_ADDRESS 0x324b >+#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION5_TOP_ADDRESS 0x324c >+#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION6_TOP_ADDRESS 0x324d >+#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION7_TOP_ADDRESS 0x324e >+#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x324f >+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x3250 >+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x3251 >+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x3252 >+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x3253 >+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x3254 >+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x3255 >+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x3256 >+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x3257 >+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x3258 >+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x3259 >+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x325a >+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x325b >+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x325c >+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x325d >+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x325e >+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW0_OFFSET 0x325f >+#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x3260 >+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW1_OFFSET 0x3261 >+#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x3262 >+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW2_OFFSET 0x3263 >+#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x3264 >+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW3_OFFSET 0x3265 >+#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x3266 >+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW4_OFFSET 0x3267 >+#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x3268 >+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW5_OFFSET 0x3269 >+#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x326a >+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW6_OFFSET 0x326b >+#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x326c >+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW7_OFFSET 0x326d >+#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 >+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x326e >+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 >+#define mmDMCUB_INTERRUPT_ENABLE 0x326f >+#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 >+#define mmDMCUB_INTERRUPT_ACK 0x3270 >+#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2 >+#define mmDMCUB_INTERRUPT_STATUS 0x3271 >+#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDMCUB_INTERRUPT_TYPE 0x3272 >+#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2 >+#define mmDMCUB_EXT_INTERRUPT_STATUS 0x3273 >+#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 >+#define mmDMCUB_EXT_INTERRUPT_CTXID 0x3274 >+#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 >+#define mmDMCUB_EXT_INTERRUPT_ACK 0x3275 >+#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 >+#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x3276 >+#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 >+#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x3277 >+#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 >+#define mmDMCUB_SEC_CNTL 0x3278 >+#define mmDMCUB_SEC_CNTL_BASE_IDX 2 >+#define mmDMCUB_MEM_CNTL 0x3279 >+#define mmDMCUB_MEM_CNTL_BASE_IDX 2 >+#define mmDMCUB_INBOX0_BASE_ADDRESS 0x327a >+#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_INBOX0_SIZE 0x327b >+#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2 >+#define mmDMCUB_INBOX0_WPTR 0x327c >+#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2 >+#define mmDMCUB_INBOX0_RPTR 0x327d >+#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2 >+#define mmDMCUB_INBOX1_BASE_ADDRESS 0x327e >+#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_INBOX1_SIZE 0x327f >+#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2 >+#define mmDMCUB_INBOX1_WPTR 0x3280 >+#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2 >+#define mmDMCUB_INBOX1_RPTR 0x3281 >+#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2 >+#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x3282 >+#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_OUTBOX0_SIZE 0x3283 >+#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2 >+#define mmDMCUB_OUTBOX0_WPTR 0x3284 >+#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2 >+#define mmDMCUB_OUTBOX0_RPTR 0x3285 >+#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2 >+#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x3286 >+#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 >+#define mmDMCUB_OUTBOX1_SIZE 0x3287 >+#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2 >+#define mmDMCUB_OUTBOX1_WPTR 0x3288 >+#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2 >+#define mmDMCUB_OUTBOX1_RPTR 0x3289 >+#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2 >+#define mmDMCUB_TIMER_TRIGGER0 0x328a >+#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2 >+#define mmDMCUB_TIMER_TRIGGER1 0x328b >+#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2 >+#define mmDMCUB_TIMER_WINDOW 0x328c >+#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2 >+#define mmDMCUB_SCRATCH0 0x328d >+#define mmDMCUB_SCRATCH0_BASE_IDX 2 >+#define mmDMCUB_SCRATCH1 0x328e >+#define mmDMCUB_SCRATCH1_BASE_IDX 2 >+#define mmDMCUB_SCRATCH2 0x328f >+#define mmDMCUB_SCRATCH2_BASE_IDX 2 >+#define mmDMCUB_SCRATCH3 0x3290 >+#define mmDMCUB_SCRATCH3_BASE_IDX 2 >+#define mmDMCUB_SCRATCH4 0x3291 >+#define mmDMCUB_SCRATCH4_BASE_IDX 2 >+#define mmDMCUB_SCRATCH5 0x3292 >+#define mmDMCUB_SCRATCH5_BASE_IDX 2 >+#define mmDMCUB_SCRATCH6 0x3293 >+#define mmDMCUB_SCRATCH6_BASE_IDX 2 >+#define mmDMCUB_SCRATCH7 0x3294 >+#define mmDMCUB_SCRATCH7_BASE_IDX 2 >+#define mmDMCUB_SCRATCH8 0x3295 >+#define mmDMCUB_SCRATCH8_BASE_IDX 2 >+#define mmDMCUB_SCRATCH9 0x3296 >+#define mmDMCUB_SCRATCH9_BASE_IDX 2 >+#define mmDMCUB_SCRATCH10 0x3297 >+#define mmDMCUB_SCRATCH10_BASE_IDX 2 >+#define mmDMCUB_SCRATCH11 0x3298 >+#define mmDMCUB_SCRATCH11_BASE_IDX 2 >+#define mmDMCUB_SCRATCH12 0x3299 >+#define mmDMCUB_SCRATCH12_BASE_IDX 2 >+#define mmDMCUB_SCRATCH13 0x329a >+#define mmDMCUB_SCRATCH13_BASE_IDX 2 >+#define mmDMCUB_SCRATCH14 0x329b >+#define mmDMCUB_SCRATCH14_BASE_IDX 2 >+#define mmDMCUB_SCRATCH15 0x329c >+#define mmDMCUB_SCRATCH15_BASE_IDX 2 >+#define mmDMCUB_CNTL 0x32a0 >+#define mmDMCUB_CNTL_BASE_IDX 2 >+#define mmDMCUB_GPINT_DATAIN0 0x32a1 >+#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2 >+#define mmDMCUB_GPINT_DATAIN1 0x32a2 >+#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2 >+#define mmDMCUB_GPINT_DATAOUT 0x32a3 >+#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2 >+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x32a4 >+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 >+#define mmDMCUB_LS_WAKE_INT_ENABLE 0x32a5 >+#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 >+#define mmDMCUB_MEM_PWR_CNTL 0x32a6 >+#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2 >+#define mmDMCUB_TIMER_CURRENT 0x32a7 >+#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2 >+#define mmDMCUB_PROC_ID 0x32a9 >+#define mmDMCUB_PROC_ID_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec >+// base address: 0xc6b8 >+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x3460 >+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x3461 >+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x3462 >+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x3463 >+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x3464 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x3465 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x3466 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x3467 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x3468 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x3469 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x346a >+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x346b >+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x346c >+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x346d >+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x346e >+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x346f >+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x3470 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x3471 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x3472 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x3473 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x3474 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x3475 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x3476 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x3477 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x3478 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x3479 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x347a >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x347b >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x347c >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x347d >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x347e >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x347f >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x3480 >+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x3481 >+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x3482 >+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x3483 >+#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x3484 >+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x3485 >+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x3486 >+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 >+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x3487 >+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x3489 >+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x348a >+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x348b >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH 0x348c >+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x348d >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH 0x348e >+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x348f >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH 0x3490 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x3491 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH 0x3492 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION 0x3493 >+#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION 0x3494 >+#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION 0x3495 >+#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION 0x3496 >+#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 >+ >+ >+// addressBlock: dce_dc_dchvm_hvm_dispdec >+// base address: 0x0 >+#define mmDCHVM_CTRL0 0x016b >+#define mmDCHVM_CTRL0_BASE_IDX 3 >+#define mmDCHVM_CTRL1 0x016c >+#define mmDCHVM_CTRL1_BASE_IDX 3 >+#define mmDCHVM_CLK_CTRL 0x016d >+#define mmDCHVM_CLK_CTRL_BASE_IDX 3 >+#define mmDCHVM_MEM_CTRL 0x016e >+#define mmDCHVM_MEM_CTRL_BASE_IDX 3 >+#define mmDCHVM_RIOMMU_CTRL0 0x016f >+#define mmDCHVM_RIOMMU_CTRL0_BASE_IDX 3 >+#define mmDCHVM_RIOMMU_STAT0 0x0170 >+#define mmDCHVM_RIOMMU_STAT0_BASE_IDX 3 >+ >+ >+// addressBlock: vga_vgaseqind >+// base address: 0x0 >+#define ixSEQ00 0x0000 >+#define ixSEQ01 0x0001 >+#define ixSEQ02 0x0002 >+#define ixSEQ03 0x0003 >+#define ixSEQ04 0x0004 >+ >+ >+// addressBlock: vga_vgacrtind >+// base address: 0x0 >+#define ixCRT00 0x0000 >+#define ixCRT01 0x0001 >+#define ixCRT02 0x0002 >+#define ixCRT03 0x0003 >+#define ixCRT04 0x0004 >+#define ixCRT05 0x0005 >+#define ixCRT06 0x0006 >+#define ixCRT07 0x0007 >+#define ixCRT08 0x0008 >+#define ixCRT09 0x0009 >+#define ixCRT0A 0x000a >+#define ixCRT0B 0x000b >+#define ixCRT0C 0x000c >+#define ixCRT0D 0x000d >+#define ixCRT0E 0x000e >+#define ixCRT0F 0x000f >+#define ixCRT10 0x0010 >+#define ixCRT11 0x0011 >+#define ixCRT12 0x0012 >+#define ixCRT13 0x0013 >+#define ixCRT14 0x0014 >+#define ixCRT15 0x0015 >+#define ixCRT16 0x0016 >+#define ixCRT17 0x0017 >+#define ixCRT18 0x0018 >+#define ixCRT1E 0x001e >+#define ixCRT1F 0x001f >+#define ixCRT22 0x0022 >+ >+ >+// addressBlock: vga_vgagrphind >+// base address: 0x0 >+#define ixGRA00 0x0000 >+#define ixGRA01 0x0001 >+#define ixGRA02 0x0002 >+#define ixGRA03 0x0003 >+#define ixGRA04 0x0004 >+#define ixGRA05 0x0005 >+#define ixGRA06 0x0006 >+#define ixGRA07 0x0007 >+#define ixGRA08 0x0008 >+ >+ >+// addressBlock: vga_vgaattrind >+// base address: 0x0 >+#define ixATTR00 0x0000 >+#define ixATTR01 0x0001 >+#define ixATTR02 0x0002 >+#define ixATTR03 0x0003 >+#define ixATTR04 0x0004 >+#define ixATTR05 0x0005 >+#define ixATTR06 0x0006 >+#define ixATTR07 0x0007 >+#define ixATTR08 0x0008 >+#define ixATTR09 0x0009 >+#define ixATTR0A 0x000a >+#define ixATTR0B 0x000b >+#define ixATTR0C 0x000c >+#define ixATTR0D 0x000d >+#define ixATTR0E 0x000e >+#define ixATTR0F 0x000f >+#define ixATTR10 0x0010 >+#define ixATTR11 0x0011 >+#define ixATTR12 0x0012 >+#define ixATTR13 0x0013 >+#define ixATTR14 0x0014 >+ >+ >+// addressBlock: azendpoint_f2codecind >+// base address: 0x0 >+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 >+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 >+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d >+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e >+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 >+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e >+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 >+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 >+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 >+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a >+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 >+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 >+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e >+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 >+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c >+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e >+ >+ >+// addressBlock: azendpoint_descriptorind >+// base address: 0x0 >+#define ixAUDIO_DESCRIPTOR0 0x0001 >+#define ixAUDIO_DESCRIPTOR1 0x0002 >+#define ixAUDIO_DESCRIPTOR2 0x0003 >+#define ixAUDIO_DESCRIPTOR3 0x0004 >+#define ixAUDIO_DESCRIPTOR4 0x0005 >+#define ixAUDIO_DESCRIPTOR5 0x0006 >+#define ixAUDIO_DESCRIPTOR6 0x0007 >+#define ixAUDIO_DESCRIPTOR7 0x0008 >+#define ixAUDIO_DESCRIPTOR8 0x0009 >+#define ixAUDIO_DESCRIPTOR9 0x000a >+#define ixAUDIO_DESCRIPTOR10 0x000b >+#define ixAUDIO_DESCRIPTOR11 0x000c >+#define ixAUDIO_DESCRIPTOR12 0x000d >+#define ixAUDIO_DESCRIPTOR13 0x000e >+ >+ >+// addressBlock: azendpoint_sinkinfoind >+// base address: 0x0 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 >+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 >+#define ixSINK_DESCRIPTION0 0x0005 >+#define ixSINK_DESCRIPTION1 0x0006 >+#define ixSINK_DESCRIPTION2 0x0007 >+#define ixSINK_DESCRIPTION3 0x0008 >+#define ixSINK_DESCRIPTION4 0x0009 >+#define ixSINK_DESCRIPTION5 0x000a >+#define ixSINK_DESCRIPTION6 0x000b >+#define ixSINK_DESCRIPTION7 0x000c >+#define ixSINK_DESCRIPTION8 0x000d >+#define ixSINK_DESCRIPTION9 0x000e >+#define ixSINK_DESCRIPTION10 0x000f >+#define ixSINK_DESCRIPTION11 0x0010 >+#define ixSINK_DESCRIPTION12 0x0011 >+#define ixSINK_DESCRIPTION13 0x0012 >+#define ixSINK_DESCRIPTION14 0x0013 >+#define ixSINK_DESCRIPTION15 0x0014 >+#define ixSINK_DESCRIPTION16 0x0015 >+#define ixSINK_DESCRIPTION17 0x0016 >+ >+ >+// addressBlock: azf0controller_azinputcrc0resultind >+// base address: 0x0 >+#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 >+#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 >+#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 >+#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 >+#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 >+#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 >+#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 >+#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 >+ >+ >+// addressBlock: azf0controller_azinputcrc1resultind >+// base address: 0x0 >+#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 >+#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 >+#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 >+#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 >+#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 >+#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 >+#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 >+#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 >+ >+ >+// addressBlock: azf0controller_azcrc0resultind >+// base address: 0x0 >+#define ixAZALIA_CRC0_CHANNEL0 0x0000 >+#define ixAZALIA_CRC0_CHANNEL1 0x0001 >+#define ixAZALIA_CRC0_CHANNEL2 0x0002 >+#define ixAZALIA_CRC0_CHANNEL3 0x0003 >+#define ixAZALIA_CRC0_CHANNEL4 0x0004 >+#define ixAZALIA_CRC0_CHANNEL5 0x0005 >+#define ixAZALIA_CRC0_CHANNEL6 0x0006 >+#define ixAZALIA_CRC0_CHANNEL7 0x0007 >+ >+ >+// addressBlock: azf0controller_azcrc1resultind >+// base address: 0x0 >+#define ixAZALIA_CRC1_CHANNEL0 0x0000 >+#define ixAZALIA_CRC1_CHANNEL1 0x0001 >+#define ixAZALIA_CRC1_CHANNEL2 0x0002 >+#define ixAZALIA_CRC1_CHANNEL3 0x0003 >+#define ixAZALIA_CRC1_CHANNEL4 0x0004 >+#define ixAZALIA_CRC1_CHANNEL5 0x0005 >+#define ixAZALIA_CRC1_CHANNEL6 0x0006 >+#define ixAZALIA_CRC1_CHANNEL7 0x0007 >+ >+ >+// addressBlock: azinputendpoint_f2codecind >+// base address: 0x0 >+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 >+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 >+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d >+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 >+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a >+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d >+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e >+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 >+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c >+ >+ >+// addressBlock: azroot_f2codecind >+// base address: 0x0 >+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 >+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 >+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 >+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 >+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 >+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 >+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 >+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 >+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 >+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff >+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 >+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 >+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a >+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b >+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f >+ >+ >+// addressBlock: azf0stream0_streamind >+// base address: 0x0 >+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream1_streamind >+// base address: 0x0 >+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream2_streamind >+// base address: 0x0 >+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream3_streamind >+// base address: 0x0 >+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream4_streamind >+// base address: 0x0 >+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream5_streamind >+// base address: 0x0 >+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream6_streamind >+// base address: 0x0 >+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream7_streamind >+// base address: 0x0 >+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream8_streamind >+// base address: 0x0 >+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream9_streamind >+// base address: 0x0 >+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream10_streamind >+// base address: 0x0 >+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream11_streamind >+// base address: 0x0 >+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream12_streamind >+// base address: 0x0 >+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream13_streamind >+// base address: 0x0 >+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream14_streamind >+// base address: 0x0 >+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0stream15_streamind >+// base address: 0x0 >+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 >+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 >+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 >+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 >+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 >+ >+ >+// addressBlock: azf0endpoint0_endpointind >+// base address: 0x0 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 >+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 >+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a >+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b >+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c >+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d >+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e >+ >+ >+// addressBlock: azf0endpoint1_endpointind >+// base address: 0x0 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 >+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 >+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a >+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b >+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c >+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d >+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e >+ >+ >+// addressBlock: azf0endpoint2_endpointind >+// base address: 0x0 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 >+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 >+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a >+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b >+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c >+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d >+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e >+ >+ >+// addressBlock: azf0endpoint3_endpointind >+// base address: 0x0 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 >+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 >+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a >+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b >+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c >+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d >+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e >+ >+ >+// addressBlock: azf0endpoint4_endpointind >+// base address: 0x0 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 >+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 >+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a >+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b >+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c >+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d >+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e >+ >+ >+// addressBlock: azf0endpoint5_endpointind >+// base address: 0x0 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 >+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 >+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a >+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b >+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c >+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d >+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e >+ >+ >+// addressBlock: azf0endpoint6_endpointind >+// base address: 0x0 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 >+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 >+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a >+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b >+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c >+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d >+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e >+ >+ >+// addressBlock: azf0endpoint7_endpointind >+// base address: 0x0 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 >+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 >+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a >+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b >+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c >+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d >+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e >+ >+ >+// addressBlock: azf0inputendpoint0_inputendpointind >+// base address: 0x0 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 >+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 >+ >+ >+// addressBlock: azf0inputendpoint1_inputendpointind >+// base address: 0x0 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 >+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 >+ >+ >+// addressBlock: azf0inputendpoint2_inputendpointind >+// base address: 0x0 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 >+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 >+ >+ >+// addressBlock: azf0inputendpoint3_inputendpointind >+// base address: 0x0 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 >+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 >+ >+ >+// addressBlock: azf0inputendpoint4_inputendpointind >+// base address: 0x0 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 >+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 >+ >+ >+// addressBlock: azf0inputendpoint5_inputendpointind >+// base address: 0x0 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 >+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 >+ >+ >+// addressBlock: azf0inputendpoint6_inputendpointind >+// base address: 0x0 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 >+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 >+ >+ >+// addressBlock: azf0inputendpoint7_inputendpointind >+// base address: 0x0 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 >+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 >+ >+ >+#endif >diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h >--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h 1969-12-31 18:00:00.000000000 -0600 >+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h 2019-08-31 15:01:11.885736171 -0500 >@@ -0,0 +1,56638 @@ >+/* >+ * Copyright (C) 2019 Advanced Micro Devices, Inc. >+ * >+ * Permission is hereby granted, free of charge, to any person obtaining a >+ * copy of this software and associated documentation files (the "Software"), >+ * to deal in the Software without restriction, including without limitation >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, >+ * and/or sell copies of the Software, and to permit persons to whom the >+ * Software is furnished to do so, subject to the following conditions: >+ * >+ * The above copyright notice and this permission notice shall be included >+ * in all copies or substantial portions of the Software. >+ * >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN >+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN >+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. >+ */ >+#ifndef _dcn_2_1_0_SH_MASK_HEADER >+#define _dcn_2_1_0_SH_MASK_HEADER >+ >+ >+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] >+//VGA_MEM_WRITE_PAGE_ADDR >+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 >+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 >+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL >+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L >+//VGA_MEM_READ_PAGE_ADDR >+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 >+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 >+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL >+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L >+// addressBlock: dce_dc_mmhubbub_vga_dispdec >+//VGA_RENDER_CONTROL >+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 >+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 >+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 >+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 >+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 >+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 >+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 >+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL >+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L >+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L >+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L >+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L >+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L >+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L >+//VGA_SEQUENCER_RESET_CONTROL >+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 >+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 >+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 >+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 >+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 >+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 >+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 >+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 >+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa >+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb >+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc >+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd >+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 >+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 >+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 >+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L >+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L >+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L >+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L >+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L >+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L >+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L >+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L >+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L >+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L >+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L >+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L >+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L >+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L >+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L >+//VGA_MODE_CONTROL >+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 >+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 >+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 >+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 >+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18 >+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L >+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L >+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L >+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L >+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L >+//VGA_SURFACE_PITCH_SELECT >+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 >+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 >+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L >+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L >+//VGA_MEMORY_BASE_ADDRESS >+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 >+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL >+//VGA_DISPBUF1_SURFACE_ADDR >+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 >+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL >+//VGA_DISPBUF2_SURFACE_ADDR >+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 >+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL >+//VGA_MEMORY_BASE_ADDRESS_HIGH >+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 >+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//VGA_HDP_CONTROL >+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 >+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 >+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 >+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 >+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 >+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L >+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L >+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L >+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L >+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L >+//VGA_CACHE_CONTROL >+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 >+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 >+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 >+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 >+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 >+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L >+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L >+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L >+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L >+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L >+//D1VGA_CONTROL >+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 >+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 >+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 >+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 >+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 >+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L >+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L >+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L >+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L >+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L >+//D2VGA_CONTROL >+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 >+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 >+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 >+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 >+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 >+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L >+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L >+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L >+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L >+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L >+//VGA_STATUS >+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 >+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 >+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 >+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 >+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L >+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L >+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L >+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L >+//VGA_INTERRUPT_CONTROL >+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 >+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 >+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 >+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 >+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L >+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L >+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L >+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L >+//VGA_STATUS_CLEAR >+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 >+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 >+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 >+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 >+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L >+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L >+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L >+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L >+//VGA_INTERRUPT_STATUS >+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 >+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 >+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 >+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 >+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L >+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L >+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L >+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L >+//VGA_MAIN_CONTROL >+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 >+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 >+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 >+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 >+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc >+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 >+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 >+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a >+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d >+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f >+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L >+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L >+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L >+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L >+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L >+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L >+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L >+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L >+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L >+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L >+//VGA_TEST_CONTROL >+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 >+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 >+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 >+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 >+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L >+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L >+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L >+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L >+//VGA_QOS_CTRL >+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0 >+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4 >+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL >+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L >+//D3VGA_CONTROL >+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 >+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 >+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 >+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 >+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 >+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L >+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L >+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L >+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L >+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L >+//D4VGA_CONTROL >+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 >+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 >+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 >+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 >+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 >+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L >+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L >+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L >+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L >+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L >+//D5VGA_CONTROL >+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 >+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 >+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 >+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 >+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 >+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L >+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L >+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L >+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L >+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L >+//D6VGA_CONTROL >+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 >+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 >+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 >+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 >+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 >+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L >+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L >+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L >+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L >+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L >+//VGA_SOURCE_SELECT >+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 >+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 >+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L >+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L >+ >+ >+// addressBlock: dce_dc_dccg_dccg_dispdec >+//PHYPLLA_PIXCLK_RESYNC_CNTL >+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 >+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 >+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 >+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 >+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L >+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L >+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L >+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L >+//PHYPLLB_PIXCLK_RESYNC_CNTL >+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 >+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 >+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 >+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 >+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L >+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L >+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L >+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L >+//PHYPLLC_PIXCLK_RESYNC_CNTL >+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 >+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 >+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 >+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 >+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L >+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L >+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L >+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L >+//PHYPLLD_PIXCLK_RESYNC_CNTL >+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 >+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 >+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 >+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 >+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L >+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L >+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L >+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L >+//DP_DTO_DBUF_EN >+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 >+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 >+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 >+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 >+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 >+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 >+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 >+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 >+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L >+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L >+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L >+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L >+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L >+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L >+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L >+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L >+//DPREFCLK_CGTT_BLK_CTRL_REG >+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 >+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 >+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL >+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L >+//REFCLK_CNTL >+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 >+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 >+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L >+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L >+//REFCLK_CGTT_BLK_CTRL_REG >+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 >+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 >+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL >+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L >+//PHYPLLE_PIXCLK_RESYNC_CNTL >+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 >+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 >+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 >+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 >+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L >+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L >+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L >+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L >+//DCCG_PERFMON_CNTL2 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L >+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L >+//DCCG_DS_DTO_INCR >+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 >+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL >+//DCCG_DS_DTO_MODULO >+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 >+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL >+//DCCG_DS_CNTL >+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 >+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 >+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 >+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 >+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 >+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 >+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 >+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L >+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L >+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L >+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L >+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L >+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L >+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L >+//DCCG_DS_HW_CAL_INTERVAL >+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 >+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL >+//DPREFCLK_CNTL >+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 >+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L >+//DCE_VERSION >+#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 >+#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 >+#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL >+#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L >+//DCCG_GTC_CNTL >+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 >+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L >+//DCCG_GTC_DTO_INCR >+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 >+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL >+//DCCG_GTC_DTO_MODULO >+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 >+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL >+//DCCG_GTC_CURRENT >+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 >+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL >+//DSCCLK0_DTO_PARAM >+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0 >+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10 >+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL >+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L >+//DSCCLK1_DTO_PARAM >+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0 >+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10 >+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL >+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L >+//DSCCLK2_DTO_PARAM >+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT 0x0 >+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT 0x10 >+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK 0x000000FFL >+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK 0x00FF0000L >+//MILLISECOND_TIME_BASE_DIV >+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 >+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 >+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL >+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L >+//DISPCLK_FREQ_CHANGE_CNTL >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 >+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c >+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d >+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L >+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L >+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L >+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L >+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L >+//DC_MEM_GLOBAL_PWR_REQ_CNTL >+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 >+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L >+//DCCG_PERFMON_CNTL >+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8 >+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb >+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L >+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L >+//DCCG_GATE_DISABLE_CNTL >+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 >+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 >+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 >+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 >+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 >+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 >+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 >+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 >+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa >+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb >+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT 0xc >+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 >+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 >+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 >+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 >+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 >+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a >+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b >+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c >+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d >+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e >+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L >+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L >+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L >+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L >+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L >+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L >+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L >+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L >+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L >+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L >+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK 0x00001000L >+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L >+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L >+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L >+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x00200000L >+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L >+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L >+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L >+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L >+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L >+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L >+//DISPCLK_CGTT_BLK_CTRL_REG >+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 >+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 >+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL >+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L >+//SOCCLK_CGTT_BLK_CTRL_REG >+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 >+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 >+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL >+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L >+//DCCG_CAC_STATUS >+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 >+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL >+//MICROSECOND_TIME_BASE_DIV >+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 >+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 >+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 >+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 >+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 >+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL >+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L >+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L >+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L >+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L >+//DCCG_GATE_DISABLE_CNTL2 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L >+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L >+//SYMCLK_CGTT_BLK_CTRL_REG >+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 >+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 >+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL >+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L >+//DCCG_DISP_CNTL_REG >+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 >+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L >+//OTG0_PIXEL_RATE_CNTL >+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 >+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 >+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 >+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8 >+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9 >+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT 0xb >+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe >+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 >+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L >+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L >+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L >+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L >+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L >+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK 0x00000800L >+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L >+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L >+//DP_DTO0_PHASE >+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 >+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL >+//DP_DTO0_MODULO >+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 >+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL >+//OTG0_PHYPLL_PIXEL_RATE_CNTL >+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 >+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 >+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L >+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L >+//OTG1_PIXEL_RATE_CNTL >+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 >+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 >+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 >+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8 >+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 >+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT 0xb >+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe >+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 >+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L >+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L >+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L >+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L >+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L >+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK 0x00000800L >+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L >+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L >+//DP_DTO1_PHASE >+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 >+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL >+//DP_DTO1_MODULO >+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 >+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL >+//OTG1_PHYPLL_PIXEL_RATE_CNTL >+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 >+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 >+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L >+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L >+//OTG2_PIXEL_RATE_CNTL >+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 >+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 >+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 >+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT 0x8 >+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT 0x9 >+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT 0xb >+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT 0xe >+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT 0x10 >+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L >+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L >+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L >+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK 0x00000100L >+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK 0x00000200L >+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK 0x00000800L >+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK 0x0000C000L >+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK 0x0FFF0000L >+//DP_DTO2_PHASE >+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 >+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL >+//DP_DTO2_MODULO >+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 >+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL >+//OTG2_PHYPLL_PIXEL_RATE_CNTL >+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 >+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 >+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L >+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L >+//OTG3_PIXEL_RATE_CNTL >+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 >+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 >+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 >+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT 0x8 >+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT 0x9 >+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT 0xb >+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT 0xe >+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT 0x10 >+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L >+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L >+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L >+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK 0x00000100L >+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK 0x00000200L >+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK 0x00000800L >+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK 0x0000C000L >+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK 0x0FFF0000L >+//DP_DTO3_PHASE >+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 >+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL >+//DP_DTO3_MODULO >+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 >+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL >+//OTG3_PHYPLL_PIXEL_RATE_CNTL >+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 >+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 >+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L >+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L >+//DPPCLK_CGTT_BLK_CTRL_REG >+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 >+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 >+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL >+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L >+//DPPCLK0_DTO_PARAM >+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0 >+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 >+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL >+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L >+//DPPCLK1_DTO_PARAM >+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0 >+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 >+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL >+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L >+//DPPCLK2_DTO_PARAM >+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT 0x0 >+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10 >+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK 0x000000FFL >+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK 0x00FF0000L >+//DPPCLK3_DTO_PARAM >+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT 0x0 >+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10 >+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK 0x000000FFL >+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK 0x00FF0000L >+//DCCG_CAC_STATUS2 >+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0 >+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x0000007FL >+//SYMCLKA_CLOCK_ENABLE >+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 >+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 >+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 >+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L >+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L >+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L >+//SYMCLKB_CLOCK_ENABLE >+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 >+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 >+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 >+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L >+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L >+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L >+//SYMCLKC_CLOCK_ENABLE >+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 >+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 >+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 >+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L >+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L >+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L >+//SYMCLKD_CLOCK_ENABLE >+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 >+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 >+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 >+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L >+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L >+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L >+//SYMCLKE_CLOCK_ENABLE >+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 >+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 >+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 >+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L >+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L >+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L >+//DCCG_SOFT_RESET >+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 >+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 >+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 >+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 >+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 >+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 >+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc >+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd >+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe >+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf >+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 >+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 >+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 >+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 >+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 >+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 >+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L >+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L >+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L >+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L >+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L >+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L >+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L >+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L >+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L >+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L >+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L >+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L >+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L >+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L >+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L >+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L >+//DSCCLK_DTO_CTRL >+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT 0x0 >+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT 0x1 >+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT 0x2 >+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT 0x3 >+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT 0x4 >+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT 0x5 >+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE__SHIFT 0x6 >+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8 >+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9 >+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa >+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb >+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc >+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd >+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN__SHIFT 0xe >+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK 0x00000001L >+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK 0x00000002L >+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK 0x00000004L >+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK 0x00000008L >+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK 0x00000010L >+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK 0x00000020L >+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE_MASK 0x00000040L >+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L >+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L >+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L >+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L >+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L >+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L >+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN_MASK 0x00004000L >+//DCCG_AUDIO_DTO_SOURCE >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x00003000L >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x00010000L >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L >+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L >+//DCCG_AUDIO_DTO0_PHASE >+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 >+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL >+//DCCG_AUDIO_DTO0_MODULE >+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 >+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL >+//DCCG_AUDIO_DTO1_PHASE >+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 >+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL >+//DCCG_AUDIO_DTO1_MODULE >+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 >+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL >+//DCCG_VSYNC_OTG0_LATCH_VALUE >+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 >+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL >+//DCCG_VSYNC_OTG1_LATCH_VALUE >+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 >+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL >+//DCCG_VSYNC_OTG2_LATCH_VALUE >+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 >+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL >+//DCCG_VSYNC_OTG3_LATCH_VALUE >+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 >+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL >+//DCCG_VSYNC_OTG4_LATCH_VALUE >+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 >+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL >+//DCCG_VSYNC_OTG5_LATCH_VALUE >+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 >+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL >+//DPPCLK_DTO_CTRL >+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT 0x0 >+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1 >+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT 0x4 >+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5 >+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT 0x8 >+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9 >+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT 0xc >+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd >+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT 0x10 >+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11 >+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT 0x14 >+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15 >+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK 0x00000001L >+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L >+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK 0x00000010L >+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L >+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK 0x00000100L >+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L >+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK 0x00001000L >+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L >+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK 0x00010000L >+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L >+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK 0x00100000L >+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L >+//DCCG_VSYNC_CNT_CTRL >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT 0x1 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK 0x00000002L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L >+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L >+//DCCG_VSYNC_CNT_INT_CTRL >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9 >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L >+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L >+//FORCE_SYMCLK_DISABLE >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0 >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1 >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2 >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3 >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4 >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5 >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6 >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L >+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L >+//DCCG_TEST_CLK_SEL >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT 0xe >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK 0x0000C000L >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L >+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L >+ >+ >+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec >+//DENTIST_DISPCLK_CNTL >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L >+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L >+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L >+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L >+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L >+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L >+ >+ >+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec >+//DC_PERFMON0_PERFCOUNTER_CNTL >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON0_PERFCOUNTER_CNTL2 >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON0_PERFCOUNTER_STATE >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON0_PERFMON_CNTL >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON0_PERFMON_CNTL2 >+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON0_PERFMON_CVALUE_LOW >+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON0_PERFMON_HI >+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON0_PERFMON_LOW >+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec >+//DC_PERFMON1_PERFCOUNTER_CNTL >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON1_PERFCOUNTER_CNTL2 >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON1_PERFCOUNTER_STATE >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON1_PERFMON_CNTL >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON1_PERFMON_CNTL2 >+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON1_PERFMON_CVALUE_LOW >+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON1_PERFMON_HI >+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON1_PERFMON_LOW >+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dccg_dccg_pll_dispdec >+//PLL_MACRO_CNTL_RESERVED0 >+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED1 >+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED2 >+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED3 >+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED4 >+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED5 >+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED6 >+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED7 >+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED8 >+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED9 >+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED10 >+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED11 >+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED12 >+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED13 >+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED14 >+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED15 >+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED16 >+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED17 >+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED18 >+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED19 >+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED20 >+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED21 >+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED22 >+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED23 >+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED24 >+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED25 >+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED26 >+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED27 >+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED28 >+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED29 >+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED30 >+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED31 >+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED32 >+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED33 >+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED34 >+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED35 >+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED36 >+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED37 >+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED38 >+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED39 >+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED40 >+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+//PLL_MACRO_CNTL_RESERVED41 >+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 >+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dmu_rbbmif_dispdec >+//RBBMIF_TIMEOUT >+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 >+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 >+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL >+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L >+//RBBMIF_STATUS >+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 >+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xFFFFFFFFL >+//RBBMIF_STATUS_2 >+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT 0x0 >+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK 0x0000003FL >+//RBBMIF_INT_STATUS >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK 0x0003FFFCL >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L >+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L >+//RBBMIF_TIMEOUT_DIS >+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 >+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 >+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 >+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 >+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 >+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 >+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 >+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 >+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 >+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 >+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa >+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb >+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc >+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd >+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe >+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf >+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 >+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 >+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 >+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 >+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 >+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 >+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 >+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 >+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 >+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 >+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a >+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b >+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c >+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d >+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT 0x1e >+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT 0x1f >+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L >+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L >+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L >+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L >+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L >+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L >+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L >+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L >+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L >+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L >+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L >+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L >+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK 0x40000000L >+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK 0x80000000L >+//RBBMIF_TIMEOUT_DIS_2 >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT 0x0 >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT 0x1 >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT 0x2 >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT 0x3 >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT 0x4 >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT 0x5 >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK 0x00000001L >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK 0x00000002L >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK 0x00000004L >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK 0x00000008L >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK 0x00000010L >+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK 0x00000020L >+//RBBMIF_STATUS_FLAG >+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 >+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 >+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 >+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 >+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 >+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 >+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 >+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L >+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L >+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L >+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L >+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L >+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L >+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dmu_dc_pg_dispdec >+//DOMAIN0_PG_CONFIG >+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT 0x8 >+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK 0x00000100L >+//DOMAIN0_PG_STATUS >+#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN1_PG_CONFIG >+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT 0x8 >+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK 0x00000100L >+//DOMAIN1_PG_STATUS >+#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN2_PG_CONFIG >+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT 0x8 >+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK 0x00000100L >+//DOMAIN2_PG_STATUS >+#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN3_PG_CONFIG >+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT 0x8 >+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK 0x00000100L >+//DOMAIN3_PG_STATUS >+#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN4_PG_CONFIG >+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT 0x8 >+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK 0x00000100L >+//DOMAIN4_PG_STATUS >+#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN5_PG_CONFIG >+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT 0x8 >+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK 0x00000100L >+//DOMAIN5_PG_STATUS >+#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN6_PG_CONFIG >+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT 0x8 >+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK 0x00000100L >+//DOMAIN6_PG_STATUS >+#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN7_PG_CONFIG >+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT 0x8 >+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK 0x00000100L >+//DOMAIN7_PG_STATUS >+#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN16_PG_CONFIG >+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE__SHIFT 0x8 >+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE_MASK 0x00000100L >+//DOMAIN16_PG_STATUS >+#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN17_PG_CONFIG >+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE__SHIFT 0x8 >+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE_MASK 0x00000100L >+//DOMAIN17_PG_STATUS >+#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DOMAIN18_PG_CONFIG >+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON__SHIFT 0x0 >+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE__SHIFT 0x8 >+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON_MASK 0x00000001L >+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE_MASK 0x00000100L >+//DOMAIN18_PG_STATUS >+#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE__SHIFT 0x1c >+#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS__SHIFT 0x1e >+#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE_MASK 0x10000000L >+#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS_MASK 0xC0000000L >+//DCPG_INTERRUPT_STATUS >+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 >+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 >+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 >+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 >+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 >+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 >+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 >+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 >+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x8 >+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 >+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0xa >+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb >+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0xc >+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xd >+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0xe >+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xf >+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x10 >+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 >+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x12 >+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 >+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x14 >+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 >+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x16 >+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 >+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x18 >+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x19 >+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x1a >+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x1b >+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x1c >+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x1d >+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x1e >+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x1f >+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L >+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L >+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L >+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L >+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L >+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L >+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L >+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L >+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00000100L >+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L >+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00000400L >+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L >+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00001000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00004000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00010000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00040000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00100000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00400000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x01000000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x02000000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x04000000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x08000000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x10000000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x20000000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x40000000L >+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x80000000L >+//DCPG_INTERRUPT_STATUS_2 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x2 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x4 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x6 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT 0x8 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT 0xa >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT 0xb >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000004L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000010L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000040L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED_MASK 0x00000100L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED_MASK 0x00000400L >+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L >+//DCPG_INTERRUPT_CONTROL_1 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT 0x10 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x11 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT 0x12 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x13 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT 0x14 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x15 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT 0x16 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT 0x18 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x19 >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT 0x1a >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0x1b >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT 0x1c >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1d >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT 0x1e >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0x1f >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK 0x00010000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00020000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK 0x00040000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00080000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK 0x00100000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00200000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK 0x00400000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK 0x01000000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x02000000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK 0x04000000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x08000000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK 0x10000000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x20000000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK 0x40000000L >+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x80000000L >+//DCPG_INTERRUPT_CONTROL_2 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT 0x0 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x1 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT 0x2 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0x3 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT 0x4 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x5 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT 0x6 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0x7 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT 0x8 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x9 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT 0xa >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xb >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT 0xc >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0xd >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT 0xe >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT 0x10 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x11 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT 0x12 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x13 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT 0x14 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x15 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT 0x16 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x17 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT 0x18 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x19 >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT 0x1a >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x1b >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT 0x1c >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x1d >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT 0x1e >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x1f >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK 0x00000001L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000002L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK 0x00000004L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00000008L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK 0x00000010L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000020L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK 0x00000040L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00000080L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK 0x00000100L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000200L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK 0x00000400L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00000800L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK 0x00001000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00002000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK 0x00004000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK 0x00010000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00020000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK 0x00040000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00080000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK 0x00100000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00200000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK 0x00400000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00800000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK 0x01000000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x02000000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK 0x04000000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x08000000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK 0x10000000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x20000000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK 0x40000000L >+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x80000000L >+//DCPG_INTERRUPT_CONTROL_3 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT 0x0 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x1 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT 0x2 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x3 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT 0x4 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x5 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT 0x6 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT 0x8 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x9 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT 0xa >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0xb >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT 0xc >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0xd >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT 0xe >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0xf >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK__SHIFT 0x10 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR__SHIFT 0x11 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK__SHIFT 0x12 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT 0x13 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK__SHIFT 0x14 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR__SHIFT 0x15 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK__SHIFT 0x16 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT 0x17 >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK 0x00000001L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000002L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK 0x00000004L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000008L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK 0x00000010L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000020L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK 0x00000040L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK 0x00000100L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000200L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK 0x00000400L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000800L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK 0x00001000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00002000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK 0x00004000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00008000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK_MASK 0x00010000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR_MASK 0x00020000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK_MASK 0x00040000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR_MASK 0x00080000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK_MASK 0x00100000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR_MASK 0x00200000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK_MASK 0x00400000L >+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR_MASK 0x00800000L >+//DC_IP_REQUEST_CNTL >+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 >+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON2_PERFCOUNTER_CNTL >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON2_PERFCOUNTER_CNTL2 >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON2_PERFCOUNTER_STATE >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON2_PERFMON_CNTL >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON2_PERFMON_CNTL2 >+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON2_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON2_PERFMON_CVALUE_LOW >+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON2_PERFMON_HI >+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON2_PERFMON_LOW >+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dmu_dmu_misc_dispdec >+//CC_DC_PIPE_DIS >+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 >+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10 >+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL >+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L >+//DMU_CLK_CNTL >+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 >+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4 >+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x5 >+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x6 >+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x8 >+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT 0x9 >+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0xa >+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL >+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L >+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00000020L >+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000040L >+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000100L >+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK 0x00000200L >+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000400L >+//DMU_MEM_PWR_CNTL >+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x0 >+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x1 >+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0x3 >+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x4 >+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0x8 >+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0x9 >+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa >+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L >+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000006L >+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000008L >+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000030L >+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00000100L >+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00000200L >+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L >+//DMCU_SMU_INTERRUPT_CNTL >+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 >+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 >+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L >+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L >+//SMU_INTERRUPT_CONTROL >+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 >+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 >+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 >+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L >+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L >+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L >+//DMU_MISC_ALLOW_DS_FORCE >+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0 >+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4 >+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L >+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L >+ >+ >+// addressBlock: dce_dc_dmu_dmcu_dispdec >+//DMCU_CTRL >+#define DMCU_CTRL__RESET_UC__SHIFT 0x0 >+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 >+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 >+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 >+#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 >+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 >+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 >+#define DMCU_CTRL__RESET_UC_MASK 0x00000001L >+#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L >+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L >+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L >+#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L >+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L >+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L >+//DMCU_STATUS >+#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 >+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 >+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 >+#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L >+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L >+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L >+//DMCU_PC_START_ADDR >+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 >+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 >+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL >+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L >+//DMCU_FW_START_ADDR >+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 >+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 >+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL >+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L >+//DMCU_FW_END_ADDR >+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 >+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 >+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL >+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L >+//DMCU_FW_ISR_START_ADDR >+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 >+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 >+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL >+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L >+//DMCU_FW_CS_HI >+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 >+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL >+//DMCU_FW_CS_LO >+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 >+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL >+//DMCU_RAM_ACCESS_CTRL >+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 >+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 >+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 >+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 >+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 >+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 >+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L >+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L >+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L >+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L >+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L >+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L >+//DMCU_ERAM_WR_CTRL >+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 >+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 >+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 >+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL >+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L >+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L >+//DMCU_ERAM_WR_DATA >+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 >+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL >+//DMCU_ERAM_RD_CTRL >+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 >+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 >+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 >+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL >+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L >+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L >+//DMCU_ERAM_RD_DATA >+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 >+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL >+//DMCU_IRAM_WR_CTRL >+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 >+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL >+//DMCU_IRAM_WR_DATA >+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 >+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL >+//DMCU_IRAM_RD_CTRL >+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 >+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL >+//DMCU_IRAM_RD_DATA >+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 >+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL >+//DMCU_EVENT_TRIGGER >+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 >+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 >+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 >+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L >+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L >+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L >+//DMCU_UC_INTERNAL_INT_STATUS >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L >+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L >+//DMCU_SS_INTERRUPT_CNTL_STATUS >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L >+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L >+//DMCU_INTERRUPT_STATUS >+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 >+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 >+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 >+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 >+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 >+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 >+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 >+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 >+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa >+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa >+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb >+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0xc >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0xc >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0xd >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0xd >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0xe >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0xe >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0xf >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xf >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x10 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x10 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0x11 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x11 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 >+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 >+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 >+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 >+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 >+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a >+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a >+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b >+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b >+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c >+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c >+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d >+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d >+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L >+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L >+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L >+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L >+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L >+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L >+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L >+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L >+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L >+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L >+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L >+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00001000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00001000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00002000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00002000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00004000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00004000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00008000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00008000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00010000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00010000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00020000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00020000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L >+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L >+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L >+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L >+//DMCU_INTERRUPT_STATUS_1 >+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6 >+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6 >+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7 >+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7 >+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8 >+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8 >+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9 >+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9 >+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa >+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa >+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb >+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb >+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd >+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd >+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L >+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L >+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L >+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L >+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L >+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L >+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L >+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L >+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L >+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L >+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L >+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L >+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L >+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L >+//DMCU_INTERRUPT_TO_HOST_EN_MASK >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT 0x0 >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT 0x1 >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT 0x2 >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x3 >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x4 >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x5 >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK 0x00000001L >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK 0x00000002L >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK 0x00000004L >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000008L >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000010L >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000020L >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L >+//DMCU_INTERRUPT_TO_UC_EN_MASK >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L >+//DMCU_INTERRUPT_TO_UC_EN_MASK_1 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L >+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L >+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L >+//DC_DMCU_SCRATCH >+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 >+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL >+//DMCU_INT_CNT >+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 >+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 >+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 >+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL >+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L >+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L >+//DMCU_FW_CHECKSUM_SMPL_BYTE_POS >+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 >+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 >+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L >+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL >+//DMCU_UC_CLK_GATING_CNTL >+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 >+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 >+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 >+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L >+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L >+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L >+//MASTER_COMM_DATA_REG1 >+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 >+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 >+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 >+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 >+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL >+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L >+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L >+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L >+//MASTER_COMM_DATA_REG2 >+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 >+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 >+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 >+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 >+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL >+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L >+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L >+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L >+//MASTER_COMM_DATA_REG3 >+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 >+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 >+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 >+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 >+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL >+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L >+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L >+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L >+//MASTER_COMM_CMD_REG >+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 >+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 >+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 >+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 >+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL >+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L >+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L >+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L >+//MASTER_COMM_CNTL_REG >+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 >+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L >+//SLAVE_COMM_DATA_REG1 >+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 >+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 >+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 >+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 >+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL >+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L >+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L >+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L >+//SLAVE_COMM_DATA_REG2 >+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 >+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 >+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 >+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 >+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL >+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L >+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L >+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L >+//SLAVE_COMM_DATA_REG3 >+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 >+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 >+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 >+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 >+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL >+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L >+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L >+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L >+//SLAVE_COMM_CMD_REG >+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 >+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 >+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 >+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 >+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL >+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L >+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L >+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L >+//SLAVE_COMM_CNTL_REG >+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 >+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 >+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L >+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L >+//DMCU_PERFMON_INTERRUPT_STATUS1 >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L >+//DMCU_PERFMON_INTERRUPT_STATUS2 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L >+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L >+//DMCU_PERFMON_INTERRUPT_STATUS3 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L >+//DMCU_PERFMON_INTERRUPT_STATUS4 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L >+//DMCU_PERFMON_INTERRUPT_STATUS5 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x9 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x9 >+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000200L >+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000200L >+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L >+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L >+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L >+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L >+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x9 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000200L >+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L >+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L >+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L >+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L >+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x9 >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L >+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000200L >+//DMCU_DPRX_INTERRUPT_STATUS1 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L >+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L >+//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L >+//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L >+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L >+//DMCU_INTERRUPT_STATUS_CONTINUE >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x0 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x2 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x2 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x3 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x3 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x4 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x4 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x5 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0x5 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x6 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x6 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x7 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x7 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x8 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x8 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x9 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x9 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xa >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0xa >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xb >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0xb >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0xc >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0xc >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0xd >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0xd >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0xe >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xe >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0xf >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x10 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x10 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x11 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x12 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x13 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT 0x14 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT 0x14 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT 0x15 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT 0x15 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT 0x16 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT 0x16 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT 0x17 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT 0x17 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT 0x18 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT 0x18 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT 0x19 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT 0x19 >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT 0x1a >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT 0x1a >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT 0x1b >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT 0x1b >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT 0x1c >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT 0x1c >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x00000001L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x00000002L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00000004L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000004L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00000008L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000008L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00000010L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000010L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00000020L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00000020L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x00000040L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00000040L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x00000080L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00000080L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x00000100L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x00000100L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x00000200L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x00000200L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x00000400L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x00000800L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00001000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00001000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00002000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00004000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00004000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x00010000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00010000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00020000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x00040000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x00080000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK 0x00100000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK 0x00100000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK 0x00200000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK 0x00200000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK 0x00400000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK 0x00400000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK 0x00800000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK 0x00800000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK 0x01000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK 0x01000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK 0x02000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK 0x02000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK 0x04000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK 0x04000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK 0x08000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK 0x08000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK 0x10000000L >+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK 0x10000000L >+//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT 0x2 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT 0x5 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT 0x6 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT 0x7 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT 0x8 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xc >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xd >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xe >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xf >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x10 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x11 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT 0x14 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT 0x15 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT 0x16 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT 0x17 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT 0x18 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT 0x19 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT 0x1a >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT 0x1b >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x1c >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK 0x00000040L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK 0x00000080L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK 0x00000100L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK 0x00001000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK 0x00002000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK 0x00004000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK 0x00008000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK 0x00010000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK 0x00020000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK 0x00100000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK 0x00200000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK 0x00400000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK 0x00800000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK 0x01000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK 0x02000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK 0x04000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK 0x08000000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK 0x10000000L >+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x6 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x7 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x8 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xc >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xd >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xe >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xf >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x10 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x11 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT 0x14 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT 0x15 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT 0x16 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT 0x17 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT 0x18 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT 0x19 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1a >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1b >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x1c >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000040L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000080L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000100L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00001000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00002000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00004000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00008000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00010000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00020000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK 0x00100000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK 0x00200000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK 0x00400000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK 0x00800000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK 0x01000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK 0x02000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x04000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x08000000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x10000000L >+//DMCU_INT_CNT_CONTINUE >+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT 0x0 >+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT 0x8 >+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT 0x10 >+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK 0x000000FFL >+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK 0x0000FF00L >+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK 0x00FF0000L >+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x6 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x7 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x8 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT 0x10 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT 0x11 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT 0x12 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT 0x13 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT 0x14 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT 0x15 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT 0x16 >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000040L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000080L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000100L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK 0x00010000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK 0x00020000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK 0x00040000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK 0x00080000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK 0x00100000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK 0x00200000L >+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK 0x00400000L >+//DMCU_INTERRUPT_STATUS_2 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x0 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x1 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x1 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x2 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x2 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x3 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0x3 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT 0x4 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT 0x4 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT 0x5 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT 0x5 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x6 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x6 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x8 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0x8 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0x9 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT 0xa >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT 0xa >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT 0xb >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT 0xb >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT 0x10 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT 0x10 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT 0x11 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT 0x11 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT 0x12 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT 0x12 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT 0x13 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT 0x13 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT 0x14 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT 0x14 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT 0x15 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT 0x15 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT 0x16 >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT 0x16 >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000001L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000002L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000002L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000004L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000004L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000008L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00000008L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK 0x00000010L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK 0x00000010L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK 0x00000020L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK 0x00000020L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000040L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000040L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000100L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000100L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00000200L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK 0x00000400L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L >+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK 0x00000800L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK 0x00010000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK 0x00010000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK 0x00020000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK 0x00020000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK 0x00040000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK 0x00040000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK 0x00080000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK 0x00080000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK 0x00100000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK 0x00100000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK 0x00200000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK 0x00200000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK 0x00400000L >+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK 0x00400000L >+//DMCU_INTERRUPT_TO_UC_EN_MASK_2 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT 0x1 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT 0x2 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT 0x5 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x6 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x7 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x8 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x9 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT 0x10 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT 0x11 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT 0x12 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT 0x13 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT 0x14 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT 0x15 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT 0x16 >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000040L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000080L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000100L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000200L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK 0x00010000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK 0x00020000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK 0x00040000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK 0x00080000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK 0x00100000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK 0x00200000L >+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK 0x00400000L >+ >+ >+// addressBlock: dce_dc_dmu_ihc_dispdec >+//DC_GPU_TIMER_START_POSITION_V_UPDATE >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L >+//DC_GPU_TIMER_START_POSITION_VSTARTUP >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L >+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L >+//DC_GPU_TIMER_READ >+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 >+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL >+//DC_GPU_TIMER_READ_CNTL >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L >+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L >+//DISP_INTERRUPT_STATUS >+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE >+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE2 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE3 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE4 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE5 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE6 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE7 >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE8 >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE9 >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE10 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE11 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE12 >+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE13 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE14 >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE15 >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e >+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE16 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE17 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE18 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE19 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE20 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE21 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT 0xe >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK 0x00004000L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE22 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT 0xe >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK 0x00004000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L >+//DC_GPU_TIMER_START_POSITION_VREADY >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L >+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L >+//DC_GPU_TIMER_START_POSITION_FLIP >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L >+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L >+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L >+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L >+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L >+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L >+//DISP_INTERRUPT_STATUS_CONTINUE23 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1a >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1b >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x02000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x04000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x08000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L >+//DISP_INTERRUPT_STATUS_CONTINUE24 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x2 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x3 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x4 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x5 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x18 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x19 >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000004L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000008L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000010L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000020L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x01000000L >+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x02000000L >+//DCCG_INTERRUPT_DEST >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0 >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1 >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2 >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3 >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4 >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5 >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT 0xe >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT 0xf >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L >+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L >+//DMU_INTERRUPT_DEST >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0x4 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0x5 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0x6 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0x7 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0x8 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0x9 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0xa >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0xb >+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT 0xe >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT 0xf >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x10 >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT 0x11 >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT 0x12 >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x13 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x18 >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x19 >+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1a >+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT 0x1b >+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT 0x1c >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000010L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000020L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00000040L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00000080L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00000100L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00000200L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00000400L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00000800L >+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK 0x00004000L >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK 0x00008000L >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK 0x00010000L >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK 0x00020000L >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK 0x00040000L >+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK 0x00080000L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x01000000L >+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x02000000L >+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x04000000L >+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK 0x08000000L >+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK 0x10000000L >+//DCPG_INTERRUPT_DEST >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT 0x8 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT 0x9 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT 0xa >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT 0xb >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT 0xc >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT 0xd >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT 0xe >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT 0xf >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x18 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x19 >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1a >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1b >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1c >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1d >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1e >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1f >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK 0x00000100L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK 0x00000200L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK 0x00000400L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK 0x00000800L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK 0x00001000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK 0x00002000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK 0x00004000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK 0x00008000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK 0x01000000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK 0x02000000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK 0x04000000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK 0x08000000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK 0x10000000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK 0x20000000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK 0x40000000L >+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK 0x80000000L >+//DCPG_INTERRUPT_DEST2 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x6 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x7 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x8 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x9 >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xa >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xb >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000040L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000080L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000100L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000200L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000400L >+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000800L >+//MMHUBBUB_INTERRUPT_DEST >+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT 0x0 >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1 >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2 >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3 >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4 >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5 >+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK 0x00000001L >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L >+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L >+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+//WB_INTERRUPT_DEST >+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0x0 >+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1 >+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0x8 >+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9 >+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0xa >+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb >+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe >+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf >+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 >+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 >+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000001L >+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L >+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000100L >+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L >+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000400L >+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L >+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L >+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L >+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L >+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L >+//DCHUB_INTERRUPT_DEST >+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0 >+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1 >+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2 >+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x3 >+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4 >+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5 >+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6 >+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x7 >+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8 >+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9 >+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa >+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xb >+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc >+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd >+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe >+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xf >+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10 >+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11 >+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12 >+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x13 >+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14 >+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15 >+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16 >+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x17 >+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18 >+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19 >+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a >+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b >+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c >+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d >+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e >+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1f >+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L >+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L >+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L >+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000008L >+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L >+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L >+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L >+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000080L >+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L >+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L >+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L >+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000800L >+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L >+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L >+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L >+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00008000L >+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L >+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L >+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L >+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00080000L >+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L >+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L >+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L >+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00800000L >+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L >+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L >+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L >+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L >+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L >+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L >+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L >+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x80000000L >+//DCHUB_PERFCOUNTER_INTERRUPT_DEST >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1c >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1d >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x10000000L >+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x20000000L >+//DCHUB_INTERRUPT_DEST2 >+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0 >+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1 >+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2 >+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3 >+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4 >+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5 >+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6 >+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7 >+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8 >+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9 >+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa >+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb >+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc >+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd >+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe >+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf >+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18 >+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x19 >+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L >+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L >+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L >+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L >+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L >+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L >+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L >+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L >+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L >+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L >+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L >+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L >+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L >+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L >+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L >+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L >+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L >+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x02000000L >+//DPP_PERFCOUNTER_INTERRUPT_DEST >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L >+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L >+//MPC_INTERRUPT_DEST >+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0 >+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1 >+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2 >+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3 >+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4 >+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5 >+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6 >+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7 >+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L >+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L >+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L >+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L >+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L >+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L >+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L >+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L >+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+//OPP_INTERRUPT_DEST >+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+//OPTC_INTERRUPT_DEST >+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18 >+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19 >+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a >+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b >+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c >+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d >+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L >+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L >+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L >+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L >+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L >+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L >+//OTG0_INTERRUPT_DEST >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L >+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L >+//OTG1_INTERRUPT_DEST >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L >+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L >+//OTG2_INTERRUPT_DEST >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L >+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L >+//OTG3_INTERRUPT_DEST >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L >+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L >+//OTG4_INTERRUPT_DEST >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L >+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L >+//OTG5_INTERRUPT_DEST >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L >+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L >+//DIG_INTERRUPT_DEST >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9 >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L >+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L >+//I2C_DDC_HPD_INTERRUPT_DEST >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16 >+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x17 >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L >+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L >+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK 0x00800000L >+//DIO_INTERRUPT_DEST >+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc >+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd >+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L >+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L >+//DCIO_INTERRUPT_DEST >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0 >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1 >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2 >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3 >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4 >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5 >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6 >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10 >+#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST__SHIFT 0x18 >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L >+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L >+#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST_MASK 0x01000000L >+//HPD_INTERRUPT_DEST >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0 >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1 >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2 >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3 >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4 >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5 >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8 >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9 >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd >+#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST__SHIFT 0xe >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L >+#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST_MASK 0x00004000L >+//AZ_INTERRUPT_DEST >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16 >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17 >+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1e >+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1f >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x40000000L >+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x80000000L >+//AUX_INTERRUPT_DEST >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x10 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x11 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x12 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x13 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x14 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x15 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x16 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x17 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x18 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x19 >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x1a >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x1b >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00010000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00020000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00040000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00080000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00100000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00200000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00400000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00800000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x01000000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x02000000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x04000000L >+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x08000000L >+//DSC_INTERRUPT_DEST >+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x0 >+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1 >+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 >+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 >+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x4 >+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5 >+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x6 >+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x7 >+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x8 >+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9 >+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xa >+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xb >+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0xc >+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd >+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe >+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf >+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x10 >+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11 >+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 >+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 >+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x14 >+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15 >+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 >+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 >+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000001L >+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L >+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L >+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L >+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000010L >+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L >+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000040L >+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000080L >+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000100L >+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L >+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000400L >+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000800L >+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00001000L >+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L >+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L >+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L >+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00010000L >+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L >+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L >+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L >+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00100000L >+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L >+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L >+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L >+ >+ >+// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec >+//WB_ENABLE >+#define WB_ENABLE__WB_ENABLE__SHIFT 0x0 >+#define WB_ENABLE__WB_ENABLE_MASK 0x00000001L >+//WB_EC_CONFIG >+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 >+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 >+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 >+#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3 >+#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7 >+#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8 >+#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9 >+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc >+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe >+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf >+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15 >+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 >+#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE__SHIFT 0x18 >+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L >+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L >+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L >+#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L >+#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L >+#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L >+#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L >+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L >+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L >+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L >+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L >+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L >+#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE_MASK 0x03000000L >+//CNV_MODE >+#define CNV_MODE__CNV_OUT_BPC__SHIFT 0x4 >+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 >+#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc >+#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd >+#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf >+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 >+#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 >+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 >+#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 >+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 >+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1e >+#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f >+#define CNV_MODE__CNV_OUT_BPC_MASK 0x00000010L >+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L >+#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L >+#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L >+#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L >+#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L >+#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L >+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L >+#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L >+#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L >+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT_MASK 0x40000000L >+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L >+//CNV_WINDOW_START >+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 >+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 >+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL >+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L >+//CNV_WINDOW_SIZE >+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 >+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 >+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL >+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L >+//CNV_UPDATE >+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 >+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 >+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 >+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L >+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L >+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L >+//CNV_SOURCE_SIZE >+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 >+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 >+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL >+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L >+//CNV_TEST_CNTL >+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 >+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 >+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L >+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L >+//CNV_TEST_CRC_RED >+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 >+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 >+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L >+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L >+//CNV_TEST_CRC_GREEN >+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 >+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 >+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L >+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L >+//CNV_TEST_CRC_BLUE >+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 >+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 >+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L >+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L >+//WB_DEBUG_CTRL >+#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0 >+#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6 >+#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x00000001L >+#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0x000000C0L >+//WB_DBG_MODE >+#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0 >+#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1 >+#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2 >+#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3 >+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8 >+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10 >+#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x00000001L >+#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x00000002L >+#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x00000004L >+#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x00000008L >+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x00000100L >+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7FFF0000L >+//WB_HW_DEBUG >+#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0 >+#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xFFFFFFFFL >+//WB_SOFT_RESET >+#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 >+#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L >+//WB_WARM_UP_MODE_CTL1 >+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0 >+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10 >+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f >+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL >+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L >+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L >+//WB_WARM_UP_MODE_CTL2 >+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0 >+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x10 >+#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP__SHIFT 0x14 >+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000003FFL >+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00010000L >+#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP_MASK 0x00100000L >+//CNV_TEST_DEBUG_INDEX >+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//CNV_TEST_DEBUG_DATA >+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 >+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec >+//WBSCL_COEF_RAM_SELECT >+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 >+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8 >+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 >+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L >+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L >+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L >+//WBSCL_COEF_RAM_TAP_DATA >+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 >+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf >+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 >+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f >+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL >+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L >+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L >+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L >+//WBSCL_MODE >+#define WBSCL_MODE__WBSCL_MODE__SHIFT 0x0 >+#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH__SHIFT 0x4 >+#define WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L >+#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH_MASK 0x00000010L >+//WBSCL_TAP_CONTROL >+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 >+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 >+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 >+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc >+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL >+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L >+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L >+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L >+//WBSCL_DEST_SIZE >+#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0 >+#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10 >+#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL >+#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L >+//WBSCL_HORZ_FILTER_SCALE_RATIO >+#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0 >+#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL >+//WBSCL_HORZ_FILTER_INIT_Y_RGB >+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 >+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18 >+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL >+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L >+//WBSCL_HORZ_FILTER_INIT_CBCR >+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0 >+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18 >+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL >+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L >+//WBSCL_VERT_FILTER_SCALE_RATIO >+#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0 >+#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL >+//WBSCL_VERT_FILTER_INIT_Y_RGB >+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 >+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18 >+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL >+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L >+//WBSCL_VERT_FILTER_INIT_CBCR >+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0 >+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18 >+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL >+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L >+//WBSCL_ROUND_OFFSET >+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 >+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10 >+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x000003FFL >+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0x03FF0000L >+//WBSCL_OVERFLOW_STATUS >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8 >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L >+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L >+//WBSCL_COEF_RAM_CONFLICT_STATUS >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0 >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8 >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L >+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L >+//WBSCL_TEST_CNTL >+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4 >+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8 >+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L >+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L >+//WBSCL_TEST_CRC_RED >+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x0 >+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10 >+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x000003FFL >+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L >+//WBSCL_TEST_CRC_GREEN >+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 >+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 >+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL >+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L >+//WBSCL_TEST_CRC_BLUE >+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x0 >+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 >+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x000003FFL >+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L >+//WBSCL_BACKPRESSURE_CNT_EN >+#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 >+#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L >+//WB_MCIF_BACKPRESSURE_CNT >+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 >+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 >+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL >+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L >+//WBSCL_CLAMP_Y_RGB >+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 >+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x10 >+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000003FFL >+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x03FF0000L >+//WBSCL_CLAMP_CBCR >+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x0 >+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x10 >+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR_MASK 0x000003FFL >+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR_MASK 0x03FF0000L >+//WBSCL_OUTSIDE_PIX_STRATEGY >+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 >+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10 >+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L >+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x03FF0000L >+//WBSCL_OUTSIDE_PIX_STRATEGY_CBCR >+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x0 >+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x10 >+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB_MASK 0x000003FFL >+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR_MASK 0x03FF0000L >+//WBSCL_DEBUG >+#define WBSCL_DEBUG__WBSCL_DEBUG__SHIFT 0x0 >+#define WBSCL_DEBUG__WBSCL_DEBUG_MASK 0xFFFFFFFFL >+//WBSCL_TEST_DEBUG_INDEX >+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//WBSCL_TEST_DEBUG_DATA >+#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA__SHIFT 0x0 >+#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON3_PERFCOUNTER_CNTL >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON3_PERFCOUNTER_CNTL2 >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON3_PERFCOUNTER_STATE >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON3_PERFMON_CNTL >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON3_PERFMON_CNTL2 >+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON3_PERFMON_CVALUE_LOW >+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON3_PERFMON_HI >+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON3_PERFMON_LOW >+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec >+//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L >+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L >+//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R >+#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL >+//MCIF_WB0_MCIF_WB_BUFMGR_STATUS >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L >+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L >+//MCIF_WB0_MCIF_WB_BUF_PITCH >+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 >+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L >+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L >+//MCIF_WB0_MCIF_WB_BUF_1_STATUS >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB0_MCIF_WB_BUF_1_STATUS2 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB0_MCIF_WB_BUF_2_STATUS >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB0_MCIF_WB_BUF_2_STATUS2 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB0_MCIF_WB_BUF_3_STATUS >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB0_MCIF_WB_BUF_3_STATUS2 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB0_MCIF_WB_BUF_4_STATUS >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB0_MCIF_WB_BUF_4_STATUS2 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL >+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 >+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L >+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L >+//MCIF_WB0_MCIF_WB_SCLK_CHANGE >+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL >+//MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX >+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA >+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L >+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L >+//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL >+//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L >+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L >+//MCIF_WB0_MCIF_WB_WATERMARK >+#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL >+//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL >+#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L >+//MCIF_WB0_MCIF_WB_WARM_UP_CNTL >+#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 >+#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L >+//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL >+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 >+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L >+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L >+//MCIF_WB0_MULTI_LEVEL_QOS_CTRL >+#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 >+#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL >+//MCIF_WB0_MCIF_WB_SECURITY_LEVEL >+#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L >+//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE >+#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL >+//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE >+#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL >+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION >+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION >+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION >+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION >+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+ >+ >+// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec >+//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L >+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L >+//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R >+#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL >+//MCIF_WB1_MCIF_WB_BUFMGR_STATUS >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L >+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L >+//MCIF_WB1_MCIF_WB_BUF_PITCH >+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 >+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L >+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L >+//MCIF_WB1_MCIF_WB_BUF_1_STATUS >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB1_MCIF_WB_BUF_1_STATUS2 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB1_MCIF_WB_BUF_2_STATUS >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB1_MCIF_WB_BUF_2_STATUS2 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB1_MCIF_WB_BUF_3_STATUS >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB1_MCIF_WB_BUF_3_STATUS2 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB1_MCIF_WB_BUF_4_STATUS >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB1_MCIF_WB_BUF_4_STATUS2 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL >+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 >+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L >+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L >+//MCIF_WB1_MCIF_WB_SCLK_CHANGE >+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL >+//MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX >+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA >+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L >+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L >+//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL >+//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L >+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L >+//MCIF_WB1_MCIF_WB_WATERMARK >+#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL >+//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL >+#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L >+//MCIF_WB1_MCIF_WB_WARM_UP_CNTL >+#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 >+#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L >+//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL >+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 >+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L >+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L >+//MCIF_WB1_MULTI_LEVEL_QOS_CTRL >+#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 >+#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL >+//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE >+#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL >+//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE >+#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL >+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION >+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION >+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION >+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION >+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+ >+ >+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec >+//WBIF0_MISC_CTRL >+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 >+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 >+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL >+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L >+//WBIF0_SMU_WM_CONTROL >+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL__SHIFT 0x14 >+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ__SHIFT 0x16 >+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 >+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 >+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL_MASK 0x00300000L >+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ_MASK 0x00400000L >+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L >+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L >+//WBIF0_PHASE0_OUTSTANDING_COUNTER >+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 >+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL >+//WBIF0_PHASE1_OUTSTANDING_COUNTER >+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 >+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL >+//VGA_SRC_SPLIT_CNTL >+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0 >+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L >+//MMHUBBUB_MEM_PWR_STATUS >+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 >+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 >+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 >+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 >+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f >+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L >+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL >+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L >+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L >+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L >+//MMHUBBUB_MEM_PWR_CNTL >+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0 >+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1 >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 >+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L >+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L >+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L >+//MMHUBBUB_CLOCK_CNTL >+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 >+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 >+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6 >+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7 >+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8 >+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 >+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa >+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL >+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L >+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L >+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L >+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L >+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L >+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L >+//MMHUBBUB_SOFT_RESET >+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 >+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1 >+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 >+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8 >+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L >+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L >+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L >+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L >+//DMU_IF_ERR_STATUS >+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0 >+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4 >+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L >+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L >+//MMHUBBUB_CLIENT_UNIT_ID >+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT 0x0 >+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8 >+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK 0x0000003FL >+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L >+ >+ >+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec >+//MCIF_CONTROL >+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e >+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f >+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L >+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L >+//MCIF_WRITE_COMBINE_CONTROL >+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 >+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL >+//MCIF_PHASE0_OUTSTANDING_COUNTER >+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 >+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL >+//MCIF_PHASE1_OUTSTANDING_COUNTER >+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 >+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL >+//MCIF_PHASE2_OUTSTANDING_COUNTER >+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0 >+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL >+ >+ >+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON4_PERFCOUNTER_CNTL >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON4_PERFCOUNTER_CNTL2 >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON4_PERFCOUNTER_STATE >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON4_PERFMON_CNTL >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON4_PERFMON_CNTL2 >+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON4_PERFMON_CVALUE_LOW >+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON4_PERFMON_HI >+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON4_PERFMON_LOW >+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream0_dispdec >+//AZF0STREAM0_AZALIA_STREAM_INDEX >+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM0_AZALIA_STREAM_DATA >+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream1_dispdec >+//AZF0STREAM1_AZALIA_STREAM_INDEX >+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM1_AZALIA_STREAM_DATA >+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream2_dispdec >+//AZF0STREAM2_AZALIA_STREAM_INDEX >+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM2_AZALIA_STREAM_DATA >+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream3_dispdec >+//AZF0STREAM3_AZALIA_STREAM_INDEX >+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM3_AZALIA_STREAM_DATA >+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream4_dispdec >+//AZF0STREAM4_AZALIA_STREAM_INDEX >+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM4_AZALIA_STREAM_DATA >+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream5_dispdec >+//AZF0STREAM5_AZALIA_STREAM_INDEX >+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM5_AZALIA_STREAM_DATA >+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream6_dispdec >+//AZF0STREAM6_AZALIA_STREAM_INDEX >+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM6_AZALIA_STREAM_DATA >+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream7_dispdec >+//AZF0STREAM7_AZALIA_STREAM_INDEX >+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM7_AZALIA_STREAM_DATA >+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_az_misc_dispdec >+//AZ_CLOCK_CNTL >+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 >+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 >+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x10 >+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0x18 >+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L >+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L >+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00010000L >+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x1F000000L >+ >+ >+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON5_PERFCOUNTER_CNTL >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON5_PERFCOUNTER_CNTL2 >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON5_PERFCOUNTER_STATE >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON5_PERFMON_CNTL >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON5_PERFMON_CNTL2 >+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON5_PERFMON_CVALUE_LOW >+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON5_PERFMON_HI >+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON5_PERFMON_LOW >+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0controller_dispdec >+//AZALIA_CONTROLLER_CLOCK_GATING >+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 >+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L >+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L >+//AZALIA_AUDIO_DTO >+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 >+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 >+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL >+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L >+//AZALIA_AUDIO_DTO_CONTROL >+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 >+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L >+//AZALIA_SOCCLK_CONTROL >+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 >+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L >+//AZALIA_UNDERFLOW_FILLER_SAMPLE >+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 >+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL >+//AZALIA_DATA_DMA_CONTROL >+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 >+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 >+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 >+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 >+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 >+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 >+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L >+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL >+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L >+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L >+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L >+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L >+//AZALIA_BDL_DMA_CONTROL >+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 >+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 >+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 >+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 >+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L >+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL >+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L >+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L >+//AZALIA_RIRB_AND_DP_CONTROL >+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 >+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 >+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 >+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L >+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L >+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L >+//AZALIA_CORB_DMA_CONTROL >+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 >+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 >+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L >+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L >+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER >+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 >+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL >+//AZALIA_CYCLIC_BUFFER_SYNC >+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 >+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L >+//AZALIA_GLOBAL_CAPABILITIES >+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 >+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L >+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY >+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 >+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 >+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL >+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L >+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL >+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 >+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 >+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 >+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL >+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L >+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L >+//AZALIA_INPUT_PAYLOAD_CAPABILITY >+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 >+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 >+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL >+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L >+//AZALIA_INPUT_CRC0_CONTROL0 >+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 >+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 >+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L >+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L >+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L >+//AZALIA_INPUT_CRC0_CONTROL1 >+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC0_CONTROL2 >+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL >+//AZALIA_INPUT_CRC0_CONTROL3 >+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 >+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 >+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L >+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L >+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L >+//AZALIA_INPUT_CRC0_RESULT >+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CONTROL0 >+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 >+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 >+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L >+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L >+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L >+//AZALIA_INPUT_CRC1_CONTROL1 >+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CONTROL2 >+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL >+//AZALIA_INPUT_CRC1_CONTROL3 >+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 >+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 >+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L >+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L >+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L >+//AZALIA_INPUT_CRC1_RESULT >+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CONTROL0 >+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 >+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 >+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 >+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc >+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L >+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L >+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L >+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L >+//AZALIA_CRC0_CONTROL1 >+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 >+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CONTROL2 >+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 >+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL >+//AZALIA_CRC0_CONTROL3 >+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 >+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 >+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 >+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L >+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L >+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L >+//AZALIA_CRC0_RESULT >+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 >+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CONTROL0 >+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 >+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 >+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 >+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc >+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L >+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L >+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L >+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L >+//AZALIA_CRC1_CONTROL1 >+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 >+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CONTROL2 >+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 >+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL >+//AZALIA_CRC1_CONTROL3 >+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 >+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 >+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 >+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L >+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L >+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L >+//AZALIA_CRC1_RESULT >+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 >+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL >+//AZALIA_MEM_PWR_CTRL >+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 >+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 >+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c >+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L >+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L >+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L >+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L >+//AZALIA_MEM_PWR_STATUS >+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc >+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L >+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L >+ >+ >+// addressBlock: dce_dc_hda_azf0root_dispdec >+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID >+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 >+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL >+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID >+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 >+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL >+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL >+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 >+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 >+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L >+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L >+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL >+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 >+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL >+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL >+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L >+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L >+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L >+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L >+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L >+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 >+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL >+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY >+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 >+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 >+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L >+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L >+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY >+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 >+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 >+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L >+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L >+//AZALIA_F0_GTC_GROUP_OFFSET0 >+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 >+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL >+//AZALIA_F0_GTC_GROUP_OFFSET1 >+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 >+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL >+//AZALIA_F0_GTC_GROUP_OFFSET2 >+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 >+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL >+//AZALIA_F0_GTC_GROUP_OFFSET3 >+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 >+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL >+//AZALIA_F0_GTC_GROUP_OFFSET4 >+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 >+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL >+//AZALIA_F0_GTC_GROUP_OFFSET5 >+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 >+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL >+//AZALIA_F0_GTC_GROUP_OFFSET6 >+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 >+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL >+//REG_DC_AUDIO_PORT_CONNECTIVITY >+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 >+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 >+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L >+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L >+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY >+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 >+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 >+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L >+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L >+ >+ >+// addressBlock: dce_dc_hda_azf0stream8_dispdec >+//AZF0STREAM8_AZALIA_STREAM_INDEX >+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM8_AZALIA_STREAM_DATA >+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream9_dispdec >+//AZF0STREAM9_AZALIA_STREAM_INDEX >+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM9_AZALIA_STREAM_DATA >+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream10_dispdec >+//AZF0STREAM10_AZALIA_STREAM_INDEX >+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM10_AZALIA_STREAM_DATA >+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream11_dispdec >+//AZF0STREAM11_AZALIA_STREAM_INDEX >+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM11_AZALIA_STREAM_DATA >+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream12_dispdec >+//AZF0STREAM12_AZALIA_STREAM_INDEX >+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM12_AZALIA_STREAM_DATA >+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream13_dispdec >+//AZF0STREAM13_AZALIA_STREAM_INDEX >+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM13_AZALIA_STREAM_DATA >+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream14_dispdec >+//AZF0STREAM14_AZALIA_STREAM_INDEX >+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM14_AZALIA_STREAM_DATA >+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0stream15_dispdec >+//AZF0STREAM15_AZALIA_STREAM_INDEX >+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 >+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 >+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL >+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L >+//AZF0STREAM15_AZALIA_STREAM_DATA >+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 >+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec >+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX >+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA >+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec >+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX >+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 >+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL >+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA >+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 >+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec >+//DCHUBBUB_SDPIF_CFG0 >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6 >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19 >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L >+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L >+//VM_REQUEST_PHYSICAL >+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0 >+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3 >+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L >+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L >+//DCHUBBUB_FORCE_IO_STATUS_0 >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L >+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L >+//DCHUBBUB_FORCE_IO_STATUS_1 >+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 >+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL >+//DCN_VM_FB_LOCATION_BASE >+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 >+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL >+//DCN_VM_FB_LOCATION_TOP >+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 >+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL >+//DCN_VM_FB_OFFSET >+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 >+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL >+//DCN_VM_AGP_BOT >+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 >+#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL >+//DCN_VM_AGP_TOP >+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 >+#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL >+//DCN_VM_AGP_BASE >+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 >+#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL >+//DCN_VM_LOCAL_HBM_ADDRESS_START >+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0 >+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL >+//DCN_VM_LOCAL_HBM_ADDRESS_END >+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0 >+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL >+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL >+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 >+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L >+//DCHUBBUB_SDPIF_PIPE_SEC_LVL >+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 >+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x3 >+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x6 >+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0x9 >+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x00000007L >+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x00000038L >+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x000001C0L >+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x00000E00L >+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL >+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT 0x0 >+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT 0x3 >+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT 0x6 >+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT 0x9 >+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK 0x00000007L >+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK 0x00000038L >+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK 0x000001C0L >+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK 0x00000E00L >+//DCHUBBUB_SDPIF_MEM_PWR_CTRL >+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 >+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 >+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L >+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L >+//DCHUBBUB_SDPIF_MEM_PWR_STATUS >+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 >+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L >+//DCHUBBUB_SDPIF_CFG1 >+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0 >+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1 >+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2 >+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8 >+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L >+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L >+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L >+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L >+//DCHUBBUB_SDPIF_CFG2 >+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT 0x0 >+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT 0x8 >+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10 >+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK 0x00000001L >+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK 0x00000700L >+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L >+ >+ >+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec >+//DCHUBBUB_RET_PATH_DCC_CFG >+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK 0x00000001L >+//DCHUBBUB_RET_PATH_DCC_CFG0_0 >+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG0_1 >+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG1_0 >+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG1_1 >+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG2_0 >+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG2_1 >+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG3_0 >+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG3_1 >+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG4_0 >+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG4_1 >+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG5_0 >+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG5_1 >+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG6_0 >+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG6_1 >+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG7_0 >+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_DCC_CFG7_1 >+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK 0xFFFFFFFFL >+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL >+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 >+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L >+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L >+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS >+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 >+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L >+//DCHUBBUB_CRC_CTRL >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB__SHIFT 0xf >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14 >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00007000L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB_MASK 0x00008000L >+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L >+//DCHUBBUB_CRC0_VAL_R_G >+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 >+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10 >+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL >+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L >+//DCHUBBUB_CRC0_VAL_B_A >+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 >+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10 >+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL >+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L >+//DCHUBBUB_CRC1_VAL_R_G >+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 >+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10 >+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL >+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L >+//DCHUBBUB_CRC1_VAL_B_A >+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 >+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10 >+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL >+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dchubbub_hubbub_dispdec >+//DCHUBBUB_ARB_DF_REQ_OUTSTAND >+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 >+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0xc >+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT 0x17 >+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL >+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x001FF000L >+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK 0xFF800000L >+//DCHUBBUB_ARB_SAT_LEVEL >+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 >+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL >+//DCHUBBUB_ARB_QOS_FORCE >+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 >+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 >+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL >+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L >+//DCHUBBUB_ARB_DRAM_STATE_CNTL >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT 0x8 >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT 0x9 >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK 0x00000100L >+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK 0x00000200L >+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A__SHIFT 0x10 >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x00003FFFL >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A_MASK 0x3FFF0000L >+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A >+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT 0x0 >+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK 0x00003FFFL >+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B__SHIFT 0x10 >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x00003FFFL >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B_MASK 0x3FFF0000L >+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B >+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT 0x0 >+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK 0x00003FFFL >+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C__SHIFT 0x10 >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x00003FFFL >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C_MASK 0x3FFF0000L >+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C >+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT 0x0 >+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK 0x00003FFFL >+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D__SHIFT 0x10 >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x00003FFFL >+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D_MASK 0x3FFF0000L >+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D >+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT 0x0 >+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK 0x00003FFFL >+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x0 >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x10 >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0x0000FFFFL >+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0xFFFF0000L >+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL >+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 >+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 >+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 >+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 >+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L >+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L >+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L >+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L >+//DCHUBBUB_ARB_TIMEOUT_ENABLE >+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 >+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L >+//DCHUBBUB_GLOBAL_TIMER_CNTL >+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 >+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc >+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 >+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL >+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L >+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L >+//SURFACE_CHECK0_ADDRESS_LSB >+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 >+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL >+//SURFACE_CHECK0_ADDRESS_MSB >+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 >+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f >+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL >+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L >+//SURFACE_CHECK1_ADDRESS_LSB >+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 >+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL >+//SURFACE_CHECK1_ADDRESS_MSB >+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 >+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f >+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL >+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L >+//SURFACE_CHECK2_ADDRESS_LSB >+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 >+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL >+//SURFACE_CHECK2_ADDRESS_MSB >+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 >+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f >+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL >+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L >+//SURFACE_CHECK3_ADDRESS_LSB >+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 >+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL >+//SURFACE_CHECK3_ADDRESS_MSB >+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 >+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f >+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL >+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L >+//VTG0_CONTROL >+#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 >+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10 >+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f >+#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL >+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L >+#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L >+//VTG1_CONTROL >+#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 >+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10 >+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f >+#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL >+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L >+#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L >+//VTG2_CONTROL >+#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 >+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0x10 >+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f >+#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL >+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x7FFF0000L >+#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L >+//VTG3_CONTROL >+#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 >+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10 >+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f >+#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL >+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x7FFF0000L >+#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L >+//DCHUBBUB_SOFT_RESET >+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 >+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 >+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 >+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L >+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L >+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L >+//DCHUBBUB_CLOCK_CNTL >+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 >+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 >+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 >+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL >+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L >+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L >+//DCFCLK_CNTL >+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 >+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 >+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f >+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL >+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L >+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L >+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x007FF800L >+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x13 >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x7FF80000L >+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L >+//DCHUBBUB_VLINE_SNAPSHOT >+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 >+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L >+//DCHUBBUB_CTRL_STATUS >+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0 >+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L >+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1 >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6 >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L >+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2 >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0 >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L >+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L >+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS >+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0 >+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1 >+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2 >+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3 >+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L >+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L >+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L >+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L >+//DCHUBBUB_TEST_DEBUG_INDEX >+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK 0x000000FFL >+//DCHUBBUB_TEST_DEBUG_DATA >+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT 0x0 >+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A >+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT 0x0 >+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK 0x000003FFL >+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A >+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT 0x0 >+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK 0x000003FFL >+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B >+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT 0x0 >+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK 0x000003FFL >+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B >+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT 0x0 >+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK 0x000003FFL >+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C >+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT 0x0 >+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK 0x000003FFL >+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C >+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT 0x0 >+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK 0x000003FFL >+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D >+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT 0x0 >+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK 0x000003FFL >+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D >+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT 0x0 >+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK 0x000003FFL >+//DCHUBBUB_ARB_HOSTVM_CNTL >+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT 0x0 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT 0x1 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT 0x2 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT 0x3 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT 0x4 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT 0x5 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT 0x6 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT 0x8 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT 0x10 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT 0x18 >+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT 0x1c >+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK 0x00000001L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK 0x00000002L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK 0x00000004L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK 0x00000008L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK 0x00000010L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK 0x00000020L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK 0x00000040L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK 0x00003F00L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK 0x00FF0000L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK 0x0F000000L >+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK 0xF0000000L >+//FMON_CTRL >+#define FMON_CTRL__FMON_START__SHIFT 0x0 >+#define FMON_CTRL__FMON_MODE__SHIFT 0x1 >+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4 >+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5 >+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6 >+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7 >+#define FMON_CTRL__FMON_STATE__SHIFT 0x9 >+#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc >+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd >+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11 >+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16 >+#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b >+#define FMON_CTRL__FMON_START_MASK 0x00000001L >+#define FMON_CTRL__FMON_MODE_MASK 0x00000006L >+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L >+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L >+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L >+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L >+#define FMON_CTRL__FMON_STATE_MASK 0x00000600L >+#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L >+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L >+#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L >+#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L >+#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L >+ >+ >+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON6_PERFCOUNTER_CNTL >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON6_PERFCOUNTER_CNTL2 >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON6_PERFCOUNTER_STATE >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON6_PERFMON_CNTL >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON6_PERFMON_CNTL2 >+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON6_PERFMON_CVALUE_LOW >+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON6_PERFMON_HI >+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON6_PERFMON_LOW >+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec >+//DCN_VM_CONTEXT0_CNTL >+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT1_CNTL >+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT2_CNTL >+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT3_CNTL >+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT4_CNTL >+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT5_CNTL >+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT6_CNTL >+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT7_CNTL >+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT8_CNTL >+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT9_CNTL >+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT10_CNTL >+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT11_CNTL >+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT12_CNTL >+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT13_CNTL >+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT14_CNTL >+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT15_CNTL >+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1 >+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 >+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L >+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L >+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL >+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 >+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL >+//DCN_VM_DEFAULT_ADDR_MSB >+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT 0x0 >+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT 0x1c >+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT 0x1d >+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK 0x0000000FL >+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK 0x10000000L >+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK 0x20000000L >+//DCN_VM_DEFAULT_ADDR_LSB >+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT 0x0 >+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL >+//DCN_VM_FAULT_CNTL >+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0 >+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1 >+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2 >+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8 >+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9 >+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L >+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L >+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L >+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L >+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L >+//DCN_VM_FAULT_STATUS >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0 >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10 >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x14 >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x18 >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x00300000L >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x0F000000L >+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L >+//DCN_VM_FAULT_ADDR_MSB >+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0 >+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL >+//DCN_VM_FAULT_ADDR_LSB >+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0 >+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec >+//HUBP0_DCSURF_SURFACE_CONFIG >+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 >+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 >+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa >+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL >+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L >+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L >+//HUBP0_DCSURF_ADDR_CONFIG >+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 >+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 >+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 >+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 >+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa >+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc >+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L >+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L >+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L >+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L >+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L >+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L >+//HUBP0_DCSURF_TILING_CONFIG >+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 >+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 >+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 >+#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa >+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb >+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL >+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L >+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L >+#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L >+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L >+//HUBP0_DCSURF_PRI_VIEWPORT_START >+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 >+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 >+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL >+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L >+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION >+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 >+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 >+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL >+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L >+//HUBP0_DCSURF_PRI_VIEWPORT_START_C >+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 >+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 >+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL >+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L >+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C >+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 >+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 >+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL >+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L >+//HUBP0_DCSURF_SEC_VIEWPORT_START >+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 >+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 >+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL >+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L >+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION >+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 >+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 >+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL >+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L >+//HUBP0_DCSURF_SEC_VIEWPORT_START_C >+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 >+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 >+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL >+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L >+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C >+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 >+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 >+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL >+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L >+//HUBP0_DCHUBP_REQ_SIZE_CONFIG >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L >+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L >+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L >+//HUBP0_DCHUBP_CNTL >+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 >+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 >+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 >+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 >+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 >+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 >+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 >+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc >+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd >+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 >+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 >+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 >+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a >+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b >+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c >+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f >+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L >+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L >+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L >+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L >+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L >+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L >+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L >+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L >+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L >+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L >+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L >+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L >+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L >+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L >+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L >+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L >+//HUBP0_HUBP_CLK_CNTL >+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 >+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c >+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L >+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L >+//HUBP0_DCHUBP_VMPG_CONFIG >+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 >+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L >+//HUBP0_HUBPREQ_DEBUG_DB >+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 >+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL >+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L >+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L >+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec >+//HUBPREQ0_DCSURF_SURFACE_PITCH >+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 >+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL >+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L >+//HUBPREQ0_DCSURF_SURFACE_PITCH_C >+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 >+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL >+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L >+//HUBPREQ0_VMID_SETTINGS_0 >+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 >+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL >+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS >+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH >+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C >+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS >+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH >+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C >+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS >+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH >+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C >+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS >+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH >+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C >+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_SURFACE_CONTROL >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L >+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L >+//HUBPREQ0_DCSURF_FLIP_CONTROL >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L >+//HUBPREQ0_DCSURF_FLIP_CONTROL2 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L >+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L >+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L >+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L >+//HUBPREQ0_DCSURF_SURFACE_INUSE >+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH >+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_SURFACE_INUSE_C >+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C >+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE >+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH >+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C >+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C >+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ0_DCN_EXPANSION_MODE >+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 >+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 >+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 >+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 >+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L >+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL >+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L >+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L >+//HUBPREQ0_DCN_TTU_QOS_WM >+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 >+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 >+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL >+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L >+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL >+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 >+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c >+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL >+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L >+//HUBPREQ0_DCN_SURF0_TTU_CNTL0 >+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ0_DCN_SURF0_TTU_CNTL1 >+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ0_DCN_SURF1_TTU_CNTL0 >+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ0_DCN_SURF1_TTU_CNTL1 >+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ0_DCN_CUR0_TTU_CNTL0 >+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ0_DCN_CUR0_TTU_CNTL1 >+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ0_DCN_CUR1_TTU_CNTL0 >+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ0_DCN_CUR1_TTU_CNTL1 >+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR >+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 >+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL >+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR >+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 >+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL >+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL >+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 >+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 >+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 >+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 >+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L >+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L >+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L >+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L >+//HUBPREQ0_BLANK_OFFSET_0 >+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 >+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 >+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL >+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L >+//HUBPREQ0_BLANK_OFFSET_1 >+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 >+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL >+//HUBPREQ0_DST_DIMENSIONS >+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 >+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL >+//HUBPREQ0_DST_AFTER_SCALER >+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 >+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 >+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL >+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L >+//HUBPREQ0_PREFETCH_SETTINGS >+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 >+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 >+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL >+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L >+//HUBPREQ0_PREFETCH_SETTINGS_C >+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 >+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL >+//HUBPREQ0_VBLANK_PARAMETERS_0 >+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 >+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 >+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL >+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L >+//HUBPREQ0_VBLANK_PARAMETERS_1 >+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 >+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL >+//HUBPREQ0_VBLANK_PARAMETERS_2 >+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 >+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL >+//HUBPREQ0_VBLANK_PARAMETERS_3 >+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 >+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL >+//HUBPREQ0_VBLANK_PARAMETERS_4 >+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 >+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL >+//HUBPREQ0_FLIP_PARAMETERS_0 >+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 >+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 >+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL >+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L >+//HUBPREQ0_FLIP_PARAMETERS_1 >+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 >+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL >+//HUBPREQ0_FLIP_PARAMETERS_2 >+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 >+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL >+//HUBPREQ0_NOM_PARAMETERS_0 >+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 >+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL >+//HUBPREQ0_NOM_PARAMETERS_1 >+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 >+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL >+//HUBPREQ0_NOM_PARAMETERS_2 >+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 >+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL >+//HUBPREQ0_NOM_PARAMETERS_3 >+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 >+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL >+//HUBPREQ0_NOM_PARAMETERS_4 >+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 >+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL >+//HUBPREQ0_NOM_PARAMETERS_5 >+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 >+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL >+//HUBPREQ0_NOM_PARAMETERS_6 >+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 >+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL >+//HUBPREQ0_NOM_PARAMETERS_7 >+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 >+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL >+//HUBPREQ0_PER_LINE_DELIVERY_PRE >+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 >+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 >+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL >+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L >+//HUBPREQ0_PER_LINE_DELIVERY >+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 >+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 >+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL >+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L >+//HUBPREQ0_CURSOR_SETTINGS >+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 >+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 >+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 >+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 >+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL >+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L >+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L >+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L >+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ >+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 >+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL >+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT >+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 >+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL >+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L >+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS >+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 >+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL >+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L >+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L >+//HUBPREQ0_VBLANK_PARAMETERS_5 >+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 >+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL >+//HUBPREQ0_VBLANK_PARAMETERS_6 >+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 >+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL >+//HUBPREQ0_FLIP_PARAMETERS_3 >+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 >+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL >+//HUBPREQ0_FLIP_PARAMETERS_4 >+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 >+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL >+//HUBPREQ0_FLIP_PARAMETERS_5 >+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 >+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL >+//HUBPREQ0_FLIP_PARAMETERS_6 >+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 >+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec >+//HUBPRET0_HUBPRET_CONTROL >+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc >+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 >+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 >+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 >+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 >+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 >+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL >+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L >+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L >+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L >+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L >+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L >+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L >+//HUBPRET0_HUBPRET_MEM_PWR_CTRL >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L >+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L >+//HUBPRET0_HUBPRET_MEM_PWR_STATUS >+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 >+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 >+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L >+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL >+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L >+//HUBPRET0_HUBPRET_READ_LINE_CTRL0 >+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 >+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL >+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L >+//HUBPRET0_HUBPRET_READ_LINE_CTRL1 >+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 >+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL >+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L >+//HUBPRET0_HUBPRET_READ_LINE0 >+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 >+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL >+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L >+//HUBPRET0_HUBPRET_READ_LINE1 >+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 >+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL >+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L >+//HUBPRET0_HUBPRET_INTERRUPT >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L >+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L >+//HUBPRET0_HUBPRET_READ_LINE_VALUE >+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 >+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL >+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L >+//HUBPRET0_HUBPRET_READ_LINE_STATUS >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L >+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec >+//CURSOR0_0_CURSOR_CONTROL >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L >+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L >+//CURSOR0_0_CURSOR_SURFACE_ADDRESS >+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH >+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//CURSOR0_0_CURSOR_SIZE >+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 >+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL >+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L >+//CURSOR0_0_CURSOR_POSITION >+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 >+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL >+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L >+//CURSOR0_0_CURSOR_HOT_SPOT >+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 >+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL >+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L >+//CURSOR0_0_CURSOR_STEREO_CONTROL >+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 >+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 >+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L >+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L >+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L >+//CURSOR0_0_CURSOR_DST_OFFSET >+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL >+//CURSOR0_0_CURSOR_MEM_PWR_CTRL >+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 >+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 >+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L >+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L >+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L >+//CURSOR0_0_CURSOR_MEM_PWR_STATUS >+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 >+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L >+//CURSOR0_0_DMDATA_ADDRESS_HIGH >+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 >+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c >+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d >+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e >+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL >+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L >+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L >+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L >+//CURSOR0_0_DMDATA_ADDRESS_LOW >+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 >+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL >+//CURSOR0_0_DMDATA_CNTL >+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 >+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 >+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 >+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 >+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L >+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L >+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L >+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L >+//CURSOR0_0_DMDATA_QOS_CNTL >+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 >+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 >+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 >+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L >+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L >+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L >+//CURSOR0_0_DMDATA_STATUS >+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 >+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 >+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 >+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L >+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L >+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L >+//CURSOR0_0_DMDATA_SW_CNTL >+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 >+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 >+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 >+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L >+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L >+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L >+//CURSOR0_0_DMDATA_SW_DATA >+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 >+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON7_PERFCOUNTER_CNTL >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON7_PERFCOUNTER_CNTL2 >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON7_PERFCOUNTER_STATE >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON7_PERFMON_CNTL >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON7_PERFMON_CNTL2 >+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON7_PERFMON_CVALUE_LOW >+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON7_PERFMON_HI >+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON7_PERFMON_LOW >+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec >+//HUBP1_DCSURF_SURFACE_CONFIG >+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 >+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 >+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa >+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL >+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L >+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L >+//HUBP1_DCSURF_ADDR_CONFIG >+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 >+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 >+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 >+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 >+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa >+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc >+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L >+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L >+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L >+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L >+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L >+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L >+//HUBP1_DCSURF_TILING_CONFIG >+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 >+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 >+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 >+#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa >+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb >+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL >+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L >+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L >+#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L >+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L >+//HUBP1_DCSURF_PRI_VIEWPORT_START >+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 >+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 >+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL >+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L >+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION >+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 >+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 >+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL >+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L >+//HUBP1_DCSURF_PRI_VIEWPORT_START_C >+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 >+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 >+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL >+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L >+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C >+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 >+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 >+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL >+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L >+//HUBP1_DCSURF_SEC_VIEWPORT_START >+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 >+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 >+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL >+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L >+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION >+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 >+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 >+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL >+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L >+//HUBP1_DCSURF_SEC_VIEWPORT_START_C >+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 >+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 >+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL >+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L >+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C >+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 >+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 >+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL >+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L >+//HUBP1_DCHUBP_REQ_SIZE_CONFIG >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L >+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L >+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L >+//HUBP1_DCHUBP_CNTL >+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 >+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 >+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 >+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 >+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 >+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 >+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 >+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc >+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd >+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 >+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 >+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 >+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a >+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b >+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c >+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f >+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L >+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L >+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L >+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L >+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L >+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L >+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L >+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L >+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L >+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L >+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L >+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L >+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L >+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L >+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L >+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L >+//HUBP1_HUBP_CLK_CNTL >+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 >+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c >+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L >+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L >+//HUBP1_DCHUBP_VMPG_CONFIG >+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 >+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L >+//HUBP1_HUBPREQ_DEBUG_DB >+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 >+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL >+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L >+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L >+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec >+//HUBPREQ1_DCSURF_SURFACE_PITCH >+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 >+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL >+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L >+//HUBPREQ1_DCSURF_SURFACE_PITCH_C >+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 >+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL >+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L >+//HUBPREQ1_VMID_SETTINGS_0 >+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0 >+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL >+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS >+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH >+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C >+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS >+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH >+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C >+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS >+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH >+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C >+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS >+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH >+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C >+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_SURFACE_CONTROL >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L >+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L >+//HUBPREQ1_DCSURF_FLIP_CONTROL >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L >+//HUBPREQ1_DCSURF_FLIP_CONTROL2 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L >+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L >+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L >+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L >+//HUBPREQ1_DCSURF_SURFACE_INUSE >+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH >+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_SURFACE_INUSE_C >+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C >+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE >+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH >+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C >+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C >+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ1_DCN_EXPANSION_MODE >+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 >+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 >+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 >+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 >+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L >+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL >+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L >+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L >+//HUBPREQ1_DCN_TTU_QOS_WM >+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 >+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 >+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL >+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L >+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL >+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 >+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c >+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL >+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L >+//HUBPREQ1_DCN_SURF0_TTU_CNTL0 >+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ1_DCN_SURF0_TTU_CNTL1 >+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ1_DCN_SURF1_TTU_CNTL0 >+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ1_DCN_SURF1_TTU_CNTL1 >+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ1_DCN_CUR0_TTU_CNTL0 >+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ1_DCN_CUR0_TTU_CNTL1 >+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ1_DCN_CUR1_TTU_CNTL0 >+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ1_DCN_CUR1_TTU_CNTL1 >+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR >+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 >+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL >+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR >+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 >+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL >+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL >+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 >+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 >+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 >+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 >+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L >+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L >+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L >+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L >+//HUBPREQ1_BLANK_OFFSET_0 >+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 >+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 >+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL >+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L >+//HUBPREQ1_BLANK_OFFSET_1 >+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 >+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL >+//HUBPREQ1_DST_DIMENSIONS >+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 >+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL >+//HUBPREQ1_DST_AFTER_SCALER >+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 >+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 >+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL >+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L >+//HUBPREQ1_PREFETCH_SETTINGS >+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 >+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 >+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL >+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L >+//HUBPREQ1_PREFETCH_SETTINGS_C >+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 >+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL >+//HUBPREQ1_VBLANK_PARAMETERS_0 >+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 >+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 >+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL >+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L >+//HUBPREQ1_VBLANK_PARAMETERS_1 >+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 >+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL >+//HUBPREQ1_VBLANK_PARAMETERS_2 >+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 >+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL >+//HUBPREQ1_VBLANK_PARAMETERS_3 >+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 >+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL >+//HUBPREQ1_VBLANK_PARAMETERS_4 >+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 >+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL >+//HUBPREQ1_FLIP_PARAMETERS_0 >+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 >+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 >+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL >+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L >+//HUBPREQ1_FLIP_PARAMETERS_1 >+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 >+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL >+//HUBPREQ1_FLIP_PARAMETERS_2 >+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 >+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL >+//HUBPREQ1_NOM_PARAMETERS_0 >+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 >+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL >+//HUBPREQ1_NOM_PARAMETERS_1 >+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 >+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL >+//HUBPREQ1_NOM_PARAMETERS_2 >+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 >+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL >+//HUBPREQ1_NOM_PARAMETERS_3 >+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 >+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL >+//HUBPREQ1_NOM_PARAMETERS_4 >+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 >+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL >+//HUBPREQ1_NOM_PARAMETERS_5 >+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 >+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL >+//HUBPREQ1_NOM_PARAMETERS_6 >+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 >+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL >+//HUBPREQ1_NOM_PARAMETERS_7 >+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 >+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL >+//HUBPREQ1_PER_LINE_DELIVERY_PRE >+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 >+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 >+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL >+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L >+//HUBPREQ1_PER_LINE_DELIVERY >+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 >+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 >+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL >+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L >+//HUBPREQ1_CURSOR_SETTINGS >+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 >+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 >+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 >+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 >+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL >+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L >+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L >+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L >+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ >+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 >+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL >+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT >+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 >+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL >+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L >+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS >+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 >+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL >+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L >+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L >+//HUBPREQ1_VBLANK_PARAMETERS_5 >+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 >+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL >+//HUBPREQ1_VBLANK_PARAMETERS_6 >+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 >+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL >+//HUBPREQ1_FLIP_PARAMETERS_3 >+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 >+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL >+//HUBPREQ1_FLIP_PARAMETERS_4 >+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 >+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL >+//HUBPREQ1_FLIP_PARAMETERS_5 >+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 >+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL >+//HUBPREQ1_FLIP_PARAMETERS_6 >+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 >+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec >+//HUBPRET1_HUBPRET_CONTROL >+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc >+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 >+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 >+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 >+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 >+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 >+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL >+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L >+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L >+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L >+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L >+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L >+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L >+//HUBPRET1_HUBPRET_MEM_PWR_CTRL >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L >+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L >+//HUBPRET1_HUBPRET_MEM_PWR_STATUS >+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 >+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 >+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L >+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL >+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L >+//HUBPRET1_HUBPRET_READ_LINE_CTRL0 >+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 >+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL >+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L >+//HUBPRET1_HUBPRET_READ_LINE_CTRL1 >+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 >+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL >+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L >+//HUBPRET1_HUBPRET_READ_LINE0 >+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 >+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL >+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L >+//HUBPRET1_HUBPRET_READ_LINE1 >+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 >+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL >+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L >+//HUBPRET1_HUBPRET_INTERRUPT >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L >+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L >+//HUBPRET1_HUBPRET_READ_LINE_VALUE >+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 >+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL >+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L >+//HUBPRET1_HUBPRET_READ_LINE_STATUS >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L >+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec >+//CURSOR0_1_CURSOR_CONTROL >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L >+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L >+//CURSOR0_1_CURSOR_SURFACE_ADDRESS >+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH >+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//CURSOR0_1_CURSOR_SIZE >+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 >+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL >+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L >+//CURSOR0_1_CURSOR_POSITION >+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 >+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL >+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L >+//CURSOR0_1_CURSOR_HOT_SPOT >+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 >+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL >+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L >+//CURSOR0_1_CURSOR_STEREO_CONTROL >+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 >+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 >+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L >+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L >+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L >+//CURSOR0_1_CURSOR_DST_OFFSET >+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL >+//CURSOR0_1_CURSOR_MEM_PWR_CTRL >+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 >+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 >+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L >+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L >+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L >+//CURSOR0_1_CURSOR_MEM_PWR_STATUS >+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 >+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L >+//CURSOR0_1_DMDATA_ADDRESS_HIGH >+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 >+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c >+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d >+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e >+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL >+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L >+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L >+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L >+//CURSOR0_1_DMDATA_ADDRESS_LOW >+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 >+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL >+//CURSOR0_1_DMDATA_CNTL >+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 >+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 >+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 >+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 >+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L >+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L >+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L >+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L >+//CURSOR0_1_DMDATA_QOS_CNTL >+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 >+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 >+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 >+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L >+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L >+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L >+//CURSOR0_1_DMDATA_STATUS >+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 >+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 >+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 >+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L >+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L >+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L >+//CURSOR0_1_DMDATA_SW_CNTL >+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 >+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 >+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 >+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L >+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L >+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L >+//CURSOR0_1_DMDATA_SW_DATA >+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 >+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON8_PERFCOUNTER_CNTL >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON8_PERFCOUNTER_CNTL2 >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON8_PERFCOUNTER_STATE >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON8_PERFMON_CNTL >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON8_PERFMON_CNTL2 >+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON8_PERFMON_CVALUE_LOW >+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON8_PERFMON_HI >+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON8_PERFMON_LOW >+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec >+//HUBP2_DCSURF_SURFACE_CONFIG >+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 >+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 >+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa >+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL >+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L >+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L >+//HUBP2_DCSURF_ADDR_CONFIG >+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 >+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 >+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 >+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 >+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa >+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc >+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L >+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L >+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L >+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L >+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L >+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L >+//HUBP2_DCSURF_TILING_CONFIG >+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 >+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 >+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 >+#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa >+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb >+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL >+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L >+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L >+#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L >+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L >+//HUBP2_DCSURF_PRI_VIEWPORT_START >+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 >+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 >+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL >+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L >+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION >+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 >+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 >+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL >+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L >+//HUBP2_DCSURF_PRI_VIEWPORT_START_C >+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 >+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 >+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL >+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L >+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C >+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 >+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 >+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL >+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L >+//HUBP2_DCSURF_SEC_VIEWPORT_START >+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 >+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 >+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL >+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L >+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION >+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 >+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 >+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL >+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L >+//HUBP2_DCSURF_SEC_VIEWPORT_START_C >+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 >+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 >+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL >+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L >+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C >+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 >+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 >+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL >+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L >+//HUBP2_DCHUBP_REQ_SIZE_CONFIG >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L >+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L >+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L >+//HUBP2_DCHUBP_CNTL >+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 >+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 >+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 >+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 >+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 >+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 >+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 >+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc >+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd >+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 >+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 >+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 >+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a >+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b >+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c >+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f >+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L >+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L >+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L >+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L >+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L >+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L >+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L >+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L >+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L >+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L >+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L >+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L >+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L >+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L >+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L >+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L >+//HUBP2_HUBP_CLK_CNTL >+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 >+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c >+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L >+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L >+//HUBP2_DCHUBP_VMPG_CONFIG >+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 >+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L >+//HUBP2_HUBPREQ_DEBUG_DB >+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 >+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL >+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L >+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L >+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec >+//HUBPREQ2_DCSURF_SURFACE_PITCH >+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 >+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL >+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L >+//HUBPREQ2_DCSURF_SURFACE_PITCH_C >+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 >+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL >+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L >+//HUBPREQ2_VMID_SETTINGS_0 >+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT 0x0 >+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK 0x0000000FL >+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS >+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH >+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C >+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS >+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH >+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C >+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS >+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH >+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C >+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS >+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH >+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C >+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_SURFACE_CONTROL >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L >+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L >+//HUBPREQ2_DCSURF_FLIP_CONTROL >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L >+//HUBPREQ2_DCSURF_FLIP_CONTROL2 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L >+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L >+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L >+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L >+//HUBPREQ2_DCSURF_SURFACE_INUSE >+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH >+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_SURFACE_INUSE_C >+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C >+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE >+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH >+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C >+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C >+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ2_DCN_EXPANSION_MODE >+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 >+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 >+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 >+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 >+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L >+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL >+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L >+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L >+//HUBPREQ2_DCN_TTU_QOS_WM >+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 >+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 >+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL >+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L >+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL >+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 >+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c >+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL >+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L >+//HUBPREQ2_DCN_SURF0_TTU_CNTL0 >+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ2_DCN_SURF0_TTU_CNTL1 >+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ2_DCN_SURF1_TTU_CNTL0 >+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ2_DCN_SURF1_TTU_CNTL1 >+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ2_DCN_CUR0_TTU_CNTL0 >+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ2_DCN_CUR0_TTU_CNTL1 >+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ2_DCN_CUR1_TTU_CNTL0 >+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ2_DCN_CUR1_TTU_CNTL1 >+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR >+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 >+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL >+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR >+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 >+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL >+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL >+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 >+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 >+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 >+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 >+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L >+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L >+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L >+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L >+//HUBPREQ2_BLANK_OFFSET_0 >+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 >+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 >+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL >+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L >+//HUBPREQ2_BLANK_OFFSET_1 >+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 >+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL >+//HUBPREQ2_DST_DIMENSIONS >+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 >+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL >+//HUBPREQ2_DST_AFTER_SCALER >+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 >+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 >+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL >+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L >+//HUBPREQ2_PREFETCH_SETTINGS >+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 >+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 >+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL >+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L >+//HUBPREQ2_PREFETCH_SETTINGS_C >+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 >+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL >+//HUBPREQ2_VBLANK_PARAMETERS_0 >+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 >+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 >+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL >+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L >+//HUBPREQ2_VBLANK_PARAMETERS_1 >+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 >+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL >+//HUBPREQ2_VBLANK_PARAMETERS_2 >+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 >+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL >+//HUBPREQ2_VBLANK_PARAMETERS_3 >+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 >+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL >+//HUBPREQ2_VBLANK_PARAMETERS_4 >+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 >+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL >+//HUBPREQ2_FLIP_PARAMETERS_0 >+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 >+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 >+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL >+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L >+//HUBPREQ2_FLIP_PARAMETERS_1 >+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 >+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL >+//HUBPREQ2_FLIP_PARAMETERS_2 >+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 >+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL >+//HUBPREQ2_NOM_PARAMETERS_0 >+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 >+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL >+//HUBPREQ2_NOM_PARAMETERS_1 >+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 >+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL >+//HUBPREQ2_NOM_PARAMETERS_2 >+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 >+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL >+//HUBPREQ2_NOM_PARAMETERS_3 >+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 >+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL >+//HUBPREQ2_NOM_PARAMETERS_4 >+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 >+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL >+//HUBPREQ2_NOM_PARAMETERS_5 >+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 >+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL >+//HUBPREQ2_NOM_PARAMETERS_6 >+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 >+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL >+//HUBPREQ2_NOM_PARAMETERS_7 >+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 >+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL >+//HUBPREQ2_PER_LINE_DELIVERY_PRE >+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 >+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 >+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL >+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L >+//HUBPREQ2_PER_LINE_DELIVERY >+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 >+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 >+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL >+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L >+//HUBPREQ2_CURSOR_SETTINGS >+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 >+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 >+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 >+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 >+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL >+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L >+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L >+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L >+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ >+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 >+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL >+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT >+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 >+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL >+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L >+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS >+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 >+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL >+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L >+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L >+//HUBPREQ2_VBLANK_PARAMETERS_5 >+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 >+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL >+//HUBPREQ2_VBLANK_PARAMETERS_6 >+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 >+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL >+//HUBPREQ2_FLIP_PARAMETERS_3 >+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 >+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL >+//HUBPREQ2_FLIP_PARAMETERS_4 >+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 >+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL >+//HUBPREQ2_FLIP_PARAMETERS_5 >+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 >+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL >+//HUBPREQ2_FLIP_PARAMETERS_6 >+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 >+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec >+//HUBPRET2_HUBPRET_CONTROL >+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc >+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 >+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 >+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 >+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 >+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 >+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL >+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L >+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L >+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L >+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L >+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L >+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L >+//HUBPRET2_HUBPRET_MEM_PWR_CTRL >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L >+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L >+//HUBPRET2_HUBPRET_MEM_PWR_STATUS >+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 >+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 >+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L >+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL >+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L >+//HUBPRET2_HUBPRET_READ_LINE_CTRL0 >+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 >+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL >+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L >+//HUBPRET2_HUBPRET_READ_LINE_CTRL1 >+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 >+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL >+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L >+//HUBPRET2_HUBPRET_READ_LINE0 >+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 >+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL >+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L >+//HUBPRET2_HUBPRET_READ_LINE1 >+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 >+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL >+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L >+//HUBPRET2_HUBPRET_INTERRUPT >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L >+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L >+//HUBPRET2_HUBPRET_READ_LINE_VALUE >+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 >+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL >+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L >+//HUBPRET2_HUBPRET_READ_LINE_STATUS >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L >+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec >+//CURSOR0_2_CURSOR_CONTROL >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L >+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L >+//CURSOR0_2_CURSOR_SURFACE_ADDRESS >+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH >+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//CURSOR0_2_CURSOR_SIZE >+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 >+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL >+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L >+//CURSOR0_2_CURSOR_POSITION >+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 >+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL >+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L >+//CURSOR0_2_CURSOR_HOT_SPOT >+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 >+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL >+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L >+//CURSOR0_2_CURSOR_STEREO_CONTROL >+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 >+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 >+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L >+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L >+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L >+//CURSOR0_2_CURSOR_DST_OFFSET >+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL >+//CURSOR0_2_CURSOR_MEM_PWR_CTRL >+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 >+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 >+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L >+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L >+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L >+//CURSOR0_2_CURSOR_MEM_PWR_STATUS >+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 >+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L >+//CURSOR0_2_DMDATA_ADDRESS_HIGH >+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 >+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c >+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d >+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e >+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL >+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L >+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L >+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L >+//CURSOR0_2_DMDATA_ADDRESS_LOW >+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 >+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL >+//CURSOR0_2_DMDATA_CNTL >+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 >+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 >+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 >+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 >+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L >+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L >+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L >+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L >+//CURSOR0_2_DMDATA_QOS_CNTL >+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 >+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 >+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 >+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L >+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L >+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L >+//CURSOR0_2_DMDATA_STATUS >+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 >+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 >+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 >+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L >+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L >+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L >+//CURSOR0_2_DMDATA_SW_CNTL >+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 >+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 >+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 >+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L >+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L >+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L >+//CURSOR0_2_DMDATA_SW_DATA >+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 >+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON9_PERFCOUNTER_CNTL >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON9_PERFCOUNTER_CNTL2 >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON9_PERFCOUNTER_STATE >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON9_PERFMON_CNTL >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON9_PERFMON_CNTL2 >+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON9_PERFMON_CVALUE_LOW >+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON9_PERFMON_HI >+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON9_PERFMON_LOW >+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec >+//HUBP3_DCSURF_SURFACE_CONFIG >+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 >+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 >+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa >+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL >+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L >+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L >+//HUBP3_DCSURF_ADDR_CONFIG >+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 >+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 >+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 >+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 >+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa >+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc >+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L >+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L >+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L >+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L >+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L >+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L >+//HUBP3_DCSURF_TILING_CONFIG >+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 >+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 >+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 >+#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa >+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb >+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL >+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L >+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L >+#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L >+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L >+//HUBP3_DCSURF_PRI_VIEWPORT_START >+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 >+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 >+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL >+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L >+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION >+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 >+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 >+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL >+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L >+//HUBP3_DCSURF_PRI_VIEWPORT_START_C >+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 >+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 >+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL >+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L >+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C >+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 >+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 >+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL >+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L >+//HUBP3_DCSURF_SEC_VIEWPORT_START >+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 >+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 >+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL >+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L >+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION >+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 >+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 >+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL >+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L >+//HUBP3_DCSURF_SEC_VIEWPORT_START_C >+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 >+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 >+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL >+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L >+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C >+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 >+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 >+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL >+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L >+//HUBP3_DCHUBP_REQ_SIZE_CONFIG >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L >+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L >+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L >+//HUBP3_DCHUBP_CNTL >+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 >+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 >+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 >+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 >+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 >+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 >+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 >+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc >+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd >+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 >+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 >+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 >+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a >+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b >+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c >+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f >+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L >+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L >+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L >+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L >+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L >+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L >+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L >+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L >+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L >+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L >+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L >+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L >+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L >+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L >+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L >+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L >+//HUBP3_HUBP_CLK_CNTL >+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 >+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c >+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L >+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L >+//HUBP3_DCHUBP_VMPG_CONFIG >+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 >+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L >+//HUBP3_HUBPREQ_DEBUG_DB >+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 >+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL >+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L >+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L >+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec >+//HUBPREQ3_DCSURF_SURFACE_PITCH >+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 >+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL >+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L >+//HUBPREQ3_DCSURF_SURFACE_PITCH_C >+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 >+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL >+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L >+//HUBPREQ3_VMID_SETTINGS_0 >+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT 0x0 >+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK 0x0000000FL >+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS >+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH >+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C >+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS >+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH >+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C >+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS >+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH >+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C >+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS >+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH >+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C >+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C >+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_SURFACE_CONTROL >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L >+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L >+//HUBPREQ3_DCSURF_FLIP_CONTROL >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L >+//HUBPREQ3_DCSURF_FLIP_CONTROL2 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L >+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L >+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L >+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L >+//HUBPREQ3_DCSURF_SURFACE_INUSE >+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH >+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_SURFACE_INUSE_C >+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C >+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE >+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH >+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C >+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL >+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C >+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 >+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL >+//HUBPREQ3_DCN_EXPANSION_MODE >+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 >+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 >+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 >+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 >+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L >+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL >+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L >+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L >+//HUBPREQ3_DCN_TTU_QOS_WM >+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 >+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 >+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL >+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L >+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL >+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 >+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c >+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL >+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L >+//HUBPREQ3_DCN_SURF0_TTU_CNTL0 >+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ3_DCN_SURF0_TTU_CNTL1 >+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ3_DCN_SURF1_TTU_CNTL0 >+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ3_DCN_SURF1_TTU_CNTL1 >+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ3_DCN_CUR0_TTU_CNTL0 >+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ3_DCN_CUR0_TTU_CNTL1 >+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ3_DCN_CUR1_TTU_CNTL0 >+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 >+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 >+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c >+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL >+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L >+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L >+//HUBPREQ3_DCN_CUR1_TTU_CNTL1 >+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 >+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL >+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR >+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 >+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL >+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR >+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 >+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL >+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL >+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 >+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 >+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 >+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 >+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L >+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L >+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L >+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L >+//HUBPREQ3_BLANK_OFFSET_0 >+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 >+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 >+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL >+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L >+//HUBPREQ3_BLANK_OFFSET_1 >+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 >+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL >+//HUBPREQ3_DST_DIMENSIONS >+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 >+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL >+//HUBPREQ3_DST_AFTER_SCALER >+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 >+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 >+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL >+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L >+//HUBPREQ3_PREFETCH_SETTINGS >+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 >+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 >+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL >+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L >+//HUBPREQ3_PREFETCH_SETTINGS_C >+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 >+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL >+//HUBPREQ3_VBLANK_PARAMETERS_0 >+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 >+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 >+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL >+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L >+//HUBPREQ3_VBLANK_PARAMETERS_1 >+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 >+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL >+//HUBPREQ3_VBLANK_PARAMETERS_2 >+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 >+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL >+//HUBPREQ3_VBLANK_PARAMETERS_3 >+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 >+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL >+//HUBPREQ3_VBLANK_PARAMETERS_4 >+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 >+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL >+//HUBPREQ3_FLIP_PARAMETERS_0 >+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 >+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 >+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL >+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L >+//HUBPREQ3_FLIP_PARAMETERS_1 >+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 >+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL >+//HUBPREQ3_FLIP_PARAMETERS_2 >+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 >+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL >+//HUBPREQ3_NOM_PARAMETERS_0 >+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 >+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL >+//HUBPREQ3_NOM_PARAMETERS_1 >+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 >+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL >+//HUBPREQ3_NOM_PARAMETERS_2 >+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 >+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL >+//HUBPREQ3_NOM_PARAMETERS_3 >+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 >+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL >+//HUBPREQ3_NOM_PARAMETERS_4 >+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 >+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL >+//HUBPREQ3_NOM_PARAMETERS_5 >+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 >+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL >+//HUBPREQ3_NOM_PARAMETERS_6 >+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 >+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL >+//HUBPREQ3_NOM_PARAMETERS_7 >+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 >+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL >+//HUBPREQ3_PER_LINE_DELIVERY_PRE >+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 >+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 >+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL >+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L >+//HUBPREQ3_PER_LINE_DELIVERY >+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 >+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 >+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL >+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L >+//HUBPREQ3_CURSOR_SETTINGS >+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 >+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 >+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 >+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 >+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL >+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L >+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L >+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L >+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ >+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 >+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL >+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT >+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 >+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL >+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L >+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS >+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 >+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL >+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L >+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L >+//HUBPREQ3_VBLANK_PARAMETERS_5 >+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 >+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL >+//HUBPREQ3_VBLANK_PARAMETERS_6 >+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 >+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL >+//HUBPREQ3_FLIP_PARAMETERS_3 >+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 >+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL >+//HUBPREQ3_FLIP_PARAMETERS_4 >+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 >+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL >+//HUBPREQ3_FLIP_PARAMETERS_5 >+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 >+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL >+//HUBPREQ3_FLIP_PARAMETERS_6 >+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 >+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec >+//HUBPRET3_HUBPRET_CONTROL >+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc >+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 >+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 >+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 >+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 >+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 >+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL >+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L >+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L >+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L >+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L >+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L >+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L >+//HUBPRET3_HUBPRET_MEM_PWR_CTRL >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L >+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L >+//HUBPRET3_HUBPRET_MEM_PWR_STATUS >+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 >+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 >+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L >+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL >+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L >+//HUBPRET3_HUBPRET_READ_LINE_CTRL0 >+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 >+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL >+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L >+//HUBPRET3_HUBPRET_READ_LINE_CTRL1 >+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 >+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL >+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L >+//HUBPRET3_HUBPRET_READ_LINE0 >+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 >+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL >+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L >+//HUBPRET3_HUBPRET_READ_LINE1 >+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 >+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL >+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L >+//HUBPRET3_HUBPRET_INTERRUPT >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L >+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L >+//HUBPRET3_HUBPRET_READ_LINE_VALUE >+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 >+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL >+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L >+//HUBPRET3_HUBPRET_READ_LINE_STATUS >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L >+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec >+//CURSOR0_3_CURSOR_CONTROL >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L >+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L >+//CURSOR0_3_CURSOR_SURFACE_ADDRESS >+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL >+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH >+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL >+//CURSOR0_3_CURSOR_SIZE >+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 >+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL >+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L >+//CURSOR0_3_CURSOR_POSITION >+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 >+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL >+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L >+//CURSOR0_3_CURSOR_HOT_SPOT >+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 >+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL >+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L >+//CURSOR0_3_CURSOR_STEREO_CONTROL >+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 >+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 >+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L >+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L >+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L >+//CURSOR0_3_CURSOR_DST_OFFSET >+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL >+//CURSOR0_3_CURSOR_MEM_PWR_CTRL >+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 >+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 >+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L >+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L >+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L >+//CURSOR0_3_CURSOR_MEM_PWR_STATUS >+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 >+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L >+//CURSOR0_3_DMDATA_ADDRESS_HIGH >+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 >+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c >+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d >+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e >+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL >+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L >+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L >+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L >+//CURSOR0_3_DMDATA_ADDRESS_LOW >+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 >+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL >+//CURSOR0_3_DMDATA_CNTL >+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 >+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 >+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 >+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 >+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L >+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L >+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L >+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L >+//CURSOR0_3_DMDATA_QOS_CNTL >+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 >+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 >+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 >+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L >+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L >+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L >+//CURSOR0_3_DMDATA_STATUS >+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 >+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 >+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 >+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L >+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L >+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L >+//CURSOR0_3_DMDATA_SW_CNTL >+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 >+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 >+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 >+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L >+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L >+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L >+//CURSOR0_3_DMDATA_SW_DATA >+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 >+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON10_PERFCOUNTER_CNTL >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON10_PERFCOUNTER_CNTL2 >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON10_PERFCOUNTER_STATE >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON10_PERFMON_CNTL >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON10_PERFMON_CNTL2 >+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON10_PERFMON_CVALUE_LOW >+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON10_PERFMON_HI >+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON10_PERFMON_LOW >+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec >+//DPP_TOP0_DPP_CONTROL >+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 >+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 >+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 >+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c >+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L >+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L >+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L >+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L >+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L >+//DPP_TOP0_DPP_SOFT_RESET >+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 >+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 >+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 >+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc >+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L >+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L >+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L >+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L >+//DPP_TOP0_DPP_CRC_VAL_R_G >+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 >+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 >+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL >+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L >+//DPP_TOP0_DPP_CRC_VAL_B_A >+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 >+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 >+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL >+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L >+//DPP_TOP0_DPP_CRC_CTRL >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L >+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L >+//DPP_TOP0_HOST_READ_CONTROL >+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 >+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec >+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT >+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 >+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL >+//CNVC_CFG0_FORMAT_CONTROL >+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 >+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 >+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 >+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc >+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd >+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 >+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 >+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 >+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L >+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L >+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L >+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L >+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L >+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L >+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L >+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L >+//CNVC_CFG0_FCNV_FP_BIAS_R >+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 >+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL >+//CNVC_CFG0_FCNV_FP_BIAS_G >+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 >+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL >+//CNVC_CFG0_FCNV_FP_BIAS_B >+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 >+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL >+//CNVC_CFG0_FCNV_FP_SCALE_R >+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 >+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL >+//CNVC_CFG0_FCNV_FP_SCALE_G >+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 >+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL >+//CNVC_CFG0_FCNV_FP_SCALE_B >+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 >+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL >+//CNVC_CFG0_COLOR_KEYER_CONTROL >+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 >+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 >+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L >+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L >+//CNVC_CFG0_COLOR_KEYER_ALPHA >+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 >+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 >+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG0_COLOR_KEYER_RED >+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 >+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 >+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG0_COLOR_KEYER_GREEN >+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 >+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 >+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG0_COLOR_KEYER_BLUE >+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 >+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 >+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG0_ALPHA_2BIT_LUT >+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 >+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 >+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 >+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 >+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL >+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L >+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L >+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec >+//CNVC_CUR0_CURSOR0_CONTROL >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L >+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L >+//CNVC_CUR0_CURSOR0_COLOR0 >+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 >+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL >+//CNVC_CUR0_CURSOR0_COLOR1 >+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 >+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL >+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS >+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 >+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 >+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL >+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec >+//DSCL0_SCL_COEF_RAM_TAP_SELECT >+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 >+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 >+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 >+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L >+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L >+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L >+//DSCL0_SCL_COEF_RAM_TAP_DATA >+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 >+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf >+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 >+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f >+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL >+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L >+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L >+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L >+//DSCL0_SCL_MODE >+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 >+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 >+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc >+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 >+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 >+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 >+#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L >+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L >+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L >+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L >+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L >+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L >+//DSCL0_SCL_TAP_CONTROL >+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 >+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 >+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 >+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc >+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L >+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L >+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L >+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L >+//DSCL0_DSCL_CONTROL >+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 >+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L >+//DSCL0_DSCL_2TAP_CONTROL >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L >+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L >+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL >+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 >+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 >+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL >+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L >+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO >+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 >+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL >+//DSCL0_SCL_HORZ_FILTER_INIT >+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 >+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 >+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL >+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L >+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C >+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 >+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL >+//DSCL0_SCL_HORZ_FILTER_INIT_C >+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 >+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 >+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL >+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L >+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO >+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 >+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL >+//DSCL0_SCL_VERT_FILTER_INIT >+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 >+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 >+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL >+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L >+//DSCL0_SCL_VERT_FILTER_INIT_BOT >+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 >+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 >+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL >+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L >+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C >+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 >+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL >+//DSCL0_SCL_VERT_FILTER_INIT_C >+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 >+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 >+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL >+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L >+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C >+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 >+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 >+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL >+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L >+//DSCL0_SCL_BLACK_OFFSET >+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 >+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 >+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL >+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L >+//DSCL0_DSCL_UPDATE >+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 >+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L >+//DSCL0_DSCL_AUTOCAL >+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 >+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 >+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc >+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L >+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L >+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L >+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT >+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 >+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 >+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL >+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L >+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM >+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 >+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 >+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL >+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L >+//DSCL0_OTG_H_BLANK >+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 >+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 >+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL >+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L >+//DSCL0_OTG_V_BLANK >+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 >+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 >+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL >+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L >+//DSCL0_RECOUT_START >+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 >+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 >+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL >+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L >+//DSCL0_RECOUT_SIZE >+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 >+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 >+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL >+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L >+//DSCL0_MPC_SIZE >+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 >+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 >+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL >+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L >+//DSCL0_LB_DATA_FORMAT >+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 >+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 >+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L >+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L >+//DSCL0_LB_MEMORY_CTRL >+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 >+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 >+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 >+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 >+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L >+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L >+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L >+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L >+//DSCL0_LB_V_COUNTER >+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 >+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 >+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL >+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L >+//DSCL0_DSCL_MEM_PWR_CTRL >+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c >+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L >+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L >+//DSCL0_DSCL_MEM_PWR_STATUS >+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc >+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L >+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L >+//DSCL0_OBUF_CONTROL >+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 >+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 >+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc >+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c >+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L >+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L >+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L >+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L >+//DSCL0_OBUF_MEM_PWR_CTRL >+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 >+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 >+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 >+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L >+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L >+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L >+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec >+//CM0_CM_CONTROL >+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0 >+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 >+#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L >+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L >+//CM0_CM_ICSC_CONTROL >+#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 >+#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L >+//CM0_CM_ICSC_C11_C12 >+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 >+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 >+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L >+//CM0_CM_ICSC_C13_C14 >+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 >+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 >+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L >+//CM0_CM_ICSC_C21_C22 >+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 >+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 >+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L >+//CM0_CM_ICSC_C23_C24 >+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 >+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 >+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L >+//CM0_CM_ICSC_C31_C32 >+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 >+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 >+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L >+//CM0_CM_ICSC_C33_C34 >+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 >+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 >+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L >+//CM0_CM_ICSC_B_C11_C12 >+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0 >+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10 >+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L >+//CM0_CM_ICSC_B_C13_C14 >+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0 >+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10 >+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L >+//CM0_CM_ICSC_B_C21_C22 >+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0 >+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10 >+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L >+//CM0_CM_ICSC_B_C23_C24 >+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0 >+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10 >+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L >+//CM0_CM_ICSC_B_C31_C32 >+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0 >+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10 >+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L >+//CM0_CM_ICSC_B_C33_C34 >+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0 >+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10 >+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL >+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_CONTROL >+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L >+//CM0_CM_GAMUT_REMAP_C11_C12 >+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_C13_C14 >+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_C21_C22 >+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_C23_C24 >+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_C31_C32 >+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_C33_C34 >+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_B_C11_C12 >+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_B_C13_C14 >+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_B_C21_C22 >+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_B_C23_C24 >+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_B_C31_C32 >+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L >+//CM0_CM_GAMUT_REMAP_B_C33_C34 >+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 >+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 >+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL >+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L >+//CM0_CM_BIAS_CR_R >+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 >+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL >+//CM0_CM_BIAS_Y_G_CB_B >+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 >+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 >+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL >+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L >+//CM0_CM_DGAM_CONTROL >+#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 >+#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L >+//CM0_CM_DGAM_LUT_INDEX >+#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 >+#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL >+//CM0_CM_DGAM_LUT_DATA >+#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 >+#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL >+//CM0_CM_DGAM_LUT_WRITE_EN_MASK >+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8 >+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc >+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L >+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L >+//CM0_CM_DGAM_RAMA_START_CNTL_B >+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM0_CM_DGAM_RAMA_START_CNTL_G >+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM0_CM_DGAM_RAMA_START_CNTL_R >+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_B >+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_G >+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_R >+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM0_CM_DGAM_RAMA_END_CNTL1_B >+#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM0_CM_DGAM_RAMA_END_CNTL2_B >+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM0_CM_DGAM_RAMA_END_CNTL1_G >+#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM0_CM_DGAM_RAMA_END_CNTL2_G >+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM0_CM_DGAM_RAMA_END_CNTL1_R >+#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM0_CM_DGAM_RAMA_END_CNTL2_R >+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM0_CM_DGAM_RAMA_REGION_0_1 >+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMA_REGION_2_3 >+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMA_REGION_4_5 >+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMA_REGION_6_7 >+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMA_REGION_8_9 >+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMA_REGION_10_11 >+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMA_REGION_12_13 >+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMA_REGION_14_15 >+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMB_START_CNTL_B >+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM0_CM_DGAM_RAMB_START_CNTL_G >+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM0_CM_DGAM_RAMB_START_CNTL_R >+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_B >+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_G >+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_R >+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM0_CM_DGAM_RAMB_END_CNTL1_B >+#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM0_CM_DGAM_RAMB_END_CNTL2_B >+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM0_CM_DGAM_RAMB_END_CNTL1_G >+#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM0_CM_DGAM_RAMB_END_CNTL2_G >+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM0_CM_DGAM_RAMB_END_CNTL1_R >+#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM0_CM_DGAM_RAMB_END_CNTL2_R >+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM0_CM_DGAM_RAMB_REGION_0_1 >+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMB_REGION_2_3 >+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMB_REGION_4_5 >+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMB_REGION_6_7 >+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMB_REGION_8_9 >+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMB_REGION_10_11 >+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMB_REGION_12_13 >+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_DGAM_RAMB_REGION_14_15 >+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_CONTROL >+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L >+//CM0_CM_BLNDGAM_LUT_INDEX >+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL >+//CM0_CM_BLNDGAM_LUT_DATA >+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL >+//CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK >+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8 >+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L >+//CM0_CM_BLNDGAM_RAMA_START_CNTL_B >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM0_CM_BLNDGAM_RAMA_START_CNTL_G >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM0_CM_BLNDGAM_RAMA_START_CNTL_R >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B >+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G >+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R >+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM0_CM_BLNDGAM_RAMA_REGION_0_1 >+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_2_3 >+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_4_5 >+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_6_7 >+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_8_9 >+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_10_11 >+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_12_13 >+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_14_15 >+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_16_17 >+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_18_19 >+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_20_21 >+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_22_23 >+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_24_25 >+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_26_27 >+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_28_29 >+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_30_31 >+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMA_REGION_32_33 >+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_START_CNTL_B >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM0_CM_BLNDGAM_RAMB_START_CNTL_G >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM0_CM_BLNDGAM_RAMB_START_CNTL_R >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B >+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G >+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R >+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM0_CM_BLNDGAM_RAMB_REGION_0_1 >+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_2_3 >+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_4_5 >+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_6_7 >+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_8_9 >+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_10_11 >+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_12_13 >+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_14_15 >+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_16_17 >+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_18_19 >+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_20_21 >+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_22_23 >+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_24_25 >+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_26_27 >+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_28_29 >+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_30_31 >+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_BLNDGAM_RAMB_REGION_32_33 >+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_HDR_MULT_COEF >+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 >+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL >+//CM0_CM_MEM_PWR_CTRL >+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 >+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 >+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 >+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 >+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L >+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L >+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L >+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L >+//CM0_CM_MEM_PWR_STATUS >+#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 >+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 >+#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L >+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL >+//CM0_CM_DEALPHA >+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 >+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L >+//CM0_CM_COEF_FORMAT >+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 >+#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4 >+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 >+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L >+#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L >+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L >+//CM0_CM_SHAPER_CONTROL >+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 >+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L >+//CM0_CM_SHAPER_OFFSET_R >+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 >+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL >+//CM0_CM_SHAPER_OFFSET_G >+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 >+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL >+//CM0_CM_SHAPER_OFFSET_B >+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 >+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL >+//CM0_CM_SHAPER_SCALE_R >+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 >+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL >+//CM0_CM_SHAPER_SCALE_G_B >+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 >+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 >+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL >+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L >+//CM0_CM_SHAPER_LUT_INDEX >+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 >+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL >+//CM0_CM_SHAPER_LUT_DATA >+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 >+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL >+//CM0_CM_SHAPER_LUT_WRITE_EN_MASK >+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8 >+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L >+//CM0_CM_SHAPER_RAMA_START_CNTL_B >+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM0_CM_SHAPER_RAMA_START_CNTL_G >+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM0_CM_SHAPER_RAMA_START_CNTL_R >+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM0_CM_SHAPER_RAMA_END_CNTL_B >+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L >+//CM0_CM_SHAPER_RAMA_END_CNTL_G >+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L >+//CM0_CM_SHAPER_RAMA_END_CNTL_R >+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L >+//CM0_CM_SHAPER_RAMA_REGION_0_1 >+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_2_3 >+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_4_5 >+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_6_7 >+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_8_9 >+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_10_11 >+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_12_13 >+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_14_15 >+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_16_17 >+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_18_19 >+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_20_21 >+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_22_23 >+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_24_25 >+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_26_27 >+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_28_29 >+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_30_31 >+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMA_REGION_32_33 >+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_START_CNTL_B >+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM0_CM_SHAPER_RAMB_START_CNTL_G >+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM0_CM_SHAPER_RAMB_START_CNTL_R >+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM0_CM_SHAPER_RAMB_END_CNTL_B >+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L >+//CM0_CM_SHAPER_RAMB_END_CNTL_G >+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L >+//CM0_CM_SHAPER_RAMB_END_CNTL_R >+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L >+//CM0_CM_SHAPER_RAMB_REGION_0_1 >+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_2_3 >+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_4_5 >+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_6_7 >+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_8_9 >+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_10_11 >+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_12_13 >+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_14_15 >+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_16_17 >+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_18_19 >+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_20_21 >+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_22_23 >+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_24_25 >+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_26_27 >+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_28_29 >+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_30_31 >+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_SHAPER_RAMB_REGION_32_33 >+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM0_CM_MEM_PWR_CTRL2 >+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 >+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa >+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc >+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe >+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L >+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L >+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L >+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L >+//CM0_CM_MEM_PWR_STATUS2 >+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 >+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 >+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L >+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L >+//CM0_CM_3DLUT_MODE >+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 >+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 >+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L >+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L >+//CM0_CM_3DLUT_INDEX >+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 >+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL >+//CM0_CM_3DLUT_DATA >+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 >+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 >+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL >+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L >+//CM0_CM_3DLUT_DATA_30BIT >+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 >+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL >+//CM0_CM_3DLUT_READ_WRITE_CONTROL >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L >+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L >+//CM0_CM_3DLUT_OUT_NORM_FACTOR >+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 >+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL >+//CM0_CM_3DLUT_OUT_OFFSET_R >+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 >+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 >+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL >+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L >+//CM0_CM_3DLUT_OUT_OFFSET_G >+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 >+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 >+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL >+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L >+//CM0_CM_3DLUT_OUT_OFFSET_B >+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 >+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 >+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL >+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L >+//CM0_CM_TEST_DEBUG_INDEX >+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//CM0_CM_TEST_DEBUG_DATA >+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 >+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON11_PERFCOUNTER_CNTL >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON11_PERFCOUNTER_CNTL2 >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON11_PERFCOUNTER_STATE >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON11_PERFMON_CNTL >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON11_PERFMON_CNTL2 >+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON11_PERFMON_CVALUE_LOW >+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON11_PERFMON_HI >+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON11_PERFMON_LOW >+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec >+//DPP_TOP1_DPP_CONTROL >+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 >+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 >+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 >+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c >+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L >+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L >+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L >+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L >+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L >+//DPP_TOP1_DPP_SOFT_RESET >+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 >+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 >+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 >+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc >+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L >+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L >+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L >+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L >+//DPP_TOP1_DPP_CRC_VAL_R_G >+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 >+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 >+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL >+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L >+//DPP_TOP1_DPP_CRC_VAL_B_A >+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 >+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 >+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL >+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L >+//DPP_TOP1_DPP_CRC_CTRL >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L >+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L >+//DPP_TOP1_HOST_READ_CONTROL >+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 >+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec >+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT >+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 >+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL >+//CNVC_CFG1_FORMAT_CONTROL >+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 >+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 >+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 >+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc >+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd >+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 >+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 >+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 >+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L >+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L >+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L >+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L >+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L >+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L >+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L >+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L >+//CNVC_CFG1_FCNV_FP_BIAS_R >+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 >+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL >+//CNVC_CFG1_FCNV_FP_BIAS_G >+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 >+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL >+//CNVC_CFG1_FCNV_FP_BIAS_B >+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 >+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL >+//CNVC_CFG1_FCNV_FP_SCALE_R >+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 >+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL >+//CNVC_CFG1_FCNV_FP_SCALE_G >+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 >+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL >+//CNVC_CFG1_FCNV_FP_SCALE_B >+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 >+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL >+//CNVC_CFG1_COLOR_KEYER_CONTROL >+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 >+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 >+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L >+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L >+//CNVC_CFG1_COLOR_KEYER_ALPHA >+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 >+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 >+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG1_COLOR_KEYER_RED >+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 >+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 >+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG1_COLOR_KEYER_GREEN >+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 >+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 >+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG1_COLOR_KEYER_BLUE >+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 >+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 >+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG1_ALPHA_2BIT_LUT >+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 >+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 >+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 >+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 >+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL >+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L >+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L >+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec >+//CNVC_CUR1_CURSOR0_CONTROL >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L >+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L >+//CNVC_CUR1_CURSOR0_COLOR0 >+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 >+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL >+//CNVC_CUR1_CURSOR0_COLOR1 >+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 >+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL >+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS >+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 >+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 >+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL >+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec >+//DSCL1_SCL_COEF_RAM_TAP_SELECT >+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 >+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 >+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 >+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L >+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L >+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L >+//DSCL1_SCL_COEF_RAM_TAP_DATA >+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 >+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf >+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 >+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f >+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL >+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L >+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L >+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L >+//DSCL1_SCL_MODE >+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 >+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 >+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc >+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 >+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 >+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 >+#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L >+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L >+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L >+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L >+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L >+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L >+//DSCL1_SCL_TAP_CONTROL >+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 >+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 >+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 >+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc >+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L >+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L >+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L >+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L >+//DSCL1_DSCL_CONTROL >+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 >+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L >+//DSCL1_DSCL_2TAP_CONTROL >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L >+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L >+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL >+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 >+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 >+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL >+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L >+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO >+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 >+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL >+//DSCL1_SCL_HORZ_FILTER_INIT >+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 >+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 >+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL >+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L >+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C >+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 >+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL >+//DSCL1_SCL_HORZ_FILTER_INIT_C >+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 >+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 >+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL >+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L >+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO >+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 >+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL >+//DSCL1_SCL_VERT_FILTER_INIT >+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 >+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 >+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL >+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L >+//DSCL1_SCL_VERT_FILTER_INIT_BOT >+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 >+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 >+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL >+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L >+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C >+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 >+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL >+//DSCL1_SCL_VERT_FILTER_INIT_C >+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 >+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 >+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL >+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L >+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C >+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 >+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 >+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL >+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L >+//DSCL1_SCL_BLACK_OFFSET >+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 >+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 >+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL >+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L >+//DSCL1_DSCL_UPDATE >+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 >+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L >+//DSCL1_DSCL_AUTOCAL >+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 >+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 >+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc >+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L >+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L >+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L >+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT >+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 >+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 >+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL >+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L >+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM >+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 >+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 >+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL >+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L >+//DSCL1_OTG_H_BLANK >+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 >+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 >+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL >+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L >+//DSCL1_OTG_V_BLANK >+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 >+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 >+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL >+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L >+//DSCL1_RECOUT_START >+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 >+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 >+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL >+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L >+//DSCL1_RECOUT_SIZE >+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 >+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 >+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL >+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L >+//DSCL1_MPC_SIZE >+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 >+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 >+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL >+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L >+//DSCL1_LB_DATA_FORMAT >+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 >+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 >+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L >+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L >+//DSCL1_LB_MEMORY_CTRL >+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 >+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 >+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 >+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 >+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L >+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L >+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L >+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L >+//DSCL1_LB_V_COUNTER >+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 >+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 >+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL >+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L >+//DSCL1_DSCL_MEM_PWR_CTRL >+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c >+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L >+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L >+//DSCL1_DSCL_MEM_PWR_STATUS >+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc >+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L >+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L >+//DSCL1_OBUF_CONTROL >+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 >+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 >+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc >+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c >+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L >+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L >+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L >+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L >+//DSCL1_OBUF_MEM_PWR_CTRL >+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 >+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 >+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 >+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L >+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L >+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L >+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec >+//CM1_CM_CONTROL >+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0 >+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 >+#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L >+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L >+//CM1_CM_ICSC_CONTROL >+#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 >+#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L >+//CM1_CM_ICSC_C11_C12 >+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 >+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 >+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L >+//CM1_CM_ICSC_C13_C14 >+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 >+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 >+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L >+//CM1_CM_ICSC_C21_C22 >+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 >+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 >+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L >+//CM1_CM_ICSC_C23_C24 >+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 >+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 >+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L >+//CM1_CM_ICSC_C31_C32 >+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 >+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 >+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L >+//CM1_CM_ICSC_C33_C34 >+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 >+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 >+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L >+//CM1_CM_ICSC_B_C11_C12 >+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0 >+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10 >+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L >+//CM1_CM_ICSC_B_C13_C14 >+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0 >+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10 >+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L >+//CM1_CM_ICSC_B_C21_C22 >+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0 >+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10 >+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L >+//CM1_CM_ICSC_B_C23_C24 >+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0 >+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10 >+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L >+//CM1_CM_ICSC_B_C31_C32 >+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0 >+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10 >+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L >+//CM1_CM_ICSC_B_C33_C34 >+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0 >+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10 >+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL >+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_CONTROL >+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L >+//CM1_CM_GAMUT_REMAP_C11_C12 >+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_C13_C14 >+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_C21_C22 >+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_C23_C24 >+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_C31_C32 >+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_C33_C34 >+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_B_C11_C12 >+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_B_C13_C14 >+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_B_C21_C22 >+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_B_C23_C24 >+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_B_C31_C32 >+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L >+//CM1_CM_GAMUT_REMAP_B_C33_C34 >+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 >+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 >+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL >+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L >+//CM1_CM_BIAS_CR_R >+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 >+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL >+//CM1_CM_BIAS_Y_G_CB_B >+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 >+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 >+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL >+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L >+//CM1_CM_DGAM_CONTROL >+#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 >+#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L >+//CM1_CM_DGAM_LUT_INDEX >+#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 >+#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL >+//CM1_CM_DGAM_LUT_DATA >+#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 >+#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL >+//CM1_CM_DGAM_LUT_WRITE_EN_MASK >+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8 >+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc >+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L >+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L >+//CM1_CM_DGAM_RAMA_START_CNTL_B >+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM1_CM_DGAM_RAMA_START_CNTL_G >+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM1_CM_DGAM_RAMA_START_CNTL_R >+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_B >+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_G >+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_R >+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM1_CM_DGAM_RAMA_END_CNTL1_B >+#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM1_CM_DGAM_RAMA_END_CNTL2_B >+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM1_CM_DGAM_RAMA_END_CNTL1_G >+#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM1_CM_DGAM_RAMA_END_CNTL2_G >+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM1_CM_DGAM_RAMA_END_CNTL1_R >+#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM1_CM_DGAM_RAMA_END_CNTL2_R >+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM1_CM_DGAM_RAMA_REGION_0_1 >+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMA_REGION_2_3 >+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMA_REGION_4_5 >+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMA_REGION_6_7 >+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMA_REGION_8_9 >+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMA_REGION_10_11 >+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMA_REGION_12_13 >+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMA_REGION_14_15 >+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMB_START_CNTL_B >+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM1_CM_DGAM_RAMB_START_CNTL_G >+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM1_CM_DGAM_RAMB_START_CNTL_R >+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_B >+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_G >+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_R >+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM1_CM_DGAM_RAMB_END_CNTL1_B >+#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM1_CM_DGAM_RAMB_END_CNTL2_B >+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM1_CM_DGAM_RAMB_END_CNTL1_G >+#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM1_CM_DGAM_RAMB_END_CNTL2_G >+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM1_CM_DGAM_RAMB_END_CNTL1_R >+#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM1_CM_DGAM_RAMB_END_CNTL2_R >+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM1_CM_DGAM_RAMB_REGION_0_1 >+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMB_REGION_2_3 >+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMB_REGION_4_5 >+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMB_REGION_6_7 >+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMB_REGION_8_9 >+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMB_REGION_10_11 >+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMB_REGION_12_13 >+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_DGAM_RAMB_REGION_14_15 >+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_CONTROL >+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L >+//CM1_CM_BLNDGAM_LUT_INDEX >+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL >+//CM1_CM_BLNDGAM_LUT_DATA >+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL >+//CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK >+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8 >+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L >+//CM1_CM_BLNDGAM_RAMA_START_CNTL_B >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM1_CM_BLNDGAM_RAMA_START_CNTL_G >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM1_CM_BLNDGAM_RAMA_START_CNTL_R >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B >+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G >+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R >+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM1_CM_BLNDGAM_RAMA_REGION_0_1 >+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_2_3 >+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_4_5 >+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_6_7 >+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_8_9 >+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_10_11 >+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_12_13 >+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_14_15 >+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_16_17 >+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_18_19 >+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_20_21 >+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_22_23 >+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_24_25 >+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_26_27 >+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_28_29 >+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_30_31 >+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMA_REGION_32_33 >+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_START_CNTL_B >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM1_CM_BLNDGAM_RAMB_START_CNTL_G >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM1_CM_BLNDGAM_RAMB_START_CNTL_R >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B >+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G >+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R >+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM1_CM_BLNDGAM_RAMB_REGION_0_1 >+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_2_3 >+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_4_5 >+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_6_7 >+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_8_9 >+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_10_11 >+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_12_13 >+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_14_15 >+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_16_17 >+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_18_19 >+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_20_21 >+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_22_23 >+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_24_25 >+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_26_27 >+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_28_29 >+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_30_31 >+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_BLNDGAM_RAMB_REGION_32_33 >+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_HDR_MULT_COEF >+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 >+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL >+//CM1_CM_MEM_PWR_CTRL >+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 >+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 >+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 >+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 >+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L >+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L >+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L >+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L >+//CM1_CM_MEM_PWR_STATUS >+#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 >+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 >+#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L >+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL >+//CM1_CM_DEALPHA >+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 >+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L >+//CM1_CM_COEF_FORMAT >+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 >+#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4 >+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 >+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L >+#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L >+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L >+//CM1_CM_SHAPER_CONTROL >+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 >+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L >+//CM1_CM_SHAPER_OFFSET_R >+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 >+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL >+//CM1_CM_SHAPER_OFFSET_G >+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 >+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL >+//CM1_CM_SHAPER_OFFSET_B >+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 >+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL >+//CM1_CM_SHAPER_SCALE_R >+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 >+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL >+//CM1_CM_SHAPER_SCALE_G_B >+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 >+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 >+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL >+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L >+//CM1_CM_SHAPER_LUT_INDEX >+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 >+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL >+//CM1_CM_SHAPER_LUT_DATA >+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 >+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL >+//CM1_CM_SHAPER_LUT_WRITE_EN_MASK >+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8 >+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L >+//CM1_CM_SHAPER_RAMA_START_CNTL_B >+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM1_CM_SHAPER_RAMA_START_CNTL_G >+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM1_CM_SHAPER_RAMA_START_CNTL_R >+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM1_CM_SHAPER_RAMA_END_CNTL_B >+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L >+//CM1_CM_SHAPER_RAMA_END_CNTL_G >+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L >+//CM1_CM_SHAPER_RAMA_END_CNTL_R >+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L >+//CM1_CM_SHAPER_RAMA_REGION_0_1 >+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_2_3 >+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_4_5 >+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_6_7 >+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_8_9 >+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_10_11 >+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_12_13 >+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_14_15 >+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_16_17 >+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_18_19 >+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_20_21 >+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_22_23 >+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_24_25 >+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_26_27 >+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_28_29 >+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_30_31 >+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMA_REGION_32_33 >+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_START_CNTL_B >+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM1_CM_SHAPER_RAMB_START_CNTL_G >+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM1_CM_SHAPER_RAMB_START_CNTL_R >+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM1_CM_SHAPER_RAMB_END_CNTL_B >+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L >+//CM1_CM_SHAPER_RAMB_END_CNTL_G >+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L >+//CM1_CM_SHAPER_RAMB_END_CNTL_R >+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L >+//CM1_CM_SHAPER_RAMB_REGION_0_1 >+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_2_3 >+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_4_5 >+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_6_7 >+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_8_9 >+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_10_11 >+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_12_13 >+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_14_15 >+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_16_17 >+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_18_19 >+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_20_21 >+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_22_23 >+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_24_25 >+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_26_27 >+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_28_29 >+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_30_31 >+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_SHAPER_RAMB_REGION_32_33 >+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM1_CM_MEM_PWR_CTRL2 >+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 >+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa >+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc >+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe >+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L >+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L >+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L >+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L >+//CM1_CM_MEM_PWR_STATUS2 >+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 >+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 >+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L >+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L >+//CM1_CM_3DLUT_MODE >+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 >+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 >+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L >+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L >+//CM1_CM_3DLUT_INDEX >+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 >+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL >+//CM1_CM_3DLUT_DATA >+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 >+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 >+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL >+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L >+//CM1_CM_3DLUT_DATA_30BIT >+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 >+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL >+//CM1_CM_3DLUT_READ_WRITE_CONTROL >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L >+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L >+//CM1_CM_3DLUT_OUT_NORM_FACTOR >+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 >+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL >+//CM1_CM_3DLUT_OUT_OFFSET_R >+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 >+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 >+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL >+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L >+//CM1_CM_3DLUT_OUT_OFFSET_G >+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 >+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 >+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL >+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L >+//CM1_CM_3DLUT_OUT_OFFSET_B >+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 >+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 >+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL >+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L >+//CM1_CM_TEST_DEBUG_INDEX >+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//CM1_CM_TEST_DEBUG_DATA >+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 >+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON12_PERFCOUNTER_CNTL >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON12_PERFCOUNTER_CNTL2 >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON12_PERFCOUNTER_STATE >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON12_PERFMON_CNTL >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON12_PERFMON_CNTL2 >+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON12_PERFMON_CVALUE_LOW >+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON12_PERFMON_HI >+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON12_PERFMON_LOW >+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec >+//DPP_TOP2_DPP_CONTROL >+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 >+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 >+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 >+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c >+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L >+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L >+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L >+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L >+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L >+//DPP_TOP2_DPP_SOFT_RESET >+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 >+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 >+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 >+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc >+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L >+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L >+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L >+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L >+//DPP_TOP2_DPP_CRC_VAL_R_G >+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 >+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 >+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL >+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L >+//DPP_TOP2_DPP_CRC_VAL_B_A >+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 >+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 >+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL >+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L >+//DPP_TOP2_DPP_CRC_CTRL >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L >+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L >+//DPP_TOP2_HOST_READ_CONTROL >+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 >+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec >+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT >+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 >+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL >+//CNVC_CFG2_FORMAT_CONTROL >+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 >+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 >+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 >+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc >+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd >+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 >+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 >+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 >+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L >+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L >+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L >+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L >+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L >+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L >+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L >+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L >+//CNVC_CFG2_FCNV_FP_BIAS_R >+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 >+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL >+//CNVC_CFG2_FCNV_FP_BIAS_G >+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 >+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL >+//CNVC_CFG2_FCNV_FP_BIAS_B >+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 >+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL >+//CNVC_CFG2_FCNV_FP_SCALE_R >+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 >+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL >+//CNVC_CFG2_FCNV_FP_SCALE_G >+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 >+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL >+//CNVC_CFG2_FCNV_FP_SCALE_B >+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 >+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL >+//CNVC_CFG2_COLOR_KEYER_CONTROL >+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 >+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 >+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L >+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L >+//CNVC_CFG2_COLOR_KEYER_ALPHA >+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 >+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 >+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG2_COLOR_KEYER_RED >+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 >+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 >+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG2_COLOR_KEYER_GREEN >+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 >+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 >+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG2_COLOR_KEYER_BLUE >+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 >+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 >+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG2_ALPHA_2BIT_LUT >+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 >+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 >+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 >+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 >+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL >+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L >+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L >+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec >+//CNVC_CUR2_CURSOR0_CONTROL >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L >+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L >+//CNVC_CUR2_CURSOR0_COLOR0 >+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 >+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL >+//CNVC_CUR2_CURSOR0_COLOR1 >+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 >+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL >+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS >+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 >+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 >+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL >+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec >+//DSCL2_SCL_COEF_RAM_TAP_SELECT >+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 >+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 >+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 >+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L >+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L >+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L >+//DSCL2_SCL_COEF_RAM_TAP_DATA >+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 >+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf >+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 >+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f >+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL >+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L >+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L >+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L >+//DSCL2_SCL_MODE >+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 >+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 >+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc >+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 >+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 >+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 >+#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L >+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L >+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L >+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L >+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L >+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L >+//DSCL2_SCL_TAP_CONTROL >+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 >+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 >+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 >+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc >+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L >+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L >+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L >+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L >+//DSCL2_DSCL_CONTROL >+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 >+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L >+//DSCL2_DSCL_2TAP_CONTROL >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L >+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L >+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL >+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 >+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 >+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL >+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L >+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO >+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 >+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL >+//DSCL2_SCL_HORZ_FILTER_INIT >+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 >+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 >+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL >+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L >+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C >+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 >+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL >+//DSCL2_SCL_HORZ_FILTER_INIT_C >+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 >+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 >+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL >+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L >+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO >+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 >+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL >+//DSCL2_SCL_VERT_FILTER_INIT >+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 >+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 >+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL >+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L >+//DSCL2_SCL_VERT_FILTER_INIT_BOT >+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 >+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 >+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL >+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L >+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C >+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 >+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL >+//DSCL2_SCL_VERT_FILTER_INIT_C >+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 >+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 >+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL >+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L >+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C >+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 >+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 >+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL >+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L >+//DSCL2_SCL_BLACK_OFFSET >+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 >+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 >+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL >+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L >+//DSCL2_DSCL_UPDATE >+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 >+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L >+//DSCL2_DSCL_AUTOCAL >+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 >+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 >+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc >+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L >+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L >+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L >+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT >+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 >+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 >+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL >+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L >+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM >+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 >+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 >+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL >+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L >+//DSCL2_OTG_H_BLANK >+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 >+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 >+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL >+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L >+//DSCL2_OTG_V_BLANK >+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 >+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 >+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL >+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L >+//DSCL2_RECOUT_START >+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 >+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 >+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL >+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L >+//DSCL2_RECOUT_SIZE >+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 >+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 >+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL >+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L >+//DSCL2_MPC_SIZE >+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 >+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 >+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL >+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L >+//DSCL2_LB_DATA_FORMAT >+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 >+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 >+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L >+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L >+//DSCL2_LB_MEMORY_CTRL >+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 >+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 >+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 >+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 >+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L >+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L >+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L >+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L >+//DSCL2_LB_V_COUNTER >+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 >+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 >+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL >+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L >+//DSCL2_DSCL_MEM_PWR_CTRL >+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c >+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L >+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L >+//DSCL2_DSCL_MEM_PWR_STATUS >+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc >+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L >+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L >+//DSCL2_OBUF_CONTROL >+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 >+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 >+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc >+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c >+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L >+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L >+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L >+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L >+//DSCL2_OBUF_MEM_PWR_CTRL >+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 >+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 >+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 >+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L >+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L >+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L >+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec >+//CM2_CM_CONTROL >+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT 0x0 >+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 >+#define CM2_CM_CONTROL__CM_BYPASS_MASK 0x00000001L >+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L >+//CM2_CM_ICSC_CONTROL >+#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 >+#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L >+//CM2_CM_ICSC_C11_C12 >+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 >+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 >+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L >+//CM2_CM_ICSC_C13_C14 >+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 >+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 >+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L >+//CM2_CM_ICSC_C21_C22 >+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 >+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 >+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L >+//CM2_CM_ICSC_C23_C24 >+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 >+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 >+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L >+//CM2_CM_ICSC_C31_C32 >+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 >+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 >+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L >+//CM2_CM_ICSC_C33_C34 >+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 >+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 >+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L >+//CM2_CM_ICSC_B_C11_C12 >+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0 >+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10 >+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L >+//CM2_CM_ICSC_B_C13_C14 >+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0 >+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10 >+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L >+//CM2_CM_ICSC_B_C21_C22 >+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0 >+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10 >+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L >+//CM2_CM_ICSC_B_C23_C24 >+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0 >+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10 >+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L >+//CM2_CM_ICSC_B_C31_C32 >+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0 >+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10 >+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L >+//CM2_CM_ICSC_B_C33_C34 >+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0 >+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10 >+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL >+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_CONTROL >+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L >+//CM2_CM_GAMUT_REMAP_C11_C12 >+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_C13_C14 >+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_C21_C22 >+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_C23_C24 >+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_C31_C32 >+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_C33_C34 >+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_B_C11_C12 >+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_B_C13_C14 >+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_B_C21_C22 >+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_B_C23_C24 >+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_B_C31_C32 >+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L >+//CM2_CM_GAMUT_REMAP_B_C33_C34 >+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 >+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 >+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL >+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L >+//CM2_CM_BIAS_CR_R >+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 >+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL >+//CM2_CM_BIAS_Y_G_CB_B >+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 >+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 >+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL >+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L >+//CM2_CM_DGAM_CONTROL >+#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 >+#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L >+//CM2_CM_DGAM_LUT_INDEX >+#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 >+#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL >+//CM2_CM_DGAM_LUT_DATA >+#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 >+#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL >+//CM2_CM_DGAM_LUT_WRITE_EN_MASK >+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8 >+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc >+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L >+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L >+//CM2_CM_DGAM_RAMA_START_CNTL_B >+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM2_CM_DGAM_RAMA_START_CNTL_G >+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM2_CM_DGAM_RAMA_START_CNTL_R >+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_B >+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_G >+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_R >+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM2_CM_DGAM_RAMA_END_CNTL1_B >+#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM2_CM_DGAM_RAMA_END_CNTL2_B >+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM2_CM_DGAM_RAMA_END_CNTL1_G >+#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM2_CM_DGAM_RAMA_END_CNTL2_G >+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM2_CM_DGAM_RAMA_END_CNTL1_R >+#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM2_CM_DGAM_RAMA_END_CNTL2_R >+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM2_CM_DGAM_RAMA_REGION_0_1 >+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMA_REGION_2_3 >+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMA_REGION_4_5 >+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMA_REGION_6_7 >+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMA_REGION_8_9 >+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMA_REGION_10_11 >+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMA_REGION_12_13 >+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMA_REGION_14_15 >+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMB_START_CNTL_B >+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM2_CM_DGAM_RAMB_START_CNTL_G >+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM2_CM_DGAM_RAMB_START_CNTL_R >+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_B >+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_G >+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_R >+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM2_CM_DGAM_RAMB_END_CNTL1_B >+#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM2_CM_DGAM_RAMB_END_CNTL2_B >+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM2_CM_DGAM_RAMB_END_CNTL1_G >+#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM2_CM_DGAM_RAMB_END_CNTL2_G >+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM2_CM_DGAM_RAMB_END_CNTL1_R >+#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM2_CM_DGAM_RAMB_END_CNTL2_R >+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM2_CM_DGAM_RAMB_REGION_0_1 >+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMB_REGION_2_3 >+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMB_REGION_4_5 >+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMB_REGION_6_7 >+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMB_REGION_8_9 >+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMB_REGION_10_11 >+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMB_REGION_12_13 >+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_DGAM_RAMB_REGION_14_15 >+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_CONTROL >+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L >+//CM2_CM_BLNDGAM_LUT_INDEX >+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL >+//CM2_CM_BLNDGAM_LUT_DATA >+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL >+//CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK >+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8 >+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L >+//CM2_CM_BLNDGAM_RAMA_START_CNTL_B >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM2_CM_BLNDGAM_RAMA_START_CNTL_G >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM2_CM_BLNDGAM_RAMA_START_CNTL_R >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B >+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G >+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R >+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM2_CM_BLNDGAM_RAMA_REGION_0_1 >+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_2_3 >+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_4_5 >+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_6_7 >+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_8_9 >+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_10_11 >+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_12_13 >+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_14_15 >+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_16_17 >+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_18_19 >+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_20_21 >+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_22_23 >+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_24_25 >+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_26_27 >+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_28_29 >+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_30_31 >+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMA_REGION_32_33 >+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_START_CNTL_B >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM2_CM_BLNDGAM_RAMB_START_CNTL_G >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM2_CM_BLNDGAM_RAMB_START_CNTL_R >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B >+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G >+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R >+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM2_CM_BLNDGAM_RAMB_REGION_0_1 >+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_2_3 >+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_4_5 >+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_6_7 >+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_8_9 >+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_10_11 >+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_12_13 >+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_14_15 >+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_16_17 >+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_18_19 >+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_20_21 >+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_22_23 >+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_24_25 >+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_26_27 >+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_28_29 >+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_30_31 >+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_BLNDGAM_RAMB_REGION_32_33 >+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_HDR_MULT_COEF >+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 >+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL >+//CM2_CM_MEM_PWR_CTRL >+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 >+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 >+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 >+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 >+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L >+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L >+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L >+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L >+//CM2_CM_MEM_PWR_STATUS >+#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 >+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 >+#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L >+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL >+//CM2_CM_DEALPHA >+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 >+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L >+//CM2_CM_COEF_FORMAT >+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 >+#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4 >+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 >+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L >+#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L >+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L >+//CM2_CM_SHAPER_CONTROL >+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 >+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L >+//CM2_CM_SHAPER_OFFSET_R >+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 >+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL >+//CM2_CM_SHAPER_OFFSET_G >+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 >+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL >+//CM2_CM_SHAPER_OFFSET_B >+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 >+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL >+//CM2_CM_SHAPER_SCALE_R >+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 >+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL >+//CM2_CM_SHAPER_SCALE_G_B >+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 >+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 >+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL >+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L >+//CM2_CM_SHAPER_LUT_INDEX >+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 >+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL >+//CM2_CM_SHAPER_LUT_DATA >+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 >+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL >+//CM2_CM_SHAPER_LUT_WRITE_EN_MASK >+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8 >+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L >+//CM2_CM_SHAPER_RAMA_START_CNTL_B >+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM2_CM_SHAPER_RAMA_START_CNTL_G >+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM2_CM_SHAPER_RAMA_START_CNTL_R >+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM2_CM_SHAPER_RAMA_END_CNTL_B >+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L >+//CM2_CM_SHAPER_RAMA_END_CNTL_G >+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L >+//CM2_CM_SHAPER_RAMA_END_CNTL_R >+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L >+//CM2_CM_SHAPER_RAMA_REGION_0_1 >+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_2_3 >+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_4_5 >+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_6_7 >+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_8_9 >+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_10_11 >+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_12_13 >+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_14_15 >+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_16_17 >+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_18_19 >+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_20_21 >+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_22_23 >+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_24_25 >+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_26_27 >+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_28_29 >+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_30_31 >+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMA_REGION_32_33 >+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_START_CNTL_B >+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM2_CM_SHAPER_RAMB_START_CNTL_G >+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM2_CM_SHAPER_RAMB_START_CNTL_R >+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM2_CM_SHAPER_RAMB_END_CNTL_B >+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L >+//CM2_CM_SHAPER_RAMB_END_CNTL_G >+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L >+//CM2_CM_SHAPER_RAMB_END_CNTL_R >+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L >+//CM2_CM_SHAPER_RAMB_REGION_0_1 >+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_2_3 >+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_4_5 >+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_6_7 >+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_8_9 >+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_10_11 >+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_12_13 >+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_14_15 >+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_16_17 >+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_18_19 >+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_20_21 >+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_22_23 >+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_24_25 >+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_26_27 >+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_28_29 >+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_30_31 >+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_SHAPER_RAMB_REGION_32_33 >+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM2_CM_MEM_PWR_CTRL2 >+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 >+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa >+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc >+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe >+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L >+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L >+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L >+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L >+//CM2_CM_MEM_PWR_STATUS2 >+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 >+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 >+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L >+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L >+//CM2_CM_3DLUT_MODE >+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 >+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 >+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L >+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L >+//CM2_CM_3DLUT_INDEX >+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 >+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL >+//CM2_CM_3DLUT_DATA >+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 >+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 >+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL >+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L >+//CM2_CM_3DLUT_DATA_30BIT >+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 >+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL >+//CM2_CM_3DLUT_READ_WRITE_CONTROL >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L >+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L >+//CM2_CM_3DLUT_OUT_NORM_FACTOR >+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 >+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL >+//CM2_CM_3DLUT_OUT_OFFSET_R >+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 >+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 >+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL >+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L >+//CM2_CM_3DLUT_OUT_OFFSET_G >+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 >+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 >+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL >+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L >+//CM2_CM_3DLUT_OUT_OFFSET_B >+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 >+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 >+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL >+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L >+//CM2_CM_TEST_DEBUG_INDEX >+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//CM2_CM_TEST_DEBUG_DATA >+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 >+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON13_PERFCOUNTER_CNTL >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON13_PERFCOUNTER_CNTL2 >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON13_PERFCOUNTER_STATE >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON13_PERFMON_CNTL >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON13_PERFMON_CNTL2 >+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON13_PERFMON_CVALUE_LOW >+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON13_PERFMON_HI >+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON13_PERFMON_LOW >+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec >+//DPP_TOP3_DPP_CONTROL >+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 >+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 >+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 >+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c >+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L >+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L >+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L >+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L >+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L >+//DPP_TOP3_DPP_SOFT_RESET >+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 >+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 >+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 >+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc >+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L >+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L >+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L >+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L >+//DPP_TOP3_DPP_CRC_VAL_R_G >+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 >+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 >+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL >+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L >+//DPP_TOP3_DPP_CRC_VAL_B_A >+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 >+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 >+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL >+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L >+//DPP_TOP3_DPP_CRC_CTRL >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L >+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L >+//DPP_TOP3_HOST_READ_CONTROL >+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 >+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec >+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT >+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 >+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL >+//CNVC_CFG3_FORMAT_CONTROL >+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 >+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 >+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 >+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc >+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd >+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 >+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 >+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 >+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L >+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L >+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L >+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L >+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L >+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L >+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L >+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L >+//CNVC_CFG3_FCNV_FP_BIAS_R >+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 >+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL >+//CNVC_CFG3_FCNV_FP_BIAS_G >+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 >+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL >+//CNVC_CFG3_FCNV_FP_BIAS_B >+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 >+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL >+//CNVC_CFG3_FCNV_FP_SCALE_R >+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 >+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL >+//CNVC_CFG3_FCNV_FP_SCALE_G >+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 >+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL >+//CNVC_CFG3_FCNV_FP_SCALE_B >+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 >+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL >+//CNVC_CFG3_COLOR_KEYER_CONTROL >+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 >+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 >+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L >+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L >+//CNVC_CFG3_COLOR_KEYER_ALPHA >+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 >+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 >+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG3_COLOR_KEYER_RED >+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 >+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 >+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG3_COLOR_KEYER_GREEN >+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 >+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 >+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG3_COLOR_KEYER_BLUE >+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 >+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 >+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL >+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L >+//CNVC_CFG3_ALPHA_2BIT_LUT >+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 >+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 >+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 >+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 >+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL >+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L >+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L >+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec >+//CNVC_CUR3_CURSOR0_CONTROL >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L >+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L >+//CNVC_CUR3_CURSOR0_COLOR0 >+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 >+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL >+//CNVC_CUR3_CURSOR0_COLOR1 >+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 >+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL >+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS >+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 >+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 >+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL >+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec >+//DSCL3_SCL_COEF_RAM_TAP_SELECT >+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 >+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 >+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 >+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L >+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L >+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L >+//DSCL3_SCL_COEF_RAM_TAP_DATA >+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 >+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf >+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 >+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f >+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL >+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L >+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L >+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L >+//DSCL3_SCL_MODE >+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 >+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 >+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc >+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 >+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 >+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 >+#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L >+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L >+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L >+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L >+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L >+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L >+//DSCL3_SCL_TAP_CONTROL >+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 >+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 >+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 >+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc >+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L >+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L >+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L >+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L >+//DSCL3_DSCL_CONTROL >+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 >+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L >+//DSCL3_DSCL_2TAP_CONTROL >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L >+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L >+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL >+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 >+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 >+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL >+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L >+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO >+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 >+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL >+//DSCL3_SCL_HORZ_FILTER_INIT >+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 >+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 >+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL >+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L >+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C >+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 >+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL >+//DSCL3_SCL_HORZ_FILTER_INIT_C >+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 >+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 >+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL >+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L >+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO >+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 >+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL >+//DSCL3_SCL_VERT_FILTER_INIT >+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 >+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 >+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL >+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L >+//DSCL3_SCL_VERT_FILTER_INIT_BOT >+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 >+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 >+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL >+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L >+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C >+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 >+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL >+//DSCL3_SCL_VERT_FILTER_INIT_C >+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 >+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 >+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL >+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L >+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C >+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 >+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 >+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL >+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L >+//DSCL3_SCL_BLACK_OFFSET >+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 >+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 >+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL >+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L >+//DSCL3_DSCL_UPDATE >+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 >+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L >+//DSCL3_DSCL_AUTOCAL >+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 >+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 >+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc >+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L >+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L >+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L >+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT >+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 >+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 >+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL >+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L >+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM >+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 >+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 >+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL >+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L >+//DSCL3_OTG_H_BLANK >+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 >+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 >+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL >+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L >+//DSCL3_OTG_V_BLANK >+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 >+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 >+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL >+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L >+//DSCL3_RECOUT_START >+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 >+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 >+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL >+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L >+//DSCL3_RECOUT_SIZE >+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 >+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 >+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL >+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L >+//DSCL3_MPC_SIZE >+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 >+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 >+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL >+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L >+//DSCL3_LB_DATA_FORMAT >+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 >+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 >+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L >+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L >+//DSCL3_LB_MEMORY_CTRL >+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 >+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 >+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 >+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 >+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L >+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L >+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L >+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L >+//DSCL3_LB_V_COUNTER >+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 >+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 >+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL >+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L >+//DSCL3_DSCL_MEM_PWR_CTRL >+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c >+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L >+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L >+//DSCL3_DSCL_MEM_PWR_STATUS >+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc >+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L >+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L >+//DSCL3_OBUF_CONTROL >+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 >+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 >+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc >+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c >+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L >+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L >+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L >+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L >+//DSCL3_OBUF_MEM_PWR_CTRL >+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 >+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 >+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 >+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L >+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L >+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L >+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec >+//CM3_CM_CONTROL >+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT 0x0 >+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 >+#define CM3_CM_CONTROL__CM_BYPASS_MASK 0x00000001L >+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L >+//CM3_CM_ICSC_CONTROL >+#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 >+#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L >+//CM3_CM_ICSC_C11_C12 >+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 >+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 >+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L >+//CM3_CM_ICSC_C13_C14 >+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 >+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 >+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L >+//CM3_CM_ICSC_C21_C22 >+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 >+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 >+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L >+//CM3_CM_ICSC_C23_C24 >+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 >+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 >+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L >+//CM3_CM_ICSC_C31_C32 >+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 >+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 >+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L >+//CM3_CM_ICSC_C33_C34 >+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 >+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 >+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L >+//CM3_CM_ICSC_B_C11_C12 >+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0 >+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10 >+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L >+//CM3_CM_ICSC_B_C13_C14 >+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0 >+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10 >+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L >+//CM3_CM_ICSC_B_C21_C22 >+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0 >+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10 >+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L >+//CM3_CM_ICSC_B_C23_C24 >+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0 >+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10 >+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L >+//CM3_CM_ICSC_B_C31_C32 >+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0 >+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10 >+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L >+//CM3_CM_ICSC_B_C33_C34 >+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0 >+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10 >+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL >+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_CONTROL >+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L >+//CM3_CM_GAMUT_REMAP_C11_C12 >+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_C13_C14 >+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_C21_C22 >+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_C23_C24 >+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_C31_C32 >+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_C33_C34 >+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_B_C11_C12 >+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_B_C13_C14 >+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_B_C21_C22 >+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_B_C23_C24 >+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_B_C31_C32 >+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L >+//CM3_CM_GAMUT_REMAP_B_C33_C34 >+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 >+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 >+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL >+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L >+//CM3_CM_BIAS_CR_R >+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 >+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL >+//CM3_CM_BIAS_Y_G_CB_B >+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 >+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 >+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL >+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L >+//CM3_CM_DGAM_CONTROL >+#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 >+#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L >+//CM3_CM_DGAM_LUT_INDEX >+#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 >+#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL >+//CM3_CM_DGAM_LUT_DATA >+#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 >+#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL >+//CM3_CM_DGAM_LUT_WRITE_EN_MASK >+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8 >+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc >+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L >+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L >+//CM3_CM_DGAM_RAMA_START_CNTL_B >+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM3_CM_DGAM_RAMA_START_CNTL_G >+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM3_CM_DGAM_RAMA_START_CNTL_R >+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_B >+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_G >+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_R >+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM3_CM_DGAM_RAMA_END_CNTL1_B >+#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM3_CM_DGAM_RAMA_END_CNTL2_B >+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM3_CM_DGAM_RAMA_END_CNTL1_G >+#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM3_CM_DGAM_RAMA_END_CNTL2_G >+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM3_CM_DGAM_RAMA_END_CNTL1_R >+#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM3_CM_DGAM_RAMA_END_CNTL2_R >+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM3_CM_DGAM_RAMA_REGION_0_1 >+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMA_REGION_2_3 >+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMA_REGION_4_5 >+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMA_REGION_6_7 >+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMA_REGION_8_9 >+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMA_REGION_10_11 >+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMA_REGION_12_13 >+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMA_REGION_14_15 >+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMB_START_CNTL_B >+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM3_CM_DGAM_RAMB_START_CNTL_G >+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM3_CM_DGAM_RAMB_START_CNTL_R >+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_B >+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_G >+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_R >+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM3_CM_DGAM_RAMB_END_CNTL1_B >+#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM3_CM_DGAM_RAMB_END_CNTL2_B >+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM3_CM_DGAM_RAMB_END_CNTL1_G >+#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM3_CM_DGAM_RAMB_END_CNTL2_G >+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM3_CM_DGAM_RAMB_END_CNTL1_R >+#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM3_CM_DGAM_RAMB_END_CNTL2_R >+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM3_CM_DGAM_RAMB_REGION_0_1 >+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMB_REGION_2_3 >+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMB_REGION_4_5 >+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMB_REGION_6_7 >+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMB_REGION_8_9 >+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMB_REGION_10_11 >+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMB_REGION_12_13 >+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_DGAM_RAMB_REGION_14_15 >+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_CONTROL >+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L >+//CM3_CM_BLNDGAM_LUT_INDEX >+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL >+//CM3_CM_BLNDGAM_LUT_DATA >+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL >+//CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK >+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8 >+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L >+//CM3_CM_BLNDGAM_RAMA_START_CNTL_B >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM3_CM_BLNDGAM_RAMA_START_CNTL_G >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM3_CM_BLNDGAM_RAMA_START_CNTL_R >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B >+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G >+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R >+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM3_CM_BLNDGAM_RAMA_REGION_0_1 >+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_2_3 >+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_4_5 >+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_6_7 >+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_8_9 >+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_10_11 >+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_12_13 >+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_14_15 >+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_16_17 >+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_18_19 >+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_20_21 >+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_22_23 >+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_24_25 >+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_26_27 >+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_28_29 >+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_30_31 >+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMA_REGION_32_33 >+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_START_CNTL_B >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM3_CM_BLNDGAM_RAMB_START_CNTL_G >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM3_CM_BLNDGAM_RAMB_START_CNTL_R >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B >+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G >+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R >+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//CM3_CM_BLNDGAM_RAMB_REGION_0_1 >+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_2_3 >+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_4_5 >+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_6_7 >+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_8_9 >+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_10_11 >+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_12_13 >+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_14_15 >+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_16_17 >+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_18_19 >+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_20_21 >+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_22_23 >+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_24_25 >+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_26_27 >+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_28_29 >+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_30_31 >+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_BLNDGAM_RAMB_REGION_32_33 >+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_HDR_MULT_COEF >+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 >+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL >+//CM3_CM_MEM_PWR_CTRL >+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 >+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 >+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 >+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 >+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L >+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L >+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L >+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L >+//CM3_CM_MEM_PWR_STATUS >+#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 >+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 >+#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L >+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL >+//CM3_CM_DEALPHA >+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 >+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L >+//CM3_CM_COEF_FORMAT >+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 >+#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4 >+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 >+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L >+#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L >+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L >+//CM3_CM_SHAPER_CONTROL >+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 >+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L >+//CM3_CM_SHAPER_OFFSET_R >+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 >+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL >+//CM3_CM_SHAPER_OFFSET_G >+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 >+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL >+//CM3_CM_SHAPER_OFFSET_B >+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 >+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL >+//CM3_CM_SHAPER_SCALE_R >+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 >+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL >+//CM3_CM_SHAPER_SCALE_G_B >+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 >+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 >+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL >+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L >+//CM3_CM_SHAPER_LUT_INDEX >+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 >+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL >+//CM3_CM_SHAPER_LUT_DATA >+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 >+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL >+//CM3_CM_SHAPER_LUT_WRITE_EN_MASK >+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 >+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8 >+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L >+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L >+//CM3_CM_SHAPER_RAMA_START_CNTL_B >+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM3_CM_SHAPER_RAMA_START_CNTL_G >+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM3_CM_SHAPER_RAMA_START_CNTL_R >+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM3_CM_SHAPER_RAMA_END_CNTL_B >+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L >+//CM3_CM_SHAPER_RAMA_END_CNTL_G >+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L >+//CM3_CM_SHAPER_RAMA_END_CNTL_R >+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L >+//CM3_CM_SHAPER_RAMA_REGION_0_1 >+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_2_3 >+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_4_5 >+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_6_7 >+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_8_9 >+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_10_11 >+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_12_13 >+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_14_15 >+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_16_17 >+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_18_19 >+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_20_21 >+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_22_23 >+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_24_25 >+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_26_27 >+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_28_29 >+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_30_31 >+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMA_REGION_32_33 >+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_START_CNTL_B >+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//CM3_CM_SHAPER_RAMB_START_CNTL_G >+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//CM3_CM_SHAPER_RAMB_START_CNTL_R >+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//CM3_CM_SHAPER_RAMB_END_CNTL_B >+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L >+//CM3_CM_SHAPER_RAMB_END_CNTL_G >+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L >+//CM3_CM_SHAPER_RAMB_END_CNTL_R >+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L >+//CM3_CM_SHAPER_RAMB_REGION_0_1 >+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_2_3 >+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_4_5 >+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_6_7 >+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_8_9 >+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_10_11 >+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_12_13 >+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_14_15 >+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_16_17 >+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_18_19 >+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_20_21 >+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_22_23 >+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_24_25 >+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_26_27 >+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_28_29 >+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_30_31 >+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_SHAPER_RAMB_REGION_32_33 >+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//CM3_CM_MEM_PWR_CTRL2 >+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 >+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa >+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc >+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe >+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L >+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L >+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L >+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L >+//CM3_CM_MEM_PWR_STATUS2 >+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 >+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 >+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L >+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L >+//CM3_CM_3DLUT_MODE >+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 >+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 >+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L >+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L >+//CM3_CM_3DLUT_INDEX >+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 >+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL >+//CM3_CM_3DLUT_DATA >+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 >+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 >+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL >+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L >+//CM3_CM_3DLUT_DATA_30BIT >+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 >+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL >+//CM3_CM_3DLUT_READ_WRITE_CONTROL >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L >+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L >+//CM3_CM_3DLUT_OUT_NORM_FACTOR >+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 >+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL >+//CM3_CM_3DLUT_OUT_OFFSET_R >+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 >+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 >+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL >+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L >+//CM3_CM_3DLUT_OUT_OFFSET_G >+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 >+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 >+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL >+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L >+//CM3_CM_3DLUT_OUT_OFFSET_B >+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 >+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 >+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL >+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L >+//CM3_CM_TEST_DEBUG_INDEX >+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//CM3_CM_TEST_DEBUG_DATA >+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 >+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON14_PERFCOUNTER_CNTL >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON14_PERFCOUNTER_CNTL2 >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON14_PERFCOUNTER_STATE >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON14_PERFMON_CNTL >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON14_PERFMON_CNTL2 >+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON14_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON14_PERFMON_CVALUE_LOW >+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON14_PERFMON_HI >+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON14_PERFMON_LOW >+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_mpc_mpcc0_dispdec >+//MPCC0_MPCC_TOP_SEL >+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 >+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL >+//MPCC0_MPCC_BOT_SEL >+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 >+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL >+//MPCC0_MPCC_OPP_ID >+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 >+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL >+//MPCC0_MPCC_CONTROL >+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 >+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 >+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 >+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 >+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 >+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb >+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 >+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 >+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L >+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L >+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L >+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L >+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L >+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L >+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L >+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L >+//MPCC0_MPCC_SM_CONTROL >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L >+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L >+//MPCC0_MPCC_UPDATE_LOCK_SEL >+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 >+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 >+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL >+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L >+//MPCC0_MPCC_TOP_GAIN >+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 >+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL >+//MPCC0_MPCC_BOT_GAIN_INSIDE >+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 >+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL >+//MPCC0_MPCC_BOT_GAIN_OUTSIDE >+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 >+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL >+//MPCC0_MPCC_BG_R_CR >+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 >+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL >+//MPCC0_MPCC_BG_G_Y >+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 >+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL >+//MPCC0_MPCC_BG_B_CB >+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 >+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL >+//MPCC0_MPCC_MEM_PWR_CTRL >+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 >+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 >+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 >+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L >+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L >+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L >+//MPCC0_MPCC_STALL_STATUS >+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 >+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 >+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 >+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc >+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L >+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L >+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L >+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L >+//MPCC0_MPCC_STATUS >+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 >+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 >+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 >+#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d >+#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e >+#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f >+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L >+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L >+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L >+#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L >+#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L >+#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc1_dispdec >+//MPCC1_MPCC_TOP_SEL >+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 >+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL >+//MPCC1_MPCC_BOT_SEL >+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 >+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL >+//MPCC1_MPCC_OPP_ID >+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 >+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL >+//MPCC1_MPCC_CONTROL >+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 >+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 >+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 >+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 >+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 >+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb >+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 >+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 >+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L >+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L >+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L >+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L >+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L >+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L >+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L >+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L >+//MPCC1_MPCC_SM_CONTROL >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L >+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L >+//MPCC1_MPCC_UPDATE_LOCK_SEL >+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 >+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 >+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL >+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L >+//MPCC1_MPCC_TOP_GAIN >+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 >+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL >+//MPCC1_MPCC_BOT_GAIN_INSIDE >+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 >+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL >+//MPCC1_MPCC_BOT_GAIN_OUTSIDE >+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 >+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL >+//MPCC1_MPCC_BG_R_CR >+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 >+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL >+//MPCC1_MPCC_BG_G_Y >+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 >+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL >+//MPCC1_MPCC_BG_B_CB >+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 >+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL >+//MPCC1_MPCC_MEM_PWR_CTRL >+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 >+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 >+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 >+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L >+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L >+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L >+//MPCC1_MPCC_STALL_STATUS >+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 >+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 >+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 >+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc >+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L >+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L >+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L >+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L >+//MPCC1_MPCC_STATUS >+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 >+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 >+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 >+#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d >+#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e >+#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f >+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L >+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L >+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L >+#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L >+#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L >+#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc2_dispdec >+//MPCC2_MPCC_TOP_SEL >+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 >+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL >+//MPCC2_MPCC_BOT_SEL >+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 >+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL >+//MPCC2_MPCC_OPP_ID >+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 >+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL >+//MPCC2_MPCC_CONTROL >+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 >+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 >+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 >+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 >+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 >+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb >+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 >+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 >+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L >+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L >+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L >+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L >+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L >+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L >+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L >+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L >+//MPCC2_MPCC_SM_CONTROL >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L >+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L >+//MPCC2_MPCC_UPDATE_LOCK_SEL >+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 >+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 >+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL >+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L >+//MPCC2_MPCC_TOP_GAIN >+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 >+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL >+//MPCC2_MPCC_BOT_GAIN_INSIDE >+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 >+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL >+//MPCC2_MPCC_BOT_GAIN_OUTSIDE >+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 >+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL >+//MPCC2_MPCC_BG_R_CR >+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 >+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL >+//MPCC2_MPCC_BG_G_Y >+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 >+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL >+//MPCC2_MPCC_BG_B_CB >+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 >+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL >+//MPCC2_MPCC_MEM_PWR_CTRL >+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 >+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 >+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 >+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L >+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L >+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L >+//MPCC2_MPCC_STALL_STATUS >+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 >+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 >+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 >+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc >+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L >+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L >+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L >+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L >+//MPCC2_MPCC_STATUS >+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 >+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 >+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 >+#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d >+#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e >+#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f >+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L >+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L >+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L >+#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L >+#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L >+#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc3_dispdec >+//MPCC3_MPCC_TOP_SEL >+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 >+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL >+//MPCC3_MPCC_BOT_SEL >+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 >+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL >+//MPCC3_MPCC_OPP_ID >+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 >+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL >+//MPCC3_MPCC_CONTROL >+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 >+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 >+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 >+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 >+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 >+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb >+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 >+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 >+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L >+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L >+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L >+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L >+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L >+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L >+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L >+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L >+//MPCC3_MPCC_SM_CONTROL >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L >+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L >+//MPCC3_MPCC_UPDATE_LOCK_SEL >+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 >+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 >+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL >+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L >+//MPCC3_MPCC_TOP_GAIN >+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 >+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL >+//MPCC3_MPCC_BOT_GAIN_INSIDE >+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 >+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL >+//MPCC3_MPCC_BOT_GAIN_OUTSIDE >+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 >+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL >+//MPCC3_MPCC_BG_R_CR >+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 >+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL >+//MPCC3_MPCC_BG_G_Y >+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 >+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL >+//MPCC3_MPCC_BG_B_CB >+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 >+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL >+//MPCC3_MPCC_MEM_PWR_CTRL >+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 >+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 >+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 >+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L >+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L >+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L >+//MPCC3_MPCC_STALL_STATUS >+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 >+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 >+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 >+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc >+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L >+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L >+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L >+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L >+//MPCC3_MPCC_STATUS >+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 >+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 >+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 >+#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d >+#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e >+#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f >+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L >+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L >+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L >+#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L >+#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L >+#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc4_dispdec >+//MPCC4_MPCC_TOP_SEL >+#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 >+#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL >+//MPCC4_MPCC_BOT_SEL >+#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 >+#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL >+//MPCC4_MPCC_OPP_ID >+#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 >+#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL >+//MPCC4_MPCC_CONTROL >+#define MPCC4_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 >+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 >+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 >+#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 >+#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 >+#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb >+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 >+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 >+#define MPCC4_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L >+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L >+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L >+#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L >+#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L >+#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L >+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L >+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L >+//MPCC4_MPCC_SM_CONTROL >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L >+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L >+//MPCC4_MPCC_UPDATE_LOCK_SEL >+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 >+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 >+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL >+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L >+//MPCC4_MPCC_TOP_GAIN >+#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 >+#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL >+//MPCC4_MPCC_BOT_GAIN_INSIDE >+#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 >+#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL >+//MPCC4_MPCC_BOT_GAIN_OUTSIDE >+#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 >+#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL >+//MPCC4_MPCC_BG_R_CR >+#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 >+#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL >+//MPCC4_MPCC_BG_G_Y >+#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 >+#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL >+//MPCC4_MPCC_BG_B_CB >+#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 >+#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL >+//MPCC4_MPCC_MEM_PWR_CTRL >+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 >+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 >+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 >+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L >+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L >+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L >+//MPCC4_MPCC_STALL_STATUS >+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 >+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 >+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 >+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc >+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L >+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L >+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L >+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L >+//MPCC4_MPCC_STATUS >+#define MPCC4_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 >+#define MPCC4_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 >+#define MPCC4_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 >+#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d >+#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e >+#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f >+#define MPCC4_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L >+#define MPCC4_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L >+#define MPCC4_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L >+#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L >+#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L >+#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc5_dispdec >+//MPCC5_MPCC_TOP_SEL >+#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 >+#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL >+//MPCC5_MPCC_BOT_SEL >+#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 >+#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL >+//MPCC5_MPCC_OPP_ID >+#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 >+#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL >+//MPCC5_MPCC_CONTROL >+#define MPCC5_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 >+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 >+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 >+#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 >+#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 >+#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb >+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 >+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 >+#define MPCC5_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L >+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L >+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L >+#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L >+#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L >+#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L >+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L >+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L >+//MPCC5_MPCC_SM_CONTROL >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L >+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L >+//MPCC5_MPCC_UPDATE_LOCK_SEL >+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 >+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 >+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL >+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L >+//MPCC5_MPCC_TOP_GAIN >+#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 >+#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL >+//MPCC5_MPCC_BOT_GAIN_INSIDE >+#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 >+#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL >+//MPCC5_MPCC_BOT_GAIN_OUTSIDE >+#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 >+#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL >+//MPCC5_MPCC_BG_R_CR >+#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 >+#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL >+//MPCC5_MPCC_BG_G_Y >+#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 >+#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL >+//MPCC5_MPCC_BG_B_CB >+#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 >+#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL >+//MPCC5_MPCC_MEM_PWR_CTRL >+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 >+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 >+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 >+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L >+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L >+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L >+//MPCC5_MPCC_STALL_STATUS >+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 >+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 >+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 >+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc >+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L >+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L >+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L >+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L >+//MPCC5_MPCC_STATUS >+#define MPCC5_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 >+#define MPCC5_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 >+#define MPCC5_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 >+#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d >+#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e >+#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f >+#define MPCC5_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L >+#define MPCC5_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L >+#define MPCC5_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L >+#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L >+#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L >+#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc6_dispdec >+//MPCC6_MPCC_TOP_SEL >+#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 >+#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL >+//MPCC6_MPCC_BOT_SEL >+#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 >+#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL >+//MPCC6_MPCC_OPP_ID >+#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 >+#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL >+//MPCC6_MPCC_CONTROL >+#define MPCC6_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 >+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 >+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 >+#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 >+#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 >+#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb >+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 >+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 >+#define MPCC6_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L >+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L >+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L >+#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L >+#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L >+#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L >+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L >+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L >+//MPCC6_MPCC_SM_CONTROL >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L >+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L >+//MPCC6_MPCC_UPDATE_LOCK_SEL >+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 >+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 >+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL >+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L >+//MPCC6_MPCC_TOP_GAIN >+#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 >+#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL >+//MPCC6_MPCC_BOT_GAIN_INSIDE >+#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 >+#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL >+//MPCC6_MPCC_BOT_GAIN_OUTSIDE >+#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 >+#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL >+//MPCC6_MPCC_BG_R_CR >+#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 >+#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL >+//MPCC6_MPCC_BG_G_Y >+#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 >+#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL >+//MPCC6_MPCC_BG_B_CB >+#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 >+#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL >+//MPCC6_MPCC_MEM_PWR_CTRL >+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 >+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 >+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 >+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L >+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L >+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L >+//MPCC6_MPCC_STALL_STATUS >+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 >+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 >+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 >+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc >+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L >+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L >+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L >+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L >+//MPCC6_MPCC_STATUS >+#define MPCC6_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 >+#define MPCC6_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 >+#define MPCC6_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 >+#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d >+#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e >+#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f >+#define MPCC6_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L >+#define MPCC6_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L >+#define MPCC6_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L >+#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L >+#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L >+#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc7_dispdec >+//MPCC7_MPCC_TOP_SEL >+#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 >+#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL >+//MPCC7_MPCC_BOT_SEL >+#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 >+#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL >+//MPCC7_MPCC_OPP_ID >+#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 >+#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL >+//MPCC7_MPCC_CONTROL >+#define MPCC7_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 >+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 >+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 >+#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 >+#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 >+#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb >+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 >+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 >+#define MPCC7_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L >+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L >+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L >+#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L >+#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L >+#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L >+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L >+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L >+//MPCC7_MPCC_SM_CONTROL >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L >+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L >+//MPCC7_MPCC_UPDATE_LOCK_SEL >+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 >+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 >+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL >+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L >+//MPCC7_MPCC_TOP_GAIN >+#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 >+#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL >+//MPCC7_MPCC_BOT_GAIN_INSIDE >+#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 >+#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL >+//MPCC7_MPCC_BOT_GAIN_OUTSIDE >+#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 >+#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL >+//MPCC7_MPCC_BG_R_CR >+#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 >+#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL >+//MPCC7_MPCC_BG_G_Y >+#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 >+#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL >+//MPCC7_MPCC_BG_B_CB >+#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 >+#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL >+//MPCC7_MPCC_MEM_PWR_CTRL >+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 >+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 >+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 >+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L >+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L >+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L >+//MPCC7_MPCC_STALL_STATUS >+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 >+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 >+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 >+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc >+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L >+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L >+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L >+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L >+//MPCC7_MPCC_STATUS >+#define MPCC7_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 >+#define MPCC7_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 >+#define MPCC7_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 >+#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d >+#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e >+#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f >+#define MPCC7_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L >+#define MPCC7_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L >+#define MPCC7_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L >+#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L >+#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L >+#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec >+//MPC_CLOCK_CONTROL >+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1 >+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4 >+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L >+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L >+//MPC_SOFT_RESET >+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 >+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 >+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 >+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 >+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa >+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb >+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc >+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd >+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 >+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 >+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 >+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 >+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f >+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L >+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L >+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L >+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L >+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L >+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L >+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L >+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L >+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L >+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L >+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L >+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L >+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L >+//MPC_CRC_CTRL >+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 >+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 >+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 >+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa >+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc >+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 >+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c >+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e >+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f >+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L >+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L >+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L >+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L >+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L >+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L >+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L >+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L >+//MPC_CRC_SEL_CONTROL >+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 >+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 >+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 >+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL >+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L >+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L >+//MPC_CRC_RESULT_AR >+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0 >+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10 >+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL >+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L >+//MPC_CRC_RESULT_GB >+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0 >+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10 >+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL >+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L >+//MPC_CRC_RESULT_C >+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0 >+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL >+//MPC_PERFMON_EVENT_CTRL >+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0 >+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L >+//MPC_BYPASS_BG_AR >+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 >+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 >+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL >+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L >+//MPC_BYPASS_BG_GB >+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 >+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 >+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL >+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L >+//MPC_STALL_GRACE_WINDOW >+#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD__SHIFT 0x0 >+#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD_MASK 0x000000FFL >+//MPC_HOST_READ_CONTROL >+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 >+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL >+//MPC_PENDING_TAKEN_STATUS_REG1 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN__SHIFT 0x1 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x2 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN__SHIFT 0x3 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x4 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN__SHIFT 0x5 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x6 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN__SHIFT 0x7 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x8 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN__SHIFT 0x9 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0xa >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN__SHIFT 0xb >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT 0xc >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN__SHIFT 0xd >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT 0xe >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN__SHIFT 0xf >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT 0x10 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN__SHIFT 0x11 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT 0x12 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN__SHIFT 0x13 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT 0x14 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN__SHIFT 0x15 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT 0x16 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN__SHIFT 0x17 >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN_MASK 0x00000002L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000004L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN_MASK 0x00000008L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000010L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN_MASK 0x00000020L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000040L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN_MASK 0x00000080L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000100L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN_MASK 0x00000200L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000400L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN_MASK 0x00000800L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING_MASK 0x00001000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN_MASK 0x00002000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING_MASK 0x00004000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN_MASK 0x00008000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING_MASK 0x00010000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN_MASK 0x00020000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING_MASK 0x00040000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN_MASK 0x00080000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING_MASK 0x00100000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN_MASK 0x00200000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING_MASK 0x00400000L >+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN_MASK 0x00800000L >+//MPC_PENDING_TAKEN_STATUS_REG3 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN__SHIFT 0x1 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x2 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN__SHIFT 0x3 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT 0x4 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN__SHIFT 0x5 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT 0x6 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN__SHIFT 0x7 >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0xc >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN__SHIFT 0xd >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0xe >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN__SHIFT 0xf >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING__SHIFT 0x10 >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN__SHIFT 0x11 >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING__SHIFT 0x12 >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN__SHIFT 0x13 >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN_MASK 0x00000002L >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000004L >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN_MASK 0x00000008L >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK 0x00000010L >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN_MASK 0x00000020L >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK 0x00000040L >+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN_MASK 0x00000080L >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00001000L >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN_MASK 0x00002000L >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00004000L >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN_MASK 0x00008000L >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING_MASK 0x00010000L >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN_MASK 0x00020000L >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING_MASK 0x00040000L >+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN_MASK 0x00080000L >+//MPC_UPDATE_ACK_REG5 >+#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK__SHIFT 0x0 >+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK__SHIFT 0x1 >+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK__SHIFT 0x2 >+#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK__SHIFT 0x3 >+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK__SHIFT 0x4 >+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK__SHIFT 0x5 >+#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK__SHIFT 0x6 >+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK__SHIFT 0x7 >+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK__SHIFT 0x8 >+#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK__SHIFT 0x9 >+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK__SHIFT 0xa >+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK__SHIFT 0xb >+#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK__SHIFT 0xf >+#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK__SHIFT 0x10 >+#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK__SHIFT 0x11 >+#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK__SHIFT 0x12 >+#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK__SHIFT 0x14 >+#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK__SHIFT 0x15 >+#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK__SHIFT 0x16 >+#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK__SHIFT 0x17 >+#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK_MASK 0x00000001L >+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK_MASK 0x00000002L >+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK_MASK 0x00000004L >+#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK_MASK 0x00000008L >+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK_MASK 0x00000010L >+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK_MASK 0x00000020L >+#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK_MASK 0x00000040L >+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK_MASK 0x00000080L >+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK_MASK 0x00000100L >+#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK_MASK 0x00000200L >+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK_MASK 0x00000400L >+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK_MASK 0x00000800L >+#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK_MASK 0x00008000L >+#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK_MASK 0x00010000L >+#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK_MASK 0x00020000L >+#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK_MASK 0x00040000L >+#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK_MASK 0x00100000L >+#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK_MASK 0x00200000L >+#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK_MASK 0x00400000L >+#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK_MASK 0x00800000L >+//ADR_CFG_CUR_VUPDATE_LOCK_SET0 >+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_CFG_VUPDATE_LOCK_SET0 >+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_VUPDATE_LOCK_SET0 >+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//CFG_VUPDATE_LOCK_SET0 >+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L >+//CUR_VUPDATE_LOCK_SET0 >+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_CFG_CUR_VUPDATE_LOCK_SET1 >+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_CFG_VUPDATE_LOCK_SET1 >+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_VUPDATE_LOCK_SET1 >+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//CFG_VUPDATE_LOCK_SET1 >+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L >+//CUR_VUPDATE_LOCK_SET1 >+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_CFG_CUR_VUPDATE_LOCK_SET2 >+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_CFG_VUPDATE_LOCK_SET2 >+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_VUPDATE_LOCK_SET2 >+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//CFG_VUPDATE_LOCK_SET2 >+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L >+//CUR_VUPDATE_LOCK_SET2 >+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_CFG_CUR_VUPDATE_LOCK_SET3 >+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_CFG_VUPDATE_LOCK_SET3 >+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L >+//ADR_VUPDATE_LOCK_SET3 >+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//CFG_VUPDATE_LOCK_SET3 >+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L >+//CUR_VUPDATE_LOCK_SET3 >+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 >+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L >+//MPC_OUT0_MUX >+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 >+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL >+//MPC_OUT0_DENORM_CONTROL >+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 >+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc >+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 >+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL >+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L >+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L >+//MPC_OUT0_DENORM_CLAMP_G_Y >+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 >+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc >+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL >+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L >+//MPC_OUT0_DENORM_CLAMP_B_CB >+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 >+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc >+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL >+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L >+//MPC_OUT1_MUX >+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 >+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL >+//MPC_OUT1_DENORM_CONTROL >+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 >+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc >+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 >+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL >+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L >+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L >+//MPC_OUT1_DENORM_CLAMP_G_Y >+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 >+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc >+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL >+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L >+//MPC_OUT1_DENORM_CLAMP_B_CB >+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 >+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc >+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL >+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L >+//MPC_OUT2_MUX >+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 >+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL >+//MPC_OUT2_DENORM_CONTROL >+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 >+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc >+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 >+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL >+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L >+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L >+//MPC_OUT2_DENORM_CLAMP_G_Y >+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 >+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc >+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL >+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L >+//MPC_OUT2_DENORM_CLAMP_B_CB >+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 >+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc >+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL >+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L >+//MPC_OUT3_MUX >+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 >+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL >+//MPC_OUT3_DENORM_CONTROL >+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 >+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc >+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 >+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL >+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L >+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L >+//MPC_OUT3_DENORM_CLAMP_G_Y >+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 >+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc >+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL >+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L >+//MPC_OUT3_DENORM_CLAMP_B_CB >+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 >+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc >+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL >+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec >+//MPCC_OGAM0_MPCC_OGAM_MODE >+#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L >+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX >+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL >+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA >+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL >+//MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL >+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 >+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 >+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L >+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec >+//MPCC_OGAM1_MPCC_OGAM_MODE >+#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L >+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX >+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL >+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA >+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL >+//MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL >+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 >+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 >+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L >+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec >+//MPCC_OGAM2_MPCC_OGAM_MODE >+#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L >+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX >+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL >+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA >+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL >+//MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL >+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 >+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 >+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L >+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec >+//MPCC_OGAM3_MPCC_OGAM_MODE >+#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L >+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX >+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL >+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA >+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL >+//MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL >+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 >+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 >+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L >+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec >+//MPCC_OGAM4_MPCC_OGAM_MODE >+#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L >+//MPCC_OGAM4_MPCC_OGAM_LUT_INDEX >+#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL >+//MPCC_OGAM4_MPCC_OGAM_LUT_DATA >+#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL >+//MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL >+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 >+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 >+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L >+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec >+//MPCC_OGAM5_MPCC_OGAM_MODE >+#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L >+//MPCC_OGAM5_MPCC_OGAM_LUT_INDEX >+#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL >+//MPCC_OGAM5_MPCC_OGAM_LUT_DATA >+#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL >+//MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL >+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 >+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 >+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L >+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec >+//MPCC_OGAM6_MPCC_OGAM_MODE >+#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L >+//MPCC_OGAM6_MPCC_OGAM_LUT_INDEX >+#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL >+//MPCC_OGAM6_MPCC_OGAM_LUT_DATA >+#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL >+//MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL >+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 >+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 >+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L >+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec >+//MPCC_OGAM7_MPCC_OGAM_MODE >+#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L >+//MPCC_OGAM7_MPCC_OGAM_LUT_INDEX >+#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL >+//MPCC_OGAM7_MPCC_OGAM_LUT_DATA >+#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL >+//MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL >+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 >+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 >+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L >+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L >+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL >+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L >+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L >+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L >+ >+ >+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec >+//MPC_OUT_CSC_COEF_FORMAT >+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0 >+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1 >+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT 0x2 >+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT 0x3 >+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L >+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L >+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK 0x00000004L >+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK 0x00000008L >+//MPC_OUT0_CSC_MODE >+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 >+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L >+//MPC_OUT0_CSC_C11_C12_A >+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 >+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 >+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C13_C14_A >+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 >+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 >+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C21_C22_A >+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 >+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 >+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C23_C24_A >+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 >+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 >+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C31_C32_A >+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 >+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 >+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C33_C34_A >+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 >+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 >+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C11_C12_B >+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 >+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 >+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C13_C14_B >+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 >+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 >+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C21_C22_B >+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 >+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 >+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C23_C24_B >+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 >+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 >+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C31_C32_B >+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 >+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 >+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L >+//MPC_OUT0_CSC_C33_C34_B >+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 >+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 >+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL >+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_MODE >+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 >+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L >+//MPC_OUT1_CSC_C11_C12_A >+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 >+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 >+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C13_C14_A >+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 >+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 >+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C21_C22_A >+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 >+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 >+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C23_C24_A >+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 >+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 >+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C31_C32_A >+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 >+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 >+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C33_C34_A >+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 >+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 >+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C11_C12_B >+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 >+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 >+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C13_C14_B >+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 >+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 >+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C21_C22_B >+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 >+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 >+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C23_C24_B >+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 >+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 >+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C31_C32_B >+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 >+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 >+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L >+//MPC_OUT1_CSC_C33_C34_B >+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 >+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 >+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL >+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_MODE >+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 >+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L >+//MPC_OUT2_CSC_C11_C12_A >+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 >+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 >+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C13_C14_A >+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 >+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 >+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C21_C22_A >+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 >+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 >+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C23_C24_A >+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 >+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 >+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C31_C32_A >+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 >+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 >+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C33_C34_A >+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 >+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 >+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C11_C12_B >+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 >+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 >+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C13_C14_B >+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 >+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 >+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C21_C22_B >+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 >+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 >+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C23_C24_B >+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 >+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 >+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C31_C32_B >+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 >+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 >+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L >+//MPC_OUT2_CSC_C33_C34_B >+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 >+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 >+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL >+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_MODE >+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 >+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L >+//MPC_OUT3_CSC_C11_C12_A >+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 >+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 >+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C13_C14_A >+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 >+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 >+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C21_C22_A >+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 >+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 >+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C23_C24_A >+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 >+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 >+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C31_C32_A >+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 >+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 >+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C33_C34_A >+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 >+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 >+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C11_C12_B >+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 >+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 >+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C13_C14_B >+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 >+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 >+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C21_C22_B >+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 >+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 >+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C23_C24_B >+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 >+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 >+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C31_C32_B >+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 >+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 >+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L >+//MPC_OUT3_CSC_C33_C34_B >+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 >+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 >+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL >+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON15_PERFCOUNTER_CNTL >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON15_PERFCOUNTER_CNTL2 >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON15_PERFCOUNTER_STATE >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON15_PERFMON_CNTL >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON15_PERFMON_CNTL2 >+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON15_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON15_PERFMON_CVALUE_LOW >+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON15_PERFMON_HI >+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON15_PERFMON_LOW >+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_opp_abm0_dispdec >+//BL1_PWM_AMBIENT_LIGHT_LEVEL >+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 >+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL >+//BL1_PWM_USER_LEVEL >+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 >+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL >+//BL1_PWM_TARGET_ABM_LEVEL >+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 >+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL >+//BL1_PWM_CURRENT_ABM_LEVEL >+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 >+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL >+//BL1_PWM_FINAL_DUTY_CYCLE >+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 >+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL >+//BL1_PWM_MINIMUM_DUTY_CYCLE >+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 >+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL >+//BL1_PWM_ABM_CNTL >+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 >+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 >+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 >+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 >+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 >+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L >+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L >+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L >+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L >+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L >+//BL1_PWM_BL_UPDATE_SAMPLE_RATE >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L >+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L >+//BL1_PWM_GRP2_REG_LOCK >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L >+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L >+//DC_ABM1_CNTL >+#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 >+#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 >+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 >+#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L >+#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L >+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L >+//DC_ABM1_IPCSC_COEFF_SEL >+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 >+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 >+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 >+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f >+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL >+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L >+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L >+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L >+//DC_ABM1_ACE_OFFSET_SLOPE_0 >+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 >+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 >+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f >+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL >+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L >+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L >+//DC_ABM1_ACE_OFFSET_SLOPE_1 >+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 >+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 >+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f >+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL >+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L >+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L >+//DC_ABM1_ACE_OFFSET_SLOPE_2 >+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 >+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 >+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f >+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL >+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L >+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L >+//DC_ABM1_ACE_OFFSET_SLOPE_3 >+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 >+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 >+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f >+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL >+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L >+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L >+//DC_ABM1_ACE_OFFSET_SLOPE_4 >+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 >+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 >+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f >+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL >+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L >+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L >+//DC_ABM1_ACE_THRES_12 >+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 >+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 >+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f >+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL >+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L >+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L >+//DC_ABM1_ACE_THRES_34 >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L >+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L >+//DC_ABM1_ACE_CNTL_MISC >+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 >+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 >+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L >+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L >+//DC_ABM1_HGLS_REG_READ_PROGRESS >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L >+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L >+//DC_ABM1_HG_MISC_CTRL >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 >+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 >+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 >+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 >+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d >+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L >+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L >+//DC_ABM1_LS_SUM_OF_LUMA >+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 >+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL >+//DC_ABM1_LS_MIN_MAX_LUMA >+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 >+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 >+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL >+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L >+//DC_ABM1_LS_FILTERED_MIN_MAX_LUMA >+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 >+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 >+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL >+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L >+//DC_ABM1_LS_PIXEL_COUNT >+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 >+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 >+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL >+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L >+//DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES >+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 >+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 >+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f >+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL >+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L >+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L >+//DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT >+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 >+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL >+//DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT >+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 >+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL >+//DC_ABM1_HG_SAMPLE_RATE >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L >+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L >+//DC_ABM1_LS_SAMPLE_RATE >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L >+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L >+//DC_ABM1_HG_BIN_1_32_SHIFT_FLAG >+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 >+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_BIN_1_8_SHIFT_INDEX >+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 >+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_BIN_9_16_SHIFT_INDEX >+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 >+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_BIN_17_24_SHIFT_INDEX >+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 >+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_BIN_25_32_SHIFT_INDEX >+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 >+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_1 >+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_2 >+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_3 >+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_4 >+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_5 >+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_6 >+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_7 >+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_8 >+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_9 >+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_10 >+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_11 >+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_12 >+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_13 >+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_14 >+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_15 >+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_16 >+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_17 >+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_18 >+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_19 >+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_20 >+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_21 >+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_22 >+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_23 >+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL >+//DC_ABM1_HG_RESULT_24 >+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 >+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL >+//DC_ABM1_BL_MASTER_LOCK >+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f >+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L >+ >+ >+// addressBlock: dce_dc_opp_fmt0_dispdec >+//FMT0_FMT_CLAMP_COMPONENT_R >+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 >+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 >+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL >+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L >+//FMT0_FMT_CLAMP_COMPONENT_G >+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 >+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 >+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL >+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L >+//FMT0_FMT_CLAMP_COMPONENT_B >+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 >+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 >+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL >+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L >+//FMT0_FMT_DYNAMIC_EXP_CNTL >+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 >+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 >+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L >+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L >+//FMT0_FMT_CONTROL >+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 >+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 >+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc >+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 >+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 >+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 >+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 >+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c >+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L >+#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L >+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L >+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L >+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L >+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L >+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L >+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L >+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L >+//FMT0_FMT_BIT_DEPTH_CONTROL >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L >+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L >+//FMT0_FMT_DITHER_RAND_R_SEED >+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 >+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 >+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL >+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L >+//FMT0_FMT_DITHER_RAND_G_SEED >+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 >+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 >+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL >+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L >+//FMT0_FMT_DITHER_RAND_B_SEED >+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 >+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 >+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL >+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L >+//FMT0_FMT_CLAMP_CNTL >+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 >+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 >+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L >+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L >+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL >+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 >+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL >+//FMT0_FMT_MAP420_MEMORY_CONTROL >+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 >+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 >+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 >+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc >+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L >+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L >+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L >+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L >+//FMT0_FMT_422_CONTROL >+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 >+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_dpg0_dispdec >+//DPG0_DPG_CONTROL >+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 >+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4 >+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 >+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc >+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10 >+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14 >+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 >+#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L >+#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L >+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L >+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L >+#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L >+#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L >+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L >+//DPG0_DPG_RAMP_CONTROL >+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 >+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 >+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c >+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL >+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L >+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L >+//DPG0_DPG_DIMENSIONS >+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 >+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 >+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL >+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L >+//DPG0_DPG_COLOUR_R_CR >+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 >+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 >+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL >+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L >+//DPG0_DPG_COLOUR_G_Y >+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 >+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 >+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL >+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L >+//DPG0_DPG_COLOUR_B_CB >+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 >+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 >+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL >+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L >+//DPG0_DPG_OFFSET_SEGMENT >+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 >+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 >+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL >+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L >+//DPG0_DPG_STATUS >+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 >+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_oppbuf0_dispdec >+//OPPBUF0_OPPBUF_CONTROL >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L >+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L >+//OPPBUF0_OPPBUF_3D_PARAMETERS_0 >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L >+//OPPBUF0_OPPBUF_3D_PARAMETERS_1 >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL >+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L >+//OPPBUF0_OPPBUF_CONTROL1 >+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 >+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe0_dispdec >+//OPP_PIPE0_OPP_PIPE_CONTROL >+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 >+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 >+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 >+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L >+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L >+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec >+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L >+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL >+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L >+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L >+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 >+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL >+ >+ >+// addressBlock: dce_dc_opp_fmt1_dispdec >+//FMT1_FMT_CLAMP_COMPONENT_R >+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 >+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 >+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL >+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L >+//FMT1_FMT_CLAMP_COMPONENT_G >+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 >+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 >+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL >+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L >+//FMT1_FMT_CLAMP_COMPONENT_B >+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 >+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 >+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL >+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L >+//FMT1_FMT_DYNAMIC_EXP_CNTL >+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 >+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 >+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L >+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L >+//FMT1_FMT_CONTROL >+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 >+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 >+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc >+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 >+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 >+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 >+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 >+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c >+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L >+#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L >+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L >+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L >+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L >+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L >+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L >+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L >+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L >+//FMT1_FMT_BIT_DEPTH_CONTROL >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L >+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L >+//FMT1_FMT_DITHER_RAND_R_SEED >+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 >+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 >+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL >+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L >+//FMT1_FMT_DITHER_RAND_G_SEED >+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 >+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 >+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL >+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L >+//FMT1_FMT_DITHER_RAND_B_SEED >+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 >+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 >+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL >+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L >+//FMT1_FMT_CLAMP_CNTL >+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 >+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 >+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L >+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L >+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL >+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 >+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL >+//FMT1_FMT_MAP420_MEMORY_CONTROL >+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 >+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 >+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 >+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc >+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L >+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L >+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L >+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L >+//FMT1_FMT_422_CONTROL >+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 >+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_dpg1_dispdec >+//DPG1_DPG_CONTROL >+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0 >+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4 >+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 >+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc >+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10 >+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14 >+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 >+#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L >+#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L >+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L >+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L >+#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L >+#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L >+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L >+//DPG1_DPG_RAMP_CONTROL >+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 >+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 >+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c >+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL >+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L >+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L >+//DPG1_DPG_DIMENSIONS >+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 >+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 >+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL >+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L >+//DPG1_DPG_COLOUR_R_CR >+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 >+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 >+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL >+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L >+//DPG1_DPG_COLOUR_G_Y >+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 >+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 >+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL >+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L >+//DPG1_DPG_COLOUR_B_CB >+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 >+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 >+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL >+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L >+//DPG1_DPG_OFFSET_SEGMENT >+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 >+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 >+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL >+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L >+//DPG1_DPG_STATUS >+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 >+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_oppbuf1_dispdec >+//OPPBUF1_OPPBUF_CONTROL >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L >+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L >+//OPPBUF1_OPPBUF_3D_PARAMETERS_0 >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L >+//OPPBUF1_OPPBUF_3D_PARAMETERS_1 >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL >+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L >+//OPPBUF1_OPPBUF_CONTROL1 >+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 >+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe1_dispdec >+//OPP_PIPE1_OPP_PIPE_CONTROL >+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 >+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 >+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 >+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L >+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L >+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec >+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L >+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL >+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L >+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L >+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 >+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL >+ >+ >+// addressBlock: dce_dc_opp_fmt2_dispdec >+//FMT2_FMT_CLAMP_COMPONENT_R >+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 >+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 >+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL >+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L >+//FMT2_FMT_CLAMP_COMPONENT_G >+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 >+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 >+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL >+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L >+//FMT2_FMT_CLAMP_COMPONENT_B >+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 >+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 >+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL >+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L >+//FMT2_FMT_DYNAMIC_EXP_CNTL >+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 >+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 >+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L >+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L >+//FMT2_FMT_CONTROL >+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 >+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 >+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc >+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 >+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 >+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 >+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 >+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c >+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L >+#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L >+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L >+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L >+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L >+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L >+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L >+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L >+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L >+//FMT2_FMT_BIT_DEPTH_CONTROL >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L >+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L >+//FMT2_FMT_DITHER_RAND_R_SEED >+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 >+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 >+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL >+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L >+//FMT2_FMT_DITHER_RAND_G_SEED >+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 >+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 >+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL >+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L >+//FMT2_FMT_DITHER_RAND_B_SEED >+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 >+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 >+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL >+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L >+//FMT2_FMT_CLAMP_CNTL >+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 >+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 >+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L >+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L >+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL >+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 >+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL >+//FMT2_FMT_MAP420_MEMORY_CONTROL >+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 >+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 >+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 >+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc >+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L >+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L >+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L >+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L >+//FMT2_FMT_422_CONTROL >+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 >+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_dpg2_dispdec >+//DPG2_DPG_CONTROL >+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT 0x0 >+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT 0x4 >+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 >+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc >+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT 0x10 >+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT 0x14 >+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 >+#define DPG2_DPG_CONTROL__DPG_EN_MASK 0x00000001L >+#define DPG2_DPG_CONTROL__DPG_MODE_MASK 0x00000070L >+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L >+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L >+#define DPG2_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L >+#define DPG2_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L >+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L >+//DPG2_DPG_RAMP_CONTROL >+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 >+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 >+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c >+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL >+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L >+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L >+//DPG2_DPG_DIMENSIONS >+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 >+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 >+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL >+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L >+//DPG2_DPG_COLOUR_R_CR >+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 >+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 >+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL >+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L >+//DPG2_DPG_COLOUR_G_Y >+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 >+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 >+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL >+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L >+//DPG2_DPG_COLOUR_B_CB >+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 >+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 >+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL >+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L >+//DPG2_DPG_OFFSET_SEGMENT >+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 >+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 >+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL >+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L >+//DPG2_DPG_STATUS >+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 >+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_oppbuf2_dispdec >+//OPPBUF2_OPPBUF_CONTROL >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L >+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L >+//OPPBUF2_OPPBUF_3D_PARAMETERS_0 >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L >+//OPPBUF2_OPPBUF_3D_PARAMETERS_1 >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL >+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L >+//OPPBUF2_OPPBUF_CONTROL1 >+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 >+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe2_dispdec >+//OPP_PIPE2_OPP_PIPE_CONTROL >+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 >+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 >+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 >+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L >+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L >+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec >+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L >+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL >+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L >+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L >+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 >+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL >+ >+ >+// addressBlock: dce_dc_opp_fmt3_dispdec >+//FMT3_FMT_CLAMP_COMPONENT_R >+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 >+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 >+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL >+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L >+//FMT3_FMT_CLAMP_COMPONENT_G >+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 >+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 >+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL >+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L >+//FMT3_FMT_CLAMP_COMPONENT_B >+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 >+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 >+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL >+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L >+//FMT3_FMT_DYNAMIC_EXP_CNTL >+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 >+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 >+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L >+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L >+//FMT3_FMT_CONTROL >+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 >+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 >+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc >+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 >+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 >+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 >+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 >+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c >+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L >+#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L >+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L >+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L >+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L >+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L >+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L >+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L >+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L >+//FMT3_FMT_BIT_DEPTH_CONTROL >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L >+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L >+//FMT3_FMT_DITHER_RAND_R_SEED >+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 >+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 >+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL >+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L >+//FMT3_FMT_DITHER_RAND_G_SEED >+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 >+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 >+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL >+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L >+//FMT3_FMT_DITHER_RAND_B_SEED >+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 >+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 >+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL >+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L >+//FMT3_FMT_CLAMP_CNTL >+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 >+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 >+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L >+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L >+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL >+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 >+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL >+//FMT3_FMT_MAP420_MEMORY_CONTROL >+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 >+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 >+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 >+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc >+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L >+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L >+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L >+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L >+//FMT3_FMT_422_CONTROL >+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 >+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_dpg3_dispdec >+//DPG3_DPG_CONTROL >+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT 0x0 >+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT 0x4 >+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 >+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc >+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT 0x10 >+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT 0x14 >+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 >+#define DPG3_DPG_CONTROL__DPG_EN_MASK 0x00000001L >+#define DPG3_DPG_CONTROL__DPG_MODE_MASK 0x00000070L >+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L >+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L >+#define DPG3_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L >+#define DPG3_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L >+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L >+//DPG3_DPG_RAMP_CONTROL >+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 >+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 >+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c >+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL >+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L >+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L >+//DPG3_DPG_DIMENSIONS >+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 >+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 >+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL >+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L >+//DPG3_DPG_COLOUR_R_CR >+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 >+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 >+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL >+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L >+//DPG3_DPG_COLOUR_G_Y >+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 >+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 >+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL >+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L >+//DPG3_DPG_COLOUR_B_CB >+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 >+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 >+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL >+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L >+//DPG3_DPG_OFFSET_SEGMENT >+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 >+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 >+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL >+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L >+//DPG3_DPG_STATUS >+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 >+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_oppbuf3_dispdec >+//OPPBUF3_OPPBUF_CONTROL >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L >+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L >+//OPPBUF3_OPPBUF_3D_PARAMETERS_0 >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L >+//OPPBUF3_OPPBUF_3D_PARAMETERS_1 >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL >+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L >+//OPPBUF3_OPPBUF_CONTROL1 >+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 >+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe3_dispdec >+//OPP_PIPE3_OPP_PIPE_CONTROL >+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 >+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 >+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 >+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L >+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L >+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec >+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L >+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL >+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L >+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L >+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 >+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL >+ >+ >+// addressBlock: dce_dc_opp_fmt4_dispdec >+//FMT4_FMT_CLAMP_COMPONENT_R >+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 >+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 >+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL >+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L >+//FMT4_FMT_CLAMP_COMPONENT_G >+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 >+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 >+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL >+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L >+//FMT4_FMT_CLAMP_COMPONENT_B >+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 >+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 >+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL >+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L >+//FMT4_FMT_DYNAMIC_EXP_CNTL >+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 >+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 >+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L >+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L >+//FMT4_FMT_CONTROL >+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 >+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 >+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc >+#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 >+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 >+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 >+#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 >+#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c >+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L >+#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L >+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L >+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L >+#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L >+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L >+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L >+#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L >+#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L >+//FMT4_FMT_BIT_DEPTH_CONTROL >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L >+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L >+//FMT4_FMT_DITHER_RAND_R_SEED >+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 >+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 >+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL >+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L >+//FMT4_FMT_DITHER_RAND_G_SEED >+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 >+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 >+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL >+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L >+//FMT4_FMT_DITHER_RAND_B_SEED >+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 >+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 >+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL >+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L >+//FMT4_FMT_CLAMP_CNTL >+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 >+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 >+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L >+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L >+//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL >+#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 >+#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL >+//FMT4_FMT_MAP420_MEMORY_CONTROL >+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 >+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 >+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 >+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc >+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L >+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L >+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L >+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L >+//FMT4_FMT_422_CONTROL >+#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 >+#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_dpg4_dispdec >+//DPG4_DPG_CONTROL >+#define DPG4_DPG_CONTROL__DPG_EN__SHIFT 0x0 >+#define DPG4_DPG_CONTROL__DPG_MODE__SHIFT 0x4 >+#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 >+#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc >+#define DPG4_DPG_CONTROL__DPG_VRES__SHIFT 0x10 >+#define DPG4_DPG_CONTROL__DPG_HRES__SHIFT 0x14 >+#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 >+#define DPG4_DPG_CONTROL__DPG_EN_MASK 0x00000001L >+#define DPG4_DPG_CONTROL__DPG_MODE_MASK 0x00000070L >+#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L >+#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L >+#define DPG4_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L >+#define DPG4_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L >+#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L >+//DPG4_DPG_RAMP_CONTROL >+#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 >+#define DPG4_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 >+#define DPG4_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c >+#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL >+#define DPG4_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L >+#define DPG4_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L >+//DPG4_DPG_DIMENSIONS >+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 >+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 >+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL >+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L >+//DPG4_DPG_COLOUR_R_CR >+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 >+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 >+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL >+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L >+//DPG4_DPG_COLOUR_G_Y >+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 >+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 >+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL >+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L >+//DPG4_DPG_COLOUR_B_CB >+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 >+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 >+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL >+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L >+//DPG4_DPG_OFFSET_SEGMENT >+#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 >+#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 >+#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL >+#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L >+//DPG4_DPG_STATUS >+#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 >+#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_oppbuf4_dispdec >+//OPPBUF4_OPPBUF_CONTROL >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L >+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L >+//OPPBUF4_OPPBUF_3D_PARAMETERS_0 >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L >+//OPPBUF4_OPPBUF_3D_PARAMETERS_1 >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL >+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L >+//OPPBUF4_OPPBUF_CONTROL1 >+#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 >+#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe4_dispdec >+//OPP_PIPE4_OPP_PIPE_CONTROL >+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 >+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 >+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 >+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L >+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L >+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec >+//OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L >+//OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL >+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L >+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L >+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 >+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL >+ >+ >+// addressBlock: dce_dc_opp_fmt5_dispdec >+//FMT5_FMT_CLAMP_COMPONENT_R >+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 >+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 >+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL >+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L >+//FMT5_FMT_CLAMP_COMPONENT_G >+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 >+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 >+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL >+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L >+//FMT5_FMT_CLAMP_COMPONENT_B >+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 >+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 >+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL >+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L >+//FMT5_FMT_DYNAMIC_EXP_CNTL >+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 >+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 >+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L >+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L >+//FMT5_FMT_CONTROL >+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 >+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 >+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc >+#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 >+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 >+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 >+#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 >+#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c >+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L >+#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L >+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L >+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L >+#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L >+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L >+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L >+#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L >+#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L >+//FMT5_FMT_BIT_DEPTH_CONTROL >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L >+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L >+//FMT5_FMT_DITHER_RAND_R_SEED >+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 >+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 >+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL >+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L >+//FMT5_FMT_DITHER_RAND_G_SEED >+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 >+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 >+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL >+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L >+//FMT5_FMT_DITHER_RAND_B_SEED >+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 >+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 >+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL >+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L >+//FMT5_FMT_CLAMP_CNTL >+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 >+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 >+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L >+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L >+//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL >+#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 >+#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL >+//FMT5_FMT_MAP420_MEMORY_CONTROL >+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 >+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 >+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 >+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc >+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L >+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L >+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L >+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L >+//FMT5_FMT_422_CONTROL >+#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 >+#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_dpg5_dispdec >+//DPG5_DPG_CONTROL >+#define DPG5_DPG_CONTROL__DPG_EN__SHIFT 0x0 >+#define DPG5_DPG_CONTROL__DPG_MODE__SHIFT 0x4 >+#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 >+#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc >+#define DPG5_DPG_CONTROL__DPG_VRES__SHIFT 0x10 >+#define DPG5_DPG_CONTROL__DPG_HRES__SHIFT 0x14 >+#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 >+#define DPG5_DPG_CONTROL__DPG_EN_MASK 0x00000001L >+#define DPG5_DPG_CONTROL__DPG_MODE_MASK 0x00000070L >+#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L >+#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L >+#define DPG5_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L >+#define DPG5_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L >+#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L >+//DPG5_DPG_RAMP_CONTROL >+#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 >+#define DPG5_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 >+#define DPG5_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c >+#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL >+#define DPG5_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L >+#define DPG5_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L >+//DPG5_DPG_DIMENSIONS >+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 >+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 >+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL >+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L >+//DPG5_DPG_COLOUR_R_CR >+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 >+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 >+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL >+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L >+//DPG5_DPG_COLOUR_G_Y >+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 >+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 >+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL >+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L >+//DPG5_DPG_COLOUR_B_CB >+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 >+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 >+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL >+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L >+//DPG5_DPG_OFFSET_SEGMENT >+#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 >+#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 >+#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL >+#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L >+//DPG5_DPG_STATUS >+#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 >+#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_opp_oppbuf5_dispdec >+//OPPBUF5_OPPBUF_CONTROL >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L >+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L >+//OPPBUF5_OPPBUF_3D_PARAMETERS_0 >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L >+//OPPBUF5_OPPBUF_3D_PARAMETERS_1 >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL >+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L >+//OPPBUF5_OPPBUF_CONTROL1 >+#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 >+#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe5_dispdec >+//OPP_PIPE5_OPP_PIPE_CONTROL >+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 >+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 >+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 >+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L >+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L >+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L >+ >+ >+// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec >+//OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L >+//OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL >+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L >+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L >+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 >+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL >+ >+ >+// addressBlock: dce_dc_opp_opp_top_dispdec >+//OPP_TOP_CLK_CONTROL >+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 >+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 >+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 >+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc >+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd >+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L >+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L >+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L >+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L >+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L >+ >+ >+// addressBlock: dce_dc_opp_dscrm0_dispdec >+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG >+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 >+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 >+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 >+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc >+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L >+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L >+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L >+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L >+ >+ >+// addressBlock: dce_dc_opp_dscrm1_dispdec >+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG >+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 >+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 >+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 >+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc >+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L >+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L >+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L >+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L >+ >+ >+// addressBlock: dce_dc_opp_dscrm2_dispdec >+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG >+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 >+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 >+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 >+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc >+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L >+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L >+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L >+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L >+ >+ >+// addressBlock: dce_dc_opp_dscrm3_dispdec >+//DSCRM3_DSCRM_DSC_FORWARD_CONFIG >+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 >+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 >+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 >+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc >+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L >+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L >+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L >+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L >+ >+ >+// addressBlock: dce_dc_opp_dscrm4_dispdec >+//DSCRM4_DSCRM_DSC_FORWARD_CONFIG >+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 >+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 >+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 >+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc >+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L >+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L >+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L >+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L >+ >+ >+// addressBlock: dce_dc_opp_dscrm5_dispdec >+//DSCRM5_DSCRM_DSC_FORWARD_CONFIG >+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 >+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 >+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 >+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc >+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L >+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L >+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L >+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L >+ >+ >+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON16_PERFCOUNTER_CNTL >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON16_PERFCOUNTER_CNTL2 >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON16_PERFCOUNTER_STATE >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON16_PERFMON_CNTL >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON16_PERFMON_CNTL2 >+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON16_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON16_PERFMON_CVALUE_LOW >+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON16_PERFMON_HI >+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON16_PERFMON_LOW >+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_odm0_dispdec >+//ODM0_OPTC_INPUT_GLOBAL_CONTROL >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L >+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L >+//ODM0_OPTC_DATA_SOURCE_SELECT >+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 >+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 >+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 >+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc >+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L >+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL >+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L >+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L >+//ODM0_OPTC_DATA_FORMAT_CONTROL >+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 >+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 >+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L >+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L >+//ODM0_OPTC_BYTES_PER_PIXEL >+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//ODM0_OPTC_WIDTH_CONTROL >+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 >+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL >+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//ODM0_OPTC_INPUT_CLOCK_CONTROL >+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 >+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 >+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 >+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L >+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L >+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L >+//ODM0_OPTC_MEMORY_CONFIG >+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 >+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL >+//ODM0_OPTC_INPUT_SPARE_REGISTER >+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 >+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_odm1_dispdec >+//ODM1_OPTC_INPUT_GLOBAL_CONTROL >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L >+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L >+//ODM1_OPTC_DATA_SOURCE_SELECT >+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 >+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 >+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 >+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc >+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L >+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL >+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L >+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L >+//ODM1_OPTC_DATA_FORMAT_CONTROL >+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 >+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 >+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L >+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L >+//ODM1_OPTC_BYTES_PER_PIXEL >+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//ODM1_OPTC_WIDTH_CONTROL >+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 >+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL >+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//ODM1_OPTC_INPUT_CLOCK_CONTROL >+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 >+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 >+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 >+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L >+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L >+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L >+//ODM1_OPTC_MEMORY_CONFIG >+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 >+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL >+//ODM1_OPTC_INPUT_SPARE_REGISTER >+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 >+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_odm2_dispdec >+//ODM2_OPTC_INPUT_GLOBAL_CONTROL >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L >+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L >+//ODM2_OPTC_DATA_SOURCE_SELECT >+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 >+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 >+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 >+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc >+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L >+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL >+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L >+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L >+//ODM2_OPTC_DATA_FORMAT_CONTROL >+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 >+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 >+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L >+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L >+//ODM2_OPTC_BYTES_PER_PIXEL >+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//ODM2_OPTC_WIDTH_CONTROL >+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 >+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL >+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//ODM2_OPTC_INPUT_CLOCK_CONTROL >+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 >+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 >+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 >+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L >+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L >+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L >+//ODM2_OPTC_MEMORY_CONFIG >+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 >+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL >+//ODM2_OPTC_INPUT_SPARE_REGISTER >+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 >+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_odm3_dispdec >+//ODM3_OPTC_INPUT_GLOBAL_CONTROL >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L >+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L >+//ODM3_OPTC_DATA_SOURCE_SELECT >+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 >+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 >+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 >+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc >+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L >+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL >+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L >+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L >+//ODM3_OPTC_DATA_FORMAT_CONTROL >+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 >+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 >+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L >+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L >+//ODM3_OPTC_BYTES_PER_PIXEL >+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//ODM3_OPTC_WIDTH_CONTROL >+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 >+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL >+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//ODM3_OPTC_INPUT_CLOCK_CONTROL >+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 >+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 >+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 >+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L >+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L >+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L >+//ODM3_OPTC_MEMORY_CONFIG >+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 >+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL >+//ODM3_OPTC_INPUT_SPARE_REGISTER >+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 >+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_odm4_dispdec >+//ODM4_OPTC_INPUT_GLOBAL_CONTROL >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L >+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L >+//ODM4_OPTC_DATA_SOURCE_SELECT >+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 >+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 >+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 >+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc >+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L >+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL >+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L >+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L >+//ODM4_OPTC_DATA_FORMAT_CONTROL >+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 >+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 >+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L >+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L >+//ODM4_OPTC_BYTES_PER_PIXEL >+#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//ODM4_OPTC_WIDTH_CONTROL >+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 >+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL >+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//ODM4_OPTC_INPUT_CLOCK_CONTROL >+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 >+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 >+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 >+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L >+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L >+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L >+//ODM4_OPTC_MEMORY_CONFIG >+#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 >+#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL >+//ODM4_OPTC_INPUT_SPARE_REGISTER >+#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 >+#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_odm5_dispdec >+//ODM5_OPTC_INPUT_GLOBAL_CONTROL >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L >+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L >+//ODM5_OPTC_DATA_SOURCE_SELECT >+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 >+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 >+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 >+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc >+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L >+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL >+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L >+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L >+//ODM5_OPTC_DATA_FORMAT_CONTROL >+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 >+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 >+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L >+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L >+//ODM5_OPTC_BYTES_PER_PIXEL >+#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//ODM5_OPTC_WIDTH_CONTROL >+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 >+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL >+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//ODM5_OPTC_INPUT_CLOCK_CONTROL >+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 >+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 >+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 >+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L >+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L >+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L >+//ODM5_OPTC_MEMORY_CONFIG >+#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 >+#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL >+//ODM5_OPTC_INPUT_SPARE_REGISTER >+#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 >+#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_otg0_dispdec >+//OTG0_OTG_H_TOTAL >+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 >+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL >+//OTG0_OTG_H_BLANK_START_END >+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 >+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 >+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL >+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L >+//OTG0_OTG_H_SYNC_A >+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 >+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 >+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL >+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L >+//OTG0_OTG_H_SYNC_A_CNTL >+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 >+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 >+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 >+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L >+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L >+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L >+//OTG0_OTG_H_TIMING_CNTL >+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 >+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 >+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L >+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L >+//OTG0_OTG_V_TOTAL >+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 >+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL >+//OTG0_OTG_V_TOTAL_MIN >+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 >+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL >+//OTG0_OTG_V_TOTAL_MAX >+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 >+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL >+//OTG0_OTG_V_TOTAL_MID >+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 >+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL >+//OTG0_OTG_V_TOTAL_CONTROL >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L >+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L >+//OTG0_OTG_V_TOTAL_INT_STATUS >+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 >+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 >+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 >+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc >+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L >+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L >+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L >+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L >+//OTG0_OTG_VSYNC_NOM_INT_STATUS >+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 >+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 >+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L >+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L >+//OTG0_OTG_V_BLANK_START_END >+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 >+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 >+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL >+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L >+//OTG0_OTG_V_SYNC_A >+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 >+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 >+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL >+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L >+//OTG0_OTG_V_SYNC_A_CNTL >+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 >+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L >+//OTG0_OTG_TRIGA_CNTL >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L >+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L >+//OTG0_OTG_TRIGA_MANUAL_TRIG >+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 >+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L >+//OTG0_OTG_TRIGB_CNTL >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L >+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L >+//OTG0_OTG_TRIGB_MANUAL_TRIG >+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 >+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L >+//OTG0_OTG_FORCE_COUNT_NOW_CNTL >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L >+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L >+//OTG0_OTG_FLOW_CONTROL >+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 >+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 >+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 >+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 >+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L >+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L >+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L >+//OTG0_OTG_STEREO_FORCE_NEXT_EYE >+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 >+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 >+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 >+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L >+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L >+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L >+//OTG0_OTG_CONTROL >+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 >+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc >+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd >+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe >+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 >+#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 >+#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e >+#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f >+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L >+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L >+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L >+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L >+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L >+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L >+#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L >+#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L >+#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L >+//OTG0_OTG_BLANK_CONTROL >+#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 >+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 >+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 >+#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L >+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L >+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L >+//OTG0_OTG_PIPE_ABORT_CONTROL >+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 >+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 >+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L >+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L >+//OTG0_OTG_INTERLACE_CONTROL >+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 >+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 >+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L >+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L >+//OTG0_OTG_INTERLACE_STATUS >+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 >+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 >+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L >+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L >+//OTG0_OTG_PIXEL_DATA_READBACK0 >+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 >+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 >+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL >+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L >+//OTG0_OTG_PIXEL_DATA_READBACK1 >+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 >+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL >+//OTG0_OTG_STATUS >+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 >+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 >+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 >+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 >+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 >+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 >+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 >+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 >+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L >+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L >+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L >+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L >+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L >+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L >+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L >+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L >+//OTG0_OTG_STATUS_POSITION >+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 >+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 >+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL >+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG0_OTG_NOM_VERT_POSITION >+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 >+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL >+//OTG0_OTG_STATUS_FRAME_COUNT >+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 >+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG0_OTG_STATUS_VF_COUNT >+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 >+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL >+//OTG0_OTG_STATUS_HV_COUNT >+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 >+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL >+//OTG0_OTG_COUNT_CONTROL >+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 >+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 >+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L >+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL >+//OTG0_OTG_COUNT_RESET >+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 >+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L >+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE >+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 >+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L >+//OTG0_OTG_VERT_SYNC_CONTROL >+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 >+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 >+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 >+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L >+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L >+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L >+//OTG0_OTG_STEREO_STATUS >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 >+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e >+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L >+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L >+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L >+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L >+//OTG0_OTG_STEREO_CONTROL >+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 >+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf >+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 >+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 >+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 >+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 >+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 >+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 >+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL >+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L >+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L >+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L >+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L >+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L >+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L >+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L >+//OTG0_OTG_SNAPSHOT_STATUS >+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 >+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 >+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 >+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L >+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L >+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L >+//OTG0_OTG_SNAPSHOT_CONTROL >+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 >+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L >+//OTG0_OTG_SNAPSHOT_POSITION >+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 >+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 >+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL >+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG0_OTG_SNAPSHOT_FRAME >+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 >+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG0_OTG_INTERRUPT_CONTROL >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L >+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L >+//OTG0_OTG_UPDATE_LOCK >+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 >+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L >+//OTG0_OTG_DOUBLE_BUFFER_CONTROL >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L >+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L >+//OTG0_OTG_MASTER_EN >+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L >+//OTG0_OTG_BLANK_DATA_COLOR >+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 >+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa >+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 >+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL >+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L >+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L >+//OTG0_OTG_BLANK_DATA_COLOR_EXT >+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 >+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 >+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 >+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL >+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L >+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L >+//OTG0_OTG_BLACK_COLOR >+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 >+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa >+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 >+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL >+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L >+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L >+//OTG0_OTG_BLACK_COLOR_EXT >+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 >+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 >+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 >+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL >+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L >+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L >+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION >+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 >+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 >+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL >+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L >+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L >+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L >+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION >+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 >+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL >+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L >+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L >+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION >+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 >+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL >+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L >+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L >+//OTG0_OTG_CRC_CNTL >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 >+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 >+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c >+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d >+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e >+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L >+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L >+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L >+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L >+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L >+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L >+//OTG0_OTG_CRC_CNTL2 >+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 >+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 >+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 >+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 >+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L >+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L >+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L >+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L >+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL >+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 >+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 >+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL >+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL >+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 >+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 >+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL >+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG0_OTG_CRC0_DATA_RG >+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 >+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 >+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L >+//OTG0_OTG_CRC0_DATA_B >+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 >+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 >+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L >+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL >+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 >+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 >+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL >+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL >+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 >+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 >+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL >+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG0_OTG_CRC1_DATA_RG >+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 >+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 >+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L >+//OTG0_OTG_CRC1_DATA_B >+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 >+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 >+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L >+//OTG0_OTG_CRC2_DATA_RG >+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 >+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 >+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L >+//OTG0_OTG_CRC2_DATA_B >+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 >+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 >+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L >+//OTG0_OTG_CRC3_DATA_RG >+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 >+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 >+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L >+//OTG0_OTG_CRC3_DATA_B >+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 >+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 >+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L >+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK >+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 >+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 >+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L >+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK >+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 >+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 >+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL >+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L >+//OTG0_OTG_STATIC_SCREEN_CONTROL >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L >+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L >+//OTG0_OTG_3D_STRUCTURE_CONTROL >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L >+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L >+//OTG0_OTG_GSL_VSYNC_GAP >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L >+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L >+//OTG0_OTG_MASTER_UPDATE_MODE >+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 >+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L >+//OTG0_OTG_CLOCK_CONTROL >+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 >+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 >+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 >+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 >+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 >+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L >+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L >+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L >+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L >+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L >+//OTG0_OTG_VSTARTUP_PARAM >+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 >+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL >+//OTG0_OTG_VUPDATE_PARAM >+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 >+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 >+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL >+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L >+//OTG0_OTG_VREADY_PARAM >+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 >+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL >+//OTG0_OTG_GLOBAL_SYNC_STATUS >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L >+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L >+//OTG0_OTG_MASTER_UPDATE_LOCK >+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 >+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 >+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L >+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L >+//OTG0_OTG_GSL_CONTROL >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c >+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L >+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L >+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L >+//OTG0_OTG_GSL_WINDOW_X >+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 >+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 >+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL >+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L >+//OTG0_OTG_GSL_WINDOW_Y >+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 >+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 >+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL >+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L >+//OTG0_OTG_VUPDATE_KEEPOUT >+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 >+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 >+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f >+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL >+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L >+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L >+//OTG0_OTG_GLOBAL_CONTROL0 >+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 >+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 >+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 >+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL >+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L >+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L >+//OTG0_OTG_GLOBAL_CONTROL1 >+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 >+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 >+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f >+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL >+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L >+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L >+//OTG0_OTG_GLOBAL_CONTROL2 >+#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 >+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa >+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 >+#define OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d >+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e >+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f >+#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL >+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L >+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L >+#define OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L >+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L >+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L >+//OTG0_OTG_GLOBAL_CONTROL3 >+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 >+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 >+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 >+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L >+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L >+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L >+//OTG0_OTG_TRIG_MANUAL_CONTROL >+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 >+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L >+//OTG0_OTG_MANUAL_FLOW_CONTROL >+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 >+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L >+//OTG0_OTG_RANGE_TIMING_INT_STATUS >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L >+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L >+//OTG0_OTG_DRR_CONTROL >+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 >+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 >+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L >+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L >+//OTG0_OTG_REQUEST_CONTROL >+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 >+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L >+//OTG0_OTG_DSC_START_POSITION >+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 >+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 >+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL >+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L >+//OTG0_OTG_PIPE_UPDATE_STATUS >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L >+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L >+//OTG0_OTG_SPARE_REGISTER >+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 >+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_otg1_dispdec >+//OTG1_OTG_H_TOTAL >+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 >+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL >+//OTG1_OTG_H_BLANK_START_END >+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 >+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 >+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL >+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L >+//OTG1_OTG_H_SYNC_A >+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 >+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 >+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL >+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L >+//OTG1_OTG_H_SYNC_A_CNTL >+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 >+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 >+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 >+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L >+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L >+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L >+//OTG1_OTG_H_TIMING_CNTL >+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 >+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 >+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L >+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L >+//OTG1_OTG_V_TOTAL >+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 >+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL >+//OTG1_OTG_V_TOTAL_MIN >+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 >+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL >+//OTG1_OTG_V_TOTAL_MAX >+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 >+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL >+//OTG1_OTG_V_TOTAL_MID >+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 >+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL >+//OTG1_OTG_V_TOTAL_CONTROL >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L >+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L >+//OTG1_OTG_V_TOTAL_INT_STATUS >+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 >+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 >+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 >+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc >+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L >+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L >+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L >+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L >+//OTG1_OTG_VSYNC_NOM_INT_STATUS >+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 >+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 >+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L >+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L >+//OTG1_OTG_V_BLANK_START_END >+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 >+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 >+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL >+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L >+//OTG1_OTG_V_SYNC_A >+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 >+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 >+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL >+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L >+//OTG1_OTG_V_SYNC_A_CNTL >+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 >+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L >+//OTG1_OTG_TRIGA_CNTL >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L >+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L >+//OTG1_OTG_TRIGA_MANUAL_TRIG >+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 >+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L >+//OTG1_OTG_TRIGB_CNTL >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L >+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L >+//OTG1_OTG_TRIGB_MANUAL_TRIG >+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 >+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L >+//OTG1_OTG_FORCE_COUNT_NOW_CNTL >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L >+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L >+//OTG1_OTG_FLOW_CONTROL >+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 >+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 >+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 >+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 >+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L >+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L >+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L >+//OTG1_OTG_STEREO_FORCE_NEXT_EYE >+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 >+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 >+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 >+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L >+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L >+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L >+//OTG1_OTG_CONTROL >+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 >+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc >+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd >+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe >+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 >+#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 >+#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e >+#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f >+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L >+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L >+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L >+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L >+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L >+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L >+#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L >+#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L >+#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L >+//OTG1_OTG_BLANK_CONTROL >+#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 >+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 >+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 >+#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L >+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L >+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L >+//OTG1_OTG_PIPE_ABORT_CONTROL >+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 >+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 >+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L >+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L >+//OTG1_OTG_INTERLACE_CONTROL >+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 >+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 >+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L >+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L >+//OTG1_OTG_INTERLACE_STATUS >+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 >+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 >+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L >+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L >+//OTG1_OTG_PIXEL_DATA_READBACK0 >+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 >+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 >+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL >+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L >+//OTG1_OTG_PIXEL_DATA_READBACK1 >+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 >+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL >+//OTG1_OTG_STATUS >+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 >+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 >+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 >+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 >+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 >+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 >+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 >+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 >+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L >+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L >+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L >+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L >+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L >+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L >+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L >+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L >+//OTG1_OTG_STATUS_POSITION >+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 >+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 >+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL >+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG1_OTG_NOM_VERT_POSITION >+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 >+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL >+//OTG1_OTG_STATUS_FRAME_COUNT >+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 >+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG1_OTG_STATUS_VF_COUNT >+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 >+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL >+//OTG1_OTG_STATUS_HV_COUNT >+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 >+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL >+//OTG1_OTG_COUNT_CONTROL >+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 >+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 >+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L >+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL >+//OTG1_OTG_COUNT_RESET >+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 >+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L >+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE >+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 >+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L >+//OTG1_OTG_VERT_SYNC_CONTROL >+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 >+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 >+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 >+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L >+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L >+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L >+//OTG1_OTG_STEREO_STATUS >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 >+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e >+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L >+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L >+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L >+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L >+//OTG1_OTG_STEREO_CONTROL >+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 >+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf >+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 >+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 >+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 >+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 >+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 >+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 >+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL >+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L >+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L >+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L >+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L >+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L >+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L >+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L >+//OTG1_OTG_SNAPSHOT_STATUS >+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 >+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 >+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 >+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L >+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L >+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L >+//OTG1_OTG_SNAPSHOT_CONTROL >+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 >+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L >+//OTG1_OTG_SNAPSHOT_POSITION >+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 >+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 >+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL >+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG1_OTG_SNAPSHOT_FRAME >+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 >+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG1_OTG_INTERRUPT_CONTROL >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L >+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L >+//OTG1_OTG_UPDATE_LOCK >+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 >+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L >+//OTG1_OTG_DOUBLE_BUFFER_CONTROL >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L >+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L >+//OTG1_OTG_MASTER_EN >+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L >+//OTG1_OTG_BLANK_DATA_COLOR >+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 >+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa >+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 >+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL >+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L >+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L >+//OTG1_OTG_BLANK_DATA_COLOR_EXT >+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 >+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 >+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 >+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL >+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L >+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L >+//OTG1_OTG_BLACK_COLOR >+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 >+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa >+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 >+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL >+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L >+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L >+//OTG1_OTG_BLACK_COLOR_EXT >+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 >+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 >+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 >+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL >+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L >+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L >+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION >+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 >+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 >+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL >+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L >+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L >+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L >+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION >+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 >+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL >+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L >+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L >+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION >+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 >+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL >+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L >+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L >+//OTG1_OTG_CRC_CNTL >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 >+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 >+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c >+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d >+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e >+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L >+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L >+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L >+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L >+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L >+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L >+//OTG1_OTG_CRC_CNTL2 >+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 >+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 >+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 >+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 >+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L >+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L >+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L >+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L >+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL >+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 >+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 >+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL >+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL >+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 >+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 >+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL >+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG1_OTG_CRC0_DATA_RG >+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 >+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 >+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L >+//OTG1_OTG_CRC0_DATA_B >+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 >+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 >+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L >+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL >+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 >+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 >+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL >+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL >+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 >+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 >+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL >+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG1_OTG_CRC1_DATA_RG >+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 >+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 >+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L >+//OTG1_OTG_CRC1_DATA_B >+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 >+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 >+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L >+//OTG1_OTG_CRC2_DATA_RG >+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 >+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 >+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L >+//OTG1_OTG_CRC2_DATA_B >+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 >+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 >+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L >+//OTG1_OTG_CRC3_DATA_RG >+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 >+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 >+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L >+//OTG1_OTG_CRC3_DATA_B >+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 >+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 >+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L >+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK >+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 >+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 >+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L >+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK >+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 >+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 >+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL >+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L >+//OTG1_OTG_STATIC_SCREEN_CONTROL >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L >+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L >+//OTG1_OTG_3D_STRUCTURE_CONTROL >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L >+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L >+//OTG1_OTG_GSL_VSYNC_GAP >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L >+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L >+//OTG1_OTG_MASTER_UPDATE_MODE >+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 >+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L >+//OTG1_OTG_CLOCK_CONTROL >+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 >+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 >+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 >+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 >+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 >+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L >+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L >+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L >+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L >+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L >+//OTG1_OTG_VSTARTUP_PARAM >+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 >+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL >+//OTG1_OTG_VUPDATE_PARAM >+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 >+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 >+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL >+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L >+//OTG1_OTG_VREADY_PARAM >+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 >+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL >+//OTG1_OTG_GLOBAL_SYNC_STATUS >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L >+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L >+//OTG1_OTG_MASTER_UPDATE_LOCK >+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 >+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 >+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L >+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L >+//OTG1_OTG_GSL_CONTROL >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c >+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L >+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L >+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L >+//OTG1_OTG_GSL_WINDOW_X >+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 >+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 >+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL >+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L >+//OTG1_OTG_GSL_WINDOW_Y >+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 >+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 >+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL >+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L >+//OTG1_OTG_VUPDATE_KEEPOUT >+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 >+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 >+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f >+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL >+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L >+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L >+//OTG1_OTG_GLOBAL_CONTROL0 >+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 >+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 >+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 >+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL >+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L >+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L >+//OTG1_OTG_GLOBAL_CONTROL1 >+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 >+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 >+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f >+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL >+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L >+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L >+//OTG1_OTG_GLOBAL_CONTROL2 >+#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 >+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa >+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 >+#define OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d >+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e >+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f >+#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL >+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L >+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L >+#define OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L >+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L >+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L >+//OTG1_OTG_GLOBAL_CONTROL3 >+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 >+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 >+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 >+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L >+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L >+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L >+//OTG1_OTG_TRIG_MANUAL_CONTROL >+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 >+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L >+//OTG1_OTG_MANUAL_FLOW_CONTROL >+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 >+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L >+//OTG1_OTG_RANGE_TIMING_INT_STATUS >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L >+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L >+//OTG1_OTG_DRR_CONTROL >+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 >+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 >+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L >+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L >+//OTG1_OTG_REQUEST_CONTROL >+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 >+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L >+//OTG1_OTG_DSC_START_POSITION >+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 >+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 >+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL >+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L >+//OTG1_OTG_PIPE_UPDATE_STATUS >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L >+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L >+//OTG1_OTG_SPARE_REGISTER >+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 >+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_otg2_dispdec >+//OTG2_OTG_H_TOTAL >+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 >+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL >+//OTG2_OTG_H_BLANK_START_END >+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 >+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 >+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL >+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L >+//OTG2_OTG_H_SYNC_A >+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 >+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 >+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL >+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L >+//OTG2_OTG_H_SYNC_A_CNTL >+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 >+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 >+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 >+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L >+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L >+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L >+//OTG2_OTG_H_TIMING_CNTL >+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 >+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 >+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L >+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L >+//OTG2_OTG_V_TOTAL >+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 >+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL >+//OTG2_OTG_V_TOTAL_MIN >+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 >+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL >+//OTG2_OTG_V_TOTAL_MAX >+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 >+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL >+//OTG2_OTG_V_TOTAL_MID >+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 >+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL >+//OTG2_OTG_V_TOTAL_CONTROL >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L >+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L >+//OTG2_OTG_V_TOTAL_INT_STATUS >+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 >+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 >+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 >+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc >+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L >+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L >+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L >+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L >+//OTG2_OTG_VSYNC_NOM_INT_STATUS >+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 >+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 >+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L >+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L >+//OTG2_OTG_V_BLANK_START_END >+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 >+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 >+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL >+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L >+//OTG2_OTG_V_SYNC_A >+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 >+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 >+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL >+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L >+//OTG2_OTG_V_SYNC_A_CNTL >+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 >+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L >+//OTG2_OTG_TRIGA_CNTL >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L >+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L >+//OTG2_OTG_TRIGA_MANUAL_TRIG >+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 >+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L >+//OTG2_OTG_TRIGB_CNTL >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L >+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L >+//OTG2_OTG_TRIGB_MANUAL_TRIG >+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 >+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L >+//OTG2_OTG_FORCE_COUNT_NOW_CNTL >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L >+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L >+//OTG2_OTG_FLOW_CONTROL >+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 >+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 >+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 >+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 >+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L >+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L >+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L >+//OTG2_OTG_STEREO_FORCE_NEXT_EYE >+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 >+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 >+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 >+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L >+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L >+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L >+//OTG2_OTG_CONTROL >+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 >+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc >+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd >+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe >+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 >+#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 >+#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e >+#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f >+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L >+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L >+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L >+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L >+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L >+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L >+#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L >+#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L >+#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L >+//OTG2_OTG_BLANK_CONTROL >+#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 >+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 >+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 >+#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L >+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L >+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L >+//OTG2_OTG_PIPE_ABORT_CONTROL >+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 >+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 >+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L >+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L >+//OTG2_OTG_INTERLACE_CONTROL >+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 >+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 >+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L >+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L >+//OTG2_OTG_INTERLACE_STATUS >+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 >+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 >+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L >+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L >+//OTG2_OTG_PIXEL_DATA_READBACK0 >+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 >+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 >+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL >+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L >+//OTG2_OTG_PIXEL_DATA_READBACK1 >+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 >+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL >+//OTG2_OTG_STATUS >+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 >+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 >+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 >+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 >+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 >+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 >+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 >+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 >+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L >+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L >+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L >+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L >+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L >+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L >+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L >+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L >+//OTG2_OTG_STATUS_POSITION >+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 >+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 >+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL >+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG2_OTG_NOM_VERT_POSITION >+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 >+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL >+//OTG2_OTG_STATUS_FRAME_COUNT >+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 >+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG2_OTG_STATUS_VF_COUNT >+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 >+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL >+//OTG2_OTG_STATUS_HV_COUNT >+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 >+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL >+//OTG2_OTG_COUNT_CONTROL >+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 >+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 >+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L >+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL >+//OTG2_OTG_COUNT_RESET >+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 >+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L >+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE >+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 >+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L >+//OTG2_OTG_VERT_SYNC_CONTROL >+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 >+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 >+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 >+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L >+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L >+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L >+//OTG2_OTG_STEREO_STATUS >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 >+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e >+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L >+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L >+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L >+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L >+//OTG2_OTG_STEREO_CONTROL >+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 >+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf >+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 >+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 >+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 >+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 >+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 >+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 >+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL >+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L >+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L >+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L >+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L >+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L >+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L >+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L >+//OTG2_OTG_SNAPSHOT_STATUS >+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 >+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 >+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 >+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L >+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L >+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L >+//OTG2_OTG_SNAPSHOT_CONTROL >+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 >+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L >+//OTG2_OTG_SNAPSHOT_POSITION >+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 >+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 >+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL >+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG2_OTG_SNAPSHOT_FRAME >+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 >+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG2_OTG_INTERRUPT_CONTROL >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L >+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L >+//OTG2_OTG_UPDATE_LOCK >+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 >+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L >+//OTG2_OTG_DOUBLE_BUFFER_CONTROL >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L >+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L >+//OTG2_OTG_MASTER_EN >+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L >+//OTG2_OTG_BLANK_DATA_COLOR >+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 >+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa >+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 >+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL >+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L >+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L >+//OTG2_OTG_BLANK_DATA_COLOR_EXT >+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 >+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 >+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 >+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL >+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L >+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L >+//OTG2_OTG_BLACK_COLOR >+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 >+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa >+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 >+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL >+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L >+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L >+//OTG2_OTG_BLACK_COLOR_EXT >+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 >+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 >+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 >+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL >+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L >+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L >+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION >+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 >+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 >+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL >+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L >+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L >+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L >+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION >+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 >+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL >+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L >+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L >+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION >+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 >+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL >+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L >+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L >+//OTG2_OTG_CRC_CNTL >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 >+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 >+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c >+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d >+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e >+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L >+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L >+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L >+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L >+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L >+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L >+//OTG2_OTG_CRC_CNTL2 >+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 >+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 >+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 >+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 >+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L >+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L >+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L >+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L >+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL >+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 >+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 >+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL >+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL >+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 >+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 >+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL >+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG2_OTG_CRC0_DATA_RG >+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 >+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 >+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L >+//OTG2_OTG_CRC0_DATA_B >+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 >+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 >+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L >+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL >+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 >+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 >+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL >+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL >+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 >+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 >+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL >+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG2_OTG_CRC1_DATA_RG >+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 >+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 >+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L >+//OTG2_OTG_CRC1_DATA_B >+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 >+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 >+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L >+//OTG2_OTG_CRC2_DATA_RG >+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 >+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 >+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L >+//OTG2_OTG_CRC2_DATA_B >+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 >+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 >+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L >+//OTG2_OTG_CRC3_DATA_RG >+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 >+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 >+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L >+//OTG2_OTG_CRC3_DATA_B >+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 >+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 >+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L >+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK >+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 >+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 >+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L >+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK >+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 >+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 >+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL >+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L >+//OTG2_OTG_STATIC_SCREEN_CONTROL >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L >+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L >+//OTG2_OTG_3D_STRUCTURE_CONTROL >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L >+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L >+//OTG2_OTG_GSL_VSYNC_GAP >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L >+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L >+//OTG2_OTG_MASTER_UPDATE_MODE >+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 >+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L >+//OTG2_OTG_CLOCK_CONTROL >+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 >+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 >+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 >+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 >+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 >+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L >+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L >+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L >+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L >+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L >+//OTG2_OTG_VSTARTUP_PARAM >+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 >+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL >+//OTG2_OTG_VUPDATE_PARAM >+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 >+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 >+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL >+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L >+//OTG2_OTG_VREADY_PARAM >+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 >+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL >+//OTG2_OTG_GLOBAL_SYNC_STATUS >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L >+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L >+//OTG2_OTG_MASTER_UPDATE_LOCK >+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 >+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 >+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L >+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L >+//OTG2_OTG_GSL_CONTROL >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c >+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L >+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L >+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L >+//OTG2_OTG_GSL_WINDOW_X >+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 >+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 >+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL >+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L >+//OTG2_OTG_GSL_WINDOW_Y >+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 >+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 >+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL >+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L >+//OTG2_OTG_VUPDATE_KEEPOUT >+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 >+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 >+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f >+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL >+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L >+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L >+//OTG2_OTG_GLOBAL_CONTROL0 >+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 >+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 >+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 >+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL >+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L >+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L >+//OTG2_OTG_GLOBAL_CONTROL1 >+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 >+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 >+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f >+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL >+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L >+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L >+//OTG2_OTG_GLOBAL_CONTROL2 >+#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 >+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa >+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 >+#define OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d >+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e >+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f >+#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL >+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L >+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L >+#define OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L >+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L >+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L >+//OTG2_OTG_GLOBAL_CONTROL3 >+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 >+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 >+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 >+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L >+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L >+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L >+//OTG2_OTG_TRIG_MANUAL_CONTROL >+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 >+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L >+//OTG2_OTG_MANUAL_FLOW_CONTROL >+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 >+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L >+//OTG2_OTG_RANGE_TIMING_INT_STATUS >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L >+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L >+//OTG2_OTG_DRR_CONTROL >+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 >+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 >+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L >+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L >+//OTG2_OTG_REQUEST_CONTROL >+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 >+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L >+//OTG2_OTG_DSC_START_POSITION >+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 >+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 >+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL >+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L >+//OTG2_OTG_PIPE_UPDATE_STATUS >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L >+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L >+//OTG2_OTG_SPARE_REGISTER >+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 >+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_otg3_dispdec >+//OTG3_OTG_H_TOTAL >+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 >+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL >+//OTG3_OTG_H_BLANK_START_END >+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 >+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 >+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL >+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L >+//OTG3_OTG_H_SYNC_A >+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 >+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 >+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL >+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L >+//OTG3_OTG_H_SYNC_A_CNTL >+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 >+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 >+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 >+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L >+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L >+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L >+//OTG3_OTG_H_TIMING_CNTL >+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 >+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 >+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L >+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L >+//OTG3_OTG_V_TOTAL >+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 >+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL >+//OTG3_OTG_V_TOTAL_MIN >+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 >+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL >+//OTG3_OTG_V_TOTAL_MAX >+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 >+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL >+//OTG3_OTG_V_TOTAL_MID >+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 >+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL >+//OTG3_OTG_V_TOTAL_CONTROL >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L >+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L >+//OTG3_OTG_V_TOTAL_INT_STATUS >+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 >+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 >+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 >+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc >+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L >+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L >+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L >+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L >+//OTG3_OTG_VSYNC_NOM_INT_STATUS >+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 >+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 >+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L >+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L >+//OTG3_OTG_V_BLANK_START_END >+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 >+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 >+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL >+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L >+//OTG3_OTG_V_SYNC_A >+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 >+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 >+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL >+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L >+//OTG3_OTG_V_SYNC_A_CNTL >+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 >+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L >+//OTG3_OTG_TRIGA_CNTL >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L >+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L >+//OTG3_OTG_TRIGA_MANUAL_TRIG >+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 >+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L >+//OTG3_OTG_TRIGB_CNTL >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L >+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L >+//OTG3_OTG_TRIGB_MANUAL_TRIG >+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 >+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L >+//OTG3_OTG_FORCE_COUNT_NOW_CNTL >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L >+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L >+//OTG3_OTG_FLOW_CONTROL >+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 >+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 >+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 >+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 >+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L >+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L >+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L >+//OTG3_OTG_STEREO_FORCE_NEXT_EYE >+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 >+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 >+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 >+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L >+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L >+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L >+//OTG3_OTG_CONTROL >+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 >+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc >+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd >+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe >+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 >+#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 >+#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e >+#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f >+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L >+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L >+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L >+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L >+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L >+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L >+#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L >+#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L >+#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L >+//OTG3_OTG_BLANK_CONTROL >+#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 >+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 >+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 >+#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L >+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L >+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L >+//OTG3_OTG_PIPE_ABORT_CONTROL >+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 >+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 >+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L >+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L >+//OTG3_OTG_INTERLACE_CONTROL >+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 >+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 >+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L >+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L >+//OTG3_OTG_INTERLACE_STATUS >+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 >+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 >+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L >+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L >+//OTG3_OTG_PIXEL_DATA_READBACK0 >+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 >+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 >+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL >+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L >+//OTG3_OTG_PIXEL_DATA_READBACK1 >+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 >+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL >+//OTG3_OTG_STATUS >+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 >+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 >+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 >+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 >+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 >+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 >+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 >+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 >+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L >+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L >+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L >+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L >+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L >+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L >+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L >+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L >+//OTG3_OTG_STATUS_POSITION >+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 >+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 >+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL >+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG3_OTG_NOM_VERT_POSITION >+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 >+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL >+//OTG3_OTG_STATUS_FRAME_COUNT >+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 >+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG3_OTG_STATUS_VF_COUNT >+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 >+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL >+//OTG3_OTG_STATUS_HV_COUNT >+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 >+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL >+//OTG3_OTG_COUNT_CONTROL >+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 >+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 >+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L >+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL >+//OTG3_OTG_COUNT_RESET >+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 >+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L >+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE >+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 >+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L >+//OTG3_OTG_VERT_SYNC_CONTROL >+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 >+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 >+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 >+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L >+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L >+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L >+//OTG3_OTG_STEREO_STATUS >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 >+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e >+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L >+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L >+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L >+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L >+//OTG3_OTG_STEREO_CONTROL >+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 >+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf >+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 >+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 >+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 >+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 >+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 >+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 >+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL >+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L >+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L >+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L >+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L >+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L >+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L >+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L >+//OTG3_OTG_SNAPSHOT_STATUS >+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 >+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 >+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 >+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L >+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L >+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L >+//OTG3_OTG_SNAPSHOT_CONTROL >+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 >+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L >+//OTG3_OTG_SNAPSHOT_POSITION >+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 >+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 >+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL >+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG3_OTG_SNAPSHOT_FRAME >+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 >+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG3_OTG_INTERRUPT_CONTROL >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L >+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L >+//OTG3_OTG_UPDATE_LOCK >+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 >+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L >+//OTG3_OTG_DOUBLE_BUFFER_CONTROL >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L >+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L >+//OTG3_OTG_MASTER_EN >+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L >+//OTG3_OTG_BLANK_DATA_COLOR >+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 >+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa >+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 >+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL >+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L >+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L >+//OTG3_OTG_BLANK_DATA_COLOR_EXT >+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 >+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 >+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 >+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL >+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L >+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L >+//OTG3_OTG_BLACK_COLOR >+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 >+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa >+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 >+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL >+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L >+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L >+//OTG3_OTG_BLACK_COLOR_EXT >+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 >+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 >+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 >+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL >+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L >+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L >+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION >+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 >+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 >+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL >+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L >+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L >+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L >+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION >+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 >+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL >+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L >+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L >+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION >+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 >+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL >+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L >+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L >+//OTG3_OTG_CRC_CNTL >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 >+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 >+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c >+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d >+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e >+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L >+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L >+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L >+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L >+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L >+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L >+//OTG3_OTG_CRC_CNTL2 >+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 >+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 >+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 >+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 >+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L >+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L >+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L >+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L >+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL >+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 >+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 >+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL >+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL >+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 >+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 >+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL >+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG3_OTG_CRC0_DATA_RG >+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 >+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 >+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L >+//OTG3_OTG_CRC0_DATA_B >+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 >+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 >+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L >+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL >+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 >+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 >+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL >+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL >+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 >+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 >+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL >+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG3_OTG_CRC1_DATA_RG >+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 >+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 >+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L >+//OTG3_OTG_CRC1_DATA_B >+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 >+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 >+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L >+//OTG3_OTG_CRC2_DATA_RG >+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 >+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 >+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L >+//OTG3_OTG_CRC2_DATA_B >+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 >+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 >+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L >+//OTG3_OTG_CRC3_DATA_RG >+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 >+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 >+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L >+//OTG3_OTG_CRC3_DATA_B >+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 >+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 >+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L >+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK >+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 >+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 >+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L >+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK >+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 >+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 >+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL >+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L >+//OTG3_OTG_STATIC_SCREEN_CONTROL >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L >+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L >+//OTG3_OTG_3D_STRUCTURE_CONTROL >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L >+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L >+//OTG3_OTG_GSL_VSYNC_GAP >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L >+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L >+//OTG3_OTG_MASTER_UPDATE_MODE >+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 >+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L >+//OTG3_OTG_CLOCK_CONTROL >+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 >+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 >+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 >+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 >+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 >+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L >+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L >+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L >+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L >+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L >+//OTG3_OTG_VSTARTUP_PARAM >+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 >+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL >+//OTG3_OTG_VUPDATE_PARAM >+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 >+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 >+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL >+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L >+//OTG3_OTG_VREADY_PARAM >+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 >+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL >+//OTG3_OTG_GLOBAL_SYNC_STATUS >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L >+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L >+//OTG3_OTG_MASTER_UPDATE_LOCK >+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 >+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 >+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L >+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L >+//OTG3_OTG_GSL_CONTROL >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c >+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L >+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L >+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L >+//OTG3_OTG_GSL_WINDOW_X >+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 >+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 >+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL >+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L >+//OTG3_OTG_GSL_WINDOW_Y >+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 >+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 >+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL >+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L >+//OTG3_OTG_VUPDATE_KEEPOUT >+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 >+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 >+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f >+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL >+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L >+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L >+//OTG3_OTG_GLOBAL_CONTROL0 >+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 >+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 >+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 >+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL >+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L >+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L >+//OTG3_OTG_GLOBAL_CONTROL1 >+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 >+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 >+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f >+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL >+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L >+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L >+//OTG3_OTG_GLOBAL_CONTROL2 >+#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 >+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa >+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 >+#define OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d >+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e >+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f >+#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL >+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L >+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L >+#define OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L >+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L >+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L >+//OTG3_OTG_GLOBAL_CONTROL3 >+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 >+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 >+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 >+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L >+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L >+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L >+//OTG3_OTG_TRIG_MANUAL_CONTROL >+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 >+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L >+//OTG3_OTG_MANUAL_FLOW_CONTROL >+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 >+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L >+//OTG3_OTG_RANGE_TIMING_INT_STATUS >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L >+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L >+//OTG3_OTG_DRR_CONTROL >+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 >+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 >+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L >+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L >+//OTG3_OTG_REQUEST_CONTROL >+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 >+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L >+//OTG3_OTG_DSC_START_POSITION >+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 >+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 >+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL >+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L >+//OTG3_OTG_PIPE_UPDATE_STATUS >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L >+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L >+//OTG3_OTG_SPARE_REGISTER >+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 >+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_otg4_dispdec >+//OTG4_OTG_H_TOTAL >+#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 >+#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL >+//OTG4_OTG_H_BLANK_START_END >+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 >+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 >+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL >+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L >+//OTG4_OTG_H_SYNC_A >+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 >+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 >+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL >+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L >+//OTG4_OTG_H_SYNC_A_CNTL >+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 >+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 >+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 >+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L >+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L >+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L >+//OTG4_OTG_H_TIMING_CNTL >+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 >+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 >+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L >+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L >+//OTG4_OTG_V_TOTAL >+#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 >+#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL >+//OTG4_OTG_V_TOTAL_MIN >+#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 >+#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL >+//OTG4_OTG_V_TOTAL_MAX >+#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 >+#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL >+//OTG4_OTG_V_TOTAL_MID >+#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 >+#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL >+//OTG4_OTG_V_TOTAL_CONTROL >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L >+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L >+//OTG4_OTG_V_TOTAL_INT_STATUS >+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 >+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 >+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 >+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc >+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L >+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L >+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L >+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L >+//OTG4_OTG_VSYNC_NOM_INT_STATUS >+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 >+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 >+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L >+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L >+//OTG4_OTG_V_BLANK_START_END >+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 >+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 >+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL >+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L >+//OTG4_OTG_V_SYNC_A >+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 >+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 >+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL >+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L >+//OTG4_OTG_V_SYNC_A_CNTL >+#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 >+#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L >+//OTG4_OTG_TRIGA_CNTL >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L >+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L >+//OTG4_OTG_TRIGA_MANUAL_TRIG >+#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 >+#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L >+//OTG4_OTG_TRIGB_CNTL >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L >+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L >+//OTG4_OTG_TRIGB_MANUAL_TRIG >+#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 >+#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L >+//OTG4_OTG_FORCE_COUNT_NOW_CNTL >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L >+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L >+//OTG4_OTG_FLOW_CONTROL >+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 >+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 >+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 >+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 >+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L >+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L >+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L >+//OTG4_OTG_STEREO_FORCE_NEXT_EYE >+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 >+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 >+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 >+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L >+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L >+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L >+//OTG4_OTG_CONTROL >+#define OTG4_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 >+#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc >+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd >+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe >+#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 >+#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 >+#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e >+#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f >+#define OTG4_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L >+#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L >+#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L >+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L >+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L >+#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L >+#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L >+#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L >+#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L >+//OTG4_OTG_BLANK_CONTROL >+#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 >+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 >+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 >+#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L >+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L >+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L >+//OTG4_OTG_PIPE_ABORT_CONTROL >+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 >+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 >+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L >+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L >+//OTG4_OTG_INTERLACE_CONTROL >+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 >+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 >+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L >+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L >+//OTG4_OTG_INTERLACE_STATUS >+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 >+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 >+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L >+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L >+//OTG4_OTG_PIXEL_DATA_READBACK0 >+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 >+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 >+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL >+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L >+//OTG4_OTG_PIXEL_DATA_READBACK1 >+#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 >+#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL >+//OTG4_OTG_STATUS >+#define OTG4_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 >+#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 >+#define OTG4_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 >+#define OTG4_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 >+#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 >+#define OTG4_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 >+#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 >+#define OTG4_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 >+#define OTG4_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L >+#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L >+#define OTG4_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L >+#define OTG4_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L >+#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L >+#define OTG4_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L >+#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L >+#define OTG4_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L >+//OTG4_OTG_STATUS_POSITION >+#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 >+#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 >+#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL >+#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG4_OTG_NOM_VERT_POSITION >+#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 >+#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL >+//OTG4_OTG_STATUS_FRAME_COUNT >+#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 >+#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG4_OTG_STATUS_VF_COUNT >+#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 >+#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL >+//OTG4_OTG_STATUS_HV_COUNT >+#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 >+#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL >+//OTG4_OTG_COUNT_CONTROL >+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 >+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 >+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L >+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL >+//OTG4_OTG_COUNT_RESET >+#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 >+#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L >+//OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE >+#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 >+#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L >+//OTG4_OTG_VERT_SYNC_CONTROL >+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 >+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 >+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 >+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L >+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L >+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L >+//OTG4_OTG_STEREO_STATUS >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 >+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e >+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L >+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L >+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L >+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L >+//OTG4_OTG_STEREO_CONTROL >+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 >+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf >+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 >+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 >+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 >+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 >+#define OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 >+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 >+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL >+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L >+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L >+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L >+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L >+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L >+#define OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L >+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L >+//OTG4_OTG_SNAPSHOT_STATUS >+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 >+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 >+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 >+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L >+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L >+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L >+//OTG4_OTG_SNAPSHOT_CONTROL >+#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 >+#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L >+//OTG4_OTG_SNAPSHOT_POSITION >+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 >+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 >+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL >+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG4_OTG_SNAPSHOT_FRAME >+#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 >+#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG4_OTG_INTERRUPT_CONTROL >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L >+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L >+//OTG4_OTG_UPDATE_LOCK >+#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 >+#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L >+//OTG4_OTG_DOUBLE_BUFFER_CONTROL >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L >+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L >+//OTG4_OTG_MASTER_EN >+#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L >+//OTG4_OTG_BLANK_DATA_COLOR >+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 >+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa >+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 >+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL >+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L >+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L >+//OTG4_OTG_BLANK_DATA_COLOR_EXT >+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 >+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 >+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 >+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL >+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L >+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L >+//OTG4_OTG_BLACK_COLOR >+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 >+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa >+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 >+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL >+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L >+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L >+//OTG4_OTG_BLACK_COLOR_EXT >+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 >+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 >+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 >+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL >+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L >+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L >+//OTG4_OTG_VERTICAL_INTERRUPT0_POSITION >+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 >+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 >+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL >+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L >+//OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L >+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L >+//OTG4_OTG_VERTICAL_INTERRUPT1_POSITION >+#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 >+#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL >+//OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L >+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L >+//OTG4_OTG_VERTICAL_INTERRUPT2_POSITION >+#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 >+#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL >+//OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L >+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L >+//OTG4_OTG_CRC_CNTL >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 >+#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 >+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c >+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d >+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e >+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L >+#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L >+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L >+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L >+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L >+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L >+//OTG4_OTG_CRC_CNTL2 >+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 >+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 >+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 >+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 >+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L >+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L >+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L >+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L >+//OTG4_OTG_CRC0_WINDOWA_X_CONTROL >+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 >+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 >+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG4_OTG_CRC0_WINDOWA_Y_CONTROL >+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG4_OTG_CRC0_WINDOWB_X_CONTROL >+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 >+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 >+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG4_OTG_CRC0_WINDOWB_Y_CONTROL >+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG4_OTG_CRC0_DATA_RG >+#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 >+#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 >+#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L >+//OTG4_OTG_CRC0_DATA_B >+#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 >+#define OTG4_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 >+#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L >+//OTG4_OTG_CRC1_WINDOWA_X_CONTROL >+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 >+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 >+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG4_OTG_CRC1_WINDOWA_Y_CONTROL >+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG4_OTG_CRC1_WINDOWB_X_CONTROL >+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 >+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 >+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG4_OTG_CRC1_WINDOWB_Y_CONTROL >+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG4_OTG_CRC1_DATA_RG >+#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 >+#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 >+#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L >+//OTG4_OTG_CRC1_DATA_B >+#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 >+#define OTG4_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 >+#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L >+//OTG4_OTG_CRC2_DATA_RG >+#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 >+#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 >+#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L >+//OTG4_OTG_CRC2_DATA_B >+#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 >+#define OTG4_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 >+#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L >+//OTG4_OTG_CRC3_DATA_RG >+#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 >+#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 >+#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L >+//OTG4_OTG_CRC3_DATA_B >+#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 >+#define OTG4_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 >+#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L >+//OTG4_OTG_CRC_SIG_RED_GREEN_MASK >+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 >+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 >+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L >+//OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK >+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 >+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 >+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL >+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L >+//OTG4_OTG_STATIC_SCREEN_CONTROL >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L >+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L >+//OTG4_OTG_3D_STRUCTURE_CONTROL >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L >+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L >+//OTG4_OTG_GSL_VSYNC_GAP >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L >+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L >+//OTG4_OTG_MASTER_UPDATE_MODE >+#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 >+#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L >+//OTG4_OTG_CLOCK_CONTROL >+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 >+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 >+#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 >+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 >+#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 >+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L >+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L >+#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L >+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L >+#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L >+//OTG4_OTG_VSTARTUP_PARAM >+#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 >+#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL >+//OTG4_OTG_VUPDATE_PARAM >+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 >+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 >+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL >+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L >+//OTG4_OTG_VREADY_PARAM >+#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 >+#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL >+//OTG4_OTG_GLOBAL_SYNC_STATUS >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L >+#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L >+//OTG4_OTG_MASTER_UPDATE_LOCK >+#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 >+#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 >+#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L >+#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L >+//OTG4_OTG_GSL_CONTROL >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c >+#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L >+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L >+#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L >+//OTG4_OTG_GSL_WINDOW_X >+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 >+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 >+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL >+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L >+//OTG4_OTG_GSL_WINDOW_Y >+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 >+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 >+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL >+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L >+//OTG4_OTG_VUPDATE_KEEPOUT >+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 >+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 >+#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f >+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL >+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L >+#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L >+//OTG4_OTG_GLOBAL_CONTROL0 >+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 >+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 >+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 >+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL >+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L >+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L >+//OTG4_OTG_GLOBAL_CONTROL1 >+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 >+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 >+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f >+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL >+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L >+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L >+//OTG4_OTG_GLOBAL_CONTROL2 >+#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 >+#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa >+#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 >+#define OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d >+#define OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e >+#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f >+#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL >+#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L >+#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L >+#define OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L >+#define OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L >+#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L >+//OTG4_OTG_GLOBAL_CONTROL3 >+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 >+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 >+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 >+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L >+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L >+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L >+//OTG4_OTG_TRIG_MANUAL_CONTROL >+#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 >+#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L >+//OTG4_OTG_MANUAL_FLOW_CONTROL >+#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 >+#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L >+//OTG4_OTG_RANGE_TIMING_INT_STATUS >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L >+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L >+//OTG4_OTG_DRR_CONTROL >+#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 >+#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 >+#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L >+#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L >+//OTG4_OTG_REQUEST_CONTROL >+#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 >+#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L >+//OTG4_OTG_DSC_START_POSITION >+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 >+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 >+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL >+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L >+//OTG4_OTG_PIPE_UPDATE_STATUS >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L >+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L >+//OTG4_OTG_SPARE_REGISTER >+#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 >+#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_otg5_dispdec >+//OTG5_OTG_H_TOTAL >+#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 >+#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL >+//OTG5_OTG_H_BLANK_START_END >+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 >+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 >+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL >+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L >+//OTG5_OTG_H_SYNC_A >+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 >+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 >+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL >+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L >+//OTG5_OTG_H_SYNC_A_CNTL >+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 >+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 >+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 >+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L >+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L >+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L >+//OTG5_OTG_H_TIMING_CNTL >+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 >+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 >+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L >+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L >+//OTG5_OTG_V_TOTAL >+#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 >+#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL >+//OTG5_OTG_V_TOTAL_MIN >+#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 >+#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL >+//OTG5_OTG_V_TOTAL_MAX >+#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 >+#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL >+//OTG5_OTG_V_TOTAL_MID >+#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 >+#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL >+//OTG5_OTG_V_TOTAL_CONTROL >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L >+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L >+//OTG5_OTG_V_TOTAL_INT_STATUS >+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 >+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 >+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 >+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc >+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L >+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L >+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L >+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L >+//OTG5_OTG_VSYNC_NOM_INT_STATUS >+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 >+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 >+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L >+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L >+//OTG5_OTG_V_BLANK_START_END >+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 >+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 >+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL >+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L >+//OTG5_OTG_V_SYNC_A >+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 >+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 >+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL >+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L >+//OTG5_OTG_V_SYNC_A_CNTL >+#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 >+#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L >+//OTG5_OTG_TRIGA_CNTL >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L >+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L >+//OTG5_OTG_TRIGA_MANUAL_TRIG >+#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 >+#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L >+//OTG5_OTG_TRIGB_CNTL >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L >+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L >+//OTG5_OTG_TRIGB_MANUAL_TRIG >+#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 >+#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L >+//OTG5_OTG_FORCE_COUNT_NOW_CNTL >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L >+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L >+//OTG5_OTG_FLOW_CONTROL >+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 >+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 >+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 >+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 >+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL >+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L >+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L >+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L >+//OTG5_OTG_STEREO_FORCE_NEXT_EYE >+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 >+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 >+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 >+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L >+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L >+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L >+//OTG5_OTG_CONTROL >+#define OTG5_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 >+#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc >+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd >+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe >+#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 >+#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 >+#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e >+#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f >+#define OTG5_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L >+#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L >+#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L >+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L >+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L >+#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L >+#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L >+#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L >+#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L >+//OTG5_OTG_BLANK_CONTROL >+#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 >+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 >+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 >+#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L >+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L >+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L >+//OTG5_OTG_PIPE_ABORT_CONTROL >+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 >+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 >+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L >+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L >+//OTG5_OTG_INTERLACE_CONTROL >+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 >+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 >+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L >+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L >+//OTG5_OTG_INTERLACE_STATUS >+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 >+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 >+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L >+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L >+//OTG5_OTG_PIXEL_DATA_READBACK0 >+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 >+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 >+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL >+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L >+//OTG5_OTG_PIXEL_DATA_READBACK1 >+#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 >+#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL >+//OTG5_OTG_STATUS >+#define OTG5_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 >+#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 >+#define OTG5_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 >+#define OTG5_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 >+#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 >+#define OTG5_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 >+#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 >+#define OTG5_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 >+#define OTG5_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L >+#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L >+#define OTG5_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L >+#define OTG5_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L >+#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L >+#define OTG5_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L >+#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L >+#define OTG5_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L >+//OTG5_OTG_STATUS_POSITION >+#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 >+#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 >+#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL >+#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG5_OTG_NOM_VERT_POSITION >+#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 >+#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL >+//OTG5_OTG_STATUS_FRAME_COUNT >+#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 >+#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG5_OTG_STATUS_VF_COUNT >+#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 >+#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL >+//OTG5_OTG_STATUS_HV_COUNT >+#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 >+#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL >+//OTG5_OTG_COUNT_CONTROL >+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 >+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 >+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L >+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL >+//OTG5_OTG_COUNT_RESET >+#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 >+#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L >+//OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE >+#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 >+#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L >+//OTG5_OTG_VERT_SYNC_CONTROL >+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 >+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 >+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 >+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L >+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L >+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L >+//OTG5_OTG_STEREO_STATUS >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 >+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e >+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L >+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L >+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L >+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L >+//OTG5_OTG_STEREO_CONTROL >+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 >+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf >+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 >+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 >+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 >+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 >+#define OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 >+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 >+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL >+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L >+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L >+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L >+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L >+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L >+#define OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L >+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L >+//OTG5_OTG_SNAPSHOT_STATUS >+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 >+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 >+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 >+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L >+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L >+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L >+//OTG5_OTG_SNAPSHOT_CONTROL >+#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 >+#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L >+//OTG5_OTG_SNAPSHOT_POSITION >+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 >+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 >+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL >+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L >+//OTG5_OTG_SNAPSHOT_FRAME >+#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 >+#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL >+//OTG5_OTG_INTERRUPT_CONTROL >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L >+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L >+//OTG5_OTG_UPDATE_LOCK >+#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 >+#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L >+//OTG5_OTG_DOUBLE_BUFFER_CONTROL >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L >+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L >+//OTG5_OTG_MASTER_EN >+#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 >+#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L >+//OTG5_OTG_BLANK_DATA_COLOR >+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 >+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa >+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 >+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL >+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L >+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L >+//OTG5_OTG_BLANK_DATA_COLOR_EXT >+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 >+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 >+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 >+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL >+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L >+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L >+//OTG5_OTG_BLACK_COLOR >+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 >+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa >+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 >+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL >+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L >+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L >+//OTG5_OTG_BLACK_COLOR_EXT >+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 >+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 >+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 >+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL >+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L >+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L >+//OTG5_OTG_VERTICAL_INTERRUPT0_POSITION >+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 >+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 >+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL >+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L >+//OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L >+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L >+//OTG5_OTG_VERTICAL_INTERRUPT1_POSITION >+#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 >+#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL >+//OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L >+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L >+//OTG5_OTG_VERTICAL_INTERRUPT2_POSITION >+#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 >+#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL >+//OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L >+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L >+//OTG5_OTG_CRC_CNTL >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 >+#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 >+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c >+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d >+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e >+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L >+#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L >+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L >+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L >+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L >+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L >+//OTG5_OTG_CRC_CNTL2 >+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 >+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 >+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 >+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 >+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L >+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L >+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L >+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L >+//OTG5_OTG_CRC0_WINDOWA_X_CONTROL >+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 >+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 >+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG5_OTG_CRC0_WINDOWA_Y_CONTROL >+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG5_OTG_CRC0_WINDOWB_X_CONTROL >+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 >+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 >+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG5_OTG_CRC0_WINDOWB_Y_CONTROL >+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG5_OTG_CRC0_DATA_RG >+#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 >+#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 >+#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L >+//OTG5_OTG_CRC0_DATA_B >+#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 >+#define OTG5_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 >+#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L >+//OTG5_OTG_CRC1_WINDOWA_X_CONTROL >+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 >+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 >+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL >+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L >+//OTG5_OTG_CRC1_WINDOWA_Y_CONTROL >+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 >+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 >+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL >+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L >+//OTG5_OTG_CRC1_WINDOWB_X_CONTROL >+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 >+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 >+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL >+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L >+//OTG5_OTG_CRC1_WINDOWB_Y_CONTROL >+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 >+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 >+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL >+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L >+//OTG5_OTG_CRC1_DATA_RG >+#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 >+#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 >+#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L >+//OTG5_OTG_CRC1_DATA_B >+#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 >+#define OTG5_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 >+#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L >+//OTG5_OTG_CRC2_DATA_RG >+#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 >+#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 >+#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L >+//OTG5_OTG_CRC2_DATA_B >+#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 >+#define OTG5_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 >+#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L >+//OTG5_OTG_CRC3_DATA_RG >+#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 >+#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 >+#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L >+//OTG5_OTG_CRC3_DATA_B >+#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 >+#define OTG5_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 >+#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L >+//OTG5_OTG_CRC_SIG_RED_GREEN_MASK >+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 >+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 >+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L >+//OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK >+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 >+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 >+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL >+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L >+//OTG5_OTG_STATIC_SCREEN_CONTROL >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L >+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L >+//OTG5_OTG_3D_STRUCTURE_CONTROL >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L >+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L >+//OTG5_OTG_GSL_VSYNC_GAP >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L >+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L >+//OTG5_OTG_MASTER_UPDATE_MODE >+#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 >+#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L >+//OTG5_OTG_CLOCK_CONTROL >+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 >+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 >+#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 >+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 >+#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 >+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L >+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L >+#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L >+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L >+#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L >+//OTG5_OTG_VSTARTUP_PARAM >+#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 >+#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL >+//OTG5_OTG_VUPDATE_PARAM >+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 >+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 >+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL >+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L >+//OTG5_OTG_VREADY_PARAM >+#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 >+#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL >+//OTG5_OTG_GLOBAL_SYNC_STATUS >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L >+#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L >+//OTG5_OTG_MASTER_UPDATE_LOCK >+#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 >+#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 >+#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L >+#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L >+//OTG5_OTG_GSL_CONTROL >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c >+#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L >+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L >+#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L >+//OTG5_OTG_GSL_WINDOW_X >+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 >+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 >+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL >+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L >+//OTG5_OTG_GSL_WINDOW_Y >+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 >+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 >+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL >+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L >+//OTG5_OTG_VUPDATE_KEEPOUT >+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 >+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 >+#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f >+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL >+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L >+#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L >+//OTG5_OTG_GLOBAL_CONTROL0 >+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 >+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 >+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 >+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL >+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L >+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L >+//OTG5_OTG_GLOBAL_CONTROL1 >+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 >+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 >+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f >+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL >+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L >+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L >+//OTG5_OTG_GLOBAL_CONTROL2 >+#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 >+#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa >+#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 >+#define OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d >+#define OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e >+#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f >+#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL >+#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L >+#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L >+#define OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L >+#define OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L >+#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L >+//OTG5_OTG_GLOBAL_CONTROL3 >+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 >+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 >+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 >+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L >+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L >+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L >+//OTG5_OTG_TRIG_MANUAL_CONTROL >+#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 >+#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L >+//OTG5_OTG_MANUAL_FLOW_CONTROL >+#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 >+#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L >+//OTG5_OTG_RANGE_TIMING_INT_STATUS >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L >+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L >+//OTG5_OTG_DRR_CONTROL >+#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 >+#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 >+#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L >+#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L >+//OTG5_OTG_REQUEST_CONTROL >+#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 >+#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L >+//OTG5_OTG_DSC_START_POSITION >+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 >+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 >+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL >+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L >+//OTG5_OTG_PIPE_UPDATE_STATUS >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L >+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L >+//OTG5_OTG_SPARE_REGISTER >+#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 >+#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_optc_optc_misc_dispdec >+//DWB_SOURCE_SELECT >+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT 0x0 >+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT 0x3 >+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT 0x6 >+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK 0x00000007L >+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK 0x00000038L >+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK 0x000001C0L >+//GSL_SOURCE_SELECT >+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 >+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 >+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 >+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 >+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L >+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L >+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L >+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L >+//OPTC_CLOCK_CONTROL >+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 >+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 >+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 >+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L >+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L >+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L >+//ODM_MEM_PWR_CTRL >+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0 >+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2 >+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4 >+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6 >+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8 >+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa >+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc >+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe >+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT 0x10 >+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT 0x12 >+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT 0x14 >+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT 0x16 >+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT 0x18 >+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT 0x1a >+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT 0x1c >+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT 0x1e >+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L >+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L >+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L >+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L >+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L >+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L >+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK 0x00030000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK 0x00040000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK 0x00300000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK 0x00400000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK 0x03000000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK 0x04000000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK 0x30000000L >+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK 0x40000000L >+//ODM_MEM_PWR_CTRL2 >+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE__SHIFT 0x0 >+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS__SHIFT 0x2 >+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE__SHIFT 0x4 >+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS__SHIFT 0x6 >+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE__SHIFT 0x8 >+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS__SHIFT 0xa >+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE__SHIFT 0xc >+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS__SHIFT 0xe >+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE_MASK 0x00000003L >+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS_MASK 0x00000004L >+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE_MASK 0x00000030L >+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS_MASK 0x00000040L >+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE_MASK 0x00000300L >+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS_MASK 0x00000400L >+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE_MASK 0x00003000L >+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS_MASK 0x00004000L >+//ODM_MEM_PWR_CTRL3 >+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0 >+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2 >+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L >+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL >+//ODM_MEM_PWR_STATUS >+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0 >+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2 >+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4 >+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6 >+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT 0x8 >+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT 0xa >+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT 0xc >+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT 0xe >+#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE__SHIFT 0x10 >+#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE__SHIFT 0x12 >+#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE__SHIFT 0x14 >+#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE__SHIFT 0x16 >+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L >+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL >+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L >+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L >+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK 0x00000300L >+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK 0x00000C00L >+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK 0x00003000L >+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK 0x0000C000L >+#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE_MASK 0x00030000L >+#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE_MASK 0x000C0000L >+#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE_MASK 0x00300000L >+#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE_MASK 0x00C00000L >+//OPTC_MISC_SPARE_REGISTER >+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 >+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL >+ >+ >+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON17_PERFCOUNTER_CNTL >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON17_PERFCOUNTER_CNTL2 >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON17_PERFCOUNTER_STATE >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON17_PERFMON_CNTL >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON17_PERFMON_CNTL2 >+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON17_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON17_PERFMON_CVALUE_LOW >+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON17_PERFMON_HI >+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON17_PERFMON_LOW >+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dio_dout_i2c_dispdec >+//DC_I2C_CONTROL >+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 >+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 >+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 >+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 >+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 >+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 >+#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L >+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L >+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L >+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L >+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L >+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L >+//DC_I2C_ARBITRATION >+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 >+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 >+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 >+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 >+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc >+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 >+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 >+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 >+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 >+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L >+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL >+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L >+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L >+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L >+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L >+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L >+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L >+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L >+//DC_I2C_INTERRUPT_CONTROL >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L >+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L >+//DC_I2C_SW_STATUS >+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 >+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 >+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 >+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 >+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 >+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 >+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 >+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc >+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd >+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe >+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf >+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 >+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L >+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L >+//DC_I2C_DDC1_HW_STATUS >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L >+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L >+//DC_I2C_DDC2_HW_STATUS >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L >+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L >+//DC_I2C_DDC3_HW_STATUS >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L >+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L >+//DC_I2C_DDC4_HW_STATUS >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L >+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L >+//DC_I2C_DDC5_HW_STATUS >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L >+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L >+//DC_I2C_DDC1_SPEED >+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 >+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 >+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 >+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 >+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L >+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L >+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L >+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L >+//DC_I2C_DDC1_SETUP >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L >+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L >+//DC_I2C_DDC2_SPEED >+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 >+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 >+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 >+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 >+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L >+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L >+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L >+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L >+//DC_I2C_DDC2_SETUP >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L >+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L >+//DC_I2C_DDC3_SPEED >+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 >+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 >+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 >+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 >+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L >+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L >+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L >+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L >+//DC_I2C_DDC3_SETUP >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT 0x2 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK 0x00000004L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L >+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L >+//DC_I2C_DDC4_SPEED >+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 >+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 >+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 >+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 >+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L >+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L >+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L >+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L >+//DC_I2C_DDC4_SETUP >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT 0x2 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK 0x00000004L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L >+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L >+//DC_I2C_DDC5_SPEED >+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 >+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 >+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 >+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 >+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L >+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L >+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L >+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L >+//DC_I2C_DDC5_SETUP >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT 0x2 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK 0x00000004L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L >+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L >+//DC_I2C_TRANSACTION0 >+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 >+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 >+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc >+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd >+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 >+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L >+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L >+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L >+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L >+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L >+//DC_I2C_TRANSACTION1 >+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 >+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 >+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc >+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd >+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 >+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L >+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L >+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L >+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L >+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L >+//DC_I2C_TRANSACTION2 >+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 >+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 >+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc >+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd >+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 >+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L >+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L >+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L >+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L >+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L >+//DC_I2C_TRANSACTION3 >+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 >+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 >+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc >+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd >+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 >+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L >+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L >+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L >+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L >+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L >+//DC_I2C_DATA >+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 >+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 >+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 >+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f >+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L >+#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L >+#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L >+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L >+//DC_I2C_EDID_DETECT_CTRL >+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 >+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 >+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c >+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL >+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L >+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L >+//DC_I2C_READ_REQUEST_INTERRUPT >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L >+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L >+ >+ >+//DIG_SOFT_RESET >+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 >+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 >+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 >+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 >+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 >+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 >+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc >+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd >+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 >+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 >+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 >+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 >+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 >+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 >+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L >+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L >+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L >+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L >+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L >+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L >+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L >+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L >+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L >+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L >+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L >+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L >+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L >+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L >+//DIO_MEM_PWR_STATUS1 >+#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE__SHIFT 0x0 >+#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE__SHIFT 0x2 >+#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE__SHIFT 0x4 >+#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE__SHIFT 0x6 >+#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE__SHIFT 0x8 >+#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE__SHIFT 0xa >+#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE__SHIFT 0x10 >+#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE__SHIFT 0x12 >+#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE__SHIFT 0x14 >+#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE__SHIFT 0x16 >+#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE__SHIFT 0x18 >+#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE__SHIFT 0x1a >+#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE_MASK 0x00000001L >+#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE_MASK 0x00000004L >+#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE_MASK 0x00000010L >+#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE_MASK 0x00000040L >+#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE_MASK 0x00000100L >+#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE_MASK 0x00000400L >+#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE_MASK 0x00030000L >+#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE_MASK 0x000C0000L >+#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE_MASK 0x00300000L >+#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE_MASK 0x00C00000L >+#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE_MASK 0x03000000L >+#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE_MASK 0x0C000000L >+//DIO_CLK_CNTL2 >+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0 >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd >+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 >+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 >+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 >+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 >+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 >+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 >+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 >+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L >+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L >+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L >+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L >+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L >+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L >+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L >+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L >+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L >+//DIO_CLK_CNTL3 >+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 >+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 >+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 >+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 >+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 >+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 >+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 >+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa >+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb >+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc >+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd >+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe >+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf >+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 >+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L >+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L >+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L >+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L >+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L >+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L >+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L >+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L >+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L >+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L >+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L >+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L >+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L >+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L >+//DIO_HDMI_RXSTATUS_TIMER_CONTROL >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L >+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L >+//DIO_PSP_INTERRUPT_STATUS >+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT 0x0 >+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1 >+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK 0x00000001L >+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL >+//DIO_PSP_INTERRUPT_CLEAR >+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT 0x0 >+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L >+//DIO_GENERIC_INTERRUPT_MESSAGE >+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0 >+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1 >+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L >+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL >+//DIO_GENERIC_INTERRUPT_CLEAR >+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0 >+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_dio_hpd0_dispdec >+//HPD0_DC_HPD_INT_STATUS >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L >+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L >+//HPD0_DC_HPD_INT_CONTROL >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L >+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L >+//HPD0_DC_HPD_CONTROL >+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 >+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 >+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c >+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL >+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L >+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L >+//HPD0_DC_HPD_FAST_TRAIN_CNTL >+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 >+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc >+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 >+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c >+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL >+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L >+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L >+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L >+//HPD0_DC_HPD_TOGGLE_FILT_CNTL >+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 >+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 >+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL >+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L >+ >+ >+// addressBlock: dce_dc_dio_hpd1_dispdec >+//HPD1_DC_HPD_INT_STATUS >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L >+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L >+//HPD1_DC_HPD_INT_CONTROL >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L >+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L >+//HPD1_DC_HPD_CONTROL >+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 >+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 >+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c >+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL >+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L >+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L >+//HPD1_DC_HPD_FAST_TRAIN_CNTL >+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 >+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc >+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 >+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c >+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL >+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L >+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L >+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L >+//HPD1_DC_HPD_TOGGLE_FILT_CNTL >+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 >+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 >+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL >+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L >+ >+ >+// addressBlock: dce_dc_dio_hpd2_dispdec >+//HPD2_DC_HPD_INT_STATUS >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L >+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L >+//HPD2_DC_HPD_INT_CONTROL >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L >+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L >+//HPD2_DC_HPD_CONTROL >+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 >+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 >+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c >+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL >+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L >+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L >+//HPD2_DC_HPD_FAST_TRAIN_CNTL >+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 >+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc >+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 >+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c >+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL >+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L >+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L >+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L >+//HPD2_DC_HPD_TOGGLE_FILT_CNTL >+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 >+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 >+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL >+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L >+ >+ >+// addressBlock: dce_dc_dio_hpd3_dispdec >+//HPD3_DC_HPD_INT_STATUS >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L >+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L >+//HPD3_DC_HPD_INT_CONTROL >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L >+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L >+//HPD3_DC_HPD_CONTROL >+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 >+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 >+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c >+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL >+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L >+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L >+//HPD3_DC_HPD_FAST_TRAIN_CNTL >+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 >+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc >+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 >+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c >+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL >+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L >+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L >+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L >+//HPD3_DC_HPD_TOGGLE_FILT_CNTL >+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 >+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 >+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL >+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L >+ >+ >+// addressBlock: dce_dc_dio_hpd4_dispdec >+//HPD4_DC_HPD_INT_STATUS >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L >+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L >+//HPD4_DC_HPD_INT_CONTROL >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L >+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L >+//HPD4_DC_HPD_CONTROL >+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 >+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 >+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c >+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL >+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L >+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L >+//HPD4_DC_HPD_FAST_TRAIN_CNTL >+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 >+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc >+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 >+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c >+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL >+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L >+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L >+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L >+//HPD4_DC_HPD_TOGGLE_FILT_CNTL >+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 >+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 >+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL >+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L >+ >+ >+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON18_PERFCOUNTER_CNTL >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON18_PERFCOUNTER_CNTL2 >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON18_PERFCOUNTER_STATE >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON18_PERFMON_CNTL >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON18_PERFMON_CNTL2 >+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON18_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON18_PERFMON_CVALUE_LOW >+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON18_PERFMON_HI >+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON18_PERFMON_LOW >+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dio_dp_aux0_dispdec >+//DP_AUX0_AUX_CONTROL >+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 >+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 >+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 >+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 >+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc >+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 >+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 >+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 >+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 >+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c >+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d >+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e >+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f >+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L >+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L >+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L >+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L >+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L >+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L >+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L >+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L >+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L >+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L >+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L >+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L >+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L >+//DP_AUX0_AUX_SW_CONTROL >+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 >+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 >+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 >+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 >+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L >+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L >+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L >+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L >+//DP_AUX0_AUX_ARB_CONTROL >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L >+//DP_AUX0_AUX_INTERRUPT_CONTROL >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L >+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L >+//DP_AUX0_AUX_SW_STATUS >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L >+//DP_AUX0_AUX_LS_STATUS >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L >+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L >+//DP_AUX0_AUX_SW_DATA >+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 >+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 >+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 >+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f >+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L >+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L >+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L >+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L >+//DP_AUX0_AUX_LS_DATA >+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 >+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 >+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L >+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L >+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL >+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 >+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 >+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 >+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L >+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L >+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L >+//DP_AUX0_AUX_DPHY_TX_CONTROL >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L >+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L >+//DP_AUX0_AUX_DPHY_RX_CONTROL0 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L >+//DP_AUX0_AUX_DPHY_RX_CONTROL1 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 >+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf >+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL >+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L >+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L >+//DP_AUX0_AUX_DPHY_TX_STATUS >+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 >+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 >+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 >+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L >+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L >+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L >+//DP_AUX0_AUX_DPHY_RX_STATUS >+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 >+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 >+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 >+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 >+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L >+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L >+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L >+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L >+//DP_AUX0_AUX_GTC_SYNC_CONTROL >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L >+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL >+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 >+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 >+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 >+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 >+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL >+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L >+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L >+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L >+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L >+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L >+//DP_AUX0_AUX_GTC_SYNC_STATUS >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L >+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L >+//DP_AUX0_AUX_PHY_WAKE_CNTL >+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 >+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 >+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 >+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 >+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L >+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L >+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L >+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L >+ >+ >+// addressBlock: dce_dc_dio_dp_aux1_dispdec >+//DP_AUX1_AUX_CONTROL >+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 >+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 >+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 >+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 >+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc >+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 >+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 >+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 >+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 >+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c >+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d >+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e >+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f >+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L >+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L >+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L >+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L >+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L >+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L >+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L >+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L >+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L >+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L >+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L >+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L >+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L >+//DP_AUX1_AUX_SW_CONTROL >+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 >+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 >+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 >+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 >+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L >+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L >+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L >+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L >+//DP_AUX1_AUX_ARB_CONTROL >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L >+//DP_AUX1_AUX_INTERRUPT_CONTROL >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L >+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L >+//DP_AUX1_AUX_SW_STATUS >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L >+//DP_AUX1_AUX_LS_STATUS >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L >+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L >+//DP_AUX1_AUX_SW_DATA >+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 >+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 >+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 >+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f >+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L >+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L >+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L >+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L >+//DP_AUX1_AUX_LS_DATA >+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 >+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 >+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L >+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L >+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL >+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 >+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 >+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 >+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L >+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L >+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L >+//DP_AUX1_AUX_DPHY_TX_CONTROL >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L >+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L >+//DP_AUX1_AUX_DPHY_RX_CONTROL0 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L >+//DP_AUX1_AUX_DPHY_RX_CONTROL1 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 >+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf >+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL >+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L >+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L >+//DP_AUX1_AUX_DPHY_TX_STATUS >+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 >+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 >+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 >+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L >+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L >+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L >+//DP_AUX1_AUX_DPHY_RX_STATUS >+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 >+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 >+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 >+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 >+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L >+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L >+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L >+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L >+//DP_AUX1_AUX_GTC_SYNC_CONTROL >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L >+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL >+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 >+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 >+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 >+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 >+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL >+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L >+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L >+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L >+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L >+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L >+//DP_AUX1_AUX_GTC_SYNC_STATUS >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L >+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L >+//DP_AUX1_AUX_PHY_WAKE_CNTL >+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 >+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 >+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 >+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 >+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L >+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L >+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L >+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L >+ >+ >+// addressBlock: dce_dc_dio_dp_aux2_dispdec >+//DP_AUX2_AUX_CONTROL >+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 >+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 >+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 >+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 >+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc >+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 >+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 >+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 >+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 >+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c >+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d >+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e >+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f >+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L >+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L >+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L >+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L >+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L >+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L >+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L >+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L >+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L >+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L >+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L >+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L >+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L >+//DP_AUX2_AUX_SW_CONTROL >+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 >+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 >+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 >+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 >+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L >+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L >+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L >+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L >+//DP_AUX2_AUX_ARB_CONTROL >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L >+//DP_AUX2_AUX_INTERRUPT_CONTROL >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L >+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L >+//DP_AUX2_AUX_SW_STATUS >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L >+//DP_AUX2_AUX_LS_STATUS >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L >+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L >+//DP_AUX2_AUX_SW_DATA >+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 >+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 >+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 >+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f >+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L >+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L >+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L >+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L >+//DP_AUX2_AUX_LS_DATA >+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 >+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 >+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L >+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L >+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL >+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 >+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 >+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 >+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L >+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L >+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L >+//DP_AUX2_AUX_DPHY_TX_CONTROL >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L >+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L >+//DP_AUX2_AUX_DPHY_RX_CONTROL0 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L >+//DP_AUX2_AUX_DPHY_RX_CONTROL1 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 >+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf >+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL >+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L >+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L >+//DP_AUX2_AUX_DPHY_TX_STATUS >+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 >+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 >+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 >+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L >+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L >+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L >+//DP_AUX2_AUX_DPHY_RX_STATUS >+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 >+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 >+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 >+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 >+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L >+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L >+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L >+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L >+//DP_AUX2_AUX_GTC_SYNC_CONTROL >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L >+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL >+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 >+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 >+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 >+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 >+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL >+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L >+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L >+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L >+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L >+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L >+//DP_AUX2_AUX_GTC_SYNC_STATUS >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L >+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L >+//DP_AUX2_AUX_PHY_WAKE_CNTL >+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 >+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 >+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 >+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 >+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L >+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L >+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L >+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L >+ >+ >+// addressBlock: dce_dc_dio_dp_aux3_dispdec >+//DP_AUX3_AUX_CONTROL >+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 >+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 >+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 >+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 >+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc >+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 >+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 >+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 >+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 >+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c >+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d >+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e >+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f >+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L >+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L >+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L >+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L >+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L >+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L >+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L >+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L >+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L >+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L >+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L >+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L >+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L >+//DP_AUX3_AUX_SW_CONTROL >+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 >+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 >+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 >+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 >+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L >+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L >+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L >+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L >+//DP_AUX3_AUX_ARB_CONTROL >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L >+//DP_AUX3_AUX_INTERRUPT_CONTROL >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L >+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L >+//DP_AUX3_AUX_SW_STATUS >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L >+//DP_AUX3_AUX_LS_STATUS >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L >+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L >+//DP_AUX3_AUX_SW_DATA >+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 >+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 >+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 >+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f >+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L >+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L >+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L >+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L >+//DP_AUX3_AUX_LS_DATA >+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 >+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 >+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L >+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L >+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL >+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 >+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 >+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 >+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L >+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L >+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L >+//DP_AUX3_AUX_DPHY_TX_CONTROL >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L >+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L >+//DP_AUX3_AUX_DPHY_RX_CONTROL0 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L >+//DP_AUX3_AUX_DPHY_RX_CONTROL1 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 >+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf >+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL >+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L >+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L >+//DP_AUX3_AUX_DPHY_TX_STATUS >+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 >+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 >+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 >+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L >+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L >+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L >+//DP_AUX3_AUX_DPHY_RX_STATUS >+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 >+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 >+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 >+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 >+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L >+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L >+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L >+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L >+//DP_AUX3_AUX_GTC_SYNC_CONTROL >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L >+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL >+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 >+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 >+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 >+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 >+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL >+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L >+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L >+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L >+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L >+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L >+//DP_AUX3_AUX_GTC_SYNC_STATUS >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L >+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L >+//DP_AUX3_AUX_PHY_WAKE_CNTL >+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 >+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 >+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 >+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 >+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L >+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L >+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L >+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L >+ >+ >+// addressBlock: dce_dc_dio_dp_aux4_dispdec >+//DP_AUX4_AUX_CONTROL >+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 >+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 >+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 >+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 >+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc >+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 >+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 >+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 >+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 >+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c >+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d >+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e >+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f >+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L >+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L >+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L >+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L >+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L >+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L >+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L >+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L >+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L >+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L >+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L >+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L >+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L >+//DP_AUX4_AUX_SW_CONTROL >+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 >+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 >+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 >+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 >+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L >+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L >+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L >+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L >+//DP_AUX4_AUX_ARB_CONTROL >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L >+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L >+//DP_AUX4_AUX_INTERRUPT_CONTROL >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L >+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L >+//DP_AUX4_AUX_SW_STATUS >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L >+//DP_AUX4_AUX_LS_STATUS >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L >+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L >+//DP_AUX4_AUX_SW_DATA >+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 >+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 >+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 >+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f >+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L >+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L >+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L >+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L >+//DP_AUX4_AUX_LS_DATA >+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 >+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 >+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L >+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L >+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL >+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 >+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 >+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 >+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L >+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L >+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L >+//DP_AUX4_AUX_DPHY_TX_CONTROL >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L >+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L >+//DP_AUX4_AUX_DPHY_RX_CONTROL0 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L >+//DP_AUX4_AUX_DPHY_RX_CONTROL1 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 >+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf >+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL >+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L >+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L >+//DP_AUX4_AUX_DPHY_TX_STATUS >+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 >+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 >+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 >+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L >+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L >+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L >+//DP_AUX4_AUX_DPHY_RX_STATUS >+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 >+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 >+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 >+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 >+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L >+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L >+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L >+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L >+//DP_AUX4_AUX_GTC_SYNC_CONTROL >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L >+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL >+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 >+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 >+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 >+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 >+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL >+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L >+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L >+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L >+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L >+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L >+//DP_AUX4_AUX_GTC_SYNC_STATUS >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L >+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L >+//DP_AUX4_AUX_PHY_WAKE_CNTL >+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 >+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 >+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 >+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 >+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L >+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L >+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L >+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L >+ >+ >+// addressBlock: dce_dc_dio_dig0_dispdec >+//DIG0_DIG_FE_CNTL >+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 >+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 >+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 >+#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa >+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc >+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 >+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 >+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 >+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 >+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c >+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e >+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L >+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L >+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L >+#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L >+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L >+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L >+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L >+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L >+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L >+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L >+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L >+//DIG0_DIG_OUTPUT_CRC_CNTL >+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 >+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 >+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 >+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L >+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L >+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L >+//DIG0_DIG_OUTPUT_CRC_RESULT >+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 >+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL >+//DIG0_DIG_CLOCK_PATTERN >+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 >+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL >+//DIG0_DIG_TEST_PATTERN >+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 >+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 >+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 >+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 >+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 >+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 >+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L >+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L >+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L >+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L >+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L >+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L >+//DIG0_DIG_RANDOM_PATTERN_SEED >+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 >+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 >+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL >+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L >+//DIG0_DIG_FIFO_STATUS >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L >+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L >+//DIG0_HDMI_METADATA_PACKET_CONTROL >+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 >+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 >+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L >+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L >+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DIG0_HDMI_GENERIC_PACKET_CONTROL4 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L >+//DIG0_HDMI_CONTROL >+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 >+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 >+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 >+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 >+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 >+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 >+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 >+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 >+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 >+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c >+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L >+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L >+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L >+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L >+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L >+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L >+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L >+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L >+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L >+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L >+//DIG0_HDMI_STATUS >+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 >+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 >+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 >+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b >+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L >+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L >+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L >+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L >+//DIG0_HDMI_AUDIO_PACKET_CONTROL >+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 >+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 >+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 >+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L >+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L >+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L >+//DIG0_HDMI_ACR_PACKET_CONTROL >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L >+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L >+//DIG0_HDMI_VBI_PACKET_CONTROL >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L >+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L >+//DIG0_HDMI_INFOFRAME_CONTROL0 >+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 >+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 >+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 >+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 >+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L >+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L >+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L >+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L >+//DIG0_HDMI_INFOFRAME_CONTROL1 >+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 >+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 >+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L >+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L >+//DIG0_HDMI_GENERIC_PACKET_CONTROL0 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L >+//DIG0_HDMI_GC >+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 >+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 >+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 >+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 >+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc >+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L >+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L >+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L >+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L >+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L >+//DIG0_AFMT_AUDIO_PACKET_CONTROL2 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L >+//DIG0_AFMT_ISRC1_0 >+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 >+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 >+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 >+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L >+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L >+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L >+//DIG0_AFMT_ISRC1_1 >+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 >+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 >+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 >+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 >+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL >+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L >+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L >+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L >+//DIG0_AFMT_ISRC1_2 >+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 >+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 >+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 >+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 >+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL >+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L >+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L >+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L >+//DIG0_AFMT_ISRC1_3 >+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 >+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 >+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 >+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 >+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL >+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L >+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L >+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L >+//DIG0_AFMT_ISRC1_4 >+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 >+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 >+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 >+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 >+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL >+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L >+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L >+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L >+//DIG0_AFMT_ISRC2_0 >+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 >+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 >+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 >+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 >+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL >+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L >+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L >+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L >+//DIG0_AFMT_ISRC2_1 >+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 >+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 >+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 >+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 >+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL >+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L >+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L >+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L >+//DIG0_AFMT_ISRC2_2 >+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 >+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 >+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 >+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 >+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL >+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L >+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L >+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L >+//DIG0_AFMT_ISRC2_3 >+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 >+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 >+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 >+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 >+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL >+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L >+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L >+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L >+//DIG0_HDMI_GENERIC_PACKET_CONTROL2 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L >+//DIG0_HDMI_GENERIC_PACKET_CONTROL3 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L >+//DIG0_HDMI_DB_CONTROL >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc >+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf >+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L >+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L >+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DIG0_DME_CONTROL >+#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 >+#define DIG0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 >+#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 >+#define DIG0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc >+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd >+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 >+#define DIG0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 >+#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L >+#define DIG0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L >+#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L >+#define DIG0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L >+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L >+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L >+#define DIG0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L >+//DIG0_AFMT_MPEG_INFO0 >+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 >+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 >+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 >+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L >+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L >+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L >+//DIG0_AFMT_MPEG_INFO1 >+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 >+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 >+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc >+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL >+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L >+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L >+//DIG0_AFMT_GENERIC_HDR >+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L >+//DIG0_AFMT_GENERIC_0 >+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L >+//DIG0_AFMT_GENERIC_1 >+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L >+//DIG0_AFMT_GENERIC_2 >+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L >+//DIG0_AFMT_GENERIC_3 >+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L >+//DIG0_AFMT_GENERIC_4 >+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L >+//DIG0_AFMT_GENERIC_5 >+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L >+//DIG0_AFMT_GENERIC_6 >+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L >+//DIG0_AFMT_GENERIC_7 >+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 >+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 >+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 >+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 >+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL >+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L >+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L >+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L >+//DIG0_HDMI_GENERIC_PACKET_CONTROL1 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L >+//DIG0_HDMI_ACR_32_0 >+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc >+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L >+//DIG0_HDMI_ACR_32_1 >+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 >+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL >+//DIG0_HDMI_ACR_44_0 >+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc >+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L >+//DIG0_HDMI_ACR_44_1 >+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 >+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL >+//DIG0_HDMI_ACR_48_0 >+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc >+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L >+//DIG0_HDMI_ACR_48_1 >+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 >+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL >+//DIG0_HDMI_ACR_STATUS_0 >+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc >+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L >+//DIG0_HDMI_ACR_STATUS_1 >+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 >+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL >+//DIG0_AFMT_AUDIO_INFO0 >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L >+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L >+//DIG0_AFMT_AUDIO_INFO1 >+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 >+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb >+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf >+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 >+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL >+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L >+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L >+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L >+//DIG0_AFMT_60958_0 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L >+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L >+//DIG0_AFMT_60958_1 >+#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 >+#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 >+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 >+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 >+#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 >+#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL >+#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L >+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L >+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L >+#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L >+//DIG0_AFMT_AUDIO_CRC_CONTROL >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L >+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L >+//DIG0_AFMT_RAMP_CONTROL0 >+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 >+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f >+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL >+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L >+//DIG0_AFMT_RAMP_CONTROL1 >+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 >+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 >+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL >+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L >+//DIG0_AFMT_RAMP_CONTROL2 >+#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 >+#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL >+//DIG0_AFMT_RAMP_CONTROL3 >+#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 >+#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL >+//DIG0_AFMT_60958_2 >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L >+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L >+//DIG0_AFMT_AUDIO_CRC_RESULT >+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 >+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 >+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L >+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L >+//DIG0_AFMT_STATUS >+#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 >+#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 >+#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 >+#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e >+#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L >+#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L >+#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L >+#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L >+//DIG0_AFMT_AUDIO_PACKET_CONTROL >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L >+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L >+//DIG0_AFMT_VBI_PACKET_CONTROL >+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 >+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 >+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 >+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c >+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L >+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L >+//DIG0_AFMT_INFOFRAME_CONTROL0 >+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 >+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 >+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa >+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L >+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L >+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L >+//DIG0_AFMT_AUDIO_SRC_CONTROL >+#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 >+#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L >+//DIG0_DIG_BE_CNTL >+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 >+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 >+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 >+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 >+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 >+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c >+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L >+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L >+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L >+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L >+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L >+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L >+//DIG0_DIG_BE_EN_CNTL >+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 >+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 >+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L >+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L >+//DIG0_TMDS_CNTL >+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 >+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L >+//DIG0_TMDS_CONTROL_CHAR >+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 >+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 >+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 >+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 >+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L >+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L >+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L >+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L >+//DIG0_TMDS_CONTROL0_FEEDBACK >+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 >+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 >+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L >+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L >+//DIG0_TMDS_STEREOSYNC_CTL_SEL >+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 >+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L >+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 >+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 >+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 >+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL >+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L >+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 >+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 >+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 >+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL >+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L >+//DIG0_TMDS_CTL_BITS >+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 >+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 >+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 >+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 >+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L >+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L >+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L >+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L >+//DIG0_TMDS_DCBALANCER_CONTROL >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L >+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L >+//DIG0_TMDS_SYNC_DCBALANCE_CHAR >+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 >+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 >+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL >+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L >+//DIG0_TMDS_CTL0_1_GEN_CNTL >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L >+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L >+//DIG0_TMDS_CTL2_3_GEN_CNTL >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L >+//DIG0_DIG_VERSION >+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 >+#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L >+//DIG0_DIG_LANE_ENABLE >+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 >+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 >+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 >+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 >+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 >+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L >+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L >+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L >+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L >+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L >+//DIG0_AFMT_CNTL >+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 >+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 >+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L >+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L >+//DIG0_AFMT_VBI_PACKET_CONTROL1 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L >+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L >+//DIG0_HDMI_GENERIC_PACKET_CONTROL5 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L >+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L >+//DIG0_FORCE_DIG_DISABLE >+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 >+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_dio_dp0_dispdec >+//DP0_DP_LINK_CNTL >+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 >+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 >+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 >+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L >+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L >+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L >+//DP0_DP_PIXEL_FORMAT >+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 >+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 >+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c >+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L >+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L >+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L >+//DP0_DP_MSA_COLORIMETRY >+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 >+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L >+//DP0_DP_CONFIG >+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 >+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L >+//DP0_DP_VID_STREAM_CNTL >+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 >+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 >+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 >+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 >+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L >+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L >+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L >+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L >+//DP0_DP_STEER_FIFO >+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 >+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 >+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 >+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 >+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 >+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 >+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc >+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L >+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L >+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L >+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L >+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L >+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L >+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L >+//DP0_DP_MSA_MISC >+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 >+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 >+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 >+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 >+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL >+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L >+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L >+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L >+//DP0_DP_VID_TIMING >+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 >+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 >+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa >+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc >+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 >+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L >+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L >+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L >+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L >+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L >+//DP0_DP_VID_N >+#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 >+#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL >+//DP0_DP_VID_M >+#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 >+#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL >+//DP0_DP_LINK_FRAMING_CNTL >+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 >+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 >+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c >+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL >+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L >+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L >+//DP0_DP_HBR2_EYE_PATTERN >+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 >+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L >+//DP0_DP_VID_MSA_VBID >+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 >+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 >+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL >+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L >+//DP0_DP_VID_INTERRUPT_CNTL >+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 >+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 >+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 >+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L >+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L >+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L >+//DP0_DP_DPHY_CNTL >+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 >+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 >+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 >+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 >+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 >+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 >+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 >+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 >+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 >+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L >+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L >+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L >+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L >+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L >+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L >+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L >+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L >+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L >+//DP0_DP_DPHY_TRAINING_PATTERN_SEL >+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 >+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L >+//DP0_DP_DPHY_SYM0 >+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 >+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa >+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 >+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL >+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L >+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L >+//DP0_DP_DPHY_SYM1 >+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 >+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa >+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 >+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL >+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L >+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L >+//DP0_DP_DPHY_SYM2 >+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 >+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa >+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL >+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L >+//DP0_DP_DPHY_8B10B_CNTL >+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 >+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 >+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 >+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L >+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L >+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L >+//DP0_DP_DPHY_PRBS_CNTL >+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 >+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 >+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 >+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L >+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L >+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L >+//DP0_DP_DPHY_SCRAM_CNTL >+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 >+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 >+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 >+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 >+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L >+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L >+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L >+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L >+//DP0_DP_DPHY_CRC_EN >+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 >+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 >+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 >+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L >+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L >+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L >+//DP0_DP_DPHY_CRC_CNTL >+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 >+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 >+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 >+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L >+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L >+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L >+//DP0_DP_DPHY_CRC_RESULT >+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 >+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 >+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 >+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 >+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL >+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L >+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L >+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L >+//DP0_DP_DPHY_CRC_MST_CNTL >+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 >+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 >+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL >+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L >+//DP0_DP_DPHY_CRC_MST_STATUS >+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 >+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 >+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 >+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L >+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L >+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L >+//DP0_DP_DPHY_FAST_TRAINING >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L >+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L >+//DP0_DP_DPHY_FAST_TRAINING_STATUS >+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 >+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 >+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 >+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc >+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L >+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L >+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L >+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L >+//DP0_DP_SEC_CNTL >+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 >+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 >+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 >+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc >+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b >+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c >+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L >+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L >+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L >+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L >+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L >+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L >+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L >+//DP0_DP_SEC_CNTL1 >+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 >+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L >+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L >+//DP0_DP_SEC_FRAMING1 >+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 >+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL >+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP0_DP_SEC_FRAMING2 >+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 >+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL >+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP0_DP_SEC_FRAMING3 >+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 >+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL >+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP0_DP_SEC_FRAMING4 >+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 >+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 >+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 >+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c >+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d >+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L >+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L >+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L >+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L >+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L >+//DP0_DP_SEC_AUD_N >+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 >+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL >+//DP0_DP_SEC_AUD_N_READBACK >+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 >+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL >+//DP0_DP_SEC_AUD_M >+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 >+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL >+//DP0_DP_SEC_AUD_M_READBACK >+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 >+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL >+//DP0_DP_SEC_TIMESTAMP >+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 >+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L >+//DP0_DP_SEC_PACKET_CNTL >+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 >+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 >+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 >+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 >+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL >+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L >+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L >+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L >+//DP0_DP_MSE_RATE_CNTL >+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 >+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a >+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL >+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L >+//DP0_DP_MSE_RATE_UPDATE >+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 >+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L >+//DP0_DP_MSE_SAT0 >+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 >+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 >+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 >+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 >+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L >+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L >+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L >+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L >+//DP0_DP_MSE_SAT1 >+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 >+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 >+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 >+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 >+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L >+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L >+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L >+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L >+//DP0_DP_MSE_SAT2 >+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 >+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 >+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 >+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 >+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L >+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L >+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L >+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L >+//DP0_DP_MSE_SAT_UPDATE >+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 >+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 >+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L >+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L >+//DP0_DP_MSE_LINK_TIMING >+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 >+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 >+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL >+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L >+//DP0_DP_MSE_MISC_CNTL >+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 >+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 >+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 >+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L >+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L >+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L >+//DP0_DP_DPHY_BS_SR_SWAP_CNTL >+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 >+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf >+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 >+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL >+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L >+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L >+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL >+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 >+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L >+//DP0_DP_MSE_SAT0_STATUS >+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 >+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 >+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 >+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 >+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L >+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L >+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L >+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L >+//DP0_DP_MSE_SAT1_STATUS >+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 >+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 >+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 >+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 >+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L >+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L >+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L >+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L >+//DP0_DP_MSE_SAT2_STATUS >+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 >+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 >+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 >+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 >+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L >+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L >+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L >+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L >+//DP0_DP_MSA_TIMING_PARAM1 >+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 >+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 >+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL >+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L >+//DP0_DP_MSA_TIMING_PARAM2 >+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 >+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 >+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL >+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L >+//DP0_DP_MSA_TIMING_PARAM3 >+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 >+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf >+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 >+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f >+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL >+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L >+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L >+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L >+//DP0_DP_MSA_TIMING_PARAM4 >+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 >+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 >+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL >+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L >+//DP0_DP_MSO_CNTL >+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c >+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L >+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L >+//DP0_DP_MSO_CNTL1 >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L >+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L >+//DP0_DP_DSC_CNTL >+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 >+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L >+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//DP0_DP_SEC_CNTL2 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L >+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L >+//DP0_DP_SEC_CNTL3 >+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 >+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 >+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL >+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L >+//DP0_DP_SEC_CNTL4 >+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 >+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 >+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL >+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L >+//DP0_DP_SEC_CNTL5 >+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 >+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 >+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL >+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L >+//DP0_DP_SEC_CNTL6 >+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 >+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL >+//DP0_DP_SEC_CNTL7 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L >+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L >+//DP0_DP_DB_CNTL >+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 >+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 >+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 >+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 >+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc >+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf >+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L >+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L >+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L >+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L >+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L >+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DP0_DP_MSA_VBID_MISC >+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 >+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 >+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 >+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc >+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd >+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf >+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 >+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L >+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L >+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L >+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L >+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L >+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L >+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L >+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L >+//DP0_DP_SEC_METADATA_TRANSMISSION >+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 >+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 >+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L >+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L >+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DP0_DP_DSC_BYTES_PER_PIXEL >+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//DP0_DP_ALPM_CNTL >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 >+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L >+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L >+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dio_dig1_dispdec >+//DIG1_DIG_FE_CNTL >+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 >+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 >+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 >+#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa >+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc >+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 >+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 >+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 >+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 >+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c >+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e >+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L >+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L >+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L >+#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L >+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L >+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L >+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L >+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L >+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L >+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L >+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L >+//DIG1_DIG_OUTPUT_CRC_CNTL >+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 >+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 >+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 >+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L >+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L >+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L >+//DIG1_DIG_OUTPUT_CRC_RESULT >+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 >+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL >+//DIG1_DIG_CLOCK_PATTERN >+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 >+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL >+//DIG1_DIG_TEST_PATTERN >+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 >+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 >+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 >+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 >+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 >+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 >+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L >+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L >+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L >+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L >+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L >+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L >+//DIG1_DIG_RANDOM_PATTERN_SEED >+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 >+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 >+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL >+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L >+//DIG1_DIG_FIFO_STATUS >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L >+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L >+//DIG1_HDMI_METADATA_PACKET_CONTROL >+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 >+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 >+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L >+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L >+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DIG1_HDMI_GENERIC_PACKET_CONTROL4 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L >+//DIG1_HDMI_CONTROL >+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 >+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 >+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 >+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 >+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 >+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 >+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 >+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 >+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 >+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c >+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L >+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L >+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L >+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L >+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L >+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L >+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L >+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L >+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L >+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L >+//DIG1_HDMI_STATUS >+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 >+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 >+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 >+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b >+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L >+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L >+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L >+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L >+//DIG1_HDMI_AUDIO_PACKET_CONTROL >+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 >+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 >+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 >+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L >+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L >+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L >+//DIG1_HDMI_ACR_PACKET_CONTROL >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L >+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L >+//DIG1_HDMI_VBI_PACKET_CONTROL >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L >+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L >+//DIG1_HDMI_INFOFRAME_CONTROL0 >+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 >+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 >+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 >+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 >+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L >+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L >+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L >+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L >+//DIG1_HDMI_INFOFRAME_CONTROL1 >+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 >+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 >+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L >+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L >+//DIG1_HDMI_GENERIC_PACKET_CONTROL0 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L >+//DIG1_HDMI_GC >+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 >+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 >+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 >+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 >+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc >+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L >+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L >+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L >+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L >+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L >+//DIG1_AFMT_AUDIO_PACKET_CONTROL2 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L >+//DIG1_AFMT_ISRC1_0 >+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 >+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 >+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 >+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L >+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L >+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L >+//DIG1_AFMT_ISRC1_1 >+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 >+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 >+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 >+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 >+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL >+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L >+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L >+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L >+//DIG1_AFMT_ISRC1_2 >+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 >+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 >+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 >+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 >+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL >+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L >+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L >+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L >+//DIG1_AFMT_ISRC1_3 >+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 >+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 >+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 >+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 >+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL >+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L >+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L >+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L >+//DIG1_AFMT_ISRC1_4 >+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 >+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 >+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 >+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 >+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL >+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L >+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L >+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L >+//DIG1_AFMT_ISRC2_0 >+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 >+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 >+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 >+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 >+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL >+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L >+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L >+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L >+//DIG1_AFMT_ISRC2_1 >+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 >+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 >+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 >+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 >+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL >+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L >+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L >+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L >+//DIG1_AFMT_ISRC2_2 >+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 >+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 >+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 >+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 >+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL >+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L >+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L >+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L >+//DIG1_AFMT_ISRC2_3 >+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 >+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 >+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 >+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 >+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL >+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L >+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L >+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L >+//DIG1_HDMI_GENERIC_PACKET_CONTROL2 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L >+//DIG1_HDMI_GENERIC_PACKET_CONTROL3 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L >+//DIG1_HDMI_DB_CONTROL >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc >+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf >+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L >+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L >+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DIG1_DME_CONTROL >+#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 >+#define DIG1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 >+#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 >+#define DIG1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc >+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd >+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 >+#define DIG1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 >+#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L >+#define DIG1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L >+#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L >+#define DIG1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L >+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L >+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L >+#define DIG1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L >+//DIG1_AFMT_MPEG_INFO0 >+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 >+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 >+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 >+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L >+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L >+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L >+//DIG1_AFMT_MPEG_INFO1 >+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 >+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 >+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc >+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL >+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L >+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L >+//DIG1_AFMT_GENERIC_HDR >+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L >+//DIG1_AFMT_GENERIC_0 >+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L >+//DIG1_AFMT_GENERIC_1 >+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L >+//DIG1_AFMT_GENERIC_2 >+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L >+//DIG1_AFMT_GENERIC_3 >+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L >+//DIG1_AFMT_GENERIC_4 >+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L >+//DIG1_AFMT_GENERIC_5 >+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L >+//DIG1_AFMT_GENERIC_6 >+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L >+//DIG1_AFMT_GENERIC_7 >+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 >+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 >+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 >+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 >+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL >+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L >+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L >+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L >+//DIG1_HDMI_GENERIC_PACKET_CONTROL1 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L >+//DIG1_HDMI_ACR_32_0 >+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc >+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L >+//DIG1_HDMI_ACR_32_1 >+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 >+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL >+//DIG1_HDMI_ACR_44_0 >+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc >+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L >+//DIG1_HDMI_ACR_44_1 >+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 >+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL >+//DIG1_HDMI_ACR_48_0 >+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc >+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L >+//DIG1_HDMI_ACR_48_1 >+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 >+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL >+//DIG1_HDMI_ACR_STATUS_0 >+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc >+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L >+//DIG1_HDMI_ACR_STATUS_1 >+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 >+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL >+//DIG1_AFMT_AUDIO_INFO0 >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L >+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L >+//DIG1_AFMT_AUDIO_INFO1 >+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 >+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb >+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf >+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 >+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL >+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L >+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L >+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L >+//DIG1_AFMT_60958_0 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L >+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L >+//DIG1_AFMT_60958_1 >+#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 >+#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 >+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 >+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 >+#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 >+#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL >+#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L >+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L >+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L >+#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L >+//DIG1_AFMT_AUDIO_CRC_CONTROL >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L >+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L >+//DIG1_AFMT_RAMP_CONTROL0 >+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 >+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f >+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL >+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L >+//DIG1_AFMT_RAMP_CONTROL1 >+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 >+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 >+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL >+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L >+//DIG1_AFMT_RAMP_CONTROL2 >+#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 >+#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL >+//DIG1_AFMT_RAMP_CONTROL3 >+#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 >+#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL >+//DIG1_AFMT_60958_2 >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L >+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L >+//DIG1_AFMT_AUDIO_CRC_RESULT >+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 >+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 >+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L >+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L >+//DIG1_AFMT_STATUS >+#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 >+#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 >+#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 >+#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e >+#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L >+#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L >+#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L >+#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L >+//DIG1_AFMT_AUDIO_PACKET_CONTROL >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L >+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L >+//DIG1_AFMT_VBI_PACKET_CONTROL >+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 >+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 >+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 >+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c >+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L >+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L >+//DIG1_AFMT_INFOFRAME_CONTROL0 >+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 >+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 >+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa >+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L >+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L >+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L >+//DIG1_AFMT_AUDIO_SRC_CONTROL >+#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 >+#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L >+//DIG1_DIG_BE_CNTL >+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 >+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 >+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 >+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 >+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 >+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c >+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L >+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L >+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L >+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L >+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L >+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L >+//DIG1_DIG_BE_EN_CNTL >+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 >+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 >+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L >+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L >+//DIG1_TMDS_CNTL >+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 >+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L >+//DIG1_TMDS_CONTROL_CHAR >+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 >+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 >+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 >+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 >+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L >+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L >+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L >+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L >+//DIG1_TMDS_CONTROL0_FEEDBACK >+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 >+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 >+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L >+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L >+//DIG1_TMDS_STEREOSYNC_CTL_SEL >+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 >+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L >+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 >+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 >+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 >+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL >+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L >+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 >+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 >+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 >+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL >+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L >+//DIG1_TMDS_CTL_BITS >+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 >+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 >+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 >+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 >+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L >+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L >+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L >+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L >+//DIG1_TMDS_DCBALANCER_CONTROL >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L >+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L >+//DIG1_TMDS_SYNC_DCBALANCE_CHAR >+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 >+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 >+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL >+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L >+//DIG1_TMDS_CTL0_1_GEN_CNTL >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L >+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L >+//DIG1_TMDS_CTL2_3_GEN_CNTL >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L >+//DIG1_DIG_VERSION >+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 >+#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L >+//DIG1_DIG_LANE_ENABLE >+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 >+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 >+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 >+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 >+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 >+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L >+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L >+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L >+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L >+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L >+//DIG1_AFMT_CNTL >+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 >+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 >+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L >+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L >+//DIG1_AFMT_VBI_PACKET_CONTROL1 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L >+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L >+//DIG1_HDMI_GENERIC_PACKET_CONTROL5 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L >+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L >+//DIG1_FORCE_DIG_DISABLE >+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 >+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_dio_dp1_dispdec >+//DP1_DP_LINK_CNTL >+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 >+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 >+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 >+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L >+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L >+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L >+//DP1_DP_PIXEL_FORMAT >+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 >+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 >+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c >+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L >+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L >+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L >+//DP1_DP_MSA_COLORIMETRY >+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 >+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L >+//DP1_DP_CONFIG >+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 >+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L >+//DP1_DP_VID_STREAM_CNTL >+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 >+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 >+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 >+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 >+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L >+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L >+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L >+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L >+//DP1_DP_STEER_FIFO >+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 >+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 >+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 >+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 >+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 >+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 >+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc >+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L >+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L >+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L >+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L >+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L >+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L >+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L >+//DP1_DP_MSA_MISC >+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 >+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 >+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 >+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 >+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL >+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L >+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L >+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L >+//DP1_DP_VID_TIMING >+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 >+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 >+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa >+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc >+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 >+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L >+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L >+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L >+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L >+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L >+//DP1_DP_VID_N >+#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 >+#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL >+//DP1_DP_VID_M >+#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 >+#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL >+//DP1_DP_LINK_FRAMING_CNTL >+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 >+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 >+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c >+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL >+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L >+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L >+//DP1_DP_HBR2_EYE_PATTERN >+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 >+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L >+//DP1_DP_VID_MSA_VBID >+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 >+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 >+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL >+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L >+//DP1_DP_VID_INTERRUPT_CNTL >+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 >+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 >+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 >+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L >+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L >+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L >+//DP1_DP_DPHY_CNTL >+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 >+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 >+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 >+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 >+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 >+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 >+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 >+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 >+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 >+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L >+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L >+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L >+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L >+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L >+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L >+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L >+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L >+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L >+//DP1_DP_DPHY_TRAINING_PATTERN_SEL >+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 >+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L >+//DP1_DP_DPHY_SYM0 >+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 >+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa >+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 >+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL >+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L >+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L >+//DP1_DP_DPHY_SYM1 >+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 >+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa >+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 >+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL >+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L >+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L >+//DP1_DP_DPHY_SYM2 >+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 >+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa >+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL >+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L >+//DP1_DP_DPHY_8B10B_CNTL >+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 >+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 >+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 >+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L >+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L >+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L >+//DP1_DP_DPHY_PRBS_CNTL >+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 >+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 >+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 >+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L >+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L >+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L >+//DP1_DP_DPHY_SCRAM_CNTL >+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 >+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 >+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 >+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 >+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L >+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L >+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L >+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L >+//DP1_DP_DPHY_CRC_EN >+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 >+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 >+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 >+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L >+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L >+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L >+//DP1_DP_DPHY_CRC_CNTL >+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 >+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 >+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 >+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L >+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L >+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L >+//DP1_DP_DPHY_CRC_RESULT >+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 >+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 >+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 >+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 >+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL >+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L >+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L >+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L >+//DP1_DP_DPHY_CRC_MST_CNTL >+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 >+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 >+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL >+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L >+//DP1_DP_DPHY_CRC_MST_STATUS >+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 >+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 >+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 >+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L >+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L >+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L >+//DP1_DP_DPHY_FAST_TRAINING >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L >+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L >+//DP1_DP_DPHY_FAST_TRAINING_STATUS >+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 >+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 >+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 >+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc >+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L >+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L >+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L >+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L >+//DP1_DP_SEC_CNTL >+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 >+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 >+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 >+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc >+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b >+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c >+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L >+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L >+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L >+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L >+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L >+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L >+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L >+//DP1_DP_SEC_CNTL1 >+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 >+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L >+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L >+//DP1_DP_SEC_FRAMING1 >+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 >+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL >+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP1_DP_SEC_FRAMING2 >+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 >+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL >+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP1_DP_SEC_FRAMING3 >+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 >+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL >+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP1_DP_SEC_FRAMING4 >+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 >+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 >+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 >+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c >+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d >+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L >+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L >+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L >+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L >+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L >+//DP1_DP_SEC_AUD_N >+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 >+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL >+//DP1_DP_SEC_AUD_N_READBACK >+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 >+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL >+//DP1_DP_SEC_AUD_M >+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 >+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL >+//DP1_DP_SEC_AUD_M_READBACK >+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 >+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL >+//DP1_DP_SEC_TIMESTAMP >+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 >+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L >+//DP1_DP_SEC_PACKET_CNTL >+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 >+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 >+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 >+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 >+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL >+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L >+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L >+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L >+//DP1_DP_MSE_RATE_CNTL >+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 >+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a >+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL >+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L >+//DP1_DP_MSE_RATE_UPDATE >+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 >+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L >+//DP1_DP_MSE_SAT0 >+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 >+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 >+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 >+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 >+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L >+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L >+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L >+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L >+//DP1_DP_MSE_SAT1 >+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 >+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 >+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 >+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 >+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L >+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L >+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L >+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L >+//DP1_DP_MSE_SAT2 >+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 >+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 >+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 >+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 >+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L >+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L >+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L >+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L >+//DP1_DP_MSE_SAT_UPDATE >+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 >+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 >+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L >+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L >+//DP1_DP_MSE_LINK_TIMING >+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 >+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 >+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL >+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L >+//DP1_DP_MSE_MISC_CNTL >+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 >+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 >+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 >+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L >+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L >+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L >+//DP1_DP_DPHY_BS_SR_SWAP_CNTL >+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 >+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf >+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 >+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL >+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L >+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L >+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL >+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 >+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L >+//DP1_DP_MSE_SAT0_STATUS >+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 >+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 >+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 >+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 >+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L >+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L >+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L >+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L >+//DP1_DP_MSE_SAT1_STATUS >+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 >+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 >+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 >+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 >+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L >+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L >+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L >+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L >+//DP1_DP_MSE_SAT2_STATUS >+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 >+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 >+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 >+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 >+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L >+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L >+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L >+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L >+//DP1_DP_MSA_TIMING_PARAM1 >+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 >+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 >+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL >+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L >+//DP1_DP_MSA_TIMING_PARAM2 >+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 >+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 >+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL >+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L >+//DP1_DP_MSA_TIMING_PARAM3 >+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 >+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf >+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 >+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f >+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL >+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L >+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L >+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L >+//DP1_DP_MSA_TIMING_PARAM4 >+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 >+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 >+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL >+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L >+//DP1_DP_MSO_CNTL >+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c >+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L >+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L >+//DP1_DP_MSO_CNTL1 >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L >+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L >+//DP1_DP_DSC_CNTL >+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 >+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L >+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//DP1_DP_SEC_CNTL2 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L >+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L >+//DP1_DP_SEC_CNTL3 >+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 >+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 >+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL >+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L >+//DP1_DP_SEC_CNTL4 >+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 >+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 >+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL >+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L >+//DP1_DP_SEC_CNTL5 >+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 >+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 >+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL >+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L >+//DP1_DP_SEC_CNTL6 >+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 >+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL >+//DP1_DP_SEC_CNTL7 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L >+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L >+//DP1_DP_DB_CNTL >+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 >+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 >+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 >+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 >+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc >+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf >+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L >+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L >+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L >+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L >+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L >+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DP1_DP_MSA_VBID_MISC >+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 >+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 >+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 >+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc >+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd >+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf >+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 >+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L >+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L >+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L >+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L >+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L >+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L >+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L >+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L >+//DP1_DP_SEC_METADATA_TRANSMISSION >+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 >+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 >+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L >+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L >+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DP1_DP_DSC_BYTES_PER_PIXEL >+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//DP1_DP_ALPM_CNTL >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 >+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L >+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L >+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dio_dig2_dispdec >+//DIG2_DIG_FE_CNTL >+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 >+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 >+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 >+#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa >+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc >+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 >+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 >+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 >+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 >+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c >+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e >+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L >+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L >+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L >+#define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L >+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L >+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L >+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L >+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L >+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L >+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L >+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L >+//DIG2_DIG_OUTPUT_CRC_CNTL >+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 >+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 >+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 >+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L >+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L >+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L >+//DIG2_DIG_OUTPUT_CRC_RESULT >+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 >+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL >+//DIG2_DIG_CLOCK_PATTERN >+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 >+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL >+//DIG2_DIG_TEST_PATTERN >+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 >+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 >+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 >+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 >+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 >+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 >+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L >+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L >+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L >+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L >+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L >+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L >+//DIG2_DIG_RANDOM_PATTERN_SEED >+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 >+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 >+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL >+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L >+//DIG2_DIG_FIFO_STATUS >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L >+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L >+//DIG2_HDMI_METADATA_PACKET_CONTROL >+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 >+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 >+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L >+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L >+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DIG2_HDMI_GENERIC_PACKET_CONTROL4 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L >+//DIG2_HDMI_CONTROL >+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 >+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 >+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 >+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 >+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 >+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 >+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 >+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 >+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 >+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c >+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L >+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L >+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L >+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L >+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L >+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L >+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L >+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L >+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L >+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L >+//DIG2_HDMI_STATUS >+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 >+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 >+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 >+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b >+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L >+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L >+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L >+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L >+//DIG2_HDMI_AUDIO_PACKET_CONTROL >+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 >+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 >+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 >+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L >+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L >+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L >+//DIG2_HDMI_ACR_PACKET_CONTROL >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L >+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L >+//DIG2_HDMI_VBI_PACKET_CONTROL >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L >+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L >+//DIG2_HDMI_INFOFRAME_CONTROL0 >+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 >+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 >+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 >+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 >+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L >+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L >+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L >+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L >+//DIG2_HDMI_INFOFRAME_CONTROL1 >+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 >+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 >+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L >+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L >+//DIG2_HDMI_GENERIC_PACKET_CONTROL0 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L >+//DIG2_HDMI_GC >+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 >+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 >+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 >+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 >+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc >+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L >+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L >+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L >+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L >+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L >+//DIG2_AFMT_AUDIO_PACKET_CONTROL2 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L >+//DIG2_AFMT_ISRC1_0 >+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 >+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 >+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 >+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L >+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L >+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L >+//DIG2_AFMT_ISRC1_1 >+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 >+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 >+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 >+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 >+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL >+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L >+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L >+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L >+//DIG2_AFMT_ISRC1_2 >+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 >+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 >+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 >+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 >+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL >+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L >+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L >+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L >+//DIG2_AFMT_ISRC1_3 >+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 >+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 >+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 >+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 >+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL >+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L >+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L >+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L >+//DIG2_AFMT_ISRC1_4 >+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 >+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 >+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 >+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 >+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL >+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L >+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L >+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L >+//DIG2_AFMT_ISRC2_0 >+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 >+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 >+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 >+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 >+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL >+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L >+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L >+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L >+//DIG2_AFMT_ISRC2_1 >+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 >+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 >+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 >+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 >+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL >+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L >+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L >+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L >+//DIG2_AFMT_ISRC2_2 >+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 >+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 >+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 >+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 >+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL >+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L >+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L >+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L >+//DIG2_AFMT_ISRC2_3 >+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 >+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 >+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 >+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 >+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL >+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L >+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L >+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L >+//DIG2_HDMI_GENERIC_PACKET_CONTROL2 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L >+//DIG2_HDMI_GENERIC_PACKET_CONTROL3 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L >+//DIG2_HDMI_DB_CONTROL >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc >+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf >+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L >+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L >+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DIG2_DME_CONTROL >+#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 >+#define DIG2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 >+#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 >+#define DIG2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc >+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd >+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 >+#define DIG2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 >+#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L >+#define DIG2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L >+#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L >+#define DIG2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L >+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L >+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L >+#define DIG2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L >+//DIG2_AFMT_MPEG_INFO0 >+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 >+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 >+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 >+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L >+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L >+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L >+//DIG2_AFMT_MPEG_INFO1 >+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 >+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 >+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc >+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL >+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L >+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L >+//DIG2_AFMT_GENERIC_HDR >+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L >+//DIG2_AFMT_GENERIC_0 >+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L >+//DIG2_AFMT_GENERIC_1 >+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L >+//DIG2_AFMT_GENERIC_2 >+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L >+//DIG2_AFMT_GENERIC_3 >+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L >+//DIG2_AFMT_GENERIC_4 >+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L >+//DIG2_AFMT_GENERIC_5 >+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L >+//DIG2_AFMT_GENERIC_6 >+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L >+//DIG2_AFMT_GENERIC_7 >+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 >+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 >+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 >+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 >+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL >+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L >+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L >+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L >+//DIG2_HDMI_GENERIC_PACKET_CONTROL1 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L >+//DIG2_HDMI_ACR_32_0 >+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc >+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L >+//DIG2_HDMI_ACR_32_1 >+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 >+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL >+//DIG2_HDMI_ACR_44_0 >+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc >+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L >+//DIG2_HDMI_ACR_44_1 >+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 >+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL >+//DIG2_HDMI_ACR_48_0 >+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc >+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L >+//DIG2_HDMI_ACR_48_1 >+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 >+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL >+//DIG2_HDMI_ACR_STATUS_0 >+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc >+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L >+//DIG2_HDMI_ACR_STATUS_1 >+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 >+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL >+//DIG2_AFMT_AUDIO_INFO0 >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L >+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L >+//DIG2_AFMT_AUDIO_INFO1 >+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 >+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb >+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf >+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 >+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL >+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L >+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L >+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L >+//DIG2_AFMT_60958_0 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L >+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L >+//DIG2_AFMT_60958_1 >+#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 >+#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 >+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 >+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 >+#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 >+#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL >+#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L >+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L >+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L >+#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L >+//DIG2_AFMT_AUDIO_CRC_CONTROL >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L >+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L >+//DIG2_AFMT_RAMP_CONTROL0 >+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 >+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f >+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL >+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L >+//DIG2_AFMT_RAMP_CONTROL1 >+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 >+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 >+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL >+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L >+//DIG2_AFMT_RAMP_CONTROL2 >+#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 >+#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL >+//DIG2_AFMT_RAMP_CONTROL3 >+#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 >+#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL >+//DIG2_AFMT_60958_2 >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L >+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L >+//DIG2_AFMT_AUDIO_CRC_RESULT >+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 >+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 >+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L >+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L >+//DIG2_AFMT_STATUS >+#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 >+#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 >+#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 >+#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e >+#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L >+#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L >+#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L >+#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L >+//DIG2_AFMT_AUDIO_PACKET_CONTROL >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L >+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L >+//DIG2_AFMT_VBI_PACKET_CONTROL >+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 >+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 >+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 >+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c >+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L >+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L >+//DIG2_AFMT_INFOFRAME_CONTROL0 >+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 >+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 >+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa >+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L >+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L >+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L >+//DIG2_AFMT_AUDIO_SRC_CONTROL >+#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 >+#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L >+//DIG2_DIG_BE_CNTL >+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 >+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 >+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 >+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 >+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 >+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c >+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L >+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L >+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L >+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L >+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L >+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L >+//DIG2_DIG_BE_EN_CNTL >+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 >+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 >+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L >+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L >+//DIG2_TMDS_CNTL >+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 >+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L >+//DIG2_TMDS_CONTROL_CHAR >+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 >+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 >+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 >+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 >+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L >+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L >+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L >+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L >+//DIG2_TMDS_CONTROL0_FEEDBACK >+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 >+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 >+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L >+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L >+//DIG2_TMDS_STEREOSYNC_CTL_SEL >+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 >+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L >+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 >+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 >+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 >+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL >+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L >+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 >+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 >+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 >+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL >+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L >+//DIG2_TMDS_CTL_BITS >+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 >+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 >+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 >+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 >+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L >+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L >+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L >+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L >+//DIG2_TMDS_DCBALANCER_CONTROL >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L >+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L >+//DIG2_TMDS_SYNC_DCBALANCE_CHAR >+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 >+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 >+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL >+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L >+//DIG2_TMDS_CTL0_1_GEN_CNTL >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L >+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L >+//DIG2_TMDS_CTL2_3_GEN_CNTL >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L >+//DIG2_DIG_VERSION >+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 >+#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L >+//DIG2_DIG_LANE_ENABLE >+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 >+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 >+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 >+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 >+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 >+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L >+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L >+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L >+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L >+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L >+//DIG2_AFMT_CNTL >+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 >+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 >+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L >+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L >+//DIG2_AFMT_VBI_PACKET_CONTROL1 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L >+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L >+//DIG2_HDMI_GENERIC_PACKET_CONTROL5 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L >+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L >+//DIG2_FORCE_DIG_DISABLE >+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 >+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_dio_dp2_dispdec >+//DP2_DP_LINK_CNTL >+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 >+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 >+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 >+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L >+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L >+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L >+//DP2_DP_PIXEL_FORMAT >+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 >+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 >+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c >+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L >+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L >+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L >+//DP2_DP_MSA_COLORIMETRY >+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 >+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L >+//DP2_DP_CONFIG >+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 >+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L >+//DP2_DP_VID_STREAM_CNTL >+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 >+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 >+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 >+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 >+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L >+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L >+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L >+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L >+//DP2_DP_STEER_FIFO >+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 >+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 >+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 >+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 >+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 >+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 >+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc >+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L >+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L >+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L >+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L >+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L >+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L >+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L >+//DP2_DP_MSA_MISC >+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 >+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 >+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 >+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 >+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL >+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L >+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L >+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L >+//DP2_DP_VID_TIMING >+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 >+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 >+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa >+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc >+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 >+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L >+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L >+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L >+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L >+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L >+//DP2_DP_VID_N >+#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 >+#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL >+//DP2_DP_VID_M >+#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 >+#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL >+//DP2_DP_LINK_FRAMING_CNTL >+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 >+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 >+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c >+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL >+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L >+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L >+//DP2_DP_HBR2_EYE_PATTERN >+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 >+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L >+//DP2_DP_VID_MSA_VBID >+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 >+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 >+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL >+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L >+//DP2_DP_VID_INTERRUPT_CNTL >+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 >+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 >+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 >+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L >+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L >+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L >+//DP2_DP_DPHY_CNTL >+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 >+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 >+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 >+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 >+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 >+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 >+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 >+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 >+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 >+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L >+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L >+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L >+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L >+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L >+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L >+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L >+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L >+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L >+//DP2_DP_DPHY_TRAINING_PATTERN_SEL >+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 >+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L >+//DP2_DP_DPHY_SYM0 >+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 >+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa >+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 >+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL >+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L >+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L >+//DP2_DP_DPHY_SYM1 >+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 >+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa >+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 >+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL >+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L >+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L >+//DP2_DP_DPHY_SYM2 >+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 >+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa >+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL >+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L >+//DP2_DP_DPHY_8B10B_CNTL >+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 >+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 >+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 >+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L >+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L >+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L >+//DP2_DP_DPHY_PRBS_CNTL >+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 >+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 >+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 >+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L >+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L >+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L >+//DP2_DP_DPHY_SCRAM_CNTL >+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 >+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 >+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 >+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 >+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L >+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L >+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L >+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L >+//DP2_DP_DPHY_CRC_EN >+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 >+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 >+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 >+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L >+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L >+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L >+//DP2_DP_DPHY_CRC_CNTL >+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 >+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 >+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 >+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L >+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L >+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L >+//DP2_DP_DPHY_CRC_RESULT >+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 >+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 >+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 >+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 >+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL >+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L >+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L >+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L >+//DP2_DP_DPHY_CRC_MST_CNTL >+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 >+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 >+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL >+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L >+//DP2_DP_DPHY_CRC_MST_STATUS >+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 >+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 >+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 >+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L >+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L >+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L >+//DP2_DP_DPHY_FAST_TRAINING >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L >+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L >+//DP2_DP_DPHY_FAST_TRAINING_STATUS >+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 >+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 >+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 >+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc >+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L >+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L >+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L >+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L >+//DP2_DP_SEC_CNTL >+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 >+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 >+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 >+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc >+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b >+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c >+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L >+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L >+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L >+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L >+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L >+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L >+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L >+//DP2_DP_SEC_CNTL1 >+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 >+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L >+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L >+//DP2_DP_SEC_FRAMING1 >+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 >+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL >+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP2_DP_SEC_FRAMING2 >+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 >+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL >+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP2_DP_SEC_FRAMING3 >+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 >+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL >+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP2_DP_SEC_FRAMING4 >+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 >+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 >+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 >+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c >+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d >+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L >+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L >+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L >+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L >+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L >+//DP2_DP_SEC_AUD_N >+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 >+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL >+//DP2_DP_SEC_AUD_N_READBACK >+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 >+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL >+//DP2_DP_SEC_AUD_M >+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 >+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL >+//DP2_DP_SEC_AUD_M_READBACK >+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 >+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL >+//DP2_DP_SEC_TIMESTAMP >+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 >+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L >+//DP2_DP_SEC_PACKET_CNTL >+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 >+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 >+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 >+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 >+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL >+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L >+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L >+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L >+//DP2_DP_MSE_RATE_CNTL >+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 >+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a >+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL >+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L >+//DP2_DP_MSE_RATE_UPDATE >+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 >+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L >+//DP2_DP_MSE_SAT0 >+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 >+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 >+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 >+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 >+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L >+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L >+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L >+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L >+//DP2_DP_MSE_SAT1 >+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 >+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 >+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 >+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 >+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L >+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L >+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L >+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L >+//DP2_DP_MSE_SAT2 >+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 >+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 >+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 >+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 >+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L >+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L >+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L >+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L >+//DP2_DP_MSE_SAT_UPDATE >+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 >+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 >+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L >+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L >+//DP2_DP_MSE_LINK_TIMING >+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 >+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 >+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL >+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L >+//DP2_DP_MSE_MISC_CNTL >+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 >+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 >+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 >+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L >+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L >+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L >+//DP2_DP_DPHY_BS_SR_SWAP_CNTL >+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 >+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf >+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 >+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL >+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L >+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L >+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL >+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 >+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L >+//DP2_DP_MSE_SAT0_STATUS >+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 >+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 >+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 >+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 >+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L >+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L >+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L >+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L >+//DP2_DP_MSE_SAT1_STATUS >+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 >+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 >+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 >+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 >+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L >+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L >+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L >+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L >+//DP2_DP_MSE_SAT2_STATUS >+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 >+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 >+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 >+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 >+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L >+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L >+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L >+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L >+//DP2_DP_MSA_TIMING_PARAM1 >+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 >+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 >+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL >+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L >+//DP2_DP_MSA_TIMING_PARAM2 >+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 >+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 >+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL >+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L >+//DP2_DP_MSA_TIMING_PARAM3 >+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 >+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf >+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 >+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f >+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL >+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L >+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L >+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L >+//DP2_DP_MSA_TIMING_PARAM4 >+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 >+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 >+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL >+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L >+//DP2_DP_MSO_CNTL >+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c >+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L >+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L >+//DP2_DP_MSO_CNTL1 >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L >+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L >+//DP2_DP_DSC_CNTL >+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 >+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L >+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//DP2_DP_SEC_CNTL2 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L >+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L >+//DP2_DP_SEC_CNTL3 >+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 >+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 >+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL >+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L >+//DP2_DP_SEC_CNTL4 >+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 >+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 >+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL >+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L >+//DP2_DP_SEC_CNTL5 >+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 >+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 >+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL >+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L >+//DP2_DP_SEC_CNTL6 >+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 >+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL >+//DP2_DP_SEC_CNTL7 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L >+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L >+//DP2_DP_DB_CNTL >+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 >+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 >+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 >+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 >+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc >+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf >+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L >+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L >+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L >+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L >+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L >+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DP2_DP_MSA_VBID_MISC >+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 >+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 >+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 >+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc >+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd >+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf >+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 >+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L >+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L >+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L >+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L >+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L >+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L >+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L >+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L >+//DP2_DP_SEC_METADATA_TRANSMISSION >+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 >+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 >+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L >+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L >+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DP2_DP_DSC_BYTES_PER_PIXEL >+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//DP2_DP_ALPM_CNTL >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 >+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L >+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L >+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dio_dig3_dispdec >+//DIG3_DIG_FE_CNTL >+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 >+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 >+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 >+#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa >+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc >+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 >+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 >+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 >+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 >+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c >+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e >+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L >+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L >+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L >+#define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L >+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L >+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L >+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L >+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L >+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L >+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L >+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L >+//DIG3_DIG_OUTPUT_CRC_CNTL >+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 >+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 >+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 >+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L >+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L >+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L >+//DIG3_DIG_OUTPUT_CRC_RESULT >+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 >+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL >+//DIG3_DIG_CLOCK_PATTERN >+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 >+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL >+//DIG3_DIG_TEST_PATTERN >+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 >+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 >+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 >+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 >+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 >+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 >+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L >+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L >+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L >+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L >+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L >+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L >+//DIG3_DIG_RANDOM_PATTERN_SEED >+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 >+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 >+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL >+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L >+//DIG3_DIG_FIFO_STATUS >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L >+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L >+//DIG3_HDMI_METADATA_PACKET_CONTROL >+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 >+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 >+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L >+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L >+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DIG3_HDMI_GENERIC_PACKET_CONTROL4 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L >+//DIG3_HDMI_CONTROL >+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 >+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 >+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 >+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 >+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 >+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 >+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 >+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 >+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 >+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c >+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L >+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L >+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L >+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L >+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L >+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L >+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L >+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L >+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L >+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L >+//DIG3_HDMI_STATUS >+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 >+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 >+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 >+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b >+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L >+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L >+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L >+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L >+//DIG3_HDMI_AUDIO_PACKET_CONTROL >+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 >+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 >+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 >+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L >+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L >+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L >+//DIG3_HDMI_ACR_PACKET_CONTROL >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L >+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L >+//DIG3_HDMI_VBI_PACKET_CONTROL >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L >+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L >+//DIG3_HDMI_INFOFRAME_CONTROL0 >+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 >+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 >+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 >+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 >+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L >+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L >+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L >+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L >+//DIG3_HDMI_INFOFRAME_CONTROL1 >+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 >+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 >+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L >+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L >+//DIG3_HDMI_GENERIC_PACKET_CONTROL0 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L >+//DIG3_HDMI_GC >+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 >+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 >+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 >+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 >+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc >+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L >+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L >+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L >+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L >+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L >+//DIG3_AFMT_AUDIO_PACKET_CONTROL2 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L >+//DIG3_AFMT_ISRC1_0 >+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 >+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 >+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 >+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L >+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L >+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L >+//DIG3_AFMT_ISRC1_1 >+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 >+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 >+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 >+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 >+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL >+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L >+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L >+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L >+//DIG3_AFMT_ISRC1_2 >+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 >+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 >+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 >+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 >+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL >+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L >+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L >+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L >+//DIG3_AFMT_ISRC1_3 >+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 >+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 >+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 >+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 >+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL >+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L >+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L >+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L >+//DIG3_AFMT_ISRC1_4 >+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 >+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 >+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 >+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 >+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL >+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L >+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L >+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L >+//DIG3_AFMT_ISRC2_0 >+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 >+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 >+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 >+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 >+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL >+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L >+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L >+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L >+//DIG3_AFMT_ISRC2_1 >+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 >+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 >+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 >+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 >+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL >+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L >+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L >+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L >+//DIG3_AFMT_ISRC2_2 >+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 >+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 >+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 >+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 >+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL >+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L >+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L >+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L >+//DIG3_AFMT_ISRC2_3 >+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 >+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 >+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 >+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 >+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL >+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L >+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L >+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L >+//DIG3_HDMI_GENERIC_PACKET_CONTROL2 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L >+//DIG3_HDMI_GENERIC_PACKET_CONTROL3 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L >+//DIG3_HDMI_DB_CONTROL >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc >+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf >+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L >+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L >+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DIG3_DME_CONTROL >+#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 >+#define DIG3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 >+#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 >+#define DIG3_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc >+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd >+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 >+#define DIG3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 >+#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L >+#define DIG3_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L >+#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L >+#define DIG3_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L >+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L >+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L >+#define DIG3_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L >+//DIG3_AFMT_MPEG_INFO0 >+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 >+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 >+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 >+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L >+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L >+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L >+//DIG3_AFMT_MPEG_INFO1 >+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 >+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 >+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc >+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL >+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L >+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L >+//DIG3_AFMT_GENERIC_HDR >+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L >+//DIG3_AFMT_GENERIC_0 >+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L >+//DIG3_AFMT_GENERIC_1 >+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L >+//DIG3_AFMT_GENERIC_2 >+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L >+//DIG3_AFMT_GENERIC_3 >+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L >+//DIG3_AFMT_GENERIC_4 >+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L >+//DIG3_AFMT_GENERIC_5 >+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L >+//DIG3_AFMT_GENERIC_6 >+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L >+//DIG3_AFMT_GENERIC_7 >+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 >+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 >+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 >+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 >+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL >+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L >+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L >+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L >+//DIG3_HDMI_GENERIC_PACKET_CONTROL1 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L >+//DIG3_HDMI_ACR_32_0 >+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc >+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L >+//DIG3_HDMI_ACR_32_1 >+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 >+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL >+//DIG3_HDMI_ACR_44_0 >+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc >+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L >+//DIG3_HDMI_ACR_44_1 >+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 >+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL >+//DIG3_HDMI_ACR_48_0 >+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc >+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L >+//DIG3_HDMI_ACR_48_1 >+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 >+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL >+//DIG3_HDMI_ACR_STATUS_0 >+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc >+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L >+//DIG3_HDMI_ACR_STATUS_1 >+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 >+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL >+//DIG3_AFMT_AUDIO_INFO0 >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L >+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L >+//DIG3_AFMT_AUDIO_INFO1 >+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 >+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb >+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf >+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 >+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL >+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L >+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L >+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L >+//DIG3_AFMT_60958_0 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L >+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L >+//DIG3_AFMT_60958_1 >+#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 >+#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 >+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 >+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 >+#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 >+#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL >+#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L >+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L >+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L >+#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L >+//DIG3_AFMT_AUDIO_CRC_CONTROL >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L >+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L >+//DIG3_AFMT_RAMP_CONTROL0 >+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 >+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f >+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL >+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L >+//DIG3_AFMT_RAMP_CONTROL1 >+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 >+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 >+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL >+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L >+//DIG3_AFMT_RAMP_CONTROL2 >+#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 >+#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL >+//DIG3_AFMT_RAMP_CONTROL3 >+#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 >+#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL >+//DIG3_AFMT_60958_2 >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L >+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L >+//DIG3_AFMT_AUDIO_CRC_RESULT >+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 >+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 >+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L >+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L >+//DIG3_AFMT_STATUS >+#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 >+#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 >+#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 >+#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e >+#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L >+#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L >+#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L >+#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L >+//DIG3_AFMT_AUDIO_PACKET_CONTROL >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L >+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L >+//DIG3_AFMT_VBI_PACKET_CONTROL >+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 >+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 >+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 >+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c >+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L >+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L >+//DIG3_AFMT_INFOFRAME_CONTROL0 >+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 >+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 >+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa >+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L >+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L >+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L >+//DIG3_AFMT_AUDIO_SRC_CONTROL >+#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 >+#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L >+//DIG3_DIG_BE_CNTL >+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 >+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 >+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 >+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 >+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 >+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c >+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L >+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L >+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L >+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L >+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L >+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L >+//DIG3_DIG_BE_EN_CNTL >+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 >+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 >+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L >+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L >+//DIG3_TMDS_CNTL >+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 >+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L >+//DIG3_TMDS_CONTROL_CHAR >+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 >+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 >+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 >+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 >+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L >+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L >+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L >+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L >+//DIG3_TMDS_CONTROL0_FEEDBACK >+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 >+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 >+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L >+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L >+//DIG3_TMDS_STEREOSYNC_CTL_SEL >+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 >+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L >+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 >+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 >+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 >+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL >+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L >+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 >+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 >+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 >+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL >+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L >+//DIG3_TMDS_CTL_BITS >+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 >+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 >+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 >+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 >+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L >+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L >+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L >+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L >+//DIG3_TMDS_DCBALANCER_CONTROL >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L >+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L >+//DIG3_TMDS_SYNC_DCBALANCE_CHAR >+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 >+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 >+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL >+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L >+//DIG3_TMDS_CTL0_1_GEN_CNTL >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L >+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L >+//DIG3_TMDS_CTL2_3_GEN_CNTL >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L >+//DIG3_DIG_VERSION >+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 >+#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L >+//DIG3_DIG_LANE_ENABLE >+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 >+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 >+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 >+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 >+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 >+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L >+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L >+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L >+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L >+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L >+//DIG3_AFMT_CNTL >+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 >+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 >+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L >+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L >+//DIG3_AFMT_VBI_PACKET_CONTROL1 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L >+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L >+//DIG3_HDMI_GENERIC_PACKET_CONTROL5 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L >+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L >+//DIG3_FORCE_DIG_DISABLE >+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 >+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_dio_dp3_dispdec >+//DP3_DP_LINK_CNTL >+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 >+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 >+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 >+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L >+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L >+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L >+//DP3_DP_PIXEL_FORMAT >+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 >+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 >+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c >+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L >+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L >+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L >+//DP3_DP_MSA_COLORIMETRY >+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 >+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L >+//DP3_DP_CONFIG >+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 >+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L >+//DP3_DP_VID_STREAM_CNTL >+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 >+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 >+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 >+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 >+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L >+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L >+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L >+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L >+//DP3_DP_STEER_FIFO >+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 >+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 >+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 >+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 >+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 >+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 >+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc >+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L >+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L >+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L >+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L >+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L >+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L >+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L >+//DP3_DP_MSA_MISC >+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 >+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 >+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 >+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 >+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL >+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L >+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L >+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L >+//DP3_DP_VID_TIMING >+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 >+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 >+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa >+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc >+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 >+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L >+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L >+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L >+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L >+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L >+//DP3_DP_VID_N >+#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 >+#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL >+//DP3_DP_VID_M >+#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 >+#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL >+//DP3_DP_LINK_FRAMING_CNTL >+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 >+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 >+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c >+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL >+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L >+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L >+//DP3_DP_HBR2_EYE_PATTERN >+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 >+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L >+//DP3_DP_VID_MSA_VBID >+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 >+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 >+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL >+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L >+//DP3_DP_VID_INTERRUPT_CNTL >+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 >+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 >+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 >+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L >+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L >+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L >+//DP3_DP_DPHY_CNTL >+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 >+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 >+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 >+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 >+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 >+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 >+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 >+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 >+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 >+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L >+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L >+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L >+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L >+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L >+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L >+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L >+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L >+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L >+//DP3_DP_DPHY_TRAINING_PATTERN_SEL >+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 >+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L >+//DP3_DP_DPHY_SYM0 >+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 >+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa >+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 >+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL >+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L >+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L >+//DP3_DP_DPHY_SYM1 >+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 >+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa >+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 >+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL >+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L >+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L >+//DP3_DP_DPHY_SYM2 >+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 >+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa >+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL >+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L >+//DP3_DP_DPHY_8B10B_CNTL >+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 >+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 >+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 >+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L >+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L >+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L >+//DP3_DP_DPHY_PRBS_CNTL >+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 >+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 >+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 >+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L >+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L >+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L >+//DP3_DP_DPHY_SCRAM_CNTL >+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 >+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 >+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 >+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 >+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L >+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L >+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L >+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L >+//DP3_DP_DPHY_CRC_EN >+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 >+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 >+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 >+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L >+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L >+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L >+//DP3_DP_DPHY_CRC_CNTL >+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 >+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 >+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 >+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L >+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L >+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L >+//DP3_DP_DPHY_CRC_RESULT >+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 >+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 >+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 >+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 >+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL >+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L >+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L >+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L >+//DP3_DP_DPHY_CRC_MST_CNTL >+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 >+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 >+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL >+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L >+//DP3_DP_DPHY_CRC_MST_STATUS >+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 >+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 >+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 >+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L >+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L >+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L >+//DP3_DP_DPHY_FAST_TRAINING >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L >+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L >+//DP3_DP_DPHY_FAST_TRAINING_STATUS >+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 >+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 >+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 >+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc >+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L >+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L >+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L >+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L >+//DP3_DP_SEC_CNTL >+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 >+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 >+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 >+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc >+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b >+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c >+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L >+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L >+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L >+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L >+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L >+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L >+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L >+//DP3_DP_SEC_CNTL1 >+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 >+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L >+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L >+//DP3_DP_SEC_FRAMING1 >+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 >+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL >+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP3_DP_SEC_FRAMING2 >+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 >+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL >+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP3_DP_SEC_FRAMING3 >+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 >+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL >+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP3_DP_SEC_FRAMING4 >+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 >+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 >+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 >+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c >+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d >+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L >+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L >+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L >+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L >+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L >+//DP3_DP_SEC_AUD_N >+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 >+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL >+//DP3_DP_SEC_AUD_N_READBACK >+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 >+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL >+//DP3_DP_SEC_AUD_M >+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 >+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL >+//DP3_DP_SEC_AUD_M_READBACK >+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 >+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL >+//DP3_DP_SEC_TIMESTAMP >+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 >+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L >+//DP3_DP_SEC_PACKET_CNTL >+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 >+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 >+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 >+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 >+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL >+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L >+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L >+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L >+//DP3_DP_MSE_RATE_CNTL >+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 >+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a >+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL >+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L >+//DP3_DP_MSE_RATE_UPDATE >+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 >+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L >+//DP3_DP_MSE_SAT0 >+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 >+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 >+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 >+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 >+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L >+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L >+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L >+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L >+//DP3_DP_MSE_SAT1 >+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 >+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 >+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 >+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 >+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L >+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L >+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L >+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L >+//DP3_DP_MSE_SAT2 >+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 >+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 >+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 >+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 >+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L >+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L >+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L >+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L >+//DP3_DP_MSE_SAT_UPDATE >+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 >+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 >+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L >+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L >+//DP3_DP_MSE_LINK_TIMING >+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 >+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 >+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL >+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L >+//DP3_DP_MSE_MISC_CNTL >+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 >+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 >+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 >+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L >+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L >+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L >+//DP3_DP_DPHY_BS_SR_SWAP_CNTL >+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 >+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf >+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 >+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL >+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L >+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L >+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL >+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 >+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L >+//DP3_DP_MSE_SAT0_STATUS >+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 >+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 >+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 >+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 >+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L >+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L >+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L >+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L >+//DP3_DP_MSE_SAT1_STATUS >+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 >+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 >+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 >+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 >+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L >+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L >+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L >+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L >+//DP3_DP_MSE_SAT2_STATUS >+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 >+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 >+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 >+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 >+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L >+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L >+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L >+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L >+//DP3_DP_MSA_TIMING_PARAM1 >+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 >+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 >+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL >+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L >+//DP3_DP_MSA_TIMING_PARAM2 >+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 >+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 >+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL >+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L >+//DP3_DP_MSA_TIMING_PARAM3 >+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 >+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf >+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 >+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f >+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL >+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L >+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L >+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L >+//DP3_DP_MSA_TIMING_PARAM4 >+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 >+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 >+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL >+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L >+//DP3_DP_MSO_CNTL >+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c >+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L >+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L >+//DP3_DP_MSO_CNTL1 >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L >+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L >+//DP3_DP_DSC_CNTL >+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 >+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L >+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//DP3_DP_SEC_CNTL2 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L >+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L >+//DP3_DP_SEC_CNTL3 >+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 >+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 >+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL >+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L >+//DP3_DP_SEC_CNTL4 >+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 >+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 >+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL >+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L >+//DP3_DP_SEC_CNTL5 >+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 >+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 >+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL >+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L >+//DP3_DP_SEC_CNTL6 >+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 >+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL >+//DP3_DP_SEC_CNTL7 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L >+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L >+//DP3_DP_DB_CNTL >+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 >+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 >+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 >+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 >+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc >+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf >+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L >+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L >+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L >+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L >+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L >+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DP3_DP_MSA_VBID_MISC >+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 >+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 >+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 >+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc >+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd >+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf >+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 >+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L >+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L >+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L >+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L >+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L >+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L >+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L >+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L >+//DP3_DP_SEC_METADATA_TRANSMISSION >+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 >+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 >+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L >+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L >+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DP3_DP_DSC_BYTES_PER_PIXEL >+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//DP3_DP_ALPM_CNTL >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 >+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L >+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L >+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dio_dig4_dispdec >+//DIG4_DIG_FE_CNTL >+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 >+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 >+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 >+#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa >+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc >+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 >+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 >+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 >+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 >+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c >+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e >+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L >+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L >+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L >+#define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L >+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L >+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L >+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L >+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L >+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L >+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L >+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L >+//DIG4_DIG_OUTPUT_CRC_CNTL >+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 >+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 >+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 >+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L >+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L >+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L >+//DIG4_DIG_OUTPUT_CRC_RESULT >+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 >+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL >+//DIG4_DIG_CLOCK_PATTERN >+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 >+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL >+//DIG4_DIG_TEST_PATTERN >+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 >+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 >+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 >+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 >+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 >+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 >+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L >+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L >+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L >+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L >+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L >+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L >+//DIG4_DIG_RANDOM_PATTERN_SEED >+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 >+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 >+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL >+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L >+//DIG4_DIG_FIFO_STATUS >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L >+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L >+//DIG4_HDMI_METADATA_PACKET_CONTROL >+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 >+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 >+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L >+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L >+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DIG4_HDMI_GENERIC_PACKET_CONTROL4 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L >+//DIG4_HDMI_CONTROL >+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 >+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 >+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 >+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 >+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 >+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 >+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 >+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 >+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 >+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c >+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L >+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L >+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L >+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L >+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L >+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L >+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L >+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L >+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L >+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L >+//DIG4_HDMI_STATUS >+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 >+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 >+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 >+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b >+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L >+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L >+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L >+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L >+//DIG4_HDMI_AUDIO_PACKET_CONTROL >+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 >+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 >+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 >+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L >+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L >+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L >+//DIG4_HDMI_ACR_PACKET_CONTROL >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L >+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L >+//DIG4_HDMI_VBI_PACKET_CONTROL >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L >+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L >+//DIG4_HDMI_INFOFRAME_CONTROL0 >+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 >+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 >+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 >+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 >+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L >+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L >+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L >+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L >+//DIG4_HDMI_INFOFRAME_CONTROL1 >+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 >+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 >+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L >+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L >+//DIG4_HDMI_GENERIC_PACKET_CONTROL0 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L >+//DIG4_HDMI_GC >+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 >+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 >+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 >+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 >+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc >+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L >+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L >+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L >+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L >+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L >+//DIG4_AFMT_AUDIO_PACKET_CONTROL2 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L >+//DIG4_AFMT_ISRC1_0 >+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 >+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 >+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 >+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L >+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L >+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L >+//DIG4_AFMT_ISRC1_1 >+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 >+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 >+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 >+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 >+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL >+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L >+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L >+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L >+//DIG4_AFMT_ISRC1_2 >+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 >+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 >+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 >+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 >+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL >+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L >+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L >+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L >+//DIG4_AFMT_ISRC1_3 >+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 >+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 >+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 >+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 >+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL >+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L >+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L >+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L >+//DIG4_AFMT_ISRC1_4 >+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 >+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 >+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 >+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 >+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL >+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L >+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L >+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L >+//DIG4_AFMT_ISRC2_0 >+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 >+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 >+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 >+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 >+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL >+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L >+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L >+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L >+//DIG4_AFMT_ISRC2_1 >+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 >+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 >+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 >+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 >+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL >+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L >+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L >+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L >+//DIG4_AFMT_ISRC2_2 >+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 >+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 >+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 >+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 >+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL >+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L >+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L >+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L >+//DIG4_AFMT_ISRC2_3 >+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 >+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 >+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 >+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 >+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL >+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L >+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L >+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L >+//DIG4_HDMI_GENERIC_PACKET_CONTROL2 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L >+//DIG4_HDMI_GENERIC_PACKET_CONTROL3 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L >+//DIG4_HDMI_DB_CONTROL >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc >+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf >+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L >+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L >+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DIG4_DME_CONTROL >+#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 >+#define DIG4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 >+#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 >+#define DIG4_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc >+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd >+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 >+#define DIG4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 >+#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L >+#define DIG4_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L >+#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L >+#define DIG4_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L >+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L >+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L >+#define DIG4_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L >+//DIG4_AFMT_MPEG_INFO0 >+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 >+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 >+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 >+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L >+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L >+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L >+//DIG4_AFMT_MPEG_INFO1 >+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 >+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 >+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc >+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL >+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L >+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L >+//DIG4_AFMT_GENERIC_HDR >+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L >+//DIG4_AFMT_GENERIC_0 >+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L >+//DIG4_AFMT_GENERIC_1 >+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L >+//DIG4_AFMT_GENERIC_2 >+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L >+//DIG4_AFMT_GENERIC_3 >+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L >+//DIG4_AFMT_GENERIC_4 >+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L >+//DIG4_AFMT_GENERIC_5 >+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L >+//DIG4_AFMT_GENERIC_6 >+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L >+//DIG4_AFMT_GENERIC_7 >+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 >+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 >+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 >+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 >+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL >+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L >+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L >+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L >+//DIG4_HDMI_GENERIC_PACKET_CONTROL1 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L >+//DIG4_HDMI_ACR_32_0 >+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc >+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L >+//DIG4_HDMI_ACR_32_1 >+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 >+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL >+//DIG4_HDMI_ACR_44_0 >+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc >+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L >+//DIG4_HDMI_ACR_44_1 >+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 >+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL >+//DIG4_HDMI_ACR_48_0 >+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc >+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L >+//DIG4_HDMI_ACR_48_1 >+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 >+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL >+//DIG4_HDMI_ACR_STATUS_0 >+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc >+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L >+//DIG4_HDMI_ACR_STATUS_1 >+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 >+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL >+//DIG4_AFMT_AUDIO_INFO0 >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L >+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L >+//DIG4_AFMT_AUDIO_INFO1 >+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 >+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb >+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf >+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 >+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL >+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L >+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L >+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L >+//DIG4_AFMT_60958_0 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L >+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L >+//DIG4_AFMT_60958_1 >+#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 >+#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 >+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 >+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 >+#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 >+#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL >+#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L >+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L >+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L >+#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L >+//DIG4_AFMT_AUDIO_CRC_CONTROL >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L >+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L >+//DIG4_AFMT_RAMP_CONTROL0 >+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 >+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f >+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL >+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L >+//DIG4_AFMT_RAMP_CONTROL1 >+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 >+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 >+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL >+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L >+//DIG4_AFMT_RAMP_CONTROL2 >+#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 >+#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL >+//DIG4_AFMT_RAMP_CONTROL3 >+#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 >+#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL >+//DIG4_AFMT_60958_2 >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L >+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L >+//DIG4_AFMT_AUDIO_CRC_RESULT >+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 >+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 >+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L >+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L >+//DIG4_AFMT_STATUS >+#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 >+#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 >+#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 >+#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e >+#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L >+#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L >+#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L >+#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L >+//DIG4_AFMT_AUDIO_PACKET_CONTROL >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L >+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L >+//DIG4_AFMT_VBI_PACKET_CONTROL >+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 >+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 >+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 >+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c >+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L >+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L >+//DIG4_AFMT_INFOFRAME_CONTROL0 >+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 >+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 >+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa >+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L >+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L >+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L >+//DIG4_AFMT_AUDIO_SRC_CONTROL >+#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 >+#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L >+//DIG4_DIG_BE_CNTL >+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 >+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 >+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 >+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 >+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 >+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c >+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L >+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L >+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L >+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L >+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L >+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L >+//DIG4_DIG_BE_EN_CNTL >+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 >+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 >+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L >+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L >+//DIG4_TMDS_CNTL >+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 >+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L >+//DIG4_TMDS_CONTROL_CHAR >+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 >+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 >+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 >+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 >+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L >+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L >+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L >+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L >+//DIG4_TMDS_CONTROL0_FEEDBACK >+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 >+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 >+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L >+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L >+//DIG4_TMDS_STEREOSYNC_CTL_SEL >+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 >+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L >+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 >+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 >+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 >+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL >+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L >+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 >+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 >+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 >+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL >+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L >+//DIG4_TMDS_CTL_BITS >+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 >+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 >+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 >+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 >+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L >+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L >+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L >+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L >+//DIG4_TMDS_DCBALANCER_CONTROL >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L >+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L >+//DIG4_TMDS_SYNC_DCBALANCE_CHAR >+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 >+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 >+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL >+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L >+//DIG4_TMDS_CTL0_1_GEN_CNTL >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L >+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L >+//DIG4_TMDS_CTL2_3_GEN_CNTL >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L >+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L >+//DIG4_DIG_VERSION >+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 >+#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L >+//DIG4_DIG_LANE_ENABLE >+#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 >+#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 >+#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 >+#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 >+#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 >+#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L >+#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L >+#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L >+#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L >+#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L >+//DIG4_AFMT_CNTL >+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 >+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 >+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L >+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L >+//DIG4_AFMT_VBI_PACKET_CONTROL1 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L >+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L >+//DIG4_HDMI_GENERIC_PACKET_CONTROL5 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L >+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L >+//DIG4_FORCE_DIG_DISABLE >+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 >+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L >+ >+ >+// addressBlock: dce_dc_dio_dp4_dispdec >+//DP4_DP_LINK_CNTL >+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 >+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 >+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 >+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L >+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L >+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L >+//DP4_DP_PIXEL_FORMAT >+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 >+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 >+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c >+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L >+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L >+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L >+//DP4_DP_MSA_COLORIMETRY >+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 >+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L >+//DP4_DP_CONFIG >+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 >+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L >+//DP4_DP_VID_STREAM_CNTL >+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 >+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 >+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 >+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 >+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L >+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L >+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L >+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L >+//DP4_DP_STEER_FIFO >+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 >+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 >+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 >+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 >+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 >+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 >+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc >+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L >+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L >+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L >+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L >+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L >+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L >+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L >+//DP4_DP_MSA_MISC >+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 >+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 >+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 >+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 >+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL >+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L >+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L >+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L >+//DP4_DP_VID_TIMING >+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 >+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 >+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa >+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc >+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 >+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L >+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L >+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L >+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L >+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L >+//DP4_DP_VID_N >+#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 >+#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL >+//DP4_DP_VID_M >+#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 >+#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL >+//DP4_DP_LINK_FRAMING_CNTL >+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 >+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 >+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c >+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL >+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L >+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L >+//DP4_DP_HBR2_EYE_PATTERN >+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 >+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L >+//DP4_DP_VID_MSA_VBID >+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 >+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 >+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL >+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L >+//DP4_DP_VID_INTERRUPT_CNTL >+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 >+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 >+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 >+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L >+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L >+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L >+//DP4_DP_DPHY_CNTL >+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 >+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 >+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 >+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 >+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 >+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 >+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 >+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 >+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 >+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L >+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L >+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L >+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L >+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L >+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L >+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L >+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L >+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L >+//DP4_DP_DPHY_TRAINING_PATTERN_SEL >+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 >+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L >+//DP4_DP_DPHY_SYM0 >+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 >+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa >+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 >+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL >+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L >+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L >+//DP4_DP_DPHY_SYM1 >+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 >+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa >+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 >+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL >+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L >+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L >+//DP4_DP_DPHY_SYM2 >+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 >+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa >+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL >+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L >+//DP4_DP_DPHY_8B10B_CNTL >+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 >+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 >+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 >+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L >+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L >+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L >+//DP4_DP_DPHY_PRBS_CNTL >+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 >+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 >+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 >+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L >+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L >+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L >+//DP4_DP_DPHY_SCRAM_CNTL >+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 >+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 >+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 >+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 >+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L >+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L >+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L >+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L >+//DP4_DP_DPHY_CRC_EN >+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 >+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 >+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 >+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L >+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L >+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L >+//DP4_DP_DPHY_CRC_CNTL >+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 >+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 >+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 >+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L >+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L >+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L >+//DP4_DP_DPHY_CRC_RESULT >+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 >+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 >+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 >+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 >+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL >+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L >+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L >+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L >+//DP4_DP_DPHY_CRC_MST_CNTL >+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 >+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 >+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL >+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L >+//DP4_DP_DPHY_CRC_MST_STATUS >+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 >+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 >+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 >+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L >+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L >+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L >+//DP4_DP_DPHY_FAST_TRAINING >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L >+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L >+//DP4_DP_DPHY_FAST_TRAINING_STATUS >+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 >+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 >+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 >+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc >+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L >+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L >+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L >+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L >+//DP4_DP_SEC_CNTL >+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 >+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 >+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 >+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc >+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b >+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c >+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L >+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L >+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L >+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L >+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L >+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L >+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L >+//DP4_DP_SEC_CNTL1 >+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 >+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L >+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L >+//DP4_DP_SEC_FRAMING1 >+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 >+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL >+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP4_DP_SEC_FRAMING2 >+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 >+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL >+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP4_DP_SEC_FRAMING3 >+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 >+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 >+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL >+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L >+//DP4_DP_SEC_FRAMING4 >+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 >+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 >+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 >+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c >+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d >+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L >+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L >+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L >+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L >+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L >+//DP4_DP_SEC_AUD_N >+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 >+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL >+//DP4_DP_SEC_AUD_N_READBACK >+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 >+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL >+//DP4_DP_SEC_AUD_M >+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 >+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL >+//DP4_DP_SEC_AUD_M_READBACK >+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 >+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL >+//DP4_DP_SEC_TIMESTAMP >+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 >+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L >+//DP4_DP_SEC_PACKET_CNTL >+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 >+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 >+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 >+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 >+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL >+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L >+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L >+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L >+//DP4_DP_MSE_RATE_CNTL >+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 >+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a >+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL >+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L >+//DP4_DP_MSE_RATE_UPDATE >+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 >+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L >+//DP4_DP_MSE_SAT0 >+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 >+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 >+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 >+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 >+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L >+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L >+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L >+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L >+//DP4_DP_MSE_SAT1 >+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 >+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 >+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 >+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 >+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L >+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L >+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L >+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L >+//DP4_DP_MSE_SAT2 >+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 >+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 >+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 >+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 >+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L >+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L >+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L >+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L >+//DP4_DP_MSE_SAT_UPDATE >+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 >+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 >+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L >+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L >+//DP4_DP_MSE_LINK_TIMING >+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 >+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 >+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL >+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L >+//DP4_DP_MSE_MISC_CNTL >+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 >+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 >+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 >+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L >+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L >+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L >+//DP4_DP_DPHY_BS_SR_SWAP_CNTL >+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 >+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf >+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 >+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL >+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L >+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L >+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL >+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 >+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L >+//DP4_DP_MSE_SAT0_STATUS >+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 >+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 >+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 >+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 >+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L >+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L >+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L >+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L >+//DP4_DP_MSE_SAT1_STATUS >+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 >+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 >+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 >+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 >+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L >+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L >+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L >+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L >+//DP4_DP_MSE_SAT2_STATUS >+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 >+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 >+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 >+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 >+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L >+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L >+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L >+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L >+//DP4_DP_MSA_TIMING_PARAM1 >+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 >+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 >+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL >+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L >+//DP4_DP_MSA_TIMING_PARAM2 >+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 >+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 >+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL >+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L >+//DP4_DP_MSA_TIMING_PARAM3 >+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 >+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf >+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 >+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f >+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL >+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L >+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L >+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L >+//DP4_DP_MSA_TIMING_PARAM4 >+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 >+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 >+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL >+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L >+//DP4_DP_MSO_CNTL >+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c >+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L >+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L >+//DP4_DP_MSO_CNTL1 >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L >+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L >+//DP4_DP_DSC_CNTL >+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 >+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 >+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L >+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L >+//DP4_DP_SEC_CNTL2 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L >+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L >+//DP4_DP_SEC_CNTL3 >+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 >+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 >+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL >+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L >+//DP4_DP_SEC_CNTL4 >+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 >+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 >+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL >+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L >+//DP4_DP_SEC_CNTL5 >+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 >+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 >+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL >+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L >+//DP4_DP_SEC_CNTL6 >+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 >+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL >+//DP4_DP_SEC_CNTL7 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L >+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L >+//DP4_DP_DB_CNTL >+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 >+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 >+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 >+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 >+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc >+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf >+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 >+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 >+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L >+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L >+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L >+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L >+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L >+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L >+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L >+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L >+//DP4_DP_MSA_VBID_MISC >+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 >+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 >+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 >+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 >+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc >+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd >+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf >+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 >+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L >+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L >+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L >+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L >+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L >+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L >+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L >+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L >+//DP4_DP_SEC_METADATA_TRANSMISSION >+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 >+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 >+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 >+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 >+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L >+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L >+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L >+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L >+//DP4_DP_DSC_BYTES_PER_PIXEL >+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 >+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL >+//DP4_DP_ALPM_CNTL >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 >+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L >+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L >+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dcio_dcio_dispdec >+//DC_GENERICA >+#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 >+#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 >+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc >+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 >+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 >+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 >+#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L >+#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L >+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L >+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L >+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L >+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L >+//DC_GENERICB >+#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 >+#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 >+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc >+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 >+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 >+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 >+#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L >+#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L >+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L >+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L >+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L >+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L >+//DC_REF_CLK_CNTL >+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 >+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 >+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L >+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L >+//UNIPHYA_LINK_CNTL >+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 >+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 >+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 >+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc >+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd >+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe >+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf >+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 >+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 >+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L >+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L >+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L >+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L >+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L >+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L >+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L >+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L >+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L >+//UNIPHYA_CHANNEL_XBAR_CNTL >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L >+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L >+//UNIPHYB_LINK_CNTL >+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 >+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 >+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 >+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc >+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd >+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe >+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf >+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 >+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 >+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L >+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L >+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L >+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L >+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L >+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L >+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L >+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L >+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L >+//UNIPHYB_CHANNEL_XBAR_CNTL >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L >+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L >+//UNIPHYC_LINK_CNTL >+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 >+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 >+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 >+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc >+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd >+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe >+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf >+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 >+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 >+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L >+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L >+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L >+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L >+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L >+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L >+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L >+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L >+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L >+//UNIPHYC_CHANNEL_XBAR_CNTL >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L >+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L >+//UNIPHYD_LINK_CNTL >+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 >+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 >+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 >+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc >+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd >+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe >+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf >+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 >+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 >+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L >+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L >+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L >+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L >+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L >+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L >+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L >+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L >+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L >+//UNIPHYD_CHANNEL_XBAR_CNTL >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L >+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L >+//UNIPHYE_LINK_CNTL >+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 >+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 >+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 >+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc >+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd >+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe >+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf >+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 >+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 >+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L >+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L >+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L >+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L >+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L >+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L >+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L >+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L >+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L >+//UNIPHYE_CHANNEL_XBAR_CNTL >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L >+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L >+//DCIO_WRCMD_DELAY >+#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 >+#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 >+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc >+#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10 >+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 >+#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0x000000F0L >+#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L >+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L >+#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L >+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L >+//DC_PINSTRAPS >+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd >+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe >+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 >+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 >+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L >+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L >+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L >+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0x000E0000L >+//LVTMA_PWRSEQ_CNTL >+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa >+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 >+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a >+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L >+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L >+//LVTMA_PWRSEQ_STATE >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L >+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L >+//LVTMA_PWRSEQ_REF_DIV >+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 >+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 >+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL >+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L >+//LVTMA_PWRSEQ_DELAY1 >+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 >+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 >+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 >+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 >+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL >+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L >+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L >+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L >+//LVTMA_PWRSEQ_DELAY2 >+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 >+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 >+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 >+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 >+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL >+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L >+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L >+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L >+//BL_PWM_CNTL >+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 >+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e >+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f >+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL >+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L >+#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L >+//BL_PWM_CNTL2 >+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 >+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e >+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f >+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL >+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L >+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L >+//BL_PWM_PERIOD_CNTL >+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 >+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 >+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL >+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L >+//BL_PWM_GRP1_REG_LOCK >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L >+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L >+//DCIO_GSL_GENLK_PAD_CNTL >+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 >+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 >+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 >+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 >+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L >+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L >+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L >+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L >+//DCIO_GSL_SWAPLOCK_PAD_CNTL >+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 >+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 >+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 >+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 >+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L >+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L >+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L >+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L >+//DCIO_CLOCK_CNTL >+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 >+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 >+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL >+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L >+//DCIO_SOFT_RESET >+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 >+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 >+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 >+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 >+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 >+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 >+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 >+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 >+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 >+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 >+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa >+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb >+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc >+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd >+#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 >+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 >+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 >+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a >+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L >+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L >+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L >+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L >+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L >+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L >+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L >+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L >+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L >+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L >+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L >+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L >+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L >+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L >+#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00010000L >+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L >+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x01000000L >+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L >+ >+ >+// addressBlock: dce_dc_dcio_dcio_chip_dispdec >+//DC_GPIO_GENERIC_MASK >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L >+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L >+//DC_GPIO_GENERIC_A >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L >+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L >+//DC_GPIO_GENERIC_EN >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L >+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L >+//DC_GPIO_GENERIC_Y >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L >+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L >+//DC_GPIO_DDC1_MASK >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe >+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 >+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 >+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L >+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L >+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L >+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L >+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L >+//DC_GPIO_DDC1_A >+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 >+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 >+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L >+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L >+//DC_GPIO_DDC1_EN >+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 >+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 >+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L >+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L >+//DC_GPIO_DDC1_Y >+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 >+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 >+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L >+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L >+//DC_GPIO_DDC2_MASK >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe >+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 >+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 >+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L >+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L >+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L >+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L >+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L >+//DC_GPIO_DDC2_A >+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 >+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 >+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L >+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L >+//DC_GPIO_DDC2_EN >+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 >+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 >+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L >+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L >+//DC_GPIO_DDC2_Y >+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 >+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 >+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L >+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L >+//DC_GPIO_DDC3_MASK >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe >+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 >+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 >+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L >+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L >+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L >+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L >+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L >+//DC_GPIO_DDC3_A >+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 >+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 >+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L >+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L >+//DC_GPIO_DDC3_EN >+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 >+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 >+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L >+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L >+//DC_GPIO_DDC3_Y >+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 >+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 >+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L >+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L >+//DC_GPIO_DDC4_MASK >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe >+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 >+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 >+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L >+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L >+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L >+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L >+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L >+//DC_GPIO_DDC4_A >+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 >+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 >+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L >+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L >+//DC_GPIO_DDC4_EN >+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 >+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 >+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L >+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L >+//DC_GPIO_DDC4_Y >+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 >+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 >+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L >+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L >+//DC_GPIO_DDC5_MASK >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe >+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 >+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 >+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L >+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L >+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L >+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L >+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L >+//DC_GPIO_DDC5_A >+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 >+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 >+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L >+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L >+//DC_GPIO_DDC5_EN >+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 >+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 >+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L >+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L >+//DC_GPIO_DDC5_Y >+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 >+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 >+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L >+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L >+//DC_GPIO_DDCVGA_MASK >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe >+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 >+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 >+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L >+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L >+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L >+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L >+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L >+//DC_GPIO_DDCVGA_A >+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 >+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 >+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L >+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L >+//DC_GPIO_DDCVGA_EN >+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 >+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 >+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L >+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L >+//DC_GPIO_DDCVGA_Y >+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 >+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 >+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L >+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L >+//DC_GPIO_GENLK_MASK >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L >+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L >+//DC_GPIO_GENLK_A >+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 >+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 >+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 >+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 >+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L >+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L >+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L >+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L >+//DC_GPIO_GENLK_EN >+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 >+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 >+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 >+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 >+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L >+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L >+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L >+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L >+//DC_GPIO_GENLK_Y >+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 >+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 >+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 >+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 >+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L >+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L >+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L >+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L >+//DC_GPIO_HPD_MASK >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 >+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 >+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 >+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L >+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L >+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L >+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L >+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L >+//DC_GPIO_HPD_A >+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 >+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 >+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 >+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 >+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a >+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c >+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L >+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L >+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L >+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L >+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L >+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L >+//DC_GPIO_HPD_EN >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 >+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 >+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 >+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 >+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 >+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 >+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 >+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 >+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 >+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 >+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 >+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 >+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 >+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 >+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 >+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c >+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d >+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L >+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L >+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L >+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L >+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L >+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L >+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L >+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L >+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L >+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L >+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L >+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L >+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L >+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L >+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L >+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L >+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L >+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L >+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L >+//DC_GPIO_HPD_Y >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L >+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L >+//DC_GPIO_PWRSEQ_MASK >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L >+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L >+//DC_GPIO_PWRSEQ_A >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L >+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L >+//DC_GPIO_PWRSEQ_EN >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L >+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L >+//DC_GPIO_PWRSEQ_Y >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L >+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L >+//DC_GPIO_PAD_STRENGTH_1 >+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 >+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 >+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 >+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc >+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 >+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 >+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 >+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c >+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL >+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L >+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L >+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L >+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L >+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L >+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L >+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L >+//DC_GPIO_PAD_STRENGTH_2 >+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 >+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 >+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 >+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc >+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 >+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 >+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e >+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL >+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L >+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L >+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L >+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L >+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L >+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L >+//PHY_AUX_CNTL >+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 >+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 >+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 >+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 >+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 >+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 >+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 >+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 >+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0x8 >+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 >+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa >+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc >+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe >+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 >+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 >+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 >+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17 >+#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18 >+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x1c >+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L >+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L >+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L >+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L >+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L >+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L >+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L >+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L >+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00000100L >+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L >+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L >+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L >+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L >+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L >+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L >+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L >+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L >+#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L >+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x70000000L >+//DC_GPIO_TX12_EN >+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0 >+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 >+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2 >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 >+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L >+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L >+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L >+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L >+//DC_GPIO_AUX_CTRL_0 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L >+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L >+//DC_GPIO_AUX_CTRL_1 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xc >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00001000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L >+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0x40000000L >+//DC_GPIO_AUX_CTRL_2 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L >+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L >+//DC_GPIO_RXEN >+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 >+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 >+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 >+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 >+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 >+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 >+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 >+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 >+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 >+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa >+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb >+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc >+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd >+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe >+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf >+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 >+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 >+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 >+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 >+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14 >+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15 >+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16 >+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L >+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L >+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L >+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L >+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L >+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L >+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L >+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L >+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L >+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L >+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L >+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L >+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L >+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L >+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L >+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L >+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L >+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L >+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L >+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L >+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L >+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L >+//DC_GPIO_PULLUPEN >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 >+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 >+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT 0xf >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT 0x10 >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT 0x11 >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT 0x12 >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT 0x13 >+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT 0x14 >+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT 0x15 >+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT 0x16 >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L >+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L >+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L >+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK 0x00008000L >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK 0x00010000L >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK 0x00020000L >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK 0x00040000L >+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK 0x00080000L >+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK 0x00100000L >+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK 0x00200000L >+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK 0x00400000L >+//DC_GPIO_AUX_CTRL_3 >+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 >+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 >+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 >+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 >+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 >+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 >+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 >+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 >+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa >+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb >+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc >+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd >+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 >+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 >+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 >+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 >+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 >+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a >+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L >+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L >+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L >+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L >+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L >+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L >+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L >+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L >+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L >+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L >+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L >+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L >+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L >+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L >+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L >+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L >+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L >+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L >+//DC_GPIO_AUX_CTRL_4 >+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 >+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 >+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 >+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc >+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 >+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 >+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL >+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L >+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L >+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L >+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L >+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L >+//DC_GPIO_AUX_CTRL_5 >+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 >+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 >+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 >+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 >+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 >+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 >+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 >+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 >+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 >+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 >+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 >+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 >+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 >+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 >+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a >+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b >+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c >+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d >+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L >+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL >+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L >+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L >+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L >+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L >+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L >+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L >+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L >+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L >+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L >+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L >+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L >+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L >+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L >+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L >+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L >+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L >+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L >+//AUXI2C_PAD_ALL_PWR_OK >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L >+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L >+ >+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec >+//DSC_TOP0_DSC_TOP_CONTROL >+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 >+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 >+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L >+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L >+//DSC_TOP0_DSC_DEBUG_CONTROL >+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 >+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 >+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L >+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L >+ >+ >+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec >+//DSCCIF0_DSCCIF_CONFIG0 >+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 >+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 >+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 >+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc >+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 >+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L >+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L >+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L >+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L >+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L >+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+//DSCCIF0_DSCCIF_CONFIG1 >+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 >+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 >+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec >+//DSCC0_DSCC_CONFIG0 >+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 >+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 >+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 >+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 >+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL >+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L >+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L >+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L >+//DSCC0_DSCC_CONFIG1 >+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 >+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 >+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL >+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L >+//DSCC0_DSCC_STATUS >+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 >+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L >+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L >+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L >+//DSCC0_DSCC_PPS_CONFIG0 >+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 >+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 >+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 >+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c >+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL >+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L >+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L >+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L >+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L >+//DSCC0_DSCC_PPS_CONFIG1 >+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa >+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb >+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc >+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd >+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe >+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf >+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL >+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L >+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L >+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L >+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L >+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L >+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L >+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG2 >+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG3 >+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL >+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG4 >+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL >+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG5 >+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL >+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG6 >+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 >+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL >+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L >+//DSCC0_DSCC_PPS_CONFIG7 >+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG8 >+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG9 >+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL >+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG10 >+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 >+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL >+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L >+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L >+//DSCC0_DSCC_PPS_CONFIG11 >+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 >+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 >+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c >+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL >+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L >+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L >+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L >+//DSCC0_DSCC_PPS_CONFIG12 >+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 >+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 >+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL >+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L >+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L >+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L >+//DSCC0_DSCC_PPS_CONFIG13 >+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 >+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 >+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL >+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L >+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L >+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L >+//DSCC0_DSCC_PPS_CONFIG14 >+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 >+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 >+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL >+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L >+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L >+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L >+//DSCC0_DSCC_PPS_CONFIG15 >+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 >+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 >+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a >+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL >+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L >+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L >+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L >+//DSCC0_DSCC_PPS_CONFIG16 >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L >+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L >+//DSCC0_DSCC_PPS_CONFIG17 >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L >+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L >+//DSCC0_DSCC_PPS_CONFIG18 >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L >+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L >+//DSCC0_DSCC_PPS_CONFIG19 >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L >+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L >+//DSCC0_DSCC_PPS_CONFIG20 >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L >+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L >+//DSCC0_DSCC_PPS_CONFIG21 >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L >+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L >+//DSCC0_DSCC_PPS_CONFIG22 >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L >+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L >+//DSCC0_DSCC_MEM_POWER_CONTROL >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L >+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L >+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER >+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER >+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER >+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER >+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER >+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER >+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC0_DSCC_MAX_ABS_ERROR0 >+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 >+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL >+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L >+//DSCC0_DSCC_MAX_ABS_ERROR1 >+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL >+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE >+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 >+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 >+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 >+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 >+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL >+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L >+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L >+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L >+ >+ >+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON19_PERFCOUNTER_CNTL >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON19_PERFCOUNTER_CNTL2 >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON19_PERFCOUNTER_STATE >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON19_PERFMON_CNTL >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON19_PERFMON_CNTL2 >+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON19_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON19_PERFMON_CVALUE_LOW >+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON19_PERFMON_HI >+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON19_PERFMON_LOW >+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec >+//DSC_TOP1_DSC_TOP_CONTROL >+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 >+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 >+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L >+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L >+//DSC_TOP1_DSC_DEBUG_CONTROL >+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 >+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 >+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L >+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L >+ >+ >+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec >+//DSCCIF1_DSCCIF_CONFIG0 >+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 >+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 >+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 >+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc >+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 >+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L >+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L >+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L >+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L >+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L >+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+//DSCCIF1_DSCCIF_CONFIG1 >+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 >+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 >+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec >+//DSCC1_DSCC_CONFIG0 >+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 >+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 >+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 >+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 >+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL >+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L >+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L >+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L >+//DSCC1_DSCC_CONFIG1 >+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 >+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 >+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL >+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L >+//DSCC1_DSCC_STATUS >+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 >+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L >+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L >+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L >+//DSCC1_DSCC_PPS_CONFIG0 >+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 >+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 >+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 >+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c >+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL >+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L >+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L >+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L >+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L >+//DSCC1_DSCC_PPS_CONFIG1 >+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa >+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb >+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc >+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd >+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe >+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf >+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL >+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L >+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L >+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L >+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L >+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L >+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L >+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG2 >+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG3 >+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL >+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG4 >+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL >+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG5 >+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL >+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG6 >+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 >+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL >+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L >+//DSCC1_DSCC_PPS_CONFIG7 >+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG8 >+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG9 >+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL >+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG10 >+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 >+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL >+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L >+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L >+//DSCC1_DSCC_PPS_CONFIG11 >+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 >+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 >+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c >+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL >+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L >+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L >+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L >+//DSCC1_DSCC_PPS_CONFIG12 >+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 >+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 >+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL >+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L >+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L >+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L >+//DSCC1_DSCC_PPS_CONFIG13 >+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 >+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 >+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL >+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L >+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L >+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L >+//DSCC1_DSCC_PPS_CONFIG14 >+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 >+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 >+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL >+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L >+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L >+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L >+//DSCC1_DSCC_PPS_CONFIG15 >+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 >+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 >+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a >+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL >+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L >+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L >+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L >+//DSCC1_DSCC_PPS_CONFIG16 >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L >+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L >+//DSCC1_DSCC_PPS_CONFIG17 >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L >+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L >+//DSCC1_DSCC_PPS_CONFIG18 >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L >+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L >+//DSCC1_DSCC_PPS_CONFIG19 >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L >+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L >+//DSCC1_DSCC_PPS_CONFIG20 >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L >+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L >+//DSCC1_DSCC_PPS_CONFIG21 >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L >+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L >+//DSCC1_DSCC_PPS_CONFIG22 >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L >+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L >+//DSCC1_DSCC_MEM_POWER_CONTROL >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L >+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L >+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER >+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER >+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER >+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER >+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER >+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER >+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC1_DSCC_MAX_ABS_ERROR0 >+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 >+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL >+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L >+//DSCC1_DSCC_MAX_ABS_ERROR1 >+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL >+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE >+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 >+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 >+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 >+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 >+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL >+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L >+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L >+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L >+ >+ >+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON20_PERFCOUNTER_CNTL >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON20_PERFCOUNTER_CNTL2 >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON20_PERFCOUNTER_STATE >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON20_PERFMON_CNTL >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON20_PERFMON_CNTL2 >+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON20_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON20_PERFMON_CVALUE_LOW >+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON20_PERFMON_HI >+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON20_PERFMON_LOW >+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec >+//DSC_TOP2_DSC_TOP_CONTROL >+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 >+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 >+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L >+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L >+//DSC_TOP2_DSC_DEBUG_CONTROL >+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 >+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 >+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L >+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L >+ >+ >+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec >+//DSCCIF2_DSCCIF_CONFIG0 >+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 >+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 >+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 >+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc >+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 >+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L >+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L >+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L >+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L >+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L >+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+//DSCCIF2_DSCCIF_CONFIG1 >+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 >+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 >+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec >+//DSCC2_DSCC_CONFIG0 >+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 >+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 >+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 >+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 >+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL >+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L >+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L >+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L >+//DSCC2_DSCC_CONFIG1 >+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 >+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 >+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL >+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L >+//DSCC2_DSCC_STATUS >+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 >+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L >+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L >+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L >+//DSCC2_DSCC_PPS_CONFIG0 >+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 >+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 >+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 >+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c >+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL >+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L >+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L >+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L >+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L >+//DSCC2_DSCC_PPS_CONFIG1 >+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa >+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb >+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc >+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd >+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe >+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf >+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL >+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L >+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L >+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L >+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L >+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L >+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L >+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG2 >+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG3 >+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL >+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG4 >+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL >+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG5 >+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL >+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG6 >+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 >+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL >+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L >+//DSCC2_DSCC_PPS_CONFIG7 >+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG8 >+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG9 >+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL >+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG10 >+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 >+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL >+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L >+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L >+//DSCC2_DSCC_PPS_CONFIG11 >+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 >+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 >+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c >+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL >+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L >+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L >+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L >+//DSCC2_DSCC_PPS_CONFIG12 >+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 >+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 >+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL >+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L >+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L >+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L >+//DSCC2_DSCC_PPS_CONFIG13 >+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 >+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 >+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL >+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L >+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L >+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L >+//DSCC2_DSCC_PPS_CONFIG14 >+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 >+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 >+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL >+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L >+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L >+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L >+//DSCC2_DSCC_PPS_CONFIG15 >+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 >+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 >+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a >+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL >+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L >+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L >+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L >+//DSCC2_DSCC_PPS_CONFIG16 >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L >+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L >+//DSCC2_DSCC_PPS_CONFIG17 >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L >+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L >+//DSCC2_DSCC_PPS_CONFIG18 >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L >+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L >+//DSCC2_DSCC_PPS_CONFIG19 >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L >+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L >+//DSCC2_DSCC_PPS_CONFIG20 >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L >+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L >+//DSCC2_DSCC_PPS_CONFIG21 >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L >+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L >+//DSCC2_DSCC_PPS_CONFIG22 >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L >+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L >+//DSCC2_DSCC_MEM_POWER_CONTROL >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L >+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L >+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER >+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER >+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER >+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER >+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER >+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER >+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC2_DSCC_MAX_ABS_ERROR0 >+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 >+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL >+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L >+//DSCC2_DSCC_MAX_ABS_ERROR1 >+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL >+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE >+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 >+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 >+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 >+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 >+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL >+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L >+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L >+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L >+ >+ >+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON21_PERFCOUNTER_CNTL >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON21_PERFCOUNTER_CNTL2 >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON21_PERFCOUNTER_STATE >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON21_PERFMON_CNTL >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON21_PERFMON_CNTL2 >+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON21_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON21_PERFMON_CVALUE_LOW >+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON21_PERFMON_HI >+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON21_PERFMON_LOW >+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec >+//DSC_TOP3_DSC_TOP_CONTROL >+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 >+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 >+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L >+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L >+//DSC_TOP3_DSC_DEBUG_CONTROL >+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 >+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 >+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L >+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L >+ >+ >+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec >+//DSCCIF3_DSCCIF_CONFIG0 >+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 >+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 >+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 >+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc >+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 >+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L >+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L >+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L >+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L >+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L >+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+//DSCCIF3_DSCCIF_CONFIG1 >+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 >+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 >+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec >+//DSCC3_DSCC_CONFIG0 >+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 >+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 >+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 >+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 >+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL >+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L >+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L >+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L >+//DSCC3_DSCC_CONFIG1 >+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 >+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 >+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL >+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L >+//DSCC3_DSCC_STATUS >+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 >+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L >+//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L >+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L >+//DSCC3_DSCC_PPS_CONFIG0 >+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 >+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 >+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 >+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c >+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL >+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L >+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L >+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L >+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L >+//DSCC3_DSCC_PPS_CONFIG1 >+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa >+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb >+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc >+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd >+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe >+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf >+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL >+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L >+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L >+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L >+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L >+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L >+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L >+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG2 >+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG3 >+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL >+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG4 >+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL >+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG5 >+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL >+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG6 >+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 >+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL >+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L >+//DSCC3_DSCC_PPS_CONFIG7 >+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG8 >+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG9 >+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL >+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG10 >+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 >+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL >+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L >+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L >+//DSCC3_DSCC_PPS_CONFIG11 >+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 >+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 >+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c >+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL >+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L >+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L >+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L >+//DSCC3_DSCC_PPS_CONFIG12 >+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 >+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 >+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL >+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L >+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L >+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L >+//DSCC3_DSCC_PPS_CONFIG13 >+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 >+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 >+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL >+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L >+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L >+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L >+//DSCC3_DSCC_PPS_CONFIG14 >+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 >+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 >+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL >+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L >+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L >+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L >+//DSCC3_DSCC_PPS_CONFIG15 >+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 >+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 >+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a >+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL >+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L >+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L >+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L >+//DSCC3_DSCC_PPS_CONFIG16 >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L >+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L >+//DSCC3_DSCC_PPS_CONFIG17 >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L >+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L >+//DSCC3_DSCC_PPS_CONFIG18 >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L >+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L >+//DSCC3_DSCC_PPS_CONFIG19 >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L >+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L >+//DSCC3_DSCC_PPS_CONFIG20 >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L >+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L >+//DSCC3_DSCC_PPS_CONFIG21 >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L >+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L >+//DSCC3_DSCC_PPS_CONFIG22 >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L >+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L >+//DSCC3_DSCC_MEM_POWER_CONTROL >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L >+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L >+//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER >+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER >+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER >+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER >+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER >+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER >+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC3_DSCC_MAX_ABS_ERROR0 >+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 >+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL >+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L >+//DSCC3_DSCC_MAX_ABS_ERROR1 >+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL >+//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE >+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 >+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 >+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 >+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 >+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL >+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L >+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L >+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L >+ >+ >+// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON22_PERFCOUNTER_CNTL >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON22_PERFCOUNTER_CNTL2 >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON22_PERFCOUNTER_STATE >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON22_PERFMON_CNTL >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON22_PERFMON_CNTL2 >+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON22_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON22_PERFMON_CVALUE_LOW >+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON22_PERFMON_HI >+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON22_PERFMON_LOW >+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec >+//DSC_TOP4_DSC_TOP_CONTROL >+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 >+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 >+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L >+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L >+//DSC_TOP4_DSC_DEBUG_CONTROL >+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 >+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 >+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L >+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L >+ >+ >+// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec >+//DSCCIF4_DSCCIF_CONFIG0 >+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 >+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 >+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 >+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc >+#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 >+#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L >+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L >+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L >+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L >+#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L >+#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+//DSCCIF4_DSCCIF_CONFIG1 >+#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 >+#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 >+#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec >+//DSCC4_DSCC_CONFIG0 >+#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 >+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 >+#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 >+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 >+#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL >+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L >+#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L >+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L >+//DSCC4_DSCC_CONFIG1 >+#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 >+#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 >+#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL >+#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L >+//DSCC4_DSCC_STATUS >+#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 >+#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L >+//DSCC4_DSCC_INTERRUPT_CONTROL_STATUS >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L >+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L >+//DSCC4_DSCC_PPS_CONFIG0 >+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 >+#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 >+#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 >+#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c >+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL >+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L >+#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L >+#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L >+#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L >+//DSCC4_DSCC_PPS_CONFIG1 >+#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa >+#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb >+#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc >+#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd >+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe >+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf >+#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL >+#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L >+#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L >+#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L >+#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L >+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L >+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L >+#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG2 >+#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG3 >+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL >+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG4 >+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL >+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG5 >+#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL >+#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG6 >+#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 >+#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL >+#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L >+//DSCC4_DSCC_PPS_CONFIG7 >+#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG8 >+#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG9 >+#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL >+#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG10 >+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 >+#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL >+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L >+#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L >+//DSCC4_DSCC_PPS_CONFIG11 >+#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 >+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 >+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c >+#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL >+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L >+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L >+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L >+//DSCC4_DSCC_PPS_CONFIG12 >+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 >+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 >+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL >+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L >+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L >+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L >+//DSCC4_DSCC_PPS_CONFIG13 >+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 >+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 >+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL >+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L >+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L >+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L >+//DSCC4_DSCC_PPS_CONFIG14 >+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 >+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 >+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL >+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L >+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L >+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L >+//DSCC4_DSCC_PPS_CONFIG15 >+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 >+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 >+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a >+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL >+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L >+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L >+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L >+//DSCC4_DSCC_PPS_CONFIG16 >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L >+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L >+//DSCC4_DSCC_PPS_CONFIG17 >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L >+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L >+//DSCC4_DSCC_PPS_CONFIG18 >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L >+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L >+//DSCC4_DSCC_PPS_CONFIG19 >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L >+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L >+//DSCC4_DSCC_PPS_CONFIG20 >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L >+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L >+//DSCC4_DSCC_PPS_CONFIG21 >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L >+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L >+//DSCC4_DSCC_PPS_CONFIG22 >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L >+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L >+//DSCC4_DSCC_MEM_POWER_CONTROL >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L >+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L >+//DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER >+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER >+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER >+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER >+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER >+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER >+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC4_DSCC_MAX_ABS_ERROR0 >+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 >+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL >+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L >+//DSCC4_DSCC_MAX_ABS_ERROR1 >+#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL >+//DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE >+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 >+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 >+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 >+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 >+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL >+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L >+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L >+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L >+ >+ >+// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON23_PERFCOUNTER_CNTL >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON23_PERFCOUNTER_CNTL2 >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON23_PERFCOUNTER_STATE >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON23_PERFMON_CNTL >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON23_PERFMON_CNTL2 >+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON23_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON23_PERFMON_CVALUE_LOW >+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON23_PERFMON_HI >+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON23_PERFMON_LOW >+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec >+//DSC_TOP5_DSC_TOP_CONTROL >+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 >+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 >+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 >+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L >+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L >+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L >+//DSC_TOP5_DSC_DEBUG_CONTROL >+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 >+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 >+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L >+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L >+ >+ >+// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec >+//DSCCIF5_DSCCIF_CONFIG0 >+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 >+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 >+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 >+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc >+#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 >+#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 >+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L >+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L >+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L >+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L >+#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L >+#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L >+//DSCCIF5_DSCCIF_CONFIG1 >+#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 >+#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 >+#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L >+ >+ >+// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec >+//DSCC5_DSCC_CONFIG0 >+#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 >+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 >+#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 >+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 >+#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL >+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L >+#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L >+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L >+//DSCC5_DSCC_CONFIG1 >+#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 >+#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 >+#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL >+#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L >+//DSCC5_DSCC_STATUS >+#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 >+#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L >+//DSCC5_DSCC_INTERRUPT_CONTROL_STATUS >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L >+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L >+//DSCC5_DSCC_PPS_CONFIG0 >+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 >+#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 >+#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 >+#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c >+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL >+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L >+#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L >+#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L >+#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L >+//DSCC5_DSCC_PPS_CONFIG1 >+#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa >+#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb >+#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc >+#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd >+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe >+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf >+#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL >+#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L >+#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L >+#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L >+#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L >+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L >+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L >+#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG2 >+#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL >+#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG3 >+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL >+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG4 >+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL >+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG5 >+#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL >+#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG6 >+#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 >+#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL >+#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L >+//DSCC5_DSCC_PPS_CONFIG7 >+#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG8 >+#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL >+#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG9 >+#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL >+#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG10 >+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 >+#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL >+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L >+#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L >+//DSCC5_DSCC_PPS_CONFIG11 >+#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 >+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 >+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c >+#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL >+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L >+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L >+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L >+//DSCC5_DSCC_PPS_CONFIG12 >+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 >+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 >+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL >+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L >+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L >+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L >+//DSCC5_DSCC_PPS_CONFIG13 >+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 >+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 >+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL >+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L >+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L >+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L >+//DSCC5_DSCC_PPS_CONFIG14 >+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 >+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 >+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL >+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L >+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L >+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L >+//DSCC5_DSCC_PPS_CONFIG15 >+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 >+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 >+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a >+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL >+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L >+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L >+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L >+//DSCC5_DSCC_PPS_CONFIG16 >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L >+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L >+//DSCC5_DSCC_PPS_CONFIG17 >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L >+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L >+//DSCC5_DSCC_PPS_CONFIG18 >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L >+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L >+//DSCC5_DSCC_PPS_CONFIG19 >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L >+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L >+//DSCC5_DSCC_PPS_CONFIG20 >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L >+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L >+//DSCC5_DSCC_PPS_CONFIG21 >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L >+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L >+//DSCC5_DSCC_PPS_CONFIG22 >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L >+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L >+//DSCC5_DSCC_MEM_POWER_CONTROL >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L >+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L >+//DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER >+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER >+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER >+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER >+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER >+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 >+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL >+//DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER >+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 >+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL >+//DSCC5_DSCC_MAX_ABS_ERROR0 >+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 >+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL >+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L >+//DSCC5_DSCC_MAX_ABS_ERROR1 >+#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 >+#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL >+//DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL >+#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL >+#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL >+#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL >+#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 >+#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL >+//DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE >+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 >+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 >+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 >+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 >+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL >+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L >+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L >+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L >+ >+ >+// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec >+//DC_PERFMON24_PERFCOUNTER_CNTL >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L >+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L >+//DC_PERFMON24_PERFCOUNTER_CNTL2 >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L >+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L >+//DC_PERFMON24_PERFCOUNTER_STATE >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L >+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L >+//DC_PERFMON24_PERFMON_CNTL >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L >+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L >+//DC_PERFMON24_PERFMON_CNTL2 >+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 >+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 >+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 >+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa >+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L >+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L >+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL >+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L >+//DC_PERFMON24_PERFMON_CVALUE_INT_MISC >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L >+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L >+//DC_PERFMON24_PERFMON_CVALUE_LOW >+#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 >+#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL >+//DC_PERFMON24_PERFMON_HI >+#define DC_PERFMON24_PERFMON_HI__PERFMON_HI__SHIFT 0x0 >+#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d >+#define DC_PERFMON24_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL >+#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L >+//DC_PERFMON24_PERFMON_LOW >+#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 >+#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: dce_dc_dmu_dmcub_dispdec >+//DMCUB_REGION0_OFFSET >+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION0_OFFSET_HIGH >+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION1_OFFSET >+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION1_OFFSET_HIGH >+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION2_OFFSET >+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION2_OFFSET_HIGH >+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION4_OFFSET >+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION4_OFFSET_HIGH >+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION5_OFFSET >+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION5_OFFSET_HIGH >+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION6_OFFSET >+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION6_OFFSET_HIGH >+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION7_OFFSET >+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION7_OFFSET_HIGH >+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION0_TOP_ADDRESS >+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L >+//DMCUB_REGION1_TOP_ADDRESS >+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L >+//DMCUB_REGION2_TOP_ADDRESS >+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L >+//DMCUB_REGION4_TOP_ADDRESS >+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L >+//DMCUB_REGION5_TOP_ADDRESS >+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L >+//DMCUB_REGION6_TOP_ADDRESS >+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L >+//DMCUB_REGION7_TOP_ADDRESS >+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW0_BASE_ADDRESS >+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL >+//DMCUB_REGION3_CW1_BASE_ADDRESS >+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL >+//DMCUB_REGION3_CW2_BASE_ADDRESS >+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL >+//DMCUB_REGION3_CW3_BASE_ADDRESS >+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL >+//DMCUB_REGION3_CW4_BASE_ADDRESS >+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL >+//DMCUB_REGION3_CW5_BASE_ADDRESS >+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL >+//DMCUB_REGION3_CW6_BASE_ADDRESS >+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL >+//DMCUB_REGION3_CW7_BASE_ADDRESS >+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL >+//DMCUB_REGION3_CW0_TOP_ADDRESS >+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW1_TOP_ADDRESS >+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW2_TOP_ADDRESS >+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW3_TOP_ADDRESS >+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW4_TOP_ADDRESS >+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW5_TOP_ADDRESS >+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW6_TOP_ADDRESS >+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW7_TOP_ADDRESS >+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0 >+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f >+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL >+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L >+//DMCUB_REGION3_CW0_OFFSET >+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION3_CW0_OFFSET_HIGH >+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION3_CW1_OFFSET >+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION3_CW1_OFFSET_HIGH >+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION3_CW2_OFFSET >+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION3_CW2_OFFSET_HIGH >+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION3_CW3_OFFSET >+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION3_CW3_OFFSET_HIGH >+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION3_CW4_OFFSET >+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION3_CW4_OFFSET_HIGH >+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION3_CW5_OFFSET >+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION3_CW5_OFFSET_HIGH >+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION3_CW6_OFFSET >+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION3_CW6_OFFSET_HIGH >+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_REGION3_CW7_OFFSET >+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8 >+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L >+//DMCUB_REGION3_CW7_OFFSET_HIGH >+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0 >+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL >+//DMCUB_INTERRUPT_ENABLE >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9 >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0xd >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L >+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00002000L >+//DMCUB_INTERRUPT_ACK >+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0 >+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1 >+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2 >+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3 >+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4 >+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5 >+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6 >+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7 >+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8 >+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9 >+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa >+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb >+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc >+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0xd >+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L >+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L >+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L >+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L >+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L >+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L >+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L >+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L >+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L >+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L >+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L >+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L >+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L >+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00002000L >+//DMCUB_INTERRUPT_STATUS >+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9 >+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa >+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb >+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc >+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0xd >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0xe >+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0xf >+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00002000L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00004000L >+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00008000L >+//DMCUB_INTERRUPT_TYPE >+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9 >+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa >+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb >+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc >+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0xd >+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L >+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00002000L >+//DMCUB_EXT_INTERRUPT_STATUS >+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0 >+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8 >+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL >+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L >+//DMCUB_EXT_INTERRUPT_CTXID >+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0 >+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL >+//DMCUB_EXT_INTERRUPT_ACK >+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0 >+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L >+//DMCUB_INST_FETCH_FAULT_ADDR >+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0 >+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL >+//DMCUB_DATA_WRITE_FAULT_ADDR >+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0 >+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL >+//DMCUB_SEC_CNTL >+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT 0x0 >+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8 >+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10 >+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11 >+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14 >+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15 >+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18 >+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19 >+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK 0x00000007L >+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L >+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L >+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L >+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L >+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L >+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L >+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L >+//DMCUB_MEM_CNTL >+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0 >+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4 >+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT 0x8 >+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT 0xc >+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL >+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L >+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK 0x00000700L >+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK 0x00007000L >+//DMCUB_INBOX0_BASE_ADDRESS >+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL >+//DMCUB_INBOX0_SIZE >+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0 >+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL >+//DMCUB_INBOX0_WPTR >+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0 >+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL >+//DMCUB_INBOX0_RPTR >+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0 >+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL >+//DMCUB_INBOX1_BASE_ADDRESS >+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL >+//DMCUB_INBOX1_SIZE >+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0 >+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL >+//DMCUB_INBOX1_WPTR >+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0 >+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL >+//DMCUB_INBOX1_RPTR >+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0 >+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL >+//DMCUB_OUTBOX0_BASE_ADDRESS >+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL >+//DMCUB_OUTBOX0_SIZE >+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0 >+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL >+//DMCUB_OUTBOX0_WPTR >+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0 >+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL >+//DMCUB_OUTBOX0_RPTR >+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0 >+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL >+//DMCUB_OUTBOX1_BASE_ADDRESS >+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0 >+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL >+//DMCUB_OUTBOX1_SIZE >+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0 >+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL >+//DMCUB_OUTBOX1_WPTR >+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0 >+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL >+//DMCUB_OUTBOX1_RPTR >+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0 >+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL >+//DMCUB_TIMER_TRIGGER0 >+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0 >+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL >+//DMCUB_TIMER_TRIGGER1 >+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0 >+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL >+//DMCUB_TIMER_WINDOW >+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0 >+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L >+//DMCUB_SCRATCH0 >+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0 >+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH1 >+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0 >+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH2 >+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0 >+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH3 >+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0 >+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH4 >+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0 >+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH5 >+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0 >+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH6 >+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0 >+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH7 >+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0 >+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH8 >+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0 >+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH9 >+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0 >+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH10 >+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0 >+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH11 >+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0 >+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH12 >+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0 >+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH13 >+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0 >+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH14 >+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0 >+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL >+//DMCUB_SCRATCH15 >+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0 >+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL >+//DMCUB_CNTL >+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0 >+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8 >+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10 >+#define DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT 0x11 >+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12 >+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13 >+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14 >+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL >+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L >+#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L >+#define DMCUB_CNTL__DMCUB_SOFT_RESET_MASK 0x00020000L >+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L >+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L >+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L >+//DMCUB_GPINT_DATAIN0 >+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0 >+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL >+//DMCUB_GPINT_DATAIN1 >+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0 >+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL >+//DMCUB_GPINT_DATAOUT >+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0 >+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL >+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR >+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0 >+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL >+//DMCUB_LS_WAKE_INT_ENABLE >+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0 >+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL >+//DMCUB_MEM_PWR_CNTL >+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1 >+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3 >+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4 >+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L >+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L >+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L >+//DMCUB_TIMER_CURRENT >+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0 >+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL >+//DMCUB_PROC_ID >+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0 >+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL >+ >+ >+// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec >+//MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L >+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L >+//MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R >+#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL >+//MCIF_WB2_MCIF_WB_BUFMGR_STATUS >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L >+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L >+//MCIF_WB2_MCIF_WB_BUF_PITCH >+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 >+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L >+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L >+//MCIF_WB2_MCIF_WB_BUF_1_STATUS >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB2_MCIF_WB_BUF_1_STATUS2 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB2_MCIF_WB_BUF_2_STATUS >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB2_MCIF_WB_BUF_2_STATUS2 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB2_MCIF_WB_BUF_3_STATUS >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB2_MCIF_WB_BUF_3_STATUS2 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB2_MCIF_WB_BUF_4_STATUS >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L >+//MCIF_WB2_MCIF_WB_BUF_4_STATUS2 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L >+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L >+//MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL >+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 >+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L >+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L >+//MCIF_WB2_MCIF_WB_SCLK_CHANGE >+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL >+//MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX >+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL >+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L >+//MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA >+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL >+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL >+//MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L >+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L >+//MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL >+//MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L >+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L >+//MCIF_WB2_MCIF_WB_WATERMARK >+#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL >+//MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL >+#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L >+//MCIF_WB2_MCIF_WB_WARM_UP_CNTL >+#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 >+#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L >+//MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL >+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 >+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L >+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L >+//MCIF_WB2_MULTI_LEVEL_QOS_CTRL >+#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 >+#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL >+//MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE >+#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL >+//MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE >+#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL >+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL >+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL >+//MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION >+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION >+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION >+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+//MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION >+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 >+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 >+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL >+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L >+ >+ >+// addressBlock: dce_dc_dchvm_hvm_dispdec >+//DCHVM_CTRL0 >+#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT 0x0 >+#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK 0x00000001L >+//DCHVM_CTRL1 >+#define DCHVM_CTRL1__DUMMY1__SHIFT 0x0 >+#define DCHVM_CTRL1__DUMMY1_MASK 0xFFFFFFFFL >+//DCHVM_CLK_CTRL >+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT 0x0 >+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT 0x1 >+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT 0x4 >+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT 0x5 >+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT 0x8 >+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT 0xa >+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK 0x00000001L >+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK 0x00000002L >+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK 0x00000010L >+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK 0x00000020L >+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK 0x00000300L >+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK 0x00000C00L >+//DCHVM_MEM_CTRL >+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT 0x0 >+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT 0x2 >+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT 0x4 >+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK 0x00000001L >+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK 0x0000000CL >+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK 0x00000030L >+//DCHVM_RIOMMU_CTRL0 >+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT 0x0 >+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT 0x1 >+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK 0x00000001L >+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK 0x00000002L >+//DCHVM_RIOMMU_STAT0 >+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT 0x0 >+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT 0x1 >+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK 0x00000001L >+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK 0x00000002L >+ >+ >+// addressBlock: vga_vgaseqind >+//SEQ00 >+#define SEQ00__SEQ_RST0B__SHIFT 0x0 >+#define SEQ00__SEQ_RST1B__SHIFT 0x1 >+#define SEQ00__SEQ_RST0B_MASK 0x01L >+#define SEQ00__SEQ_RST1B_MASK 0x02L >+//SEQ01 >+#define SEQ01__SEQ_DOT8__SHIFT 0x0 >+#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 >+#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 >+#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 >+#define SEQ01__SEQ_MAXBW__SHIFT 0x5 >+#define SEQ01__SEQ_DOT8_MASK 0x01L >+#define SEQ01__SEQ_SHIFT2_MASK 0x04L >+#define SEQ01__SEQ_PCLKBY2_MASK 0x08L >+#define SEQ01__SEQ_SHIFT4_MASK 0x10L >+#define SEQ01__SEQ_MAXBW_MASK 0x20L >+//SEQ02 >+#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 >+#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 >+#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 >+#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 >+#define SEQ02__SEQ_MAP0_EN_MASK 0x01L >+#define SEQ02__SEQ_MAP1_EN_MASK 0x02L >+#define SEQ02__SEQ_MAP2_EN_MASK 0x04L >+#define SEQ02__SEQ_MAP3_EN_MASK 0x08L >+//SEQ03 >+#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 >+#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 >+#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 >+#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 >+#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 >+#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 >+#define SEQ03__SEQ_FONT_B1_MASK 0x01L >+#define SEQ03__SEQ_FONT_B2_MASK 0x02L >+#define SEQ03__SEQ_FONT_A1_MASK 0x04L >+#define SEQ03__SEQ_FONT_A2_MASK 0x08L >+#define SEQ03__SEQ_FONT_B0_MASK 0x10L >+#define SEQ03__SEQ_FONT_A0_MASK 0x20L >+//SEQ04 >+#define SEQ04__SEQ_256K__SHIFT 0x1 >+#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 >+#define SEQ04__SEQ_CHAIN__SHIFT 0x3 >+#define SEQ04__SEQ_256K_MASK 0x02L >+#define SEQ04__SEQ_ODDEVEN_MASK 0x04L >+#define SEQ04__SEQ_CHAIN_MASK 0x08L >+ >+ >+// addressBlock: vga_vgacrtind >+//CRT00 >+#define CRT00__H_TOTAL__SHIFT 0x0 >+#define CRT00__H_TOTAL_MASK 0xFFL >+//CRT01 >+#define CRT01__H_DISP_END__SHIFT 0x0 >+#define CRT01__H_DISP_END_MASK 0xFFL >+//CRT02 >+#define CRT02__H_BLANK_START__SHIFT 0x0 >+#define CRT02__H_BLANK_START_MASK 0xFFL >+//CRT03 >+#define CRT03__H_BLANK_END__SHIFT 0x0 >+#define CRT03__H_DE_SKEW__SHIFT 0x5 >+#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 >+#define CRT03__H_BLANK_END_MASK 0x1FL >+#define CRT03__H_DE_SKEW_MASK 0x60L >+#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L >+//CRT04 >+#define CRT04__H_SYNC_START__SHIFT 0x0 >+#define CRT04__H_SYNC_START_MASK 0xFFL >+//CRT05 >+#define CRT05__H_SYNC_END__SHIFT 0x0 >+#define CRT05__H_SYNC_SKEW__SHIFT 0x5 >+#define CRT05__H_BLANK_END_B5__SHIFT 0x7 >+#define CRT05__H_SYNC_END_MASK 0x1FL >+#define CRT05__H_SYNC_SKEW_MASK 0x60L >+#define CRT05__H_BLANK_END_B5_MASK 0x80L >+//CRT06 >+#define CRT06__V_TOTAL__SHIFT 0x0 >+#define CRT06__V_TOTAL_MASK 0xFFL >+//CRT07 >+#define CRT07__V_TOTAL_B8__SHIFT 0x0 >+#define CRT07__V_DISP_END_B8__SHIFT 0x1 >+#define CRT07__V_SYNC_START_B8__SHIFT 0x2 >+#define CRT07__V_BLANK_START_B8__SHIFT 0x3 >+#define CRT07__LINE_CMP_B8__SHIFT 0x4 >+#define CRT07__V_TOTAL_B9__SHIFT 0x5 >+#define CRT07__V_DISP_END_B9__SHIFT 0x6 >+#define CRT07__V_SYNC_START_B9__SHIFT 0x7 >+#define CRT07__V_TOTAL_B8_MASK 0x01L >+#define CRT07__V_DISP_END_B8_MASK 0x02L >+#define CRT07__V_SYNC_START_B8_MASK 0x04L >+#define CRT07__V_BLANK_START_B8_MASK 0x08L >+#define CRT07__LINE_CMP_B8_MASK 0x10L >+#define CRT07__V_TOTAL_B9_MASK 0x20L >+#define CRT07__V_DISP_END_B9_MASK 0x40L >+#define CRT07__V_SYNC_START_B9_MASK 0x80L >+//CRT08 >+#define CRT08__ROW_SCAN_START__SHIFT 0x0 >+#define CRT08__BYTE_PAN__SHIFT 0x5 >+#define CRT08__ROW_SCAN_START_MASK 0x1FL >+#define CRT08__BYTE_PAN_MASK 0x60L >+//CRT09 >+#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 >+#define CRT09__V_BLANK_START_B9__SHIFT 0x5 >+#define CRT09__LINE_CMP_B9__SHIFT 0x6 >+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 >+#define CRT09__MAX_ROW_SCAN_MASK 0x1FL >+#define CRT09__V_BLANK_START_B9_MASK 0x20L >+#define CRT09__LINE_CMP_B9_MASK 0x40L >+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L >+//CRT0A >+#define CRT0A__CURSOR_START__SHIFT 0x0 >+#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 >+#define CRT0A__CURSOR_START_MASK 0x1FL >+#define CRT0A__CURSOR_DISABLE_MASK 0x20L >+//CRT0B >+#define CRT0B__CURSOR_END__SHIFT 0x0 >+#define CRT0B__CURSOR_SKEW__SHIFT 0x5 >+#define CRT0B__CURSOR_END_MASK 0x1FL >+#define CRT0B__CURSOR_SKEW_MASK 0x60L >+//CRT0C >+#define CRT0C__DISP_START__SHIFT 0x0 >+#define CRT0C__DISP_START_MASK 0xFFL >+//CRT0D >+#define CRT0D__DISP_START__SHIFT 0x0 >+#define CRT0D__DISP_START_MASK 0xFFL >+//CRT0E >+#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 >+#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL >+//CRT0F >+#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 >+#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL >+//CRT10 >+#define CRT10__V_SYNC_START__SHIFT 0x0 >+#define CRT10__V_SYNC_START_MASK 0xFFL >+//CRT11 >+#define CRT11__V_SYNC_END__SHIFT 0x0 >+#define CRT11__V_INTR_CLR__SHIFT 0x4 >+#define CRT11__V_INTR_EN__SHIFT 0x5 >+#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 >+#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 >+#define CRT11__V_SYNC_END_MASK 0x0FL >+#define CRT11__V_INTR_CLR_MASK 0x10L >+#define CRT11__V_INTR_EN_MASK 0x20L >+#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L >+#define CRT11__C0T7_WR_ONLY_MASK 0x80L >+//CRT12 >+#define CRT12__V_DISP_END__SHIFT 0x0 >+#define CRT12__V_DISP_END_MASK 0xFFL >+//CRT13 >+#define CRT13__DISP_PITCH__SHIFT 0x0 >+#define CRT13__DISP_PITCH_MASK 0xFFL >+//CRT14 >+#define CRT14__UNDRLN_LOC__SHIFT 0x0 >+#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 >+#define CRT14__DOUBLE_WORD__SHIFT 0x6 >+#define CRT14__UNDRLN_LOC_MASK 0x1FL >+#define CRT14__ADDR_CNT_BY4_MASK 0x20L >+#define CRT14__DOUBLE_WORD_MASK 0x40L >+//CRT15 >+#define CRT15__V_BLANK_START__SHIFT 0x0 >+#define CRT15__V_BLANK_START_MASK 0xFFL >+//CRT16 >+#define CRT16__V_BLANK_END__SHIFT 0x0 >+#define CRT16__V_BLANK_END_MASK 0xFFL >+//CRT17 >+#define CRT17__RA0_AS_A13B__SHIFT 0x0 >+#define CRT17__RA1_AS_A14B__SHIFT 0x1 >+#define CRT17__VCOUNT_BY2__SHIFT 0x2 >+#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 >+#define CRT17__WRAP_A15TOA0__SHIFT 0x5 >+#define CRT17__BYTE_MODE__SHIFT 0x6 >+#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 >+#define CRT17__RA0_AS_A13B_MASK 0x01L >+#define CRT17__RA1_AS_A14B_MASK 0x02L >+#define CRT17__VCOUNT_BY2_MASK 0x04L >+#define CRT17__ADDR_CNT_BY2_MASK 0x08L >+#define CRT17__WRAP_A15TOA0_MASK 0x20L >+#define CRT17__BYTE_MODE_MASK 0x40L >+#define CRT17__CRTC_SYNC_EN_MASK 0x80L >+//CRT18 >+#define CRT18__LINE_CMP__SHIFT 0x0 >+#define CRT18__LINE_CMP_MASK 0xFFL >+//CRT1E >+#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 >+#define CRT1E__GRPH_DEC_RD1_MASK 0x02L >+//CRT1F >+#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 >+#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL >+//CRT22 >+#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 >+#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL >+ >+ >+// addressBlock: vga_vgagrphind >+//GRA00 >+#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 >+#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 >+#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 >+#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 >+#define GRA00__GRPH_SET_RESET0_MASK 0x01L >+#define GRA00__GRPH_SET_RESET1_MASK 0x02L >+#define GRA00__GRPH_SET_RESET2_MASK 0x04L >+#define GRA00__GRPH_SET_RESET3_MASK 0x08L >+//GRA01 >+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 >+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 >+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 >+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 >+#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L >+#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L >+#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L >+#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L >+//GRA02 >+#define GRA02__GRPH_CCOMP__SHIFT 0x0 >+#define GRA02__GRPH_CCOMP_MASK 0x0FL >+//GRA03 >+#define GRA03__GRPH_ROTATE__SHIFT 0x0 >+#define GRA03__GRPH_FN_SEL__SHIFT 0x3 >+#define GRA03__GRPH_ROTATE_MASK 0x07L >+#define GRA03__GRPH_FN_SEL_MASK 0x18L >+//GRA04 >+#define GRA04__GRPH_RMAP__SHIFT 0x0 >+#define GRA04__GRPH_RMAP_MASK 0x03L >+//GRA05 >+#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 >+#define GRA05__GRPH_READ1__SHIFT 0x3 >+#define GRA05__CGA_ODDEVEN__SHIFT 0x4 >+#define GRA05__GRPH_OES__SHIFT 0x5 >+#define GRA05__GRPH_PACK__SHIFT 0x6 >+#define GRA05__GRPH_WRITE_MODE_MASK 0x03L >+#define GRA05__GRPH_READ1_MASK 0x08L >+#define GRA05__CGA_ODDEVEN_MASK 0x10L >+#define GRA05__GRPH_OES_MASK 0x20L >+#define GRA05__GRPH_PACK_MASK 0x40L >+//GRA06 >+#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 >+#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 >+#define GRA06__GRPH_ADRSEL__SHIFT 0x2 >+#define GRA06__GRPH_GRAPHICS_MASK 0x01L >+#define GRA06__GRPH_ODDEVEN_MASK 0x02L >+#define GRA06__GRPH_ADRSEL_MASK 0x0CL >+//GRA07 >+#define GRA07__GRPH_XCARE0__SHIFT 0x0 >+#define GRA07__GRPH_XCARE1__SHIFT 0x1 >+#define GRA07__GRPH_XCARE2__SHIFT 0x2 >+#define GRA07__GRPH_XCARE3__SHIFT 0x3 >+#define GRA07__GRPH_XCARE0_MASK 0x01L >+#define GRA07__GRPH_XCARE1_MASK 0x02L >+#define GRA07__GRPH_XCARE2_MASK 0x04L >+#define GRA07__GRPH_XCARE3_MASK 0x08L >+//GRA08 >+#define GRA08__GRPH_BMSK__SHIFT 0x0 >+#define GRA08__GRPH_BMSK_MASK 0xFFL >+ >+ >+// addressBlock: vga_vgaattrind >+//ATTR00 >+#define ATTR00__ATTR_PAL__SHIFT 0x0 >+#define ATTR00__ATTR_PAL_MASK 0x3FL >+//ATTR01 >+#define ATTR01__ATTR_PAL__SHIFT 0x0 >+#define ATTR01__ATTR_PAL_MASK 0x3FL >+//ATTR02 >+#define ATTR02__ATTR_PAL__SHIFT 0x0 >+#define ATTR02__ATTR_PAL_MASK 0x3FL >+//ATTR03 >+#define ATTR03__ATTR_PAL__SHIFT 0x0 >+#define ATTR03__ATTR_PAL_MASK 0x3FL >+//ATTR04 >+#define ATTR04__ATTR_PAL__SHIFT 0x0 >+#define ATTR04__ATTR_PAL_MASK 0x3FL >+//ATTR05 >+#define ATTR05__ATTR_PAL__SHIFT 0x0 >+#define ATTR05__ATTR_PAL_MASK 0x3FL >+//ATTR06 >+#define ATTR06__ATTR_PAL__SHIFT 0x0 >+#define ATTR06__ATTR_PAL_MASK 0x3FL >+//ATTR07 >+#define ATTR07__ATTR_PAL__SHIFT 0x0 >+#define ATTR07__ATTR_PAL_MASK 0x3FL >+//ATTR08 >+#define ATTR08__ATTR_PAL__SHIFT 0x0 >+#define ATTR08__ATTR_PAL_MASK 0x3FL >+//ATTR09 >+#define ATTR09__ATTR_PAL__SHIFT 0x0 >+#define ATTR09__ATTR_PAL_MASK 0x3FL >+//ATTR0A >+#define ATTR0A__ATTR_PAL__SHIFT 0x0 >+#define ATTR0A__ATTR_PAL_MASK 0x3FL >+//ATTR0B >+#define ATTR0B__ATTR_PAL__SHIFT 0x0 >+#define ATTR0B__ATTR_PAL_MASK 0x3FL >+//ATTR0C >+#define ATTR0C__ATTR_PAL__SHIFT 0x0 >+#define ATTR0C__ATTR_PAL_MASK 0x3FL >+//ATTR0D >+#define ATTR0D__ATTR_PAL__SHIFT 0x0 >+#define ATTR0D__ATTR_PAL_MASK 0x3FL >+//ATTR0E >+#define ATTR0E__ATTR_PAL__SHIFT 0x0 >+#define ATTR0E__ATTR_PAL_MASK 0x3FL >+//ATTR0F >+#define ATTR0F__ATTR_PAL__SHIFT 0x0 >+#define ATTR0F__ATTR_PAL_MASK 0x3FL >+//ATTR10 >+#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 >+#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 >+#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 >+#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 >+#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 >+#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 >+#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 >+#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L >+#define ATTR10__ATTR_MONO_EN_MASK 0x02L >+#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L >+#define ATTR10__ATTR_BLINK_EN_MASK 0x08L >+#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L >+#define ATTR10__ATTR_PCLKBY2_MASK 0x40L >+#define ATTR10__ATTR_CSEL_EN_MASK 0x80L >+//ATTR11 >+#define ATTR11__ATTR_OVSC__SHIFT 0x0 >+#define ATTR11__ATTR_OVSC_MASK 0xFFL >+//ATTR12 >+#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 >+#define ATTR12__ATTR_VSMUX__SHIFT 0x4 >+#define ATTR12__ATTR_MAP_EN_MASK 0x0FL >+#define ATTR12__ATTR_VSMUX_MASK 0x30L >+//ATTR13 >+#define ATTR13__ATTR_PPAN__SHIFT 0x0 >+#define ATTR13__ATTR_PPAN_MASK 0x0FL >+//ATTR14 >+#define ATTR14__ATTR_CSEL1__SHIFT 0x0 >+#define ATTR14__ATTR_CSEL2__SHIFT 0x2 >+#define ATTR14__ATTR_CSEL1_MASK 0x03L >+#define ATTR14__ATTR_CSEL2_MASK 0x0CL >+ >+ >+// addressBlock: azendpoint_f2codecind >+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L >+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL >+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L >+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L >+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L >+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L >+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L >+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION >+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL >+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO >+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 >+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 >+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L >+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L >+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L >+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC >+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZALIA_F2_CODEC_PIN_CONTROL_HBR >+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL >+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO >+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB >+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azendpoint_descriptorind >+//AUDIO_DESCRIPTOR0 >+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR1 >+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR2 >+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR3 >+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR4 >+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR5 >+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR6 >+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR7 >+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR8 >+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR9 >+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR10 >+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR11 >+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR12 >+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AUDIO_DESCRIPTOR13 >+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+ >+ >+// addressBlock: azendpoint_sinkinfoind >+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID >+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID >+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN >+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 >+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 >+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL >+//SINK_DESCRIPTION0 >+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION1 >+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION2 >+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION3 >+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION4 >+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION5 >+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION6 >+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION7 >+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION8 >+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION9 >+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION10 >+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION11 >+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION12 >+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION13 >+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION14 >+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION15 >+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION16 >+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL >+//SINK_DESCRIPTION17 >+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 >+#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL >+ >+ >+// addressBlock: azf0controller_azinputcrc0resultind >+//AZALIA_INPUT_CRC0_CHANNEL0 >+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC0_CHANNEL1 >+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC0_CHANNEL2 >+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC0_CHANNEL3 >+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC0_CHANNEL4 >+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC0_CHANNEL5 >+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC0_CHANNEL6 >+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC0_CHANNEL7 >+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 >+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0controller_azinputcrc1resultind >+//AZALIA_INPUT_CRC1_CHANNEL0 >+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CHANNEL1 >+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CHANNEL2 >+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CHANNEL3 >+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CHANNEL4 >+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CHANNEL5 >+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CHANNEL6 >+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL >+//AZALIA_INPUT_CRC1_CHANNEL7 >+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 >+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0controller_azcrc0resultind >+//AZALIA_CRC0_CHANNEL0 >+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 >+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CHANNEL1 >+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 >+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CHANNEL2 >+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 >+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CHANNEL3 >+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 >+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CHANNEL4 >+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 >+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CHANNEL5 >+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 >+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CHANNEL6 >+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 >+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL >+//AZALIA_CRC0_CHANNEL7 >+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 >+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0controller_azcrc1resultind >+//AZALIA_CRC1_CHANNEL0 >+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 >+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CHANNEL1 >+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 >+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CHANNEL2 >+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 >+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CHANNEL3 >+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 >+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CHANNEL4 >+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 >+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CHANNEL5 >+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 >+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CHANNEL6 >+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 >+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL >+//AZALIA_CRC1_CHANNEL7 >+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 >+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azinputendpoint_f2codecind >+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+ >+ >+// addressBlock: azroot_f2codecind >+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID >+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 >+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID >+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 >+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT >+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 >+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L >+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L >+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL >+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL >+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL >+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL >+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L >+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L >+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L >+ >+ >+// addressBlock: azf0stream0_streamind >+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream1_streamind >+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream2_streamind >+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream3_streamind >+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream4_streamind >+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream5_streamind >+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream6_streamind >+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream7_streamind >+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream8_streamind >+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream9_streamind >+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream10_streamind >+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream11_streamind >+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream12_streamind >+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream13_streamind >+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream14_streamind >+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0stream15_streamind >+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL >+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 >+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 >+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 >+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL >+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L >+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L >+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL >+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 >+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L >+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT >+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT >+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 >+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL >+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT >+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 >+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL >+ >+ >+// addressBlock: azf0endpoint0_endpointind >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L >+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L >+ >+ >+// addressBlock: azf0endpoint1_endpointind >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L >+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L >+ >+ >+// addressBlock: azf0endpoint2_endpointind >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L >+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L >+ >+ >+// addressBlock: azf0endpoint3_endpointind >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L >+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L >+ >+ >+// addressBlock: azf0endpoint4_endpointind >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L >+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L >+ >+ >+// addressBlock: azf0endpoint5_endpointind >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L >+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L >+ >+ >+// addressBlock: azf0endpoint6_endpointind >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L >+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L >+ >+ >+// addressBlock: azf0endpoint7_endpointind >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L >+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL >+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L >+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L >+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L >+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L >+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L >+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L >+ >+ >+// addressBlock: azf0inputendpoint0_inputendpointind >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L >+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L >+ >+ >+// addressBlock: azf0inputendpoint1_inputendpointind >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L >+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L >+ >+ >+// addressBlock: azf0inputendpoint2_inputendpointind >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L >+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L >+ >+ >+// addressBlock: azf0inputendpoint3_inputendpointind >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L >+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L >+ >+ >+// addressBlock: azf0inputendpoint4_inputendpointind >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L >+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L >+ >+ >+// addressBlock: azf0inputendpoint5_inputendpointind >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L >+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L >+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME >