Attachment 145460 Details for Bug 111749 – Patch fixing all the issues on AUO PSR2 panel by forcibly enabling PSR1 on it

[patch] Patch fixing all the issues on AUO PSR2 panel by forcibly enabling PSR1 on it

0001-drm-i915-forcibly-enabling-only-PSR1-on-Hel.patch (text/plain), 2.60 KB, created by gaurav.k.singh on 2019-09-22 13:13:49 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: gaurav.k.singh

Created: 2019-09-22 13:13:49 UTC

Size: 2.60 KB

patch

obsolete

>From 778410d806ba3e7f4894c0c34b9e47b89b6e03e3 Mon Sep 17 00:00:00 2001
>From: Gaurav K Singh <gaurav.k.singh@intel.com>
>Date: Sun, 22 Sep 2019 18:32:25 +0530
>Subject: [PATCH] drm/i915: forcibly enabling only PSR1 on AUO PSR2 panel
>
>Results with the patch:
>
>All issues resolved:
>1. No display corruption
>2. No corruption from tab to VT mode
>3. No mouse trace issue
>4. No characters lag in VT2 mode
>5. No corruption on login screen
>6. No slowless of system
>
>Change-Id: Id72e5000be3499d9c1302d4aacf9499e024c51a7
>Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index c1278b2ede09..cab2e83970d3 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -72,6 +72,7 @@ static bool psr_global_enabled(u32 debug)
> static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> 			       const struct intel_crtc_state *crtc_state)
> {
>+	return false;
> 	switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> 	case I915_PSR_DEBUG_DISABLE:
> 	case I915_PSR_DEBUG_FORCE_PSR1:
>@@ -222,7 +223,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> 		schedule_work(&dev_priv->psr.work);
> 	}
> }
>-
>+/*
> static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> {
> 	uint8_t dprx = 0;
>@@ -242,7 +243,7 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
> 		return false;
> 	return alpm_caps & DP_ALPM_CAP;
> }
>-
>+*/
> static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> {
> 	u8 val = 8; /* assume the worst if we can't read the value */
>@@ -254,7 +255,7 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> 		DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");
> 	return val;
> }
>-
>+#if 0
> static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
> {
> 	u16 val;
>@@ -280,7 +281,7 @@ static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
> 
> 	return val;
> }
>-
>+#endif
> void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> {
> 	struct drm_i915_private *dev_priv =
>@@ -310,6 +311,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> 
> 	WARN_ON(dev_priv->psr.dp);
> 	dev_priv->psr.dp = intel_dp;
>+#if 0
> 
> 	if (INTEL_GEN(dev_priv) >= 9 &&
> 	    (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
>@@ -339,6 +341,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> 				intel_dp_get_su_x_granulartiy(intel_dp);
> 		}
> 	}
>+#endif
> }
> 
> static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
>-- 
>1.9.1
>

Actions: View | Splinter Review

Attachments on bug 111749: 145431 | 145432 | 145460 | 145489 | 145509 | 145547 | 145548 | 145549

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.