Attachment 16667 Details for Bug 13326 – Fixup FIFO underrun on modeset

[patch] Fixup FIFO underrun on modeset

i830-default-dsparb-value-2.patch (text/plain), 3.38 KB, created by Jesse Barnes on 2008-05-21 12:19:06 UTC

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Creator: Jesse Barnes

Created: 2008-05-21 12:19:06 UTC

Size: 3.38 KB

patch

obsolete

>diff --git a/src/i810_reg.h b/src/i810_reg.h
>index 860d1db..aabf5b6 100644
>--- a/src/i810_reg.h
>+++ b/src/i810_reg.h
>@@ -2100,6 +2100,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> 				 
> 
> #define DSPARB			0x70030
>+#define   DSPARB_CSTART_SHIFT	7
>+#define   DSPARB_BSTART_SHIFT	0
> #define DSPFW1			0x70034
> #define DSPFW2			0x70038
> #define DSPFW3			0x7003c
>diff --git a/src/i830_display.c b/src/i830_display.c
>index 1122721..2d2d072 100644
>--- a/src/i830_display.c
>+++ b/src/i830_display.c
>@@ -1077,6 +1077,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
>     int dspstride_reg = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
>     int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
>     int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
>+    int pipestat_reg = (pipe == 0) ? PIPEASTAT : PIPEBSTAT;
>     int i;
>     int refclk;
>     intel_clock_t clock;
>@@ -1376,6 +1377,9 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
> #endif
>     
>     i830WaitForVblank(pScrn);
>+
>+    /* Clear any FIFO underrun status that may have occurred normally */
>+    OUTREG(pipestat_reg, INREG(pipestat_reg) | FIFO_UNDERRUN);
> }
> 
> 
>diff --git a/src/i830_driver.c b/src/i830_driver.c
>index 8d993ba..2a8bd55 100644
>--- a/src/i830_driver.c
>+++ b/src/i830_driver.c
>@@ -1898,9 +1898,26 @@ static void
> SetHWOperatingState(ScrnInfoPtr pScrn)
> {
>    I830Ptr pI830 = I830PTR(pScrn);
>-
>+   xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
>+   int i;
>+   
>    DPRINTF(PFX, "SetHWOperatingState\n");
> 
>+   /*
>+    * Disable outputs & pipes since some of these regs can only be updated
>+    * when they're off.
>+    */
>+   for (i = 0; i < xf86_config->num_output; i++) {
>+      xf86OutputPtr   output = xf86_config->output[i];
>+      output->funcs->dpms(output, DPMSModeOff);
>+   }
>+   i830WaitForVblank(pScrn);
>+   for (i = 0; i < xf86_config->num_crtc; i++) {
>+      xf86CrtcPtr crtc = xf86_config->crtc[i];
>+      crtc->funcs->dpms(crtc, DPMSModeOff);
>+   }
>+   i830WaitForVblank(pScrn);
>+
>    /* Disable clock gating reported to work incorrectly according to the specs.
>     */
>    if (IS_IGD_GM(pI830)) {
>@@ -1921,6 +1938,13 @@ SetHWOperatingState(ScrnInfoPtr pScrn)
>    i830_start_ring(pScrn);
>    if (!pI830->SWCursor)
>       I830InitHWCursor(pScrn);
>+
>+   /*
>+    * Fixup FIFO defaults:
>+    * we don't use plane C at all so we can allocate the 96 FIFO RAM
>+    * entries equally between planes A and B.
>+    */
>+   OUTREG(DSPARB, (95 << DSPARB_CSTART_SHIFT) | (48 << DSPARB_BSTART_SHIFT));
> }
> 
> enum pipe {
>@@ -2443,6 +2467,22 @@ I830BlockHandler(int i,
>     if (pScrn->vtSema && !pI830->noAccel && !pI830->directRenderingEnabled)
> 	I830EmitFlush(pScrn);
> 
>+    /*
>+     * Check for FIFO underruns at block time (which amounts to just
>+     * periodically).  If this happens, it means our DSPARB or some other
>+     * memory arbitration setting is wrong for the current configuration
>+     * (except for mode setting, where it may occur naturally).
>+     * Check & ack the condition.
>+     */
>+    if (INREG(PIPEASTAT) & FIFO_UNDERRUN) {
>+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "underrun on pipe A!\n");
>+	    OUTREG(PIPEASTAT, INREG(PIPEASTAT) | FIFO_UNDERRUN);
>+    }
>+    if (INREG(PIPEBSTAT) & FIFO_UNDERRUN) {
>+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "underrun on pipe B!\n");
>+	    OUTREG(PIPEBSTAT, INREG(PIPEBSTAT) | FIFO_UNDERRUN);
>+    }
>+
>     I830VideoBlockHandler(i, blockData, pTimeout, pReadmask);
> }
>

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Attachments on bug 13326: 12690 | 12691 | 12704 | 12833 | 12921 | 12933 | 12983 | 13717 | 14432 | 15590 | 16394 | 16666 | 16667

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