Attachment 20590 Details for Bug 17823 – 2.5.1 Debug logs

2.5.1 Debug logs

2.5.1-Xorg.0.log (text/plain), 69.46 KB, created by Ulhume on 2008-11-25 18:40:49 UTC

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Creator: Ulhume

Created: 2008-11-25 18:40:49 UTC

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>
>X.Org X Server 1.4.2
>Release Date: 11 June 2008
>X Protocol Version 11, Revision 0
>Build Operating System: Linux_2.6.22.12-server-1mdv Mandriva
>Current Operating System: Linux horus.karma-lab.net 2.6.27.4-desktop-2mnb #1 SMP Thu Nov 6 13:00:14 EST 2008 i686
>Build Date: 31 October 2008  11:34:23AM
> 
>	Before reporting problems, check http://qa.mandriva.com
>	to make sure that you have the latest version.
>Module Loader present
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Wed Nov 26 03:37:13 2008
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) ServerLayout "Horizontal Layout"
>(**) |-->Screen "Screen" (0)
>(**) |   |-->Monitor "External VGA"
>(**) |   |-->Device "Intel 945GU"
>(**) |-->Input Device "Keyboard"
>(**) |-->Input Device "Tablet"
>(**) |-->Input Device "Mouse1"
>(**) Option "AllowMouseOpenFail"
>(==) Automatically adding devices
>(==) Automatically enabling devices
>(==) No FontPath specified.  Using compiled-in default.
>(==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d
>(==) RgbPath set to "/usr/share/X11/rgb"
>(==) ModulePath set to "/usr/lib/xorg/modules"
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) Loader magic: 0x820d5c0
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.3
>	X.Org Video Driver: 2.0
>	X.Org XInput driver : 2.0
>	X.Org Server Extension : 0.3
>	X.Org Font Renderer : 0.5
>(II) Loader running on linux
>(II) LoadModule: "pcidata"
>(II) Loading /usr/lib/xorg/modules//libpcidata.so
>(II) Module pcidata: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 2.0
>(++) using VT number 7
>
>(II) PCI: PCI scan (all values are in hex)
>(II) PCI: 00:00:0: chip 8086,27a0 card 10cf,1378 rev 03 class 06,00,00 hdr 00
>(II) PCI: 00:01:0: chip 8086,27a1 card 0000,0000 rev 03 class 06,04,00 hdr 01
>(II) PCI: 00:02:0: chip 8086,27a2 card 10cf,13da rev 03 class 03,00,00 hdr 80
>(II) PCI: 00:02:1: chip 8086,27a6 card 10cf,13da rev 03 class 03,80,00 hdr 80
>(II) PCI: 00:1b:0: chip 8086,27d8 card 10cf,142d rev 02 class 04,03,00 hdr 00
>(II) PCI: 00:1d:0: chip 8086,27c8 card 10cf,1389 rev 02 class 0c,03,00 hdr 80
>(II) PCI: 00:1d:1: chip 8086,27c9 card 10cf,1389 rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:2: chip 8086,27ca card 10cf,1389 rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:3: chip 8086,27cb card 10cf,1389 rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:7: chip 8086,27cc card 10cf,138a rev 02 class 0c,03,20 hdr 00
>(II) PCI: 00:1e:0: chip 8086,2448 card 0000,0000 rev e2 class 06,04,01 hdr 01
>(II) PCI: 00:1f:0: chip 8086,27b9 card 10cf,1384 rev 02 class 06,01,00 hdr 80
>(II) PCI: 00:1f:1: chip 8086,27df card 10cf,1385 rev 02 class 01,01,8a hdr 00
>(II) PCI: 00:1f:3: chip 8086,27da card 10cf,1388 rev 02 class 0c,05,00 hdr 00
>(II) PCI: 01:00:0: chip 168c,001c card 10cf,139c rev 01 class 02,00,00 hdr 00
>(II) PCI: 08:03:0: chip 1217,7134 card 2001,0000 rev 20 class 06,07,00 hdr 82
>(II) PCI: 08:03:2: chip 1217,7120 card 10cf,131e rev 00 class 08,05,00 hdr 00
>(II) PCI: 08:04:0: chip 10ec,8139 card 10cf,1213 rev 10 class 02,00,00 hdr 00
>(II) PCI: End of PCI scan
>(II) Intel Bridge workaround enabled
>(II) Host-to-PCI bridge:
>(II) Bus 0: bridge is at (0:0:0), (0,0,9), BCTRL: 0x0008 (VGA_EN is set)
>(II) Bus 0 I/O range:
>	[0] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) Bus 0 non-prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>(II) Bus 0 prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 1: bridge is at (0:1:0), (0,1,1), BCTRL: 0x0000 (VGA_EN is cleared)
>(II) Bus 1 non-prefetchable memory range:
>	[0] -1	0	0xf0000000 - 0xf00fffff (0x100000) MX[B]
>(II) Subtractive PCI-to-PCI bridge:
>(II) Bus 8: bridge is at (0:30:0), (0,8,12), BCTRL: 0x0004 (VGA_EN is cleared)
>(II) Bus 8 I/O range:
>	[0] -1	0	0x00002000 - 0x000020ff (0x100) IX[B]
>	[1] -1	0	0x00002400 - 0x000024ff (0x100) IX[B]
>	[2] -1	0	0x00002800 - 0x000028ff (0x100) IX[B]
>	[3] -1	0	0x00002c00 - 0x00002cff (0x100) IX[B]
>(II) Bus 8 non-prefetchable memory range:
>	[0] -1	0	0xf0100000 - 0xf01fffff (0x100000) MX[B]
>(II) Bus 8 prefetchable memory range:
>	[0] -1	0	0x50000000 - 0x53ffffff (0x4000000) MX[B]
>(II) PCI-to-ISA bridge:
>(II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set)
>(II) PCI-to-CardBus bridge:
>(II) Bus 9: bridge is at (8:3:0), (8,9,12), BCTRL: 0x0580 (VGA_EN is cleared)
>(II) Bus 9 I/O range:
>	[0] -1	0	0x00002000 - 0x000020ff (0x100) IX[B]
>	[1] -1	0	0x00002400 - 0x000024ff (0x100) IX[B]
>(II) Bus 9 prefetchable memory range:
>	[0] -1	0	0x50000000 - 0x53ffffff (0x4000000) MX[B]
>(--) PCI:*(0:2:0) Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller rev 3, Mem @ 0xf0200000/19, 0xe0000000/28, 0xf0300000/18, I/O @ 0x1800/3
>(--) PCI: (0:2:1) Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller rev 3, Mem @ 0xf0280000/19
>(II) Addressable bus resource ranges are
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>	[1] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) OS-reported resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) Active PCI resource ranges:
>	[0] -1	0	0xf0100400 - 0xf01004ff (0x100) MX[B]
>	[1] -1	0	0xf0100000 - 0xf01000ff (0x100) MX[B]
>	[2] -1	0	0xf0000000 - 0xf000ffff (0x10000) MX[B]
>	[3] -1	0	0xf0544000 - 0xf05443ff (0x400) MX[B]
>	[4] -1	0	0xf0340000 - 0xf0343fff (0x4000) MX[B]
>	[5] -1	0	0xf0280000 - 0xf02fffff (0x80000) MX[B](B)
>	[6] -1	0	0xf0300000 - 0xf033ffff (0x40000) MX[B](B)
>	[7] -1	0	0xe0000000 - 0xefffffff (0x10000000) MX[B](B)
>	[8] -1	0	0xf0200000 - 0xf027ffff (0x80000) MX[B](B)
>	[9] -1	0	0x0000f800 - 0x0000f8ff (0x100) IX[B]
>	[10] -1	0	0x000018a0 - 0x000018bf (0x20) IX[B]
>	[11] -1	0	0x00001810 - 0x0000181f (0x10) IX[B]
>	[12] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[13] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[14] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[15] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[16] -1	0	0x00001880 - 0x0000189f (0x20) IX[B]
>	[17] -1	0	0x00001860 - 0x0000187f (0x20) IX[B]
>	[18] -1	0	0x00001840 - 0x0000185f (0x20) IX[B]
>	[19] -1	0	0x00001820 - 0x0000183f (0x20) IX[B]
>	[20] -1	0	0x00001800 - 0x00001807 (0x8) IX[B](B)
>(II) Active PCI resource ranges after removing overlaps:
>	[0] -1	0	0xf0100400 - 0xf01004ff (0x100) MX[B]
>	[1] -1	0	0xf0100000 - 0xf01000ff (0x100) MX[B]
>	[2] -1	0	0xf0000000 - 0xf000ffff (0x10000) MX[B]
>	[3] -1	0	0xf0544000 - 0xf05443ff (0x400) MX[B]
>	[4] -1	0	0xf0340000 - 0xf0343fff (0x4000) MX[B]
>	[5] -1	0	0xf0280000 - 0xf02fffff (0x80000) MX[B](B)
>	[6] -1	0	0xf0300000 - 0xf033ffff (0x40000) MX[B](B)
>	[7] -1	0	0xe0000000 - 0xefffffff (0x10000000) MX[B](B)
>	[8] -1	0	0xf0200000 - 0xf027ffff (0x80000) MX[B](B)
>	[9] -1	0	0x0000f800 - 0x0000f8ff (0x100) IX[B]
>	[10] -1	0	0x000018a0 - 0x000018bf (0x20) IX[B]
>	[11] -1	0	0x00001810 - 0x0000181f (0x10) IX[B]
>	[12] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[13] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[14] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[15] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[16] -1	0	0x00001880 - 0x0000189f (0x20) IX[B]
>	[17] -1	0	0x00001860 - 0x0000187f (0x20) IX[B]
>	[18] -1	0	0x00001840 - 0x0000185f (0x20) IX[B]
>	[19] -1	0	0x00001820 - 0x0000183f (0x20) IX[B]
>	[20] -1	0	0x00001800 - 0x00001807 (0x8) IX[B](B)
>(II) OS-reported resource ranges after removing overlaps with PCI:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) All system resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xf0100400 - 0xf01004ff (0x100) MX[B]
>	[5] -1	0	0xf0100000 - 0xf01000ff (0x100) MX[B]
>	[6] -1	0	0xf0000000 - 0xf000ffff (0x10000) MX[B]
>	[7] -1	0	0xf0544000 - 0xf05443ff (0x400) MX[B]
>	[8] -1	0	0xf0340000 - 0xf0343fff (0x4000) MX[B]
>	[9] -1	0	0xf0280000 - 0xf02fffff (0x80000) MX[B](B)
>	[10] -1	0	0xf0300000 - 0xf033ffff (0x40000) MX[B](B)
>	[11] -1	0	0xe0000000 - 0xefffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xf0200000 - 0xf027ffff (0x80000) MX[B](B)
>	[13] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[14] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[15] -1	0	0x0000f800 - 0x0000f8ff (0x100) IX[B]
>	[16] -1	0	0x000018a0 - 0x000018bf (0x20) IX[B]
>	[17] -1	0	0x00001810 - 0x0000181f (0x10) IX[B]
>	[18] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[19] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[20] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[21] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[22] -1	0	0x00001880 - 0x0000189f (0x20) IX[B]
>	[23] -1	0	0x00001860 - 0x0000187f (0x20) IX[B]
>	[24] -1	0	0x00001840 - 0x0000185f (0x20) IX[B]
>	[25] -1	0	0x00001820 - 0x0000183f (0x20) IX[B]
>	[26] -1	0	0x00001800 - 0x00001807 (0x8) IX[B](B)
>(II) "extmod" will be loaded. This was enabled by default and also specified in the config file.
>(II) "dbe" will be loaded. This was enabled by default and also specified in the config file.
>(II) "glx" will be loaded. This was enabled by default and also specified in the config file.
>(II) "freetype" will be loaded. This was enabled by default and also specified in the config file.
>(II) "type1" will be loaded. This was enabled by default and also specified in the config file.
>(II) "record" will be loaded by default.
>(II) "dri" will be loaded. This was enabled by default and also specified in the config file.
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "v4l"
>(II) Loading /usr/lib/xorg/modules/drivers//v4l_drv.so
>(II) Module v4l: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 0.1.1
>	ABI class: X.Org Video Driver, version 2.0
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension SHAPE
>(II) Loading extension Multi-Buffering
>(II) Loading extension MIT-SUNDRY-NONSTANDARD
>(II) Loading extension BIG-REQUESTS
>(II) Loading extension SYNC
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XC-MISC
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-Misc
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension TOG-CUP
>(II) Loading extension Extended-Visual-Information
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "type1"
>(II) Loading /usr/lib/xorg/modules/fonts//libtype1.so
>(II) Module type1: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.0.2
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font Type1
>(II) LoadModule: "freetype"
>(II) Loading /usr/lib/xorg/modules/fonts//libfreetype.so
>(II) Module freetype: vendor="X.Org Foundation & the After X-TT Project"
>	compiled for 1.4.2, module version = 2.1.0
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font FreeType
>(II) LoadModule: "glx"
>(II) Loading /usr/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "dri"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "record"
>(II) Loading /usr/lib/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension RECORD
>(II) LoadModule: "intel"
>(II) Loading /usr/lib/xorg/modules/drivers//intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 2.5.1
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 2.0
>(II) LoadModule: "kbd"
>(II) Loading /usr/lib/xorg/modules/input//kbd_drv.so
>(II) Module kbd: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.3.1
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 2.0
>(II) LoadModule: "evtouch"
>(II) Loading /usr/lib/xorg/modules/input//evtouch_drv.so
>(II) Module evtouch: vendor="Kenan Esau"
>	compiled for 4.3.99.902, module version = 0.8.7
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 2.0
>(II) LoadModule: "mouse"
>(II) Loading /usr/lib/xorg/modules/input//mouse_drv.so
>(II) Module mouse: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.3.0
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 2.0
>(II) v4l driver for Video4Linux
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, 965G, G35, 965Q, 946GZ,
>	965GM, 965GME/GLE, G33, Q35, Q33,
>	Mobile IntelÂ® GM45 Express Chipset,
>	Intel Integrated Graphics Device, G45/G43, Q45/Q43, G41
>(II) Primary Device is: PCI 00:02:0
>(--) Assigning device section with no busID to primary device
>(WW) intel: No matching Device section for instance (BusID PCI:0:2:1) found
>(--) Chipset 945GM found
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xf0100400 - 0xf01004ff (0x100) MX[B]
>	[5] -1	0	0xf0100000 - 0xf01000ff (0x100) MX[B]
>	[6] -1	0	0xf0000000 - 0xf000ffff (0x10000) MX[B]
>	[7] -1	0	0xf0544000 - 0xf05443ff (0x400) MX[B]
>	[8] -1	0	0xf0340000 - 0xf0343fff (0x4000) MX[B]
>	[9] -1	0	0xf0280000 - 0xf02fffff (0x80000) MX[B](B)
>	[10] -1	0	0xf0300000 - 0xf033ffff (0x40000) MX[B](B)
>	[11] -1	0	0xe0000000 - 0xefffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xf0200000 - 0xf027ffff (0x80000) MX[B](B)
>	[13] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[14] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[15] -1	0	0x0000f800 - 0x0000f8ff (0x100) IX[B]
>	[16] -1	0	0x000018a0 - 0x000018bf (0x20) IX[B]
>	[17] -1	0	0x00001810 - 0x0000181f (0x10) IX[B]
>	[18] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[19] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[20] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[21] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[22] -1	0	0x00001880 - 0x0000189f (0x20) IX[B]
>	[23] -1	0	0x00001860 - 0x0000187f (0x20) IX[B]
>	[24] -1	0	0x00001840 - 0x0000185f (0x20) IX[B]
>	[25] -1	0	0x00001820 - 0x0000183f (0x20) IX[B]
>	[26] -1	0	0x00001800 - 0x00001807 (0x8) IX[B](B)
>(II) resource ranges after probing:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xf0100400 - 0xf01004ff (0x100) MX[B]
>	[5] -1	0	0xf0100000 - 0xf01000ff (0x100) MX[B]
>	[6] -1	0	0xf0000000 - 0xf000ffff (0x10000) MX[B]
>	[7] -1	0	0xf0544000 - 0xf05443ff (0x400) MX[B]
>	[8] -1	0	0xf0340000 - 0xf0343fff (0x4000) MX[B]
>	[9] -1	0	0xf0280000 - 0xf02fffff (0x80000) MX[B](B)
>	[10] -1	0	0xf0300000 - 0xf033ffff (0x40000) MX[B](B)
>	[11] -1	0	0xe0000000 - 0xefffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xf0200000 - 0xf027ffff (0x80000) MX[B](B)
>	[13] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[14] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[15] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[16] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[17] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[18] -1	0	0x0000f800 - 0x0000f8ff (0x100) IX[B]
>	[19] -1	0	0x000018a0 - 0x000018bf (0x20) IX[B]
>	[20] -1	0	0x00001810 - 0x0000181f (0x10) IX[B]
>	[21] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[22] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[23] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[24] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[25] -1	0	0x00001880 - 0x0000189f (0x20) IX[B]
>	[26] -1	0	0x00001860 - 0x0000187f (0x20) IX[B]
>	[27] -1	0	0x00001840 - 0x0000185f (0x20) IX[B]
>	[28] -1	0	0x00001820 - 0x0000183f (0x20) IX[B]
>	[29] -1	0	0x00001800 - 0x00001807 (0x8) IX[B](B)
>	[30] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[31] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Setting vga for screen 0.
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 2.0
>(==) intel(0): Depth 24, (==) framebuffer bpp 32
>(==) intel(0): RGB weight 888
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "ModeDebug" "true"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) 945GM
>(--) intel(0): Chipset: "945GM"
>(--) intel(0): Linear framebuffer at 0xE0000000
>(--) intel(0): IO registers at addr 0xF0200000
>(==) intel(0): Using EXA for acceleration
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x11987418 (none, ch2 enh enabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0400 (0x0400)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x01080000 (0x0000)
>(II) intel(0):               C1DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB3: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA01: 0x04020108 (0x0108)
>(II) intel(0):              C0DRA23: 0x00000402 (0x0402)
>(II) intel(0):              C1DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x0048000c (disabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0xc0130300 (enabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x0048000c (disabled, pipe A, no stall, +hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) intel(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00640bb8
>(II) intel(0):        PP_OFF_DELAYS: 0x00641388
>(II) intel(0):           PP_DIVISOR: 0x00270f07
>(II) intel(0):         PFIT_CONTROL: 0x80002668
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000400
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x00000203 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x95000000 (enabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000640 (1600 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x0257031f (800, 600)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x031f0257 (800, 600)
>(II) intel(0):            PIPEBSTAT: 0x00000242 (status: VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00020e09 (n = 2, m1 = 14, m2 = 9)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x98046003 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 14, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x048f03ff (1024 active, 1168 total)
>(II) intel(0):             HBLANK_B: 0x048f03ff (1024 start, 1168 end)
>(II) intel(0):              HSYNC_B: 0x044f042f (1072 start, 1104 end)
>(II) intel(0):             VTOTAL_B: 0x03030257 (600 active, 772 total)
>(II) intel(0):             VBLANK_B: 0x03030257 (600 start, 772 end)
>(II) intel(0):              VSYNC_B: 0x025e025a (603 start, 607 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0xa2c4008e (disabled)
>(II) intel(0):               TV_CTL: 0x400c0000
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x0332012d
>(II) intel(0):            TV_CSC_Y2: 0x07d30104
>(II) intel(0):             TV_CSC_U: 0x0733052d
>(II) intel(0):            TV_CSC_U2: 0x05c70200
>(II) intel(0):             TV_CSC_V: 0x0340030c
>(II) intel(0):            TV_CSC_V2: 0x06d00200
>(II) intel(0):         TV_CLR_KNOBS: 0x00606000
>(II) intel(0):         TV_CLR_LEVEL: 0x010b00e1
>(II) intel(0):           TV_H_CTL_1: 0x00400359
>(II) intel(0):           TV_H_CTL_2: 0x80480022
>(II) intel(0):           TV_H_CTL_3: 0x007c0344
>(II) intel(0):           TV_V_CTL_1: 0x00f01415
>(II) intel(0):           TV_V_CTL_2: 0x00060607
>(II) intel(0):           TV_V_CTL_3: 0x80120001
>(II) intel(0):           TV_V_CTL_4: 0x000900f0
>(II) intel(0):           TV_V_CTL_5: 0x000a00f0
>(II) intel(0):           TV_V_CTL_6: 0x000900f0
>(II) intel(0):           TV_V_CTL_7: 0x000a00f0
>(II) intel(0):          TV_SC_CTL_1: 0xc1710088
>(II) intel(0):          TV_SC_CTL_2: 0x4e2d1dc8
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00360024
>(II) intel(0):          TV_WIN_SIZE: 0x02640198
>(II) intel(0):      TV_FILTER_CTL_1: 0x80000a75
>(II) intel(0):      TV_FILTER_CTL_2: 0x00017878
>(II) intel(0):      TV_FILTER_CTL_3: 0x0000bc3c
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0xb1403000
>(II) intel(0):         TV_H_LUMA_59: 0x0000b060
>(II) intel(0):        TV_H_CHROMA_0: 0xb1403000
>(II) intel(0):       TV_H_CHROMA_59: 0x0000b060
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): pipe B dot 54166 n 2 m1 14 m2 9 p1 3 p2 14
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"(II) Module "i2c" already built-in
>(II) intel(0): Output VGA using monitor section External VGA
>(**) intel(0): Option "PreferredMode" "1280x1024"
>(II) intel(0): Output LVDS has no monitor section
>(II) intel(0): I2C bus "LVDSDDC_C" initialized.
>(II) intel(0): Attempting to determine panel fixed mode.
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" removed.
>(II) intel(0): found backlight control method /sys/class/backlight/acpi_video0
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) intel(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) intel(0): SDVOB: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) intel(0): SDVOB: R: 02 42 02 01 01 3D 3E 00 (Success)
>(II) intel(0): Output TV-1 has no monitor section
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) intel(0): SDVOB: R: C4 09 74 40             (Success)
>(II) intel(0): SDVOB: device VID/DID: 02:42.02, clock range 25.0MHz - 165.0MHz
>(II) intel(0): SDVOB: 1 input channel
>(II) intel(0): SDVOB: RGB0 output reported
>(II) intel(0): SDVOB: CVBS0 output reported
>(II) intel(0): SDVOB: SVID0 output reported
>(II) intel(0): SDVOB: YPRPB0 output reported
>(II) intel(0): SDVOB: SCART0 output reported
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 16 20 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 04 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 08 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 10 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 20 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): EDID for output VGA
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" removed.
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Not using default mode "1024x768" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1024x768" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1024x768" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1024x768" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1152x864" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1280x960" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1280x960" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1280x1024" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1280x1024" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1280x1024" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1792x1344" (height too large for virtual size)
>(II) intel(0): Not using default mode "1792x1344" (height too large for virtual size)
>(II) intel(0): Not using default mode "1856x1392" (height too large for virtual size)
>(II) intel(0): Not using default mode "1856x1392" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "832x624" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1152x768" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1024" (exceeds panel dimensions)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1024x600"x59.9   54.00  1024 1072 1104 1168  600 603 607 772 (46.2 kHz)
>(II) intel(0): Modeline "800x600"x85.1   56.30  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz)
>(II) intel(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
>(II) intel(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
>(II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz)
>(II) intel(0): Modeline "640x480"x85.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz)
>(II) intel(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Modeline "720x400"x85.0   35.50  720 756 828 936  400 401 404 446 -hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x400"x85.1   31.50  640 672 736 832  400 401 404 445 -hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x350"x85.1   31.50  640 672 736 832  350 382 385 445 +hsync -vsync (37.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Pending)
>(II) intel(0): SDVOB: R: 00 00                   (Pending)
>(II) intel(0): SDVOB: R: 00 00                   (Pending)
>(II) intel(0): SDVOB: R: 00 00                   (Pending)
>(II) intel(0): SDVOB: R: 00 00                   (Pending)
>(II) intel(0): SDVOB: R: 02 00                   (Success)
>(II) intel(0): SDVOB: W: 28                         (SDVO_CMD_GET_TV_FORMAT)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00       (Success)
>(II) intel(0): SDVOB: W: 83                         (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT)
>(II) intel(0): SDVOB: R: FF FF 07                (Success)
>(II) intel(0): Not using mode "720x400@60.00" (mode clock too low)
>(II) intel(0): Not using mode "720x350@60.00" (mode clock too low)
>(II) intel(0): Not using mode "704x480@60.00" (mode clock too low)
>(II) intel(0): Not using mode "640x480@60.00" (mode clock too low)
>(II) intel(0): Not using mode "640x400@60.00" (mode clock too low)
>(II) intel(0): Not using mode "640x350@60.00" (mode clock too low)
>(II) intel(0): Not using mode "400x300@60.00" (mode clock too low)
>(II) intel(0): Not using mode "320x240@60.00" (mode clock too low)
>(II) intel(0): Not using mode "320x200@60.00" (mode clock too low)
>(II) intel(0): Not using default mode "640x350" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "720x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) intel(0): Not using default mode "1280x960" (hsync out of range)
>(II) intel(0): Not using default mode "1280x960" (vrefresh out of range)
>(II) intel(0): Not using default mode "1280x1024" (hsync out of range)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1792x1344" (height too large for virtual size)
>(II) intel(0): Not using default mode "1792x1344" (height too large for virtual size)
>(II) intel(0): Not using default mode "1856x1392" (height too large for virtual size)
>(II) intel(0): Not using default mode "1856x1392" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "832x624" (vrefresh out of range)
>(II) intel(0): Not using default mode "1152x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1024" (hsync out of range)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Printing probed modes for output TV-1
>(II) intel(0): Modeline "1280x1024@60.00"x60.0   87.27  1280 1281 1344 1376  1024 1025 1056 1057 (63.4 kHz)
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Modeline "1024x768@60.00"x60.0   53.83  1024 1025 1088 1120  768 769 800 801 (48.1 kHz)
>(II) intel(0): Modeline "920x766@60.00"x60.0   48.71  920 921 984 1016  766 767 798 799 (47.9 kHz)
>(II) intel(0): Modeline "832x624@60.00"x60.0   36.58  832 833 896 928  624 625 656 657 (39.4 kHz)
>(II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "800x600@60.00"x60.0   34.03  800 801 864 896  600 601 632 633 (38.0 kHz)
>(II) intel(0): Modeline "720x576@60.00"x60.0   29.82  720 721 784 816  576 577 608 609 (36.5 kHz)
>(II) intel(0): Modeline "704x576@60.00"x60.0   29.23  704 705 768 800  576 577 608 609 (36.5 kHz)
>(II) intel(0): Modeline "720x540@60.00"x60.0   28.05  720 721 784 816  540 541 572 573 (34.4 kHz)
>(II) intel(0): Modeline "720x480@60.00"x60.0   25.12  720 721 784 816  480 481 512 513 (30.8 kHz)
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Output VGA disconnected
>(II) intel(0): Output LVDS connected
>(II) intel(0): Output TV-1 connected
>(II) intel(0): Output LVDS using initial mode 1024x600
>(II) intel(0): Output TV-1 using initial mode 1024x768
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 00 00 00 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 04 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 00 00 00 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 08 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 00 00 00 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 10 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 00 00 00 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 20 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 00 00 00 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 00 00 00 00 16 20 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Monitoring connected displays enabled
>(II) intel(0): detected 256 kB GTT.
>(II) intel(0): detected 7932 kB stolen memory.
>(==) intel(0): video overlay key set to 0x101fe
>(==) intel(0): Intel XvMC decoder disabled
>(==) intel(0): Will not try to enable page flipping
>(==) intel(0): Triple buffering disabled
>(==) intel(0): Using gamma correction (1.0, 1.0, 1.0)
>(==) intel(0): DPI set to (96, 96)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /usr/lib/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(II) Loading sub module "exa"
>(II) LoadModule: "exa"
>(II) Loading /usr/lib/xorg/modules//libexa.so
>(II) Module exa: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 2.2.0
>	ABI class: X.Org Video Driver, version 2.0
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"(II) Module "ramdac" already built-in
>(II) intel(0): Comparing regs from server start up to After PreInit
>(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00000203 to 0x00000000
>(WW) intel(0): PIPEASTAT before: status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(WW) intel(0): PIPEASTAT after: status:
>(WW) intel(0): Register 0x71024 (PIPEBSTAT) changed from 0x00000242 to 0x00000202
>(WW) intel(0): PIPEBSTAT before: status: VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS
>(WW) intel(0): PIPEBSTAT after: status: VSYNC_INT_STATUS VBLANK_INT_STATUS
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] 0	0	0xf0300000 - 0xf033ffff (0x40000) MS[B]
>	[1] 0	0	0xe0000000 - 0xefffffff (0x10000000) MS[B]
>	[2] 0	0	0xf0200000 - 0xf027ffff (0x80000) MS[B]
>	[3] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[4] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[5] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[6] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[7] -1	0	0xf0100400 - 0xf01004ff (0x100) MX[B]
>	[8] -1	0	0xf0100000 - 0xf01000ff (0x100) MX[B]
>	[9] -1	0	0xf0000000 - 0xf000ffff (0x10000) MX[B]
>	[10] -1	0	0xf0544000 - 0xf05443ff (0x400) MX[B]
>	[11] -1	0	0xf0340000 - 0xf0343fff (0x4000) MX[B]
>	[12] -1	0	0xf0280000 - 0xf02fffff (0x80000) MX[B](B)
>	[13] -1	0	0xf0300000 - 0xf033ffff (0x40000) MX[B](B)
>	[14] -1	0	0xe0000000 - 0xefffffff (0x10000000) MX[B](B)
>	[15] -1	0	0xf0200000 - 0xf027ffff (0x80000) MX[B](B)
>	[16] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[17] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[18] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[19] 0	0	0x00001800 - 0x00001807 (0x8) IS[B]
>	[20] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[21] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[22] -1	0	0x0000f800 - 0x0000f8ff (0x100) IX[B]
>	[23] -1	0	0x000018a0 - 0x000018bf (0x20) IX[B]
>	[24] -1	0	0x00001810 - 0x0000181f (0x10) IX[B]
>	[25] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[26] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[27] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[28] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[29] -1	0	0x00001880 - 0x0000189f (0x20) IX[B]
>	[30] -1	0	0x00001860 - 0x0000187f (0x20) IX[B]
>	[31] -1	0	0x00001840 - 0x0000185f (0x20) IX[B]
>	[32] -1	0	0x00001820 - 0x0000183f (0x20) IX[B]
>	[33] -1	0	0x00001800 - 0x00001807 (0x8) IX[B](B)
>	[34] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[35] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) intel(0): Kernel reported 238592 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 954364 kB available
>(EE) intel(0): Cannot support DRI with frame buffer width > 2048.
>(**) intel(0): Framebuffer compression enabled
>(**) intel(0): Tiling enabled
>(==) intel(0): VideoRam: 262144 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(EE) intel(0): Front buffer stride 16 kB exceed display limit
>(II) intel(0): Tiled allocation failed.
>(WW) intel(0): Couldn't allocate tiled memory, fb compression disabled
>(II) intel(0): Attempting memory allocation with untiled buffers.
>(II) intel(0): Untiled allocation successful.
>(==) intel(0): Write-combining range (0xe0000000,0x10000000)
>(II) intel(0): adjusting plane->pipe mappings to allow for framebuffer compression
>(II) intel(0): Page Flipping disabled
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) EXA(0): Offscreen pixmap area of 28311552 bytes
>(II) EXA(0): Driver registered support for the following operations:
>(II)         Solid
>(II)         Copy
>(II)         Composite (RENDER acceleration)
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 16 20 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 04 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 08 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 10 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 20 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x007bf000 (pgoffset 1983)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x01580000 (pgoffset 5504)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x0001ffff: ring buffer (128 kB)
>(II) intel(0): 0x00020000-0x00029fff: HW cursors (40 kB, 0x000000003f820000 physical
>)
>(II) intel(0): 0x0002a000-0x00031fff: logical 3D context (32 kB)
>(II) intel(0): 0x00032000-0x00131fff: fake bufmgr (1024 kB)
>(II) intel(0): 0x00132000-0x00132fff: overlay registers (4 kB, 0x000000003f932000 physical
>)
>(II) intel(0): 0x00140000-0x0157ffff: front buffer (20736 kB)
>(II) intel(0): 0x007bf000:            end of stolen memory
>(II) intel(0): 0x01580000-0x0307ffff: exa offscreen (27648 kB)
>(II) intel(0): 0x10000000:            end of aperture
>(WW) intel(0): ESR is 0x00000001, instruction error
>(WW) intel(0): Existing errors found in hardware state.
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>output modeline:
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): SDVOB: W: 11 08 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 64 19 00 40 41 00 26 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 18 88 36 00 18 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1A 64 19 00 04 00 03       (SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1B                         (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1)
>(II) intel(0): SDVOB: R: 64 19 00 40 41 00 26 30 (Success)
>(II) intel(0): SDVOB: W: 1C                         (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2)
>(II) intel(0): SDVOB: R: 18 88 36 00 18 00 00 00 (Success)
>input modeline:
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 (48.4 kHz)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 (48.4 kHz)
>(II) intel(0): chosen: dotclock 64800 vco 2592000 ((m 81, m1 12, m2 9), n 1, (p 40, p1 4, p2 10))
>(II) intel(0): SDVOB: W: 07 08 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 64 19 00 40 41 00 26 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 18 88 36 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 02                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 08 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): using SSC reference clock of 100 MHz
>(II) intel(0): Mode for pipe B:
>(II) intel(0): Modeline "1024x600"x59.9   54.00  1024 1072 1104 1168  600 603 607 772 (46.2 kHz)
>(II) intel(0): chosen: dotclock 54081 vco 1514285 ((m 106, m1 17, m2 9), n 5, (p 28, p1 2, p2 14))
>(II) intel(0): Selecting standard 18 bit TMDS pixel format.
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x11987418 (none, ch2 enh enabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0400 (0x0400)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x01080000 (0x0000)
>(II) intel(0):               C1DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB3: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA01: 0x04020108 (0x0108)
>(II) intel(0):              C0DRA23: 0x00000402 (0x0402)
>(II) intel(0):              C1DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x8048008c (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00002f2f
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0xc0130300 (enabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x8048008c (enabled, pipe A, no stall, +hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) intel(0):            PP_STATUS: 0xd000000a (on, ready, sequencing on)
>(II) intel(0):         PP_ON_DELAYS: 0x00640bb8
>(II) intel(0):        PP_OFF_DELAYS: 0x00641388
>(II) intel(0):           PP_DIVISOR: 0x00270f07
>(II) intel(0):         PFIT_CONTROL: 0x00000008
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000400
>(II) intel(0):             DSPACNTR: 0xd9000000 (enabled, pipe B)
>(II) intel(0):           DSPASTRIDE: 0x00002400 (9216 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x025703ff (1024, 600)
>(II) intel(0):             DSPABASE: 0x00140000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II) intel(0):            PIPEASTAT: 0x00000203 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):                 FPA0: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4084000 (enabled, dvo, TV B/C clock, DAC/serial mode, p1 = 4, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>(II) intel(0):             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>(II) intel(0):              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>(II) intel(0):             VTOTAL_A: 0x032502ff (768 active, 806 total)
>(II) intel(0):             VBLANK_A: 0x032502ff (768 start, 806 end)
>(II) intel(0):              VSYNC_A: 0x03080302 (771 start, 777 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0xd8000000 (enabled, pipe A)
>(II) intel(0):           DSPBSTRIDE: 0x00002400 (9216 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x02ff03ff (1024, 768)
>(II) intel(0):             DSPBBASE: 0x00140000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x03ff0257 (1024, 600)
>(II) intel(0):            PIPEBSTAT: 0x00000242 (status: VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00051109 (n = 5, m1 = 17, m2 = 9)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x048f03ff (1024 active, 1168 total)
>(II) intel(0):             HBLANK_B: 0x048f03ff (1024 start, 1168 end)
>(II) intel(0):              HSYNC_B: 0x044f042f (1072 start, 1104 end)
>(II) intel(0):             VTOTAL_B: 0x03030257 (600 active, 772 total)
>(II) intel(0):             VBLANK_B: 0x03030257 (600 start, 772 end)
>(II) intel(0):              VSYNC_B: 0x025e025a (603 start, 607 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x80000000 (disabled)
>(II) intel(0):               TV_CTL: 0x400c0000
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x0332012d
>(II) intel(0):            TV_CSC_Y2: 0x07d30104
>(II) intel(0):             TV_CSC_U: 0x0733052d
>(II) intel(0):            TV_CSC_U2: 0x05c70200
>(II) intel(0):             TV_CSC_V: 0x0340030c
>(II) intel(0):            TV_CSC_V2: 0x06d00200
>(II) intel(0):         TV_CLR_KNOBS: 0x00606000
>(II) intel(0):         TV_CLR_LEVEL: 0x010b00e1
>(II) intel(0):           TV_H_CTL_1: 0x00400359
>(II) intel(0):           TV_H_CTL_2: 0x80480022
>(II) intel(0):           TV_H_CTL_3: 0x007c0344
>(II) intel(0):           TV_V_CTL_1: 0x00f01415
>(II) intel(0):           TV_V_CTL_2: 0x00060607
>(II) intel(0):           TV_V_CTL_3: 0x80120001
>(II) intel(0):           TV_V_CTL_4: 0x000900f0
>(II) intel(0):           TV_V_CTL_5: 0x000a00f0
>(II) intel(0):           TV_V_CTL_6: 0x000900f0
>(II) intel(0):           TV_V_CTL_7: 0x000a00f0
>(II) intel(0):          TV_SC_CTL_1: 0xc1710088
>(II) intel(0):          TV_SC_CTL_2: 0x4e2d1dc8
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00360024
>(II) intel(0):          TV_WIN_SIZE: 0x02640198
>(II) intel(0):      TV_FILTER_CTL_1: 0x80000a75
>(II) intel(0):      TV_FILTER_CTL_2: 0x00017878
>(II) intel(0):      TV_FILTER_CTL_3: 0x0000bc3c
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0xb1403000
>(II) intel(0):         TV_H_LUMA_59: 0x0000b060
>(II) intel(0):        TV_H_CHROMA_0: 0xb1403000
>(II) intel(0):       TV_H_CHROMA_59: 0x0000b060
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(WW) intel(0): ref out of range
>(II) intel(0): pipe A dot 0 n 1 m1 12 m2 9 p1 4 p2 10
>(II) intel(0): pipe B dot 54081 n 5 m1 17 m2 9 p1 2 p2 14
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane B is now enabled and connected to pipe A.
>(II) intel(0):   Pipe B is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe B.
>(II) intel(0):   Output VGA is connected to pipe none
>(II) intel(0):   Output LVDS is connected to pipe B
>(II) intel(0):   Output TV-1 is connected to pipe A
>(II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>(II) intel(0): Set up overlay video
>(II) intel(0): direct rendering: Disabled
>(WW) intel(0): Option "monitor-TV" is not used
>(WW) intel(0): Option "PreferredMode" is not used
>(--) RandR disabled
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-APPGROUP
>(II) Initializing built-in extension XAccessControlExtension
>(II) Initializing built-in extension SECURITY
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension XFree86-Bigfont
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) Initializing built-in extension XEVIE
>(II) AIGLX: Screen 0 is not DRI capable
>(II) Loading sub module "GLcore"
>(II) LoadModule: "GLcore"
>(II) Loading /usr/lib/xorg/modules/extensions//libGLcore.so
>(II) Module GLcore: vendor="X.Org Foundation"
>	compiled for 1.4.2, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(II) GLX: Initialized MESA-PROXY GL provider for screen 0
>(II) intel(0): Setting screen physical size to 270 x 203
>(**) Option "CoreKeyboard"
>(**) Keyboard: always reports core events
>(**) Option "Protocol" "standard"
>(**) Keyboard: Protocol: standard
>(**) Option "AutoRepeat" "500 30"
>(**) Option "XkbRules" "xorg"
>(**) Keyboard: XkbRules: "xorg"
>(**) Option "XkbModel" "pc105"
>(**) Keyboard: XkbModel: "pc105"
>(**) Option "XkbLayout" "u810"
>(**) Keyboard: XkbLayout: "u810"
>(**) Option "XkbOptions" "compose:rwin"
>(**) Keyboard: XkbOptions: "compose:rwin"
>(**) Option "CustomKeycodes" "off"
>(**) Keyboard: CustomKeycodes disabled
>(**) Option "longtouched_button" "3"
>(**) Option "maybetapped_button" "1"
>(**) Option "oneandahalftap_button" "0"
>(**) Option "touched_drag" "1"
>State: S_UNTOUCHED	Action: No Action		Button: 0
>State: S_TOUCHED	Action: No Action		Button: 0
>State: S_LONGTOUCHED	Action: down		Button: 3
>State: S_MOVING	Action: No Action		Button: 0
>State: S_MAYBETAPPED	Action: click		Button: 1
>State: S_ONEANDAHALFTAP	Action: down		Button: 0
>(**) Option "MinX" "13000"
>(**) Option "MaxX" "382000"
>(**) Option "MinY" "25000"
>(**) Option "MaxY" "392000"
>(**) Option "Emulate3Buttons"
>(**) Option "Emulate3Timeout" "50"
>(**) Option "TapTimer" "90"
>(**) Option "LongtouchTimer" "500"
>(**) Option "MoveLimit" "18"
>(**) Option "DeviceName" "touchscreen"
>(**) Option "SendCoreEvents"
>(**) touchscreen: always reports core events
>(**) Option "Protocol" "ExplorerPS/2"
>(**) Mouse1: Device: "/dev/mouse"
>(**) Mouse1: Protocol: "ExplorerPS/2"
>(**) Option "CorePointer"
>(**) Mouse1: always reports core events
>(**) Option "Device" "/dev/mouse"
>(==) Mouse1: Emulate3Buttons, Emulate3Timeout: 50
>(**) Mouse1: ZAxisMapping: buttons 4 and 5
>(**) Mouse1: Buttons: 9
>(**) Mouse1: Sensitivity: 1
>(II) evaluating device (Mouse1)
>(II) XINPUT: Adding extended input device "Mouse1" (type: MOUSE)
>(II) evaluating device (touchscreen)
>(II) XINPUT: Adding extended input device "touchscreen" (type: TOUCHSCREEN)
>(II) evaluating device (Keyboard)
>(II) XINPUT: Adding extended input device "Keyboard" (type: KEYBOARD)
>(II) Mouse1: ps2EnableDataReporting: succeeded
>(**) Option "Device" "/dev/input/by-id/usb-Fujitsu_Component_USB_Touch_Panel-event-mouse"
>(EE) xf86OpenSerial: Cannot open device /dev/input/by-id/usb-Fujitsu_Component_USB_Touch_Panel-event-mouse
>	No such file or directory.
>(WW) touchscreen: cannot open input device
>couldn't enable device 3
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 08 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 08 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)

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Attachments on bug 17823: 19278 | 20588 | 20590 | 20826 | 21135 | 21225 | 21722 | 21820 | 23100 | 23323 | 23365 | 23429 | 23433 | 23467 | 23468

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