Attachment 23340 Details for Bug 20339 – Xorg log using default config with "ModeDebug yes" added

Xorg log using default config with "ModeDebug yes" added

Xorg.0.log (text/plain), 24.84 KB, created by Brian De Wolf on 2009-02-26 15:07:43 UTC

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Creator: Brian De Wolf

Created: 2009-02-26 15:07:43 UTC

Size: 24.84 KB

patch

obsolete

>_XSERVTransSocketOpenCOTSServer: Unable to open socket for inet6
>_XSERVTransOpen: transport open failed for inet6/meow:0
>_XSERVTransMakeAllCOTSServerListeners: failed to open listener for inet6
>
>X.Org X Server 1.6.0
>Release Date: 2009-2-25
>X Protocol Version 11, Revision 0
>Build Operating System: Linux 2.6.28-gentoo-r2 i686 
>Current Operating System: Linux meow 2.6.29-rc6 #1 PREEMPT Thu Feb 26 14:58:28 PST 2009 i686
>Build Date: 26 February 2009  10:47:33AM
> 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Thu Feb 26 15:04:31 2009
>(++) Using config file: "/root/xorg.conf.new"
>(==) ServerLayout "X.org Configured"
>(**) |-->Screen "Screen0" (0)
>(**) |   |-->Monitor "Monitor0"
>(**) |   |-->Device "Card0"
>(**) |-->Input Device "Mouse0"
>(**) |-->Input Device "Keyboard0"
>(==) Automatically adding devices
>(==) Automatically enabling devices
>(**) FontPath set to:
>	built-ins,
>	built-ins
>(**) ModulePath set to "/usr/lib/xorg/modules"
>(WW) AllowEmptyInput is on, devices using drivers 'kbd', 'mouse' or 'vmmouse' will be disabled.
>(WW) Disabling Mouse0
>(WW) Disabling Keyboard0
>(II) Loader magic: 0x1aa0
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.4
>	X.Org Video Driver: 5.0
>	X.Org XInput driver : 4.0
>	X.Org Server Extension : 2.0
>(II) Loader running on linux
>(--) using VT number 8
>
>(--) PCI:*(0@0:2:0) Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller rev 3, Mem @ 0xdff00000/524288, 0xc0000000/268435456, 0xdfec0000/262144, I/O @ 0x0000ec38/8
>(--) PCI: (0@0:2:1) Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller rev 3, Mem @ 0xdff80000/524288
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) System resource ranges:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) "extmod" will be loaded. This was enabled by default and also specified in the config file.
>(II) "dbe" will be loaded. This was enabled by default and also specified in the config file.
>(II) "glx" will be loaded. This was enabled by default and also specified in the config file.
>(II) "record" will be loaded. This was enabled by default and also specified in the config file.
>(II) "dri" will be loaded. This was enabled by default and also specified in the config file.
>(II) "dri2" will be loaded. This was enabled by default and also specified in the config file.
>(II) LoadModule: "glx"
>(II) Loading /usr/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.6.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.6.0, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "record"
>(II) Loading /usr/lib/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 1.6.0, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension RECORD
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.6.0, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "dri"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.6.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "dri2"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri2.so
>(II) Module dri2: vendor="X.Org Foundation"
>	compiled for 1.6.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DRI2
>(II) LoadModule: "intel"
>(II) Loading /usr/lib/xorg/modules/drivers//intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.6.0, module version = 2.6.99
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, 965G, G35, 965Q, 946GZ,
>	965GM, 965GME/GLE, G33, Q35, Q33,
>	Mobile IntelÂ® GM45 Express Chipset,
>	Intel Integrated Graphics Device, G45/G43, Q45/Q43, G41
>(II) Primary Device is: PCI 00@00:02:0
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) resource ranges after probing:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.6.0, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 5.0
>(==) intel(0): Depth 24, (--) framebuffer bpp 32
>(==) intel(0): RGB weight 888
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "ModeDebug" "yes"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) 915GM
>(--) intel(0): Chipset: "915GM"
>(--) intel(0): Linear framebuffer at 0xC0000000
>(--) intel(0): IO registers at addr 0xDFF00000
>(WW) intel(0): libpciaccess reported 0 rom size, guessing 64kB
>(==) intel(0): Using EXA for acceleration
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x11987820 (XOR bank/rank, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0202 (0x0202)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x08000000 (0x0000)
>(II) intel(0):               C1DRB0: 0x05040302 (0x0302)
>(II) intel(0):               C1DRB1: 0x07060504 (0x0504)
>(II) intel(0):               C1DRB2: 0x09080706 (0x0706)
>(II) intel(0):               C1DRB3: 0x0b0a0908 (0x0908)
>(II) intel(0):              C0DRA01: 0x00010800 (0x0800)
>(II) intel(0):              C0DRA23: 0x04020001 (0x0001)
>(II) intel(0):              C1DRA01: 0x0d0c0b0a (0x0b0a)
>(II) intel(0):              C1DRA23: 0x0f0e0d0c (0x0d0c)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00800080 (vga0 p1 = 2, p2 = 4, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00480004 (disabled, pipe A, stall disabled, detected, SDVO mult 1)
>(II) intel(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) intel(0):              SDVOUDI: 0x000000ef
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0xc030033c (enabled, pipe B, 18 bit, 2 channels)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00480004 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) intel(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x012c0fa0
>(II) intel(0):        PP_OFF_DELAYS: 0x01c20fa0
>(II) intel(0):           PP_DIVISOR: 0x00270f09
>(II) intel(0):         PFIT_CONTROL: 0x80002668
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x00000000 (status:)
>(II) intel(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x49000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000280 (640 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x018f02cf (720, 400)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f018f (640, 400)
>(II) intel(0):            PIPEBSTAT: 0x80000202 (status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x99046000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 7)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x06970577 (1400 active, 1688 total)
>(II) intel(0):             HBLANK_B: 0x06970577 (1400 start, 1688 end)
>(II) intel(0):              HSYNC_B: 0x061305a3 (1444 start, 1556 end)
>(II) intel(0):             VTOTAL_B: 0x04290419 (1050 active, 1066 total)
>(II) intel(0):             VBLANK_B: 0x04290419 (1050 start, 1066 end)
>(II) intel(0):              VSYNC_B: 0x041c0419 (1050 start, 1053 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00800080
>(II) intel(0):             VGACNTRL: 0x22c4008e (enabled)
>(II) intel(0):               TV_CTL: 0x400c0c00
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x0332012d
>(II) intel(0):            TV_CSC_Y2: 0x07d30104
>(II) intel(0):             TV_CSC_U: 0x0733052d
>(II) intel(0):            TV_CSC_U2: 0x05c70200
>(II) intel(0):             TV_CSC_V: 0x0340030c
>(II) intel(0):            TV_CSC_V2: 0x06d00200
>(II) intel(0):         TV_CLR_KNOBS: 0x00606000
>(II) intel(0):         TV_CLR_LEVEL: 0x010b00e1
>(II) intel(0):           TV_H_CTL_1: 0x00400359
>(II) intel(0):           TV_H_CTL_2: 0x80480022
>(II) intel(0):           TV_H_CTL_3: 0x007c0344
>(II) intel(0):           TV_V_CTL_1: 0x00f01415
>(II) intel(0):           TV_V_CTL_2: 0x00060607
>(II) intel(0):           TV_V_CTL_3: 0x80120001
>(II) intel(0):           TV_V_CTL_4: 0x000900f0
>(II) intel(0):           TV_V_CTL_5: 0x000a00f0
>(II) intel(0):           TV_V_CTL_6: 0x000900f0
>(II) intel(0):           TV_V_CTL_7: 0x000a00f0
>(II) intel(0):          TV_SC_CTL_1: 0xc1710087
>(II) intel(0):          TV_SC_CTL_2: 0x6b405140
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00360024
>(II) intel(0):          TV_WIN_SIZE: 0x02640198
>(II) intel(0):      TV_FILTER_CTL_1: 0x800010bb
>(II) intel(0):      TV_FILTER_CTL_2: 0x00028283
>(II) intel(0):      TV_FILTER_CTL_3: 0x00014141
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0xb1403000
>(II) intel(0):         TV_H_LUMA_59: 0x0000b060
>(II) intel(0):        TV_H_CHROMA_0: 0xb1403000
>(II) intel(0):       TV_H_CHROMA_59: 0x0000b060
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 0: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 1: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 1: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 2: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 2: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 3: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 3: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 4: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 4: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 5: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 5: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 6: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 6: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 7: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 7: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 8: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 8: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 9: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 9: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 10: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 10: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 11: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 11: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 12: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 12: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 13: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 13: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 14: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 14: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 15: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 15: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): pipe B dot 112380 n 3 m1 20 m2 6 p1 3 p2 7
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Module "i2c" already built-in
>(II) intel(0): Output VGA using monitor section Monitor0
>(II) intel(0): Skipping LVDS from driver feature BDB's LVDS config info.
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) intel(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) intel(0): SDVOB: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) intel(0): SDVOB: R: 04 AA 02 00 01 01 01 00 (Success)
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 00 00                   (Not supported)
>(II) intel(0): Output TMDS-1 has no monitor section
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) intel(0): SDVOB: R: C4 09 74 40             (Success)
>(II) intel(0): SDVOB: device VID/DID: 04:AA.02, clock range 25.0MHz - 165.0MHz
>(II) intel(0): SDVOB: 1 input channel
>(II) intel(0): SDVOB: TMDS0 output reported
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" registered at address 0x72.
>(II) intel(0): No SDVO device found on SDVOC
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" removed.
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" removed.
>(II) intel(0): Output TV has no monitor section
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Not supported)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Not supported)
>(II) intel(0): Resizable framebuffer: not available (1 3)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): chosen: dotclock 31500 vco 2520000 ((m 105, m1 17, m2 8), n 2, (p 80, p1 8, p2 10))
>(II) intel(0): I2C bus "CRTDDC_A" initialized.
>(II) intel(0): I2C bus "CRTDDC_A" removed.
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output VGA
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(II) intel(0): Output VGA disconnected
>(II) intel(0): Output TMDS-1 disconnected
>(II) intel(0): Output TV disconnected
>(WW) intel(0): No outputs definitely connected, trying again...
>(II) intel(0): Output VGA disconnected
>(II) intel(0): Output TMDS-1 disconnected
>(II) intel(0): Output TV disconnected
>(WW) intel(0): Unable to find initial modes
>(EE) intel(0): No valid modes.
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) UnloadModule: "intel"
>(II) UnloadModule: "vgahw"
>(II) Unloading /usr/lib/xorg/modules//libvgahw.so
>(EE) Screen(s) found, but none have a usable configuration.
>
>Fatal server error:
>no screens found
>
>Please consult the The X.Org Foundation support 
>	 at http://wiki.x.org
> for help. 
>Please also check the log file at "/var/log/Xorg.0.log" for additional information.
>

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Attachments on bug 20339: 23340 | 23341 | 23342 | 23343 | 24095

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